1 /* 2 * Copyright (c) 2023, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <platform_def.h> 8 #include <sgi_ras.h> 9 #include <sgi_sdei.h> 10 11 struct sgi_ras_ev_map plat_ras_map[] = { 12 /* Non Secure base RAM ECC CE interrupt */ 13 {SGI_SDEI_DS_EVENT_0, NS_RAM_ECC_CE_INT, SGI_RAS_INTR_TYPE_SPI}, 14 15 /* Non Secure base RAM ECC UE interrupt */ 16 {SGI_SDEI_DS_EVENT_0, NS_RAM_ECC_UE_INT, SGI_RAS_INTR_TYPE_SPI}, 17 18 /* CPU 1-bit ECC CE error interrupt */ 19 {SGI_SDEI_DS_EVENT_1, PLAT_CORE_FAULT_IRQ, SGI_RAS_INTR_TYPE_PPI} 20 }; 21 22 /* RAS error record list definition, used by the common RAS framework. */ 23 struct err_record_info plat_err_records[] = { 24 /* Base element RAM Non-secure error record. */ 25 ERR_RECORD_MEMMAP_V1(SOC_NS_RAM_ERR_REC_BASE, 4, NULL, 26 &sgi_ras_sram_intr_handler, 0), 27 ERR_RECORD_SYSREG_V1(0, 1, NULL, &sgi_ras_cpu_intr_handler, 0), 28 }; 29 30 /* RAS error interrupt list definition, used by the common RAS framework. */ 31 struct ras_interrupt plat_ras_interrupts[] = { 32 { 33 .intr_number = PLAT_CORE_FAULT_IRQ, 34 .err_record = &plat_err_records[1], 35 }, { 36 .intr_number = NS_RAM_ECC_CE_INT, 37 .err_record = &plat_err_records[0], 38 }, { 39 .intr_number = NS_RAM_ECC_UE_INT, 40 .err_record = &plat_err_records[0], 41 }, 42 }; 43 44 /* Registers the RAS error record list with common RAS framework. */ 45 REGISTER_ERR_RECORD_INFO(plat_err_records); 46 /* Registers the RAS error interrupt info list with common RAS framework. */ 47 REGISTER_RAS_INTERRUPTS(plat_ras_interrupts); 48 49 /* Platform RAS handling config data definition */ 50 struct plat_sgi_ras_config ras_config = { 51 plat_ras_map, 52 ARRAY_SIZE(plat_ras_map) 53 }; 54
