1 /*
2 * Copyright (c) 2013-2022, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8 #include <inttypes.h>
9 #include <stdint.h>
10
11 #include <arch_features.h>
12 #include <arch_helpers.h>
13 #include <bl32/tsp/tsp.h>
14 #include <common/bl_common.h>
15 #include <common/debug.h>
16 #include <lib/spinlock.h>
17 #include <plat/common/platform.h>
18 #include <platform_tsp.h>
19 #include "tsp_private.h"
20
21 #include <platform_def.h>
22
23 /*******************************************************************************
24 * TSP main entry point where it gets the opportunity to initialize its secure
25 * state/applications. Once the state is initialized, it must return to the
26 * SPD with a pointer to the 'tsp_vector_table' jump table.
27 ******************************************************************************/
tsp_main(void)28 uint64_t tsp_main(void)
29 {
30 NOTICE("TSP: %s\n", version_string);
31 NOTICE("TSP: %s\n", build_message);
32 INFO("TSP: Total memory base : 0x%lx\n", (unsigned long) BL32_BASE);
33 INFO("TSP: Total memory size : 0x%lx bytes\n", BL32_TOTAL_SIZE);
34
35 uint32_t linear_id = plat_my_core_pos();
36
37 /* Initialize the platform */
38 tsp_platform_setup();
39
40 /* Initialize secure/applications state here */
41 tsp_generic_timer_start();
42
43 /* Update this cpu's statistics */
44 tsp_stats[linear_id].smc_count++;
45 tsp_stats[linear_id].eret_count++;
46 tsp_stats[linear_id].cpu_on_count++;
47
48 INFO("TSP: cpu 0x%lx: %d smcs, %d erets %d cpu on requests\n",
49 read_mpidr(),
50 tsp_stats[linear_id].smc_count,
51 tsp_stats[linear_id].eret_count,
52 tsp_stats[linear_id].cpu_on_count);
53
54 console_flush();
55 return (uint64_t) &tsp_vector_table;
56 }
57
58 /*******************************************************************************
59 * This function performs any remaining book keeping in the test secure payload
60 * after this cpu's architectural state has been setup in response to an earlier
61 * psci cpu_on request.
62 ******************************************************************************/
tsp_cpu_on_main(void)63 smc_args_t *tsp_cpu_on_main(void)
64 {
65 uint32_t linear_id = plat_my_core_pos();
66
67 /* Initialize secure/applications state here */
68 tsp_generic_timer_start();
69
70 /* Update this cpu's statistics */
71 tsp_stats[linear_id].smc_count++;
72 tsp_stats[linear_id].eret_count++;
73 tsp_stats[linear_id].cpu_on_count++;
74
75 INFO("TSP: cpu 0x%lx turned on\n", read_mpidr());
76 INFO("TSP: cpu 0x%lx: %d smcs, %d erets %d cpu on requests\n",
77 read_mpidr(),
78 tsp_stats[linear_id].smc_count,
79 tsp_stats[linear_id].eret_count,
80 tsp_stats[linear_id].cpu_on_count);
81 /* Indicate to the SPD that we have completed turned ourselves on */
82 return set_smc_args(TSP_ON_DONE, 0, 0, 0, 0, 0, 0, 0);
83 }
84
85 /*******************************************************************************
86 * This function performs any remaining book keeping in the test secure payload
87 * before this cpu is turned off in response to a psci cpu_off request.
88 ******************************************************************************/
tsp_cpu_off_main(uint64_t arg0,uint64_t arg1,uint64_t arg2,uint64_t arg3,uint64_t arg4,uint64_t arg5,uint64_t arg6,uint64_t arg7)89 smc_args_t *tsp_cpu_off_main(uint64_t arg0,
90 uint64_t arg1,
91 uint64_t arg2,
92 uint64_t arg3,
93 uint64_t arg4,
94 uint64_t arg5,
95 uint64_t arg6,
96 uint64_t arg7)
97 {
98 uint32_t linear_id = plat_my_core_pos();
99
100 /*
101 * This cpu is being turned off, so disable the timer to prevent the
102 * secure timer interrupt from interfering with power down. A pending
103 * interrupt will be lost but we do not care as we are turning off.
104 */
105 tsp_generic_timer_stop();
106
107 /* Update this cpu's statistics */
108 tsp_stats[linear_id].smc_count++;
109 tsp_stats[linear_id].eret_count++;
110 tsp_stats[linear_id].cpu_off_count++;
111
112 INFO("TSP: cpu 0x%lx off request\n", read_mpidr());
113 INFO("TSP: cpu 0x%lx: %d smcs, %d erets %d cpu off requests\n",
114 read_mpidr(),
115 tsp_stats[linear_id].smc_count,
116 tsp_stats[linear_id].eret_count,
117 tsp_stats[linear_id].cpu_off_count);
118
119 /* Indicate to the SPD that we have completed this request */
120 return set_smc_args(TSP_OFF_DONE, 0, 0, 0, 0, 0, 0, 0);
121 }
122
123 /*******************************************************************************
124 * This function performs any book keeping in the test secure payload before
125 * this cpu's architectural state is saved in response to an earlier psci
126 * cpu_suspend request.
127 ******************************************************************************/
tsp_cpu_suspend_main(uint64_t arg0,uint64_t arg1,uint64_t arg2,uint64_t arg3,uint64_t arg4,uint64_t arg5,uint64_t arg6,uint64_t arg7)128 smc_args_t *tsp_cpu_suspend_main(uint64_t arg0,
129 uint64_t arg1,
130 uint64_t arg2,
131 uint64_t arg3,
132 uint64_t arg4,
133 uint64_t arg5,
134 uint64_t arg6,
135 uint64_t arg7)
136 {
137 uint32_t linear_id = plat_my_core_pos();
138
139 /*
140 * Save the time context and disable it to prevent the secure timer
141 * interrupt from interfering with wakeup from the suspend state.
142 */
143 tsp_generic_timer_save();
144 tsp_generic_timer_stop();
145
146 /* Update this cpu's statistics */
147 tsp_stats[linear_id].smc_count++;
148 tsp_stats[linear_id].eret_count++;
149 tsp_stats[linear_id].cpu_suspend_count++;
150
151 INFO("TSP: cpu 0x%lx: %d smcs, %d erets %d cpu suspend requests\n",
152 read_mpidr(),
153 tsp_stats[linear_id].smc_count,
154 tsp_stats[linear_id].eret_count,
155 tsp_stats[linear_id].cpu_suspend_count);
156
157 /* Indicate to the SPD that we have completed this request */
158 return set_smc_args(TSP_SUSPEND_DONE, 0, 0, 0, 0, 0, 0, 0);
159 }
160
161 /*******************************************************************************
162 * This function performs any book keeping in the test secure payload after this
163 * cpu's architectural state has been restored after wakeup from an earlier psci
164 * cpu_suspend request.
165 ******************************************************************************/
tsp_cpu_resume_main(uint64_t max_off_pwrlvl,uint64_t arg1,uint64_t arg2,uint64_t arg3,uint64_t arg4,uint64_t arg5,uint64_t arg6,uint64_t arg7)166 smc_args_t *tsp_cpu_resume_main(uint64_t max_off_pwrlvl,
167 uint64_t arg1,
168 uint64_t arg2,
169 uint64_t arg3,
170 uint64_t arg4,
171 uint64_t arg5,
172 uint64_t arg6,
173 uint64_t arg7)
174 {
175 uint32_t linear_id = plat_my_core_pos();
176
177 /* Restore the generic timer context */
178 tsp_generic_timer_restore();
179
180 /* Update this cpu's statistics */
181 tsp_stats[linear_id].smc_count++;
182 tsp_stats[linear_id].eret_count++;
183 tsp_stats[linear_id].cpu_resume_count++;
184
185 INFO("TSP: cpu 0x%lx resumed. maximum off power level %" PRId64 "\n",
186 read_mpidr(), max_off_pwrlvl);
187 INFO("TSP: cpu 0x%lx: %d smcs, %d erets %d cpu resume requests\n",
188 read_mpidr(),
189 tsp_stats[linear_id].smc_count,
190 tsp_stats[linear_id].eret_count,
191 tsp_stats[linear_id].cpu_resume_count);
192 /* Indicate to the SPD that we have completed this request */
193 return set_smc_args(TSP_RESUME_DONE, 0, 0, 0, 0, 0, 0, 0);
194 }
195
196 /*******************************************************************************
197 * TSP fast smc handler. The secure monitor jumps to this function by
198 * doing the ERET after populating X0-X7 registers. The arguments are received
199 * in the function arguments in order. Once the service is rendered, this
200 * function returns to Secure Monitor by raising SMC.
201 ******************************************************************************/
tsp_smc_handler(uint64_t func,uint64_t arg1,uint64_t arg2,uint64_t arg3,uint64_t arg4,uint64_t arg5,uint64_t arg6,uint64_t arg7)202 smc_args_t *tsp_smc_handler(uint64_t func,
203 uint64_t arg1,
204 uint64_t arg2,
205 uint64_t arg3,
206 uint64_t arg4,
207 uint64_t arg5,
208 uint64_t arg6,
209 uint64_t arg7)
210 {
211 uint128_t service_args;
212 uint64_t service_arg0;
213 uint64_t service_arg1;
214 uint64_t results[2];
215 uint32_t linear_id = plat_my_core_pos();
216 u_register_t dit;
217
218 /* Update this cpu's statistics */
219 tsp_stats[linear_id].smc_count++;
220 tsp_stats[linear_id].eret_count++;
221
222 INFO("TSP: cpu 0x%lx received %s smc 0x%" PRIx64 "\n", read_mpidr(),
223 ((func >> 31) & 1) == 1 ? "fast" : "yielding",
224 func);
225 INFO("TSP: cpu 0x%lx: %d smcs, %d erets\n", read_mpidr(),
226 tsp_stats[linear_id].smc_count,
227 tsp_stats[linear_id].eret_count);
228
229 /* Render secure services and obtain results here */
230 results[0] = arg1;
231 results[1] = arg2;
232
233 /*
234 * Request a service back from dispatcher/secure monitor.
235 * This call returns and thereafter resumes execution.
236 */
237 service_args = tsp_get_magic();
238 service_arg0 = (uint64_t)service_args;
239 service_arg1 = (uint64_t)(service_args >> 64U);
240
241 #if CTX_INCLUDE_MTE_REGS
242 /*
243 * Write a dummy value to an MTE register, to simulate usage in the
244 * secure world
245 */
246 write_gcr_el1(0x99);
247 #endif
248
249 /* Determine the function to perform based on the function ID */
250 switch (TSP_BARE_FID(func)) {
251 case TSP_ADD:
252 results[0] += service_arg0;
253 results[1] += service_arg1;
254 break;
255 case TSP_SUB:
256 results[0] -= service_arg0;
257 results[1] -= service_arg1;
258 break;
259 case TSP_MUL:
260 results[0] *= service_arg0;
261 results[1] *= service_arg1;
262 break;
263 case TSP_DIV:
264 results[0] /= service_arg0 ? service_arg0 : 1;
265 results[1] /= service_arg1 ? service_arg1 : 1;
266 break;
267 case TSP_CHECK_DIT:
268 if (!is_feat_dit_supported()) {
269 ERROR("DIT not supported\n");
270 results[0] = 0;
271 results[1] = 0xffff;
272 break;
273 }
274 dit = read_dit();
275 results[0] = dit == service_arg0;
276 results[1] = dit;
277 /* Toggle the dit bit */
278 write_dit(service_arg0 != 0U ? 0 : DIT_BIT);
279 break;
280 default:
281 break;
282 }
283
284 return set_smc_args(func, 0,
285 results[0],
286 results[1],
287 0, 0, 0, 0);
288 }
289
