1 /*
2 * Copyright (c) 2015-2023, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <assert.h>
8 #include <errno.h>
9
10 #include <arch_helpers.h>
11 #include <common/debug.h>
12 #include <drivers/clk.h>
13 #include <drivers/delay_timer.h>
14 #include <drivers/st/stm32_console.h>
15 #include <drivers/st/stm32mp_clkfunc.h>
16 #include <drivers/st/stm32mp_reset.h>
17 #include <lib/mmio.h>
18 #include <lib/smccc.h>
19 #include <lib/xlat_tables/xlat_tables_v2.h>
20 #include <plat/common/platform.h>
21 #include <services/arm_arch_svc.h>
22
23 #include <platform_def.h>
24
25 #define HEADER_VERSION_MAJOR_MASK GENMASK(23, 16)
26 #define RESET_TIMEOUT_US_1MS 1000U
27
28 /* Internal layout of the 32bit OTP word board_id */
29 #define BOARD_ID_BOARD_NB_MASK GENMASK_32(31, 16)
30 #define BOARD_ID_BOARD_NB_SHIFT 16
31 #define BOARD_ID_VARCPN_MASK GENMASK_32(15, 12)
32 #define BOARD_ID_VARCPN_SHIFT 12
33 #define BOARD_ID_REVISION_MASK GENMASK_32(11, 8)
34 #define BOARD_ID_REVISION_SHIFT 8
35 #define BOARD_ID_VARFG_MASK GENMASK_32(7, 4)
36 #define BOARD_ID_VARFG_SHIFT 4
37 #define BOARD_ID_BOM_MASK GENMASK_32(3, 0)
38
39 #define BOARD_ID2NB(_id) (((_id) & BOARD_ID_BOARD_NB_MASK) >> \
40 BOARD_ID_BOARD_NB_SHIFT)
41 #define BOARD_ID2VARCPN(_id) (((_id) & BOARD_ID_VARCPN_MASK) >> \
42 BOARD_ID_VARCPN_SHIFT)
43 #define BOARD_ID2REV(_id) (((_id) & BOARD_ID_REVISION_MASK) >> \
44 BOARD_ID_REVISION_SHIFT)
45 #define BOARD_ID2VARFG(_id) (((_id) & BOARD_ID_VARFG_MASK) >> \
46 BOARD_ID_VARFG_SHIFT)
47 #define BOARD_ID2BOM(_id) ((_id) & BOARD_ID_BOM_MASK)
48
49 #define BOOT_AUTH_MASK GENMASK_32(23, 20)
50 #define BOOT_AUTH_SHIFT 20
51 #define BOOT_PART_MASK GENMASK_32(19, 16)
52 #define BOOT_PART_SHIFT 16
53 #define BOOT_ITF_MASK GENMASK_32(15, 12)
54 #define BOOT_ITF_SHIFT 12
55 #define BOOT_INST_MASK GENMASK_32(11, 8)
56 #define BOOT_INST_SHIFT 8
57
58 static console_t console;
59
plat_get_ns_image_entrypoint(void)60 uintptr_t plat_get_ns_image_entrypoint(void)
61 {
62 return BL33_BASE;
63 }
64
plat_get_syscnt_freq2(void)65 unsigned int plat_get_syscnt_freq2(void)
66 {
67 return read_cntfrq_el0();
68 }
69
70 static uintptr_t boot_ctx_address;
71 static uint16_t boot_itf_selected;
72
stm32mp_save_boot_ctx_address(uintptr_t address)73 void stm32mp_save_boot_ctx_address(uintptr_t address)
74 {
75 boot_api_context_t *boot_context = (boot_api_context_t *)address;
76
77 boot_ctx_address = address;
78 boot_itf_selected = boot_context->boot_interface_selected;
79 }
80
stm32mp_get_boot_ctx_address(void)81 uintptr_t stm32mp_get_boot_ctx_address(void)
82 {
83 return boot_ctx_address;
84 }
85
stm32mp_get_boot_itf_selected(void)86 uint16_t stm32mp_get_boot_itf_selected(void)
87 {
88 return boot_itf_selected;
89 }
90
stm32mp_ddrctrl_base(void)91 uintptr_t stm32mp_ddrctrl_base(void)
92 {
93 return DDRCTRL_BASE;
94 }
95
stm32mp_ddrphyc_base(void)96 uintptr_t stm32mp_ddrphyc_base(void)
97 {
98 return DDRPHYC_BASE;
99 }
100
stm32mp_pwr_base(void)101 uintptr_t stm32mp_pwr_base(void)
102 {
103 return PWR_BASE;
104 }
105
stm32mp_rcc_base(void)106 uintptr_t stm32mp_rcc_base(void)
107 {
108 return RCC_BASE;
109 }
110
stm32mp_lock_available(void)111 bool stm32mp_lock_available(void)
112 {
113 const uint32_t c_m_bits = SCTLR_M_BIT | SCTLR_C_BIT;
114
115 /* The spinlocks are used only when MMU and data cache are enabled */
116 #ifdef __aarch64__
117 return (read_sctlr_el3() & c_m_bits) == c_m_bits;
118 #else
119 return (read_sctlr() & c_m_bits) == c_m_bits;
120 #endif
121 }
122
stm32mp_map_ddr_non_cacheable(void)123 int stm32mp_map_ddr_non_cacheable(void)
124 {
125 return mmap_add_dynamic_region(STM32MP_DDR_BASE, STM32MP_DDR_BASE,
126 STM32MP_DDR_MAX_SIZE,
127 MT_NON_CACHEABLE | MT_RW | MT_SECURE);
128 }
129
stm32mp_unmap_ddr(void)130 int stm32mp_unmap_ddr(void)
131 {
132 return mmap_remove_dynamic_region(STM32MP_DDR_BASE,
133 STM32MP_DDR_MAX_SIZE);
134 }
135
stm32_get_otp_index(const char * otp_name,uint32_t * otp_idx,uint32_t * otp_len)136 int stm32_get_otp_index(const char *otp_name, uint32_t *otp_idx,
137 uint32_t *otp_len)
138 {
139 assert(otp_name != NULL);
140 assert(otp_idx != NULL);
141
142 return dt_find_otp_name(otp_name, otp_idx, otp_len);
143 }
144
stm32_get_otp_value(const char * otp_name,uint32_t * otp_val)145 int stm32_get_otp_value(const char *otp_name, uint32_t *otp_val)
146 {
147 uint32_t otp_idx;
148
149 assert(otp_name != NULL);
150 assert(otp_val != NULL);
151
152 if (stm32_get_otp_index(otp_name, &otp_idx, NULL) != 0) {
153 return -1;
154 }
155
156 if (stm32_get_otp_value_from_idx(otp_idx, otp_val) != 0) {
157 ERROR("BSEC: %s Read Error\n", otp_name);
158 return -1;
159 }
160
161 return 0;
162 }
163
stm32_get_otp_value_from_idx(const uint32_t otp_idx,uint32_t * otp_val)164 int stm32_get_otp_value_from_idx(const uint32_t otp_idx, uint32_t *otp_val)
165 {
166 uint32_t ret = BSEC_NOT_SUPPORTED;
167
168 assert(otp_val != NULL);
169
170 #if defined(IMAGE_BL2)
171 ret = bsec_shadow_read_otp(otp_val, otp_idx);
172 #elif defined(IMAGE_BL32)
173 ret = bsec_read_otp(otp_val, otp_idx);
174 #else
175 #error "Not supported"
176 #endif
177 if (ret != BSEC_OK) {
178 ERROR("BSEC: idx=%u Read Error\n", otp_idx);
179 return -1;
180 }
181
182 return 0;
183 }
184
185 #if defined(IMAGE_BL2)
reset_uart(uint32_t reset)186 static void reset_uart(uint32_t reset)
187 {
188 int ret;
189
190 ret = stm32mp_reset_assert(reset, RESET_TIMEOUT_US_1MS);
191 if (ret != 0) {
192 panic();
193 }
194
195 udelay(2);
196
197 ret = stm32mp_reset_deassert(reset, RESET_TIMEOUT_US_1MS);
198 if (ret != 0) {
199 panic();
200 }
201
202 mdelay(1);
203 }
204 #endif
205
set_console(uintptr_t base,uint32_t clk_rate)206 static void set_console(uintptr_t base, uint32_t clk_rate)
207 {
208 unsigned int console_flags;
209
210 if (console_stm32_register(base, clk_rate,
211 (uint32_t)STM32MP_UART_BAUDRATE, &console) == 0) {
212 panic();
213 }
214
215 console_flags = CONSOLE_FLAG_BOOT | CONSOLE_FLAG_CRASH |
216 CONSOLE_FLAG_TRANSLATE_CRLF;
217 #if !defined(IMAGE_BL2) && defined(DEBUG)
218 console_flags |= CONSOLE_FLAG_RUNTIME;
219 #endif
220
221 console_set_scope(&console, console_flags);
222 }
223
stm32mp_uart_console_setup(void)224 int stm32mp_uart_console_setup(void)
225 {
226 struct dt_node_info dt_uart_info;
227 uint32_t clk_rate = 0U;
228 int result;
229 uint32_t boot_itf __unused;
230 uint32_t boot_instance __unused;
231
232 result = dt_get_stdout_uart_info(&dt_uart_info);
233
234 if ((result <= 0) ||
235 (dt_uart_info.status == DT_DISABLED)) {
236 return -ENODEV;
237 }
238
239 #if defined(IMAGE_BL2)
240 if ((dt_uart_info.clock < 0) ||
241 (dt_uart_info.reset < 0)) {
242 return -ENODEV;
243 }
244 #endif
245
246 #if STM32MP_UART_PROGRAMMER || !defined(IMAGE_BL2)
247 stm32_get_boot_interface(&boot_itf, &boot_instance);
248
249 if ((boot_itf == BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_UART) &&
250 (get_uart_address(boot_instance) == dt_uart_info.base)) {
251 return -EACCES;
252 }
253 #endif
254
255 #if defined(IMAGE_BL2)
256 if (dt_set_stdout_pinctrl() != 0) {
257 return -ENODEV;
258 }
259
260 clk_enable((unsigned long)dt_uart_info.clock);
261
262 reset_uart((uint32_t)dt_uart_info.reset);
263
264 clk_rate = clk_get_rate((unsigned long)dt_uart_info.clock);
265 #endif
266
267 set_console(dt_uart_info.base, clk_rate);
268
269 return 0;
270 }
271
272 #if STM32MP_EARLY_CONSOLE
stm32mp_setup_early_console(void)273 void stm32mp_setup_early_console(void)
274 {
275 #if defined(IMAGE_BL2) || STM32MP_RECONFIGURE_CONSOLE
276 plat_crash_console_init();
277 #endif
278 set_console(STM32MP_DEBUG_USART_BASE, STM32MP_DEBUG_USART_CLK_FRQ);
279 NOTICE("Early console setup\n");
280 }
281 #endif /* STM32MP_EARLY_CONSOLE */
282
283 /*****************************************************************************
284 * plat_is_smccc_feature_available() - This function checks whether SMCCC
285 * feature is availabile for platform.
286 * @fid: SMCCC function id
287 *
288 * Return SMC_ARCH_CALL_SUCCESS if SMCCC feature is available and
289 * SMC_ARCH_CALL_NOT_SUPPORTED otherwise.
290 *****************************************************************************/
plat_is_smccc_feature_available(u_register_t fid)291 int32_t plat_is_smccc_feature_available(u_register_t fid)
292 {
293 switch (fid) {
294 case SMCCC_ARCH_SOC_ID:
295 return SMC_ARCH_CALL_SUCCESS;
296 default:
297 return SMC_ARCH_CALL_NOT_SUPPORTED;
298 }
299 }
300
301 /* Get SOC version */
plat_get_soc_version(void)302 int32_t plat_get_soc_version(void)
303 {
304 uint32_t chip_id = stm32mp_get_chip_dev_id();
305 uint32_t manfid = SOC_ID_SET_JEP_106(JEDEC_ST_BKID, JEDEC_ST_MFID);
306
307 return (int32_t)(manfid | (chip_id & SOC_ID_IMPL_DEF_MASK));
308 }
309
310 /* Get SOC revision */
plat_get_soc_revision(void)311 int32_t plat_get_soc_revision(void)
312 {
313 return (int32_t)(stm32mp_get_chip_version() & SOC_ID_REV_MASK);
314 }
315
stm32_display_board_info(uint32_t board_id)316 void stm32_display_board_info(uint32_t board_id)
317 {
318 char rev[2];
319
320 rev[0] = BOARD_ID2REV(board_id) - 1 + 'A';
321 rev[1] = '\0';
322 NOTICE("Board: MB%04x Var%u.%u Rev.%s-%02u\n",
323 BOARD_ID2NB(board_id),
324 BOARD_ID2VARCPN(board_id),
325 BOARD_ID2VARFG(board_id),
326 rev,
327 BOARD_ID2BOM(board_id));
328 }
329
stm32_save_boot_info(boot_api_context_t * boot_context)330 void stm32_save_boot_info(boot_api_context_t *boot_context)
331 {
332 uint32_t auth_status;
333
334 assert(boot_context->boot_interface_instance <= (BOOT_INST_MASK >> BOOT_INST_SHIFT));
335 assert(boot_context->boot_interface_selected <= (BOOT_ITF_MASK >> BOOT_ITF_SHIFT));
336 assert(boot_context->boot_partition_used_toboot <= (BOOT_PART_MASK >> BOOT_PART_SHIFT));
337
338 switch (boot_context->auth_status) {
339 case BOOT_API_CTX_AUTH_NO:
340 auth_status = 0x0U;
341 break;
342
343 case BOOT_API_CTX_AUTH_SUCCESS:
344 auth_status = 0x2U;
345 break;
346
347 case BOOT_API_CTX_AUTH_FAILED:
348 default:
349 auth_status = 0x1U;
350 break;
351 }
352
353 clk_enable(TAMP_BKP_REG_CLK);
354
355 mmio_clrsetbits_32(stm32_get_bkpr_boot_mode_addr(),
356 BOOT_ITF_MASK | BOOT_INST_MASK | BOOT_PART_MASK | BOOT_AUTH_MASK,
357 (boot_context->boot_interface_instance << BOOT_INST_SHIFT) |
358 (boot_context->boot_interface_selected << BOOT_ITF_SHIFT) |
359 (boot_context->boot_partition_used_toboot << BOOT_PART_SHIFT) |
360 (auth_status << BOOT_AUTH_SHIFT));
361
362 clk_disable(TAMP_BKP_REG_CLK);
363 }
364
stm32_get_boot_interface(uint32_t * interface,uint32_t * instance)365 void stm32_get_boot_interface(uint32_t *interface, uint32_t *instance)
366 {
367 static uint32_t itf;
368
369 if (itf == 0U) {
370 clk_enable(TAMP_BKP_REG_CLK);
371
372 itf = mmio_read_32(stm32_get_bkpr_boot_mode_addr()) &
373 (BOOT_ITF_MASK | BOOT_INST_MASK);
374
375 clk_disable(TAMP_BKP_REG_CLK);
376 }
377
378 *interface = (itf & BOOT_ITF_MASK) >> BOOT_ITF_SHIFT;
379 *instance = (itf & BOOT_INST_MASK) >> BOOT_INST_SHIFT;
380 }
381
