1 /* 2 * Copyright 2020-2023 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 #ifndef PLATFORM_DEF_H 7 #define PLATFORM_DEF_H 8 9 #include <common/tbbr/tbbr_img_def.h> 10 #include <lib/utils_def.h> 11 #include <lib/xlat_tables/xlat_tables_v2.h> 12 #include <plat/common/common_def.h> 13 14 #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" 15 #define PLATFORM_LINKER_ARCH aarch64 16 17 #define PLATFORM_STACK_SIZE 0xB00 18 #define CACHE_WRITEBACK_GRANULE 64 19 20 #define PLAT_PRIMARY_CPU U(0x0) 21 #define PLATFORM_MAX_CPU_PER_CLUSTER U(4) 22 #define PLATFORM_CLUSTER_COUNT U(1) 23 #define PLATFORM_CLUSTER0_CORE_COUNT U(4) 24 #define PLATFORM_CLUSTER1_CORE_COUNT U(0) 25 #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER0_CORE_COUNT) 26 27 #define IMX_PWR_LVL0 MPIDR_AFFLVL0 28 #define IMX_PWR_LVL1 MPIDR_AFFLVL1 29 #define IMX_PWR_LVL2 MPIDR_AFFLVL2 30 31 #define PWR_DOMAIN_AT_MAX_LVL U(1) 32 #define PLAT_MAX_PWR_LVL U(2) 33 #define PLAT_MAX_OFF_STATE U(4) 34 #define PLAT_MAX_RET_STATE U(2) 35 36 #define PLAT_WAIT_RET_STATE U(1) 37 #define PLAT_STOP_OFF_STATE U(3) 38 39 #if defined(NEED_BL2) 40 #define BL2_BASE U(0x970000) 41 #define BL2_SIZE SZ_128K 42 #define BL2_LIMIT (BL2_BASE + BL2_SIZE) 43 #define BL31_BASE U(0x950000) 44 #define IMX_FIP_BASE U(0x40310000) 45 #define IMX_FIP_SIZE U(0x000300000) 46 #define IMX_FIP_LIMIT U(FIP_BASE + FIP_SIZE) 47 48 /* Define FIP image location on eMMC */ 49 #define IMX_FIP_MMC_BASE U(0x100000) 50 51 #define PLAT_IMX8MP_BOOT_MMC_BASE U(0x30B50000) /* SD */ 52 #else 53 #define BL31_BASE U(0x970000) 54 #endif 55 56 #define BL31_SIZE SZ_128K 57 #define BL31_LIMIT (BL31_BASE + BL31_SIZE) 58 59 #define PLAT_PRI_BITS U(3) 60 #define PLAT_SDEI_CRITICAL_PRI 0x10 61 #define PLAT_SDEI_NORMAL_PRI 0x20 62 #define PLAT_SDEI_SGI_PRIVATE U(9) 63 64 /* non-secure uboot base */ 65 #define PLAT_NS_IMAGE_OFFSET U(0x40200000) 66 #define PLAT_NS_IMAGE_SIZE U(0x00200000) 67 68 #define BL32_FDT_OVERLAY_ADDR (PLAT_NS_IMAGE_OFFSET + 0x3000000) 69 70 /* GICv3 base address */ 71 #define PLAT_GICD_BASE U(0x38800000) 72 #define PLAT_GICR_BASE U(0x38880000) 73 74 #define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 32) 75 #define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 32) 76 77 #define MAX_XLAT_TABLES 8 78 #define MAX_MMAP_REGIONS 16 79 80 #define HAB_RVT_BASE U(0x00000900) /* HAB_RVT for i.MX8MM */ 81 82 #define IMX_BOOT_UART_CLK_IN_HZ 24000000 /* Select 24MHz oscillator */ 83 #define PLAT_CRASH_UART_BASE IMX_BOOT_UART_BASE 84 #define PLAT_CRASH_UART_CLK_IN_HZ 24000000 85 #define IMX_CONSOLE_BAUDRATE 115200 86 87 #define IMX_AIPSTZ1 U(0x301f0000) 88 #define IMX_AIPSTZ2 U(0x305f0000) 89 #define IMX_AIPSTZ3 U(0x309f0000) 90 #define IMX_AIPSTZ4 U(0x32df0000) 91 #define IMX_AIPSTZ5 U(0x30df0000) 92 93 #define IMX_AIPS_BASE U(0x30000000) 94 #define IMX_AIPS_SIZE U(0x3000000) 95 #define IMX_GPV_BASE U(0x32000000) 96 #define IMX_GPV_SIZE U(0x800000) 97 #define IMX_AIPS1_BASE U(0x30200000) 98 #define IMX_AIPS4_BASE U(0x32c00000) 99 #define IMX_ANAMIX_BASE U(0x30360000) 100 #define IMX_CCM_BASE U(0x30380000) 101 #define IMX_SRC_BASE U(0x30390000) 102 #define IMX_GPC_BASE U(0x303a0000) 103 #define IMX_RDC_BASE U(0x303d0000) 104 #define IMX_CSU_BASE U(0x303e0000) 105 #define IMX_WDOG_BASE U(0x30280000) 106 #define IMX_SNVS_BASE U(0x30370000) 107 #define IMX_NOC_BASE U(0x32700000) 108 #define IMX_NOC_SIZE U(0x100000) 109 #define IMX_TZASC_BASE U(0x32F80000) 110 #define IMX_IOMUX_GPR_BASE U(0x30340000) 111 #define IMX_CAAM_BASE U(0x30900000) 112 #define IMX_DDRC_BASE U(0x3d400000) 113 #define IMX_DDRPHY_BASE U(0x3c000000) 114 #define IMX_DDR_IPS_BASE U(0x3d000000) 115 #define IMX_DDR_IPS_SIZE U(0x1900000) 116 #define IMX_ROM_BASE U(0x0) 117 #define IMX_ROM_SIZE U(0x40000) 118 #define IMX_NS_OCRAM_BASE U(0x900000) 119 #define IMX_NS_OCRAM_SIZE U(0x60000) 120 #define IMX_CAAM_RAM_BASE U(0x100000) 121 #define IMX_CAAM_RAM_SIZE U(0x10000) 122 #define IMX_DRAM_BASE U(0x40000000) 123 #define IMX_DRAM_SIZE U(0xc0000000) 124 125 #define IMX_GIC_BASE PLAT_GICD_BASE 126 #define IMX_GIC_SIZE U(0x200000) 127 128 #define IMX_HSIOMIX_CTL_BASE U(0x32f10000) 129 #define IMX_HDMI_CTL_BASE U(0x32fc0000) 130 #define RTX_RESET_CTL0 U(0x20) 131 #define RTX_CLK_CTL0 U(0x40) 132 #define RTX_CLK_CTL1 U(0x50) 133 #define TX_CONTROL0 U(0x200) 134 #define TX_CONTROL1 U(0x220) 135 136 #define IMX_MEDIAMIX_CTL_BASE U(0x32ec0000) 137 #define RSTn_CSR U(0x0) 138 #define CLK_EN_CSR U(0x4) 139 #define RST_DIV U(0x8) 140 #define LCDIF_ARCACHE_CTRL U(0x4c) 141 #define ISI_CACHE_CTRL U(0x50) 142 143 #define WDOG_WSR U(0x2) 144 #define WDOG_WCR_WDZST BIT(0) 145 #define WDOG_WCR_WDBG BIT(1) 146 #define WDOG_WCR_WDE BIT(2) 147 #define WDOG_WCR_WDT BIT(3) 148 #define WDOG_WCR_SRS BIT(4) 149 #define WDOG_WCR_WDA BIT(5) 150 #define WDOG_WCR_SRE BIT(6) 151 #define WDOG_WCR_WDW BIT(7) 152 153 #define SRC_A53RCR0 U(0x4) 154 #define SRC_A53RCR1 U(0x8) 155 #define SRC_OTG1PHY_SCR U(0x20) 156 #define SRC_OTG2PHY_SCR U(0x24) 157 #define SRC_GPR1_OFFSET U(0x74) 158 159 #define SNVS_LPCR U(0x38) 160 #define SNVS_LPCR_SRTC_ENV BIT(0) 161 #define SNVS_LPCR_DP_EN BIT(5) 162 #define SNVS_LPCR_TOP BIT(6) 163 164 #define IOMUXC_GPR10 U(0x28) 165 #define GPR_TZASC_EN BIT(0) 166 #define GPR_TZASC_EN_LOCK BIT(16) 167 168 #define ANAMIX_MISC_CTL U(0x124) 169 #define DRAM_PLL_CTRL (IMX_ANAMIX_BASE + 0x50) 170 171 #define MAX_CSU_NUM U(64) 172 173 #define OCRAM_S_BASE U(0x00180000) 174 #define OCRAM_S_SIZE U(0x8000) 175 #define OCRAM_S_LIMIT (OCRAM_S_BASE + OCRAM_S_SIZE) 176 #define SAVED_DRAM_TIMING_BASE OCRAM_S_BASE 177 178 #define COUNTER_FREQUENCY 8000000 /* 8MHz */ 179 180 #define IMX_WDOG_B_RESET 181 182 #define MAX_IO_HANDLES 3U 183 #define MAX_IO_DEVICES 2U 184 #define MAX_IO_BLOCK_DEVICES 1U 185 186 #define GIC_MAP MAP_REGION_FLAT(IMX_GIC_BASE, IMX_GIC_SIZE, MT_DEVICE | MT_RW) 187 #define AIPS_MAP MAP_REGION_FLAT(IMX_AIPS_BASE, IMX_AIPS_SIZE, MT_DEVICE | MT_RW) /* AIPS map */ 188 #define OCRAM_S_MAP MAP_REGION_FLAT(OCRAM_S_BASE, OCRAM_S_SIZE, MT_MEMORY | MT_RW) /* OCRAM_S */ 189 #define DDRC_MAP MAP_REGION_FLAT(IMX_DDRPHY_BASE, IMX_DDR_IPS_SIZE, MT_DEVICE | MT_RW) /* DDRMIX */ 190 #define NOC_MAP MAP_REGION_FLAT(IMX_NOC_BASE, IMX_NOC_SIZE, MT_DEVICE | MT_RW) /* NOC QoS */ 191 #define CAAM_RAM_MAP MAP_REGION_FLAT(IMX_CAAM_RAM_BASE, IMX_CAAM_RAM_SIZE, MT_MEMORY | MT_RW) /* CAMM RAM */ 192 #define NS_OCRAM_MAP MAP_REGION_FLAT(IMX_NS_OCRAM_BASE, IMX_NS_OCRAM_SIZE, MT_MEMORY | MT_RW) /* NS OCRAM */ 193 #define ROM_MAP MAP_REGION_FLAT(IMX_ROM_BASE, IMX_ROM_SIZE, MT_MEMORY | MT_RO) /* ROM code */ 194 195 /* 196 * Note: DRAM region is mapped with entire size available and uses MT_RW 197 * attributes. 198 * See details in docs/plat/imx8m.rst "High Assurance Boot (HABv4)" section 199 * for explanation of this mapping scheme. 200 */ 201 #define DRAM_MAP MAP_REGION_FLAT(IMX_DRAM_BASE, IMX_DRAM_SIZE, MT_MEMORY | MT_RW | MT_NS) /* DRAM */ 202 203 #endif /* platform_def.h */ 204
