1 /* 2 * Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2020-2022, NVIDIA Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef ARCH_H 9 #define ARCH_H 10 11 #include <lib/utils_def.h> 12 13 /******************************************************************************* 14 * MIDR bit definitions 15 ******************************************************************************/ 16 #define MIDR_IMPL_MASK U(0xff) 17 #define MIDR_IMPL_SHIFT U(0x18) 18 #define MIDR_VAR_SHIFT U(20) 19 #define MIDR_VAR_BITS U(4) 20 #define MIDR_VAR_MASK U(0xf) 21 #define MIDR_REV_SHIFT U(0) 22 #define MIDR_REV_BITS U(4) 23 #define MIDR_REV_MASK U(0xf) 24 #define MIDR_PN_MASK U(0xfff) 25 #define MIDR_PN_SHIFT U(0x4) 26 27 /******************************************************************************* 28 * MPIDR macros 29 ******************************************************************************/ 30 #define MPIDR_MT_MASK (ULL(1) << 24) 31 #define MPIDR_CPU_MASK MPIDR_AFFLVL_MASK 32 #define MPIDR_CLUSTER_MASK (MPIDR_AFFLVL_MASK << MPIDR_AFFINITY_BITS) 33 #define MPIDR_AFFINITY_BITS U(8) 34 #define MPIDR_AFFLVL_MASK ULL(0xff) 35 #define MPIDR_AFF0_SHIFT U(0) 36 #define MPIDR_AFF1_SHIFT U(8) 37 #define MPIDR_AFF2_SHIFT U(16) 38 #define MPIDR_AFF3_SHIFT U(32) 39 #define MPIDR_AFF_SHIFT(_n) MPIDR_AFF##_n##_SHIFT 40 #define MPIDR_AFFINITY_MASK ULL(0xff00ffffff) 41 #define MPIDR_AFFLVL_SHIFT U(3) 42 #define MPIDR_AFFLVL0 ULL(0x0) 43 #define MPIDR_AFFLVL1 ULL(0x1) 44 #define MPIDR_AFFLVL2 ULL(0x2) 45 #define MPIDR_AFFLVL3 ULL(0x3) 46 #define MPIDR_AFFLVL(_n) MPIDR_AFFLVL##_n 47 #define MPIDR_AFFLVL0_VAL(mpidr) \ 48 (((mpidr) >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK) 49 #define MPIDR_AFFLVL1_VAL(mpidr) \ 50 (((mpidr) >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK) 51 #define MPIDR_AFFLVL2_VAL(mpidr) \ 52 (((mpidr) >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK) 53 #define MPIDR_AFFLVL3_VAL(mpidr) \ 54 (((mpidr) >> MPIDR_AFF3_SHIFT) & MPIDR_AFFLVL_MASK) 55 /* 56 * The MPIDR_MAX_AFFLVL count starts from 0. Take care to 57 * add one while using this macro to define array sizes. 58 * TODO: Support only the first 3 affinity levels for now. 59 */ 60 #define MPIDR_MAX_AFFLVL U(2) 61 62 #define MPID_MASK (MPIDR_MT_MASK | \ 63 (MPIDR_AFFLVL_MASK << MPIDR_AFF3_SHIFT) | \ 64 (MPIDR_AFFLVL_MASK << MPIDR_AFF2_SHIFT) | \ 65 (MPIDR_AFFLVL_MASK << MPIDR_AFF1_SHIFT) | \ 66 (MPIDR_AFFLVL_MASK << MPIDR_AFF0_SHIFT)) 67 68 #define MPIDR_AFF_ID(mpid, n) \ 69 (((mpid) >> MPIDR_AFF_SHIFT(n)) & MPIDR_AFFLVL_MASK) 70 71 /* 72 * An invalid MPID. This value can be used by functions that return an MPID to 73 * indicate an error. 74 */ 75 #define INVALID_MPID U(0xFFFFFFFF) 76 77 /******************************************************************************* 78 * Definitions for CPU system register interface to GICv3 79 ******************************************************************************/ 80 #define ICC_IGRPEN1_EL1 S3_0_C12_C12_7 81 #define ICC_SGI1R S3_0_C12_C11_5 82 #define ICC_ASGI1R S3_0_C12_C11_6 83 #define ICC_SRE_EL1 S3_0_C12_C12_5 84 #define ICC_SRE_EL2 S3_4_C12_C9_5 85 #define ICC_SRE_EL3 S3_6_C12_C12_5 86 #define ICC_CTLR_EL1 S3_0_C12_C12_4 87 #define ICC_CTLR_EL3 S3_6_C12_C12_4 88 #define ICC_PMR_EL1 S3_0_C4_C6_0 89 #define ICC_RPR_EL1 S3_0_C12_C11_3 90 #define ICC_IGRPEN1_EL3 S3_6_c12_c12_7 91 #define ICC_IGRPEN0_EL1 S3_0_c12_c12_6 92 #define ICC_HPPIR0_EL1 S3_0_c12_c8_2 93 #define ICC_HPPIR1_EL1 S3_0_c12_c12_2 94 #define ICC_IAR0_EL1 S3_0_c12_c8_0 95 #define ICC_IAR1_EL1 S3_0_c12_c12_0 96 #define ICC_EOIR0_EL1 S3_0_c12_c8_1 97 #define ICC_EOIR1_EL1 S3_0_c12_c12_1 98 #define ICC_SGI0R_EL1 S3_0_c12_c11_7 99 100 /******************************************************************************* 101 * Definitions for EL2 system registers for save/restore routine 102 ******************************************************************************/ 103 #define CNTPOFF_EL2 S3_4_C14_C0_6 104 #define HAFGRTR_EL2 S3_4_C3_C1_6 105 #define HDFGRTR_EL2 S3_4_C3_C1_4 106 #define HDFGWTR_EL2 S3_4_C3_C1_5 107 #define HFGITR_EL2 S3_4_C1_C1_6 108 #define HFGRTR_EL2 S3_4_C1_C1_4 109 #define HFGWTR_EL2 S3_4_C1_C1_5 110 #define ICH_HCR_EL2 S3_4_C12_C11_0 111 #define ICH_VMCR_EL2 S3_4_C12_C11_7 112 #define MPAMVPM0_EL2 S3_4_C10_C6_0 113 #define MPAMVPM1_EL2 S3_4_C10_C6_1 114 #define MPAMVPM2_EL2 S3_4_C10_C6_2 115 #define MPAMVPM3_EL2 S3_4_C10_C6_3 116 #define MPAMVPM4_EL2 S3_4_C10_C6_4 117 #define MPAMVPM5_EL2 S3_4_C10_C6_5 118 #define MPAMVPM6_EL2 S3_4_C10_C6_6 119 #define MPAMVPM7_EL2 S3_4_C10_C6_7 120 #define MPAMVPMV_EL2 S3_4_C10_C4_1 121 #define TRFCR_EL2 S3_4_C1_C2_1 122 #define VNCR_EL2 S3_4_C2_C2_0 123 #define PMSCR_EL2 S3_4_C9_C9_0 124 #define TFSR_EL2 S3_4_C5_C6_0 125 #define CONTEXTIDR_EL2 S3_4_C13_C0_1 126 #define TTBR1_EL2 S3_4_C2_C0_1 127 128 /******************************************************************************* 129 * Generic timer memory mapped registers & offsets 130 ******************************************************************************/ 131 #define CNTCR_OFF U(0x000) 132 #define CNTCV_OFF U(0x008) 133 #define CNTFID_OFF U(0x020) 134 135 #define CNTCR_EN (U(1) << 0) 136 #define CNTCR_HDBG (U(1) << 1) 137 #define CNTCR_FCREQ(x) ((x) << 8) 138 139 /******************************************************************************* 140 * System register bit definitions 141 ******************************************************************************/ 142 /* CLIDR definitions */ 143 #define LOUIS_SHIFT U(21) 144 #define LOC_SHIFT U(24) 145 #define CTYPE_SHIFT(n) U(3 * (n - 1)) 146 #define CLIDR_FIELD_WIDTH U(3) 147 148 /* CSSELR definitions */ 149 #define LEVEL_SHIFT U(1) 150 151 /* Data cache set/way op type defines */ 152 #define DCISW U(0x0) 153 #define DCCISW U(0x1) 154 #if ERRATA_A53_827319 155 #define DCCSW DCCISW 156 #else 157 #define DCCSW U(0x2) 158 #endif 159 160 /* ID_AA64PFR0_EL1 definitions */ 161 #define ID_AA64PFR0_EL0_SHIFT U(0) 162 #define ID_AA64PFR0_EL1_SHIFT U(4) 163 #define ID_AA64PFR0_EL2_SHIFT U(8) 164 #define ID_AA64PFR0_EL3_SHIFT U(12) 165 166 #define ID_AA64PFR0_AMU_SHIFT U(44) 167 #define ID_AA64PFR0_AMU_MASK ULL(0xf) 168 #define ID_AA64PFR0_AMU_NOT_SUPPORTED U(0x0) 169 #define ID_AA64PFR0_AMU_V1 ULL(0x1) 170 #define ID_AA64PFR0_AMU_V1P1 U(0x2) 171 172 #define ID_AA64PFR0_ELX_MASK ULL(0xf) 173 174 #define ID_AA64PFR0_GIC_SHIFT U(24) 175 #define ID_AA64PFR0_GIC_WIDTH U(4) 176 #define ID_AA64PFR0_GIC_MASK ULL(0xf) 177 178 #define ID_AA64PFR0_SVE_SHIFT U(32) 179 #define ID_AA64PFR0_SVE_MASK ULL(0xf) 180 #define ID_AA64PFR0_SVE_SUPPORTED ULL(0x1) 181 #define ID_AA64PFR0_SVE_LENGTH U(4) 182 183 #define ID_AA64PFR0_SEL2_SHIFT U(36) 184 #define ID_AA64PFR0_SEL2_MASK ULL(0xf) 185 186 #define ID_AA64PFR0_MPAM_SHIFT U(40) 187 #define ID_AA64PFR0_MPAM_MASK ULL(0xf) 188 189 #define ID_AA64PFR0_DIT_SHIFT U(48) 190 #define ID_AA64PFR0_DIT_MASK ULL(0xf) 191 #define ID_AA64PFR0_DIT_LENGTH U(4) 192 #define ID_AA64PFR0_DIT_SUPPORTED U(1) 193 194 #define ID_AA64PFR0_CSV2_SHIFT U(56) 195 #define ID_AA64PFR0_CSV2_MASK ULL(0xf) 196 #define ID_AA64PFR0_CSV2_LENGTH U(4) 197 #define ID_AA64PFR0_CSV2_2_SUPPORTED ULL(0x2) 198 199 #define ID_AA64PFR0_FEAT_RME_SHIFT U(52) 200 #define ID_AA64PFR0_FEAT_RME_MASK ULL(0xf) 201 #define ID_AA64PFR0_FEAT_RME_LENGTH U(4) 202 #define ID_AA64PFR0_FEAT_RME_NOT_SUPPORTED U(0) 203 #define ID_AA64PFR0_FEAT_RME_V1 U(1) 204 205 #define ID_AA64PFR0_RAS_SHIFT U(28) 206 #define ID_AA64PFR0_RAS_MASK ULL(0xf) 207 #define ID_AA64PFR0_RAS_NOT_SUPPORTED ULL(0x0) 208 #define ID_AA64PFR0_RAS_LENGTH U(4) 209 210 /* Exception level handling */ 211 #define EL_IMPL_NONE ULL(0) 212 #define EL_IMPL_A64ONLY ULL(1) 213 #define EL_IMPL_A64_A32 ULL(2) 214 215 /* ID_AA64DFR0_EL1.TraceVer definitions */ 216 #define ID_AA64DFR0_TRACEVER_SHIFT U(4) 217 #define ID_AA64DFR0_TRACEVER_MASK ULL(0xf) 218 #define ID_AA64DFR0_TRACEVER_SUPPORTED ULL(1) 219 #define ID_AA64DFR0_TRACEVER_LENGTH U(4) 220 #define ID_AA64DFR0_TRACEFILT_SHIFT U(40) 221 #define ID_AA64DFR0_TRACEFILT_MASK U(0xf) 222 #define ID_AA64DFR0_TRACEFILT_SUPPORTED U(1) 223 #define ID_AA64DFR0_TRACEFILT_LENGTH U(4) 224 225 /* ID_AA64DFR0_EL1.PMS definitions (for ARMv8.2+) */ 226 #define ID_AA64DFR0_PMS_SHIFT U(32) 227 #define ID_AA64DFR0_PMS_MASK ULL(0xf) 228 #define ID_AA64DFR0_SPE_SUPPORTED ULL(0x1) 229 #define ID_AA64DFR0_SPE_NOT_SUPPORTED ULL(0x0) 230 231 /* ID_AA64DFR0_EL1.TraceBuffer definitions */ 232 #define ID_AA64DFR0_TRACEBUFFER_SHIFT U(44) 233 #define ID_AA64DFR0_TRACEBUFFER_MASK ULL(0xf) 234 #define ID_AA64DFR0_TRACEBUFFER_SUPPORTED ULL(1) 235 236 /* ID_AA64DFR0_EL1.MTPMU definitions (for ARMv8.6+) */ 237 #define ID_AA64DFR0_MTPMU_SHIFT U(48) 238 #define ID_AA64DFR0_MTPMU_MASK ULL(0xf) 239 #define ID_AA64DFR0_MTPMU_SUPPORTED ULL(1) 240 241 /* ID_AA64DFR0_EL1.BRBE definitions */ 242 #define ID_AA64DFR0_BRBE_SHIFT U(52) 243 #define ID_AA64DFR0_BRBE_MASK ULL(0xf) 244 #define ID_AA64DFR0_BRBE_SUPPORTED ULL(1) 245 246 /* ID_AA64ISAR0_EL1 definitions */ 247 #define ID_AA64ISAR0_RNDR_SHIFT U(60) 248 #define ID_AA64ISAR0_RNDR_MASK ULL(0xf) 249 250 /* ID_AA64ISAR1_EL1 definitions */ 251 #define ID_AA64ISAR1_EL1 S3_0_C0_C6_1 252 253 #define ID_AA64ISAR1_GPI_SHIFT U(28) 254 #define ID_AA64ISAR1_GPI_MASK ULL(0xf) 255 #define ID_AA64ISAR1_GPA_SHIFT U(24) 256 #define ID_AA64ISAR1_GPA_MASK ULL(0xf) 257 258 #define ID_AA64ISAR1_API_SHIFT U(8) 259 #define ID_AA64ISAR1_API_MASK ULL(0xf) 260 #define ID_AA64ISAR1_APA_SHIFT U(4) 261 #define ID_AA64ISAR1_APA_MASK ULL(0xf) 262 263 #define ID_AA64ISAR1_SB_SHIFT U(36) 264 #define ID_AA64ISAR1_SB_MASK ULL(0xf) 265 #define ID_AA64ISAR1_SB_SUPPORTED ULL(0x1) 266 #define ID_AA64ISAR1_SB_NOT_SUPPORTED ULL(0x0) 267 268 /* ID_AA64ISAR2_EL1 definitions */ 269 #define ID_AA64ISAR2_EL1 S3_0_C0_C6_2 270 271 #define ID_AA64ISAR2_GPA3_SHIFT U(8) 272 #define ID_AA64ISAR2_GPA3_MASK ULL(0xf) 273 274 #define ID_AA64ISAR2_APA3_SHIFT U(12) 275 #define ID_AA64ISAR2_APA3_MASK ULL(0xf) 276 277 /* ID_AA64MMFR0_EL1 definitions */ 278 #define ID_AA64MMFR0_EL1_PARANGE_SHIFT U(0) 279 #define ID_AA64MMFR0_EL1_PARANGE_MASK ULL(0xf) 280 281 #define PARANGE_0000 U(32) 282 #define PARANGE_0001 U(36) 283 #define PARANGE_0010 U(40) 284 #define PARANGE_0011 U(42) 285 #define PARANGE_0100 U(44) 286 #define PARANGE_0101 U(48) 287 #define PARANGE_0110 U(52) 288 289 #define ID_AA64MMFR0_EL1_ECV_SHIFT U(60) 290 #define ID_AA64MMFR0_EL1_ECV_MASK ULL(0xf) 291 #define ID_AA64MMFR0_EL1_ECV_NOT_SUPPORTED ULL(0x0) 292 #define ID_AA64MMFR0_EL1_ECV_SUPPORTED ULL(0x1) 293 #define ID_AA64MMFR0_EL1_ECV_SELF_SYNCH ULL(0x2) 294 295 #define ID_AA64MMFR0_EL1_FGT_SHIFT U(56) 296 #define ID_AA64MMFR0_EL1_FGT_MASK ULL(0xf) 297 #define ID_AA64MMFR0_EL1_FGT_SUPPORTED ULL(0x1) 298 #define ID_AA64MMFR0_EL1_FGT_NOT_SUPPORTED ULL(0x0) 299 300 #define ID_AA64MMFR0_EL1_TGRAN4_SHIFT U(28) 301 #define ID_AA64MMFR0_EL1_TGRAN4_MASK ULL(0xf) 302 #define ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED ULL(0x0) 303 #define ID_AA64MMFR0_EL1_TGRAN4_NOT_SUPPORTED ULL(0xf) 304 305 #define ID_AA64MMFR0_EL1_TGRAN64_SHIFT U(24) 306 #define ID_AA64MMFR0_EL1_TGRAN64_MASK ULL(0xf) 307 #define ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED ULL(0x0) 308 #define ID_AA64MMFR0_EL1_TGRAN64_NOT_SUPPORTED ULL(0xf) 309 310 #define ID_AA64MMFR0_EL1_TGRAN16_SHIFT U(20) 311 #define ID_AA64MMFR0_EL1_TGRAN16_MASK ULL(0xf) 312 #define ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED ULL(0x1) 313 #define ID_AA64MMFR0_EL1_TGRAN16_NOT_SUPPORTED ULL(0x0) 314 315 /* ID_AA64MMFR1_EL1 definitions */ 316 #define ID_AA64MMFR1_EL1_TWED_SHIFT U(32) 317 #define ID_AA64MMFR1_EL1_TWED_MASK ULL(0xf) 318 #define ID_AA64MMFR1_EL1_TWED_SUPPORTED ULL(0x1) 319 #define ID_AA64MMFR1_EL1_TWED_NOT_SUPPORTED ULL(0x0) 320 321 #define ID_AA64MMFR1_EL1_PAN_SHIFT U(20) 322 #define ID_AA64MMFR1_EL1_PAN_MASK ULL(0xf) 323 #define ID_AA64MMFR1_EL1_PAN_NOT_SUPPORTED ULL(0x0) 324 #define ID_AA64MMFR1_EL1_PAN_SUPPORTED ULL(0x1) 325 #define ID_AA64MMFR1_EL1_PAN2_SUPPORTED ULL(0x2) 326 #define ID_AA64MMFR1_EL1_PAN3_SUPPORTED ULL(0x3) 327 328 #define ID_AA64MMFR1_EL1_VHE_SHIFT U(8) 329 #define ID_AA64MMFR1_EL1_VHE_MASK ULL(0xf) 330 331 #define ID_AA64MMFR1_EL1_HCX_SHIFT U(40) 332 #define ID_AA64MMFR1_EL1_HCX_MASK ULL(0xf) 333 #define ID_AA64MMFR1_EL1_HCX_SUPPORTED ULL(0x1) 334 #define ID_AA64MMFR1_EL1_HCX_NOT_SUPPORTED ULL(0x0) 335 336 /* ID_AA64MMFR2_EL1 definitions */ 337 #define ID_AA64MMFR2_EL1 S3_0_C0_C7_2 338 339 #define ID_AA64MMFR2_EL1_ST_SHIFT U(28) 340 #define ID_AA64MMFR2_EL1_ST_MASK ULL(0xf) 341 342 #define ID_AA64MMFR2_EL1_CCIDX_SHIFT U(20) 343 #define ID_AA64MMFR2_EL1_CCIDX_MASK ULL(0xf) 344 #define ID_AA64MMFR2_EL1_CCIDX_LENGTH U(4) 345 346 #define ID_AA64MMFR2_EL1_CNP_SHIFT U(0) 347 #define ID_AA64MMFR2_EL1_CNP_MASK ULL(0xf) 348 349 #define ID_AA64MMFR2_EL1_NV_SHIFT U(24) 350 #define ID_AA64MMFR2_EL1_NV_MASK ULL(0xf) 351 #define ID_AA64MMFR2_EL1_NV_NOT_SUPPORTED ULL(0x0) 352 #define ID_AA64MMFR2_EL1_NV_SUPPORTED ULL(0x1) 353 #define ID_AA64MMFR2_EL1_NV2_SUPPORTED ULL(0x2) 354 355 /* ID_AA64MMFR3_EL1 definitions */ 356 #define ID_AA64MMFR3_EL1 S3_0_C0_C7_3 357 358 #define ID_AA64MMFR3_EL1_S2POE_SHIFT U(20) 359 #define ID_AA64MMFR3_EL1_S2POE_MASK ULL(0xf) 360 361 #define ID_AA64MMFR3_EL1_S1POE_SHIFT U(16) 362 #define ID_AA64MMFR3_EL1_S1POE_MASK ULL(0xf) 363 364 #define ID_AA64MMFR3_EL1_S2PIE_SHIFT U(12) 365 #define ID_AA64MMFR3_EL1_S2PIE_MASK ULL(0xf) 366 367 #define ID_AA64MMFR3_EL1_S1PIE_SHIFT U(8) 368 #define ID_AA64MMFR3_EL1_S1PIE_MASK ULL(0xf) 369 370 #define ID_AA64MMFR3_EL1_TCRX_SHIFT U(0) 371 #define ID_AA64MMFR3_EL1_TCRX_MASK ULL(0xf) 372 373 /* ID_AA64PFR1_EL1 definitions */ 374 #define ID_AA64PFR1_EL1_GCS_SHIFT U(44) 375 #define ID_AA64PFR1_EL1_GCS_MASK ULL(0xf) 376 377 #define ID_AA64PFR1_EL1_SSBS_SHIFT U(4) 378 #define ID_AA64PFR1_EL1_SSBS_MASK ULL(0xf) 379 380 #define SSBS_UNAVAILABLE ULL(0) /* No architectural SSBS support */ 381 382 #define ID_AA64PFR1_EL1_BT_SHIFT U(0) 383 #define ID_AA64PFR1_EL1_BT_MASK ULL(0xf) 384 385 #define BTI_IMPLEMENTED ULL(1) /* The BTI mechanism is implemented */ 386 387 #define ID_AA64PFR1_EL1_MTE_SHIFT U(8) 388 #define ID_AA64PFR1_EL1_MTE_MASK ULL(0xf) 389 390 #define ID_AA64PFR1_EL1_RNDR_TRAP_SHIFT U(28) 391 #define ID_AA64PFR1_EL1_RNDR_TRAP_MASK U(0xf) 392 393 #define ID_AA64PFR1_EL1_RNG_TRAP_SUPPORTED ULL(0x1) 394 #define ID_AA64PFR1_EL1_RNG_TRAP_NOT_SUPPORTED ULL(0x0) 395 396 #define VDISR_EL2 S3_4_C12_C1_1 397 #define VSESR_EL2 S3_4_C5_C2_3 398 399 /* Memory Tagging Extension is not implemented */ 400 #define MTE_UNIMPLEMENTED U(0) 401 /* FEAT_MTE: MTE instructions accessible at EL0 are implemented */ 402 #define MTE_IMPLEMENTED_EL0 U(1) 403 /* FEAT_MTE2: Full MTE is implemented */ 404 #define MTE_IMPLEMENTED_ELX U(2) 405 /* 406 * FEAT_MTE3: MTE is implemented with support for 407 * asymmetric Tag Check Fault handling 408 */ 409 #define MTE_IMPLEMENTED_ASY U(3) 410 411 #define ID_AA64PFR1_MPAM_FRAC_SHIFT ULL(16) 412 #define ID_AA64PFR1_MPAM_FRAC_MASK ULL(0xf) 413 414 #define ID_AA64PFR1_EL1_SME_SHIFT U(24) 415 #define ID_AA64PFR1_EL1_SME_MASK ULL(0xf) 416 #define ID_AA64PFR1_EL1_SME_NOT_SUPPORTED ULL(0x0) 417 #define ID_AA64PFR1_EL1_SME_SUPPORTED ULL(0x1) 418 #define ID_AA64PFR1_EL1_SME2_SUPPORTED ULL(0x2) 419 420 /* ID_PFR1_EL1 definitions */ 421 #define ID_PFR1_VIRTEXT_SHIFT U(12) 422 #define ID_PFR1_VIRTEXT_MASK U(0xf) 423 #define GET_VIRT_EXT(id) (((id) >> ID_PFR1_VIRTEXT_SHIFT) \ 424 & ID_PFR1_VIRTEXT_MASK) 425 426 /* SCTLR definitions */ 427 #define SCTLR_EL2_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \ 428 (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \ 429 (U(1) << 11) | (U(1) << 5) | (U(1) << 4)) 430 431 #define SCTLR_EL1_RES1 ((UL(1) << 29) | (UL(1) << 28) | (UL(1) << 23) | \ 432 (UL(1) << 22) | (UL(1) << 20) | (UL(1) << 11)) 433 434 #define SCTLR_AARCH32_EL1_RES1 \ 435 ((U(1) << 23) | (U(1) << 22) | (U(1) << 11) | \ 436 (U(1) << 4) | (U(1) << 3)) 437 438 #define SCTLR_EL3_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \ 439 (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \ 440 (U(1) << 11) | (U(1) << 5) | (U(1) << 4)) 441 442 #define SCTLR_M_BIT (ULL(1) << 0) 443 #define SCTLR_A_BIT (ULL(1) << 1) 444 #define SCTLR_C_BIT (ULL(1) << 2) 445 #define SCTLR_SA_BIT (ULL(1) << 3) 446 #define SCTLR_SA0_BIT (ULL(1) << 4) 447 #define SCTLR_CP15BEN_BIT (ULL(1) << 5) 448 #define SCTLR_nAA_BIT (ULL(1) << 6) 449 #define SCTLR_ITD_BIT (ULL(1) << 7) 450 #define SCTLR_SED_BIT (ULL(1) << 8) 451 #define SCTLR_UMA_BIT (ULL(1) << 9) 452 #define SCTLR_EnRCTX_BIT (ULL(1) << 10) 453 #define SCTLR_EOS_BIT (ULL(1) << 11) 454 #define SCTLR_I_BIT (ULL(1) << 12) 455 #define SCTLR_EnDB_BIT (ULL(1) << 13) 456 #define SCTLR_DZE_BIT (ULL(1) << 14) 457 #define SCTLR_UCT_BIT (ULL(1) << 15) 458 #define SCTLR_NTWI_BIT (ULL(1) << 16) 459 #define SCTLR_NTWE_BIT (ULL(1) << 18) 460 #define SCTLR_WXN_BIT (ULL(1) << 19) 461 #define SCTLR_TSCXT_BIT (ULL(1) << 20) 462 #define SCTLR_IESB_BIT (ULL(1) << 21) 463 #define SCTLR_EIS_BIT (ULL(1) << 22) 464 #define SCTLR_SPAN_BIT (ULL(1) << 23) 465 #define SCTLR_E0E_BIT (ULL(1) << 24) 466 #define SCTLR_EE_BIT (ULL(1) << 25) 467 #define SCTLR_UCI_BIT (ULL(1) << 26) 468 #define SCTLR_EnDA_BIT (ULL(1) << 27) 469 #define SCTLR_nTLSMD_BIT (ULL(1) << 28) 470 #define SCTLR_LSMAOE_BIT (ULL(1) << 29) 471 #define SCTLR_EnIB_BIT (ULL(1) << 30) 472 #define SCTLR_EnIA_BIT (ULL(1) << 31) 473 #define SCTLR_BT0_BIT (ULL(1) << 35) 474 #define SCTLR_BT1_BIT (ULL(1) << 36) 475 #define SCTLR_BT_BIT (ULL(1) << 36) 476 #define SCTLR_ITFSB_BIT (ULL(1) << 37) 477 #define SCTLR_TCF0_SHIFT U(38) 478 #define SCTLR_TCF0_MASK ULL(3) 479 #define SCTLR_ENTP2_BIT (ULL(1) << 60) 480 481 /* Tag Check Faults in EL0 have no effect on the PE */ 482 #define SCTLR_TCF0_NO_EFFECT U(0) 483 /* Tag Check Faults in EL0 cause a synchronous exception */ 484 #define SCTLR_TCF0_SYNC U(1) 485 /* Tag Check Faults in EL0 are asynchronously accumulated */ 486 #define SCTLR_TCF0_ASYNC U(2) 487 /* 488 * Tag Check Faults in EL0 cause a synchronous exception on reads, 489 * and are asynchronously accumulated on writes 490 */ 491 #define SCTLR_TCF0_SYNCR_ASYNCW U(3) 492 493 #define SCTLR_TCF_SHIFT U(40) 494 #define SCTLR_TCF_MASK ULL(3) 495 496 /* Tag Check Faults in EL1 have no effect on the PE */ 497 #define SCTLR_TCF_NO_EFFECT U(0) 498 /* Tag Check Faults in EL1 cause a synchronous exception */ 499 #define SCTLR_TCF_SYNC U(1) 500 /* Tag Check Faults in EL1 are asynchronously accumulated */ 501 #define SCTLR_TCF_ASYNC U(2) 502 /* 503 * Tag Check Faults in EL1 cause a synchronous exception on reads, 504 * and are asynchronously accumulated on writes 505 */ 506 #define SCTLR_TCF_SYNCR_ASYNCW U(3) 507 508 #define SCTLR_ATA0_BIT (ULL(1) << 42) 509 #define SCTLR_ATA_BIT (ULL(1) << 43) 510 #define SCTLR_DSSBS_SHIFT U(44) 511 #define SCTLR_DSSBS_BIT (ULL(1) << SCTLR_DSSBS_SHIFT) 512 #define SCTLR_TWEDEn_BIT (ULL(1) << 45) 513 #define SCTLR_TWEDEL_SHIFT U(46) 514 #define SCTLR_TWEDEL_MASK ULL(0xf) 515 #define SCTLR_EnASR_BIT (ULL(1) << 54) 516 #define SCTLR_EnAS0_BIT (ULL(1) << 55) 517 #define SCTLR_EnALS_BIT (ULL(1) << 56) 518 #define SCTLR_EPAN_BIT (ULL(1) << 57) 519 #define SCTLR_RESET_VAL SCTLR_EL3_RES1 520 521 /* CPACR_EL1 definitions */ 522 #define CPACR_EL1_FPEN(x) ((x) << 20) 523 #define CPACR_EL1_FP_TRAP_EL0 UL(0x1) 524 #define CPACR_EL1_FP_TRAP_ALL UL(0x2) 525 #define CPACR_EL1_FP_TRAP_NONE UL(0x3) 526 #define CPACR_EL1_SMEN_SHIFT U(24) 527 #define CPACR_EL1_SMEN_MASK ULL(0x3) 528 529 /* SCR definitions */ 530 #define SCR_RES1_BITS ((U(1) << 4) | (U(1) << 5)) 531 #define SCR_NSE_SHIFT U(62) 532 #define SCR_NSE_BIT (ULL(1) << SCR_NSE_SHIFT) 533 #define SCR_GPF_BIT (UL(1) << 48) 534 #define SCR_TWEDEL_SHIFT U(30) 535 #define SCR_TWEDEL_MASK ULL(0xf) 536 #define SCR_PIEN_BIT (UL(1) << 45) 537 #define SCR_TCR2EN_BIT (UL(1) << 43) 538 #define SCR_TRNDR_BIT (UL(1) << 40) 539 #define SCR_GCSEn_BIT (UL(1) << 39) 540 #define SCR_HXEn_BIT (UL(1) << 38) 541 #define SCR_ENTP2_SHIFT U(41) 542 #define SCR_ENTP2_BIT (UL(1) << SCR_ENTP2_SHIFT) 543 #define SCR_AMVOFFEN_SHIFT U(35) 544 #define SCR_AMVOFFEN_BIT (UL(1) << SCR_AMVOFFEN_SHIFT) 545 #define SCR_TWEDEn_BIT (UL(1) << 29) 546 #define SCR_ECVEN_BIT (UL(1) << 28) 547 #define SCR_FGTEN_BIT (UL(1) << 27) 548 #define SCR_ATA_BIT (UL(1) << 26) 549 #define SCR_EnSCXT_BIT (UL(1) << 25) 550 #define SCR_FIEN_BIT (UL(1) << 21) 551 #define SCR_EEL2_BIT (UL(1) << 18) 552 #define SCR_API_BIT (UL(1) << 17) 553 #define SCR_APK_BIT (UL(1) << 16) 554 #define SCR_TERR_BIT (UL(1) << 15) 555 #define SCR_TWE_BIT (UL(1) << 13) 556 #define SCR_TWI_BIT (UL(1) << 12) 557 #define SCR_ST_BIT (UL(1) << 11) 558 #define SCR_RW_BIT (UL(1) << 10) 559 #define SCR_SIF_BIT (UL(1) << 9) 560 #define SCR_HCE_BIT (UL(1) << 8) 561 #define SCR_SMD_BIT (UL(1) << 7) 562 #define SCR_EA_BIT (UL(1) << 3) 563 #define SCR_FIQ_BIT (UL(1) << 2) 564 #define SCR_IRQ_BIT (UL(1) << 1) 565 #define SCR_NS_BIT (UL(1) << 0) 566 #define SCR_VALID_BIT_MASK U(0x24000002F8F) 567 #define SCR_RESET_VAL SCR_RES1_BITS 568 569 /* MDCR_EL3 definitions */ 570 #define MDCR_EnPMSN_BIT (ULL(1) << 36) 571 #define MDCR_MPMX_BIT (ULL(1) << 35) 572 #define MDCR_MCCD_BIT (ULL(1) << 34) 573 #define MDCR_SBRBE_SHIFT U(32) 574 #define MDCR_SBRBE_MASK ULL(0x3) 575 #define MDCR_NSTB(x) ((x) << 24) 576 #define MDCR_NSTB_EL1 ULL(0x3) 577 #define MDCR_NSTBE (ULL(1) << 26) 578 #define MDCR_MTPME_BIT (ULL(1) << 28) 579 #define MDCR_TDCC_BIT (ULL(1) << 27) 580 #define MDCR_SCCD_BIT (ULL(1) << 23) 581 #define MDCR_EPMAD_BIT (ULL(1) << 21) 582 #define MDCR_EDAD_BIT (ULL(1) << 20) 583 #define MDCR_TTRF_BIT (ULL(1) << 19) 584 #define MDCR_STE_BIT (ULL(1) << 18) 585 #define MDCR_SPME_BIT (ULL(1) << 17) 586 #define MDCR_SDD_BIT (ULL(1) << 16) 587 #define MDCR_SPD32(x) ((x) << 14) 588 #define MDCR_SPD32_LEGACY ULL(0x0) 589 #define MDCR_SPD32_DISABLE ULL(0x2) 590 #define MDCR_SPD32_ENABLE ULL(0x3) 591 #define MDCR_NSPB(x) ((x) << 12) 592 #define MDCR_NSPB_EL1 ULL(0x3) 593 #define MDCR_TDOSA_BIT (ULL(1) << 10) 594 #define MDCR_TDA_BIT (ULL(1) << 9) 595 #define MDCR_TPM_BIT (ULL(1) << 6) 596 #define MDCR_EL3_RESET_VAL ULL(0x0) 597 598 /* MDCR_EL2 definitions */ 599 #define MDCR_EL2_MTPME (U(1) << 28) 600 #define MDCR_EL2_HLP (U(1) << 26) 601 #define MDCR_EL2_E2TB(x) ((x) << 24) 602 #define MDCR_EL2_E2TB_EL1 U(0x3) 603 #define MDCR_EL2_HCCD (U(1) << 23) 604 #define MDCR_EL2_TTRF (U(1) << 19) 605 #define MDCR_EL2_HPMD (U(1) << 17) 606 #define MDCR_EL2_TPMS (U(1) << 14) 607 #define MDCR_EL2_E2PB(x) ((x) << 12) 608 #define MDCR_EL2_E2PB_EL1 U(0x3) 609 #define MDCR_EL2_TDRA_BIT (U(1) << 11) 610 #define MDCR_EL2_TDOSA_BIT (U(1) << 10) 611 #define MDCR_EL2_TDA_BIT (U(1) << 9) 612 #define MDCR_EL2_TDE_BIT (U(1) << 8) 613 #define MDCR_EL2_HPME_BIT (U(1) << 7) 614 #define MDCR_EL2_TPM_BIT (U(1) << 6) 615 #define MDCR_EL2_TPMCR_BIT (U(1) << 5) 616 #define MDCR_EL2_RESET_VAL U(0x0) 617 618 /* HSTR_EL2 definitions */ 619 #define HSTR_EL2_RESET_VAL U(0x0) 620 #define HSTR_EL2_T_MASK U(0xff) 621 622 /* CNTHP_CTL_EL2 definitions */ 623 #define CNTHP_CTL_ENABLE_BIT (U(1) << 0) 624 #define CNTHP_CTL_RESET_VAL U(0x0) 625 626 /* VTTBR_EL2 definitions */ 627 #define VTTBR_RESET_VAL ULL(0x0) 628 #define VTTBR_VMID_MASK ULL(0xff) 629 #define VTTBR_VMID_SHIFT U(48) 630 #define VTTBR_BADDR_MASK ULL(0xffffffffffff) 631 #define VTTBR_BADDR_SHIFT U(0) 632 633 /* HCR definitions */ 634 #define HCR_RESET_VAL ULL(0x0) 635 #define HCR_AMVOFFEN_SHIFT U(51) 636 #define HCR_AMVOFFEN_BIT (ULL(1) << HCR_AMVOFFEN_SHIFT) 637 #define HCR_TEA_BIT (ULL(1) << 47) 638 #define HCR_API_BIT (ULL(1) << 41) 639 #define HCR_APK_BIT (ULL(1) << 40) 640 #define HCR_E2H_BIT (ULL(1) << 34) 641 #define HCR_HCD_BIT (ULL(1) << 29) 642 #define HCR_TGE_BIT (ULL(1) << 27) 643 #define HCR_RW_SHIFT U(31) 644 #define HCR_RW_BIT (ULL(1) << HCR_RW_SHIFT) 645 #define HCR_TWE_BIT (ULL(1) << 14) 646 #define HCR_TWI_BIT (ULL(1) << 13) 647 #define HCR_AMO_BIT (ULL(1) << 5) 648 #define HCR_IMO_BIT (ULL(1) << 4) 649 #define HCR_FMO_BIT (ULL(1) << 3) 650 651 /* ISR definitions */ 652 #define ISR_A_SHIFT U(8) 653 #define ISR_I_SHIFT U(7) 654 #define ISR_F_SHIFT U(6) 655 656 /* CNTHCTL_EL2 definitions */ 657 #define CNTHCTL_RESET_VAL U(0x0) 658 #define EVNTEN_BIT (U(1) << 2) 659 #define EL1PCEN_BIT (U(1) << 1) 660 #define EL1PCTEN_BIT (U(1) << 0) 661 662 /* CNTKCTL_EL1 definitions */ 663 #define EL0PTEN_BIT (U(1) << 9) 664 #define EL0VTEN_BIT (U(1) << 8) 665 #define EL0PCTEN_BIT (U(1) << 0) 666 #define EL0VCTEN_BIT (U(1) << 1) 667 #define EVNTEN_BIT (U(1) << 2) 668 #define EVNTDIR_BIT (U(1) << 3) 669 #define EVNTI_SHIFT U(4) 670 #define EVNTI_MASK U(0xf) 671 672 /* CPTR_EL3 definitions */ 673 #define TCPAC_BIT (U(1) << 31) 674 #define TAM_SHIFT U(30) 675 #define TAM_BIT (U(1) << TAM_SHIFT) 676 #define TTA_BIT (U(1) << 20) 677 #define ESM_BIT (U(1) << 12) 678 #define TFP_BIT (U(1) << 10) 679 #define CPTR_EZ_BIT (U(1) << 8) 680 #define CPTR_EL3_RESET_VAL ((TCPAC_BIT | TAM_BIT | TTA_BIT | TFP_BIT) & \ 681 ~(CPTR_EZ_BIT | ESM_BIT)) 682 683 /* CPTR_EL2 definitions */ 684 #define CPTR_EL2_RES1 ((U(1) << 13) | (U(1) << 12) | (U(0x3ff))) 685 #define CPTR_EL2_TCPAC_BIT (U(1) << 31) 686 #define CPTR_EL2_TAM_SHIFT U(30) 687 #define CPTR_EL2_TAM_BIT (U(1) << CPTR_EL2_TAM_SHIFT) 688 #define CPTR_EL2_SMEN_MASK ULL(0x3) 689 #define CPTR_EL2_SMEN_SHIFT U(24) 690 #define CPTR_EL2_TTA_BIT (U(1) << 20) 691 #define CPTR_EL2_TSM_BIT (U(1) << 12) 692 #define CPTR_EL2_TFP_BIT (U(1) << 10) 693 #define CPTR_EL2_TZ_BIT (U(1) << 8) 694 #define CPTR_EL2_RESET_VAL CPTR_EL2_RES1 695 696 /* VTCR_EL2 definitions */ 697 #define VTCR_RESET_VAL U(0x0) 698 #define VTCR_EL2_MSA (U(1) << 31) 699 700 /* CPSR/SPSR definitions */ 701 #define DAIF_FIQ_BIT (U(1) << 0) 702 #define DAIF_IRQ_BIT (U(1) << 1) 703 #define DAIF_ABT_BIT (U(1) << 2) 704 #define DAIF_DBG_BIT (U(1) << 3) 705 #define SPSR_DAIF_SHIFT U(6) 706 #define SPSR_DAIF_MASK U(0xf) 707 708 #define SPSR_AIF_SHIFT U(6) 709 #define SPSR_AIF_MASK U(0x7) 710 711 #define SPSR_E_SHIFT U(9) 712 #define SPSR_E_MASK U(0x1) 713 #define SPSR_E_LITTLE U(0x0) 714 #define SPSR_E_BIG U(0x1) 715 716 #define SPSR_T_SHIFT U(5) 717 #define SPSR_T_MASK U(0x1) 718 #define SPSR_T_ARM U(0x0) 719 #define SPSR_T_THUMB U(0x1) 720 721 #define SPSR_M_SHIFT U(4) 722 #define SPSR_M_MASK U(0x1) 723 #define SPSR_M_AARCH64 U(0x0) 724 #define SPSR_M_AARCH32 U(0x1) 725 #define SPSR_M_EL2H U(0x9) 726 727 #define SPSR_EL_SHIFT U(2) 728 #define SPSR_EL_WIDTH U(2) 729 730 #define SPSR_SSBS_SHIFT_AARCH64 U(12) 731 #define SPSR_SSBS_BIT_AARCH64 (ULL(1) << SPSR_SSBS_SHIFT_AARCH64) 732 #define SPSR_SSBS_SHIFT_AARCH32 U(23) 733 #define SPSR_SSBS_BIT_AARCH32 (ULL(1) << SPSR_SSBS_SHIFT_AARCH32) 734 735 #define SPSR_PAN_BIT BIT_64(22) 736 737 #define SPSR_DIT_BIT BIT(24) 738 739 #define SPSR_TCO_BIT_AARCH64 BIT_64(25) 740 741 #define DISABLE_ALL_EXCEPTIONS \ 742 (DAIF_FIQ_BIT | DAIF_IRQ_BIT | DAIF_ABT_BIT | DAIF_DBG_BIT) 743 744 #define DISABLE_INTERRUPTS (DAIF_FIQ_BIT | DAIF_IRQ_BIT) 745 746 /* 747 * RMR_EL3 definitions 748 */ 749 #define RMR_EL3_RR_BIT (U(1) << 1) 750 #define RMR_EL3_AA64_BIT (U(1) << 0) 751 752 /* 753 * HI-VECTOR address for AArch32 state 754 */ 755 #define HI_VECTOR_BASE U(0xFFFF0000) 756 757 /* 758 * TCR definitions 759 */ 760 #define TCR_EL3_RES1 ((ULL(1) << 31) | (ULL(1) << 23)) 761 #define TCR_EL2_RES1 ((ULL(1) << 31) | (ULL(1) << 23)) 762 #define TCR_EL1_IPS_SHIFT U(32) 763 #define TCR_EL2_PS_SHIFT U(16) 764 #define TCR_EL3_PS_SHIFT U(16) 765 766 #define TCR_TxSZ_MIN ULL(16) 767 #define TCR_TxSZ_MAX ULL(39) 768 #define TCR_TxSZ_MAX_TTST ULL(48) 769 770 #define TCR_T0SZ_SHIFT U(0) 771 #define TCR_T1SZ_SHIFT U(16) 772 773 /* (internal) physical address size bits in EL3/EL1 */ 774 #define TCR_PS_BITS_4GB ULL(0x0) 775 #define TCR_PS_BITS_64GB ULL(0x1) 776 #define TCR_PS_BITS_1TB ULL(0x2) 777 #define TCR_PS_BITS_4TB ULL(0x3) 778 #define TCR_PS_BITS_16TB ULL(0x4) 779 #define TCR_PS_BITS_256TB ULL(0x5) 780 781 #define ADDR_MASK_48_TO_63 ULL(0xFFFF000000000000) 782 #define ADDR_MASK_44_TO_47 ULL(0x0000F00000000000) 783 #define ADDR_MASK_42_TO_43 ULL(0x00000C0000000000) 784 #define ADDR_MASK_40_TO_41 ULL(0x0000030000000000) 785 #define ADDR_MASK_36_TO_39 ULL(0x000000F000000000) 786 #define ADDR_MASK_32_TO_35 ULL(0x0000000F00000000) 787 788 #define TCR_RGN_INNER_NC (ULL(0x0) << 8) 789 #define TCR_RGN_INNER_WBA (ULL(0x1) << 8) 790 #define TCR_RGN_INNER_WT (ULL(0x2) << 8) 791 #define TCR_RGN_INNER_WBNA (ULL(0x3) << 8) 792 793 #define TCR_RGN_OUTER_NC (ULL(0x0) << 10) 794 #define TCR_RGN_OUTER_WBA (ULL(0x1) << 10) 795 #define TCR_RGN_OUTER_WT (ULL(0x2) << 10) 796 #define TCR_RGN_OUTER_WBNA (ULL(0x3) << 10) 797 798 #define TCR_SH_NON_SHAREABLE (ULL(0x0) << 12) 799 #define TCR_SH_OUTER_SHAREABLE (ULL(0x2) << 12) 800 #define TCR_SH_INNER_SHAREABLE (ULL(0x3) << 12) 801 802 #define TCR_RGN1_INNER_NC (ULL(0x0) << 24) 803 #define TCR_RGN1_INNER_WBA (ULL(0x1) << 24) 804 #define TCR_RGN1_INNER_WT (ULL(0x2) << 24) 805 #define TCR_RGN1_INNER_WBNA (ULL(0x3) << 24) 806 807 #define TCR_RGN1_OUTER_NC (ULL(0x0) << 26) 808 #define TCR_RGN1_OUTER_WBA (ULL(0x1) << 26) 809 #define TCR_RGN1_OUTER_WT (ULL(0x2) << 26) 810 #define TCR_RGN1_OUTER_WBNA (ULL(0x3) << 26) 811 812 #define TCR_SH1_NON_SHAREABLE (ULL(0x0) << 28) 813 #define TCR_SH1_OUTER_SHAREABLE (ULL(0x2) << 28) 814 #define TCR_SH1_INNER_SHAREABLE (ULL(0x3) << 28) 815 816 #define TCR_TG0_SHIFT U(14) 817 #define TCR_TG0_MASK ULL(3) 818 #define TCR_TG0_4K (ULL(0) << TCR_TG0_SHIFT) 819 #define TCR_TG0_64K (ULL(1) << TCR_TG0_SHIFT) 820 #define TCR_TG0_16K (ULL(2) << TCR_TG0_SHIFT) 821 822 #define TCR_TG1_SHIFT U(30) 823 #define TCR_TG1_MASK ULL(3) 824 #define TCR_TG1_16K (ULL(1) << TCR_TG1_SHIFT) 825 #define TCR_TG1_4K (ULL(2) << TCR_TG1_SHIFT) 826 #define TCR_TG1_64K (ULL(3) << TCR_TG1_SHIFT) 827 828 #define TCR_EPD0_BIT (ULL(1) << 7) 829 #define TCR_EPD1_BIT (ULL(1) << 23) 830 831 #define MODE_SP_SHIFT U(0x0) 832 #define MODE_SP_MASK U(0x1) 833 #define MODE_SP_EL0 U(0x0) 834 #define MODE_SP_ELX U(0x1) 835 836 #define MODE_RW_SHIFT U(0x4) 837 #define MODE_RW_MASK U(0x1) 838 #define MODE_RW_64 U(0x0) 839 #define MODE_RW_32 U(0x1) 840 841 #define MODE_EL_SHIFT U(0x2) 842 #define MODE_EL_MASK U(0x3) 843 #define MODE_EL_WIDTH U(0x2) 844 #define MODE_EL3 U(0x3) 845 #define MODE_EL2 U(0x2) 846 #define MODE_EL1 U(0x1) 847 #define MODE_EL0 U(0x0) 848 849 #define MODE32_SHIFT U(0) 850 #define MODE32_MASK U(0xf) 851 #define MODE32_usr U(0x0) 852 #define MODE32_fiq U(0x1) 853 #define MODE32_irq U(0x2) 854 #define MODE32_svc U(0x3) 855 #define MODE32_mon U(0x6) 856 #define MODE32_abt U(0x7) 857 #define MODE32_hyp U(0xa) 858 #define MODE32_und U(0xb) 859 #define MODE32_sys U(0xf) 860 861 #define GET_RW(mode) (((mode) >> MODE_RW_SHIFT) & MODE_RW_MASK) 862 #define GET_EL(mode) (((mode) >> MODE_EL_SHIFT) & MODE_EL_MASK) 863 #define GET_SP(mode) (((mode) >> MODE_SP_SHIFT) & MODE_SP_MASK) 864 #define GET_M32(mode) (((mode) >> MODE32_SHIFT) & MODE32_MASK) 865 866 #define SPSR_64(el, sp, daif) \ 867 (((MODE_RW_64 << MODE_RW_SHIFT) | \ 868 (((el) & MODE_EL_MASK) << MODE_EL_SHIFT) | \ 869 (((sp) & MODE_SP_MASK) << MODE_SP_SHIFT) | \ 870 (((daif) & SPSR_DAIF_MASK) << SPSR_DAIF_SHIFT)) & \ 871 (~(SPSR_SSBS_BIT_AARCH64))) 872 873 #define SPSR_MODE32(mode, isa, endian, aif) \ 874 (((MODE_RW_32 << MODE_RW_SHIFT) | \ 875 (((mode) & MODE32_MASK) << MODE32_SHIFT) | \ 876 (((isa) & SPSR_T_MASK) << SPSR_T_SHIFT) | \ 877 (((endian) & SPSR_E_MASK) << SPSR_E_SHIFT) | \ 878 (((aif) & SPSR_AIF_MASK) << SPSR_AIF_SHIFT)) & \ 879 (~(SPSR_SSBS_BIT_AARCH32))) 880 881 /* 882 * TTBR Definitions 883 */ 884 #define TTBR_CNP_BIT ULL(0x1) 885 886 /* 887 * CTR_EL0 definitions 888 */ 889 #define CTR_CWG_SHIFT U(24) 890 #define CTR_CWG_MASK U(0xf) 891 #define CTR_ERG_SHIFT U(20) 892 #define CTR_ERG_MASK U(0xf) 893 #define CTR_DMINLINE_SHIFT U(16) 894 #define CTR_DMINLINE_MASK U(0xf) 895 #define CTR_L1IP_SHIFT U(14) 896 #define CTR_L1IP_MASK U(0x3) 897 #define CTR_IMINLINE_SHIFT U(0) 898 #define CTR_IMINLINE_MASK U(0xf) 899 900 #define MAX_CACHE_LINE_SIZE U(0x800) /* 2KB */ 901 902 /* Physical timer control register bit fields shifts and masks */ 903 #define CNTP_CTL_ENABLE_SHIFT U(0) 904 #define CNTP_CTL_IMASK_SHIFT U(1) 905 #define CNTP_CTL_ISTATUS_SHIFT U(2) 906 907 #define CNTP_CTL_ENABLE_MASK U(1) 908 #define CNTP_CTL_IMASK_MASK U(1) 909 #define CNTP_CTL_ISTATUS_MASK U(1) 910 911 /* Physical timer control macros */ 912 #define CNTP_CTL_ENABLE_BIT (U(1) << CNTP_CTL_ENABLE_SHIFT) 913 #define CNTP_CTL_IMASK_BIT (U(1) << CNTP_CTL_IMASK_SHIFT) 914 915 /* Exception Syndrome register bits and bobs */ 916 #define ESR_EC_SHIFT U(26) 917 #define ESR_EC_MASK U(0x3f) 918 #define ESR_EC_LENGTH U(6) 919 #define ESR_ISS_SHIFT U(0) 920 #define ESR_ISS_LENGTH U(25) 921 #define EC_UNKNOWN U(0x0) 922 #define EC_WFE_WFI U(0x1) 923 #define EC_AARCH32_CP15_MRC_MCR U(0x3) 924 #define EC_AARCH32_CP15_MRRC_MCRR U(0x4) 925 #define EC_AARCH32_CP14_MRC_MCR U(0x5) 926 #define EC_AARCH32_CP14_LDC_STC U(0x6) 927 #define EC_FP_SIMD U(0x7) 928 #define EC_AARCH32_CP10_MRC U(0x8) 929 #define EC_AARCH32_CP14_MRRC_MCRR U(0xc) 930 #define EC_ILLEGAL U(0xe) 931 #define EC_AARCH32_SVC U(0x11) 932 #define EC_AARCH32_HVC U(0x12) 933 #define EC_AARCH32_SMC U(0x13) 934 #define EC_AARCH64_SVC U(0x15) 935 #define EC_AARCH64_HVC U(0x16) 936 #define EC_AARCH64_SMC U(0x17) 937 #define EC_AARCH64_SYS U(0x18) 938 #define EC_IABORT_LOWER_EL U(0x20) 939 #define EC_IABORT_CUR_EL U(0x21) 940 #define EC_PC_ALIGN U(0x22) 941 #define EC_DABORT_LOWER_EL U(0x24) 942 #define EC_DABORT_CUR_EL U(0x25) 943 #define EC_SP_ALIGN U(0x26) 944 #define EC_AARCH32_FP U(0x28) 945 #define EC_AARCH64_FP U(0x2c) 946 #define EC_SERROR U(0x2f) 947 #define EC_BRK U(0x3c) 948 949 /* 950 * External Abort bit in Instruction and Data Aborts synchronous exception 951 * syndromes. 952 */ 953 #define ESR_ISS_EABORT_EA_BIT U(9) 954 955 #define EC_BITS(x) (((x) >> ESR_EC_SHIFT) & ESR_EC_MASK) 956 957 /* Reset bit inside the Reset management register for EL3 (RMR_EL3) */ 958 #define RMR_RESET_REQUEST_SHIFT U(0x1) 959 #define RMR_WARM_RESET_CPU (U(1) << RMR_RESET_REQUEST_SHIFT) 960 961 /******************************************************************************* 962 * Definitions of register offsets, fields and macros for CPU system 963 * instructions. 964 ******************************************************************************/ 965 966 #define TLBI_ADDR_SHIFT U(12) 967 #define TLBI_ADDR_MASK ULL(0x00000FFFFFFFFFFF) 968 #define TLBI_ADDR(x) (((x) >> TLBI_ADDR_SHIFT) & TLBI_ADDR_MASK) 969 970 /******************************************************************************* 971 * Definitions of register offsets and fields in the CNTCTLBase Frame of the 972 * system level implementation of the Generic Timer. 973 ******************************************************************************/ 974 #define CNTCTLBASE_CNTFRQ U(0x0) 975 #define CNTNSAR U(0x4) 976 #define CNTNSAR_NS_SHIFT(x) (x) 977 978 #define CNTACR_BASE(x) (U(0x40) + ((x) << 2)) 979 #define CNTACR_RPCT_SHIFT U(0x0) 980 #define CNTACR_RVCT_SHIFT U(0x1) 981 #define CNTACR_RFRQ_SHIFT U(0x2) 982 #define CNTACR_RVOFF_SHIFT U(0x3) 983 #define CNTACR_RWVT_SHIFT U(0x4) 984 #define CNTACR_RWPT_SHIFT U(0x5) 985 986 /******************************************************************************* 987 * Definitions of register offsets and fields in the CNTBaseN Frame of the 988 * system level implementation of the Generic Timer. 989 ******************************************************************************/ 990 /* Physical Count register. */ 991 #define CNTPCT_LO U(0x0) 992 /* Counter Frequency register. */ 993 #define CNTBASEN_CNTFRQ U(0x10) 994 /* Physical Timer CompareValue register. */ 995 #define CNTP_CVAL_LO U(0x20) 996 /* Physical Timer Control register. */ 997 #define CNTP_CTL U(0x2c) 998 999 /* PMCR_EL0 definitions */ 1000 #define PMCR_EL0_RESET_VAL U(0x0) 1001 #define PMCR_EL0_N_SHIFT U(11) 1002 #define PMCR_EL0_N_MASK U(0x1f) 1003 #define PMCR_EL0_N_BITS (PMCR_EL0_N_MASK << PMCR_EL0_N_SHIFT) 1004 #define PMCR_EL0_LP_BIT (U(1) << 7) 1005 #define PMCR_EL0_LC_BIT (U(1) << 6) 1006 #define PMCR_EL0_DP_BIT (U(1) << 5) 1007 #define PMCR_EL0_X_BIT (U(1) << 4) 1008 #define PMCR_EL0_D_BIT (U(1) << 3) 1009 #define PMCR_EL0_C_BIT (U(1) << 2) 1010 #define PMCR_EL0_P_BIT (U(1) << 1) 1011 #define PMCR_EL0_E_BIT (U(1) << 0) 1012 1013 /******************************************************************************* 1014 * Definitions for system register interface to SVE 1015 ******************************************************************************/ 1016 #define ZCR_EL3 S3_6_C1_C2_0 1017 #define ZCR_EL2 S3_4_C1_C2_0 1018 1019 /* ZCR_EL3 definitions */ 1020 #define ZCR_EL3_LEN_MASK U(0xf) 1021 1022 /* ZCR_EL2 definitions */ 1023 #define ZCR_EL2_LEN_MASK U(0xf) 1024 1025 /******************************************************************************* 1026 * Definitions for system register interface to SME as needed in EL3 1027 ******************************************************************************/ 1028 #define ID_AA64SMFR0_EL1 S3_0_C0_C4_5 1029 #define SMCR_EL3 S3_6_C1_C2_6 1030 1031 /* ID_AA64SMFR0_EL1 definitions */ 1032 #define ID_AA64SMFR0_EL1_SME_FA64_SHIFT U(63) 1033 #define ID_AA64SMFR0_EL1_SME_FA64_MASK U(0x1) 1034 #define ID_AA64SMFR0_EL1_SME_FA64_SUPPORTED U(0x1) 1035 #define ID_AA64SMFR0_EL1_SME_VER_SHIFT U(55) 1036 #define ID_AA64SMFR0_EL1_SME_VER_MASK ULL(0xf) 1037 #define ID_AA64SMFR0_EL1_SME_INST_SUPPORTED ULL(0x0) 1038 #define ID_AA64SMFR0_EL1_SME2_INST_SUPPORTED ULL(0x1) 1039 1040 /* SMCR_ELx definitions */ 1041 #define SMCR_ELX_LEN_SHIFT U(0) 1042 #define SMCR_ELX_LEN_MAX U(0x1ff) 1043 #define SMCR_ELX_FA64_BIT (U(1) << 31) 1044 #define SMCR_ELX_EZT0_BIT (U(1) << 30) 1045 1046 /******************************************************************************* 1047 * Definitions of MAIR encodings for device and normal memory 1048 ******************************************************************************/ 1049 /* 1050 * MAIR encodings for device memory attributes. 1051 */ 1052 #define MAIR_DEV_nGnRnE ULL(0x0) 1053 #define MAIR_DEV_nGnRE ULL(0x4) 1054 #define MAIR_DEV_nGRE ULL(0x8) 1055 #define MAIR_DEV_GRE ULL(0xc) 1056 1057 /* 1058 * MAIR encodings for normal memory attributes. 1059 * 1060 * Cache Policy 1061 * WT: Write Through 1062 * WB: Write Back 1063 * NC: Non-Cacheable 1064 * 1065 * Transient Hint 1066 * NTR: Non-Transient 1067 * TR: Transient 1068 * 1069 * Allocation Policy 1070 * RA: Read Allocate 1071 * WA: Write Allocate 1072 * RWA: Read and Write Allocate 1073 * NA: No Allocation 1074 */ 1075 #define MAIR_NORM_WT_TR_WA ULL(0x1) 1076 #define MAIR_NORM_WT_TR_RA ULL(0x2) 1077 #define MAIR_NORM_WT_TR_RWA ULL(0x3) 1078 #define MAIR_NORM_NC ULL(0x4) 1079 #define MAIR_NORM_WB_TR_WA ULL(0x5) 1080 #define MAIR_NORM_WB_TR_RA ULL(0x6) 1081 #define MAIR_NORM_WB_TR_RWA ULL(0x7) 1082 #define MAIR_NORM_WT_NTR_NA ULL(0x8) 1083 #define MAIR_NORM_WT_NTR_WA ULL(0x9) 1084 #define MAIR_NORM_WT_NTR_RA ULL(0xa) 1085 #define MAIR_NORM_WT_NTR_RWA ULL(0xb) 1086 #define MAIR_NORM_WB_NTR_NA ULL(0xc) 1087 #define MAIR_NORM_WB_NTR_WA ULL(0xd) 1088 #define MAIR_NORM_WB_NTR_RA ULL(0xe) 1089 #define MAIR_NORM_WB_NTR_RWA ULL(0xf) 1090 1091 #define MAIR_NORM_OUTER_SHIFT U(4) 1092 1093 #define MAKE_MAIR_NORMAL_MEMORY(inner, outer) \ 1094 ((inner) | ((outer) << MAIR_NORM_OUTER_SHIFT)) 1095 1096 /* PAR_EL1 fields */ 1097 #define PAR_F_SHIFT U(0) 1098 #define PAR_F_MASK ULL(0x1) 1099 #define PAR_ADDR_SHIFT U(12) 1100 #define PAR_ADDR_MASK (BIT(40) - ULL(1)) /* 40-bits-wide page address */ 1101 1102 /******************************************************************************* 1103 * Definitions for system register interface to SPE 1104 ******************************************************************************/ 1105 #define PMBLIMITR_EL1 S3_0_C9_C10_0 1106 1107 /******************************************************************************* 1108 * Definitions for system register interface, shifts and masks for MPAM 1109 ******************************************************************************/ 1110 #define MPAMIDR_EL1 S3_0_C10_C4_4 1111 #define MPAM2_EL2 S3_4_C10_C5_0 1112 #define MPAMHCR_EL2 S3_4_C10_C4_0 1113 #define MPAM3_EL3 S3_6_C10_C5_0 1114 1115 #define MPAMIDR_EL1_VPMR_MAX_SHIFT ULL(18) 1116 #define MPAMIDR_EL1_VPMR_MAX_MASK ULL(0x7) 1117 /******************************************************************************* 1118 * Definitions for system register interface to AMU for FEAT_AMUv1 1119 ******************************************************************************/ 1120 #define AMCR_EL0 S3_3_C13_C2_0 1121 #define AMCFGR_EL0 S3_3_C13_C2_1 1122 #define AMCGCR_EL0 S3_3_C13_C2_2 1123 #define AMUSERENR_EL0 S3_3_C13_C2_3 1124 #define AMCNTENCLR0_EL0 S3_3_C13_C2_4 1125 #define AMCNTENSET0_EL0 S3_3_C13_C2_5 1126 #define AMCNTENCLR1_EL0 S3_3_C13_C3_0 1127 #define AMCNTENSET1_EL0 S3_3_C13_C3_1 1128 1129 /* Activity Monitor Group 0 Event Counter Registers */ 1130 #define AMEVCNTR00_EL0 S3_3_C13_C4_0 1131 #define AMEVCNTR01_EL0 S3_3_C13_C4_1 1132 #define AMEVCNTR02_EL0 S3_3_C13_C4_2 1133 #define AMEVCNTR03_EL0 S3_3_C13_C4_3 1134 1135 /* Activity Monitor Group 0 Event Type Registers */ 1136 #define AMEVTYPER00_EL0 S3_3_C13_C6_0 1137 #define AMEVTYPER01_EL0 S3_3_C13_C6_1 1138 #define AMEVTYPER02_EL0 S3_3_C13_C6_2 1139 #define AMEVTYPER03_EL0 S3_3_C13_C6_3 1140 1141 /* Activity Monitor Group 1 Event Counter Registers */ 1142 #define AMEVCNTR10_EL0 S3_3_C13_C12_0 1143 #define AMEVCNTR11_EL0 S3_3_C13_C12_1 1144 #define AMEVCNTR12_EL0 S3_3_C13_C12_2 1145 #define AMEVCNTR13_EL0 S3_3_C13_C12_3 1146 #define AMEVCNTR14_EL0 S3_3_C13_C12_4 1147 #define AMEVCNTR15_EL0 S3_3_C13_C12_5 1148 #define AMEVCNTR16_EL0 S3_3_C13_C12_6 1149 #define AMEVCNTR17_EL0 S3_3_C13_C12_7 1150 #define AMEVCNTR18_EL0 S3_3_C13_C13_0 1151 #define AMEVCNTR19_EL0 S3_3_C13_C13_1 1152 #define AMEVCNTR1A_EL0 S3_3_C13_C13_2 1153 #define AMEVCNTR1B_EL0 S3_3_C13_C13_3 1154 #define AMEVCNTR1C_EL0 S3_3_C13_C13_4 1155 #define AMEVCNTR1D_EL0 S3_3_C13_C13_5 1156 #define AMEVCNTR1E_EL0 S3_3_C13_C13_6 1157 #define AMEVCNTR1F_EL0 S3_3_C13_C13_7 1158 1159 /* Activity Monitor Group 1 Event Type Registers */ 1160 #define AMEVTYPER10_EL0 S3_3_C13_C14_0 1161 #define AMEVTYPER11_EL0 S3_3_C13_C14_1 1162 #define AMEVTYPER12_EL0 S3_3_C13_C14_2 1163 #define AMEVTYPER13_EL0 S3_3_C13_C14_3 1164 #define AMEVTYPER14_EL0 S3_3_C13_C14_4 1165 #define AMEVTYPER15_EL0 S3_3_C13_C14_5 1166 #define AMEVTYPER16_EL0 S3_3_C13_C14_6 1167 #define AMEVTYPER17_EL0 S3_3_C13_C14_7 1168 #define AMEVTYPER18_EL0 S3_3_C13_C15_0 1169 #define AMEVTYPER19_EL0 S3_3_C13_C15_1 1170 #define AMEVTYPER1A_EL0 S3_3_C13_C15_2 1171 #define AMEVTYPER1B_EL0 S3_3_C13_C15_3 1172 #define AMEVTYPER1C_EL0 S3_3_C13_C15_4 1173 #define AMEVTYPER1D_EL0 S3_3_C13_C15_5 1174 #define AMEVTYPER1E_EL0 S3_3_C13_C15_6 1175 #define AMEVTYPER1F_EL0 S3_3_C13_C15_7 1176 1177 /* AMCNTENSET0_EL0 definitions */ 1178 #define AMCNTENSET0_EL0_Pn_SHIFT U(0) 1179 #define AMCNTENSET0_EL0_Pn_MASK ULL(0xffff) 1180 1181 /* AMCNTENSET1_EL0 definitions */ 1182 #define AMCNTENSET1_EL0_Pn_SHIFT U(0) 1183 #define AMCNTENSET1_EL0_Pn_MASK ULL(0xffff) 1184 1185 /* AMCNTENCLR0_EL0 definitions */ 1186 #define AMCNTENCLR0_EL0_Pn_SHIFT U(0) 1187 #define AMCNTENCLR0_EL0_Pn_MASK ULL(0xffff) 1188 1189 /* AMCNTENCLR1_EL0 definitions */ 1190 #define AMCNTENCLR1_EL0_Pn_SHIFT U(0) 1191 #define AMCNTENCLR1_EL0_Pn_MASK ULL(0xffff) 1192 1193 /* AMCFGR_EL0 definitions */ 1194 #define AMCFGR_EL0_NCG_SHIFT U(28) 1195 #define AMCFGR_EL0_NCG_MASK U(0xf) 1196 #define AMCFGR_EL0_N_SHIFT U(0) 1197 #define AMCFGR_EL0_N_MASK U(0xff) 1198 1199 /* AMCGCR_EL0 definitions */ 1200 #define AMCGCR_EL0_CG0NC_SHIFT U(0) 1201 #define AMCGCR_EL0_CG0NC_MASK U(0xff) 1202 #define AMCGCR_EL0_CG1NC_SHIFT U(8) 1203 #define AMCGCR_EL0_CG1NC_MASK U(0xff) 1204 1205 /* MPAM register definitions */ 1206 #define MPAM3_EL3_MPAMEN_BIT (ULL(1) << 63) 1207 #define MPAMHCR_EL2_TRAP_MPAMIDR_EL1 (ULL(1) << 31) 1208 1209 #define MPAM2_EL2_TRAPMPAM0EL1 (ULL(1) << 49) 1210 #define MPAM2_EL2_TRAPMPAM1EL1 (ULL(1) << 48) 1211 1212 #define MPAMIDR_HAS_HCR_BIT (ULL(1) << 17) 1213 1214 /******************************************************************************* 1215 * Definitions for system register interface to AMU for FEAT_AMUv1p1 1216 ******************************************************************************/ 1217 1218 /* Definition for register defining which virtual offsets are implemented. */ 1219 #define AMCG1IDR_EL0 S3_3_C13_C2_6 1220 #define AMCG1IDR_CTR_MASK ULL(0xffff) 1221 #define AMCG1IDR_CTR_SHIFT U(0) 1222 #define AMCG1IDR_VOFF_MASK ULL(0xffff) 1223 #define AMCG1IDR_VOFF_SHIFT U(16) 1224 1225 /* New bit added to AMCR_EL0 */ 1226 #define AMCR_CG1RZ_SHIFT U(17) 1227 #define AMCR_CG1RZ_BIT (ULL(0x1) << AMCR_CG1RZ_SHIFT) 1228 1229 /* 1230 * Definitions for virtual offset registers for architected activity monitor 1231 * event counters. 1232 * AMEVCNTVOFF01_EL2 intentionally left undefined, as it does not exist. 1233 */ 1234 #define AMEVCNTVOFF00_EL2 S3_4_C13_C8_0 1235 #define AMEVCNTVOFF02_EL2 S3_4_C13_C8_2 1236 #define AMEVCNTVOFF03_EL2 S3_4_C13_C8_3 1237 1238 /* 1239 * Definitions for virtual offset registers for auxiliary activity monitor event 1240 * counters. 1241 */ 1242 #define AMEVCNTVOFF10_EL2 S3_4_C13_C10_0 1243 #define AMEVCNTVOFF11_EL2 S3_4_C13_C10_1 1244 #define AMEVCNTVOFF12_EL2 S3_4_C13_C10_2 1245 #define AMEVCNTVOFF13_EL2 S3_4_C13_C10_3 1246 #define AMEVCNTVOFF14_EL2 S3_4_C13_C10_4 1247 #define AMEVCNTVOFF15_EL2 S3_4_C13_C10_5 1248 #define AMEVCNTVOFF16_EL2 S3_4_C13_C10_6 1249 #define AMEVCNTVOFF17_EL2 S3_4_C13_C10_7 1250 #define AMEVCNTVOFF18_EL2 S3_4_C13_C11_0 1251 #define AMEVCNTVOFF19_EL2 S3_4_C13_C11_1 1252 #define AMEVCNTVOFF1A_EL2 S3_4_C13_C11_2 1253 #define AMEVCNTVOFF1B_EL2 S3_4_C13_C11_3 1254 #define AMEVCNTVOFF1C_EL2 S3_4_C13_C11_4 1255 #define AMEVCNTVOFF1D_EL2 S3_4_C13_C11_5 1256 #define AMEVCNTVOFF1E_EL2 S3_4_C13_C11_6 1257 #define AMEVCNTVOFF1F_EL2 S3_4_C13_C11_7 1258 1259 /******************************************************************************* 1260 * Realm management extension register definitions 1261 ******************************************************************************/ 1262 #define GPCCR_EL3 S3_6_C2_C1_6 1263 #define GPTBR_EL3 S3_6_C2_C1_4 1264 1265 #define SCXTNUM_EL2 S3_4_C13_C0_7 1266 1267 /******************************************************************************* 1268 * RAS system registers 1269 ******************************************************************************/ 1270 #define DISR_EL1 S3_0_C12_C1_1 1271 #define DISR_A_BIT U(31) 1272 1273 #define ERRIDR_EL1 S3_0_C5_C3_0 1274 #define ERRIDR_MASK U(0xffff) 1275 1276 #define ERRSELR_EL1 S3_0_C5_C3_1 1277 1278 /* System register access to Standard Error Record registers */ 1279 #define ERXFR_EL1 S3_0_C5_C4_0 1280 #define ERXCTLR_EL1 S3_0_C5_C4_1 1281 #define ERXSTATUS_EL1 S3_0_C5_C4_2 1282 #define ERXADDR_EL1 S3_0_C5_C4_3 1283 #define ERXPFGF_EL1 S3_0_C5_C4_4 1284 #define ERXPFGCTL_EL1 S3_0_C5_C4_5 1285 #define ERXPFGCDN_EL1 S3_0_C5_C4_6 1286 #define ERXMISC0_EL1 S3_0_C5_C5_0 1287 #define ERXMISC1_EL1 S3_0_C5_C5_1 1288 1289 #define ERXCTLR_ED_SHIFT U(0) 1290 #define ERXCTLR_ED_BIT (U(1) << ERXCTLR_ED_SHIFT) 1291 #define ERXCTLR_UE_BIT (U(1) << 4) 1292 1293 #define ERXPFGCTL_UC_BIT (U(1) << 1) 1294 #define ERXPFGCTL_UEU_BIT (U(1) << 2) 1295 #define ERXPFGCTL_CDEN_BIT (U(1) << 31) 1296 1297 /******************************************************************************* 1298 * Armv8.3 Pointer Authentication Registers 1299 ******************************************************************************/ 1300 #define APIAKeyLo_EL1 S3_0_C2_C1_0 1301 #define APIAKeyHi_EL1 S3_0_C2_C1_1 1302 #define APIBKeyLo_EL1 S3_0_C2_C1_2 1303 #define APIBKeyHi_EL1 S3_0_C2_C1_3 1304 #define APDAKeyLo_EL1 S3_0_C2_C2_0 1305 #define APDAKeyHi_EL1 S3_0_C2_C2_1 1306 #define APDBKeyLo_EL1 S3_0_C2_C2_2 1307 #define APDBKeyHi_EL1 S3_0_C2_C2_3 1308 #define APGAKeyLo_EL1 S3_0_C2_C3_0 1309 #define APGAKeyHi_EL1 S3_0_C2_C3_1 1310 1311 /******************************************************************************* 1312 * Armv8.4 Data Independent Timing Registers 1313 ******************************************************************************/ 1314 #define DIT S3_3_C4_C2_5 1315 #define DIT_BIT BIT(24) 1316 1317 /******************************************************************************* 1318 * Armv8.5 - new MSR encoding to directly access PSTATE.SSBS field 1319 ******************************************************************************/ 1320 #define SSBS S3_3_C4_C2_6 1321 1322 /******************************************************************************* 1323 * Armv8.5 - Memory Tagging Extension Registers 1324 ******************************************************************************/ 1325 #define TFSRE0_EL1 S3_0_C5_C6_1 1326 #define TFSR_EL1 S3_0_C5_C6_0 1327 #define RGSR_EL1 S3_0_C1_C0_5 1328 #define GCR_EL1 S3_0_C1_C0_6 1329 1330 /******************************************************************************* 1331 * Armv8.5 - Random Number Generator Registers 1332 ******************************************************************************/ 1333 #define RNDR S3_3_C2_C4_0 1334 #define RNDRRS S3_3_C2_C4_1 1335 1336 /******************************************************************************* 1337 * FEAT_HCX - Extended Hypervisor Configuration Register 1338 ******************************************************************************/ 1339 #define HCRX_EL2 S3_4_C1_C2_2 1340 #define HCRX_EL2_MSCEn_BIT (UL(1) << 11) 1341 #define HCRX_EL2_MCE2_BIT (UL(1) << 10) 1342 #define HCRX_EL2_CMOW_BIT (UL(1) << 9) 1343 #define HCRX_EL2_VFNMI_BIT (UL(1) << 8) 1344 #define HCRX_EL2_VINMI_BIT (UL(1) << 7) 1345 #define HCRX_EL2_TALLINT_BIT (UL(1) << 6) 1346 #define HCRX_EL2_SMPME_BIT (UL(1) << 5) 1347 #define HCRX_EL2_FGTnXS_BIT (UL(1) << 4) 1348 #define HCRX_EL2_FnXS_BIT (UL(1) << 3) 1349 #define HCRX_EL2_EnASR_BIT (UL(1) << 2) 1350 #define HCRX_EL2_EnALS_BIT (UL(1) << 1) 1351 #define HCRX_EL2_EnAS0_BIT (UL(1) << 0) 1352 #define HCRX_EL2_INIT_VAL ULL(0x0) 1353 1354 /******************************************************************************* 1355 * FEAT_TCR2 - Extended Translation Control Register 1356 ******************************************************************************/ 1357 #define TCR2_EL2 S3_4_C2_C0_3 1358 1359 /******************************************************************************* 1360 * Permission indirection and overlay 1361 ******************************************************************************/ 1362 1363 #define PIRE0_EL2 S3_4_C10_C2_2 1364 #define PIR_EL2 S3_4_C10_C2_3 1365 #define POR_EL2 S3_4_C10_C2_4 1366 #define S2PIR_EL2 S3_4_C10_C2_5 1367 1368 /******************************************************************************* 1369 * FEAT_GCS - Guarded Control Stack Registers 1370 ******************************************************************************/ 1371 #define GCSCR_EL2 S3_4_C2_C5_0 1372 #define GCSPR_EL2 S3_4_C2_C5_1 1373 1374 /******************************************************************************* 1375 * Definitions for DynamicIQ Shared Unit registers 1376 ******************************************************************************/ 1377 #define CLUSTERPWRDN_EL1 S3_0_c15_c3_6 1378 1379 /* CLUSTERPWRDN_EL1 register definitions */ 1380 #define DSU_CLUSTER_PWR_OFF 0 1381 #define DSU_CLUSTER_PWR_ON 1 1382 #define DSU_CLUSTER_PWR_MASK U(1) 1383 1384 /******************************************************************************* 1385 * Definitions for CPU Power/Performance Management registers 1386 ******************************************************************************/ 1387 1388 #define CPUPPMCR_EL3 S3_6_C15_C2_0 1389 #define CPUPPMCR_EL3_MPMMPINCTL_SHIFT UINT64_C(0) 1390 #define CPUPPMCR_EL3_MPMMPINCTL_MASK UINT64_C(0x1) 1391 1392 #define CPUMPMMCR_EL3 S3_6_C15_C2_1 1393 #define CPUMPMMCR_EL3_MPMM_EN_SHIFT UINT64_C(0) 1394 #define CPUMPMMCR_EL3_MPMM_EN_MASK UINT64_C(0x1) 1395 1396 /* alternative system register encoding for the "sb" speculation barrier */ 1397 #define SYSREG_SB S0_3_C3_C0_7 1398 1399 #endif /* ARCH_H */ 1400
