1 /* 2 * Copyright 2021 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 */ 7 #include <cci.h> 8 #include <common/debug.h> 9 #include <ls_interconnect.h> 10 #include <mmio.h> 11 12 #include <platform_def.h> 13 erratum_a008850_early(void)14void erratum_a008850_early(void) 15 { 16 /* part 1 of 2 */ 17 uintptr_t cci_base = NXP_CCI_ADDR; 18 uint32_t val = mmio_read_32(cci_base + CTRL_OVERRIDE_REG); 19 20 /* enabling forced barrier termination on CCI400 */ 21 mmio_write_32(cci_base + CTRL_OVERRIDE_REG, 22 (val | CCI_TERMINATE_BARRIER_TX)); 23 24 } 25 erratum_a008850_post(void)26void erratum_a008850_post(void) 27 { 28 /* part 2 of 2 */ 29 uintptr_t cci_base = NXP_CCI_ADDR; 30 uint32_t val = mmio_read_32(cci_base + CTRL_OVERRIDE_REG); 31 32 /* Clear the BARRIER_TX bit */ 33 val = val & ~(CCI_TERMINATE_BARRIER_TX); 34 35 /* 36 * Disable barrier termination on CCI400, allowing 37 * barriers to propagate across CCI 38 */ 39 mmio_write_32(cci_base + CTRL_OVERRIDE_REG, val); 40 41 INFO("SoC workaround for Errata A008850 Post-Phase was applied\n"); 42 } 43
