1 /*
2  * Copy paste of the whole nrf52_bitfields.h
3  * (from the nrfx mdk) to be used by the HW models
4  *
5  * SPDX-License-Identifier: BSD-3-Clause
6  */
7 /*
8 
9 Copyright (c) 2010 - 2017, Nordic Semiconductor ASA All rights reserved.
10 
11 Redistribution and use in source and binary forms, with or without
12 modification, are permitted provided that the following conditions are met:
13 
14 1. Redistributions of source code must retain the above copyright notice, this
15    list of conditions and the following disclaimer.
16 
17 2. Redistributions in binary form must reproduce the above copyright
18    notice, this list of conditions and the following disclaimer in the
19    documentation and/or other materials provided with the distribution.
20 
21 3. Neither the name of Nordic Semiconductor ASA nor the names of its
22    contributors may be used to endorse or promote products derived from this
23    software without specific prior written permission.
24 
25 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
26 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
27 IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE
28 ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
29 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
30 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
31 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
32 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
33 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
35 POSSIBILITY OF SUCH DAMAGE.
36 
37 */
38 
39 #ifndef __NRF52_BITS_H
40 #define __NRF52_BITS_H
41 
42 /*lint ++flb "Enter library region" */
43 
44 /* Peripheral: AAR */
45 /* Description: Accelerated Address Resolver */
46 
47 /* Register: AAR_INTENSET */
48 /* Description: Enable interrupt */
49 
50 /* Bit 2 : Write '1' to Enable interrupt for NOTRESOLVED event */
51 #define AAR_INTENSET_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */
52 #define AAR_INTENSET_NOTRESOLVED_Msk (0x1UL << AAR_INTENSET_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */
53 #define AAR_INTENSET_NOTRESOLVED_Disabled (0UL) /*!< Read: Disabled */
54 #define AAR_INTENSET_NOTRESOLVED_Enabled (1UL) /*!< Read: Enabled */
55 #define AAR_INTENSET_NOTRESOLVED_Set (1UL) /*!< Enable */
56 
57 /* Bit 1 : Write '1' to Enable interrupt for RESOLVED event */
58 #define AAR_INTENSET_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */
59 #define AAR_INTENSET_RESOLVED_Msk (0x1UL << AAR_INTENSET_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */
60 #define AAR_INTENSET_RESOLVED_Disabled (0UL) /*!< Read: Disabled */
61 #define AAR_INTENSET_RESOLVED_Enabled (1UL) /*!< Read: Enabled */
62 #define AAR_INTENSET_RESOLVED_Set (1UL) /*!< Enable */
63 
64 /* Bit 0 : Write '1' to Enable interrupt for END event */
65 #define AAR_INTENSET_END_Pos (0UL) /*!< Position of END field. */
66 #define AAR_INTENSET_END_Msk (0x1UL << AAR_INTENSET_END_Pos) /*!< Bit mask of END field. */
67 #define AAR_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
68 #define AAR_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
69 #define AAR_INTENSET_END_Set (1UL) /*!< Enable */
70 
71 /* Register: AAR_INTENCLR */
72 /* Description: Disable interrupt */
73 
74 /* Bit 2 : Write '1' to Disable interrupt for NOTRESOLVED event */
75 #define AAR_INTENCLR_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */
76 #define AAR_INTENCLR_NOTRESOLVED_Msk (0x1UL << AAR_INTENCLR_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */
77 #define AAR_INTENCLR_NOTRESOLVED_Disabled (0UL) /*!< Read: Disabled */
78 #define AAR_INTENCLR_NOTRESOLVED_Enabled (1UL) /*!< Read: Enabled */
79 #define AAR_INTENCLR_NOTRESOLVED_Clear (1UL) /*!< Disable */
80 
81 /* Bit 1 : Write '1' to Disable interrupt for RESOLVED event */
82 #define AAR_INTENCLR_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */
83 #define AAR_INTENCLR_RESOLVED_Msk (0x1UL << AAR_INTENCLR_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */
84 #define AAR_INTENCLR_RESOLVED_Disabled (0UL) /*!< Read: Disabled */
85 #define AAR_INTENCLR_RESOLVED_Enabled (1UL) /*!< Read: Enabled */
86 #define AAR_INTENCLR_RESOLVED_Clear (1UL) /*!< Disable */
87 
88 /* Bit 0 : Write '1' to Disable interrupt for END event */
89 #define AAR_INTENCLR_END_Pos (0UL) /*!< Position of END field. */
90 #define AAR_INTENCLR_END_Msk (0x1UL << AAR_INTENCLR_END_Pos) /*!< Bit mask of END field. */
91 #define AAR_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
92 #define AAR_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
93 #define AAR_INTENCLR_END_Clear (1UL) /*!< Disable */
94 
95 /* Register: AAR_STATUS */
96 /* Description: Resolution status */
97 
98 /* Bits 3..0 : The IRK that was used last time an address was resolved */
99 #define AAR_STATUS_STATUS_Pos (0UL) /*!< Position of STATUS field. */
100 #define AAR_STATUS_STATUS_Msk (0xFUL << AAR_STATUS_STATUS_Pos) /*!< Bit mask of STATUS field. */
101 
102 /* Register: AAR_ENABLE */
103 /* Description: Enable AAR */
104 
105 /* Bits 1..0 : Enable or disable AAR */
106 #define AAR_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
107 #define AAR_ENABLE_ENABLE_Msk (0x3UL << AAR_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
108 #define AAR_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
109 #define AAR_ENABLE_ENABLE_Enabled (3UL) /*!< Enable */
110 
111 /* Register: AAR_NIRK */
112 /* Description: Number of IRKs */
113 
114 /* Bits 4..0 : Number of Identity root keys available in the IRK data structure */
115 #define AAR_NIRK_NIRK_Pos (0UL) /*!< Position of NIRK field. */
116 #define AAR_NIRK_NIRK_Msk (0x1FUL << AAR_NIRK_NIRK_Pos) /*!< Bit mask of NIRK field. */
117 
118 /* Register: AAR_IRKPTR */
119 /* Description: Pointer to IRK data structure */
120 
121 /* Bits 31..0 : Pointer to the IRK data structure */
122 #define AAR_IRKPTR_IRKPTR_Pos (0UL) /*!< Position of IRKPTR field. */
123 #define AAR_IRKPTR_IRKPTR_Msk (0xFFFFFFFFUL << AAR_IRKPTR_IRKPTR_Pos) /*!< Bit mask of IRKPTR field. */
124 
125 /* Register: AAR_ADDRPTR */
126 /* Description: Pointer to the resolvable address */
127 
128 /* Bits 31..0 : Pointer to the resolvable address (6-bytes) */
129 #define AAR_ADDRPTR_ADDRPTR_Pos (0UL) /*!< Position of ADDRPTR field. */
130 #define AAR_ADDRPTR_ADDRPTR_Msk (0xFFFFFFFFUL << AAR_ADDRPTR_ADDRPTR_Pos) /*!< Bit mask of ADDRPTR field. */
131 
132 /* Register: AAR_SCRATCHPTR */
133 /* Description: Pointer to data area used for temporary storage */
134 
135 /* Bits 31..0 : Pointer to a scratch data area used for temporary storage during resolution.A space of minimum 3 bytes must be reserved. */
136 #define AAR_SCRATCHPTR_SCRATCHPTR_Pos (0UL) /*!< Position of SCRATCHPTR field. */
137 #define AAR_SCRATCHPTR_SCRATCHPTR_Msk (0xFFFFFFFFUL << AAR_SCRATCHPTR_SCRATCHPTR_Pos) /*!< Bit mask of SCRATCHPTR field. */
138 
139 
140 /* Peripheral: BPROT */
141 /* Description: Block Protect */
142 
143 /* Register: BPROT_CONFIG0 */
144 /* Description: Block protect configuration register 0 */
145 
146 /* Bit 31 : Enable protection for region 31. Write '0' has no effect. */
147 #define BPROT_CONFIG0_REGION31_Pos (31UL) /*!< Position of REGION31 field. */
148 #define BPROT_CONFIG0_REGION31_Msk (0x1UL << BPROT_CONFIG0_REGION31_Pos) /*!< Bit mask of REGION31 field. */
149 #define BPROT_CONFIG0_REGION31_Disabled (0UL) /*!< Protection disabled */
150 #define BPROT_CONFIG0_REGION31_Enabled (1UL) /*!< Protection enable */
151 
152 /* Bit 30 : Enable protection for region 30. Write '0' has no effect. */
153 #define BPROT_CONFIG0_REGION30_Pos (30UL) /*!< Position of REGION30 field. */
154 #define BPROT_CONFIG0_REGION30_Msk (0x1UL << BPROT_CONFIG0_REGION30_Pos) /*!< Bit mask of REGION30 field. */
155 #define BPROT_CONFIG0_REGION30_Disabled (0UL) /*!< Protection disabled */
156 #define BPROT_CONFIG0_REGION30_Enabled (1UL) /*!< Protection enable */
157 
158 /* Bit 29 : Enable protection for region 29. Write '0' has no effect. */
159 #define BPROT_CONFIG0_REGION29_Pos (29UL) /*!< Position of REGION29 field. */
160 #define BPROT_CONFIG0_REGION29_Msk (0x1UL << BPROT_CONFIG0_REGION29_Pos) /*!< Bit mask of REGION29 field. */
161 #define BPROT_CONFIG0_REGION29_Disabled (0UL) /*!< Protection disabled */
162 #define BPROT_CONFIG0_REGION29_Enabled (1UL) /*!< Protection enable */
163 
164 /* Bit 28 : Enable protection for region 28. Write '0' has no effect. */
165 #define BPROT_CONFIG0_REGION28_Pos (28UL) /*!< Position of REGION28 field. */
166 #define BPROT_CONFIG0_REGION28_Msk (0x1UL << BPROT_CONFIG0_REGION28_Pos) /*!< Bit mask of REGION28 field. */
167 #define BPROT_CONFIG0_REGION28_Disabled (0UL) /*!< Protection disabled */
168 #define BPROT_CONFIG0_REGION28_Enabled (1UL) /*!< Protection enable */
169 
170 /* Bit 27 : Enable protection for region 27. Write '0' has no effect. */
171 #define BPROT_CONFIG0_REGION27_Pos (27UL) /*!< Position of REGION27 field. */
172 #define BPROT_CONFIG0_REGION27_Msk (0x1UL << BPROT_CONFIG0_REGION27_Pos) /*!< Bit mask of REGION27 field. */
173 #define BPROT_CONFIG0_REGION27_Disabled (0UL) /*!< Protection disabled */
174 #define BPROT_CONFIG0_REGION27_Enabled (1UL) /*!< Protection enable */
175 
176 /* Bit 26 : Enable protection for region 26. Write '0' has no effect. */
177 #define BPROT_CONFIG0_REGION26_Pos (26UL) /*!< Position of REGION26 field. */
178 #define BPROT_CONFIG0_REGION26_Msk (0x1UL << BPROT_CONFIG0_REGION26_Pos) /*!< Bit mask of REGION26 field. */
179 #define BPROT_CONFIG0_REGION26_Disabled (0UL) /*!< Protection disabled */
180 #define BPROT_CONFIG0_REGION26_Enabled (1UL) /*!< Protection enable */
181 
182 /* Bit 25 : Enable protection for region 25. Write '0' has no effect. */
183 #define BPROT_CONFIG0_REGION25_Pos (25UL) /*!< Position of REGION25 field. */
184 #define BPROT_CONFIG0_REGION25_Msk (0x1UL << BPROT_CONFIG0_REGION25_Pos) /*!< Bit mask of REGION25 field. */
185 #define BPROT_CONFIG0_REGION25_Disabled (0UL) /*!< Protection disabled */
186 #define BPROT_CONFIG0_REGION25_Enabled (1UL) /*!< Protection enable */
187 
188 /* Bit 24 : Enable protection for region 24. Write '0' has no effect. */
189 #define BPROT_CONFIG0_REGION24_Pos (24UL) /*!< Position of REGION24 field. */
190 #define BPROT_CONFIG0_REGION24_Msk (0x1UL << BPROT_CONFIG0_REGION24_Pos) /*!< Bit mask of REGION24 field. */
191 #define BPROT_CONFIG0_REGION24_Disabled (0UL) /*!< Protection disabled */
192 #define BPROT_CONFIG0_REGION24_Enabled (1UL) /*!< Protection enable */
193 
194 /* Bit 23 : Enable protection for region 23. Write '0' has no effect. */
195 #define BPROT_CONFIG0_REGION23_Pos (23UL) /*!< Position of REGION23 field. */
196 #define BPROT_CONFIG0_REGION23_Msk (0x1UL << BPROT_CONFIG0_REGION23_Pos) /*!< Bit mask of REGION23 field. */
197 #define BPROT_CONFIG0_REGION23_Disabled (0UL) /*!< Protection disabled */
198 #define BPROT_CONFIG0_REGION23_Enabled (1UL) /*!< Protection enable */
199 
200 /* Bit 22 : Enable protection for region 22. Write '0' has no effect. */
201 #define BPROT_CONFIG0_REGION22_Pos (22UL) /*!< Position of REGION22 field. */
202 #define BPROT_CONFIG0_REGION22_Msk (0x1UL << BPROT_CONFIG0_REGION22_Pos) /*!< Bit mask of REGION22 field. */
203 #define BPROT_CONFIG0_REGION22_Disabled (0UL) /*!< Protection disabled */
204 #define BPROT_CONFIG0_REGION22_Enabled (1UL) /*!< Protection enable */
205 
206 /* Bit 21 : Enable protection for region 21. Write '0' has no effect. */
207 #define BPROT_CONFIG0_REGION21_Pos (21UL) /*!< Position of REGION21 field. */
208 #define BPROT_CONFIG0_REGION21_Msk (0x1UL << BPROT_CONFIG0_REGION21_Pos) /*!< Bit mask of REGION21 field. */
209 #define BPROT_CONFIG0_REGION21_Disabled (0UL) /*!< Protection disabled */
210 #define BPROT_CONFIG0_REGION21_Enabled (1UL) /*!< Protection enable */
211 
212 /* Bit 20 : Enable protection for region 20. Write '0' has no effect. */
213 #define BPROT_CONFIG0_REGION20_Pos (20UL) /*!< Position of REGION20 field. */
214 #define BPROT_CONFIG0_REGION20_Msk (0x1UL << BPROT_CONFIG0_REGION20_Pos) /*!< Bit mask of REGION20 field. */
215 #define BPROT_CONFIG0_REGION20_Disabled (0UL) /*!< Protection disabled */
216 #define BPROT_CONFIG0_REGION20_Enabled (1UL) /*!< Protection enable */
217 
218 /* Bit 19 : Enable protection for region 19. Write '0' has no effect. */
219 #define BPROT_CONFIG0_REGION19_Pos (19UL) /*!< Position of REGION19 field. */
220 #define BPROT_CONFIG0_REGION19_Msk (0x1UL << BPROT_CONFIG0_REGION19_Pos) /*!< Bit mask of REGION19 field. */
221 #define BPROT_CONFIG0_REGION19_Disabled (0UL) /*!< Protection disabled */
222 #define BPROT_CONFIG0_REGION19_Enabled (1UL) /*!< Protection enable */
223 
224 /* Bit 18 : Enable protection for region 18. Write '0' has no effect. */
225 #define BPROT_CONFIG0_REGION18_Pos (18UL) /*!< Position of REGION18 field. */
226 #define BPROT_CONFIG0_REGION18_Msk (0x1UL << BPROT_CONFIG0_REGION18_Pos) /*!< Bit mask of REGION18 field. */
227 #define BPROT_CONFIG0_REGION18_Disabled (0UL) /*!< Protection disabled */
228 #define BPROT_CONFIG0_REGION18_Enabled (1UL) /*!< Protection enable */
229 
230 /* Bit 17 : Enable protection for region 17. Write '0' has no effect. */
231 #define BPROT_CONFIG0_REGION17_Pos (17UL) /*!< Position of REGION17 field. */
232 #define BPROT_CONFIG0_REGION17_Msk (0x1UL << BPROT_CONFIG0_REGION17_Pos) /*!< Bit mask of REGION17 field. */
233 #define BPROT_CONFIG0_REGION17_Disabled (0UL) /*!< Protection disabled */
234 #define BPROT_CONFIG0_REGION17_Enabled (1UL) /*!< Protection enable */
235 
236 /* Bit 16 : Enable protection for region 16. Write '0' has no effect. */
237 #define BPROT_CONFIG0_REGION16_Pos (16UL) /*!< Position of REGION16 field. */
238 #define BPROT_CONFIG0_REGION16_Msk (0x1UL << BPROT_CONFIG0_REGION16_Pos) /*!< Bit mask of REGION16 field. */
239 #define BPROT_CONFIG0_REGION16_Disabled (0UL) /*!< Protection disabled */
240 #define BPROT_CONFIG0_REGION16_Enabled (1UL) /*!< Protection enable */
241 
242 /* Bit 15 : Enable protection for region 15. Write '0' has no effect. */
243 #define BPROT_CONFIG0_REGION15_Pos (15UL) /*!< Position of REGION15 field. */
244 #define BPROT_CONFIG0_REGION15_Msk (0x1UL << BPROT_CONFIG0_REGION15_Pos) /*!< Bit mask of REGION15 field. */
245 #define BPROT_CONFIG0_REGION15_Disabled (0UL) /*!< Protection disabled */
246 #define BPROT_CONFIG0_REGION15_Enabled (1UL) /*!< Protection enable */
247 
248 /* Bit 14 : Enable protection for region 14. Write '0' has no effect. */
249 #define BPROT_CONFIG0_REGION14_Pos (14UL) /*!< Position of REGION14 field. */
250 #define BPROT_CONFIG0_REGION14_Msk (0x1UL << BPROT_CONFIG0_REGION14_Pos) /*!< Bit mask of REGION14 field. */
251 #define BPROT_CONFIG0_REGION14_Disabled (0UL) /*!< Protection disabled */
252 #define BPROT_CONFIG0_REGION14_Enabled (1UL) /*!< Protection enable */
253 
254 /* Bit 13 : Enable protection for region 13. Write '0' has no effect. */
255 #define BPROT_CONFIG0_REGION13_Pos (13UL) /*!< Position of REGION13 field. */
256 #define BPROT_CONFIG0_REGION13_Msk (0x1UL << BPROT_CONFIG0_REGION13_Pos) /*!< Bit mask of REGION13 field. */
257 #define BPROT_CONFIG0_REGION13_Disabled (0UL) /*!< Protection disabled */
258 #define BPROT_CONFIG0_REGION13_Enabled (1UL) /*!< Protection enable */
259 
260 /* Bit 12 : Enable protection for region 12. Write '0' has no effect. */
261 #define BPROT_CONFIG0_REGION12_Pos (12UL) /*!< Position of REGION12 field. */
262 #define BPROT_CONFIG0_REGION12_Msk (0x1UL << BPROT_CONFIG0_REGION12_Pos) /*!< Bit mask of REGION12 field. */
263 #define BPROT_CONFIG0_REGION12_Disabled (0UL) /*!< Protection disabled */
264 #define BPROT_CONFIG0_REGION12_Enabled (1UL) /*!< Protection enable */
265 
266 /* Bit 11 : Enable protection for region 11. Write '0' has no effect. */
267 #define BPROT_CONFIG0_REGION11_Pos (11UL) /*!< Position of REGION11 field. */
268 #define BPROT_CONFIG0_REGION11_Msk (0x1UL << BPROT_CONFIG0_REGION11_Pos) /*!< Bit mask of REGION11 field. */
269 #define BPROT_CONFIG0_REGION11_Disabled (0UL) /*!< Protection disabled */
270 #define BPROT_CONFIG0_REGION11_Enabled (1UL) /*!< Protection enable */
271 
272 /* Bit 10 : Enable protection for region 10. Write '0' has no effect. */
273 #define BPROT_CONFIG0_REGION10_Pos (10UL) /*!< Position of REGION10 field. */
274 #define BPROT_CONFIG0_REGION10_Msk (0x1UL << BPROT_CONFIG0_REGION10_Pos) /*!< Bit mask of REGION10 field. */
275 #define BPROT_CONFIG0_REGION10_Disabled (0UL) /*!< Protection disabled */
276 #define BPROT_CONFIG0_REGION10_Enabled (1UL) /*!< Protection enable */
277 
278 /* Bit 9 : Enable protection for region 9. Write '0' has no effect. */
279 #define BPROT_CONFIG0_REGION9_Pos (9UL) /*!< Position of REGION9 field. */
280 #define BPROT_CONFIG0_REGION9_Msk (0x1UL << BPROT_CONFIG0_REGION9_Pos) /*!< Bit mask of REGION9 field. */
281 #define BPROT_CONFIG0_REGION9_Disabled (0UL) /*!< Protection disabled */
282 #define BPROT_CONFIG0_REGION9_Enabled (1UL) /*!< Protection enable */
283 
284 /* Bit 8 : Enable protection for region 8. Write '0' has no effect. */
285 #define BPROT_CONFIG0_REGION8_Pos (8UL) /*!< Position of REGION8 field. */
286 #define BPROT_CONFIG0_REGION8_Msk (0x1UL << BPROT_CONFIG0_REGION8_Pos) /*!< Bit mask of REGION8 field. */
287 #define BPROT_CONFIG0_REGION8_Disabled (0UL) /*!< Protection disabled */
288 #define BPROT_CONFIG0_REGION8_Enabled (1UL) /*!< Protection enable */
289 
290 /* Bit 7 : Enable protection for region 7. Write '0' has no effect. */
291 #define BPROT_CONFIG0_REGION7_Pos (7UL) /*!< Position of REGION7 field. */
292 #define BPROT_CONFIG0_REGION7_Msk (0x1UL << BPROT_CONFIG0_REGION7_Pos) /*!< Bit mask of REGION7 field. */
293 #define BPROT_CONFIG0_REGION7_Disabled (0UL) /*!< Protection disabled */
294 #define BPROT_CONFIG0_REGION7_Enabled (1UL) /*!< Protection enable */
295 
296 /* Bit 6 : Enable protection for region 6. Write '0' has no effect. */
297 #define BPROT_CONFIG0_REGION6_Pos (6UL) /*!< Position of REGION6 field. */
298 #define BPROT_CONFIG0_REGION6_Msk (0x1UL << BPROT_CONFIG0_REGION6_Pos) /*!< Bit mask of REGION6 field. */
299 #define BPROT_CONFIG0_REGION6_Disabled (0UL) /*!< Protection disabled */
300 #define BPROT_CONFIG0_REGION6_Enabled (1UL) /*!< Protection enable */
301 
302 /* Bit 5 : Enable protection for region 5. Write '0' has no effect. */
303 #define BPROT_CONFIG0_REGION5_Pos (5UL) /*!< Position of REGION5 field. */
304 #define BPROT_CONFIG0_REGION5_Msk (0x1UL << BPROT_CONFIG0_REGION5_Pos) /*!< Bit mask of REGION5 field. */
305 #define BPROT_CONFIG0_REGION5_Disabled (0UL) /*!< Protection disabled */
306 #define BPROT_CONFIG0_REGION5_Enabled (1UL) /*!< Protection enable */
307 
308 /* Bit 4 : Enable protection for region 4. Write '0' has no effect. */
309 #define BPROT_CONFIG0_REGION4_Pos (4UL) /*!< Position of REGION4 field. */
310 #define BPROT_CONFIG0_REGION4_Msk (0x1UL << BPROT_CONFIG0_REGION4_Pos) /*!< Bit mask of REGION4 field. */
311 #define BPROT_CONFIG0_REGION4_Disabled (0UL) /*!< Protection disabled */
312 #define BPROT_CONFIG0_REGION4_Enabled (1UL) /*!< Protection enable */
313 
314 /* Bit 3 : Enable protection for region 3. Write '0' has no effect. */
315 #define BPROT_CONFIG0_REGION3_Pos (3UL) /*!< Position of REGION3 field. */
316 #define BPROT_CONFIG0_REGION3_Msk (0x1UL << BPROT_CONFIG0_REGION3_Pos) /*!< Bit mask of REGION3 field. */
317 #define BPROT_CONFIG0_REGION3_Disabled (0UL) /*!< Protection disabled */
318 #define BPROT_CONFIG0_REGION3_Enabled (1UL) /*!< Protection enable */
319 
320 /* Bit 2 : Enable protection for region 2. Write '0' has no effect. */
321 #define BPROT_CONFIG0_REGION2_Pos (2UL) /*!< Position of REGION2 field. */
322 #define BPROT_CONFIG0_REGION2_Msk (0x1UL << BPROT_CONFIG0_REGION2_Pos) /*!< Bit mask of REGION2 field. */
323 #define BPROT_CONFIG0_REGION2_Disabled (0UL) /*!< Protection disabled */
324 #define BPROT_CONFIG0_REGION2_Enabled (1UL) /*!< Protection enable */
325 
326 /* Bit 1 : Enable protection for region 1. Write '0' has no effect. */
327 #define BPROT_CONFIG0_REGION1_Pos (1UL) /*!< Position of REGION1 field. */
328 #define BPROT_CONFIG0_REGION1_Msk (0x1UL << BPROT_CONFIG0_REGION1_Pos) /*!< Bit mask of REGION1 field. */
329 #define BPROT_CONFIG0_REGION1_Disabled (0UL) /*!< Protection disabled */
330 #define BPROT_CONFIG0_REGION1_Enabled (1UL) /*!< Protection enable */
331 
332 /* Bit 0 : Enable protection for region 0. Write '0' has no effect. */
333 #define BPROT_CONFIG0_REGION0_Pos (0UL) /*!< Position of REGION0 field. */
334 #define BPROT_CONFIG0_REGION0_Msk (0x1UL << BPROT_CONFIG0_REGION0_Pos) /*!< Bit mask of REGION0 field. */
335 #define BPROT_CONFIG0_REGION0_Disabled (0UL) /*!< Protection disabled */
336 #define BPROT_CONFIG0_REGION0_Enabled (1UL) /*!< Protection enable */
337 
338 /* Register: BPROT_CONFIG1 */
339 /* Description: Block protect configuration register 1 */
340 
341 /* Bit 31 : Enable protection for region 63. Write '0' has no effect. */
342 #define BPROT_CONFIG1_REGION63_Pos (31UL) /*!< Position of REGION63 field. */
343 #define BPROT_CONFIG1_REGION63_Msk (0x1UL << BPROT_CONFIG1_REGION63_Pos) /*!< Bit mask of REGION63 field. */
344 #define BPROT_CONFIG1_REGION63_Disabled (0UL) /*!< Protection disabled */
345 #define BPROT_CONFIG1_REGION63_Enabled (1UL) /*!< Protection enabled */
346 
347 /* Bit 30 : Enable protection for region 62. Write '0' has no effect. */
348 #define BPROT_CONFIG1_REGION62_Pos (30UL) /*!< Position of REGION62 field. */
349 #define BPROT_CONFIG1_REGION62_Msk (0x1UL << BPROT_CONFIG1_REGION62_Pos) /*!< Bit mask of REGION62 field. */
350 #define BPROT_CONFIG1_REGION62_Disabled (0UL) /*!< Protection disabled */
351 #define BPROT_CONFIG1_REGION62_Enabled (1UL) /*!< Protection enabled */
352 
353 /* Bit 29 : Enable protection for region 61. Write '0' has no effect. */
354 #define BPROT_CONFIG1_REGION61_Pos (29UL) /*!< Position of REGION61 field. */
355 #define BPROT_CONFIG1_REGION61_Msk (0x1UL << BPROT_CONFIG1_REGION61_Pos) /*!< Bit mask of REGION61 field. */
356 #define BPROT_CONFIG1_REGION61_Disabled (0UL) /*!< Protection disabled */
357 #define BPROT_CONFIG1_REGION61_Enabled (1UL) /*!< Protection enabled */
358 
359 /* Bit 28 : Enable protection for region 60. Write '0' has no effect. */
360 #define BPROT_CONFIG1_REGION60_Pos (28UL) /*!< Position of REGION60 field. */
361 #define BPROT_CONFIG1_REGION60_Msk (0x1UL << BPROT_CONFIG1_REGION60_Pos) /*!< Bit mask of REGION60 field. */
362 #define BPROT_CONFIG1_REGION60_Disabled (0UL) /*!< Protection disabled */
363 #define BPROT_CONFIG1_REGION60_Enabled (1UL) /*!< Protection enabled */
364 
365 /* Bit 27 : Enable protection for region 59. Write '0' has no effect. */
366 #define BPROT_CONFIG1_REGION59_Pos (27UL) /*!< Position of REGION59 field. */
367 #define BPROT_CONFIG1_REGION59_Msk (0x1UL << BPROT_CONFIG1_REGION59_Pos) /*!< Bit mask of REGION59 field. */
368 #define BPROT_CONFIG1_REGION59_Disabled (0UL) /*!< Protection disabled */
369 #define BPROT_CONFIG1_REGION59_Enabled (1UL) /*!< Protection enabled */
370 
371 /* Bit 26 : Enable protection for region 58. Write '0' has no effect. */
372 #define BPROT_CONFIG1_REGION58_Pos (26UL) /*!< Position of REGION58 field. */
373 #define BPROT_CONFIG1_REGION58_Msk (0x1UL << BPROT_CONFIG1_REGION58_Pos) /*!< Bit mask of REGION58 field. */
374 #define BPROT_CONFIG1_REGION58_Disabled (0UL) /*!< Protection disabled */
375 #define BPROT_CONFIG1_REGION58_Enabled (1UL) /*!< Protection enabled */
376 
377 /* Bit 25 : Enable protection for region 57. Write '0' has no effect. */
378 #define BPROT_CONFIG1_REGION57_Pos (25UL) /*!< Position of REGION57 field. */
379 #define BPROT_CONFIG1_REGION57_Msk (0x1UL << BPROT_CONFIG1_REGION57_Pos) /*!< Bit mask of REGION57 field. */
380 #define BPROT_CONFIG1_REGION57_Disabled (0UL) /*!< Protection disabled */
381 #define BPROT_CONFIG1_REGION57_Enabled (1UL) /*!< Protection enabled */
382 
383 /* Bit 24 : Enable protection for region 56. Write '0' has no effect. */
384 #define BPROT_CONFIG1_REGION56_Pos (24UL) /*!< Position of REGION56 field. */
385 #define BPROT_CONFIG1_REGION56_Msk (0x1UL << BPROT_CONFIG1_REGION56_Pos) /*!< Bit mask of REGION56 field. */
386 #define BPROT_CONFIG1_REGION56_Disabled (0UL) /*!< Protection disabled */
387 #define BPROT_CONFIG1_REGION56_Enabled (1UL) /*!< Protection enabled */
388 
389 /* Bit 23 : Enable protection for region 55. Write '0' has no effect. */
390 #define BPROT_CONFIG1_REGION55_Pos (23UL) /*!< Position of REGION55 field. */
391 #define BPROT_CONFIG1_REGION55_Msk (0x1UL << BPROT_CONFIG1_REGION55_Pos) /*!< Bit mask of REGION55 field. */
392 #define BPROT_CONFIG1_REGION55_Disabled (0UL) /*!< Protection disabled */
393 #define BPROT_CONFIG1_REGION55_Enabled (1UL) /*!< Protection enabled */
394 
395 /* Bit 22 : Enable protection for region 54. Write '0' has no effect. */
396 #define BPROT_CONFIG1_REGION54_Pos (22UL) /*!< Position of REGION54 field. */
397 #define BPROT_CONFIG1_REGION54_Msk (0x1UL << BPROT_CONFIG1_REGION54_Pos) /*!< Bit mask of REGION54 field. */
398 #define BPROT_CONFIG1_REGION54_Disabled (0UL) /*!< Protection disabled */
399 #define BPROT_CONFIG1_REGION54_Enabled (1UL) /*!< Protection enabled */
400 
401 /* Bit 21 : Enable protection for region 53. Write '0' has no effect. */
402 #define BPROT_CONFIG1_REGION53_Pos (21UL) /*!< Position of REGION53 field. */
403 #define BPROT_CONFIG1_REGION53_Msk (0x1UL << BPROT_CONFIG1_REGION53_Pos) /*!< Bit mask of REGION53 field. */
404 #define BPROT_CONFIG1_REGION53_Disabled (0UL) /*!< Protection disabled */
405 #define BPROT_CONFIG1_REGION53_Enabled (1UL) /*!< Protection enabled */
406 
407 /* Bit 20 : Enable protection for region 52. Write '0' has no effect. */
408 #define BPROT_CONFIG1_REGION52_Pos (20UL) /*!< Position of REGION52 field. */
409 #define BPROT_CONFIG1_REGION52_Msk (0x1UL << BPROT_CONFIG1_REGION52_Pos) /*!< Bit mask of REGION52 field. */
410 #define BPROT_CONFIG1_REGION52_Disabled (0UL) /*!< Protection disabled */
411 #define BPROT_CONFIG1_REGION52_Enabled (1UL) /*!< Protection enabled */
412 
413 /* Bit 19 : Enable protection for region 51. Write '0' has no effect. */
414 #define BPROT_CONFIG1_REGION51_Pos (19UL) /*!< Position of REGION51 field. */
415 #define BPROT_CONFIG1_REGION51_Msk (0x1UL << BPROT_CONFIG1_REGION51_Pos) /*!< Bit mask of REGION51 field. */
416 #define BPROT_CONFIG1_REGION51_Disabled (0UL) /*!< Protection disabled */
417 #define BPROT_CONFIG1_REGION51_Enabled (1UL) /*!< Protection enabled */
418 
419 /* Bit 18 : Enable protection for region 50. Write '0' has no effect. */
420 #define BPROT_CONFIG1_REGION50_Pos (18UL) /*!< Position of REGION50 field. */
421 #define BPROT_CONFIG1_REGION50_Msk (0x1UL << BPROT_CONFIG1_REGION50_Pos) /*!< Bit mask of REGION50 field. */
422 #define BPROT_CONFIG1_REGION50_Disabled (0UL) /*!< Protection disabled */
423 #define BPROT_CONFIG1_REGION50_Enabled (1UL) /*!< Protection enabled */
424 
425 /* Bit 17 : Enable protection for region 49. Write '0' has no effect. */
426 #define BPROT_CONFIG1_REGION49_Pos (17UL) /*!< Position of REGION49 field. */
427 #define BPROT_CONFIG1_REGION49_Msk (0x1UL << BPROT_CONFIG1_REGION49_Pos) /*!< Bit mask of REGION49 field. */
428 #define BPROT_CONFIG1_REGION49_Disabled (0UL) /*!< Protection disabled */
429 #define BPROT_CONFIG1_REGION49_Enabled (1UL) /*!< Protection enabled */
430 
431 /* Bit 16 : Enable protection for region 48. Write '0' has no effect. */
432 #define BPROT_CONFIG1_REGION48_Pos (16UL) /*!< Position of REGION48 field. */
433 #define BPROT_CONFIG1_REGION48_Msk (0x1UL << BPROT_CONFIG1_REGION48_Pos) /*!< Bit mask of REGION48 field. */
434 #define BPROT_CONFIG1_REGION48_Disabled (0UL) /*!< Protection disabled */
435 #define BPROT_CONFIG1_REGION48_Enabled (1UL) /*!< Protection enabled */
436 
437 /* Bit 15 : Enable protection for region 47. Write '0' has no effect. */
438 #define BPROT_CONFIG1_REGION47_Pos (15UL) /*!< Position of REGION47 field. */
439 #define BPROT_CONFIG1_REGION47_Msk (0x1UL << BPROT_CONFIG1_REGION47_Pos) /*!< Bit mask of REGION47 field. */
440 #define BPROT_CONFIG1_REGION47_Disabled (0UL) /*!< Protection disabled */
441 #define BPROT_CONFIG1_REGION47_Enabled (1UL) /*!< Protection enabled */
442 
443 /* Bit 14 : Enable protection for region 46. Write '0' has no effect. */
444 #define BPROT_CONFIG1_REGION46_Pos (14UL) /*!< Position of REGION46 field. */
445 #define BPROT_CONFIG1_REGION46_Msk (0x1UL << BPROT_CONFIG1_REGION46_Pos) /*!< Bit mask of REGION46 field. */
446 #define BPROT_CONFIG1_REGION46_Disabled (0UL) /*!< Protection disabled */
447 #define BPROT_CONFIG1_REGION46_Enabled (1UL) /*!< Protection enabled */
448 
449 /* Bit 13 : Enable protection for region 45. Write '0' has no effect. */
450 #define BPROT_CONFIG1_REGION45_Pos (13UL) /*!< Position of REGION45 field. */
451 #define BPROT_CONFIG1_REGION45_Msk (0x1UL << BPROT_CONFIG1_REGION45_Pos) /*!< Bit mask of REGION45 field. */
452 #define BPROT_CONFIG1_REGION45_Disabled (0UL) /*!< Protection disabled */
453 #define BPROT_CONFIG1_REGION45_Enabled (1UL) /*!< Protection enabled */
454 
455 /* Bit 12 : Enable protection for region 44. Write '0' has no effect. */
456 #define BPROT_CONFIG1_REGION44_Pos (12UL) /*!< Position of REGION44 field. */
457 #define BPROT_CONFIG1_REGION44_Msk (0x1UL << BPROT_CONFIG1_REGION44_Pos) /*!< Bit mask of REGION44 field. */
458 #define BPROT_CONFIG1_REGION44_Disabled (0UL) /*!< Protection disabled */
459 #define BPROT_CONFIG1_REGION44_Enabled (1UL) /*!< Protection enabled */
460 
461 /* Bit 11 : Enable protection for region 43. Write '0' has no effect. */
462 #define BPROT_CONFIG1_REGION43_Pos (11UL) /*!< Position of REGION43 field. */
463 #define BPROT_CONFIG1_REGION43_Msk (0x1UL << BPROT_CONFIG1_REGION43_Pos) /*!< Bit mask of REGION43 field. */
464 #define BPROT_CONFIG1_REGION43_Disabled (0UL) /*!< Protection disabled */
465 #define BPROT_CONFIG1_REGION43_Enabled (1UL) /*!< Protection enabled */
466 
467 /* Bit 10 : Enable protection for region 42. Write '0' has no effect. */
468 #define BPROT_CONFIG1_REGION42_Pos (10UL) /*!< Position of REGION42 field. */
469 #define BPROT_CONFIG1_REGION42_Msk (0x1UL << BPROT_CONFIG1_REGION42_Pos) /*!< Bit mask of REGION42 field. */
470 #define BPROT_CONFIG1_REGION42_Disabled (0UL) /*!< Protection disabled */
471 #define BPROT_CONFIG1_REGION42_Enabled (1UL) /*!< Protection enabled */
472 
473 /* Bit 9 : Enable protection for region 41. Write '0' has no effect. */
474 #define BPROT_CONFIG1_REGION41_Pos (9UL) /*!< Position of REGION41 field. */
475 #define BPROT_CONFIG1_REGION41_Msk (0x1UL << BPROT_CONFIG1_REGION41_Pos) /*!< Bit mask of REGION41 field. */
476 #define BPROT_CONFIG1_REGION41_Disabled (0UL) /*!< Protection disabled */
477 #define BPROT_CONFIG1_REGION41_Enabled (1UL) /*!< Protection enabled */
478 
479 /* Bit 8 : Enable protection for region 40. Write '0' has no effect. */
480 #define BPROT_CONFIG1_REGION40_Pos (8UL) /*!< Position of REGION40 field. */
481 #define BPROT_CONFIG1_REGION40_Msk (0x1UL << BPROT_CONFIG1_REGION40_Pos) /*!< Bit mask of REGION40 field. */
482 #define BPROT_CONFIG1_REGION40_Disabled (0UL) /*!< Protection disabled */
483 #define BPROT_CONFIG1_REGION40_Enabled (1UL) /*!< Protection enabled */
484 
485 /* Bit 7 : Enable protection for region 39. Write '0' has no effect. */
486 #define BPROT_CONFIG1_REGION39_Pos (7UL) /*!< Position of REGION39 field. */
487 #define BPROT_CONFIG1_REGION39_Msk (0x1UL << BPROT_CONFIG1_REGION39_Pos) /*!< Bit mask of REGION39 field. */
488 #define BPROT_CONFIG1_REGION39_Disabled (0UL) /*!< Protection disabled */
489 #define BPROT_CONFIG1_REGION39_Enabled (1UL) /*!< Protection enabled */
490 
491 /* Bit 6 : Enable protection for region 38. Write '0' has no effect. */
492 #define BPROT_CONFIG1_REGION38_Pos (6UL) /*!< Position of REGION38 field. */
493 #define BPROT_CONFIG1_REGION38_Msk (0x1UL << BPROT_CONFIG1_REGION38_Pos) /*!< Bit mask of REGION38 field. */
494 #define BPROT_CONFIG1_REGION38_Disabled (0UL) /*!< Protection disabled */
495 #define BPROT_CONFIG1_REGION38_Enabled (1UL) /*!< Protection enabled */
496 
497 /* Bit 5 : Enable protection for region 37. Write '0' has no effect. */
498 #define BPROT_CONFIG1_REGION37_Pos (5UL) /*!< Position of REGION37 field. */
499 #define BPROT_CONFIG1_REGION37_Msk (0x1UL << BPROT_CONFIG1_REGION37_Pos) /*!< Bit mask of REGION37 field. */
500 #define BPROT_CONFIG1_REGION37_Disabled (0UL) /*!< Protection disabled */
501 #define BPROT_CONFIG1_REGION37_Enabled (1UL) /*!< Protection enabled */
502 
503 /* Bit 4 : Enable protection for region 36. Write '0' has no effect. */
504 #define BPROT_CONFIG1_REGION36_Pos (4UL) /*!< Position of REGION36 field. */
505 #define BPROT_CONFIG1_REGION36_Msk (0x1UL << BPROT_CONFIG1_REGION36_Pos) /*!< Bit mask of REGION36 field. */
506 #define BPROT_CONFIG1_REGION36_Disabled (0UL) /*!< Protection disabled */
507 #define BPROT_CONFIG1_REGION36_Enabled (1UL) /*!< Protection enabled */
508 
509 /* Bit 3 : Enable protection for region 35. Write '0' has no effect. */
510 #define BPROT_CONFIG1_REGION35_Pos (3UL) /*!< Position of REGION35 field. */
511 #define BPROT_CONFIG1_REGION35_Msk (0x1UL << BPROT_CONFIG1_REGION35_Pos) /*!< Bit mask of REGION35 field. */
512 #define BPROT_CONFIG1_REGION35_Disabled (0UL) /*!< Protection disabled */
513 #define BPROT_CONFIG1_REGION35_Enabled (1UL) /*!< Protection enabled */
514 
515 /* Bit 2 : Enable protection for region 34. Write '0' has no effect. */
516 #define BPROT_CONFIG1_REGION34_Pos (2UL) /*!< Position of REGION34 field. */
517 #define BPROT_CONFIG1_REGION34_Msk (0x1UL << BPROT_CONFIG1_REGION34_Pos) /*!< Bit mask of REGION34 field. */
518 #define BPROT_CONFIG1_REGION34_Disabled (0UL) /*!< Protection disabled */
519 #define BPROT_CONFIG1_REGION34_Enabled (1UL) /*!< Protection enabled */
520 
521 /* Bit 1 : Enable protection for region 33. Write '0' has no effect. */
522 #define BPROT_CONFIG1_REGION33_Pos (1UL) /*!< Position of REGION33 field. */
523 #define BPROT_CONFIG1_REGION33_Msk (0x1UL << BPROT_CONFIG1_REGION33_Pos) /*!< Bit mask of REGION33 field. */
524 #define BPROT_CONFIG1_REGION33_Disabled (0UL) /*!< Protection disabled */
525 #define BPROT_CONFIG1_REGION33_Enabled (1UL) /*!< Protection enabled */
526 
527 /* Bit 0 : Enable protection for region 32. Write '0' has no effect. */
528 #define BPROT_CONFIG1_REGION32_Pos (0UL) /*!< Position of REGION32 field. */
529 #define BPROT_CONFIG1_REGION32_Msk (0x1UL << BPROT_CONFIG1_REGION32_Pos) /*!< Bit mask of REGION32 field. */
530 #define BPROT_CONFIG1_REGION32_Disabled (0UL) /*!< Protection disabled */
531 #define BPROT_CONFIG1_REGION32_Enabled (1UL) /*!< Protection enabled */
532 
533 /* Register: BPROT_DISABLEINDEBUG */
534 /* Description: Disable protection mechanism in debug interface mode */
535 
536 /* Bit 0 : Disable the protection mechanism for NVM regions while in debug interface mode. This register will only disable the protection mechanism if the device is in debug interface mode. */
537 #define BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Pos (0UL) /*!< Position of DISABLEINDEBUG field. */
538 #define BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Msk (0x1UL << BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Pos) /*!< Bit mask of DISABLEINDEBUG field. */
539 #define BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Enabled (0UL) /*!< Enable in debug */
540 #define BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Disabled (1UL) /*!< Disable in debug */
541 
542 /* Register: BPROT_CONFIG2 */
543 /* Description: Block protect configuration register 2 */
544 
545 /* Bit 31 : Enable protection for region 95. Write '0' has no effect. */
546 #define BPROT_CONFIG2_REGION95_Pos (31UL) /*!< Position of REGION95 field. */
547 #define BPROT_CONFIG2_REGION95_Msk (0x1UL << BPROT_CONFIG2_REGION95_Pos) /*!< Bit mask of REGION95 field. */
548 #define BPROT_CONFIG2_REGION95_Disabled (0UL) /*!< Protection disabled */
549 #define BPROT_CONFIG2_REGION95_Enabled (1UL) /*!< Protection enabled */
550 
551 /* Bit 30 : Enable protection for region 94. Write '0' has no effect. */
552 #define BPROT_CONFIG2_REGION94_Pos (30UL) /*!< Position of REGION94 field. */
553 #define BPROT_CONFIG2_REGION94_Msk (0x1UL << BPROT_CONFIG2_REGION94_Pos) /*!< Bit mask of REGION94 field. */
554 #define BPROT_CONFIG2_REGION94_Disabled (0UL) /*!< Protection disabled */
555 #define BPROT_CONFIG2_REGION94_Enabled (1UL) /*!< Protection enabled */
556 
557 /* Bit 29 : Enable protection for region 93. Write '0' has no effect. */
558 #define BPROT_CONFIG2_REGION93_Pos (29UL) /*!< Position of REGION93 field. */
559 #define BPROT_CONFIG2_REGION93_Msk (0x1UL << BPROT_CONFIG2_REGION93_Pos) /*!< Bit mask of REGION93 field. */
560 #define BPROT_CONFIG2_REGION93_Disabled (0UL) /*!< Protection disabled */
561 #define BPROT_CONFIG2_REGION93_Enabled (1UL) /*!< Protection enabled */
562 
563 /* Bit 28 : Enable protection for region 92. Write '0' has no effect. */
564 #define BPROT_CONFIG2_REGION92_Pos (28UL) /*!< Position of REGION92 field. */
565 #define BPROT_CONFIG2_REGION92_Msk (0x1UL << BPROT_CONFIG2_REGION92_Pos) /*!< Bit mask of REGION92 field. */
566 #define BPROT_CONFIG2_REGION92_Disabled (0UL) /*!< Protection disabled */
567 #define BPROT_CONFIG2_REGION92_Enabled (1UL) /*!< Protection enabled */
568 
569 /* Bit 27 : Enable protection for region 91. Write '0' has no effect. */
570 #define BPROT_CONFIG2_REGION91_Pos (27UL) /*!< Position of REGION91 field. */
571 #define BPROT_CONFIG2_REGION91_Msk (0x1UL << BPROT_CONFIG2_REGION91_Pos) /*!< Bit mask of REGION91 field. */
572 #define BPROT_CONFIG2_REGION91_Disabled (0UL) /*!< Protection disabled */
573 #define BPROT_CONFIG2_REGION91_Enabled (1UL) /*!< Protection enabled */
574 
575 /* Bit 26 : Enable protection for region 90. Write '0' has no effect. */
576 #define BPROT_CONFIG2_REGION90_Pos (26UL) /*!< Position of REGION90 field. */
577 #define BPROT_CONFIG2_REGION90_Msk (0x1UL << BPROT_CONFIG2_REGION90_Pos) /*!< Bit mask of REGION90 field. */
578 #define BPROT_CONFIG2_REGION90_Disabled (0UL) /*!< Protection disabled */
579 #define BPROT_CONFIG2_REGION90_Enabled (1UL) /*!< Protection enabled */
580 
581 /* Bit 25 : Enable protection for region 89. Write '0' has no effect. */
582 #define BPROT_CONFIG2_REGION89_Pos (25UL) /*!< Position of REGION89 field. */
583 #define BPROT_CONFIG2_REGION89_Msk (0x1UL << BPROT_CONFIG2_REGION89_Pos) /*!< Bit mask of REGION89 field. */
584 #define BPROT_CONFIG2_REGION89_Disabled (0UL) /*!< Protection disabled */
585 #define BPROT_CONFIG2_REGION89_Enabled (1UL) /*!< Protection enabled */
586 
587 /* Bit 24 : Enable protection for region 88. Write '0' has no effect. */
588 #define BPROT_CONFIG2_REGION88_Pos (24UL) /*!< Position of REGION88 field. */
589 #define BPROT_CONFIG2_REGION88_Msk (0x1UL << BPROT_CONFIG2_REGION88_Pos) /*!< Bit mask of REGION88 field. */
590 #define BPROT_CONFIG2_REGION88_Disabled (0UL) /*!< Protection disabled */
591 #define BPROT_CONFIG2_REGION88_Enabled (1UL) /*!< Protection enabled */
592 
593 /* Bit 23 : Enable protection for region 87. Write '0' has no effect. */
594 #define BPROT_CONFIG2_REGION87_Pos (23UL) /*!< Position of REGION87 field. */
595 #define BPROT_CONFIG2_REGION87_Msk (0x1UL << BPROT_CONFIG2_REGION87_Pos) /*!< Bit mask of REGION87 field. */
596 #define BPROT_CONFIG2_REGION87_Disabled (0UL) /*!< Protection disabled */
597 #define BPROT_CONFIG2_REGION87_Enabled (1UL) /*!< Protection enabled */
598 
599 /* Bit 22 : Enable protection for region 86. Write '0' has no effect. */
600 #define BPROT_CONFIG2_REGION86_Pos (22UL) /*!< Position of REGION86 field. */
601 #define BPROT_CONFIG2_REGION86_Msk (0x1UL << BPROT_CONFIG2_REGION86_Pos) /*!< Bit mask of REGION86 field. */
602 #define BPROT_CONFIG2_REGION86_Disabled (0UL) /*!< Protection disabled */
603 #define BPROT_CONFIG2_REGION86_Enabled (1UL) /*!< Protection enabled */
604 
605 /* Bit 21 : Enable protection for region 85. Write '0' has no effect. */
606 #define BPROT_CONFIG2_REGION85_Pos (21UL) /*!< Position of REGION85 field. */
607 #define BPROT_CONFIG2_REGION85_Msk (0x1UL << BPROT_CONFIG2_REGION85_Pos) /*!< Bit mask of REGION85 field. */
608 #define BPROT_CONFIG2_REGION85_Disabled (0UL) /*!< Protection disabled */
609 #define BPROT_CONFIG2_REGION85_Enabled (1UL) /*!< Protection enabled */
610 
611 /* Bit 20 : Enable protection for region 84. Write '0' has no effect. */
612 #define BPROT_CONFIG2_REGION84_Pos (20UL) /*!< Position of REGION84 field. */
613 #define BPROT_CONFIG2_REGION84_Msk (0x1UL << BPROT_CONFIG2_REGION84_Pos) /*!< Bit mask of REGION84 field. */
614 #define BPROT_CONFIG2_REGION84_Disabled (0UL) /*!< Protection disabled */
615 #define BPROT_CONFIG2_REGION84_Enabled (1UL) /*!< Protection enabled */
616 
617 /* Bit 19 : Enable protection for region 83. Write '0' has no effect. */
618 #define BPROT_CONFIG2_REGION83_Pos (19UL) /*!< Position of REGION83 field. */
619 #define BPROT_CONFIG2_REGION83_Msk (0x1UL << BPROT_CONFIG2_REGION83_Pos) /*!< Bit mask of REGION83 field. */
620 #define BPROT_CONFIG2_REGION83_Disabled (0UL) /*!< Protection disabled */
621 #define BPROT_CONFIG2_REGION83_Enabled (1UL) /*!< Protection enabled */
622 
623 /* Bit 18 : Enable protection for region 82. Write '0' has no effect. */
624 #define BPROT_CONFIG2_REGION82_Pos (18UL) /*!< Position of REGION82 field. */
625 #define BPROT_CONFIG2_REGION82_Msk (0x1UL << BPROT_CONFIG2_REGION82_Pos) /*!< Bit mask of REGION82 field. */
626 #define BPROT_CONFIG2_REGION82_Disabled (0UL) /*!< Protection disabled */
627 #define BPROT_CONFIG2_REGION82_Enabled (1UL) /*!< Protection enabled */
628 
629 /* Bit 17 : Enable protection for region 81. Write '0' has no effect. */
630 #define BPROT_CONFIG2_REGION81_Pos (17UL) /*!< Position of REGION81 field. */
631 #define BPROT_CONFIG2_REGION81_Msk (0x1UL << BPROT_CONFIG2_REGION81_Pos) /*!< Bit mask of REGION81 field. */
632 #define BPROT_CONFIG2_REGION81_Disabled (0UL) /*!< Protection disabled */
633 #define BPROT_CONFIG2_REGION81_Enabled (1UL) /*!< Protection enabled */
634 
635 /* Bit 16 : Enable protection for region 80. Write '0' has no effect. */
636 #define BPROT_CONFIG2_REGION80_Pos (16UL) /*!< Position of REGION80 field. */
637 #define BPROT_CONFIG2_REGION80_Msk (0x1UL << BPROT_CONFIG2_REGION80_Pos) /*!< Bit mask of REGION80 field. */
638 #define BPROT_CONFIG2_REGION80_Disabled (0UL) /*!< Protection disabled */
639 #define BPROT_CONFIG2_REGION80_Enabled (1UL) /*!< Protection enabled */
640 
641 /* Bit 15 : Enable protection for region 79. Write '0' has no effect. */
642 #define BPROT_CONFIG2_REGION79_Pos (15UL) /*!< Position of REGION79 field. */
643 #define BPROT_CONFIG2_REGION79_Msk (0x1UL << BPROT_CONFIG2_REGION79_Pos) /*!< Bit mask of REGION79 field. */
644 #define BPROT_CONFIG2_REGION79_Disabled (0UL) /*!< Protection disabled */
645 #define BPROT_CONFIG2_REGION79_Enabled (1UL) /*!< Protection enabled */
646 
647 /* Bit 14 : Enable protection for region 78. Write '0' has no effect. */
648 #define BPROT_CONFIG2_REGION78_Pos (14UL) /*!< Position of REGION78 field. */
649 #define BPROT_CONFIG2_REGION78_Msk (0x1UL << BPROT_CONFIG2_REGION78_Pos) /*!< Bit mask of REGION78 field. */
650 #define BPROT_CONFIG2_REGION78_Disabled (0UL) /*!< Protection disabled */
651 #define BPROT_CONFIG2_REGION78_Enabled (1UL) /*!< Protection enabled */
652 
653 /* Bit 13 : Enable protection for region 77. Write '0' has no effect. */
654 #define BPROT_CONFIG2_REGION77_Pos (13UL) /*!< Position of REGION77 field. */
655 #define BPROT_CONFIG2_REGION77_Msk (0x1UL << BPROT_CONFIG2_REGION77_Pos) /*!< Bit mask of REGION77 field. */
656 #define BPROT_CONFIG2_REGION77_Disabled (0UL) /*!< Protection disabled */
657 #define BPROT_CONFIG2_REGION77_Enabled (1UL) /*!< Protection enabled */
658 
659 /* Bit 12 : Enable protection for region 76. Write '0' has no effect. */
660 #define BPROT_CONFIG2_REGION76_Pos (12UL) /*!< Position of REGION76 field. */
661 #define BPROT_CONFIG2_REGION76_Msk (0x1UL << BPROT_CONFIG2_REGION76_Pos) /*!< Bit mask of REGION76 field. */
662 #define BPROT_CONFIG2_REGION76_Disabled (0UL) /*!< Protection disabled */
663 #define BPROT_CONFIG2_REGION76_Enabled (1UL) /*!< Protection enabled */
664 
665 /* Bit 11 : Enable protection for region 75. Write '0' has no effect. */
666 #define BPROT_CONFIG2_REGION75_Pos (11UL) /*!< Position of REGION75 field. */
667 #define BPROT_CONFIG2_REGION75_Msk (0x1UL << BPROT_CONFIG2_REGION75_Pos) /*!< Bit mask of REGION75 field. */
668 #define BPROT_CONFIG2_REGION75_Disabled (0UL) /*!< Protection disabled */
669 #define BPROT_CONFIG2_REGION75_Enabled (1UL) /*!< Protection enabled */
670 
671 /* Bit 10 : Enable protection for region 74. Write '0' has no effect. */
672 #define BPROT_CONFIG2_REGION74_Pos (10UL) /*!< Position of REGION74 field. */
673 #define BPROT_CONFIG2_REGION74_Msk (0x1UL << BPROT_CONFIG2_REGION74_Pos) /*!< Bit mask of REGION74 field. */
674 #define BPROT_CONFIG2_REGION74_Disabled (0UL) /*!< Protection disabled */
675 #define BPROT_CONFIG2_REGION74_Enabled (1UL) /*!< Protection enabled */
676 
677 /* Bit 9 : Enable protection for region 73. Write '0' has no effect. */
678 #define BPROT_CONFIG2_REGION73_Pos (9UL) /*!< Position of REGION73 field. */
679 #define BPROT_CONFIG2_REGION73_Msk (0x1UL << BPROT_CONFIG2_REGION73_Pos) /*!< Bit mask of REGION73 field. */
680 #define BPROT_CONFIG2_REGION73_Disabled (0UL) /*!< Protection disabled */
681 #define BPROT_CONFIG2_REGION73_Enabled (1UL) /*!< Protection enabled */
682 
683 /* Bit 8 : Enable protection for region 72. Write '0' has no effect. */
684 #define BPROT_CONFIG2_REGION72_Pos (8UL) /*!< Position of REGION72 field. */
685 #define BPROT_CONFIG2_REGION72_Msk (0x1UL << BPROT_CONFIG2_REGION72_Pos) /*!< Bit mask of REGION72 field. */
686 #define BPROT_CONFIG2_REGION72_Disabled (0UL) /*!< Protection disabled */
687 #define BPROT_CONFIG2_REGION72_Enabled (1UL) /*!< Protection enabled */
688 
689 /* Bit 7 : Enable protection for region 71. Write '0' has no effect. */
690 #define BPROT_CONFIG2_REGION71_Pos (7UL) /*!< Position of REGION71 field. */
691 #define BPROT_CONFIG2_REGION71_Msk (0x1UL << BPROT_CONFIG2_REGION71_Pos) /*!< Bit mask of REGION71 field. */
692 #define BPROT_CONFIG2_REGION71_Disabled (0UL) /*!< Protection disabled */
693 #define BPROT_CONFIG2_REGION71_Enabled (1UL) /*!< Protection enabled */
694 
695 /* Bit 6 : Enable protection for region 70. Write '0' has no effect. */
696 #define BPROT_CONFIG2_REGION70_Pos (6UL) /*!< Position of REGION70 field. */
697 #define BPROT_CONFIG2_REGION70_Msk (0x1UL << BPROT_CONFIG2_REGION70_Pos) /*!< Bit mask of REGION70 field. */
698 #define BPROT_CONFIG2_REGION70_Disabled (0UL) /*!< Protection disabled */
699 #define BPROT_CONFIG2_REGION70_Enabled (1UL) /*!< Protection enabled */
700 
701 /* Bit 5 : Enable protection for region 69. Write '0' has no effect. */
702 #define BPROT_CONFIG2_REGION69_Pos (5UL) /*!< Position of REGION69 field. */
703 #define BPROT_CONFIG2_REGION69_Msk (0x1UL << BPROT_CONFIG2_REGION69_Pos) /*!< Bit mask of REGION69 field. */
704 #define BPROT_CONFIG2_REGION69_Disabled (0UL) /*!< Protection disabled */
705 #define BPROT_CONFIG2_REGION69_Enabled (1UL) /*!< Protection enabled */
706 
707 /* Bit 4 : Enable protection for region 68. Write '0' has no effect. */
708 #define BPROT_CONFIG2_REGION68_Pos (4UL) /*!< Position of REGION68 field. */
709 #define BPROT_CONFIG2_REGION68_Msk (0x1UL << BPROT_CONFIG2_REGION68_Pos) /*!< Bit mask of REGION68 field. */
710 #define BPROT_CONFIG2_REGION68_Disabled (0UL) /*!< Protection disabled */
711 #define BPROT_CONFIG2_REGION68_Enabled (1UL) /*!< Protection enabled */
712 
713 /* Bit 3 : Enable protection for region 67. Write '0' has no effect. */
714 #define BPROT_CONFIG2_REGION67_Pos (3UL) /*!< Position of REGION67 field. */
715 #define BPROT_CONFIG2_REGION67_Msk (0x1UL << BPROT_CONFIG2_REGION67_Pos) /*!< Bit mask of REGION67 field. */
716 #define BPROT_CONFIG2_REGION67_Disabled (0UL) /*!< Protection disabled */
717 #define BPROT_CONFIG2_REGION67_Enabled (1UL) /*!< Protection enabled */
718 
719 /* Bit 2 : Enable protection for region 66. Write '0' has no effect. */
720 #define BPROT_CONFIG2_REGION66_Pos (2UL) /*!< Position of REGION66 field. */
721 #define BPROT_CONFIG2_REGION66_Msk (0x1UL << BPROT_CONFIG2_REGION66_Pos) /*!< Bit mask of REGION66 field. */
722 #define BPROT_CONFIG2_REGION66_Disabled (0UL) /*!< Protection disabled */
723 #define BPROT_CONFIG2_REGION66_Enabled (1UL) /*!< Protection enabled */
724 
725 /* Bit 1 : Enable protection for region 65. Write '0' has no effect. */
726 #define BPROT_CONFIG2_REGION65_Pos (1UL) /*!< Position of REGION65 field. */
727 #define BPROT_CONFIG2_REGION65_Msk (0x1UL << BPROT_CONFIG2_REGION65_Pos) /*!< Bit mask of REGION65 field. */
728 #define BPROT_CONFIG2_REGION65_Disabled (0UL) /*!< Protection disabled */
729 #define BPROT_CONFIG2_REGION65_Enabled (1UL) /*!< Protection enabled */
730 
731 /* Bit 0 : Enable protection for region 64. Write '0' has no effect. */
732 #define BPROT_CONFIG2_REGION64_Pos (0UL) /*!< Position of REGION64 field. */
733 #define BPROT_CONFIG2_REGION64_Msk (0x1UL << BPROT_CONFIG2_REGION64_Pos) /*!< Bit mask of REGION64 field. */
734 #define BPROT_CONFIG2_REGION64_Disabled (0UL) /*!< Protection disabled */
735 #define BPROT_CONFIG2_REGION64_Enabled (1UL) /*!< Protection enabled */
736 
737 /* Register: BPROT_CONFIG3 */
738 /* Description: Block protect configuration register 3 */
739 
740 /* Bit 31 : Enable protection for region 127. Write '0' has no effect. */
741 #define BPROT_CONFIG3_REGION127_Pos (31UL) /*!< Position of REGION127 field. */
742 #define BPROT_CONFIG3_REGION127_Msk (0x1UL << BPROT_CONFIG3_REGION127_Pos) /*!< Bit mask of REGION127 field. */
743 #define BPROT_CONFIG3_REGION127_Disabled (0UL) /*!< Protection disabled */
744 #define BPROT_CONFIG3_REGION127_Enabled (1UL) /*!< Protection enabled */
745 
746 /* Bit 30 : Enable protection for region 126. Write '0' has no effect. */
747 #define BPROT_CONFIG3_REGION126_Pos (30UL) /*!< Position of REGION126 field. */
748 #define BPROT_CONFIG3_REGION126_Msk (0x1UL << BPROT_CONFIG3_REGION126_Pos) /*!< Bit mask of REGION126 field. */
749 #define BPROT_CONFIG3_REGION126_Disabled (0UL) /*!< Protection disabled */
750 #define BPROT_CONFIG3_REGION126_Enabled (1UL) /*!< Protection enabled */
751 
752 /* Bit 29 : Enable protection for region 125. Write '0' has no effect. */
753 #define BPROT_CONFIG3_REGION125_Pos (29UL) /*!< Position of REGION125 field. */
754 #define BPROT_CONFIG3_REGION125_Msk (0x1UL << BPROT_CONFIG3_REGION125_Pos) /*!< Bit mask of REGION125 field. */
755 #define BPROT_CONFIG3_REGION125_Disabled (0UL) /*!< Protection disabled */
756 #define BPROT_CONFIG3_REGION125_Enabled (1UL) /*!< Protection enabled */
757 
758 /* Bit 28 : Enable protection for region 124. Write '0' has no effect. */
759 #define BPROT_CONFIG3_REGION124_Pos (28UL) /*!< Position of REGION124 field. */
760 #define BPROT_CONFIG3_REGION124_Msk (0x1UL << BPROT_CONFIG3_REGION124_Pos) /*!< Bit mask of REGION124 field. */
761 #define BPROT_CONFIG3_REGION124_Disabled (0UL) /*!< Protection disabled */
762 #define BPROT_CONFIG3_REGION124_Enabled (1UL) /*!< Protection enabled */
763 
764 /* Bit 27 : Enable protection for region 123. Write '0' has no effect. */
765 #define BPROT_CONFIG3_REGION123_Pos (27UL) /*!< Position of REGION123 field. */
766 #define BPROT_CONFIG3_REGION123_Msk (0x1UL << BPROT_CONFIG3_REGION123_Pos) /*!< Bit mask of REGION123 field. */
767 #define BPROT_CONFIG3_REGION123_Disabled (0UL) /*!< Protection disabled */
768 #define BPROT_CONFIG3_REGION123_Enabled (1UL) /*!< Protection enabled */
769 
770 /* Bit 26 : Enable protection for region 122. Write '0' has no effect. */
771 #define BPROT_CONFIG3_REGION122_Pos (26UL) /*!< Position of REGION122 field. */
772 #define BPROT_CONFIG3_REGION122_Msk (0x1UL << BPROT_CONFIG3_REGION122_Pos) /*!< Bit mask of REGION122 field. */
773 #define BPROT_CONFIG3_REGION122_Disabled (0UL) /*!< Protection disabled */
774 #define BPROT_CONFIG3_REGION122_Enabled (1UL) /*!< Protection enabled */
775 
776 /* Bit 25 : Enable protection for region 121. Write '0' has no effect. */
777 #define BPROT_CONFIG3_REGION121_Pos (25UL) /*!< Position of REGION121 field. */
778 #define BPROT_CONFIG3_REGION121_Msk (0x1UL << BPROT_CONFIG3_REGION121_Pos) /*!< Bit mask of REGION121 field. */
779 #define BPROT_CONFIG3_REGION121_Disabled (0UL) /*!< Protection disabled */
780 #define BPROT_CONFIG3_REGION121_Enabled (1UL) /*!< Protection enabled */
781 
782 /* Bit 24 : Enable protection for region 120. Write '0' has no effect. */
783 #define BPROT_CONFIG3_REGION120_Pos (24UL) /*!< Position of REGION120 field. */
784 #define BPROT_CONFIG3_REGION120_Msk (0x1UL << BPROT_CONFIG3_REGION120_Pos) /*!< Bit mask of REGION120 field. */
785 #define BPROT_CONFIG3_REGION120_Disabled (0UL) /*!< Protection disabled */
786 #define BPROT_CONFIG3_REGION120_Enabled (1UL) /*!< Protection enabled */
787 
788 /* Bit 23 : Enable protection for region 119. Write '0' has no effect. */
789 #define BPROT_CONFIG3_REGION119_Pos (23UL) /*!< Position of REGION119 field. */
790 #define BPROT_CONFIG3_REGION119_Msk (0x1UL << BPROT_CONFIG3_REGION119_Pos) /*!< Bit mask of REGION119 field. */
791 #define BPROT_CONFIG3_REGION119_Disabled (0UL) /*!< Protection disabled */
792 #define BPROT_CONFIG3_REGION119_Enabled (1UL) /*!< Protection enabled */
793 
794 /* Bit 22 : Enable protection for region 118. Write '0' has no effect. */
795 #define BPROT_CONFIG3_REGION118_Pos (22UL) /*!< Position of REGION118 field. */
796 #define BPROT_CONFIG3_REGION118_Msk (0x1UL << BPROT_CONFIG3_REGION118_Pos) /*!< Bit mask of REGION118 field. */
797 #define BPROT_CONFIG3_REGION118_Disabled (0UL) /*!< Protection disabled */
798 #define BPROT_CONFIG3_REGION118_Enabled (1UL) /*!< Protection enabled */
799 
800 /* Bit 21 : Enable protection for region 117. Write '0' has no effect. */
801 #define BPROT_CONFIG3_REGION117_Pos (21UL) /*!< Position of REGION117 field. */
802 #define BPROT_CONFIG3_REGION117_Msk (0x1UL << BPROT_CONFIG3_REGION117_Pos) /*!< Bit mask of REGION117 field. */
803 #define BPROT_CONFIG3_REGION117_Disabled (0UL) /*!< Protection disabled */
804 #define BPROT_CONFIG3_REGION117_Enabled (1UL) /*!< Protection enabled */
805 
806 /* Bit 20 : Enable protection for region 116. Write '0' has no effect. */
807 #define BPROT_CONFIG3_REGION116_Pos (20UL) /*!< Position of REGION116 field. */
808 #define BPROT_CONFIG3_REGION116_Msk (0x1UL << BPROT_CONFIG3_REGION116_Pos) /*!< Bit mask of REGION116 field. */
809 #define BPROT_CONFIG3_REGION116_Disabled (0UL) /*!< Protection disabled */
810 #define BPROT_CONFIG3_REGION116_Enabled (1UL) /*!< Protection enabled */
811 
812 /* Bit 19 : Enable protection for region 115. Write '0' has no effect. */
813 #define BPROT_CONFIG3_REGION115_Pos (19UL) /*!< Position of REGION115 field. */
814 #define BPROT_CONFIG3_REGION115_Msk (0x1UL << BPROT_CONFIG3_REGION115_Pos) /*!< Bit mask of REGION115 field. */
815 #define BPROT_CONFIG3_REGION115_Disabled (0UL) /*!< Protection disabled */
816 #define BPROT_CONFIG3_REGION115_Enabled (1UL) /*!< Protection enabled */
817 
818 /* Bit 18 : Enable protection for region 114. Write '0' has no effect. */
819 #define BPROT_CONFIG3_REGION114_Pos (18UL) /*!< Position of REGION114 field. */
820 #define BPROT_CONFIG3_REGION114_Msk (0x1UL << BPROT_CONFIG3_REGION114_Pos) /*!< Bit mask of REGION114 field. */
821 #define BPROT_CONFIG3_REGION114_Disabled (0UL) /*!< Protection disabled */
822 #define BPROT_CONFIG3_REGION114_Enabled (1UL) /*!< Protection enabled */
823 
824 /* Bit 17 : Enable protection for region 113. Write '0' has no effect. */
825 #define BPROT_CONFIG3_REGION113_Pos (17UL) /*!< Position of REGION113 field. */
826 #define BPROT_CONFIG3_REGION113_Msk (0x1UL << BPROT_CONFIG3_REGION113_Pos) /*!< Bit mask of REGION113 field. */
827 #define BPROT_CONFIG3_REGION113_Disabled (0UL) /*!< Protection disabled */
828 #define BPROT_CONFIG3_REGION113_Enabled (1UL) /*!< Protection enabled */
829 
830 /* Bit 16 : Enable protection for region 112. Write '0' has no effect. */
831 #define BPROT_CONFIG3_REGION112_Pos (16UL) /*!< Position of REGION112 field. */
832 #define BPROT_CONFIG3_REGION112_Msk (0x1UL << BPROT_CONFIG3_REGION112_Pos) /*!< Bit mask of REGION112 field. */
833 #define BPROT_CONFIG3_REGION112_Disabled (0UL) /*!< Protection disabled */
834 #define BPROT_CONFIG3_REGION112_Enabled (1UL) /*!< Protection enabled */
835 
836 /* Bit 15 : Enable protection for region 111. Write '0' has no effect. */
837 #define BPROT_CONFIG3_REGION111_Pos (15UL) /*!< Position of REGION111 field. */
838 #define BPROT_CONFIG3_REGION111_Msk (0x1UL << BPROT_CONFIG3_REGION111_Pos) /*!< Bit mask of REGION111 field. */
839 #define BPROT_CONFIG3_REGION111_Disabled (0UL) /*!< Protection disabled */
840 #define BPROT_CONFIG3_REGION111_Enabled (1UL) /*!< Protection enabled */
841 
842 /* Bit 14 : Enable protection for region 110. Write '0' has no effect. */
843 #define BPROT_CONFIG3_REGION110_Pos (14UL) /*!< Position of REGION110 field. */
844 #define BPROT_CONFIG3_REGION110_Msk (0x1UL << BPROT_CONFIG3_REGION110_Pos) /*!< Bit mask of REGION110 field. */
845 #define BPROT_CONFIG3_REGION110_Disabled (0UL) /*!< Protection disabled */
846 #define BPROT_CONFIG3_REGION110_Enabled (1UL) /*!< Protection enabled */
847 
848 /* Bit 13 : Enable protection for region 109. Write '0' has no effect. */
849 #define BPROT_CONFIG3_REGION109_Pos (13UL) /*!< Position of REGION109 field. */
850 #define BPROT_CONFIG3_REGION109_Msk (0x1UL << BPROT_CONFIG3_REGION109_Pos) /*!< Bit mask of REGION109 field. */
851 #define BPROT_CONFIG3_REGION109_Disabled (0UL) /*!< Protection disabled */
852 #define BPROT_CONFIG3_REGION109_Enabled (1UL) /*!< Protection enabled */
853 
854 /* Bit 12 : Enable protection for region 108. Write '0' has no effect. */
855 #define BPROT_CONFIG3_REGION108_Pos (12UL) /*!< Position of REGION108 field. */
856 #define BPROT_CONFIG3_REGION108_Msk (0x1UL << BPROT_CONFIG3_REGION108_Pos) /*!< Bit mask of REGION108 field. */
857 #define BPROT_CONFIG3_REGION108_Disabled (0UL) /*!< Protection disabled */
858 #define BPROT_CONFIG3_REGION108_Enabled (1UL) /*!< Protection enabled */
859 
860 /* Bit 11 : Enable protection for region 107. Write '0' has no effect. */
861 #define BPROT_CONFIG3_REGION107_Pos (11UL) /*!< Position of REGION107 field. */
862 #define BPROT_CONFIG3_REGION107_Msk (0x1UL << BPROT_CONFIG3_REGION107_Pos) /*!< Bit mask of REGION107 field. */
863 #define BPROT_CONFIG3_REGION107_Disabled (0UL) /*!< Protection disabled */
864 #define BPROT_CONFIG3_REGION107_Enabled (1UL) /*!< Protection enabled */
865 
866 /* Bit 10 : Enable protection for region 106. Write '0' has no effect. */
867 #define BPROT_CONFIG3_REGION106_Pos (10UL) /*!< Position of REGION106 field. */
868 #define BPROT_CONFIG3_REGION106_Msk (0x1UL << BPROT_CONFIG3_REGION106_Pos) /*!< Bit mask of REGION106 field. */
869 #define BPROT_CONFIG3_REGION106_Disabled (0UL) /*!< Protection disabled */
870 #define BPROT_CONFIG3_REGION106_Enabled (1UL) /*!< Protection enabled */
871 
872 /* Bit 9 : Enable protection for region 105. Write '0' has no effect. */
873 #define BPROT_CONFIG3_REGION105_Pos (9UL) /*!< Position of REGION105 field. */
874 #define BPROT_CONFIG3_REGION105_Msk (0x1UL << BPROT_CONFIG3_REGION105_Pos) /*!< Bit mask of REGION105 field. */
875 #define BPROT_CONFIG3_REGION105_Disabled (0UL) /*!< Protection disabled */
876 #define BPROT_CONFIG3_REGION105_Enabled (1UL) /*!< Protection enabled */
877 
878 /* Bit 8 : Enable protection for region 104. Write '0' has no effect. */
879 #define BPROT_CONFIG3_REGION104_Pos (8UL) /*!< Position of REGION104 field. */
880 #define BPROT_CONFIG3_REGION104_Msk (0x1UL << BPROT_CONFIG3_REGION104_Pos) /*!< Bit mask of REGION104 field. */
881 #define BPROT_CONFIG3_REGION104_Disabled (0UL) /*!< Protection disabled */
882 #define BPROT_CONFIG3_REGION104_Enabled (1UL) /*!< Protection enabled */
883 
884 /* Bit 7 : Enable protection for region 103. Write '0' has no effect. */
885 #define BPROT_CONFIG3_REGION103_Pos (7UL) /*!< Position of REGION103 field. */
886 #define BPROT_CONFIG3_REGION103_Msk (0x1UL << BPROT_CONFIG3_REGION103_Pos) /*!< Bit mask of REGION103 field. */
887 #define BPROT_CONFIG3_REGION103_Disabled (0UL) /*!< Protection disabled */
888 #define BPROT_CONFIG3_REGION103_Enabled (1UL) /*!< Protection enabled */
889 
890 /* Bit 6 : Enable protection for region 102. Write '0' has no effect. */
891 #define BPROT_CONFIG3_REGION102_Pos (6UL) /*!< Position of REGION102 field. */
892 #define BPROT_CONFIG3_REGION102_Msk (0x1UL << BPROT_CONFIG3_REGION102_Pos) /*!< Bit mask of REGION102 field. */
893 #define BPROT_CONFIG3_REGION102_Disabled (0UL) /*!< Protection disabled */
894 #define BPROT_CONFIG3_REGION102_Enabled (1UL) /*!< Protection enabled */
895 
896 /* Bit 5 : Enable protection for region 101. Write '0' has no effect. */
897 #define BPROT_CONFIG3_REGION101_Pos (5UL) /*!< Position of REGION101 field. */
898 #define BPROT_CONFIG3_REGION101_Msk (0x1UL << BPROT_CONFIG3_REGION101_Pos) /*!< Bit mask of REGION101 field. */
899 #define BPROT_CONFIG3_REGION101_Disabled (0UL) /*!< Protection disabled */
900 #define BPROT_CONFIG3_REGION101_Enabled (1UL) /*!< Protection enabled */
901 
902 /* Bit 4 : Enable protection for region 100. Write '0' has no effect. */
903 #define BPROT_CONFIG3_REGION100_Pos (4UL) /*!< Position of REGION100 field. */
904 #define BPROT_CONFIG3_REGION100_Msk (0x1UL << BPROT_CONFIG3_REGION100_Pos) /*!< Bit mask of REGION100 field. */
905 #define BPROT_CONFIG3_REGION100_Disabled (0UL) /*!< Protection disabled */
906 #define BPROT_CONFIG3_REGION100_Enabled (1UL) /*!< Protection enabled */
907 
908 /* Bit 3 : Enable protection for region 99. Write '0' has no effect. */
909 #define BPROT_CONFIG3_REGION99_Pos (3UL) /*!< Position of REGION99 field. */
910 #define BPROT_CONFIG3_REGION99_Msk (0x1UL << BPROT_CONFIG3_REGION99_Pos) /*!< Bit mask of REGION99 field. */
911 #define BPROT_CONFIG3_REGION99_Disabled (0UL) /*!< Protection disabled */
912 #define BPROT_CONFIG3_REGION99_Enabled (1UL) /*!< Protection enabled */
913 
914 /* Bit 2 : Enable protection for region 98. Write '0' has no effect. */
915 #define BPROT_CONFIG3_REGION98_Pos (2UL) /*!< Position of REGION98 field. */
916 #define BPROT_CONFIG3_REGION98_Msk (0x1UL << BPROT_CONFIG3_REGION98_Pos) /*!< Bit mask of REGION98 field. */
917 #define BPROT_CONFIG3_REGION98_Disabled (0UL) /*!< Protection disabled */
918 #define BPROT_CONFIG3_REGION98_Enabled (1UL) /*!< Protection enabled */
919 
920 /* Bit 1 : Enable protection for region 97. Write '0' has no effect. */
921 #define BPROT_CONFIG3_REGION97_Pos (1UL) /*!< Position of REGION97 field. */
922 #define BPROT_CONFIG3_REGION97_Msk (0x1UL << BPROT_CONFIG3_REGION97_Pos) /*!< Bit mask of REGION97 field. */
923 #define BPROT_CONFIG3_REGION97_Disabled (0UL) /*!< Protection disabled */
924 #define BPROT_CONFIG3_REGION97_Enabled (1UL) /*!< Protection enabled */
925 
926 /* Bit 0 : Enable protection for region 96. Write '0' has no effect. */
927 #define BPROT_CONFIG3_REGION96_Pos (0UL) /*!< Position of REGION96 field. */
928 #define BPROT_CONFIG3_REGION96_Msk (0x1UL << BPROT_CONFIG3_REGION96_Pos) /*!< Bit mask of REGION96 field. */
929 #define BPROT_CONFIG3_REGION96_Disabled (0UL) /*!< Protection disabled */
930 #define BPROT_CONFIG3_REGION96_Enabled (1UL) /*!< Protection enabled */
931 
932 
933 /* Peripheral: CCM */
934 /* Description: AES CCM Mode Encryption */
935 
936 /* Register: CCM_SHORTS */
937 /* Description: Shortcut register */
938 
939 /* Bit 0 : Shortcut between ENDKSGEN event and CRYPT task */
940 #define CCM_SHORTS_ENDKSGEN_CRYPT_Pos (0UL) /*!< Position of ENDKSGEN_CRYPT field. */
941 #define CCM_SHORTS_ENDKSGEN_CRYPT_Msk (0x1UL << CCM_SHORTS_ENDKSGEN_CRYPT_Pos) /*!< Bit mask of ENDKSGEN_CRYPT field. */
942 #define CCM_SHORTS_ENDKSGEN_CRYPT_Disabled (0UL) /*!< Disable shortcut */
943 #define CCM_SHORTS_ENDKSGEN_CRYPT_Enabled (1UL) /*!< Enable shortcut */
944 
945 /* Register: CCM_INTENSET */
946 /* Description: Enable interrupt */
947 
948 /* Bit 2 : Write '1' to Enable interrupt for ERROR event */
949 #define CCM_INTENSET_ERROR_Pos (2UL) /*!< Position of ERROR field. */
950 #define CCM_INTENSET_ERROR_Msk (0x1UL << CCM_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
951 #define CCM_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
952 #define CCM_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
953 #define CCM_INTENSET_ERROR_Set (1UL) /*!< Enable */
954 
955 /* Bit 1 : Write '1' to Enable interrupt for ENDCRYPT event */
956 #define CCM_INTENSET_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */
957 #define CCM_INTENSET_ENDCRYPT_Msk (0x1UL << CCM_INTENSET_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */
958 #define CCM_INTENSET_ENDCRYPT_Disabled (0UL) /*!< Read: Disabled */
959 #define CCM_INTENSET_ENDCRYPT_Enabled (1UL) /*!< Read: Enabled */
960 #define CCM_INTENSET_ENDCRYPT_Set (1UL) /*!< Enable */
961 
962 /* Bit 0 : Write '1' to Enable interrupt for ENDKSGEN event */
963 #define CCM_INTENSET_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */
964 #define CCM_INTENSET_ENDKSGEN_Msk (0x1UL << CCM_INTENSET_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */
965 #define CCM_INTENSET_ENDKSGEN_Disabled (0UL) /*!< Read: Disabled */
966 #define CCM_INTENSET_ENDKSGEN_Enabled (1UL) /*!< Read: Enabled */
967 #define CCM_INTENSET_ENDKSGEN_Set (1UL) /*!< Enable */
968 
969 /* Register: CCM_INTENCLR */
970 /* Description: Disable interrupt */
971 
972 /* Bit 2 : Write '1' to Disable interrupt for ERROR event */
973 #define CCM_INTENCLR_ERROR_Pos (2UL) /*!< Position of ERROR field. */
974 #define CCM_INTENCLR_ERROR_Msk (0x1UL << CCM_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
975 #define CCM_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
976 #define CCM_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
977 #define CCM_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
978 
979 /* Bit 1 : Write '1' to Disable interrupt for ENDCRYPT event */
980 #define CCM_INTENCLR_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */
981 #define CCM_INTENCLR_ENDCRYPT_Msk (0x1UL << CCM_INTENCLR_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */
982 #define CCM_INTENCLR_ENDCRYPT_Disabled (0UL) /*!< Read: Disabled */
983 #define CCM_INTENCLR_ENDCRYPT_Enabled (1UL) /*!< Read: Enabled */
984 #define CCM_INTENCLR_ENDCRYPT_Clear (1UL) /*!< Disable */
985 
986 /* Bit 0 : Write '1' to Disable interrupt for ENDKSGEN event */
987 #define CCM_INTENCLR_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */
988 #define CCM_INTENCLR_ENDKSGEN_Msk (0x1UL << CCM_INTENCLR_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */
989 #define CCM_INTENCLR_ENDKSGEN_Disabled (0UL) /*!< Read: Disabled */
990 #define CCM_INTENCLR_ENDKSGEN_Enabled (1UL) /*!< Read: Enabled */
991 #define CCM_INTENCLR_ENDKSGEN_Clear (1UL) /*!< Disable */
992 
993 /* Register: CCM_MICSTATUS */
994 /* Description: MIC check result */
995 
996 /* Bit 0 : The result of the MIC check performed during the previous decryption operation */
997 #define CCM_MICSTATUS_MICSTATUS_Pos (0UL) /*!< Position of MICSTATUS field. */
998 #define CCM_MICSTATUS_MICSTATUS_Msk (0x1UL << CCM_MICSTATUS_MICSTATUS_Pos) /*!< Bit mask of MICSTATUS field. */
999 #define CCM_MICSTATUS_MICSTATUS_CheckFailed (0UL) /*!< MIC check failed */
1000 #define CCM_MICSTATUS_MICSTATUS_CheckPassed (1UL) /*!< MIC check passed */
1001 
1002 /* Register: CCM_ENABLE */
1003 /* Description: Enable */
1004 
1005 /* Bits 1..0 : Enable or disable CCM */
1006 #define CCM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
1007 #define CCM_ENABLE_ENABLE_Msk (0x3UL << CCM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
1008 #define CCM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
1009 #define CCM_ENABLE_ENABLE_Enabled (2UL) /*!< Enable */
1010 
1011 /* Register: CCM_MODE */
1012 /* Description: Operation mode */
1013 
1014 /* Bit 24 : Packet length configuration */
1015 #define CCM_MODE_LENGTH_Pos (24UL) /*!< Position of LENGTH field. */
1016 #define CCM_MODE_LENGTH_Msk (0x1UL << CCM_MODE_LENGTH_Pos) /*!< Bit mask of LENGTH field. */
1017 #define CCM_MODE_LENGTH_Default (0UL) /*!< Default length. Effective length of LENGTH field is 5-bit */
1018 #define CCM_MODE_LENGTH_Extended (1UL) /*!< Extended length. Effective length of LENGTH field is 8-bit */
1019 
1020 /* Bit 16 : Data rate that the CCM shall run in synch with */
1021 #define CCM_MODE_DATARATE_Pos (16UL) /*!< Position of DATARATE field. */
1022 #define CCM_MODE_DATARATE_Msk (0x1UL << CCM_MODE_DATARATE_Pos) /*!< Bit mask of DATARATE field. */
1023 #define CCM_MODE_DATARATE_1Mbit (0UL) /*!< In synch with 1 Mbit data rate */
1024 #define CCM_MODE_DATARATE_2Mbit (1UL) /*!< In synch with 2 Mbit data rate */
1025 
1026 /* Bit 0 : The mode of operation to be used */
1027 #define CCM_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
1028 #define CCM_MODE_MODE_Msk (0x1UL << CCM_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
1029 #define CCM_MODE_MODE_Encryption (0UL) /*!< AES CCM packet encryption mode */
1030 #define CCM_MODE_MODE_Decryption (1UL) /*!< AES CCM packet decryption mode */
1031 
1032 /* Register: CCM_CNFPTR */
1033 /* Description: Pointer to data structure holding AES key and NONCE vector */
1034 
1035 /* Bits 31..0 : Pointer to the data structure holding the AES key and the CCM NONCE vector (see Table 1 CCM data structure overview) */
1036 #define CCM_CNFPTR_CNFPTR_Pos (0UL) /*!< Position of CNFPTR field. */
1037 #define CCM_CNFPTR_CNFPTR_Msk (0xFFFFFFFFUL << CCM_CNFPTR_CNFPTR_Pos) /*!< Bit mask of CNFPTR field. */
1038 
1039 /* Register: CCM_INPTR */
1040 /* Description: Input pointer */
1041 
1042 /* Bits 31..0 : Input pointer */
1043 #define CCM_INPTR_INPTR_Pos (0UL) /*!< Position of INPTR field. */
1044 #define CCM_INPTR_INPTR_Msk (0xFFFFFFFFUL << CCM_INPTR_INPTR_Pos) /*!< Bit mask of INPTR field. */
1045 
1046 /* Register: CCM_OUTPTR */
1047 /* Description: Output pointer */
1048 
1049 /* Bits 31..0 : Output pointer */
1050 #define CCM_OUTPTR_OUTPTR_Pos (0UL) /*!< Position of OUTPTR field. */
1051 #define CCM_OUTPTR_OUTPTR_Msk (0xFFFFFFFFUL << CCM_OUTPTR_OUTPTR_Pos) /*!< Bit mask of OUTPTR field. */
1052 
1053 /* Register: CCM_SCRATCHPTR */
1054 /* Description: Pointer to data area used for temporary storage */
1055 
1056 /* Bits 31..0 : Pointer to a scratch data area used for temporary storage during key-stream generation, MIC generation and encryption/decryption. */
1057 #define CCM_SCRATCHPTR_SCRATCHPTR_Pos (0UL) /*!< Position of SCRATCHPTR field. */
1058 #define CCM_SCRATCHPTR_SCRATCHPTR_Msk (0xFFFFFFFFUL << CCM_SCRATCHPTR_SCRATCHPTR_Pos) /*!< Bit mask of SCRATCHPTR field. */
1059 
1060 
1061 /* Peripheral: CLOCK */
1062 /* Description: Clock control */
1063 
1064 /* Register: CLOCK_INTENSET */
1065 /* Description: Enable interrupt */
1066 
1067 /* Bit 4 : Write '1' to Enable interrupt for CTTO event */
1068 #define CLOCK_INTENSET_CTTO_Pos (4UL) /*!< Position of CTTO field. */
1069 #define CLOCK_INTENSET_CTTO_Msk (0x1UL << CLOCK_INTENSET_CTTO_Pos) /*!< Bit mask of CTTO field. */
1070 #define CLOCK_INTENSET_CTTO_Disabled (0UL) /*!< Read: Disabled */
1071 #define CLOCK_INTENSET_CTTO_Enabled (1UL) /*!< Read: Enabled */
1072 #define CLOCK_INTENSET_CTTO_Set (1UL) /*!< Enable */
1073 
1074 /* Bit 3 : Write '1' to Enable interrupt for DONE event */
1075 #define CLOCK_INTENSET_DONE_Pos (3UL) /*!< Position of DONE field. */
1076 #define CLOCK_INTENSET_DONE_Msk (0x1UL << CLOCK_INTENSET_DONE_Pos) /*!< Bit mask of DONE field. */
1077 #define CLOCK_INTENSET_DONE_Disabled (0UL) /*!< Read: Disabled */
1078 #define CLOCK_INTENSET_DONE_Enabled (1UL) /*!< Read: Enabled */
1079 #define CLOCK_INTENSET_DONE_Set (1UL) /*!< Enable */
1080 
1081 /* Bit 1 : Write '1' to Enable interrupt for LFCLKSTARTED event */
1082 #define CLOCK_INTENSET_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */
1083 #define CLOCK_INTENSET_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */
1084 #define CLOCK_INTENSET_LFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
1085 #define CLOCK_INTENSET_LFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
1086 #define CLOCK_INTENSET_LFCLKSTARTED_Set (1UL) /*!< Enable */
1087 
1088 /* Bit 0 : Write '1' to Enable interrupt for HFCLKSTARTED event */
1089 #define CLOCK_INTENSET_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */
1090 #define CLOCK_INTENSET_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */
1091 #define CLOCK_INTENSET_HFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
1092 #define CLOCK_INTENSET_HFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
1093 #define CLOCK_INTENSET_HFCLKSTARTED_Set (1UL) /*!< Enable */
1094 
1095 /* Register: CLOCK_INTENCLR */
1096 /* Description: Disable interrupt */
1097 
1098 /* Bit 4 : Write '1' to Disable interrupt for CTTO event */
1099 #define CLOCK_INTENCLR_CTTO_Pos (4UL) /*!< Position of CTTO field. */
1100 #define CLOCK_INTENCLR_CTTO_Msk (0x1UL << CLOCK_INTENCLR_CTTO_Pos) /*!< Bit mask of CTTO field. */
1101 #define CLOCK_INTENCLR_CTTO_Disabled (0UL) /*!< Read: Disabled */
1102 #define CLOCK_INTENCLR_CTTO_Enabled (1UL) /*!< Read: Enabled */
1103 #define CLOCK_INTENCLR_CTTO_Clear (1UL) /*!< Disable */
1104 
1105 /* Bit 3 : Write '1' to Disable interrupt for DONE event */
1106 #define CLOCK_INTENCLR_DONE_Pos (3UL) /*!< Position of DONE field. */
1107 #define CLOCK_INTENCLR_DONE_Msk (0x1UL << CLOCK_INTENCLR_DONE_Pos) /*!< Bit mask of DONE field. */
1108 #define CLOCK_INTENCLR_DONE_Disabled (0UL) /*!< Read: Disabled */
1109 #define CLOCK_INTENCLR_DONE_Enabled (1UL) /*!< Read: Enabled */
1110 #define CLOCK_INTENCLR_DONE_Clear (1UL) /*!< Disable */
1111 
1112 /* Bit 1 : Write '1' to Disable interrupt for LFCLKSTARTED event */
1113 #define CLOCK_INTENCLR_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */
1114 #define CLOCK_INTENCLR_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */
1115 #define CLOCK_INTENCLR_LFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
1116 #define CLOCK_INTENCLR_LFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
1117 #define CLOCK_INTENCLR_LFCLKSTARTED_Clear (1UL) /*!< Disable */
1118 
1119 /* Bit 0 : Write '1' to Disable interrupt for HFCLKSTARTED event */
1120 #define CLOCK_INTENCLR_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */
1121 #define CLOCK_INTENCLR_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */
1122 #define CLOCK_INTENCLR_HFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
1123 #define CLOCK_INTENCLR_HFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
1124 #define CLOCK_INTENCLR_HFCLKSTARTED_Clear (1UL) /*!< Disable */
1125 
1126 /* Register: CLOCK_HFCLKRUN */
1127 /* Description: Status indicating that HFCLKSTART task has been triggered */
1128 
1129 /* Bit 0 : HFCLKSTART task triggered or not */
1130 #define CLOCK_HFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */
1131 #define CLOCK_HFCLKRUN_STATUS_Msk (0x1UL << CLOCK_HFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */
1132 #define CLOCK_HFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task not triggered */
1133 #define CLOCK_HFCLKRUN_STATUS_Triggered (1UL) /*!< Task triggered */
1134 
1135 /* Register: CLOCK_HFCLKSTAT */
1136 /* Description: HFCLK status */
1137 
1138 /* Bit 16 : HFCLK state */
1139 #define CLOCK_HFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */
1140 #define CLOCK_HFCLKSTAT_STATE_Msk (0x1UL << CLOCK_HFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */
1141 #define CLOCK_HFCLKSTAT_STATE_NotRunning (0UL) /*!< HFCLK not running */
1142 #define CLOCK_HFCLKSTAT_STATE_Running (1UL) /*!< HFCLK running */
1143 
1144 /* Bit 0 : Source of HFCLK */
1145 #define CLOCK_HFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */
1146 #define CLOCK_HFCLKSTAT_SRC_Msk (0x1UL << CLOCK_HFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */
1147 #define CLOCK_HFCLKSTAT_SRC_RC (0UL) /*!< 64 MHz internal oscillator (HFINT) */
1148 #define CLOCK_HFCLKSTAT_SRC_Xtal (1UL) /*!< 64 MHz crystal oscillator (HFXO) */
1149 
1150 /* Register: CLOCK_LFCLKRUN */
1151 /* Description: Status indicating that LFCLKSTART task has been triggered */
1152 
1153 /* Bit 0 : LFCLKSTART task triggered or not */
1154 #define CLOCK_LFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */
1155 #define CLOCK_LFCLKRUN_STATUS_Msk (0x1UL << CLOCK_LFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */
1156 #define CLOCK_LFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task not triggered */
1157 #define CLOCK_LFCLKRUN_STATUS_Triggered (1UL) /*!< Task triggered */
1158 
1159 /* Register: CLOCK_LFCLKSTAT */
1160 /* Description: LFCLK status */
1161 
1162 /* Bit 16 : LFCLK state */
1163 #define CLOCK_LFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */
1164 #define CLOCK_LFCLKSTAT_STATE_Msk (0x1UL << CLOCK_LFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */
1165 #define CLOCK_LFCLKSTAT_STATE_NotRunning (0UL) /*!< LFCLK not running */
1166 #define CLOCK_LFCLKSTAT_STATE_Running (1UL) /*!< LFCLK running */
1167 
1168 /* Bits 1..0 : Source of LFCLK */
1169 #define CLOCK_LFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */
1170 #define CLOCK_LFCLKSTAT_SRC_Msk (0x3UL << CLOCK_LFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */
1171 #define CLOCK_LFCLKSTAT_SRC_RC (0UL) /*!< 32.768 kHz RC oscillator */
1172 #define CLOCK_LFCLKSTAT_SRC_Xtal (1UL) /*!< 32.768 kHz crystal oscillator */
1173 #define CLOCK_LFCLKSTAT_SRC_Synth (2UL) /*!< 32.768 kHz synthesized from HFCLK */
1174 
1175 /* Register: CLOCK_LFCLKSRCCOPY */
1176 /* Description: Copy of LFCLKSRC register, set when LFCLKSTART task was triggered */
1177 
1178 /* Bits 1..0 : Clock source */
1179 #define CLOCK_LFCLKSRCCOPY_SRC_Pos (0UL) /*!< Position of SRC field. */
1180 #define CLOCK_LFCLKSRCCOPY_SRC_Msk (0x3UL << CLOCK_LFCLKSRCCOPY_SRC_Pos) /*!< Bit mask of SRC field. */
1181 #define CLOCK_LFCLKSRCCOPY_SRC_RC (0UL) /*!< 32.768 kHz RC oscillator */
1182 #define CLOCK_LFCLKSRCCOPY_SRC_Xtal (1UL) /*!< 32.768 kHz crystal oscillator */
1183 #define CLOCK_LFCLKSRCCOPY_SRC_Synth (2UL) /*!< 32.768 kHz synthesized from HFCLK */
1184 
1185 /* Register: CLOCK_LFCLKSRC */
1186 /* Description: Clock source for the LFCLK */
1187 
1188 /* Bit 17 : Enable or disable external source for LFCLK */
1189 #define CLOCK_LFCLKSRC_EXTERNAL_Pos (17UL) /*!< Position of EXTERNAL field. */
1190 #define CLOCK_LFCLKSRC_EXTERNAL_Msk (0x1UL << CLOCK_LFCLKSRC_EXTERNAL_Pos) /*!< Bit mask of EXTERNAL field. */
1191 #define CLOCK_LFCLKSRC_EXTERNAL_Disabled (0UL) /*!< Disable external source (use with Xtal) */
1192 #define CLOCK_LFCLKSRC_EXTERNAL_Enabled (1UL) /*!< Enable use of external source instead of Xtal (SRC needs to be set to Xtal) */
1193 
1194 /* Bit 16 : Enable or disable bypass of LFCLK crystal oscillator with external clock source */
1195 #define CLOCK_LFCLKSRC_BYPASS_Pos (16UL) /*!< Position of BYPASS field. */
1196 #define CLOCK_LFCLKSRC_BYPASS_Msk (0x1UL << CLOCK_LFCLKSRC_BYPASS_Pos) /*!< Bit mask of BYPASS field. */
1197 #define CLOCK_LFCLKSRC_BYPASS_Disabled (0UL) /*!< Disable (use with Xtal or low-swing external source) */
1198 #define CLOCK_LFCLKSRC_BYPASS_Enabled (1UL) /*!< Enable (use with rail-to-rail external source) */
1199 
1200 /* Bits 1..0 : Clock source */
1201 #define CLOCK_LFCLKSRC_SRC_Pos (0UL) /*!< Position of SRC field. */
1202 #define CLOCK_LFCLKSRC_SRC_Msk (0x3UL << CLOCK_LFCLKSRC_SRC_Pos) /*!< Bit mask of SRC field. */
1203 #define CLOCK_LFCLKSRC_SRC_RC (0UL) /*!< 32.768 kHz RC oscillator */
1204 #define CLOCK_LFCLKSRC_SRC_Xtal (1UL) /*!< 32.768 kHz crystal oscillator */
1205 #define CLOCK_LFCLKSRC_SRC_Synth (2UL) /*!< 32.768 kHz synthesized from HFCLK */
1206 
1207 /* Register: CLOCK_CTIV */
1208 /* Description: Calibration timer interval */
1209 
1210 /* Bits 6..0 : Calibration timer interval in multiple of 0.25 seconds. Range: 0.25 seconds to 31.75 seconds. */
1211 #define CLOCK_CTIV_CTIV_Pos (0UL) /*!< Position of CTIV field. */
1212 #define CLOCK_CTIV_CTIV_Msk (0x7FUL << CLOCK_CTIV_CTIV_Pos) /*!< Bit mask of CTIV field. */
1213 
1214 /* Register: CLOCK_TRACECONFIG */
1215 /* Description: Clocking options for the Trace Port debug interface */
1216 
1217 /* Bits 17..16 : Pin multiplexing of trace signals. */
1218 #define CLOCK_TRACECONFIG_TRACEMUX_Pos (16UL) /*!< Position of TRACEMUX field. */
1219 #define CLOCK_TRACECONFIG_TRACEMUX_Msk (0x3UL << CLOCK_TRACECONFIG_TRACEMUX_Pos) /*!< Bit mask of TRACEMUX field. */
1220 #define CLOCK_TRACECONFIG_TRACEMUX_GPIO (0UL) /*!< GPIOs multiplexed onto all trace-pins */
1221 #define CLOCK_TRACECONFIG_TRACEMUX_Serial (1UL) /*!< SWO multiplexed onto P0.18, GPIO multiplexed onto other trace pins */
1222 #define CLOCK_TRACECONFIG_TRACEMUX_Parallel (2UL) /*!< TRACECLK and TRACEDATA multiplexed onto P0.20, P0.18, P0.16, P0.15 and P0.14. */
1223 
1224 /* Bits 1..0 : Speed of Trace Port clock. Note that the TRACECLK pin will output this clock divided by two. */
1225 #define CLOCK_TRACECONFIG_TRACEPORTSPEED_Pos (0UL) /*!< Position of TRACEPORTSPEED field. */
1226 #define CLOCK_TRACECONFIG_TRACEPORTSPEED_Msk (0x3UL << CLOCK_TRACECONFIG_TRACEPORTSPEED_Pos) /*!< Bit mask of TRACEPORTSPEED field. */
1227 #define CLOCK_TRACECONFIG_TRACEPORTSPEED_32MHz (0UL) /*!< 32 MHz Trace Port clock (TRACECLK = 16 MHz) */
1228 #define CLOCK_TRACECONFIG_TRACEPORTSPEED_16MHz (1UL) /*!< 16 MHz Trace Port clock (TRACECLK = 8 MHz) */
1229 #define CLOCK_TRACECONFIG_TRACEPORTSPEED_8MHz (2UL) /*!< 8 MHz Trace Port clock (TRACECLK = 4 MHz) */
1230 #define CLOCK_TRACECONFIG_TRACEPORTSPEED_4MHz (3UL) /*!< 4 MHz Trace Port clock (TRACECLK = 2 MHz) */
1231 
1232 
1233 /* Peripheral: COMP */
1234 /* Description: Comparator */
1235 
1236 /* Register: COMP_SHORTS */
1237 /* Description: Shortcut register */
1238 
1239 /* Bit 4 : Shortcut between CROSS event and STOP task */
1240 #define COMP_SHORTS_CROSS_STOP_Pos (4UL) /*!< Position of CROSS_STOP field. */
1241 #define COMP_SHORTS_CROSS_STOP_Msk (0x1UL << COMP_SHORTS_CROSS_STOP_Pos) /*!< Bit mask of CROSS_STOP field. */
1242 #define COMP_SHORTS_CROSS_STOP_Disabled (0UL) /*!< Disable shortcut */
1243 #define COMP_SHORTS_CROSS_STOP_Enabled (1UL) /*!< Enable shortcut */
1244 
1245 /* Bit 3 : Shortcut between UP event and STOP task */
1246 #define COMP_SHORTS_UP_STOP_Pos (3UL) /*!< Position of UP_STOP field. */
1247 #define COMP_SHORTS_UP_STOP_Msk (0x1UL << COMP_SHORTS_UP_STOP_Pos) /*!< Bit mask of UP_STOP field. */
1248 #define COMP_SHORTS_UP_STOP_Disabled (0UL) /*!< Disable shortcut */
1249 #define COMP_SHORTS_UP_STOP_Enabled (1UL) /*!< Enable shortcut */
1250 
1251 /* Bit 2 : Shortcut between DOWN event and STOP task */
1252 #define COMP_SHORTS_DOWN_STOP_Pos (2UL) /*!< Position of DOWN_STOP field. */
1253 #define COMP_SHORTS_DOWN_STOP_Msk (0x1UL << COMP_SHORTS_DOWN_STOP_Pos) /*!< Bit mask of DOWN_STOP field. */
1254 #define COMP_SHORTS_DOWN_STOP_Disabled (0UL) /*!< Disable shortcut */
1255 #define COMP_SHORTS_DOWN_STOP_Enabled (1UL) /*!< Enable shortcut */
1256 
1257 /* Bit 1 : Shortcut between READY event and STOP task */
1258 #define COMP_SHORTS_READY_STOP_Pos (1UL) /*!< Position of READY_STOP field. */
1259 #define COMP_SHORTS_READY_STOP_Msk (0x1UL << COMP_SHORTS_READY_STOP_Pos) /*!< Bit mask of READY_STOP field. */
1260 #define COMP_SHORTS_READY_STOP_Disabled (0UL) /*!< Disable shortcut */
1261 #define COMP_SHORTS_READY_STOP_Enabled (1UL) /*!< Enable shortcut */
1262 
1263 /* Bit 0 : Shortcut between READY event and SAMPLE task */
1264 #define COMP_SHORTS_READY_SAMPLE_Pos (0UL) /*!< Position of READY_SAMPLE field. */
1265 #define COMP_SHORTS_READY_SAMPLE_Msk (0x1UL << COMP_SHORTS_READY_SAMPLE_Pos) /*!< Bit mask of READY_SAMPLE field. */
1266 #define COMP_SHORTS_READY_SAMPLE_Disabled (0UL) /*!< Disable shortcut */
1267 #define COMP_SHORTS_READY_SAMPLE_Enabled (1UL) /*!< Enable shortcut */
1268 
1269 /* Register: COMP_INTEN */
1270 /* Description: Enable or disable interrupt */
1271 
1272 /* Bit 3 : Enable or disable interrupt for CROSS event */
1273 #define COMP_INTEN_CROSS_Pos (3UL) /*!< Position of CROSS field. */
1274 #define COMP_INTEN_CROSS_Msk (0x1UL << COMP_INTEN_CROSS_Pos) /*!< Bit mask of CROSS field. */
1275 #define COMP_INTEN_CROSS_Disabled (0UL) /*!< Disable */
1276 #define COMP_INTEN_CROSS_Enabled (1UL) /*!< Enable */
1277 
1278 /* Bit 2 : Enable or disable interrupt for UP event */
1279 #define COMP_INTEN_UP_Pos (2UL) /*!< Position of UP field. */
1280 #define COMP_INTEN_UP_Msk (0x1UL << COMP_INTEN_UP_Pos) /*!< Bit mask of UP field. */
1281 #define COMP_INTEN_UP_Disabled (0UL) /*!< Disable */
1282 #define COMP_INTEN_UP_Enabled (1UL) /*!< Enable */
1283 
1284 /* Bit 1 : Enable or disable interrupt for DOWN event */
1285 #define COMP_INTEN_DOWN_Pos (1UL) /*!< Position of DOWN field. */
1286 #define COMP_INTEN_DOWN_Msk (0x1UL << COMP_INTEN_DOWN_Pos) /*!< Bit mask of DOWN field. */
1287 #define COMP_INTEN_DOWN_Disabled (0UL) /*!< Disable */
1288 #define COMP_INTEN_DOWN_Enabled (1UL) /*!< Enable */
1289 
1290 /* Bit 0 : Enable or disable interrupt for READY event */
1291 #define COMP_INTEN_READY_Pos (0UL) /*!< Position of READY field. */
1292 #define COMP_INTEN_READY_Msk (0x1UL << COMP_INTEN_READY_Pos) /*!< Bit mask of READY field. */
1293 #define COMP_INTEN_READY_Disabled (0UL) /*!< Disable */
1294 #define COMP_INTEN_READY_Enabled (1UL) /*!< Enable */
1295 
1296 /* Register: COMP_INTENSET */
1297 /* Description: Enable interrupt */
1298 
1299 /* Bit 3 : Write '1' to Enable interrupt for CROSS event */
1300 #define COMP_INTENSET_CROSS_Pos (3UL) /*!< Position of CROSS field. */
1301 #define COMP_INTENSET_CROSS_Msk (0x1UL << COMP_INTENSET_CROSS_Pos) /*!< Bit mask of CROSS field. */
1302 #define COMP_INTENSET_CROSS_Disabled (0UL) /*!< Read: Disabled */
1303 #define COMP_INTENSET_CROSS_Enabled (1UL) /*!< Read: Enabled */
1304 #define COMP_INTENSET_CROSS_Set (1UL) /*!< Enable */
1305 
1306 /* Bit 2 : Write '1' to Enable interrupt for UP event */
1307 #define COMP_INTENSET_UP_Pos (2UL) /*!< Position of UP field. */
1308 #define COMP_INTENSET_UP_Msk (0x1UL << COMP_INTENSET_UP_Pos) /*!< Bit mask of UP field. */
1309 #define COMP_INTENSET_UP_Disabled (0UL) /*!< Read: Disabled */
1310 #define COMP_INTENSET_UP_Enabled (1UL) /*!< Read: Enabled */
1311 #define COMP_INTENSET_UP_Set (1UL) /*!< Enable */
1312 
1313 /* Bit 1 : Write '1' to Enable interrupt for DOWN event */
1314 #define COMP_INTENSET_DOWN_Pos (1UL) /*!< Position of DOWN field. */
1315 #define COMP_INTENSET_DOWN_Msk (0x1UL << COMP_INTENSET_DOWN_Pos) /*!< Bit mask of DOWN field. */
1316 #define COMP_INTENSET_DOWN_Disabled (0UL) /*!< Read: Disabled */
1317 #define COMP_INTENSET_DOWN_Enabled (1UL) /*!< Read: Enabled */
1318 #define COMP_INTENSET_DOWN_Set (1UL) /*!< Enable */
1319 
1320 /* Bit 0 : Write '1' to Enable interrupt for READY event */
1321 #define COMP_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */
1322 #define COMP_INTENSET_READY_Msk (0x1UL << COMP_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
1323 #define COMP_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */
1324 #define COMP_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */
1325 #define COMP_INTENSET_READY_Set (1UL) /*!< Enable */
1326 
1327 /* Register: COMP_INTENCLR */
1328 /* Description: Disable interrupt */
1329 
1330 /* Bit 3 : Write '1' to Disable interrupt for CROSS event */
1331 #define COMP_INTENCLR_CROSS_Pos (3UL) /*!< Position of CROSS field. */
1332 #define COMP_INTENCLR_CROSS_Msk (0x1UL << COMP_INTENCLR_CROSS_Pos) /*!< Bit mask of CROSS field. */
1333 #define COMP_INTENCLR_CROSS_Disabled (0UL) /*!< Read: Disabled */
1334 #define COMP_INTENCLR_CROSS_Enabled (1UL) /*!< Read: Enabled */
1335 #define COMP_INTENCLR_CROSS_Clear (1UL) /*!< Disable */
1336 
1337 /* Bit 2 : Write '1' to Disable interrupt for UP event */
1338 #define COMP_INTENCLR_UP_Pos (2UL) /*!< Position of UP field. */
1339 #define COMP_INTENCLR_UP_Msk (0x1UL << COMP_INTENCLR_UP_Pos) /*!< Bit mask of UP field. */
1340 #define COMP_INTENCLR_UP_Disabled (0UL) /*!< Read: Disabled */
1341 #define COMP_INTENCLR_UP_Enabled (1UL) /*!< Read: Enabled */
1342 #define COMP_INTENCLR_UP_Clear (1UL) /*!< Disable */
1343 
1344 /* Bit 1 : Write '1' to Disable interrupt for DOWN event */
1345 #define COMP_INTENCLR_DOWN_Pos (1UL) /*!< Position of DOWN field. */
1346 #define COMP_INTENCLR_DOWN_Msk (0x1UL << COMP_INTENCLR_DOWN_Pos) /*!< Bit mask of DOWN field. */
1347 #define COMP_INTENCLR_DOWN_Disabled (0UL) /*!< Read: Disabled */
1348 #define COMP_INTENCLR_DOWN_Enabled (1UL) /*!< Read: Enabled */
1349 #define COMP_INTENCLR_DOWN_Clear (1UL) /*!< Disable */
1350 
1351 /* Bit 0 : Write '1' to Disable interrupt for READY event */
1352 #define COMP_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */
1353 #define COMP_INTENCLR_READY_Msk (0x1UL << COMP_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
1354 #define COMP_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */
1355 #define COMP_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */
1356 #define COMP_INTENCLR_READY_Clear (1UL) /*!< Disable */
1357 
1358 /* Register: COMP_RESULT */
1359 /* Description: Compare result */
1360 
1361 /* Bit 0 : Result of last compare. Decision point SAMPLE task. */
1362 #define COMP_RESULT_RESULT_Pos (0UL) /*!< Position of RESULT field. */
1363 #define COMP_RESULT_RESULT_Msk (0x1UL << COMP_RESULT_RESULT_Pos) /*!< Bit mask of RESULT field. */
1364 #define COMP_RESULT_RESULT_Below (0UL) /*!< Input voltage is below the threshold (VIN+ &lt; VIN-) */
1365 #define COMP_RESULT_RESULT_Above (1UL) /*!< Input voltage is above the threshold (VIN+ &gt; VIN-) */
1366 
1367 /* Register: COMP_ENABLE */
1368 /* Description: COMP enable */
1369 
1370 /* Bits 1..0 : Enable or disable COMP */
1371 #define COMP_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
1372 #define COMP_ENABLE_ENABLE_Msk (0x3UL << COMP_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
1373 #define COMP_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
1374 #define COMP_ENABLE_ENABLE_Enabled (2UL) /*!< Enable */
1375 
1376 /* Register: COMP_PSEL */
1377 /* Description: Pin select */
1378 
1379 /* Bits 2..0 : Analog pin select */
1380 #define COMP_PSEL_PSEL_Pos (0UL) /*!< Position of PSEL field. */
1381 #define COMP_PSEL_PSEL_Msk (0x7UL << COMP_PSEL_PSEL_Pos) /*!< Bit mask of PSEL field. */
1382 #define COMP_PSEL_PSEL_AnalogInput0 (0UL) /*!< AIN0 selected as analog input */
1383 #define COMP_PSEL_PSEL_AnalogInput1 (1UL) /*!< AIN1 selected as analog input */
1384 #define COMP_PSEL_PSEL_AnalogInput2 (2UL) /*!< AIN2 selected as analog input */
1385 #define COMP_PSEL_PSEL_AnalogInput3 (3UL) /*!< AIN3 selected as analog input */
1386 #define COMP_PSEL_PSEL_AnalogInput4 (4UL) /*!< AIN4 selected as analog input */
1387 #define COMP_PSEL_PSEL_AnalogInput5 (5UL) /*!< AIN5 selected as analog input */
1388 #define COMP_PSEL_PSEL_AnalogInput6 (6UL) /*!< AIN6 selected as analog input */
1389 #define COMP_PSEL_PSEL_AnalogInput7 (7UL) /*!< AIN7 selected as analog input */
1390 
1391 /* Register: COMP_REFSEL */
1392 /* Description: Reference source select */
1393 
1394 /* Bits 2..0 : Reference select */
1395 #define COMP_REFSEL_REFSEL_Pos (0UL) /*!< Position of REFSEL field. */
1396 #define COMP_REFSEL_REFSEL_Msk (0x7UL << COMP_REFSEL_REFSEL_Pos) /*!< Bit mask of REFSEL field. */
1397 #define COMP_REFSEL_REFSEL_Int1V2 (0UL) /*!< VREF = internal 1.2 V reference (VDD &gt;= 1.7 V) */
1398 #define COMP_REFSEL_REFSEL_Int1V8 (1UL) /*!< VREF = internal 1.8 V reference (VDD &gt;= VREF + 0.2 V) */
1399 #define COMP_REFSEL_REFSEL_Int2V4 (2UL) /*!< VREF = internal 2.4 V reference (VDD &gt;= VREF + 0.2 V) */
1400 #define COMP_REFSEL_REFSEL_VDD (4UL) /*!< VREF = VDD */
1401 #define COMP_REFSEL_REFSEL_ARef (7UL) /*!< VREF = AREF (VDD &gt;= VREF &gt;= AREFMIN) */
1402 
1403 /* Register: COMP_EXTREFSEL */
1404 /* Description: External reference select */
1405 
1406 /* Bit 0 : External analog reference select */
1407 #define COMP_EXTREFSEL_EXTREFSEL_Pos (0UL) /*!< Position of EXTREFSEL field. */
1408 #define COMP_EXTREFSEL_EXTREFSEL_Msk (0x1UL << COMP_EXTREFSEL_EXTREFSEL_Pos) /*!< Bit mask of EXTREFSEL field. */
1409 #define COMP_EXTREFSEL_EXTREFSEL_AnalogReference0 (0UL) /*!< Use AIN0 as external analog reference */
1410 #define COMP_EXTREFSEL_EXTREFSEL_AnalogReference1 (1UL) /*!< Use AIN1 as external analog reference */
1411 
1412 /* Register: COMP_TH */
1413 /* Description: Threshold configuration for hysteresis unit */
1414 
1415 /* Bits 13..8 : VUP = (THUP+1)/64*VREF */
1416 #define COMP_TH_THUP_Pos (8UL) /*!< Position of THUP field. */
1417 #define COMP_TH_THUP_Msk (0x3FUL << COMP_TH_THUP_Pos) /*!< Bit mask of THUP field. */
1418 
1419 /* Bits 5..0 : VDOWN = (THDOWN+1)/64*VREF */
1420 #define COMP_TH_THDOWN_Pos (0UL) /*!< Position of THDOWN field. */
1421 #define COMP_TH_THDOWN_Msk (0x3FUL << COMP_TH_THDOWN_Pos) /*!< Bit mask of THDOWN field. */
1422 
1423 /* Register: COMP_MODE */
1424 /* Description: Mode configuration */
1425 
1426 /* Bit 8 : Main operation mode */
1427 #define COMP_MODE_MAIN_Pos (8UL) /*!< Position of MAIN field. */
1428 #define COMP_MODE_MAIN_Msk (0x1UL << COMP_MODE_MAIN_Pos) /*!< Bit mask of MAIN field. */
1429 #define COMP_MODE_MAIN_SE (0UL) /*!< Single ended mode */
1430 #define COMP_MODE_MAIN_Diff (1UL) /*!< Differential mode */
1431 
1432 /* Bits 1..0 : Speed and power mode */
1433 #define COMP_MODE_SP_Pos (0UL) /*!< Position of SP field. */
1434 #define COMP_MODE_SP_Msk (0x3UL << COMP_MODE_SP_Pos) /*!< Bit mask of SP field. */
1435 #define COMP_MODE_SP_Low (0UL) /*!< Low power mode */
1436 #define COMP_MODE_SP_Normal (1UL) /*!< Normal mode */
1437 #define COMP_MODE_SP_High (2UL) /*!< High speed mode */
1438 
1439 /* Register: COMP_HYST */
1440 /* Description: Comparator hysteresis enable */
1441 
1442 /* Bit 0 : Comparator hysteresis */
1443 #define COMP_HYST_HYST_Pos (0UL) /*!< Position of HYST field. */
1444 #define COMP_HYST_HYST_Msk (0x1UL << COMP_HYST_HYST_Pos) /*!< Bit mask of HYST field. */
1445 #define COMP_HYST_HYST_NoHyst (0UL) /*!< Comparator hysteresis disabled */
1446 #define COMP_HYST_HYST_Hyst50mV (1UL) /*!< Comparator hysteresis enabled */
1447 
1448 /* Register: COMP_ISOURCE */
1449 /* Description: Current source select on analog input */
1450 
1451 /* Bits 1..0 : Comparator hysteresis */
1452 #define COMP_ISOURCE_ISOURCE_Pos (0UL) /*!< Position of ISOURCE field. */
1453 #define COMP_ISOURCE_ISOURCE_Msk (0x3UL << COMP_ISOURCE_ISOURCE_Pos) /*!< Bit mask of ISOURCE field. */
1454 #define COMP_ISOURCE_ISOURCE_Off (0UL) /*!< Current source disabled */
1455 #define COMP_ISOURCE_ISOURCE_Ien2mA5 (1UL) /*!< Current source enabled (+/- 2.5 uA) */
1456 #define COMP_ISOURCE_ISOURCE_Ien5mA (2UL) /*!< Current source enabled (+/- 5 uA) */
1457 #define COMP_ISOURCE_ISOURCE_Ien10mA (3UL) /*!< Current source enabled (+/- 10 uA) */
1458 
1459 
1460 /* Peripheral: ECB */
1461 /* Description: AES ECB Mode Encryption */
1462 
1463 /* Register: ECB_INTENSET */
1464 /* Description: Enable interrupt */
1465 
1466 /* Bit 1 : Write '1' to Enable interrupt for ERRORECB event */
1467 #define ECB_INTENSET_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */
1468 #define ECB_INTENSET_ERRORECB_Msk (0x1UL << ECB_INTENSET_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */
1469 #define ECB_INTENSET_ERRORECB_Disabled (0UL) /*!< Read: Disabled */
1470 #define ECB_INTENSET_ERRORECB_Enabled (1UL) /*!< Read: Enabled */
1471 #define ECB_INTENSET_ERRORECB_Set (1UL) /*!< Enable */
1472 
1473 /* Bit 0 : Write '1' to Enable interrupt for ENDECB event */
1474 #define ECB_INTENSET_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */
1475 #define ECB_INTENSET_ENDECB_Msk (0x1UL << ECB_INTENSET_ENDECB_Pos) /*!< Bit mask of ENDECB field. */
1476 #define ECB_INTENSET_ENDECB_Disabled (0UL) /*!< Read: Disabled */
1477 #define ECB_INTENSET_ENDECB_Enabled (1UL) /*!< Read: Enabled */
1478 #define ECB_INTENSET_ENDECB_Set (1UL) /*!< Enable */
1479 
1480 /* Register: ECB_INTENCLR */
1481 /* Description: Disable interrupt */
1482 
1483 /* Bit 1 : Write '1' to Disable interrupt for ERRORECB event */
1484 #define ECB_INTENCLR_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */
1485 #define ECB_INTENCLR_ERRORECB_Msk (0x1UL << ECB_INTENCLR_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */
1486 #define ECB_INTENCLR_ERRORECB_Disabled (0UL) /*!< Read: Disabled */
1487 #define ECB_INTENCLR_ERRORECB_Enabled (1UL) /*!< Read: Enabled */
1488 #define ECB_INTENCLR_ERRORECB_Clear (1UL) /*!< Disable */
1489 
1490 /* Bit 0 : Write '1' to Disable interrupt for ENDECB event */
1491 #define ECB_INTENCLR_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */
1492 #define ECB_INTENCLR_ENDECB_Msk (0x1UL << ECB_INTENCLR_ENDECB_Pos) /*!< Bit mask of ENDECB field. */
1493 #define ECB_INTENCLR_ENDECB_Disabled (0UL) /*!< Read: Disabled */
1494 #define ECB_INTENCLR_ENDECB_Enabled (1UL) /*!< Read: Enabled */
1495 #define ECB_INTENCLR_ENDECB_Clear (1UL) /*!< Disable */
1496 
1497 /* Register: ECB_ECBDATAPTR */
1498 /* Description: ECB block encrypt memory pointers */
1499 
1500 /* Bits 31..0 : Pointer to the ECB data structure (see Table 1 ECB data structure overview) */
1501 #define ECB_ECBDATAPTR_ECBDATAPTR_Pos (0UL) /*!< Position of ECBDATAPTR field. */
1502 #define ECB_ECBDATAPTR_ECBDATAPTR_Msk (0xFFFFFFFFUL << ECB_ECBDATAPTR_ECBDATAPTR_Pos) /*!< Bit mask of ECBDATAPTR field. */
1503 
1504 
1505 /* Peripheral: EGU */
1506 /* Description: Event Generator Unit 0 */
1507 
1508 /* Register: EGU_INTEN */
1509 /* Description: Enable or disable interrupt */
1510 
1511 /* Bit 15 : Enable or disable interrupt for TRIGGERED[15] event */
1512 #define EGU_INTEN_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */
1513 #define EGU_INTEN_TRIGGERED15_Msk (0x1UL << EGU_INTEN_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */
1514 #define EGU_INTEN_TRIGGERED15_Disabled (0UL) /*!< Disable */
1515 #define EGU_INTEN_TRIGGERED15_Enabled (1UL) /*!< Enable */
1516 
1517 /* Bit 14 : Enable or disable interrupt for TRIGGERED[14] event */
1518 #define EGU_INTEN_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */
1519 #define EGU_INTEN_TRIGGERED14_Msk (0x1UL << EGU_INTEN_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */
1520 #define EGU_INTEN_TRIGGERED14_Disabled (0UL) /*!< Disable */
1521 #define EGU_INTEN_TRIGGERED14_Enabled (1UL) /*!< Enable */
1522 
1523 /* Bit 13 : Enable or disable interrupt for TRIGGERED[13] event */
1524 #define EGU_INTEN_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */
1525 #define EGU_INTEN_TRIGGERED13_Msk (0x1UL << EGU_INTEN_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */
1526 #define EGU_INTEN_TRIGGERED13_Disabled (0UL) /*!< Disable */
1527 #define EGU_INTEN_TRIGGERED13_Enabled (1UL) /*!< Enable */
1528 
1529 /* Bit 12 : Enable or disable interrupt for TRIGGERED[12] event */
1530 #define EGU_INTEN_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */
1531 #define EGU_INTEN_TRIGGERED12_Msk (0x1UL << EGU_INTEN_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */
1532 #define EGU_INTEN_TRIGGERED12_Disabled (0UL) /*!< Disable */
1533 #define EGU_INTEN_TRIGGERED12_Enabled (1UL) /*!< Enable */
1534 
1535 /* Bit 11 : Enable or disable interrupt for TRIGGERED[11] event */
1536 #define EGU_INTEN_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */
1537 #define EGU_INTEN_TRIGGERED11_Msk (0x1UL << EGU_INTEN_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */
1538 #define EGU_INTEN_TRIGGERED11_Disabled (0UL) /*!< Disable */
1539 #define EGU_INTEN_TRIGGERED11_Enabled (1UL) /*!< Enable */
1540 
1541 /* Bit 10 : Enable or disable interrupt for TRIGGERED[10] event */
1542 #define EGU_INTEN_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */
1543 #define EGU_INTEN_TRIGGERED10_Msk (0x1UL << EGU_INTEN_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */
1544 #define EGU_INTEN_TRIGGERED10_Disabled (0UL) /*!< Disable */
1545 #define EGU_INTEN_TRIGGERED10_Enabled (1UL) /*!< Enable */
1546 
1547 /* Bit 9 : Enable or disable interrupt for TRIGGERED[9] event */
1548 #define EGU_INTEN_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */
1549 #define EGU_INTEN_TRIGGERED9_Msk (0x1UL << EGU_INTEN_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */
1550 #define EGU_INTEN_TRIGGERED9_Disabled (0UL) /*!< Disable */
1551 #define EGU_INTEN_TRIGGERED9_Enabled (1UL) /*!< Enable */
1552 
1553 /* Bit 8 : Enable or disable interrupt for TRIGGERED[8] event */
1554 #define EGU_INTEN_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */
1555 #define EGU_INTEN_TRIGGERED8_Msk (0x1UL << EGU_INTEN_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */
1556 #define EGU_INTEN_TRIGGERED8_Disabled (0UL) /*!< Disable */
1557 #define EGU_INTEN_TRIGGERED8_Enabled (1UL) /*!< Enable */
1558 
1559 /* Bit 7 : Enable or disable interrupt for TRIGGERED[7] event */
1560 #define EGU_INTEN_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */
1561 #define EGU_INTEN_TRIGGERED7_Msk (0x1UL << EGU_INTEN_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */
1562 #define EGU_INTEN_TRIGGERED7_Disabled (0UL) /*!< Disable */
1563 #define EGU_INTEN_TRIGGERED7_Enabled (1UL) /*!< Enable */
1564 
1565 /* Bit 6 : Enable or disable interrupt for TRIGGERED[6] event */
1566 #define EGU_INTEN_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */
1567 #define EGU_INTEN_TRIGGERED6_Msk (0x1UL << EGU_INTEN_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */
1568 #define EGU_INTEN_TRIGGERED6_Disabled (0UL) /*!< Disable */
1569 #define EGU_INTEN_TRIGGERED6_Enabled (1UL) /*!< Enable */
1570 
1571 /* Bit 5 : Enable or disable interrupt for TRIGGERED[5] event */
1572 #define EGU_INTEN_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */
1573 #define EGU_INTEN_TRIGGERED5_Msk (0x1UL << EGU_INTEN_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */
1574 #define EGU_INTEN_TRIGGERED5_Disabled (0UL) /*!< Disable */
1575 #define EGU_INTEN_TRIGGERED5_Enabled (1UL) /*!< Enable */
1576 
1577 /* Bit 4 : Enable or disable interrupt for TRIGGERED[4] event */
1578 #define EGU_INTEN_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */
1579 #define EGU_INTEN_TRIGGERED4_Msk (0x1UL << EGU_INTEN_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */
1580 #define EGU_INTEN_TRIGGERED4_Disabled (0UL) /*!< Disable */
1581 #define EGU_INTEN_TRIGGERED4_Enabled (1UL) /*!< Enable */
1582 
1583 /* Bit 3 : Enable or disable interrupt for TRIGGERED[3] event */
1584 #define EGU_INTEN_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */
1585 #define EGU_INTEN_TRIGGERED3_Msk (0x1UL << EGU_INTEN_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */
1586 #define EGU_INTEN_TRIGGERED3_Disabled (0UL) /*!< Disable */
1587 #define EGU_INTEN_TRIGGERED3_Enabled (1UL) /*!< Enable */
1588 
1589 /* Bit 2 : Enable or disable interrupt for TRIGGERED[2] event */
1590 #define EGU_INTEN_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */
1591 #define EGU_INTEN_TRIGGERED2_Msk (0x1UL << EGU_INTEN_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */
1592 #define EGU_INTEN_TRIGGERED2_Disabled (0UL) /*!< Disable */
1593 #define EGU_INTEN_TRIGGERED2_Enabled (1UL) /*!< Enable */
1594 
1595 /* Bit 1 : Enable or disable interrupt for TRIGGERED[1] event */
1596 #define EGU_INTEN_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */
1597 #define EGU_INTEN_TRIGGERED1_Msk (0x1UL << EGU_INTEN_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */
1598 #define EGU_INTEN_TRIGGERED1_Disabled (0UL) /*!< Disable */
1599 #define EGU_INTEN_TRIGGERED1_Enabled (1UL) /*!< Enable */
1600 
1601 /* Bit 0 : Enable or disable interrupt for TRIGGERED[0] event */
1602 #define EGU_INTEN_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */
1603 #define EGU_INTEN_TRIGGERED0_Msk (0x1UL << EGU_INTEN_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */
1604 #define EGU_INTEN_TRIGGERED0_Disabled (0UL) /*!< Disable */
1605 #define EGU_INTEN_TRIGGERED0_Enabled (1UL) /*!< Enable */
1606 
1607 /* Register: EGU_INTENSET */
1608 /* Description: Enable interrupt */
1609 
1610 /* Bit 15 : Write '1' to Enable interrupt for TRIGGERED[15] event */
1611 #define EGU_INTENSET_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */
1612 #define EGU_INTENSET_TRIGGERED15_Msk (0x1UL << EGU_INTENSET_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */
1613 #define EGU_INTENSET_TRIGGERED15_Disabled (0UL) /*!< Read: Disabled */
1614 #define EGU_INTENSET_TRIGGERED15_Enabled (1UL) /*!< Read: Enabled */
1615 #define EGU_INTENSET_TRIGGERED15_Set (1UL) /*!< Enable */
1616 
1617 /* Bit 14 : Write '1' to Enable interrupt for TRIGGERED[14] event */
1618 #define EGU_INTENSET_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */
1619 #define EGU_INTENSET_TRIGGERED14_Msk (0x1UL << EGU_INTENSET_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */
1620 #define EGU_INTENSET_TRIGGERED14_Disabled (0UL) /*!< Read: Disabled */
1621 #define EGU_INTENSET_TRIGGERED14_Enabled (1UL) /*!< Read: Enabled */
1622 #define EGU_INTENSET_TRIGGERED14_Set (1UL) /*!< Enable */
1623 
1624 /* Bit 13 : Write '1' to Enable interrupt for TRIGGERED[13] event */
1625 #define EGU_INTENSET_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */
1626 #define EGU_INTENSET_TRIGGERED13_Msk (0x1UL << EGU_INTENSET_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */
1627 #define EGU_INTENSET_TRIGGERED13_Disabled (0UL) /*!< Read: Disabled */
1628 #define EGU_INTENSET_TRIGGERED13_Enabled (1UL) /*!< Read: Enabled */
1629 #define EGU_INTENSET_TRIGGERED13_Set (1UL) /*!< Enable */
1630 
1631 /* Bit 12 : Write '1' to Enable interrupt for TRIGGERED[12] event */
1632 #define EGU_INTENSET_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */
1633 #define EGU_INTENSET_TRIGGERED12_Msk (0x1UL << EGU_INTENSET_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */
1634 #define EGU_INTENSET_TRIGGERED12_Disabled (0UL) /*!< Read: Disabled */
1635 #define EGU_INTENSET_TRIGGERED12_Enabled (1UL) /*!< Read: Enabled */
1636 #define EGU_INTENSET_TRIGGERED12_Set (1UL) /*!< Enable */
1637 
1638 /* Bit 11 : Write '1' to Enable interrupt for TRIGGERED[11] event */
1639 #define EGU_INTENSET_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */
1640 #define EGU_INTENSET_TRIGGERED11_Msk (0x1UL << EGU_INTENSET_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */
1641 #define EGU_INTENSET_TRIGGERED11_Disabled (0UL) /*!< Read: Disabled */
1642 #define EGU_INTENSET_TRIGGERED11_Enabled (1UL) /*!< Read: Enabled */
1643 #define EGU_INTENSET_TRIGGERED11_Set (1UL) /*!< Enable */
1644 
1645 /* Bit 10 : Write '1' to Enable interrupt for TRIGGERED[10] event */
1646 #define EGU_INTENSET_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */
1647 #define EGU_INTENSET_TRIGGERED10_Msk (0x1UL << EGU_INTENSET_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */
1648 #define EGU_INTENSET_TRIGGERED10_Disabled (0UL) /*!< Read: Disabled */
1649 #define EGU_INTENSET_TRIGGERED10_Enabled (1UL) /*!< Read: Enabled */
1650 #define EGU_INTENSET_TRIGGERED10_Set (1UL) /*!< Enable */
1651 
1652 /* Bit 9 : Write '1' to Enable interrupt for TRIGGERED[9] event */
1653 #define EGU_INTENSET_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */
1654 #define EGU_INTENSET_TRIGGERED9_Msk (0x1UL << EGU_INTENSET_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */
1655 #define EGU_INTENSET_TRIGGERED9_Disabled (0UL) /*!< Read: Disabled */
1656 #define EGU_INTENSET_TRIGGERED9_Enabled (1UL) /*!< Read: Enabled */
1657 #define EGU_INTENSET_TRIGGERED9_Set (1UL) /*!< Enable */
1658 
1659 /* Bit 8 : Write '1' to Enable interrupt for TRIGGERED[8] event */
1660 #define EGU_INTENSET_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */
1661 #define EGU_INTENSET_TRIGGERED8_Msk (0x1UL << EGU_INTENSET_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */
1662 #define EGU_INTENSET_TRIGGERED8_Disabled (0UL) /*!< Read: Disabled */
1663 #define EGU_INTENSET_TRIGGERED8_Enabled (1UL) /*!< Read: Enabled */
1664 #define EGU_INTENSET_TRIGGERED8_Set (1UL) /*!< Enable */
1665 
1666 /* Bit 7 : Write '1' to Enable interrupt for TRIGGERED[7] event */
1667 #define EGU_INTENSET_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */
1668 #define EGU_INTENSET_TRIGGERED7_Msk (0x1UL << EGU_INTENSET_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */
1669 #define EGU_INTENSET_TRIGGERED7_Disabled (0UL) /*!< Read: Disabled */
1670 #define EGU_INTENSET_TRIGGERED7_Enabled (1UL) /*!< Read: Enabled */
1671 #define EGU_INTENSET_TRIGGERED7_Set (1UL) /*!< Enable */
1672 
1673 /* Bit 6 : Write '1' to Enable interrupt for TRIGGERED[6] event */
1674 #define EGU_INTENSET_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */
1675 #define EGU_INTENSET_TRIGGERED6_Msk (0x1UL << EGU_INTENSET_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */
1676 #define EGU_INTENSET_TRIGGERED6_Disabled (0UL) /*!< Read: Disabled */
1677 #define EGU_INTENSET_TRIGGERED6_Enabled (1UL) /*!< Read: Enabled */
1678 #define EGU_INTENSET_TRIGGERED6_Set (1UL) /*!< Enable */
1679 
1680 /* Bit 5 : Write '1' to Enable interrupt for TRIGGERED[5] event */
1681 #define EGU_INTENSET_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */
1682 #define EGU_INTENSET_TRIGGERED5_Msk (0x1UL << EGU_INTENSET_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */
1683 #define EGU_INTENSET_TRIGGERED5_Disabled (0UL) /*!< Read: Disabled */
1684 #define EGU_INTENSET_TRIGGERED5_Enabled (1UL) /*!< Read: Enabled */
1685 #define EGU_INTENSET_TRIGGERED5_Set (1UL) /*!< Enable */
1686 
1687 /* Bit 4 : Write '1' to Enable interrupt for TRIGGERED[4] event */
1688 #define EGU_INTENSET_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */
1689 #define EGU_INTENSET_TRIGGERED4_Msk (0x1UL << EGU_INTENSET_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */
1690 #define EGU_INTENSET_TRIGGERED4_Disabled (0UL) /*!< Read: Disabled */
1691 #define EGU_INTENSET_TRIGGERED4_Enabled (1UL) /*!< Read: Enabled */
1692 #define EGU_INTENSET_TRIGGERED4_Set (1UL) /*!< Enable */
1693 
1694 /* Bit 3 : Write '1' to Enable interrupt for TRIGGERED[3] event */
1695 #define EGU_INTENSET_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */
1696 #define EGU_INTENSET_TRIGGERED3_Msk (0x1UL << EGU_INTENSET_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */
1697 #define EGU_INTENSET_TRIGGERED3_Disabled (0UL) /*!< Read: Disabled */
1698 #define EGU_INTENSET_TRIGGERED3_Enabled (1UL) /*!< Read: Enabled */
1699 #define EGU_INTENSET_TRIGGERED3_Set (1UL) /*!< Enable */
1700 
1701 /* Bit 2 : Write '1' to Enable interrupt for TRIGGERED[2] event */
1702 #define EGU_INTENSET_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */
1703 #define EGU_INTENSET_TRIGGERED2_Msk (0x1UL << EGU_INTENSET_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */
1704 #define EGU_INTENSET_TRIGGERED2_Disabled (0UL) /*!< Read: Disabled */
1705 #define EGU_INTENSET_TRIGGERED2_Enabled (1UL) /*!< Read: Enabled */
1706 #define EGU_INTENSET_TRIGGERED2_Set (1UL) /*!< Enable */
1707 
1708 /* Bit 1 : Write '1' to Enable interrupt for TRIGGERED[1] event */
1709 #define EGU_INTENSET_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */
1710 #define EGU_INTENSET_TRIGGERED1_Msk (0x1UL << EGU_INTENSET_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */
1711 #define EGU_INTENSET_TRIGGERED1_Disabled (0UL) /*!< Read: Disabled */
1712 #define EGU_INTENSET_TRIGGERED1_Enabled (1UL) /*!< Read: Enabled */
1713 #define EGU_INTENSET_TRIGGERED1_Set (1UL) /*!< Enable */
1714 
1715 /* Bit 0 : Write '1' to Enable interrupt for TRIGGERED[0] event */
1716 #define EGU_INTENSET_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */
1717 #define EGU_INTENSET_TRIGGERED0_Msk (0x1UL << EGU_INTENSET_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */
1718 #define EGU_INTENSET_TRIGGERED0_Disabled (0UL) /*!< Read: Disabled */
1719 #define EGU_INTENSET_TRIGGERED0_Enabled (1UL) /*!< Read: Enabled */
1720 #define EGU_INTENSET_TRIGGERED0_Set (1UL) /*!< Enable */
1721 
1722 /* Register: EGU_INTENCLR */
1723 /* Description: Disable interrupt */
1724 
1725 /* Bit 15 : Write '1' to Disable interrupt for TRIGGERED[15] event */
1726 #define EGU_INTENCLR_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */
1727 #define EGU_INTENCLR_TRIGGERED15_Msk (0x1UL << EGU_INTENCLR_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */
1728 #define EGU_INTENCLR_TRIGGERED15_Disabled (0UL) /*!< Read: Disabled */
1729 #define EGU_INTENCLR_TRIGGERED15_Enabled (1UL) /*!< Read: Enabled */
1730 #define EGU_INTENCLR_TRIGGERED15_Clear (1UL) /*!< Disable */
1731 
1732 /* Bit 14 : Write '1' to Disable interrupt for TRIGGERED[14] event */
1733 #define EGU_INTENCLR_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */
1734 #define EGU_INTENCLR_TRIGGERED14_Msk (0x1UL << EGU_INTENCLR_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */
1735 #define EGU_INTENCLR_TRIGGERED14_Disabled (0UL) /*!< Read: Disabled */
1736 #define EGU_INTENCLR_TRIGGERED14_Enabled (1UL) /*!< Read: Enabled */
1737 #define EGU_INTENCLR_TRIGGERED14_Clear (1UL) /*!< Disable */
1738 
1739 /* Bit 13 : Write '1' to Disable interrupt for TRIGGERED[13] event */
1740 #define EGU_INTENCLR_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */
1741 #define EGU_INTENCLR_TRIGGERED13_Msk (0x1UL << EGU_INTENCLR_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */
1742 #define EGU_INTENCLR_TRIGGERED13_Disabled (0UL) /*!< Read: Disabled */
1743 #define EGU_INTENCLR_TRIGGERED13_Enabled (1UL) /*!< Read: Enabled */
1744 #define EGU_INTENCLR_TRIGGERED13_Clear (1UL) /*!< Disable */
1745 
1746 /* Bit 12 : Write '1' to Disable interrupt for TRIGGERED[12] event */
1747 #define EGU_INTENCLR_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */
1748 #define EGU_INTENCLR_TRIGGERED12_Msk (0x1UL << EGU_INTENCLR_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */
1749 #define EGU_INTENCLR_TRIGGERED12_Disabled (0UL) /*!< Read: Disabled */
1750 #define EGU_INTENCLR_TRIGGERED12_Enabled (1UL) /*!< Read: Enabled */
1751 #define EGU_INTENCLR_TRIGGERED12_Clear (1UL) /*!< Disable */
1752 
1753 /* Bit 11 : Write '1' to Disable interrupt for TRIGGERED[11] event */
1754 #define EGU_INTENCLR_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */
1755 #define EGU_INTENCLR_TRIGGERED11_Msk (0x1UL << EGU_INTENCLR_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */
1756 #define EGU_INTENCLR_TRIGGERED11_Disabled (0UL) /*!< Read: Disabled */
1757 #define EGU_INTENCLR_TRIGGERED11_Enabled (1UL) /*!< Read: Enabled */
1758 #define EGU_INTENCLR_TRIGGERED11_Clear (1UL) /*!< Disable */
1759 
1760 /* Bit 10 : Write '1' to Disable interrupt for TRIGGERED[10] event */
1761 #define EGU_INTENCLR_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */
1762 #define EGU_INTENCLR_TRIGGERED10_Msk (0x1UL << EGU_INTENCLR_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */
1763 #define EGU_INTENCLR_TRIGGERED10_Disabled (0UL) /*!< Read: Disabled */
1764 #define EGU_INTENCLR_TRIGGERED10_Enabled (1UL) /*!< Read: Enabled */
1765 #define EGU_INTENCLR_TRIGGERED10_Clear (1UL) /*!< Disable */
1766 
1767 /* Bit 9 : Write '1' to Disable interrupt for TRIGGERED[9] event */
1768 #define EGU_INTENCLR_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */
1769 #define EGU_INTENCLR_TRIGGERED9_Msk (0x1UL << EGU_INTENCLR_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */
1770 #define EGU_INTENCLR_TRIGGERED9_Disabled (0UL) /*!< Read: Disabled */
1771 #define EGU_INTENCLR_TRIGGERED9_Enabled (1UL) /*!< Read: Enabled */
1772 #define EGU_INTENCLR_TRIGGERED9_Clear (1UL) /*!< Disable */
1773 
1774 /* Bit 8 : Write '1' to Disable interrupt for TRIGGERED[8] event */
1775 #define EGU_INTENCLR_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */
1776 #define EGU_INTENCLR_TRIGGERED8_Msk (0x1UL << EGU_INTENCLR_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */
1777 #define EGU_INTENCLR_TRIGGERED8_Disabled (0UL) /*!< Read: Disabled */
1778 #define EGU_INTENCLR_TRIGGERED8_Enabled (1UL) /*!< Read: Enabled */
1779 #define EGU_INTENCLR_TRIGGERED8_Clear (1UL) /*!< Disable */
1780 
1781 /* Bit 7 : Write '1' to Disable interrupt for TRIGGERED[7] event */
1782 #define EGU_INTENCLR_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */
1783 #define EGU_INTENCLR_TRIGGERED7_Msk (0x1UL << EGU_INTENCLR_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */
1784 #define EGU_INTENCLR_TRIGGERED7_Disabled (0UL) /*!< Read: Disabled */
1785 #define EGU_INTENCLR_TRIGGERED7_Enabled (1UL) /*!< Read: Enabled */
1786 #define EGU_INTENCLR_TRIGGERED7_Clear (1UL) /*!< Disable */
1787 
1788 /* Bit 6 : Write '1' to Disable interrupt for TRIGGERED[6] event */
1789 #define EGU_INTENCLR_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */
1790 #define EGU_INTENCLR_TRIGGERED6_Msk (0x1UL << EGU_INTENCLR_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */
1791 #define EGU_INTENCLR_TRIGGERED6_Disabled (0UL) /*!< Read: Disabled */
1792 #define EGU_INTENCLR_TRIGGERED6_Enabled (1UL) /*!< Read: Enabled */
1793 #define EGU_INTENCLR_TRIGGERED6_Clear (1UL) /*!< Disable */
1794 
1795 /* Bit 5 : Write '1' to Disable interrupt for TRIGGERED[5] event */
1796 #define EGU_INTENCLR_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */
1797 #define EGU_INTENCLR_TRIGGERED5_Msk (0x1UL << EGU_INTENCLR_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */
1798 #define EGU_INTENCLR_TRIGGERED5_Disabled (0UL) /*!< Read: Disabled */
1799 #define EGU_INTENCLR_TRIGGERED5_Enabled (1UL) /*!< Read: Enabled */
1800 #define EGU_INTENCLR_TRIGGERED5_Clear (1UL) /*!< Disable */
1801 
1802 /* Bit 4 : Write '1' to Disable interrupt for TRIGGERED[4] event */
1803 #define EGU_INTENCLR_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */
1804 #define EGU_INTENCLR_TRIGGERED4_Msk (0x1UL << EGU_INTENCLR_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */
1805 #define EGU_INTENCLR_TRIGGERED4_Disabled (0UL) /*!< Read: Disabled */
1806 #define EGU_INTENCLR_TRIGGERED4_Enabled (1UL) /*!< Read: Enabled */
1807 #define EGU_INTENCLR_TRIGGERED4_Clear (1UL) /*!< Disable */
1808 
1809 /* Bit 3 : Write '1' to Disable interrupt for TRIGGERED[3] event */
1810 #define EGU_INTENCLR_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */
1811 #define EGU_INTENCLR_TRIGGERED3_Msk (0x1UL << EGU_INTENCLR_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */
1812 #define EGU_INTENCLR_TRIGGERED3_Disabled (0UL) /*!< Read: Disabled */
1813 #define EGU_INTENCLR_TRIGGERED3_Enabled (1UL) /*!< Read: Enabled */
1814 #define EGU_INTENCLR_TRIGGERED3_Clear (1UL) /*!< Disable */
1815 
1816 /* Bit 2 : Write '1' to Disable interrupt for TRIGGERED[2] event */
1817 #define EGU_INTENCLR_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */
1818 #define EGU_INTENCLR_TRIGGERED2_Msk (0x1UL << EGU_INTENCLR_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */
1819 #define EGU_INTENCLR_TRIGGERED2_Disabled (0UL) /*!< Read: Disabled */
1820 #define EGU_INTENCLR_TRIGGERED2_Enabled (1UL) /*!< Read: Enabled */
1821 #define EGU_INTENCLR_TRIGGERED2_Clear (1UL) /*!< Disable */
1822 
1823 /* Bit 1 : Write '1' to Disable interrupt for TRIGGERED[1] event */
1824 #define EGU_INTENCLR_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */
1825 #define EGU_INTENCLR_TRIGGERED1_Msk (0x1UL << EGU_INTENCLR_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */
1826 #define EGU_INTENCLR_TRIGGERED1_Disabled (0UL) /*!< Read: Disabled */
1827 #define EGU_INTENCLR_TRIGGERED1_Enabled (1UL) /*!< Read: Enabled */
1828 #define EGU_INTENCLR_TRIGGERED1_Clear (1UL) /*!< Disable */
1829 
1830 /* Bit 0 : Write '1' to Disable interrupt for TRIGGERED[0] event */
1831 #define EGU_INTENCLR_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */
1832 #define EGU_INTENCLR_TRIGGERED0_Msk (0x1UL << EGU_INTENCLR_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */
1833 #define EGU_INTENCLR_TRIGGERED0_Disabled (0UL) /*!< Read: Disabled */
1834 #define EGU_INTENCLR_TRIGGERED0_Enabled (1UL) /*!< Read: Enabled */
1835 #define EGU_INTENCLR_TRIGGERED0_Clear (1UL) /*!< Disable */
1836 
1837 
1838 /* Peripheral: FICR */
1839 /* Description: Factory Information Configuration Registers */
1840 
1841 /* Register: FICR_CODEPAGESIZE */
1842 /* Description: Code memory page size */
1843 
1844 /* Bits 31..0 : Code memory page size */
1845 #define FICR_CODEPAGESIZE_CODEPAGESIZE_Pos (0UL) /*!< Position of CODEPAGESIZE field. */
1846 #define FICR_CODEPAGESIZE_CODEPAGESIZE_Msk (0xFFFFFFFFUL << FICR_CODEPAGESIZE_CODEPAGESIZE_Pos) /*!< Bit mask of CODEPAGESIZE field. */
1847 
1848 /* Register: FICR_CODESIZE */
1849 /* Description: Code memory size */
1850 
1851 /* Bits 31..0 : Code memory size in number of pages */
1852 #define FICR_CODESIZE_CODESIZE_Pos (0UL) /*!< Position of CODESIZE field. */
1853 #define FICR_CODESIZE_CODESIZE_Msk (0xFFFFFFFFUL << FICR_CODESIZE_CODESIZE_Pos) /*!< Bit mask of CODESIZE field. */
1854 
1855 /* Register: FICR_DEVICEID */
1856 /* Description: Description collection[0]:  Device identifier */
1857 
1858 /* Bits 31..0 : 64 bit unique device identifier */
1859 #define FICR_DEVICEID_DEVICEID_Pos (0UL) /*!< Position of DEVICEID field. */
1860 #define FICR_DEVICEID_DEVICEID_Msk (0xFFFFFFFFUL << FICR_DEVICEID_DEVICEID_Pos) /*!< Bit mask of DEVICEID field. */
1861 
1862 /* Register: FICR_ER */
1863 /* Description: Description collection[0]:  Encryption Root, word 0 */
1864 
1865 /* Bits 31..0 : Encryption Root, word n */
1866 #define FICR_ER_ER_Pos (0UL) /*!< Position of ER field. */
1867 #define FICR_ER_ER_Msk (0xFFFFFFFFUL << FICR_ER_ER_Pos) /*!< Bit mask of ER field. */
1868 
1869 /* Register: FICR_IR */
1870 /* Description: Description collection[0]:  Identity Root, word 0 */
1871 
1872 /* Bits 31..0 : Identity Root, word n */
1873 #define FICR_IR_IR_Pos (0UL) /*!< Position of IR field. */
1874 #define FICR_IR_IR_Msk (0xFFFFFFFFUL << FICR_IR_IR_Pos) /*!< Bit mask of IR field. */
1875 
1876 /* Register: FICR_DEVICEADDRTYPE */
1877 /* Description: Device address type */
1878 
1879 /* Bit 0 : Device address type */
1880 #define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos (0UL) /*!< Position of DEVICEADDRTYPE field. */
1881 #define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Msk (0x1UL << FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos) /*!< Bit mask of DEVICEADDRTYPE field. */
1882 #define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Public (0UL) /*!< Public address */
1883 #define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Random (1UL) /*!< Random address */
1884 
1885 /* Register: FICR_DEVICEADDR */
1886 /* Description: Description collection[0]:  Device address 0 */
1887 
1888 /* Bits 31..0 : 48 bit device address */
1889 #define FICR_DEVICEADDR_DEVICEADDR_Pos (0UL) /*!< Position of DEVICEADDR field. */
1890 #define FICR_DEVICEADDR_DEVICEADDR_Msk (0xFFFFFFFFUL << FICR_DEVICEADDR_DEVICEADDR_Pos) /*!< Bit mask of DEVICEADDR field. */
1891 
1892 /* Register: FICR_INFO_PART */
1893 /* Description: Part code */
1894 
1895 /* Bits 31..0 : Part code */
1896 #define FICR_INFO_PART_PART_Pos (0UL) /*!< Position of PART field. */
1897 #define FICR_INFO_PART_PART_Msk (0xFFFFFFFFUL << FICR_INFO_PART_PART_Pos) /*!< Bit mask of PART field. */
1898 #define FICR_INFO_PART_PART_N52832 (0x52832UL) /*!< nRF52832 */
1899 #define FICR_INFO_PART_PART_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
1900 
1901 /* Register: FICR_INFO_VARIANT */
1902 /* Description: Part Variant, Hardware version and Production configuration */
1903 
1904 /* Bits 31..0 : Part Variant, Hardware version and Production configuration, encoded as ASCII */
1905 #define FICR_INFO_VARIANT_VARIANT_Pos (0UL) /*!< Position of VARIANT field. */
1906 #define FICR_INFO_VARIANT_VARIANT_Msk (0xFFFFFFFFUL << FICR_INFO_VARIANT_VARIANT_Pos) /*!< Bit mask of VARIANT field. */
1907 #define FICR_INFO_VARIANT_VARIANT_AAAA (0x41414141UL) /*!< AAAA */
1908 #define FICR_INFO_VARIANT_VARIANT_AAAB (0x41414142UL) /*!< AAAB */
1909 #define FICR_INFO_VARIANT_VARIANT_AAB0 (0x41414230UL) /*!< AAB0 */
1910 #define FICR_INFO_VARIANT_VARIANT_AABA (0x41414241UL) /*!< AABA */
1911 #define FICR_INFO_VARIANT_VARIANT_AABB (0x41414242UL) /*!< AABB */
1912 #define FICR_INFO_VARIANT_VARIANT_SPA0 (0x53504130UL) /*!< SPA0 */
1913 #define FICR_INFO_VARIANT_VARIANT_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
1914 
1915 /* Register: FICR_INFO_PACKAGE */
1916 /* Description: Package option */
1917 
1918 /* Bits 31..0 : Package option */
1919 #define FICR_INFO_PACKAGE_PACKAGE_Pos (0UL) /*!< Position of PACKAGE field. */
1920 #define FICR_INFO_PACKAGE_PACKAGE_Msk (0xFFFFFFFFUL << FICR_INFO_PACKAGE_PACKAGE_Pos) /*!< Bit mask of PACKAGE field. */
1921 #define FICR_INFO_PACKAGE_PACKAGE_QF (0x2000UL) /*!< QFxx - 48-pin QFN */
1922 #define FICR_INFO_PACKAGE_PACKAGE_CH (0x2001UL) /*!< CHxx - 7x8 WLCSP 56 balls */
1923 #define FICR_INFO_PACKAGE_PACKAGE_CI (0x2002UL) /*!< CIxx - 7x8 WLCSP 56 balls */
1924 #define FICR_INFO_PACKAGE_PACKAGE_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
1925 
1926 /* Register: FICR_INFO_RAM */
1927 /* Description: RAM variant */
1928 
1929 /* Bits 31..0 : RAM variant */
1930 #define FICR_INFO_RAM_RAM_Pos (0UL) /*!< Position of RAM field. */
1931 #define FICR_INFO_RAM_RAM_Msk (0xFFFFFFFFUL << FICR_INFO_RAM_RAM_Pos) /*!< Bit mask of RAM field. */
1932 #define FICR_INFO_RAM_RAM_K16 (0x10UL) /*!< 16 kByte RAM */
1933 #define FICR_INFO_RAM_RAM_K32 (0x20UL) /*!< 32 kByte RAM */
1934 #define FICR_INFO_RAM_RAM_K64 (0x40UL) /*!< 64 kByte RAM */
1935 #define FICR_INFO_RAM_RAM_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
1936 
1937 /* Register: FICR_INFO_FLASH */
1938 /* Description: Flash variant */
1939 
1940 /* Bits 31..0 : Flash variant */
1941 #define FICR_INFO_FLASH_FLASH_Pos (0UL) /*!< Position of FLASH field. */
1942 #define FICR_INFO_FLASH_FLASH_Msk (0xFFFFFFFFUL << FICR_INFO_FLASH_FLASH_Pos) /*!< Bit mask of FLASH field. */
1943 #define FICR_INFO_FLASH_FLASH_K128 (0x80UL) /*!< 128 kByte FLASH */
1944 #define FICR_INFO_FLASH_FLASH_K256 (0x100UL) /*!< 256 kByte FLASH */
1945 #define FICR_INFO_FLASH_FLASH_K512 (0x200UL) /*!< 512 kByte FLASH */
1946 #define FICR_INFO_FLASH_FLASH_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
1947 
1948 /* Register: FICR_TEMP_A0 */
1949 /* Description: Slope definition A0. */
1950 
1951 /* Bits 11..0 : A (slope definition) register. */
1952 #define FICR_TEMP_A0_A_Pos (0UL) /*!< Position of A field. */
1953 #define FICR_TEMP_A0_A_Msk (0xFFFUL << FICR_TEMP_A0_A_Pos) /*!< Bit mask of A field. */
1954 
1955 /* Register: FICR_TEMP_A1 */
1956 /* Description: Slope definition A1. */
1957 
1958 /* Bits 11..0 : A (slope definition) register. */
1959 #define FICR_TEMP_A1_A_Pos (0UL) /*!< Position of A field. */
1960 #define FICR_TEMP_A1_A_Msk (0xFFFUL << FICR_TEMP_A1_A_Pos) /*!< Bit mask of A field. */
1961 
1962 /* Register: FICR_TEMP_A2 */
1963 /* Description: Slope definition A2. */
1964 
1965 /* Bits 11..0 : A (slope definition) register. */
1966 #define FICR_TEMP_A2_A_Pos (0UL) /*!< Position of A field. */
1967 #define FICR_TEMP_A2_A_Msk (0xFFFUL << FICR_TEMP_A2_A_Pos) /*!< Bit mask of A field. */
1968 
1969 /* Register: FICR_TEMP_A3 */
1970 /* Description: Slope definition A3. */
1971 
1972 /* Bits 11..0 : A (slope definition) register. */
1973 #define FICR_TEMP_A3_A_Pos (0UL) /*!< Position of A field. */
1974 #define FICR_TEMP_A3_A_Msk (0xFFFUL << FICR_TEMP_A3_A_Pos) /*!< Bit mask of A field. */
1975 
1976 /* Register: FICR_TEMP_A4 */
1977 /* Description: Slope definition A4. */
1978 
1979 /* Bits 11..0 : A (slope definition) register. */
1980 #define FICR_TEMP_A4_A_Pos (0UL) /*!< Position of A field. */
1981 #define FICR_TEMP_A4_A_Msk (0xFFFUL << FICR_TEMP_A4_A_Pos) /*!< Bit mask of A field. */
1982 
1983 /* Register: FICR_TEMP_A5 */
1984 /* Description: Slope definition A5. */
1985 
1986 /* Bits 11..0 : A (slope definition) register. */
1987 #define FICR_TEMP_A5_A_Pos (0UL) /*!< Position of A field. */
1988 #define FICR_TEMP_A5_A_Msk (0xFFFUL << FICR_TEMP_A5_A_Pos) /*!< Bit mask of A field. */
1989 
1990 /* Register: FICR_TEMP_B0 */
1991 /* Description: y-intercept B0. */
1992 
1993 /* Bits 13..0 : B (y-intercept) */
1994 #define FICR_TEMP_B0_B_Pos (0UL) /*!< Position of B field. */
1995 #define FICR_TEMP_B0_B_Msk (0x3FFFUL << FICR_TEMP_B0_B_Pos) /*!< Bit mask of B field. */
1996 
1997 /* Register: FICR_TEMP_B1 */
1998 /* Description: y-intercept B1. */
1999 
2000 /* Bits 13..0 : B (y-intercept) */
2001 #define FICR_TEMP_B1_B_Pos (0UL) /*!< Position of B field. */
2002 #define FICR_TEMP_B1_B_Msk (0x3FFFUL << FICR_TEMP_B1_B_Pos) /*!< Bit mask of B field. */
2003 
2004 /* Register: FICR_TEMP_B2 */
2005 /* Description: y-intercept B2. */
2006 
2007 /* Bits 13..0 : B (y-intercept) */
2008 #define FICR_TEMP_B2_B_Pos (0UL) /*!< Position of B field. */
2009 #define FICR_TEMP_B2_B_Msk (0x3FFFUL << FICR_TEMP_B2_B_Pos) /*!< Bit mask of B field. */
2010 
2011 /* Register: FICR_TEMP_B3 */
2012 /* Description: y-intercept B3. */
2013 
2014 /* Bits 13..0 : B (y-intercept) */
2015 #define FICR_TEMP_B3_B_Pos (0UL) /*!< Position of B field. */
2016 #define FICR_TEMP_B3_B_Msk (0x3FFFUL << FICR_TEMP_B3_B_Pos) /*!< Bit mask of B field. */
2017 
2018 /* Register: FICR_TEMP_B4 */
2019 /* Description: y-intercept B4. */
2020 
2021 /* Bits 13..0 : B (y-intercept) */
2022 #define FICR_TEMP_B4_B_Pos (0UL) /*!< Position of B field. */
2023 #define FICR_TEMP_B4_B_Msk (0x3FFFUL << FICR_TEMP_B4_B_Pos) /*!< Bit mask of B field. */
2024 
2025 /* Register: FICR_TEMP_B5 */
2026 /* Description: y-intercept B5. */
2027 
2028 /* Bits 13..0 : B (y-intercept) */
2029 #define FICR_TEMP_B5_B_Pos (0UL) /*!< Position of B field. */
2030 #define FICR_TEMP_B5_B_Msk (0x3FFFUL << FICR_TEMP_B5_B_Pos) /*!< Bit mask of B field. */
2031 
2032 /* Register: FICR_TEMP_T0 */
2033 /* Description: Segment end T0. */
2034 
2035 /* Bits 7..0 : T (segment end)register. */
2036 #define FICR_TEMP_T0_T_Pos (0UL) /*!< Position of T field. */
2037 #define FICR_TEMP_T0_T_Msk (0xFFUL << FICR_TEMP_T0_T_Pos) /*!< Bit mask of T field. */
2038 
2039 /* Register: FICR_TEMP_T1 */
2040 /* Description: Segment end T1. */
2041 
2042 /* Bits 7..0 : T (segment end)register. */
2043 #define FICR_TEMP_T1_T_Pos (0UL) /*!< Position of T field. */
2044 #define FICR_TEMP_T1_T_Msk (0xFFUL << FICR_TEMP_T1_T_Pos) /*!< Bit mask of T field. */
2045 
2046 /* Register: FICR_TEMP_T2 */
2047 /* Description: Segment end T2. */
2048 
2049 /* Bits 7..0 : T (segment end)register. */
2050 #define FICR_TEMP_T2_T_Pos (0UL) /*!< Position of T field. */
2051 #define FICR_TEMP_T2_T_Msk (0xFFUL << FICR_TEMP_T2_T_Pos) /*!< Bit mask of T field. */
2052 
2053 /* Register: FICR_TEMP_T3 */
2054 /* Description: Segment end T3. */
2055 
2056 /* Bits 7..0 : T (segment end)register. */
2057 #define FICR_TEMP_T3_T_Pos (0UL) /*!< Position of T field. */
2058 #define FICR_TEMP_T3_T_Msk (0xFFUL << FICR_TEMP_T3_T_Pos) /*!< Bit mask of T field. */
2059 
2060 /* Register: FICR_TEMP_T4 */
2061 /* Description: Segment end T4. */
2062 
2063 /* Bits 7..0 : T (segment end)register. */
2064 #define FICR_TEMP_T4_T_Pos (0UL) /*!< Position of T field. */
2065 #define FICR_TEMP_T4_T_Msk (0xFFUL << FICR_TEMP_T4_T_Pos) /*!< Bit mask of T field. */
2066 
2067 /* Register: FICR_NFC_TAGHEADER0 */
2068 /* Description: Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */
2069 
2070 /* Bits 31..24 : Unique identifier byte 3 */
2071 #define FICR_NFC_TAGHEADER0_UD3_Pos (24UL) /*!< Position of UD3 field. */
2072 #define FICR_NFC_TAGHEADER0_UD3_Msk (0xFFUL << FICR_NFC_TAGHEADER0_UD3_Pos) /*!< Bit mask of UD3 field. */
2073 
2074 /* Bits 23..16 : Unique identifier byte 2 */
2075 #define FICR_NFC_TAGHEADER0_UD2_Pos (16UL) /*!< Position of UD2 field. */
2076 #define FICR_NFC_TAGHEADER0_UD2_Msk (0xFFUL << FICR_NFC_TAGHEADER0_UD2_Pos) /*!< Bit mask of UD2 field. */
2077 
2078 /* Bits 15..8 : Unique identifier byte 1 */
2079 #define FICR_NFC_TAGHEADER0_UD1_Pos (8UL) /*!< Position of UD1 field. */
2080 #define FICR_NFC_TAGHEADER0_UD1_Msk (0xFFUL << FICR_NFC_TAGHEADER0_UD1_Pos) /*!< Bit mask of UD1 field. */
2081 
2082 /* Bits 7..0 : Default Manufacturer ID: Nordic Semiconductor ASA has ICM 0x5F */
2083 #define FICR_NFC_TAGHEADER0_MFGID_Pos (0UL) /*!< Position of MFGID field. */
2084 #define FICR_NFC_TAGHEADER0_MFGID_Msk (0xFFUL << FICR_NFC_TAGHEADER0_MFGID_Pos) /*!< Bit mask of MFGID field. */
2085 
2086 /* Register: FICR_NFC_TAGHEADER1 */
2087 /* Description: Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */
2088 
2089 /* Bits 31..24 : Unique identifier byte 7 */
2090 #define FICR_NFC_TAGHEADER1_UD7_Pos (24UL) /*!< Position of UD7 field. */
2091 #define FICR_NFC_TAGHEADER1_UD7_Msk (0xFFUL << FICR_NFC_TAGHEADER1_UD7_Pos) /*!< Bit mask of UD7 field. */
2092 
2093 /* Bits 23..16 : Unique identifier byte 6 */
2094 #define FICR_NFC_TAGHEADER1_UD6_Pos (16UL) /*!< Position of UD6 field. */
2095 #define FICR_NFC_TAGHEADER1_UD6_Msk (0xFFUL << FICR_NFC_TAGHEADER1_UD6_Pos) /*!< Bit mask of UD6 field. */
2096 
2097 /* Bits 15..8 : Unique identifier byte 5 */
2098 #define FICR_NFC_TAGHEADER1_UD5_Pos (8UL) /*!< Position of UD5 field. */
2099 #define FICR_NFC_TAGHEADER1_UD5_Msk (0xFFUL << FICR_NFC_TAGHEADER1_UD5_Pos) /*!< Bit mask of UD5 field. */
2100 
2101 /* Bits 7..0 : Unique identifier byte 4 */
2102 #define FICR_NFC_TAGHEADER1_UD4_Pos (0UL) /*!< Position of UD4 field. */
2103 #define FICR_NFC_TAGHEADER1_UD4_Msk (0xFFUL << FICR_NFC_TAGHEADER1_UD4_Pos) /*!< Bit mask of UD4 field. */
2104 
2105 /* Register: FICR_NFC_TAGHEADER2 */
2106 /* Description: Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */
2107 
2108 /* Bits 31..24 : Unique identifier byte 11 */
2109 #define FICR_NFC_TAGHEADER2_UD11_Pos (24UL) /*!< Position of UD11 field. */
2110 #define FICR_NFC_TAGHEADER2_UD11_Msk (0xFFUL << FICR_NFC_TAGHEADER2_UD11_Pos) /*!< Bit mask of UD11 field. */
2111 
2112 /* Bits 23..16 : Unique identifier byte 10 */
2113 #define FICR_NFC_TAGHEADER2_UD10_Pos (16UL) /*!< Position of UD10 field. */
2114 #define FICR_NFC_TAGHEADER2_UD10_Msk (0xFFUL << FICR_NFC_TAGHEADER2_UD10_Pos) /*!< Bit mask of UD10 field. */
2115 
2116 /* Bits 15..8 : Unique identifier byte 9 */
2117 #define FICR_NFC_TAGHEADER2_UD9_Pos (8UL) /*!< Position of UD9 field. */
2118 #define FICR_NFC_TAGHEADER2_UD9_Msk (0xFFUL << FICR_NFC_TAGHEADER2_UD9_Pos) /*!< Bit mask of UD9 field. */
2119 
2120 /* Bits 7..0 : Unique identifier byte 8 */
2121 #define FICR_NFC_TAGHEADER2_UD8_Pos (0UL) /*!< Position of UD8 field. */
2122 #define FICR_NFC_TAGHEADER2_UD8_Msk (0xFFUL << FICR_NFC_TAGHEADER2_UD8_Pos) /*!< Bit mask of UD8 field. */
2123 
2124 /* Register: FICR_NFC_TAGHEADER3 */
2125 /* Description: Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */
2126 
2127 /* Bits 31..24 : Unique identifier byte 15 */
2128 #define FICR_NFC_TAGHEADER3_UD15_Pos (24UL) /*!< Position of UD15 field. */
2129 #define FICR_NFC_TAGHEADER3_UD15_Msk (0xFFUL << FICR_NFC_TAGHEADER3_UD15_Pos) /*!< Bit mask of UD15 field. */
2130 
2131 /* Bits 23..16 : Unique identifier byte 14 */
2132 #define FICR_NFC_TAGHEADER3_UD14_Pos (16UL) /*!< Position of UD14 field. */
2133 #define FICR_NFC_TAGHEADER3_UD14_Msk (0xFFUL << FICR_NFC_TAGHEADER3_UD14_Pos) /*!< Bit mask of UD14 field. */
2134 
2135 /* Bits 15..8 : Unique identifier byte 13 */
2136 #define FICR_NFC_TAGHEADER3_UD13_Pos (8UL) /*!< Position of UD13 field. */
2137 #define FICR_NFC_TAGHEADER3_UD13_Msk (0xFFUL << FICR_NFC_TAGHEADER3_UD13_Pos) /*!< Bit mask of UD13 field. */
2138 
2139 /* Bits 7..0 : Unique identifier byte 12 */
2140 #define FICR_NFC_TAGHEADER3_UD12_Pos (0UL) /*!< Position of UD12 field. */
2141 #define FICR_NFC_TAGHEADER3_UD12_Msk (0xFFUL << FICR_NFC_TAGHEADER3_UD12_Pos) /*!< Bit mask of UD12 field. */
2142 
2143 
2144 /* Peripheral: GPIOTE */
2145 /* Description: GPIO Tasks and Events */
2146 
2147 /* Register: GPIOTE_INTENSET */
2148 /* Description: Enable interrupt */
2149 
2150 /* Bit 31 : Write '1' to Enable interrupt for PORT event */
2151 #define GPIOTE_INTENSET_PORT_Pos (31UL) /*!< Position of PORT field. */
2152 #define GPIOTE_INTENSET_PORT_Msk (0x1UL << GPIOTE_INTENSET_PORT_Pos) /*!< Bit mask of PORT field. */
2153 #define GPIOTE_INTENSET_PORT_Disabled (0UL) /*!< Read: Disabled */
2154 #define GPIOTE_INTENSET_PORT_Enabled (1UL) /*!< Read: Enabled */
2155 #define GPIOTE_INTENSET_PORT_Set (1UL) /*!< Enable */
2156 
2157 /* Bit 7 : Write '1' to Enable interrupt for IN[7] event */
2158 #define GPIOTE_INTENSET_IN7_Pos (7UL) /*!< Position of IN7 field. */
2159 #define GPIOTE_INTENSET_IN7_Msk (0x1UL << GPIOTE_INTENSET_IN7_Pos) /*!< Bit mask of IN7 field. */
2160 #define GPIOTE_INTENSET_IN7_Disabled (0UL) /*!< Read: Disabled */
2161 #define GPIOTE_INTENSET_IN7_Enabled (1UL) /*!< Read: Enabled */
2162 #define GPIOTE_INTENSET_IN7_Set (1UL) /*!< Enable */
2163 
2164 /* Bit 6 : Write '1' to Enable interrupt for IN[6] event */
2165 #define GPIOTE_INTENSET_IN6_Pos (6UL) /*!< Position of IN6 field. */
2166 #define GPIOTE_INTENSET_IN6_Msk (0x1UL << GPIOTE_INTENSET_IN6_Pos) /*!< Bit mask of IN6 field. */
2167 #define GPIOTE_INTENSET_IN6_Disabled (0UL) /*!< Read: Disabled */
2168 #define GPIOTE_INTENSET_IN6_Enabled (1UL) /*!< Read: Enabled */
2169 #define GPIOTE_INTENSET_IN6_Set (1UL) /*!< Enable */
2170 
2171 /* Bit 5 : Write '1' to Enable interrupt for IN[5] event */
2172 #define GPIOTE_INTENSET_IN5_Pos (5UL) /*!< Position of IN5 field. */
2173 #define GPIOTE_INTENSET_IN5_Msk (0x1UL << GPIOTE_INTENSET_IN5_Pos) /*!< Bit mask of IN5 field. */
2174 #define GPIOTE_INTENSET_IN5_Disabled (0UL) /*!< Read: Disabled */
2175 #define GPIOTE_INTENSET_IN5_Enabled (1UL) /*!< Read: Enabled */
2176 #define GPIOTE_INTENSET_IN5_Set (1UL) /*!< Enable */
2177 
2178 /* Bit 4 : Write '1' to Enable interrupt for IN[4] event */
2179 #define GPIOTE_INTENSET_IN4_Pos (4UL) /*!< Position of IN4 field. */
2180 #define GPIOTE_INTENSET_IN4_Msk (0x1UL << GPIOTE_INTENSET_IN4_Pos) /*!< Bit mask of IN4 field. */
2181 #define GPIOTE_INTENSET_IN4_Disabled (0UL) /*!< Read: Disabled */
2182 #define GPIOTE_INTENSET_IN4_Enabled (1UL) /*!< Read: Enabled */
2183 #define GPIOTE_INTENSET_IN4_Set (1UL) /*!< Enable */
2184 
2185 /* Bit 3 : Write '1' to Enable interrupt for IN[3] event */
2186 #define GPIOTE_INTENSET_IN3_Pos (3UL) /*!< Position of IN3 field. */
2187 #define GPIOTE_INTENSET_IN3_Msk (0x1UL << GPIOTE_INTENSET_IN3_Pos) /*!< Bit mask of IN3 field. */
2188 #define GPIOTE_INTENSET_IN3_Disabled (0UL) /*!< Read: Disabled */
2189 #define GPIOTE_INTENSET_IN3_Enabled (1UL) /*!< Read: Enabled */
2190 #define GPIOTE_INTENSET_IN3_Set (1UL) /*!< Enable */
2191 
2192 /* Bit 2 : Write '1' to Enable interrupt for IN[2] event */
2193 #define GPIOTE_INTENSET_IN2_Pos (2UL) /*!< Position of IN2 field. */
2194 #define GPIOTE_INTENSET_IN2_Msk (0x1UL << GPIOTE_INTENSET_IN2_Pos) /*!< Bit mask of IN2 field. */
2195 #define GPIOTE_INTENSET_IN2_Disabled (0UL) /*!< Read: Disabled */
2196 #define GPIOTE_INTENSET_IN2_Enabled (1UL) /*!< Read: Enabled */
2197 #define GPIOTE_INTENSET_IN2_Set (1UL) /*!< Enable */
2198 
2199 /* Bit 1 : Write '1' to Enable interrupt for IN[1] event */
2200 #define GPIOTE_INTENSET_IN1_Pos (1UL) /*!< Position of IN1 field. */
2201 #define GPIOTE_INTENSET_IN1_Msk (0x1UL << GPIOTE_INTENSET_IN1_Pos) /*!< Bit mask of IN1 field. */
2202 #define GPIOTE_INTENSET_IN1_Disabled (0UL) /*!< Read: Disabled */
2203 #define GPIOTE_INTENSET_IN1_Enabled (1UL) /*!< Read: Enabled */
2204 #define GPIOTE_INTENSET_IN1_Set (1UL) /*!< Enable */
2205 
2206 /* Bit 0 : Write '1' to Enable interrupt for IN[0] event */
2207 #define GPIOTE_INTENSET_IN0_Pos (0UL) /*!< Position of IN0 field. */
2208 #define GPIOTE_INTENSET_IN0_Msk (0x1UL << GPIOTE_INTENSET_IN0_Pos) /*!< Bit mask of IN0 field. */
2209 #define GPIOTE_INTENSET_IN0_Disabled (0UL) /*!< Read: Disabled */
2210 #define GPIOTE_INTENSET_IN0_Enabled (1UL) /*!< Read: Enabled */
2211 #define GPIOTE_INTENSET_IN0_Set (1UL) /*!< Enable */
2212 
2213 /* Register: GPIOTE_INTENCLR */
2214 /* Description: Disable interrupt */
2215 
2216 /* Bit 31 : Write '1' to Disable interrupt for PORT event */
2217 #define GPIOTE_INTENCLR_PORT_Pos (31UL) /*!< Position of PORT field. */
2218 #define GPIOTE_INTENCLR_PORT_Msk (0x1UL << GPIOTE_INTENCLR_PORT_Pos) /*!< Bit mask of PORT field. */
2219 #define GPIOTE_INTENCLR_PORT_Disabled (0UL) /*!< Read: Disabled */
2220 #define GPIOTE_INTENCLR_PORT_Enabled (1UL) /*!< Read: Enabled */
2221 #define GPIOTE_INTENCLR_PORT_Clear (1UL) /*!< Disable */
2222 
2223 /* Bit 7 : Write '1' to Disable interrupt for IN[7] event */
2224 #define GPIOTE_INTENCLR_IN7_Pos (7UL) /*!< Position of IN7 field. */
2225 #define GPIOTE_INTENCLR_IN7_Msk (0x1UL << GPIOTE_INTENCLR_IN7_Pos) /*!< Bit mask of IN7 field. */
2226 #define GPIOTE_INTENCLR_IN7_Disabled (0UL) /*!< Read: Disabled */
2227 #define GPIOTE_INTENCLR_IN7_Enabled (1UL) /*!< Read: Enabled */
2228 #define GPIOTE_INTENCLR_IN7_Clear (1UL) /*!< Disable */
2229 
2230 /* Bit 6 : Write '1' to Disable interrupt for IN[6] event */
2231 #define GPIOTE_INTENCLR_IN6_Pos (6UL) /*!< Position of IN6 field. */
2232 #define GPIOTE_INTENCLR_IN6_Msk (0x1UL << GPIOTE_INTENCLR_IN6_Pos) /*!< Bit mask of IN6 field. */
2233 #define GPIOTE_INTENCLR_IN6_Disabled (0UL) /*!< Read: Disabled */
2234 #define GPIOTE_INTENCLR_IN6_Enabled (1UL) /*!< Read: Enabled */
2235 #define GPIOTE_INTENCLR_IN6_Clear (1UL) /*!< Disable */
2236 
2237 /* Bit 5 : Write '1' to Disable interrupt for IN[5] event */
2238 #define GPIOTE_INTENCLR_IN5_Pos (5UL) /*!< Position of IN5 field. */
2239 #define GPIOTE_INTENCLR_IN5_Msk (0x1UL << GPIOTE_INTENCLR_IN5_Pos) /*!< Bit mask of IN5 field. */
2240 #define GPIOTE_INTENCLR_IN5_Disabled (0UL) /*!< Read: Disabled */
2241 #define GPIOTE_INTENCLR_IN5_Enabled (1UL) /*!< Read: Enabled */
2242 #define GPIOTE_INTENCLR_IN5_Clear (1UL) /*!< Disable */
2243 
2244 /* Bit 4 : Write '1' to Disable interrupt for IN[4] event */
2245 #define GPIOTE_INTENCLR_IN4_Pos (4UL) /*!< Position of IN4 field. */
2246 #define GPIOTE_INTENCLR_IN4_Msk (0x1UL << GPIOTE_INTENCLR_IN4_Pos) /*!< Bit mask of IN4 field. */
2247 #define GPIOTE_INTENCLR_IN4_Disabled (0UL) /*!< Read: Disabled */
2248 #define GPIOTE_INTENCLR_IN4_Enabled (1UL) /*!< Read: Enabled */
2249 #define GPIOTE_INTENCLR_IN4_Clear (1UL) /*!< Disable */
2250 
2251 /* Bit 3 : Write '1' to Disable interrupt for IN[3] event */
2252 #define GPIOTE_INTENCLR_IN3_Pos (3UL) /*!< Position of IN3 field. */
2253 #define GPIOTE_INTENCLR_IN3_Msk (0x1UL << GPIOTE_INTENCLR_IN3_Pos) /*!< Bit mask of IN3 field. */
2254 #define GPIOTE_INTENCLR_IN3_Disabled (0UL) /*!< Read: Disabled */
2255 #define GPIOTE_INTENCLR_IN3_Enabled (1UL) /*!< Read: Enabled */
2256 #define GPIOTE_INTENCLR_IN3_Clear (1UL) /*!< Disable */
2257 
2258 /* Bit 2 : Write '1' to Disable interrupt for IN[2] event */
2259 #define GPIOTE_INTENCLR_IN2_Pos (2UL) /*!< Position of IN2 field. */
2260 #define GPIOTE_INTENCLR_IN2_Msk (0x1UL << GPIOTE_INTENCLR_IN2_Pos) /*!< Bit mask of IN2 field. */
2261 #define GPIOTE_INTENCLR_IN2_Disabled (0UL) /*!< Read: Disabled */
2262 #define GPIOTE_INTENCLR_IN2_Enabled (1UL) /*!< Read: Enabled */
2263 #define GPIOTE_INTENCLR_IN2_Clear (1UL) /*!< Disable */
2264 
2265 /* Bit 1 : Write '1' to Disable interrupt for IN[1] event */
2266 #define GPIOTE_INTENCLR_IN1_Pos (1UL) /*!< Position of IN1 field. */
2267 #define GPIOTE_INTENCLR_IN1_Msk (0x1UL << GPIOTE_INTENCLR_IN1_Pos) /*!< Bit mask of IN1 field. */
2268 #define GPIOTE_INTENCLR_IN1_Disabled (0UL) /*!< Read: Disabled */
2269 #define GPIOTE_INTENCLR_IN1_Enabled (1UL) /*!< Read: Enabled */
2270 #define GPIOTE_INTENCLR_IN1_Clear (1UL) /*!< Disable */
2271 
2272 /* Bit 0 : Write '1' to Disable interrupt for IN[0] event */
2273 #define GPIOTE_INTENCLR_IN0_Pos (0UL) /*!< Position of IN0 field. */
2274 #define GPIOTE_INTENCLR_IN0_Msk (0x1UL << GPIOTE_INTENCLR_IN0_Pos) /*!< Bit mask of IN0 field. */
2275 #define GPIOTE_INTENCLR_IN0_Disabled (0UL) /*!< Read: Disabled */
2276 #define GPIOTE_INTENCLR_IN0_Enabled (1UL) /*!< Read: Enabled */
2277 #define GPIOTE_INTENCLR_IN0_Clear (1UL) /*!< Disable */
2278 
2279 /* Register: GPIOTE_CONFIG */
2280 /* Description: Description collection[0]:  Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event */
2281 
2282 /* Bit 20 : When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect. */
2283 #define GPIOTE_CONFIG_OUTINIT_Pos (20UL) /*!< Position of OUTINIT field. */
2284 #define GPIOTE_CONFIG_OUTINIT_Msk (0x1UL << GPIOTE_CONFIG_OUTINIT_Pos) /*!< Bit mask of OUTINIT field. */
2285 #define GPIOTE_CONFIG_OUTINIT_Low (0UL) /*!< Task mode: Initial value of pin before task triggering is low */
2286 #define GPIOTE_CONFIG_OUTINIT_High (1UL) /*!< Task mode: Initial value of pin before task triggering is high */
2287 
2288 /* Bits 17..16 : When In task mode: Operation to be performed on output when OUT[n] task is triggered. When In event mode: Operation on input that shall trigger IN[n] event. */
2289 #define GPIOTE_CONFIG_POLARITY_Pos (16UL) /*!< Position of POLARITY field. */
2290 #define GPIOTE_CONFIG_POLARITY_Msk (0x3UL << GPIOTE_CONFIG_POLARITY_Pos) /*!< Bit mask of POLARITY field. */
2291 #define GPIOTE_CONFIG_POLARITY_None (0UL) /*!< Task mode: No effect on pin from OUT[n] task. Event mode: no IN[n] event generated on pin activity. */
2292 #define GPIOTE_CONFIG_POLARITY_LoToHi (1UL) /*!< Task mode: Set pin from OUT[n] task. Event mode: Generate IN[n] event when rising edge on pin. */
2293 #define GPIOTE_CONFIG_POLARITY_HiToLo (2UL) /*!< Task mode: Clear pin from OUT[n] task. Event mode: Generate IN[n] event when falling edge on pin. */
2294 #define GPIOTE_CONFIG_POLARITY_Toggle (3UL) /*!< Task mode: Toggle pin from OUT[n]. Event mode: Generate IN[n] when any change on pin. */
2295 
2296 /* Bits 12..8 : GPIO number associated with SET[n], CLR[n] and OUT[n] tasks and IN[n] event */
2297 #define GPIOTE_CONFIG_PSEL_Pos (8UL) /*!< Position of PSEL field. */
2298 #define GPIOTE_CONFIG_PSEL_Msk (0x1FUL << GPIOTE_CONFIG_PSEL_Pos) /*!< Bit mask of PSEL field. */
2299 
2300 /* Bits 1..0 : Mode */
2301 #define GPIOTE_CONFIG_MODE_Pos (0UL) /*!< Position of MODE field. */
2302 #define GPIOTE_CONFIG_MODE_Msk (0x3UL << GPIOTE_CONFIG_MODE_Pos) /*!< Bit mask of MODE field. */
2303 #define GPIOTE_CONFIG_MODE_Disabled (0UL) /*!< Disabled. Pin specified by PSEL will not be acquired by the GPIOTE module. */
2304 #define GPIOTE_CONFIG_MODE_Event (1UL) /*!< Event mode */
2305 #define GPIOTE_CONFIG_MODE_Task (3UL) /*!< Task mode */
2306 
2307 
2308 /* Peripheral: I2S */
2309 /* Description: Inter-IC Sound */
2310 
2311 /* Register: I2S_INTEN */
2312 /* Description: Enable or disable interrupt */
2313 
2314 /* Bit 5 : Enable or disable interrupt for TXPTRUPD event */
2315 #define I2S_INTEN_TXPTRUPD_Pos (5UL) /*!< Position of TXPTRUPD field. */
2316 #define I2S_INTEN_TXPTRUPD_Msk (0x1UL << I2S_INTEN_TXPTRUPD_Pos) /*!< Bit mask of TXPTRUPD field. */
2317 #define I2S_INTEN_TXPTRUPD_Disabled (0UL) /*!< Disable */
2318 #define I2S_INTEN_TXPTRUPD_Enabled (1UL) /*!< Enable */
2319 
2320 /* Bit 2 : Enable or disable interrupt for STOPPED event */
2321 #define I2S_INTEN_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */
2322 #define I2S_INTEN_STOPPED_Msk (0x1UL << I2S_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
2323 #define I2S_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
2324 #define I2S_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
2325 
2326 /* Bit 1 : Enable or disable interrupt for RXPTRUPD event */
2327 #define I2S_INTEN_RXPTRUPD_Pos (1UL) /*!< Position of RXPTRUPD field. */
2328 #define I2S_INTEN_RXPTRUPD_Msk (0x1UL << I2S_INTEN_RXPTRUPD_Pos) /*!< Bit mask of RXPTRUPD field. */
2329 #define I2S_INTEN_RXPTRUPD_Disabled (0UL) /*!< Disable */
2330 #define I2S_INTEN_RXPTRUPD_Enabled (1UL) /*!< Enable */
2331 
2332 /* Register: I2S_INTENSET */
2333 /* Description: Enable interrupt */
2334 
2335 /* Bit 5 : Write '1' to Enable interrupt for TXPTRUPD event */
2336 #define I2S_INTENSET_TXPTRUPD_Pos (5UL) /*!< Position of TXPTRUPD field. */
2337 #define I2S_INTENSET_TXPTRUPD_Msk (0x1UL << I2S_INTENSET_TXPTRUPD_Pos) /*!< Bit mask of TXPTRUPD field. */
2338 #define I2S_INTENSET_TXPTRUPD_Disabled (0UL) /*!< Read: Disabled */
2339 #define I2S_INTENSET_TXPTRUPD_Enabled (1UL) /*!< Read: Enabled */
2340 #define I2S_INTENSET_TXPTRUPD_Set (1UL) /*!< Enable */
2341 
2342 /* Bit 2 : Write '1' to Enable interrupt for STOPPED event */
2343 #define I2S_INTENSET_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */
2344 #define I2S_INTENSET_STOPPED_Msk (0x1UL << I2S_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
2345 #define I2S_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
2346 #define I2S_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
2347 #define I2S_INTENSET_STOPPED_Set (1UL) /*!< Enable */
2348 
2349 /* Bit 1 : Write '1' to Enable interrupt for RXPTRUPD event */
2350 #define I2S_INTENSET_RXPTRUPD_Pos (1UL) /*!< Position of RXPTRUPD field. */
2351 #define I2S_INTENSET_RXPTRUPD_Msk (0x1UL << I2S_INTENSET_RXPTRUPD_Pos) /*!< Bit mask of RXPTRUPD field. */
2352 #define I2S_INTENSET_RXPTRUPD_Disabled (0UL) /*!< Read: Disabled */
2353 #define I2S_INTENSET_RXPTRUPD_Enabled (1UL) /*!< Read: Enabled */
2354 #define I2S_INTENSET_RXPTRUPD_Set (1UL) /*!< Enable */
2355 
2356 /* Register: I2S_INTENCLR */
2357 /* Description: Disable interrupt */
2358 
2359 /* Bit 5 : Write '1' to Disable interrupt for TXPTRUPD event */
2360 #define I2S_INTENCLR_TXPTRUPD_Pos (5UL) /*!< Position of TXPTRUPD field. */
2361 #define I2S_INTENCLR_TXPTRUPD_Msk (0x1UL << I2S_INTENCLR_TXPTRUPD_Pos) /*!< Bit mask of TXPTRUPD field. */
2362 #define I2S_INTENCLR_TXPTRUPD_Disabled (0UL) /*!< Read: Disabled */
2363 #define I2S_INTENCLR_TXPTRUPD_Enabled (1UL) /*!< Read: Enabled */
2364 #define I2S_INTENCLR_TXPTRUPD_Clear (1UL) /*!< Disable */
2365 
2366 /* Bit 2 : Write '1' to Disable interrupt for STOPPED event */
2367 #define I2S_INTENCLR_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */
2368 #define I2S_INTENCLR_STOPPED_Msk (0x1UL << I2S_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
2369 #define I2S_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
2370 #define I2S_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
2371 #define I2S_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
2372 
2373 /* Bit 1 : Write '1' to Disable interrupt for RXPTRUPD event */
2374 #define I2S_INTENCLR_RXPTRUPD_Pos (1UL) /*!< Position of RXPTRUPD field. */
2375 #define I2S_INTENCLR_RXPTRUPD_Msk (0x1UL << I2S_INTENCLR_RXPTRUPD_Pos) /*!< Bit mask of RXPTRUPD field. */
2376 #define I2S_INTENCLR_RXPTRUPD_Disabled (0UL) /*!< Read: Disabled */
2377 #define I2S_INTENCLR_RXPTRUPD_Enabled (1UL) /*!< Read: Enabled */
2378 #define I2S_INTENCLR_RXPTRUPD_Clear (1UL) /*!< Disable */
2379 
2380 /* Register: I2S_ENABLE */
2381 /* Description: Enable I2S module. */
2382 
2383 /* Bit 0 : Enable I2S module. */
2384 #define I2S_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
2385 #define I2S_ENABLE_ENABLE_Msk (0x1UL << I2S_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
2386 #define I2S_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
2387 #define I2S_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */
2388 
2389 /* Register: I2S_CONFIG_MODE */
2390 /* Description: I2S mode. */
2391 
2392 /* Bit 0 : I2S mode. */
2393 #define I2S_CONFIG_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
2394 #define I2S_CONFIG_MODE_MODE_Msk (0x1UL << I2S_CONFIG_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
2395 #define I2S_CONFIG_MODE_MODE_Master (0UL) /*!< Master mode. SCK and LRCK generated from internal master clcok (MCK) and output on pins defined by PSEL.xxx. */
2396 #define I2S_CONFIG_MODE_MODE_Slave (1UL) /*!< Slave mode. SCK and LRCK generated by external master and received on pins defined by PSEL.xxx */
2397 
2398 /* Register: I2S_CONFIG_RXEN */
2399 /* Description: Reception (RX) enable. */
2400 
2401 /* Bit 0 : Reception (RX) enable. */
2402 #define I2S_CONFIG_RXEN_RXEN_Pos (0UL) /*!< Position of RXEN field. */
2403 #define I2S_CONFIG_RXEN_RXEN_Msk (0x1UL << I2S_CONFIG_RXEN_RXEN_Pos) /*!< Bit mask of RXEN field. */
2404 #define I2S_CONFIG_RXEN_RXEN_Disabled (0UL) /*!< Reception disabled and now data will be written to the RXD.PTR address. */
2405 #define I2S_CONFIG_RXEN_RXEN_Enabled (1UL) /*!< Reception enabled. */
2406 
2407 /* Register: I2S_CONFIG_TXEN */
2408 /* Description: Transmission (TX) enable. */
2409 
2410 /* Bit 0 : Transmission (TX) enable. */
2411 #define I2S_CONFIG_TXEN_TXEN_Pos (0UL) /*!< Position of TXEN field. */
2412 #define I2S_CONFIG_TXEN_TXEN_Msk (0x1UL << I2S_CONFIG_TXEN_TXEN_Pos) /*!< Bit mask of TXEN field. */
2413 #define I2S_CONFIG_TXEN_TXEN_Disabled (0UL) /*!< Transmission disabled and now data will be read from the RXD.TXD address. */
2414 #define I2S_CONFIG_TXEN_TXEN_Enabled (1UL) /*!< Transmission enabled. */
2415 
2416 /* Register: I2S_CONFIG_MCKEN */
2417 /* Description: Master clock generator enable. */
2418 
2419 /* Bit 0 : Master clock generator enable. */
2420 #define I2S_CONFIG_MCKEN_MCKEN_Pos (0UL) /*!< Position of MCKEN field. */
2421 #define I2S_CONFIG_MCKEN_MCKEN_Msk (0x1UL << I2S_CONFIG_MCKEN_MCKEN_Pos) /*!< Bit mask of MCKEN field. */
2422 #define I2S_CONFIG_MCKEN_MCKEN_Disabled (0UL) /*!< Master clock generator disabled and PSEL.MCK not connected(available as GPIO). */
2423 #define I2S_CONFIG_MCKEN_MCKEN_Enabled (1UL) /*!< Master clock generator running and MCK output on PSEL.MCK. */
2424 
2425 /* Register: I2S_CONFIG_MCKFREQ */
2426 /* Description: Master clock generator frequency. */
2427 
2428 /* Bits 31..0 : Master clock generator frequency. */
2429 #define I2S_CONFIG_MCKFREQ_MCKFREQ_Pos (0UL) /*!< Position of MCKFREQ field. */
2430 #define I2S_CONFIG_MCKFREQ_MCKFREQ_Msk (0xFFFFFFFFUL << I2S_CONFIG_MCKFREQ_MCKFREQ_Pos) /*!< Bit mask of MCKFREQ field. */
2431 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV125 (0x020C0000UL) /*!< 32 MHz / 125 = 0.256 MHz */
2432 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV63 (0x04100000UL) /*!< 32 MHz / 63 = 0.5079365 MHz */
2433 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV42 (0x06000000UL) /*!< 32 MHz / 42 = 0.7619048 MHz */
2434 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV32 (0x08000000UL) /*!< 32 MHz / 32 = 1.0 MHz */
2435 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV31 (0x08400000UL) /*!< 32 MHz / 31 = 1.0322581 MHz */
2436 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV30 (0x08800000UL) /*!< 32 MHz / 30 = 1.0666667 MHz */
2437 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV23 (0x0B000000UL) /*!< 32 MHz / 23 = 1.3913043 MHz */
2438 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV21 (0x0C000000UL) /*!< 32 MHz / 21 = 1.5238095 */
2439 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV16 (0x10000000UL) /*!< 32 MHz / 16 = 2.0 MHz */
2440 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV15 (0x11000000UL) /*!< 32 MHz / 15 = 2.1333333 MHz */
2441 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV11 (0x16000000UL) /*!< 32 MHz / 11 = 2.9090909 MHz */
2442 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV10 (0x18000000UL) /*!< 32 MHz / 10 = 3.2 MHz */
2443 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV8 (0x20000000UL) /*!< 32 MHz / 8 = 4.0 MHz */
2444 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV6 (0x28000000UL) /*!< 32 MHz / 6 = 5.3333333 MHz */
2445 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV5 (0x30000000UL) /*!< 32 MHz / 5 = 6.4 MHz */
2446 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV4 (0x40000000UL) /*!< 32 MHz / 4 = 8.0 MHz */
2447 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV3 (0x50000000UL) /*!< 32 MHz / 3 = 10.6666667 MHz */
2448 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV2 (0x80000000UL) /*!< 32 MHz / 2 = 16.0 MHz */
2449 
2450 /* Register: I2S_CONFIG_RATIO */
2451 /* Description: MCK / LRCK ratio. */
2452 
2453 /* Bits 3..0 : MCK / LRCK ratio. */
2454 #define I2S_CONFIG_RATIO_RATIO_Pos (0UL) /*!< Position of RATIO field. */
2455 #define I2S_CONFIG_RATIO_RATIO_Msk (0xFUL << I2S_CONFIG_RATIO_RATIO_Pos) /*!< Bit mask of RATIO field. */
2456 #define I2S_CONFIG_RATIO_RATIO_32X (0UL) /*!< LRCK = MCK / 32 */
2457 #define I2S_CONFIG_RATIO_RATIO_48X (1UL) /*!< LRCK = MCK / 48 */
2458 #define I2S_CONFIG_RATIO_RATIO_64X (2UL) /*!< LRCK = MCK / 64 */
2459 #define I2S_CONFIG_RATIO_RATIO_96X (3UL) /*!< LRCK = MCK / 96 */
2460 #define I2S_CONFIG_RATIO_RATIO_128X (4UL) /*!< LRCK = MCK / 128 */
2461 #define I2S_CONFIG_RATIO_RATIO_192X (5UL) /*!< LRCK = MCK / 192 */
2462 #define I2S_CONFIG_RATIO_RATIO_256X (6UL) /*!< LRCK = MCK / 256 */
2463 #define I2S_CONFIG_RATIO_RATIO_384X (7UL) /*!< LRCK = MCK / 384 */
2464 #define I2S_CONFIG_RATIO_RATIO_512X (8UL) /*!< LRCK = MCK / 512 */
2465 
2466 /* Register: I2S_CONFIG_SWIDTH */
2467 /* Description: Sample width. */
2468 
2469 /* Bits 1..0 : Sample width. */
2470 #define I2S_CONFIG_SWIDTH_SWIDTH_Pos (0UL) /*!< Position of SWIDTH field. */
2471 #define I2S_CONFIG_SWIDTH_SWIDTH_Msk (0x3UL << I2S_CONFIG_SWIDTH_SWIDTH_Pos) /*!< Bit mask of SWIDTH field. */
2472 #define I2S_CONFIG_SWIDTH_SWIDTH_8Bit (0UL) /*!< 8 bit. */
2473 #define I2S_CONFIG_SWIDTH_SWIDTH_16Bit (1UL) /*!< 16 bit. */
2474 #define I2S_CONFIG_SWIDTH_SWIDTH_24Bit (2UL) /*!< 24 bit. */
2475 
2476 /* Register: I2S_CONFIG_ALIGN */
2477 /* Description: Alignment of sample within a frame. */
2478 
2479 /* Bit 0 : Alignment of sample within a frame. */
2480 #define I2S_CONFIG_ALIGN_ALIGN_Pos (0UL) /*!< Position of ALIGN field. */
2481 #define I2S_CONFIG_ALIGN_ALIGN_Msk (0x1UL << I2S_CONFIG_ALIGN_ALIGN_Pos) /*!< Bit mask of ALIGN field. */
2482 #define I2S_CONFIG_ALIGN_ALIGN_Left (0UL) /*!< Left-aligned. */
2483 #define I2S_CONFIG_ALIGN_ALIGN_Right (1UL) /*!< Right-aligned. */
2484 
2485 /* Register: I2S_CONFIG_FORMAT */
2486 /* Description: Frame format. */
2487 
2488 /* Bit 0 : Frame format. */
2489 #define I2S_CONFIG_FORMAT_FORMAT_Pos (0UL) /*!< Position of FORMAT field. */
2490 #define I2S_CONFIG_FORMAT_FORMAT_Msk (0x1UL << I2S_CONFIG_FORMAT_FORMAT_Pos) /*!< Bit mask of FORMAT field. */
2491 #define I2S_CONFIG_FORMAT_FORMAT_I2S (0UL) /*!< Original I2S format. */
2492 #define I2S_CONFIG_FORMAT_FORMAT_Aligned (1UL) /*!< Alternate (left- or right-aligned) format. */
2493 
2494 /* Register: I2S_CONFIG_CHANNELS */
2495 /* Description: Enable channels. */
2496 
2497 /* Bits 1..0 : Enable channels. */
2498 #define I2S_CONFIG_CHANNELS_CHANNELS_Pos (0UL) /*!< Position of CHANNELS field. */
2499 #define I2S_CONFIG_CHANNELS_CHANNELS_Msk (0x3UL << I2S_CONFIG_CHANNELS_CHANNELS_Pos) /*!< Bit mask of CHANNELS field. */
2500 #define I2S_CONFIG_CHANNELS_CHANNELS_Stereo (0UL) /*!< Stereo. */
2501 #define I2S_CONFIG_CHANNELS_CHANNELS_Left (1UL) /*!< Left only. */
2502 #define I2S_CONFIG_CHANNELS_CHANNELS_Right (2UL) /*!< Right only. */
2503 
2504 /* Register: I2S_RXD_PTR */
2505 /* Description: Receive buffer RAM start address. */
2506 
2507 /* Bits 31..0 : Receive buffer Data RAM start address. When receiving, words containing samples will be written to this address. This address is a word aligned Data RAM address. */
2508 #define I2S_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
2509 #define I2S_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << I2S_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
2510 
2511 /* Register: I2S_TXD_PTR */
2512 /* Description: Transmit buffer RAM start address. */
2513 
2514 /* Bits 31..0 : Transmit buffer Data RAM start address. When transmitting, words containing samples will be fetched from this address. This address is a word aligned Data RAM address. */
2515 #define I2S_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
2516 #define I2S_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << I2S_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
2517 
2518 /* Register: I2S_RXTXD_MAXCNT */
2519 /* Description: Size of RXD and TXD buffers. */
2520 
2521 /* Bits 13..0 : Size of RXD and TXD buffers in number of 32 bit words. */
2522 #define I2S_RXTXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
2523 #define I2S_RXTXD_MAXCNT_MAXCNT_Msk (0x3FFFUL << I2S_RXTXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
2524 
2525 /* Register: I2S_PSEL_MCK */
2526 /* Description: Pin select for MCK signal. */
2527 
2528 /* Bit 31 : Connection */
2529 #define I2S_PSEL_MCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
2530 #define I2S_PSEL_MCK_CONNECT_Msk (0x1UL << I2S_PSEL_MCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
2531 #define I2S_PSEL_MCK_CONNECT_Connected (0UL) /*!< Connect */
2532 #define I2S_PSEL_MCK_CONNECT_Disconnected (1UL) /*!< Disconnect */
2533 
2534 /* Bits 4..0 : Pin number */
2535 #define I2S_PSEL_MCK_PIN_Pos (0UL) /*!< Position of PIN field. */
2536 #define I2S_PSEL_MCK_PIN_Msk (0x1FUL << I2S_PSEL_MCK_PIN_Pos) /*!< Bit mask of PIN field. */
2537 
2538 /* Register: I2S_PSEL_SCK */
2539 /* Description: Pin select for SCK signal. */
2540 
2541 /* Bit 31 : Connection */
2542 #define I2S_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
2543 #define I2S_PSEL_SCK_CONNECT_Msk (0x1UL << I2S_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
2544 #define I2S_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */
2545 #define I2S_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */
2546 
2547 /* Bits 4..0 : Pin number */
2548 #define I2S_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */
2549 #define I2S_PSEL_SCK_PIN_Msk (0x1FUL << I2S_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */
2550 
2551 /* Register: I2S_PSEL_LRCK */
2552 /* Description: Pin select for LRCK signal. */
2553 
2554 /* Bit 31 : Connection */
2555 #define I2S_PSEL_LRCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
2556 #define I2S_PSEL_LRCK_CONNECT_Msk (0x1UL << I2S_PSEL_LRCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
2557 #define I2S_PSEL_LRCK_CONNECT_Connected (0UL) /*!< Connect */
2558 #define I2S_PSEL_LRCK_CONNECT_Disconnected (1UL) /*!< Disconnect */
2559 
2560 /* Bits 4..0 : Pin number */
2561 #define I2S_PSEL_LRCK_PIN_Pos (0UL) /*!< Position of PIN field. */
2562 #define I2S_PSEL_LRCK_PIN_Msk (0x1FUL << I2S_PSEL_LRCK_PIN_Pos) /*!< Bit mask of PIN field. */
2563 
2564 /* Register: I2S_PSEL_SDIN */
2565 /* Description: Pin select for SDIN signal. */
2566 
2567 /* Bit 31 : Connection */
2568 #define I2S_PSEL_SDIN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
2569 #define I2S_PSEL_SDIN_CONNECT_Msk (0x1UL << I2S_PSEL_SDIN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
2570 #define I2S_PSEL_SDIN_CONNECT_Connected (0UL) /*!< Connect */
2571 #define I2S_PSEL_SDIN_CONNECT_Disconnected (1UL) /*!< Disconnect */
2572 
2573 /* Bits 4..0 : Pin number */
2574 #define I2S_PSEL_SDIN_PIN_Pos (0UL) /*!< Position of PIN field. */
2575 #define I2S_PSEL_SDIN_PIN_Msk (0x1FUL << I2S_PSEL_SDIN_PIN_Pos) /*!< Bit mask of PIN field. */
2576 
2577 /* Register: I2S_PSEL_SDOUT */
2578 /* Description: Pin select for SDOUT signal. */
2579 
2580 /* Bit 31 : Connection */
2581 #define I2S_PSEL_SDOUT_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
2582 #define I2S_PSEL_SDOUT_CONNECT_Msk (0x1UL << I2S_PSEL_SDOUT_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
2583 #define I2S_PSEL_SDOUT_CONNECT_Connected (0UL) /*!< Connect */
2584 #define I2S_PSEL_SDOUT_CONNECT_Disconnected (1UL) /*!< Disconnect */
2585 
2586 /* Bits 4..0 : Pin number */
2587 #define I2S_PSEL_SDOUT_PIN_Pos (0UL) /*!< Position of PIN field. */
2588 #define I2S_PSEL_SDOUT_PIN_Msk (0x1FUL << I2S_PSEL_SDOUT_PIN_Pos) /*!< Bit mask of PIN field. */
2589 
2590 
2591 /* Peripheral: LPCOMP */
2592 /* Description: Low Power Comparator */
2593 
2594 /* Register: LPCOMP_SHORTS */
2595 /* Description: Shortcut register */
2596 
2597 /* Bit 4 : Shortcut between CROSS event and STOP task */
2598 #define LPCOMP_SHORTS_CROSS_STOP_Pos (4UL) /*!< Position of CROSS_STOP field. */
2599 #define LPCOMP_SHORTS_CROSS_STOP_Msk (0x1UL << LPCOMP_SHORTS_CROSS_STOP_Pos) /*!< Bit mask of CROSS_STOP field. */
2600 #define LPCOMP_SHORTS_CROSS_STOP_Disabled (0UL) /*!< Disable shortcut */
2601 #define LPCOMP_SHORTS_CROSS_STOP_Enabled (1UL) /*!< Enable shortcut */
2602 
2603 /* Bit 3 : Shortcut between UP event and STOP task */
2604 #define LPCOMP_SHORTS_UP_STOP_Pos (3UL) /*!< Position of UP_STOP field. */
2605 #define LPCOMP_SHORTS_UP_STOP_Msk (0x1UL << LPCOMP_SHORTS_UP_STOP_Pos) /*!< Bit mask of UP_STOP field. */
2606 #define LPCOMP_SHORTS_UP_STOP_Disabled (0UL) /*!< Disable shortcut */
2607 #define LPCOMP_SHORTS_UP_STOP_Enabled (1UL) /*!< Enable shortcut */
2608 
2609 /* Bit 2 : Shortcut between DOWN event and STOP task */
2610 #define LPCOMP_SHORTS_DOWN_STOP_Pos (2UL) /*!< Position of DOWN_STOP field. */
2611 #define LPCOMP_SHORTS_DOWN_STOP_Msk (0x1UL << LPCOMP_SHORTS_DOWN_STOP_Pos) /*!< Bit mask of DOWN_STOP field. */
2612 #define LPCOMP_SHORTS_DOWN_STOP_Disabled (0UL) /*!< Disable shortcut */
2613 #define LPCOMP_SHORTS_DOWN_STOP_Enabled (1UL) /*!< Enable shortcut */
2614 
2615 /* Bit 1 : Shortcut between READY event and STOP task */
2616 #define LPCOMP_SHORTS_READY_STOP_Pos (1UL) /*!< Position of READY_STOP field. */
2617 #define LPCOMP_SHORTS_READY_STOP_Msk (0x1UL << LPCOMP_SHORTS_READY_STOP_Pos) /*!< Bit mask of READY_STOP field. */
2618 #define LPCOMP_SHORTS_READY_STOP_Disabled (0UL) /*!< Disable shortcut */
2619 #define LPCOMP_SHORTS_READY_STOP_Enabled (1UL) /*!< Enable shortcut */
2620 
2621 /* Bit 0 : Shortcut between READY event and SAMPLE task */
2622 #define LPCOMP_SHORTS_READY_SAMPLE_Pos (0UL) /*!< Position of READY_SAMPLE field. */
2623 #define LPCOMP_SHORTS_READY_SAMPLE_Msk (0x1UL << LPCOMP_SHORTS_READY_SAMPLE_Pos) /*!< Bit mask of READY_SAMPLE field. */
2624 #define LPCOMP_SHORTS_READY_SAMPLE_Disabled (0UL) /*!< Disable shortcut */
2625 #define LPCOMP_SHORTS_READY_SAMPLE_Enabled (1UL) /*!< Enable shortcut */
2626 
2627 /* Register: LPCOMP_INTENSET */
2628 /* Description: Enable interrupt */
2629 
2630 /* Bit 3 : Write '1' to Enable interrupt for CROSS event */
2631 #define LPCOMP_INTENSET_CROSS_Pos (3UL) /*!< Position of CROSS field. */
2632 #define LPCOMP_INTENSET_CROSS_Msk (0x1UL << LPCOMP_INTENSET_CROSS_Pos) /*!< Bit mask of CROSS field. */
2633 #define LPCOMP_INTENSET_CROSS_Disabled (0UL) /*!< Read: Disabled */
2634 #define LPCOMP_INTENSET_CROSS_Enabled (1UL) /*!< Read: Enabled */
2635 #define LPCOMP_INTENSET_CROSS_Set (1UL) /*!< Enable */
2636 
2637 /* Bit 2 : Write '1' to Enable interrupt for UP event */
2638 #define LPCOMP_INTENSET_UP_Pos (2UL) /*!< Position of UP field. */
2639 #define LPCOMP_INTENSET_UP_Msk (0x1UL << LPCOMP_INTENSET_UP_Pos) /*!< Bit mask of UP field. */
2640 #define LPCOMP_INTENSET_UP_Disabled (0UL) /*!< Read: Disabled */
2641 #define LPCOMP_INTENSET_UP_Enabled (1UL) /*!< Read: Enabled */
2642 #define LPCOMP_INTENSET_UP_Set (1UL) /*!< Enable */
2643 
2644 /* Bit 1 : Write '1' to Enable interrupt for DOWN event */
2645 #define LPCOMP_INTENSET_DOWN_Pos (1UL) /*!< Position of DOWN field. */
2646 #define LPCOMP_INTENSET_DOWN_Msk (0x1UL << LPCOMP_INTENSET_DOWN_Pos) /*!< Bit mask of DOWN field. */
2647 #define LPCOMP_INTENSET_DOWN_Disabled (0UL) /*!< Read: Disabled */
2648 #define LPCOMP_INTENSET_DOWN_Enabled (1UL) /*!< Read: Enabled */
2649 #define LPCOMP_INTENSET_DOWN_Set (1UL) /*!< Enable */
2650 
2651 /* Bit 0 : Write '1' to Enable interrupt for READY event */
2652 #define LPCOMP_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */
2653 #define LPCOMP_INTENSET_READY_Msk (0x1UL << LPCOMP_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
2654 #define LPCOMP_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */
2655 #define LPCOMP_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */
2656 #define LPCOMP_INTENSET_READY_Set (1UL) /*!< Enable */
2657 
2658 /* Register: LPCOMP_INTENCLR */
2659 /* Description: Disable interrupt */
2660 
2661 /* Bit 3 : Write '1' to Disable interrupt for CROSS event */
2662 #define LPCOMP_INTENCLR_CROSS_Pos (3UL) /*!< Position of CROSS field. */
2663 #define LPCOMP_INTENCLR_CROSS_Msk (0x1UL << LPCOMP_INTENCLR_CROSS_Pos) /*!< Bit mask of CROSS field. */
2664 #define LPCOMP_INTENCLR_CROSS_Disabled (0UL) /*!< Read: Disabled */
2665 #define LPCOMP_INTENCLR_CROSS_Enabled (1UL) /*!< Read: Enabled */
2666 #define LPCOMP_INTENCLR_CROSS_Clear (1UL) /*!< Disable */
2667 
2668 /* Bit 2 : Write '1' to Disable interrupt for UP event */
2669 #define LPCOMP_INTENCLR_UP_Pos (2UL) /*!< Position of UP field. */
2670 #define LPCOMP_INTENCLR_UP_Msk (0x1UL << LPCOMP_INTENCLR_UP_Pos) /*!< Bit mask of UP field. */
2671 #define LPCOMP_INTENCLR_UP_Disabled (0UL) /*!< Read: Disabled */
2672 #define LPCOMP_INTENCLR_UP_Enabled (1UL) /*!< Read: Enabled */
2673 #define LPCOMP_INTENCLR_UP_Clear (1UL) /*!< Disable */
2674 
2675 /* Bit 1 : Write '1' to Disable interrupt for DOWN event */
2676 #define LPCOMP_INTENCLR_DOWN_Pos (1UL) /*!< Position of DOWN field. */
2677 #define LPCOMP_INTENCLR_DOWN_Msk (0x1UL << LPCOMP_INTENCLR_DOWN_Pos) /*!< Bit mask of DOWN field. */
2678 #define LPCOMP_INTENCLR_DOWN_Disabled (0UL) /*!< Read: Disabled */
2679 #define LPCOMP_INTENCLR_DOWN_Enabled (1UL) /*!< Read: Enabled */
2680 #define LPCOMP_INTENCLR_DOWN_Clear (1UL) /*!< Disable */
2681 
2682 /* Bit 0 : Write '1' to Disable interrupt for READY event */
2683 #define LPCOMP_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */
2684 #define LPCOMP_INTENCLR_READY_Msk (0x1UL << LPCOMP_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
2685 #define LPCOMP_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */
2686 #define LPCOMP_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */
2687 #define LPCOMP_INTENCLR_READY_Clear (1UL) /*!< Disable */
2688 
2689 /* Register: LPCOMP_RESULT */
2690 /* Description: Compare result */
2691 
2692 /* Bit 0 : Result of last compare. Decision point SAMPLE task. */
2693 #define LPCOMP_RESULT_RESULT_Pos (0UL) /*!< Position of RESULT field. */
2694 #define LPCOMP_RESULT_RESULT_Msk (0x1UL << LPCOMP_RESULT_RESULT_Pos) /*!< Bit mask of RESULT field. */
2695 #define LPCOMP_RESULT_RESULT_Below (0UL) /*!< Input voltage is below the reference threshold (VIN+ &lt; VIN-). */
2696 #define LPCOMP_RESULT_RESULT_Above (1UL) /*!< Input voltage is above the reference threshold (VIN+ &gt; VIN-). */
2697 
2698 /* Register: LPCOMP_ENABLE */
2699 /* Description: Enable LPCOMP */
2700 
2701 /* Bits 1..0 : Enable or disable LPCOMP */
2702 #define LPCOMP_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
2703 #define LPCOMP_ENABLE_ENABLE_Msk (0x3UL << LPCOMP_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
2704 #define LPCOMP_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
2705 #define LPCOMP_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */
2706 
2707 /* Register: LPCOMP_PSEL */
2708 /* Description: Input pin select */
2709 
2710 /* Bits 2..0 : Analog pin select */
2711 #define LPCOMP_PSEL_PSEL_Pos (0UL) /*!< Position of PSEL field. */
2712 #define LPCOMP_PSEL_PSEL_Msk (0x7UL << LPCOMP_PSEL_PSEL_Pos) /*!< Bit mask of PSEL field. */
2713 #define LPCOMP_PSEL_PSEL_AnalogInput0 (0UL) /*!< AIN0 selected as analog input */
2714 #define LPCOMP_PSEL_PSEL_AnalogInput1 (1UL) /*!< AIN1 selected as analog input */
2715 #define LPCOMP_PSEL_PSEL_AnalogInput2 (2UL) /*!< AIN2 selected as analog input */
2716 #define LPCOMP_PSEL_PSEL_AnalogInput3 (3UL) /*!< AIN3 selected as analog input */
2717 #define LPCOMP_PSEL_PSEL_AnalogInput4 (4UL) /*!< AIN4 selected as analog input */
2718 #define LPCOMP_PSEL_PSEL_AnalogInput5 (5UL) /*!< AIN5 selected as analog input */
2719 #define LPCOMP_PSEL_PSEL_AnalogInput6 (6UL) /*!< AIN6 selected as analog input */
2720 #define LPCOMP_PSEL_PSEL_AnalogInput7 (7UL) /*!< AIN7 selected as analog input */
2721 
2722 /* Register: LPCOMP_REFSEL */
2723 /* Description: Reference select */
2724 
2725 /* Bits 3..0 : Reference select */
2726 #define LPCOMP_REFSEL_REFSEL_Pos (0UL) /*!< Position of REFSEL field. */
2727 #define LPCOMP_REFSEL_REFSEL_Msk (0xFUL << LPCOMP_REFSEL_REFSEL_Pos) /*!< Bit mask of REFSEL field. */
2728 #define LPCOMP_REFSEL_REFSEL_Ref1_8Vdd (0UL) /*!< VDD * 1/8 selected as reference */
2729 #define LPCOMP_REFSEL_REFSEL_Ref2_8Vdd (1UL) /*!< VDD * 2/8 selected as reference */
2730 #define LPCOMP_REFSEL_REFSEL_Ref3_8Vdd (2UL) /*!< VDD * 3/8 selected as reference */
2731 #define LPCOMP_REFSEL_REFSEL_Ref4_8Vdd (3UL) /*!< VDD * 4/8 selected as reference */
2732 #define LPCOMP_REFSEL_REFSEL_Ref5_8Vdd (4UL) /*!< VDD * 5/8 selected as reference */
2733 #define LPCOMP_REFSEL_REFSEL_Ref6_8Vdd (5UL) /*!< VDD * 6/8 selected as reference */
2734 #define LPCOMP_REFSEL_REFSEL_Ref7_8Vdd (6UL) /*!< VDD * 7/8 selected as reference */
2735 #define LPCOMP_REFSEL_REFSEL_ARef (7UL) /*!< External analog reference selected */
2736 #define LPCOMP_REFSEL_REFSEL_Ref1_16Vdd (8UL) /*!< VDD * 1/16 selected as reference */
2737 #define LPCOMP_REFSEL_REFSEL_Ref3_16Vdd (9UL) /*!< VDD * 3/16 selected as reference */
2738 #define LPCOMP_REFSEL_REFSEL_Ref5_16Vdd (10UL) /*!< VDD * 5/16 selected as reference */
2739 #define LPCOMP_REFSEL_REFSEL_Ref7_16Vdd (11UL) /*!< VDD * 7/16 selected as reference */
2740 #define LPCOMP_REFSEL_REFSEL_Ref9_16Vdd (12UL) /*!< VDD * 9/16 selected as reference */
2741 #define LPCOMP_REFSEL_REFSEL_Ref11_16Vdd (13UL) /*!< VDD * 11/16 selected as reference */
2742 #define LPCOMP_REFSEL_REFSEL_Ref13_16Vdd (14UL) /*!< VDD * 13/16 selected as reference */
2743 #define LPCOMP_REFSEL_REFSEL_Ref15_16Vdd (15UL) /*!< VDD * 15/16 selected as reference */
2744 
2745 /* Register: LPCOMP_EXTREFSEL */
2746 /* Description: External reference select */
2747 
2748 /* Bit 0 : External analog reference select */
2749 #define LPCOMP_EXTREFSEL_EXTREFSEL_Pos (0UL) /*!< Position of EXTREFSEL field. */
2750 #define LPCOMP_EXTREFSEL_EXTREFSEL_Msk (0x1UL << LPCOMP_EXTREFSEL_EXTREFSEL_Pos) /*!< Bit mask of EXTREFSEL field. */
2751 #define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference0 (0UL) /*!< Use AIN0 as external analog reference */
2752 #define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference1 (1UL) /*!< Use AIN1 as external analog reference */
2753 
2754 /* Register: LPCOMP_ANADETECT */
2755 /* Description: Analog detect configuration */
2756 
2757 /* Bits 1..0 : Analog detect configuration */
2758 #define LPCOMP_ANADETECT_ANADETECT_Pos (0UL) /*!< Position of ANADETECT field. */
2759 #define LPCOMP_ANADETECT_ANADETECT_Msk (0x3UL << LPCOMP_ANADETECT_ANADETECT_Pos) /*!< Bit mask of ANADETECT field. */
2760 #define LPCOMP_ANADETECT_ANADETECT_Cross (0UL) /*!< Generate ANADETECT on crossing, both upward crossing and downward crossing */
2761 #define LPCOMP_ANADETECT_ANADETECT_Up (1UL) /*!< Generate ANADETECT on upward crossing only */
2762 #define LPCOMP_ANADETECT_ANADETECT_Down (2UL) /*!< Generate ANADETECT on downward crossing only */
2763 
2764 /* Register: LPCOMP_HYST */
2765 /* Description: Comparator hysteresis enable */
2766 
2767 /* Bit 0 : Comparator hysteresis enable */
2768 #define LPCOMP_HYST_HYST_Pos (0UL) /*!< Position of HYST field. */
2769 #define LPCOMP_HYST_HYST_Msk (0x1UL << LPCOMP_HYST_HYST_Pos) /*!< Bit mask of HYST field. */
2770 #define LPCOMP_HYST_HYST_NoHyst (0UL) /*!< Comparator hysteresis disabled */
2771 #define LPCOMP_HYST_HYST_Hyst50mV (1UL) /*!< Comparator hysteresis disabled (typ. 50 mV) */
2772 
2773 
2774 /* Peripheral: MWU */
2775 /* Description: Memory Watch Unit */
2776 
2777 /* Register: MWU_INTEN */
2778 /* Description: Enable or disable interrupt */
2779 
2780 /* Bit 27 : Enable or disable interrupt for PREGION[1].RA event */
2781 #define MWU_INTEN_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */
2782 #define MWU_INTEN_PREGION1RA_Msk (0x1UL << MWU_INTEN_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */
2783 #define MWU_INTEN_PREGION1RA_Disabled (0UL) /*!< Disable */
2784 #define MWU_INTEN_PREGION1RA_Enabled (1UL) /*!< Enable */
2785 
2786 /* Bit 26 : Enable or disable interrupt for PREGION[1].WA event */
2787 #define MWU_INTEN_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */
2788 #define MWU_INTEN_PREGION1WA_Msk (0x1UL << MWU_INTEN_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */
2789 #define MWU_INTEN_PREGION1WA_Disabled (0UL) /*!< Disable */
2790 #define MWU_INTEN_PREGION1WA_Enabled (1UL) /*!< Enable */
2791 
2792 /* Bit 25 : Enable or disable interrupt for PREGION[0].RA event */
2793 #define MWU_INTEN_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */
2794 #define MWU_INTEN_PREGION0RA_Msk (0x1UL << MWU_INTEN_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */
2795 #define MWU_INTEN_PREGION0RA_Disabled (0UL) /*!< Disable */
2796 #define MWU_INTEN_PREGION0RA_Enabled (1UL) /*!< Enable */
2797 
2798 /* Bit 24 : Enable or disable interrupt for PREGION[0].WA event */
2799 #define MWU_INTEN_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */
2800 #define MWU_INTEN_PREGION0WA_Msk (0x1UL << MWU_INTEN_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */
2801 #define MWU_INTEN_PREGION0WA_Disabled (0UL) /*!< Disable */
2802 #define MWU_INTEN_PREGION0WA_Enabled (1UL) /*!< Enable */
2803 
2804 /* Bit 7 : Enable or disable interrupt for REGION[3].RA event */
2805 #define MWU_INTEN_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */
2806 #define MWU_INTEN_REGION3RA_Msk (0x1UL << MWU_INTEN_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */
2807 #define MWU_INTEN_REGION3RA_Disabled (0UL) /*!< Disable */
2808 #define MWU_INTEN_REGION3RA_Enabled (1UL) /*!< Enable */
2809 
2810 /* Bit 6 : Enable or disable interrupt for REGION[3].WA event */
2811 #define MWU_INTEN_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */
2812 #define MWU_INTEN_REGION3WA_Msk (0x1UL << MWU_INTEN_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */
2813 #define MWU_INTEN_REGION3WA_Disabled (0UL) /*!< Disable */
2814 #define MWU_INTEN_REGION3WA_Enabled (1UL) /*!< Enable */
2815 
2816 /* Bit 5 : Enable or disable interrupt for REGION[2].RA event */
2817 #define MWU_INTEN_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */
2818 #define MWU_INTEN_REGION2RA_Msk (0x1UL << MWU_INTEN_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */
2819 #define MWU_INTEN_REGION2RA_Disabled (0UL) /*!< Disable */
2820 #define MWU_INTEN_REGION2RA_Enabled (1UL) /*!< Enable */
2821 
2822 /* Bit 4 : Enable or disable interrupt for REGION[2].WA event */
2823 #define MWU_INTEN_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */
2824 #define MWU_INTEN_REGION2WA_Msk (0x1UL << MWU_INTEN_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */
2825 #define MWU_INTEN_REGION2WA_Disabled (0UL) /*!< Disable */
2826 #define MWU_INTEN_REGION2WA_Enabled (1UL) /*!< Enable */
2827 
2828 /* Bit 3 : Enable or disable interrupt for REGION[1].RA event */
2829 #define MWU_INTEN_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */
2830 #define MWU_INTEN_REGION1RA_Msk (0x1UL << MWU_INTEN_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */
2831 #define MWU_INTEN_REGION1RA_Disabled (0UL) /*!< Disable */
2832 #define MWU_INTEN_REGION1RA_Enabled (1UL) /*!< Enable */
2833 
2834 /* Bit 2 : Enable or disable interrupt for REGION[1].WA event */
2835 #define MWU_INTEN_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */
2836 #define MWU_INTEN_REGION1WA_Msk (0x1UL << MWU_INTEN_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */
2837 #define MWU_INTEN_REGION1WA_Disabled (0UL) /*!< Disable */
2838 #define MWU_INTEN_REGION1WA_Enabled (1UL) /*!< Enable */
2839 
2840 /* Bit 1 : Enable or disable interrupt for REGION[0].RA event */
2841 #define MWU_INTEN_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */
2842 #define MWU_INTEN_REGION0RA_Msk (0x1UL << MWU_INTEN_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */
2843 #define MWU_INTEN_REGION0RA_Disabled (0UL) /*!< Disable */
2844 #define MWU_INTEN_REGION0RA_Enabled (1UL) /*!< Enable */
2845 
2846 /* Bit 0 : Enable or disable interrupt for REGION[0].WA event */
2847 #define MWU_INTEN_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */
2848 #define MWU_INTEN_REGION0WA_Msk (0x1UL << MWU_INTEN_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */
2849 #define MWU_INTEN_REGION0WA_Disabled (0UL) /*!< Disable */
2850 #define MWU_INTEN_REGION0WA_Enabled (1UL) /*!< Enable */
2851 
2852 /* Register: MWU_INTENSET */
2853 /* Description: Enable interrupt */
2854 
2855 /* Bit 27 : Write '1' to Enable interrupt for PREGION[1].RA event */
2856 #define MWU_INTENSET_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */
2857 #define MWU_INTENSET_PREGION1RA_Msk (0x1UL << MWU_INTENSET_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */
2858 #define MWU_INTENSET_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */
2859 #define MWU_INTENSET_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */
2860 #define MWU_INTENSET_PREGION1RA_Set (1UL) /*!< Enable */
2861 
2862 /* Bit 26 : Write '1' to Enable interrupt for PREGION[1].WA event */
2863 #define MWU_INTENSET_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */
2864 #define MWU_INTENSET_PREGION1WA_Msk (0x1UL << MWU_INTENSET_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */
2865 #define MWU_INTENSET_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */
2866 #define MWU_INTENSET_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */
2867 #define MWU_INTENSET_PREGION1WA_Set (1UL) /*!< Enable */
2868 
2869 /* Bit 25 : Write '1' to Enable interrupt for PREGION[0].RA event */
2870 #define MWU_INTENSET_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */
2871 #define MWU_INTENSET_PREGION0RA_Msk (0x1UL << MWU_INTENSET_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */
2872 #define MWU_INTENSET_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */
2873 #define MWU_INTENSET_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */
2874 #define MWU_INTENSET_PREGION0RA_Set (1UL) /*!< Enable */
2875 
2876 /* Bit 24 : Write '1' to Enable interrupt for PREGION[0].WA event */
2877 #define MWU_INTENSET_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */
2878 #define MWU_INTENSET_PREGION0WA_Msk (0x1UL << MWU_INTENSET_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */
2879 #define MWU_INTENSET_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */
2880 #define MWU_INTENSET_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */
2881 #define MWU_INTENSET_PREGION0WA_Set (1UL) /*!< Enable */
2882 
2883 /* Bit 7 : Write '1' to Enable interrupt for REGION[3].RA event */
2884 #define MWU_INTENSET_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */
2885 #define MWU_INTENSET_REGION3RA_Msk (0x1UL << MWU_INTENSET_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */
2886 #define MWU_INTENSET_REGION3RA_Disabled (0UL) /*!< Read: Disabled */
2887 #define MWU_INTENSET_REGION3RA_Enabled (1UL) /*!< Read: Enabled */
2888 #define MWU_INTENSET_REGION3RA_Set (1UL) /*!< Enable */
2889 
2890 /* Bit 6 : Write '1' to Enable interrupt for REGION[3].WA event */
2891 #define MWU_INTENSET_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */
2892 #define MWU_INTENSET_REGION3WA_Msk (0x1UL << MWU_INTENSET_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */
2893 #define MWU_INTENSET_REGION3WA_Disabled (0UL) /*!< Read: Disabled */
2894 #define MWU_INTENSET_REGION3WA_Enabled (1UL) /*!< Read: Enabled */
2895 #define MWU_INTENSET_REGION3WA_Set (1UL) /*!< Enable */
2896 
2897 /* Bit 5 : Write '1' to Enable interrupt for REGION[2].RA event */
2898 #define MWU_INTENSET_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */
2899 #define MWU_INTENSET_REGION2RA_Msk (0x1UL << MWU_INTENSET_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */
2900 #define MWU_INTENSET_REGION2RA_Disabled (0UL) /*!< Read: Disabled */
2901 #define MWU_INTENSET_REGION2RA_Enabled (1UL) /*!< Read: Enabled */
2902 #define MWU_INTENSET_REGION2RA_Set (1UL) /*!< Enable */
2903 
2904 /* Bit 4 : Write '1' to Enable interrupt for REGION[2].WA event */
2905 #define MWU_INTENSET_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */
2906 #define MWU_INTENSET_REGION2WA_Msk (0x1UL << MWU_INTENSET_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */
2907 #define MWU_INTENSET_REGION2WA_Disabled (0UL) /*!< Read: Disabled */
2908 #define MWU_INTENSET_REGION2WA_Enabled (1UL) /*!< Read: Enabled */
2909 #define MWU_INTENSET_REGION2WA_Set (1UL) /*!< Enable */
2910 
2911 /* Bit 3 : Write '1' to Enable interrupt for REGION[1].RA event */
2912 #define MWU_INTENSET_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */
2913 #define MWU_INTENSET_REGION1RA_Msk (0x1UL << MWU_INTENSET_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */
2914 #define MWU_INTENSET_REGION1RA_Disabled (0UL) /*!< Read: Disabled */
2915 #define MWU_INTENSET_REGION1RA_Enabled (1UL) /*!< Read: Enabled */
2916 #define MWU_INTENSET_REGION1RA_Set (1UL) /*!< Enable */
2917 
2918 /* Bit 2 : Write '1' to Enable interrupt for REGION[1].WA event */
2919 #define MWU_INTENSET_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */
2920 #define MWU_INTENSET_REGION1WA_Msk (0x1UL << MWU_INTENSET_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */
2921 #define MWU_INTENSET_REGION1WA_Disabled (0UL) /*!< Read: Disabled */
2922 #define MWU_INTENSET_REGION1WA_Enabled (1UL) /*!< Read: Enabled */
2923 #define MWU_INTENSET_REGION1WA_Set (1UL) /*!< Enable */
2924 
2925 /* Bit 1 : Write '1' to Enable interrupt for REGION[0].RA event */
2926 #define MWU_INTENSET_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */
2927 #define MWU_INTENSET_REGION0RA_Msk (0x1UL << MWU_INTENSET_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */
2928 #define MWU_INTENSET_REGION0RA_Disabled (0UL) /*!< Read: Disabled */
2929 #define MWU_INTENSET_REGION0RA_Enabled (1UL) /*!< Read: Enabled */
2930 #define MWU_INTENSET_REGION0RA_Set (1UL) /*!< Enable */
2931 
2932 /* Bit 0 : Write '1' to Enable interrupt for REGION[0].WA event */
2933 #define MWU_INTENSET_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */
2934 #define MWU_INTENSET_REGION0WA_Msk (0x1UL << MWU_INTENSET_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */
2935 #define MWU_INTENSET_REGION0WA_Disabled (0UL) /*!< Read: Disabled */
2936 #define MWU_INTENSET_REGION0WA_Enabled (1UL) /*!< Read: Enabled */
2937 #define MWU_INTENSET_REGION0WA_Set (1UL) /*!< Enable */
2938 
2939 /* Register: MWU_INTENCLR */
2940 /* Description: Disable interrupt */
2941 
2942 /* Bit 27 : Write '1' to Disable interrupt for PREGION[1].RA event */
2943 #define MWU_INTENCLR_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */
2944 #define MWU_INTENCLR_PREGION1RA_Msk (0x1UL << MWU_INTENCLR_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */
2945 #define MWU_INTENCLR_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */
2946 #define MWU_INTENCLR_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */
2947 #define MWU_INTENCLR_PREGION1RA_Clear (1UL) /*!< Disable */
2948 
2949 /* Bit 26 : Write '1' to Disable interrupt for PREGION[1].WA event */
2950 #define MWU_INTENCLR_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */
2951 #define MWU_INTENCLR_PREGION1WA_Msk (0x1UL << MWU_INTENCLR_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */
2952 #define MWU_INTENCLR_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */
2953 #define MWU_INTENCLR_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */
2954 #define MWU_INTENCLR_PREGION1WA_Clear (1UL) /*!< Disable */
2955 
2956 /* Bit 25 : Write '1' to Disable interrupt for PREGION[0].RA event */
2957 #define MWU_INTENCLR_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */
2958 #define MWU_INTENCLR_PREGION0RA_Msk (0x1UL << MWU_INTENCLR_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */
2959 #define MWU_INTENCLR_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */
2960 #define MWU_INTENCLR_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */
2961 #define MWU_INTENCLR_PREGION0RA_Clear (1UL) /*!< Disable */
2962 
2963 /* Bit 24 : Write '1' to Disable interrupt for PREGION[0].WA event */
2964 #define MWU_INTENCLR_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */
2965 #define MWU_INTENCLR_PREGION0WA_Msk (0x1UL << MWU_INTENCLR_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */
2966 #define MWU_INTENCLR_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */
2967 #define MWU_INTENCLR_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */
2968 #define MWU_INTENCLR_PREGION0WA_Clear (1UL) /*!< Disable */
2969 
2970 /* Bit 7 : Write '1' to Disable interrupt for REGION[3].RA event */
2971 #define MWU_INTENCLR_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */
2972 #define MWU_INTENCLR_REGION3RA_Msk (0x1UL << MWU_INTENCLR_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */
2973 #define MWU_INTENCLR_REGION3RA_Disabled (0UL) /*!< Read: Disabled */
2974 #define MWU_INTENCLR_REGION3RA_Enabled (1UL) /*!< Read: Enabled */
2975 #define MWU_INTENCLR_REGION3RA_Clear (1UL) /*!< Disable */
2976 
2977 /* Bit 6 : Write '1' to Disable interrupt for REGION[3].WA event */
2978 #define MWU_INTENCLR_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */
2979 #define MWU_INTENCLR_REGION3WA_Msk (0x1UL << MWU_INTENCLR_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */
2980 #define MWU_INTENCLR_REGION3WA_Disabled (0UL) /*!< Read: Disabled */
2981 #define MWU_INTENCLR_REGION3WA_Enabled (1UL) /*!< Read: Enabled */
2982 #define MWU_INTENCLR_REGION3WA_Clear (1UL) /*!< Disable */
2983 
2984 /* Bit 5 : Write '1' to Disable interrupt for REGION[2].RA event */
2985 #define MWU_INTENCLR_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */
2986 #define MWU_INTENCLR_REGION2RA_Msk (0x1UL << MWU_INTENCLR_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */
2987 #define MWU_INTENCLR_REGION2RA_Disabled (0UL) /*!< Read: Disabled */
2988 #define MWU_INTENCLR_REGION2RA_Enabled (1UL) /*!< Read: Enabled */
2989 #define MWU_INTENCLR_REGION2RA_Clear (1UL) /*!< Disable */
2990 
2991 /* Bit 4 : Write '1' to Disable interrupt for REGION[2].WA event */
2992 #define MWU_INTENCLR_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */
2993 #define MWU_INTENCLR_REGION2WA_Msk (0x1UL << MWU_INTENCLR_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */
2994 #define MWU_INTENCLR_REGION2WA_Disabled (0UL) /*!< Read: Disabled */
2995 #define MWU_INTENCLR_REGION2WA_Enabled (1UL) /*!< Read: Enabled */
2996 #define MWU_INTENCLR_REGION2WA_Clear (1UL) /*!< Disable */
2997 
2998 /* Bit 3 : Write '1' to Disable interrupt for REGION[1].RA event */
2999 #define MWU_INTENCLR_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */
3000 #define MWU_INTENCLR_REGION1RA_Msk (0x1UL << MWU_INTENCLR_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */
3001 #define MWU_INTENCLR_REGION1RA_Disabled (0UL) /*!< Read: Disabled */
3002 #define MWU_INTENCLR_REGION1RA_Enabled (1UL) /*!< Read: Enabled */
3003 #define MWU_INTENCLR_REGION1RA_Clear (1UL) /*!< Disable */
3004 
3005 /* Bit 2 : Write '1' to Disable interrupt for REGION[1].WA event */
3006 #define MWU_INTENCLR_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */
3007 #define MWU_INTENCLR_REGION1WA_Msk (0x1UL << MWU_INTENCLR_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */
3008 #define MWU_INTENCLR_REGION1WA_Disabled (0UL) /*!< Read: Disabled */
3009 #define MWU_INTENCLR_REGION1WA_Enabled (1UL) /*!< Read: Enabled */
3010 #define MWU_INTENCLR_REGION1WA_Clear (1UL) /*!< Disable */
3011 
3012 /* Bit 1 : Write '1' to Disable interrupt for REGION[0].RA event */
3013 #define MWU_INTENCLR_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */
3014 #define MWU_INTENCLR_REGION0RA_Msk (0x1UL << MWU_INTENCLR_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */
3015 #define MWU_INTENCLR_REGION0RA_Disabled (0UL) /*!< Read: Disabled */
3016 #define MWU_INTENCLR_REGION0RA_Enabled (1UL) /*!< Read: Enabled */
3017 #define MWU_INTENCLR_REGION0RA_Clear (1UL) /*!< Disable */
3018 
3019 /* Bit 0 : Write '1' to Disable interrupt for REGION[0].WA event */
3020 #define MWU_INTENCLR_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */
3021 #define MWU_INTENCLR_REGION0WA_Msk (0x1UL << MWU_INTENCLR_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */
3022 #define MWU_INTENCLR_REGION0WA_Disabled (0UL) /*!< Read: Disabled */
3023 #define MWU_INTENCLR_REGION0WA_Enabled (1UL) /*!< Read: Enabled */
3024 #define MWU_INTENCLR_REGION0WA_Clear (1UL) /*!< Disable */
3025 
3026 /* Register: MWU_NMIEN */
3027 /* Description: Enable or disable non-maskable interrupt */
3028 
3029 /* Bit 27 : Enable or disable non-maskable interrupt for PREGION[1].RA event */
3030 #define MWU_NMIEN_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */
3031 #define MWU_NMIEN_PREGION1RA_Msk (0x1UL << MWU_NMIEN_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */
3032 #define MWU_NMIEN_PREGION1RA_Disabled (0UL) /*!< Disable */
3033 #define MWU_NMIEN_PREGION1RA_Enabled (1UL) /*!< Enable */
3034 
3035 /* Bit 26 : Enable or disable non-maskable interrupt for PREGION[1].WA event */
3036 #define MWU_NMIEN_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */
3037 #define MWU_NMIEN_PREGION1WA_Msk (0x1UL << MWU_NMIEN_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */
3038 #define MWU_NMIEN_PREGION1WA_Disabled (0UL) /*!< Disable */
3039 #define MWU_NMIEN_PREGION1WA_Enabled (1UL) /*!< Enable */
3040 
3041 /* Bit 25 : Enable or disable non-maskable interrupt for PREGION[0].RA event */
3042 #define MWU_NMIEN_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */
3043 #define MWU_NMIEN_PREGION0RA_Msk (0x1UL << MWU_NMIEN_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */
3044 #define MWU_NMIEN_PREGION0RA_Disabled (0UL) /*!< Disable */
3045 #define MWU_NMIEN_PREGION0RA_Enabled (1UL) /*!< Enable */
3046 
3047 /* Bit 24 : Enable or disable non-maskable interrupt for PREGION[0].WA event */
3048 #define MWU_NMIEN_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */
3049 #define MWU_NMIEN_PREGION0WA_Msk (0x1UL << MWU_NMIEN_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */
3050 #define MWU_NMIEN_PREGION0WA_Disabled (0UL) /*!< Disable */
3051 #define MWU_NMIEN_PREGION0WA_Enabled (1UL) /*!< Enable */
3052 
3053 /* Bit 7 : Enable or disable non-maskable interrupt for REGION[3].RA event */
3054 #define MWU_NMIEN_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */
3055 #define MWU_NMIEN_REGION3RA_Msk (0x1UL << MWU_NMIEN_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */
3056 #define MWU_NMIEN_REGION3RA_Disabled (0UL) /*!< Disable */
3057 #define MWU_NMIEN_REGION3RA_Enabled (1UL) /*!< Enable */
3058 
3059 /* Bit 6 : Enable or disable non-maskable interrupt for REGION[3].WA event */
3060 #define MWU_NMIEN_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */
3061 #define MWU_NMIEN_REGION3WA_Msk (0x1UL << MWU_NMIEN_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */
3062 #define MWU_NMIEN_REGION3WA_Disabled (0UL) /*!< Disable */
3063 #define MWU_NMIEN_REGION3WA_Enabled (1UL) /*!< Enable */
3064 
3065 /* Bit 5 : Enable or disable non-maskable interrupt for REGION[2].RA event */
3066 #define MWU_NMIEN_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */
3067 #define MWU_NMIEN_REGION2RA_Msk (0x1UL << MWU_NMIEN_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */
3068 #define MWU_NMIEN_REGION2RA_Disabled (0UL) /*!< Disable */
3069 #define MWU_NMIEN_REGION2RA_Enabled (1UL) /*!< Enable */
3070 
3071 /* Bit 4 : Enable or disable non-maskable interrupt for REGION[2].WA event */
3072 #define MWU_NMIEN_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */
3073 #define MWU_NMIEN_REGION2WA_Msk (0x1UL << MWU_NMIEN_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */
3074 #define MWU_NMIEN_REGION2WA_Disabled (0UL) /*!< Disable */
3075 #define MWU_NMIEN_REGION2WA_Enabled (1UL) /*!< Enable */
3076 
3077 /* Bit 3 : Enable or disable non-maskable interrupt for REGION[1].RA event */
3078 #define MWU_NMIEN_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */
3079 #define MWU_NMIEN_REGION1RA_Msk (0x1UL << MWU_NMIEN_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */
3080 #define MWU_NMIEN_REGION1RA_Disabled (0UL) /*!< Disable */
3081 #define MWU_NMIEN_REGION1RA_Enabled (1UL) /*!< Enable */
3082 
3083 /* Bit 2 : Enable or disable non-maskable interrupt for REGION[1].WA event */
3084 #define MWU_NMIEN_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */
3085 #define MWU_NMIEN_REGION1WA_Msk (0x1UL << MWU_NMIEN_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */
3086 #define MWU_NMIEN_REGION1WA_Disabled (0UL) /*!< Disable */
3087 #define MWU_NMIEN_REGION1WA_Enabled (1UL) /*!< Enable */
3088 
3089 /* Bit 1 : Enable or disable non-maskable interrupt for REGION[0].RA event */
3090 #define MWU_NMIEN_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */
3091 #define MWU_NMIEN_REGION0RA_Msk (0x1UL << MWU_NMIEN_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */
3092 #define MWU_NMIEN_REGION0RA_Disabled (0UL) /*!< Disable */
3093 #define MWU_NMIEN_REGION0RA_Enabled (1UL) /*!< Enable */
3094 
3095 /* Bit 0 : Enable or disable non-maskable interrupt for REGION[0].WA event */
3096 #define MWU_NMIEN_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */
3097 #define MWU_NMIEN_REGION0WA_Msk (0x1UL << MWU_NMIEN_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */
3098 #define MWU_NMIEN_REGION0WA_Disabled (0UL) /*!< Disable */
3099 #define MWU_NMIEN_REGION0WA_Enabled (1UL) /*!< Enable */
3100 
3101 /* Register: MWU_NMIENSET */
3102 /* Description: Enable non-maskable interrupt */
3103 
3104 /* Bit 27 : Write '1' to Enable non-maskable interrupt for PREGION[1].RA event */
3105 #define MWU_NMIENSET_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */
3106 #define MWU_NMIENSET_PREGION1RA_Msk (0x1UL << MWU_NMIENSET_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */
3107 #define MWU_NMIENSET_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */
3108 #define MWU_NMIENSET_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */
3109 #define MWU_NMIENSET_PREGION1RA_Set (1UL) /*!< Enable */
3110 
3111 /* Bit 26 : Write '1' to Enable non-maskable interrupt for PREGION[1].WA event */
3112 #define MWU_NMIENSET_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */
3113 #define MWU_NMIENSET_PREGION1WA_Msk (0x1UL << MWU_NMIENSET_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */
3114 #define MWU_NMIENSET_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */
3115 #define MWU_NMIENSET_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */
3116 #define MWU_NMIENSET_PREGION1WA_Set (1UL) /*!< Enable */
3117 
3118 /* Bit 25 : Write '1' to Enable non-maskable interrupt for PREGION[0].RA event */
3119 #define MWU_NMIENSET_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */
3120 #define MWU_NMIENSET_PREGION0RA_Msk (0x1UL << MWU_NMIENSET_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */
3121 #define MWU_NMIENSET_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */
3122 #define MWU_NMIENSET_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */
3123 #define MWU_NMIENSET_PREGION0RA_Set (1UL) /*!< Enable */
3124 
3125 /* Bit 24 : Write '1' to Enable non-maskable interrupt for PREGION[0].WA event */
3126 #define MWU_NMIENSET_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */
3127 #define MWU_NMIENSET_PREGION0WA_Msk (0x1UL << MWU_NMIENSET_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */
3128 #define MWU_NMIENSET_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */
3129 #define MWU_NMIENSET_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */
3130 #define MWU_NMIENSET_PREGION0WA_Set (1UL) /*!< Enable */
3131 
3132 /* Bit 7 : Write '1' to Enable non-maskable interrupt for REGION[3].RA event */
3133 #define MWU_NMIENSET_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */
3134 #define MWU_NMIENSET_REGION3RA_Msk (0x1UL << MWU_NMIENSET_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */
3135 #define MWU_NMIENSET_REGION3RA_Disabled (0UL) /*!< Read: Disabled */
3136 #define MWU_NMIENSET_REGION3RA_Enabled (1UL) /*!< Read: Enabled */
3137 #define MWU_NMIENSET_REGION3RA_Set (1UL) /*!< Enable */
3138 
3139 /* Bit 6 : Write '1' to Enable non-maskable interrupt for REGION[3].WA event */
3140 #define MWU_NMIENSET_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */
3141 #define MWU_NMIENSET_REGION3WA_Msk (0x1UL << MWU_NMIENSET_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */
3142 #define MWU_NMIENSET_REGION3WA_Disabled (0UL) /*!< Read: Disabled */
3143 #define MWU_NMIENSET_REGION3WA_Enabled (1UL) /*!< Read: Enabled */
3144 #define MWU_NMIENSET_REGION3WA_Set (1UL) /*!< Enable */
3145 
3146 /* Bit 5 : Write '1' to Enable non-maskable interrupt for REGION[2].RA event */
3147 #define MWU_NMIENSET_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */
3148 #define MWU_NMIENSET_REGION2RA_Msk (0x1UL << MWU_NMIENSET_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */
3149 #define MWU_NMIENSET_REGION2RA_Disabled (0UL) /*!< Read: Disabled */
3150 #define MWU_NMIENSET_REGION2RA_Enabled (1UL) /*!< Read: Enabled */
3151 #define MWU_NMIENSET_REGION2RA_Set (1UL) /*!< Enable */
3152 
3153 /* Bit 4 : Write '1' to Enable non-maskable interrupt for REGION[2].WA event */
3154 #define MWU_NMIENSET_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */
3155 #define MWU_NMIENSET_REGION2WA_Msk (0x1UL << MWU_NMIENSET_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */
3156 #define MWU_NMIENSET_REGION2WA_Disabled (0UL) /*!< Read: Disabled */
3157 #define MWU_NMIENSET_REGION2WA_Enabled (1UL) /*!< Read: Enabled */
3158 #define MWU_NMIENSET_REGION2WA_Set (1UL) /*!< Enable */
3159 
3160 /* Bit 3 : Write '1' to Enable non-maskable interrupt for REGION[1].RA event */
3161 #define MWU_NMIENSET_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */
3162 #define MWU_NMIENSET_REGION1RA_Msk (0x1UL << MWU_NMIENSET_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */
3163 #define MWU_NMIENSET_REGION1RA_Disabled (0UL) /*!< Read: Disabled */
3164 #define MWU_NMIENSET_REGION1RA_Enabled (1UL) /*!< Read: Enabled */
3165 #define MWU_NMIENSET_REGION1RA_Set (1UL) /*!< Enable */
3166 
3167 /* Bit 2 : Write '1' to Enable non-maskable interrupt for REGION[1].WA event */
3168 #define MWU_NMIENSET_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */
3169 #define MWU_NMIENSET_REGION1WA_Msk (0x1UL << MWU_NMIENSET_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */
3170 #define MWU_NMIENSET_REGION1WA_Disabled (0UL) /*!< Read: Disabled */
3171 #define MWU_NMIENSET_REGION1WA_Enabled (1UL) /*!< Read: Enabled */
3172 #define MWU_NMIENSET_REGION1WA_Set (1UL) /*!< Enable */
3173 
3174 /* Bit 1 : Write '1' to Enable non-maskable interrupt for REGION[0].RA event */
3175 #define MWU_NMIENSET_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */
3176 #define MWU_NMIENSET_REGION0RA_Msk (0x1UL << MWU_NMIENSET_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */
3177 #define MWU_NMIENSET_REGION0RA_Disabled (0UL) /*!< Read: Disabled */
3178 #define MWU_NMIENSET_REGION0RA_Enabled (1UL) /*!< Read: Enabled */
3179 #define MWU_NMIENSET_REGION0RA_Set (1UL) /*!< Enable */
3180 
3181 /* Bit 0 : Write '1' to Enable non-maskable interrupt for REGION[0].WA event */
3182 #define MWU_NMIENSET_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */
3183 #define MWU_NMIENSET_REGION0WA_Msk (0x1UL << MWU_NMIENSET_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */
3184 #define MWU_NMIENSET_REGION0WA_Disabled (0UL) /*!< Read: Disabled */
3185 #define MWU_NMIENSET_REGION0WA_Enabled (1UL) /*!< Read: Enabled */
3186 #define MWU_NMIENSET_REGION0WA_Set (1UL) /*!< Enable */
3187 
3188 /* Register: MWU_NMIENCLR */
3189 /* Description: Disable non-maskable interrupt */
3190 
3191 /* Bit 27 : Write '1' to Disable non-maskable interrupt for PREGION[1].RA event */
3192 #define MWU_NMIENCLR_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */
3193 #define MWU_NMIENCLR_PREGION1RA_Msk (0x1UL << MWU_NMIENCLR_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */
3194 #define MWU_NMIENCLR_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */
3195 #define MWU_NMIENCLR_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */
3196 #define MWU_NMIENCLR_PREGION1RA_Clear (1UL) /*!< Disable */
3197 
3198 /* Bit 26 : Write '1' to Disable non-maskable interrupt for PREGION[1].WA event */
3199 #define MWU_NMIENCLR_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */
3200 #define MWU_NMIENCLR_PREGION1WA_Msk (0x1UL << MWU_NMIENCLR_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */
3201 #define MWU_NMIENCLR_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */
3202 #define MWU_NMIENCLR_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */
3203 #define MWU_NMIENCLR_PREGION1WA_Clear (1UL) /*!< Disable */
3204 
3205 /* Bit 25 : Write '1' to Disable non-maskable interrupt for PREGION[0].RA event */
3206 #define MWU_NMIENCLR_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */
3207 #define MWU_NMIENCLR_PREGION0RA_Msk (0x1UL << MWU_NMIENCLR_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */
3208 #define MWU_NMIENCLR_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */
3209 #define MWU_NMIENCLR_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */
3210 #define MWU_NMIENCLR_PREGION0RA_Clear (1UL) /*!< Disable */
3211 
3212 /* Bit 24 : Write '1' to Disable non-maskable interrupt for PREGION[0].WA event */
3213 #define MWU_NMIENCLR_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */
3214 #define MWU_NMIENCLR_PREGION0WA_Msk (0x1UL << MWU_NMIENCLR_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */
3215 #define MWU_NMIENCLR_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */
3216 #define MWU_NMIENCLR_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */
3217 #define MWU_NMIENCLR_PREGION0WA_Clear (1UL) /*!< Disable */
3218 
3219 /* Bit 7 : Write '1' to Disable non-maskable interrupt for REGION[3].RA event */
3220 #define MWU_NMIENCLR_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */
3221 #define MWU_NMIENCLR_REGION3RA_Msk (0x1UL << MWU_NMIENCLR_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */
3222 #define MWU_NMIENCLR_REGION3RA_Disabled (0UL) /*!< Read: Disabled */
3223 #define MWU_NMIENCLR_REGION3RA_Enabled (1UL) /*!< Read: Enabled */
3224 #define MWU_NMIENCLR_REGION3RA_Clear (1UL) /*!< Disable */
3225 
3226 /* Bit 6 : Write '1' to Disable non-maskable interrupt for REGION[3].WA event */
3227 #define MWU_NMIENCLR_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */
3228 #define MWU_NMIENCLR_REGION3WA_Msk (0x1UL << MWU_NMIENCLR_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */
3229 #define MWU_NMIENCLR_REGION3WA_Disabled (0UL) /*!< Read: Disabled */
3230 #define MWU_NMIENCLR_REGION3WA_Enabled (1UL) /*!< Read: Enabled */
3231 #define MWU_NMIENCLR_REGION3WA_Clear (1UL) /*!< Disable */
3232 
3233 /* Bit 5 : Write '1' to Disable non-maskable interrupt for REGION[2].RA event */
3234 #define MWU_NMIENCLR_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */
3235 #define MWU_NMIENCLR_REGION2RA_Msk (0x1UL << MWU_NMIENCLR_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */
3236 #define MWU_NMIENCLR_REGION2RA_Disabled (0UL) /*!< Read: Disabled */
3237 #define MWU_NMIENCLR_REGION2RA_Enabled (1UL) /*!< Read: Enabled */
3238 #define MWU_NMIENCLR_REGION2RA_Clear (1UL) /*!< Disable */
3239 
3240 /* Bit 4 : Write '1' to Disable non-maskable interrupt for REGION[2].WA event */
3241 #define MWU_NMIENCLR_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */
3242 #define MWU_NMIENCLR_REGION2WA_Msk (0x1UL << MWU_NMIENCLR_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */
3243 #define MWU_NMIENCLR_REGION2WA_Disabled (0UL) /*!< Read: Disabled */
3244 #define MWU_NMIENCLR_REGION2WA_Enabled (1UL) /*!< Read: Enabled */
3245 #define MWU_NMIENCLR_REGION2WA_Clear (1UL) /*!< Disable */
3246 
3247 /* Bit 3 : Write '1' to Disable non-maskable interrupt for REGION[1].RA event */
3248 #define MWU_NMIENCLR_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */
3249 #define MWU_NMIENCLR_REGION1RA_Msk (0x1UL << MWU_NMIENCLR_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */
3250 #define MWU_NMIENCLR_REGION1RA_Disabled (0UL) /*!< Read: Disabled */
3251 #define MWU_NMIENCLR_REGION1RA_Enabled (1UL) /*!< Read: Enabled */
3252 #define MWU_NMIENCLR_REGION1RA_Clear (1UL) /*!< Disable */
3253 
3254 /* Bit 2 : Write '1' to Disable non-maskable interrupt for REGION[1].WA event */
3255 #define MWU_NMIENCLR_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */
3256 #define MWU_NMIENCLR_REGION1WA_Msk (0x1UL << MWU_NMIENCLR_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */
3257 #define MWU_NMIENCLR_REGION1WA_Disabled (0UL) /*!< Read: Disabled */
3258 #define MWU_NMIENCLR_REGION1WA_Enabled (1UL) /*!< Read: Enabled */
3259 #define MWU_NMIENCLR_REGION1WA_Clear (1UL) /*!< Disable */
3260 
3261 /* Bit 1 : Write '1' to Disable non-maskable interrupt for REGION[0].RA event */
3262 #define MWU_NMIENCLR_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */
3263 #define MWU_NMIENCLR_REGION0RA_Msk (0x1UL << MWU_NMIENCLR_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */
3264 #define MWU_NMIENCLR_REGION0RA_Disabled (0UL) /*!< Read: Disabled */
3265 #define MWU_NMIENCLR_REGION0RA_Enabled (1UL) /*!< Read: Enabled */
3266 #define MWU_NMIENCLR_REGION0RA_Clear (1UL) /*!< Disable */
3267 
3268 /* Bit 0 : Write '1' to Disable non-maskable interrupt for REGION[0].WA event */
3269 #define MWU_NMIENCLR_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */
3270 #define MWU_NMIENCLR_REGION0WA_Msk (0x1UL << MWU_NMIENCLR_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */
3271 #define MWU_NMIENCLR_REGION0WA_Disabled (0UL) /*!< Read: Disabled */
3272 #define MWU_NMIENCLR_REGION0WA_Enabled (1UL) /*!< Read: Enabled */
3273 #define MWU_NMIENCLR_REGION0WA_Clear (1UL) /*!< Disable */
3274 
3275 /* Register: MWU_PERREGION_SUBSTATWA */
3276 /* Description: Description cluster[0]:  Source of event/interrupt in region 0, write access detected while corresponding subregion was enabled for watching */
3277 
3278 /* Bit 31 : Subregion 31 in region 0 (write '1' to clear) */
3279 #define MWU_PERREGION_SUBSTATWA_SR31_Pos (31UL) /*!< Position of SR31 field. */
3280 #define MWU_PERREGION_SUBSTATWA_SR31_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR31_Pos) /*!< Bit mask of SR31 field. */
3281 #define MWU_PERREGION_SUBSTATWA_SR31_NoAccess (0UL) /*!< No write access occurred in this subregion */
3282 #define MWU_PERREGION_SUBSTATWA_SR31_Access (1UL) /*!< Write access(es) occurred in this subregion */
3283 
3284 /* Bit 30 : Subregion 30 in region 0 (write '1' to clear) */
3285 #define MWU_PERREGION_SUBSTATWA_SR30_Pos (30UL) /*!< Position of SR30 field. */
3286 #define MWU_PERREGION_SUBSTATWA_SR30_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR30_Pos) /*!< Bit mask of SR30 field. */
3287 #define MWU_PERREGION_SUBSTATWA_SR30_NoAccess (0UL) /*!< No write access occurred in this subregion */
3288 #define MWU_PERREGION_SUBSTATWA_SR30_Access (1UL) /*!< Write access(es) occurred in this subregion */
3289 
3290 /* Bit 29 : Subregion 29 in region 0 (write '1' to clear) */
3291 #define MWU_PERREGION_SUBSTATWA_SR29_Pos (29UL) /*!< Position of SR29 field. */
3292 #define MWU_PERREGION_SUBSTATWA_SR29_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR29_Pos) /*!< Bit mask of SR29 field. */
3293 #define MWU_PERREGION_SUBSTATWA_SR29_NoAccess (0UL) /*!< No write access occurred in this subregion */
3294 #define MWU_PERREGION_SUBSTATWA_SR29_Access (1UL) /*!< Write access(es) occurred in this subregion */
3295 
3296 /* Bit 28 : Subregion 28 in region 0 (write '1' to clear) */
3297 #define MWU_PERREGION_SUBSTATWA_SR28_Pos (28UL) /*!< Position of SR28 field. */
3298 #define MWU_PERREGION_SUBSTATWA_SR28_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR28_Pos) /*!< Bit mask of SR28 field. */
3299 #define MWU_PERREGION_SUBSTATWA_SR28_NoAccess (0UL) /*!< No write access occurred in this subregion */
3300 #define MWU_PERREGION_SUBSTATWA_SR28_Access (1UL) /*!< Write access(es) occurred in this subregion */
3301 
3302 /* Bit 27 : Subregion 27 in region 0 (write '1' to clear) */
3303 #define MWU_PERREGION_SUBSTATWA_SR27_Pos (27UL) /*!< Position of SR27 field. */
3304 #define MWU_PERREGION_SUBSTATWA_SR27_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR27_Pos) /*!< Bit mask of SR27 field. */
3305 #define MWU_PERREGION_SUBSTATWA_SR27_NoAccess (0UL) /*!< No write access occurred in this subregion */
3306 #define MWU_PERREGION_SUBSTATWA_SR27_Access (1UL) /*!< Write access(es) occurred in this subregion */
3307 
3308 /* Bit 26 : Subregion 26 in region 0 (write '1' to clear) */
3309 #define MWU_PERREGION_SUBSTATWA_SR26_Pos (26UL) /*!< Position of SR26 field. */
3310 #define MWU_PERREGION_SUBSTATWA_SR26_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR26_Pos) /*!< Bit mask of SR26 field. */
3311 #define MWU_PERREGION_SUBSTATWA_SR26_NoAccess (0UL) /*!< No write access occurred in this subregion */
3312 #define MWU_PERREGION_SUBSTATWA_SR26_Access (1UL) /*!< Write access(es) occurred in this subregion */
3313 
3314 /* Bit 25 : Subregion 25 in region 0 (write '1' to clear) */
3315 #define MWU_PERREGION_SUBSTATWA_SR25_Pos (25UL) /*!< Position of SR25 field. */
3316 #define MWU_PERREGION_SUBSTATWA_SR25_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR25_Pos) /*!< Bit mask of SR25 field. */
3317 #define MWU_PERREGION_SUBSTATWA_SR25_NoAccess (0UL) /*!< No write access occurred in this subregion */
3318 #define MWU_PERREGION_SUBSTATWA_SR25_Access (1UL) /*!< Write access(es) occurred in this subregion */
3319 
3320 /* Bit 24 : Subregion 24 in region 0 (write '1' to clear) */
3321 #define MWU_PERREGION_SUBSTATWA_SR24_Pos (24UL) /*!< Position of SR24 field. */
3322 #define MWU_PERREGION_SUBSTATWA_SR24_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR24_Pos) /*!< Bit mask of SR24 field. */
3323 #define MWU_PERREGION_SUBSTATWA_SR24_NoAccess (0UL) /*!< No write access occurred in this subregion */
3324 #define MWU_PERREGION_SUBSTATWA_SR24_Access (1UL) /*!< Write access(es) occurred in this subregion */
3325 
3326 /* Bit 23 : Subregion 23 in region 0 (write '1' to clear) */
3327 #define MWU_PERREGION_SUBSTATWA_SR23_Pos (23UL) /*!< Position of SR23 field. */
3328 #define MWU_PERREGION_SUBSTATWA_SR23_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR23_Pos) /*!< Bit mask of SR23 field. */
3329 #define MWU_PERREGION_SUBSTATWA_SR23_NoAccess (0UL) /*!< No write access occurred in this subregion */
3330 #define MWU_PERREGION_SUBSTATWA_SR23_Access (1UL) /*!< Write access(es) occurred in this subregion */
3331 
3332 /* Bit 22 : Subregion 22 in region 0 (write '1' to clear) */
3333 #define MWU_PERREGION_SUBSTATWA_SR22_Pos (22UL) /*!< Position of SR22 field. */
3334 #define MWU_PERREGION_SUBSTATWA_SR22_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR22_Pos) /*!< Bit mask of SR22 field. */
3335 #define MWU_PERREGION_SUBSTATWA_SR22_NoAccess (0UL) /*!< No write access occurred in this subregion */
3336 #define MWU_PERREGION_SUBSTATWA_SR22_Access (1UL) /*!< Write access(es) occurred in this subregion */
3337 
3338 /* Bit 21 : Subregion 21 in region 0 (write '1' to clear) */
3339 #define MWU_PERREGION_SUBSTATWA_SR21_Pos (21UL) /*!< Position of SR21 field. */
3340 #define MWU_PERREGION_SUBSTATWA_SR21_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR21_Pos) /*!< Bit mask of SR21 field. */
3341 #define MWU_PERREGION_SUBSTATWA_SR21_NoAccess (0UL) /*!< No write access occurred in this subregion */
3342 #define MWU_PERREGION_SUBSTATWA_SR21_Access (1UL) /*!< Write access(es) occurred in this subregion */
3343 
3344 /* Bit 20 : Subregion 20 in region 0 (write '1' to clear) */
3345 #define MWU_PERREGION_SUBSTATWA_SR20_Pos (20UL) /*!< Position of SR20 field. */
3346 #define MWU_PERREGION_SUBSTATWA_SR20_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR20_Pos) /*!< Bit mask of SR20 field. */
3347 #define MWU_PERREGION_SUBSTATWA_SR20_NoAccess (0UL) /*!< No write access occurred in this subregion */
3348 #define MWU_PERREGION_SUBSTATWA_SR20_Access (1UL) /*!< Write access(es) occurred in this subregion */
3349 
3350 /* Bit 19 : Subregion 19 in region 0 (write '1' to clear) */
3351 #define MWU_PERREGION_SUBSTATWA_SR19_Pos (19UL) /*!< Position of SR19 field. */
3352 #define MWU_PERREGION_SUBSTATWA_SR19_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR19_Pos) /*!< Bit mask of SR19 field. */
3353 #define MWU_PERREGION_SUBSTATWA_SR19_NoAccess (0UL) /*!< No write access occurred in this subregion */
3354 #define MWU_PERREGION_SUBSTATWA_SR19_Access (1UL) /*!< Write access(es) occurred in this subregion */
3355 
3356 /* Bit 18 : Subregion 18 in region 0 (write '1' to clear) */
3357 #define MWU_PERREGION_SUBSTATWA_SR18_Pos (18UL) /*!< Position of SR18 field. */
3358 #define MWU_PERREGION_SUBSTATWA_SR18_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR18_Pos) /*!< Bit mask of SR18 field. */
3359 #define MWU_PERREGION_SUBSTATWA_SR18_NoAccess (0UL) /*!< No write access occurred in this subregion */
3360 #define MWU_PERREGION_SUBSTATWA_SR18_Access (1UL) /*!< Write access(es) occurred in this subregion */
3361 
3362 /* Bit 17 : Subregion 17 in region 0 (write '1' to clear) */
3363 #define MWU_PERREGION_SUBSTATWA_SR17_Pos (17UL) /*!< Position of SR17 field. */
3364 #define MWU_PERREGION_SUBSTATWA_SR17_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR17_Pos) /*!< Bit mask of SR17 field. */
3365 #define MWU_PERREGION_SUBSTATWA_SR17_NoAccess (0UL) /*!< No write access occurred in this subregion */
3366 #define MWU_PERREGION_SUBSTATWA_SR17_Access (1UL) /*!< Write access(es) occurred in this subregion */
3367 
3368 /* Bit 16 : Subregion 16 in region 0 (write '1' to clear) */
3369 #define MWU_PERREGION_SUBSTATWA_SR16_Pos (16UL) /*!< Position of SR16 field. */
3370 #define MWU_PERREGION_SUBSTATWA_SR16_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR16_Pos) /*!< Bit mask of SR16 field. */
3371 #define MWU_PERREGION_SUBSTATWA_SR16_NoAccess (0UL) /*!< No write access occurred in this subregion */
3372 #define MWU_PERREGION_SUBSTATWA_SR16_Access (1UL) /*!< Write access(es) occurred in this subregion */
3373 
3374 /* Bit 15 : Subregion 15 in region 0 (write '1' to clear) */
3375 #define MWU_PERREGION_SUBSTATWA_SR15_Pos (15UL) /*!< Position of SR15 field. */
3376 #define MWU_PERREGION_SUBSTATWA_SR15_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR15_Pos) /*!< Bit mask of SR15 field. */
3377 #define MWU_PERREGION_SUBSTATWA_SR15_NoAccess (0UL) /*!< No write access occurred in this subregion */
3378 #define MWU_PERREGION_SUBSTATWA_SR15_Access (1UL) /*!< Write access(es) occurred in this subregion */
3379 
3380 /* Bit 14 : Subregion 14 in region 0 (write '1' to clear) */
3381 #define MWU_PERREGION_SUBSTATWA_SR14_Pos (14UL) /*!< Position of SR14 field. */
3382 #define MWU_PERREGION_SUBSTATWA_SR14_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR14_Pos) /*!< Bit mask of SR14 field. */
3383 #define MWU_PERREGION_SUBSTATWA_SR14_NoAccess (0UL) /*!< No write access occurred in this subregion */
3384 #define MWU_PERREGION_SUBSTATWA_SR14_Access (1UL) /*!< Write access(es) occurred in this subregion */
3385 
3386 /* Bit 13 : Subregion 13 in region 0 (write '1' to clear) */
3387 #define MWU_PERREGION_SUBSTATWA_SR13_Pos (13UL) /*!< Position of SR13 field. */
3388 #define MWU_PERREGION_SUBSTATWA_SR13_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR13_Pos) /*!< Bit mask of SR13 field. */
3389 #define MWU_PERREGION_SUBSTATWA_SR13_NoAccess (0UL) /*!< No write access occurred in this subregion */
3390 #define MWU_PERREGION_SUBSTATWA_SR13_Access (1UL) /*!< Write access(es) occurred in this subregion */
3391 
3392 /* Bit 12 : Subregion 12 in region 0 (write '1' to clear) */
3393 #define MWU_PERREGION_SUBSTATWA_SR12_Pos (12UL) /*!< Position of SR12 field. */
3394 #define MWU_PERREGION_SUBSTATWA_SR12_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR12_Pos) /*!< Bit mask of SR12 field. */
3395 #define MWU_PERREGION_SUBSTATWA_SR12_NoAccess (0UL) /*!< No write access occurred in this subregion */
3396 #define MWU_PERREGION_SUBSTATWA_SR12_Access (1UL) /*!< Write access(es) occurred in this subregion */
3397 
3398 /* Bit 11 : Subregion 11 in region 0 (write '1' to clear) */
3399 #define MWU_PERREGION_SUBSTATWA_SR11_Pos (11UL) /*!< Position of SR11 field. */
3400 #define MWU_PERREGION_SUBSTATWA_SR11_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR11_Pos) /*!< Bit mask of SR11 field. */
3401 #define MWU_PERREGION_SUBSTATWA_SR11_NoAccess (0UL) /*!< No write access occurred in this subregion */
3402 #define MWU_PERREGION_SUBSTATWA_SR11_Access (1UL) /*!< Write access(es) occurred in this subregion */
3403 
3404 /* Bit 10 : Subregion 10 in region 0 (write '1' to clear) */
3405 #define MWU_PERREGION_SUBSTATWA_SR10_Pos (10UL) /*!< Position of SR10 field. */
3406 #define MWU_PERREGION_SUBSTATWA_SR10_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR10_Pos) /*!< Bit mask of SR10 field. */
3407 #define MWU_PERREGION_SUBSTATWA_SR10_NoAccess (0UL) /*!< No write access occurred in this subregion */
3408 #define MWU_PERREGION_SUBSTATWA_SR10_Access (1UL) /*!< Write access(es) occurred in this subregion */
3409 
3410 /* Bit 9 : Subregion 9 in region 0 (write '1' to clear) */
3411 #define MWU_PERREGION_SUBSTATWA_SR9_Pos (9UL) /*!< Position of SR9 field. */
3412 #define MWU_PERREGION_SUBSTATWA_SR9_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR9_Pos) /*!< Bit mask of SR9 field. */
3413 #define MWU_PERREGION_SUBSTATWA_SR9_NoAccess (0UL) /*!< No write access occurred in this subregion */
3414 #define MWU_PERREGION_SUBSTATWA_SR9_Access (1UL) /*!< Write access(es) occurred in this subregion */
3415 
3416 /* Bit 8 : Subregion 8 in region 0 (write '1' to clear) */
3417 #define MWU_PERREGION_SUBSTATWA_SR8_Pos (8UL) /*!< Position of SR8 field. */
3418 #define MWU_PERREGION_SUBSTATWA_SR8_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR8_Pos) /*!< Bit mask of SR8 field. */
3419 #define MWU_PERREGION_SUBSTATWA_SR8_NoAccess (0UL) /*!< No write access occurred in this subregion */
3420 #define MWU_PERREGION_SUBSTATWA_SR8_Access (1UL) /*!< Write access(es) occurred in this subregion */
3421 
3422 /* Bit 7 : Subregion 7 in region 0 (write '1' to clear) */
3423 #define MWU_PERREGION_SUBSTATWA_SR7_Pos (7UL) /*!< Position of SR7 field. */
3424 #define MWU_PERREGION_SUBSTATWA_SR7_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR7_Pos) /*!< Bit mask of SR7 field. */
3425 #define MWU_PERREGION_SUBSTATWA_SR7_NoAccess (0UL) /*!< No write access occurred in this subregion */
3426 #define MWU_PERREGION_SUBSTATWA_SR7_Access (1UL) /*!< Write access(es) occurred in this subregion */
3427 
3428 /* Bit 6 : Subregion 6 in region 0 (write '1' to clear) */
3429 #define MWU_PERREGION_SUBSTATWA_SR6_Pos (6UL) /*!< Position of SR6 field. */
3430 #define MWU_PERREGION_SUBSTATWA_SR6_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR6_Pos) /*!< Bit mask of SR6 field. */
3431 #define MWU_PERREGION_SUBSTATWA_SR6_NoAccess (0UL) /*!< No write access occurred in this subregion */
3432 #define MWU_PERREGION_SUBSTATWA_SR6_Access (1UL) /*!< Write access(es) occurred in this subregion */
3433 
3434 /* Bit 5 : Subregion 5 in region 0 (write '1' to clear) */
3435 #define MWU_PERREGION_SUBSTATWA_SR5_Pos (5UL) /*!< Position of SR5 field. */
3436 #define MWU_PERREGION_SUBSTATWA_SR5_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR5_Pos) /*!< Bit mask of SR5 field. */
3437 #define MWU_PERREGION_SUBSTATWA_SR5_NoAccess (0UL) /*!< No write access occurred in this subregion */
3438 #define MWU_PERREGION_SUBSTATWA_SR5_Access (1UL) /*!< Write access(es) occurred in this subregion */
3439 
3440 /* Bit 4 : Subregion 4 in region 0 (write '1' to clear) */
3441 #define MWU_PERREGION_SUBSTATWA_SR4_Pos (4UL) /*!< Position of SR4 field. */
3442 #define MWU_PERREGION_SUBSTATWA_SR4_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR4_Pos) /*!< Bit mask of SR4 field. */
3443 #define MWU_PERREGION_SUBSTATWA_SR4_NoAccess (0UL) /*!< No write access occurred in this subregion */
3444 #define MWU_PERREGION_SUBSTATWA_SR4_Access (1UL) /*!< Write access(es) occurred in this subregion */
3445 
3446 /* Bit 3 : Subregion 3 in region 0 (write '1' to clear) */
3447 #define MWU_PERREGION_SUBSTATWA_SR3_Pos (3UL) /*!< Position of SR3 field. */
3448 #define MWU_PERREGION_SUBSTATWA_SR3_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR3_Pos) /*!< Bit mask of SR3 field. */
3449 #define MWU_PERREGION_SUBSTATWA_SR3_NoAccess (0UL) /*!< No write access occurred in this subregion */
3450 #define MWU_PERREGION_SUBSTATWA_SR3_Access (1UL) /*!< Write access(es) occurred in this subregion */
3451 
3452 /* Bit 2 : Subregion 2 in region 0 (write '1' to clear) */
3453 #define MWU_PERREGION_SUBSTATWA_SR2_Pos (2UL) /*!< Position of SR2 field. */
3454 #define MWU_PERREGION_SUBSTATWA_SR2_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR2_Pos) /*!< Bit mask of SR2 field. */
3455 #define MWU_PERREGION_SUBSTATWA_SR2_NoAccess (0UL) /*!< No write access occurred in this subregion */
3456 #define MWU_PERREGION_SUBSTATWA_SR2_Access (1UL) /*!< Write access(es) occurred in this subregion */
3457 
3458 /* Bit 1 : Subregion 1 in region 0 (write '1' to clear) */
3459 #define MWU_PERREGION_SUBSTATWA_SR1_Pos (1UL) /*!< Position of SR1 field. */
3460 #define MWU_PERREGION_SUBSTATWA_SR1_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR1_Pos) /*!< Bit mask of SR1 field. */
3461 #define MWU_PERREGION_SUBSTATWA_SR1_NoAccess (0UL) /*!< No write access occurred in this subregion */
3462 #define MWU_PERREGION_SUBSTATWA_SR1_Access (1UL) /*!< Write access(es) occurred in this subregion */
3463 
3464 /* Bit 0 : Subregion 0 in region 0 (write '1' to clear) */
3465 #define MWU_PERREGION_SUBSTATWA_SR0_Pos (0UL) /*!< Position of SR0 field. */
3466 #define MWU_PERREGION_SUBSTATWA_SR0_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR0_Pos) /*!< Bit mask of SR0 field. */
3467 #define MWU_PERREGION_SUBSTATWA_SR0_NoAccess (0UL) /*!< No write access occurred in this subregion */
3468 #define MWU_PERREGION_SUBSTATWA_SR0_Access (1UL) /*!< Write access(es) occurred in this subregion */
3469 
3470 /* Register: MWU_PERREGION_SUBSTATRA */
3471 /* Description: Description cluster[0]:  Source of event/interrupt in region 0, read access detected while corresponding subregion was enabled for watching */
3472 
3473 /* Bit 31 : Subregion 31 in region 0 (write '1' to clear) */
3474 #define MWU_PERREGION_SUBSTATRA_SR31_Pos (31UL) /*!< Position of SR31 field. */
3475 #define MWU_PERREGION_SUBSTATRA_SR31_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR31_Pos) /*!< Bit mask of SR31 field. */
3476 #define MWU_PERREGION_SUBSTATRA_SR31_NoAccess (0UL) /*!< No read access occurred in this subregion */
3477 #define MWU_PERREGION_SUBSTATRA_SR31_Access (1UL) /*!< Read access(es) occurred in this subregion */
3478 
3479 /* Bit 30 : Subregion 30 in region 0 (write '1' to clear) */
3480 #define MWU_PERREGION_SUBSTATRA_SR30_Pos (30UL) /*!< Position of SR30 field. */
3481 #define MWU_PERREGION_SUBSTATRA_SR30_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR30_Pos) /*!< Bit mask of SR30 field. */
3482 #define MWU_PERREGION_SUBSTATRA_SR30_NoAccess (0UL) /*!< No read access occurred in this subregion */
3483 #define MWU_PERREGION_SUBSTATRA_SR30_Access (1UL) /*!< Read access(es) occurred in this subregion */
3484 
3485 /* Bit 29 : Subregion 29 in region 0 (write '1' to clear) */
3486 #define MWU_PERREGION_SUBSTATRA_SR29_Pos (29UL) /*!< Position of SR29 field. */
3487 #define MWU_PERREGION_SUBSTATRA_SR29_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR29_Pos) /*!< Bit mask of SR29 field. */
3488 #define MWU_PERREGION_SUBSTATRA_SR29_NoAccess (0UL) /*!< No read access occurred in this subregion */
3489 #define MWU_PERREGION_SUBSTATRA_SR29_Access (1UL) /*!< Read access(es) occurred in this subregion */
3490 
3491 /* Bit 28 : Subregion 28 in region 0 (write '1' to clear) */
3492 #define MWU_PERREGION_SUBSTATRA_SR28_Pos (28UL) /*!< Position of SR28 field. */
3493 #define MWU_PERREGION_SUBSTATRA_SR28_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR28_Pos) /*!< Bit mask of SR28 field. */
3494 #define MWU_PERREGION_SUBSTATRA_SR28_NoAccess (0UL) /*!< No read access occurred in this subregion */
3495 #define MWU_PERREGION_SUBSTATRA_SR28_Access (1UL) /*!< Read access(es) occurred in this subregion */
3496 
3497 /* Bit 27 : Subregion 27 in region 0 (write '1' to clear) */
3498 #define MWU_PERREGION_SUBSTATRA_SR27_Pos (27UL) /*!< Position of SR27 field. */
3499 #define MWU_PERREGION_SUBSTATRA_SR27_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR27_Pos) /*!< Bit mask of SR27 field. */
3500 #define MWU_PERREGION_SUBSTATRA_SR27_NoAccess (0UL) /*!< No read access occurred in this subregion */
3501 #define MWU_PERREGION_SUBSTATRA_SR27_Access (1UL) /*!< Read access(es) occurred in this subregion */
3502 
3503 /* Bit 26 : Subregion 26 in region 0 (write '1' to clear) */
3504 #define MWU_PERREGION_SUBSTATRA_SR26_Pos (26UL) /*!< Position of SR26 field. */
3505 #define MWU_PERREGION_SUBSTATRA_SR26_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR26_Pos) /*!< Bit mask of SR26 field. */
3506 #define MWU_PERREGION_SUBSTATRA_SR26_NoAccess (0UL) /*!< No read access occurred in this subregion */
3507 #define MWU_PERREGION_SUBSTATRA_SR26_Access (1UL) /*!< Read access(es) occurred in this subregion */
3508 
3509 /* Bit 25 : Subregion 25 in region 0 (write '1' to clear) */
3510 #define MWU_PERREGION_SUBSTATRA_SR25_Pos (25UL) /*!< Position of SR25 field. */
3511 #define MWU_PERREGION_SUBSTATRA_SR25_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR25_Pos) /*!< Bit mask of SR25 field. */
3512 #define MWU_PERREGION_SUBSTATRA_SR25_NoAccess (0UL) /*!< No read access occurred in this subregion */
3513 #define MWU_PERREGION_SUBSTATRA_SR25_Access (1UL) /*!< Read access(es) occurred in this subregion */
3514 
3515 /* Bit 24 : Subregion 24 in region 0 (write '1' to clear) */
3516 #define MWU_PERREGION_SUBSTATRA_SR24_Pos (24UL) /*!< Position of SR24 field. */
3517 #define MWU_PERREGION_SUBSTATRA_SR24_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR24_Pos) /*!< Bit mask of SR24 field. */
3518 #define MWU_PERREGION_SUBSTATRA_SR24_NoAccess (0UL) /*!< No read access occurred in this subregion */
3519 #define MWU_PERREGION_SUBSTATRA_SR24_Access (1UL) /*!< Read access(es) occurred in this subregion */
3520 
3521 /* Bit 23 : Subregion 23 in region 0 (write '1' to clear) */
3522 #define MWU_PERREGION_SUBSTATRA_SR23_Pos (23UL) /*!< Position of SR23 field. */
3523 #define MWU_PERREGION_SUBSTATRA_SR23_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR23_Pos) /*!< Bit mask of SR23 field. */
3524 #define MWU_PERREGION_SUBSTATRA_SR23_NoAccess (0UL) /*!< No read access occurred in this subregion */
3525 #define MWU_PERREGION_SUBSTATRA_SR23_Access (1UL) /*!< Read access(es) occurred in this subregion */
3526 
3527 /* Bit 22 : Subregion 22 in region 0 (write '1' to clear) */
3528 #define MWU_PERREGION_SUBSTATRA_SR22_Pos (22UL) /*!< Position of SR22 field. */
3529 #define MWU_PERREGION_SUBSTATRA_SR22_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR22_Pos) /*!< Bit mask of SR22 field. */
3530 #define MWU_PERREGION_SUBSTATRA_SR22_NoAccess (0UL) /*!< No read access occurred in this subregion */
3531 #define MWU_PERREGION_SUBSTATRA_SR22_Access (1UL) /*!< Read access(es) occurred in this subregion */
3532 
3533 /* Bit 21 : Subregion 21 in region 0 (write '1' to clear) */
3534 #define MWU_PERREGION_SUBSTATRA_SR21_Pos (21UL) /*!< Position of SR21 field. */
3535 #define MWU_PERREGION_SUBSTATRA_SR21_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR21_Pos) /*!< Bit mask of SR21 field. */
3536 #define MWU_PERREGION_SUBSTATRA_SR21_NoAccess (0UL) /*!< No read access occurred in this subregion */
3537 #define MWU_PERREGION_SUBSTATRA_SR21_Access (1UL) /*!< Read access(es) occurred in this subregion */
3538 
3539 /* Bit 20 : Subregion 20 in region 0 (write '1' to clear) */
3540 #define MWU_PERREGION_SUBSTATRA_SR20_Pos (20UL) /*!< Position of SR20 field. */
3541 #define MWU_PERREGION_SUBSTATRA_SR20_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR20_Pos) /*!< Bit mask of SR20 field. */
3542 #define MWU_PERREGION_SUBSTATRA_SR20_NoAccess (0UL) /*!< No read access occurred in this subregion */
3543 #define MWU_PERREGION_SUBSTATRA_SR20_Access (1UL) /*!< Read access(es) occurred in this subregion */
3544 
3545 /* Bit 19 : Subregion 19 in region 0 (write '1' to clear) */
3546 #define MWU_PERREGION_SUBSTATRA_SR19_Pos (19UL) /*!< Position of SR19 field. */
3547 #define MWU_PERREGION_SUBSTATRA_SR19_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR19_Pos) /*!< Bit mask of SR19 field. */
3548 #define MWU_PERREGION_SUBSTATRA_SR19_NoAccess (0UL) /*!< No read access occurred in this subregion */
3549 #define MWU_PERREGION_SUBSTATRA_SR19_Access (1UL) /*!< Read access(es) occurred in this subregion */
3550 
3551 /* Bit 18 : Subregion 18 in region 0 (write '1' to clear) */
3552 #define MWU_PERREGION_SUBSTATRA_SR18_Pos (18UL) /*!< Position of SR18 field. */
3553 #define MWU_PERREGION_SUBSTATRA_SR18_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR18_Pos) /*!< Bit mask of SR18 field. */
3554 #define MWU_PERREGION_SUBSTATRA_SR18_NoAccess (0UL) /*!< No read access occurred in this subregion */
3555 #define MWU_PERREGION_SUBSTATRA_SR18_Access (1UL) /*!< Read access(es) occurred in this subregion */
3556 
3557 /* Bit 17 : Subregion 17 in region 0 (write '1' to clear) */
3558 #define MWU_PERREGION_SUBSTATRA_SR17_Pos (17UL) /*!< Position of SR17 field. */
3559 #define MWU_PERREGION_SUBSTATRA_SR17_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR17_Pos) /*!< Bit mask of SR17 field. */
3560 #define MWU_PERREGION_SUBSTATRA_SR17_NoAccess (0UL) /*!< No read access occurred in this subregion */
3561 #define MWU_PERREGION_SUBSTATRA_SR17_Access (1UL) /*!< Read access(es) occurred in this subregion */
3562 
3563 /* Bit 16 : Subregion 16 in region 0 (write '1' to clear) */
3564 #define MWU_PERREGION_SUBSTATRA_SR16_Pos (16UL) /*!< Position of SR16 field. */
3565 #define MWU_PERREGION_SUBSTATRA_SR16_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR16_Pos) /*!< Bit mask of SR16 field. */
3566 #define MWU_PERREGION_SUBSTATRA_SR16_NoAccess (0UL) /*!< No read access occurred in this subregion */
3567 #define MWU_PERREGION_SUBSTATRA_SR16_Access (1UL) /*!< Read access(es) occurred in this subregion */
3568 
3569 /* Bit 15 : Subregion 15 in region 0 (write '1' to clear) */
3570 #define MWU_PERREGION_SUBSTATRA_SR15_Pos (15UL) /*!< Position of SR15 field. */
3571 #define MWU_PERREGION_SUBSTATRA_SR15_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR15_Pos) /*!< Bit mask of SR15 field. */
3572 #define MWU_PERREGION_SUBSTATRA_SR15_NoAccess (0UL) /*!< No read access occurred in this subregion */
3573 #define MWU_PERREGION_SUBSTATRA_SR15_Access (1UL) /*!< Read access(es) occurred in this subregion */
3574 
3575 /* Bit 14 : Subregion 14 in region 0 (write '1' to clear) */
3576 #define MWU_PERREGION_SUBSTATRA_SR14_Pos (14UL) /*!< Position of SR14 field. */
3577 #define MWU_PERREGION_SUBSTATRA_SR14_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR14_Pos) /*!< Bit mask of SR14 field. */
3578 #define MWU_PERREGION_SUBSTATRA_SR14_NoAccess (0UL) /*!< No read access occurred in this subregion */
3579 #define MWU_PERREGION_SUBSTATRA_SR14_Access (1UL) /*!< Read access(es) occurred in this subregion */
3580 
3581 /* Bit 13 : Subregion 13 in region 0 (write '1' to clear) */
3582 #define MWU_PERREGION_SUBSTATRA_SR13_Pos (13UL) /*!< Position of SR13 field. */
3583 #define MWU_PERREGION_SUBSTATRA_SR13_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR13_Pos) /*!< Bit mask of SR13 field. */
3584 #define MWU_PERREGION_SUBSTATRA_SR13_NoAccess (0UL) /*!< No read access occurred in this subregion */
3585 #define MWU_PERREGION_SUBSTATRA_SR13_Access (1UL) /*!< Read access(es) occurred in this subregion */
3586 
3587 /* Bit 12 : Subregion 12 in region 0 (write '1' to clear) */
3588 #define MWU_PERREGION_SUBSTATRA_SR12_Pos (12UL) /*!< Position of SR12 field. */
3589 #define MWU_PERREGION_SUBSTATRA_SR12_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR12_Pos) /*!< Bit mask of SR12 field. */
3590 #define MWU_PERREGION_SUBSTATRA_SR12_NoAccess (0UL) /*!< No read access occurred in this subregion */
3591 #define MWU_PERREGION_SUBSTATRA_SR12_Access (1UL) /*!< Read access(es) occurred in this subregion */
3592 
3593 /* Bit 11 : Subregion 11 in region 0 (write '1' to clear) */
3594 #define MWU_PERREGION_SUBSTATRA_SR11_Pos (11UL) /*!< Position of SR11 field. */
3595 #define MWU_PERREGION_SUBSTATRA_SR11_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR11_Pos) /*!< Bit mask of SR11 field. */
3596 #define MWU_PERREGION_SUBSTATRA_SR11_NoAccess (0UL) /*!< No read access occurred in this subregion */
3597 #define MWU_PERREGION_SUBSTATRA_SR11_Access (1UL) /*!< Read access(es) occurred in this subregion */
3598 
3599 /* Bit 10 : Subregion 10 in region 0 (write '1' to clear) */
3600 #define MWU_PERREGION_SUBSTATRA_SR10_Pos (10UL) /*!< Position of SR10 field. */
3601 #define MWU_PERREGION_SUBSTATRA_SR10_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR10_Pos) /*!< Bit mask of SR10 field. */
3602 #define MWU_PERREGION_SUBSTATRA_SR10_NoAccess (0UL) /*!< No read access occurred in this subregion */
3603 #define MWU_PERREGION_SUBSTATRA_SR10_Access (1UL) /*!< Read access(es) occurred in this subregion */
3604 
3605 /* Bit 9 : Subregion 9 in region 0 (write '1' to clear) */
3606 #define MWU_PERREGION_SUBSTATRA_SR9_Pos (9UL) /*!< Position of SR9 field. */
3607 #define MWU_PERREGION_SUBSTATRA_SR9_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR9_Pos) /*!< Bit mask of SR9 field. */
3608 #define MWU_PERREGION_SUBSTATRA_SR9_NoAccess (0UL) /*!< No read access occurred in this subregion */
3609 #define MWU_PERREGION_SUBSTATRA_SR9_Access (1UL) /*!< Read access(es) occurred in this subregion */
3610 
3611 /* Bit 8 : Subregion 8 in region 0 (write '1' to clear) */
3612 #define MWU_PERREGION_SUBSTATRA_SR8_Pos (8UL) /*!< Position of SR8 field. */
3613 #define MWU_PERREGION_SUBSTATRA_SR8_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR8_Pos) /*!< Bit mask of SR8 field. */
3614 #define MWU_PERREGION_SUBSTATRA_SR8_NoAccess (0UL) /*!< No read access occurred in this subregion */
3615 #define MWU_PERREGION_SUBSTATRA_SR8_Access (1UL) /*!< Read access(es) occurred in this subregion */
3616 
3617 /* Bit 7 : Subregion 7 in region 0 (write '1' to clear) */
3618 #define MWU_PERREGION_SUBSTATRA_SR7_Pos (7UL) /*!< Position of SR7 field. */
3619 #define MWU_PERREGION_SUBSTATRA_SR7_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR7_Pos) /*!< Bit mask of SR7 field. */
3620 #define MWU_PERREGION_SUBSTATRA_SR7_NoAccess (0UL) /*!< No read access occurred in this subregion */
3621 #define MWU_PERREGION_SUBSTATRA_SR7_Access (1UL) /*!< Read access(es) occurred in this subregion */
3622 
3623 /* Bit 6 : Subregion 6 in region 0 (write '1' to clear) */
3624 #define MWU_PERREGION_SUBSTATRA_SR6_Pos (6UL) /*!< Position of SR6 field. */
3625 #define MWU_PERREGION_SUBSTATRA_SR6_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR6_Pos) /*!< Bit mask of SR6 field. */
3626 #define MWU_PERREGION_SUBSTATRA_SR6_NoAccess (0UL) /*!< No read access occurred in this subregion */
3627 #define MWU_PERREGION_SUBSTATRA_SR6_Access (1UL) /*!< Read access(es) occurred in this subregion */
3628 
3629 /* Bit 5 : Subregion 5 in region 0 (write '1' to clear) */
3630 #define MWU_PERREGION_SUBSTATRA_SR5_Pos (5UL) /*!< Position of SR5 field. */
3631 #define MWU_PERREGION_SUBSTATRA_SR5_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR5_Pos) /*!< Bit mask of SR5 field. */
3632 #define MWU_PERREGION_SUBSTATRA_SR5_NoAccess (0UL) /*!< No read access occurred in this subregion */
3633 #define MWU_PERREGION_SUBSTATRA_SR5_Access (1UL) /*!< Read access(es) occurred in this subregion */
3634 
3635 /* Bit 4 : Subregion 4 in region 0 (write '1' to clear) */
3636 #define MWU_PERREGION_SUBSTATRA_SR4_Pos (4UL) /*!< Position of SR4 field. */
3637 #define MWU_PERREGION_SUBSTATRA_SR4_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR4_Pos) /*!< Bit mask of SR4 field. */
3638 #define MWU_PERREGION_SUBSTATRA_SR4_NoAccess (0UL) /*!< No read access occurred in this subregion */
3639 #define MWU_PERREGION_SUBSTATRA_SR4_Access (1UL) /*!< Read access(es) occurred in this subregion */
3640 
3641 /* Bit 3 : Subregion 3 in region 0 (write '1' to clear) */
3642 #define MWU_PERREGION_SUBSTATRA_SR3_Pos (3UL) /*!< Position of SR3 field. */
3643 #define MWU_PERREGION_SUBSTATRA_SR3_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR3_Pos) /*!< Bit mask of SR3 field. */
3644 #define MWU_PERREGION_SUBSTATRA_SR3_NoAccess (0UL) /*!< No read access occurred in this subregion */
3645 #define MWU_PERREGION_SUBSTATRA_SR3_Access (1UL) /*!< Read access(es) occurred in this subregion */
3646 
3647 /* Bit 2 : Subregion 2 in region 0 (write '1' to clear) */
3648 #define MWU_PERREGION_SUBSTATRA_SR2_Pos (2UL) /*!< Position of SR2 field. */
3649 #define MWU_PERREGION_SUBSTATRA_SR2_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR2_Pos) /*!< Bit mask of SR2 field. */
3650 #define MWU_PERREGION_SUBSTATRA_SR2_NoAccess (0UL) /*!< No read access occurred in this subregion */
3651 #define MWU_PERREGION_SUBSTATRA_SR2_Access (1UL) /*!< Read access(es) occurred in this subregion */
3652 
3653 /* Bit 1 : Subregion 1 in region 0 (write '1' to clear) */
3654 #define MWU_PERREGION_SUBSTATRA_SR1_Pos (1UL) /*!< Position of SR1 field. */
3655 #define MWU_PERREGION_SUBSTATRA_SR1_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR1_Pos) /*!< Bit mask of SR1 field. */
3656 #define MWU_PERREGION_SUBSTATRA_SR1_NoAccess (0UL) /*!< No read access occurred in this subregion */
3657 #define MWU_PERREGION_SUBSTATRA_SR1_Access (1UL) /*!< Read access(es) occurred in this subregion */
3658 
3659 /* Bit 0 : Subregion 0 in region 0 (write '1' to clear) */
3660 #define MWU_PERREGION_SUBSTATRA_SR0_Pos (0UL) /*!< Position of SR0 field. */
3661 #define MWU_PERREGION_SUBSTATRA_SR0_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR0_Pos) /*!< Bit mask of SR0 field. */
3662 #define MWU_PERREGION_SUBSTATRA_SR0_NoAccess (0UL) /*!< No read access occurred in this subregion */
3663 #define MWU_PERREGION_SUBSTATRA_SR0_Access (1UL) /*!< Read access(es) occurred in this subregion */
3664 
3665 /* Register: MWU_REGIONEN */
3666 /* Description: Enable/disable regions watch */
3667 
3668 /* Bit 27 : Enable/disable read access watch in PREGION[1] */
3669 #define MWU_REGIONEN_PRGN1RA_Pos (27UL) /*!< Position of PRGN1RA field. */
3670 #define MWU_REGIONEN_PRGN1RA_Msk (0x1UL << MWU_REGIONEN_PRGN1RA_Pos) /*!< Bit mask of PRGN1RA field. */
3671 #define MWU_REGIONEN_PRGN1RA_Disable (0UL) /*!< Disable read access watch in this PREGION */
3672 #define MWU_REGIONEN_PRGN1RA_Enable (1UL) /*!< Enable read access watch in this PREGION */
3673 
3674 /* Bit 26 : Enable/disable write access watch in PREGION[1] */
3675 #define MWU_REGIONEN_PRGN1WA_Pos (26UL) /*!< Position of PRGN1WA field. */
3676 #define MWU_REGIONEN_PRGN1WA_Msk (0x1UL << MWU_REGIONEN_PRGN1WA_Pos) /*!< Bit mask of PRGN1WA field. */
3677 #define MWU_REGIONEN_PRGN1WA_Disable (0UL) /*!< Disable write access watch in this PREGION */
3678 #define MWU_REGIONEN_PRGN1WA_Enable (1UL) /*!< Enable write access watch in this PREGION */
3679 
3680 /* Bit 25 : Enable/disable read access watch in PREGION[0] */
3681 #define MWU_REGIONEN_PRGN0RA_Pos (25UL) /*!< Position of PRGN0RA field. */
3682 #define MWU_REGIONEN_PRGN0RA_Msk (0x1UL << MWU_REGIONEN_PRGN0RA_Pos) /*!< Bit mask of PRGN0RA field. */
3683 #define MWU_REGIONEN_PRGN0RA_Disable (0UL) /*!< Disable read access watch in this PREGION */
3684 #define MWU_REGIONEN_PRGN0RA_Enable (1UL) /*!< Enable read access watch in this PREGION */
3685 
3686 /* Bit 24 : Enable/disable write access watch in PREGION[0] */
3687 #define MWU_REGIONEN_PRGN0WA_Pos (24UL) /*!< Position of PRGN0WA field. */
3688 #define MWU_REGIONEN_PRGN0WA_Msk (0x1UL << MWU_REGIONEN_PRGN0WA_Pos) /*!< Bit mask of PRGN0WA field. */
3689 #define MWU_REGIONEN_PRGN0WA_Disable (0UL) /*!< Disable write access watch in this PREGION */
3690 #define MWU_REGIONEN_PRGN0WA_Enable (1UL) /*!< Enable write access watch in this PREGION */
3691 
3692 /* Bit 7 : Enable/disable read access watch in region[3] */
3693 #define MWU_REGIONEN_RGN3RA_Pos (7UL) /*!< Position of RGN3RA field. */
3694 #define MWU_REGIONEN_RGN3RA_Msk (0x1UL << MWU_REGIONEN_RGN3RA_Pos) /*!< Bit mask of RGN3RA field. */
3695 #define MWU_REGIONEN_RGN3RA_Disable (0UL) /*!< Disable read access watch in this region */
3696 #define MWU_REGIONEN_RGN3RA_Enable (1UL) /*!< Enable read access watch in this region */
3697 
3698 /* Bit 6 : Enable/disable write access watch in region[3] */
3699 #define MWU_REGIONEN_RGN3WA_Pos (6UL) /*!< Position of RGN3WA field. */
3700 #define MWU_REGIONEN_RGN3WA_Msk (0x1UL << MWU_REGIONEN_RGN3WA_Pos) /*!< Bit mask of RGN3WA field. */
3701 #define MWU_REGIONEN_RGN3WA_Disable (0UL) /*!< Disable write access watch in this region */
3702 #define MWU_REGIONEN_RGN3WA_Enable (1UL) /*!< Enable write access watch in this region */
3703 
3704 /* Bit 5 : Enable/disable read access watch in region[2] */
3705 #define MWU_REGIONEN_RGN2RA_Pos (5UL) /*!< Position of RGN2RA field. */
3706 #define MWU_REGIONEN_RGN2RA_Msk (0x1UL << MWU_REGIONEN_RGN2RA_Pos) /*!< Bit mask of RGN2RA field. */
3707 #define MWU_REGIONEN_RGN2RA_Disable (0UL) /*!< Disable read access watch in this region */
3708 #define MWU_REGIONEN_RGN2RA_Enable (1UL) /*!< Enable read access watch in this region */
3709 
3710 /* Bit 4 : Enable/disable write access watch in region[2] */
3711 #define MWU_REGIONEN_RGN2WA_Pos (4UL) /*!< Position of RGN2WA field. */
3712 #define MWU_REGIONEN_RGN2WA_Msk (0x1UL << MWU_REGIONEN_RGN2WA_Pos) /*!< Bit mask of RGN2WA field. */
3713 #define MWU_REGIONEN_RGN2WA_Disable (0UL) /*!< Disable write access watch in this region */
3714 #define MWU_REGIONEN_RGN2WA_Enable (1UL) /*!< Enable write access watch in this region */
3715 
3716 /* Bit 3 : Enable/disable read access watch in region[1] */
3717 #define MWU_REGIONEN_RGN1RA_Pos (3UL) /*!< Position of RGN1RA field. */
3718 #define MWU_REGIONEN_RGN1RA_Msk (0x1UL << MWU_REGIONEN_RGN1RA_Pos) /*!< Bit mask of RGN1RA field. */
3719 #define MWU_REGIONEN_RGN1RA_Disable (0UL) /*!< Disable read access watch in this region */
3720 #define MWU_REGIONEN_RGN1RA_Enable (1UL) /*!< Enable read access watch in this region */
3721 
3722 /* Bit 2 : Enable/disable write access watch in region[1] */
3723 #define MWU_REGIONEN_RGN1WA_Pos (2UL) /*!< Position of RGN1WA field. */
3724 #define MWU_REGIONEN_RGN1WA_Msk (0x1UL << MWU_REGIONEN_RGN1WA_Pos) /*!< Bit mask of RGN1WA field. */
3725 #define MWU_REGIONEN_RGN1WA_Disable (0UL) /*!< Disable write access watch in this region */
3726 #define MWU_REGIONEN_RGN1WA_Enable (1UL) /*!< Enable write access watch in this region */
3727 
3728 /* Bit 1 : Enable/disable read access watch in region[0] */
3729 #define MWU_REGIONEN_RGN0RA_Pos (1UL) /*!< Position of RGN0RA field. */
3730 #define MWU_REGIONEN_RGN0RA_Msk (0x1UL << MWU_REGIONEN_RGN0RA_Pos) /*!< Bit mask of RGN0RA field. */
3731 #define MWU_REGIONEN_RGN0RA_Disable (0UL) /*!< Disable read access watch in this region */
3732 #define MWU_REGIONEN_RGN0RA_Enable (1UL) /*!< Enable read access watch in this region */
3733 
3734 /* Bit 0 : Enable/disable write access watch in region[0] */
3735 #define MWU_REGIONEN_RGN0WA_Pos (0UL) /*!< Position of RGN0WA field. */
3736 #define MWU_REGIONEN_RGN0WA_Msk (0x1UL << MWU_REGIONEN_RGN0WA_Pos) /*!< Bit mask of RGN0WA field. */
3737 #define MWU_REGIONEN_RGN0WA_Disable (0UL) /*!< Disable write access watch in this region */
3738 #define MWU_REGIONEN_RGN0WA_Enable (1UL) /*!< Enable write access watch in this region */
3739 
3740 /* Register: MWU_REGIONENSET */
3741 /* Description: Enable regions watch */
3742 
3743 /* Bit 27 : Enable read access watch in PREGION[1] */
3744 #define MWU_REGIONENSET_PRGN1RA_Pos (27UL) /*!< Position of PRGN1RA field. */
3745 #define MWU_REGIONENSET_PRGN1RA_Msk (0x1UL << MWU_REGIONENSET_PRGN1RA_Pos) /*!< Bit mask of PRGN1RA field. */
3746 #define MWU_REGIONENSET_PRGN1RA_Disabled (0UL) /*!< Read access watch in this PREGION is disabled */
3747 #define MWU_REGIONENSET_PRGN1RA_Enabled (1UL) /*!< Read access watch in this PREGION is enabled */
3748 #define MWU_REGIONENSET_PRGN1RA_Set (1UL) /*!< Enable read access watch in this PREGION */
3749 
3750 /* Bit 26 : Enable write access watch in PREGION[1] */
3751 #define MWU_REGIONENSET_PRGN1WA_Pos (26UL) /*!< Position of PRGN1WA field. */
3752 #define MWU_REGIONENSET_PRGN1WA_Msk (0x1UL << MWU_REGIONENSET_PRGN1WA_Pos) /*!< Bit mask of PRGN1WA field. */
3753 #define MWU_REGIONENSET_PRGN1WA_Disabled (0UL) /*!< Write access watch in this PREGION is disabled */
3754 #define MWU_REGIONENSET_PRGN1WA_Enabled (1UL) /*!< Write access watch in this PREGION is enabled */
3755 #define MWU_REGIONENSET_PRGN1WA_Set (1UL) /*!< Enable write access watch in this PREGION */
3756 
3757 /* Bit 25 : Enable read access watch in PREGION[0] */
3758 #define MWU_REGIONENSET_PRGN0RA_Pos (25UL) /*!< Position of PRGN0RA field. */
3759 #define MWU_REGIONENSET_PRGN0RA_Msk (0x1UL << MWU_REGIONENSET_PRGN0RA_Pos) /*!< Bit mask of PRGN0RA field. */
3760 #define MWU_REGIONENSET_PRGN0RA_Disabled (0UL) /*!< Read access watch in this PREGION is disabled */
3761 #define MWU_REGIONENSET_PRGN0RA_Enabled (1UL) /*!< Read access watch in this PREGION is enabled */
3762 #define MWU_REGIONENSET_PRGN0RA_Set (1UL) /*!< Enable read access watch in this PREGION */
3763 
3764 /* Bit 24 : Enable write access watch in PREGION[0] */
3765 #define MWU_REGIONENSET_PRGN0WA_Pos (24UL) /*!< Position of PRGN0WA field. */
3766 #define MWU_REGIONENSET_PRGN0WA_Msk (0x1UL << MWU_REGIONENSET_PRGN0WA_Pos) /*!< Bit mask of PRGN0WA field. */
3767 #define MWU_REGIONENSET_PRGN0WA_Disabled (0UL) /*!< Write access watch in this PREGION is disabled */
3768 #define MWU_REGIONENSET_PRGN0WA_Enabled (1UL) /*!< Write access watch in this PREGION is enabled */
3769 #define MWU_REGIONENSET_PRGN0WA_Set (1UL) /*!< Enable write access watch in this PREGION */
3770 
3771 /* Bit 7 : Enable read access watch in region[3] */
3772 #define MWU_REGIONENSET_RGN3RA_Pos (7UL) /*!< Position of RGN3RA field. */
3773 #define MWU_REGIONENSET_RGN3RA_Msk (0x1UL << MWU_REGIONENSET_RGN3RA_Pos) /*!< Bit mask of RGN3RA field. */
3774 #define MWU_REGIONENSET_RGN3RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
3775 #define MWU_REGIONENSET_RGN3RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
3776 #define MWU_REGIONENSET_RGN3RA_Set (1UL) /*!< Enable read access watch in this region */
3777 
3778 /* Bit 6 : Enable write access watch in region[3] */
3779 #define MWU_REGIONENSET_RGN3WA_Pos (6UL) /*!< Position of RGN3WA field. */
3780 #define MWU_REGIONENSET_RGN3WA_Msk (0x1UL << MWU_REGIONENSET_RGN3WA_Pos) /*!< Bit mask of RGN3WA field. */
3781 #define MWU_REGIONENSET_RGN3WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
3782 #define MWU_REGIONENSET_RGN3WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
3783 #define MWU_REGIONENSET_RGN3WA_Set (1UL) /*!< Enable write access watch in this region */
3784 
3785 /* Bit 5 : Enable read access watch in region[2] */
3786 #define MWU_REGIONENSET_RGN2RA_Pos (5UL) /*!< Position of RGN2RA field. */
3787 #define MWU_REGIONENSET_RGN2RA_Msk (0x1UL << MWU_REGIONENSET_RGN2RA_Pos) /*!< Bit mask of RGN2RA field. */
3788 #define MWU_REGIONENSET_RGN2RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
3789 #define MWU_REGIONENSET_RGN2RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
3790 #define MWU_REGIONENSET_RGN2RA_Set (1UL) /*!< Enable read access watch in this region */
3791 
3792 /* Bit 4 : Enable write access watch in region[2] */
3793 #define MWU_REGIONENSET_RGN2WA_Pos (4UL) /*!< Position of RGN2WA field. */
3794 #define MWU_REGIONENSET_RGN2WA_Msk (0x1UL << MWU_REGIONENSET_RGN2WA_Pos) /*!< Bit mask of RGN2WA field. */
3795 #define MWU_REGIONENSET_RGN2WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
3796 #define MWU_REGIONENSET_RGN2WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
3797 #define MWU_REGIONENSET_RGN2WA_Set (1UL) /*!< Enable write access watch in this region */
3798 
3799 /* Bit 3 : Enable read access watch in region[1] */
3800 #define MWU_REGIONENSET_RGN1RA_Pos (3UL) /*!< Position of RGN1RA field. */
3801 #define MWU_REGIONENSET_RGN1RA_Msk (0x1UL << MWU_REGIONENSET_RGN1RA_Pos) /*!< Bit mask of RGN1RA field. */
3802 #define MWU_REGIONENSET_RGN1RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
3803 #define MWU_REGIONENSET_RGN1RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
3804 #define MWU_REGIONENSET_RGN1RA_Set (1UL) /*!< Enable read access watch in this region */
3805 
3806 /* Bit 2 : Enable write access watch in region[1] */
3807 #define MWU_REGIONENSET_RGN1WA_Pos (2UL) /*!< Position of RGN1WA field. */
3808 #define MWU_REGIONENSET_RGN1WA_Msk (0x1UL << MWU_REGIONENSET_RGN1WA_Pos) /*!< Bit mask of RGN1WA field. */
3809 #define MWU_REGIONENSET_RGN1WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
3810 #define MWU_REGIONENSET_RGN1WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
3811 #define MWU_REGIONENSET_RGN1WA_Set (1UL) /*!< Enable write access watch in this region */
3812 
3813 /* Bit 1 : Enable read access watch in region[0] */
3814 #define MWU_REGIONENSET_RGN0RA_Pos (1UL) /*!< Position of RGN0RA field. */
3815 #define MWU_REGIONENSET_RGN0RA_Msk (0x1UL << MWU_REGIONENSET_RGN0RA_Pos) /*!< Bit mask of RGN0RA field. */
3816 #define MWU_REGIONENSET_RGN0RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
3817 #define MWU_REGIONENSET_RGN0RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
3818 #define MWU_REGIONENSET_RGN0RA_Set (1UL) /*!< Enable read access watch in this region */
3819 
3820 /* Bit 0 : Enable write access watch in region[0] */
3821 #define MWU_REGIONENSET_RGN0WA_Pos (0UL) /*!< Position of RGN0WA field. */
3822 #define MWU_REGIONENSET_RGN0WA_Msk (0x1UL << MWU_REGIONENSET_RGN0WA_Pos) /*!< Bit mask of RGN0WA field. */
3823 #define MWU_REGIONENSET_RGN0WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
3824 #define MWU_REGIONENSET_RGN0WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
3825 #define MWU_REGIONENSET_RGN0WA_Set (1UL) /*!< Enable write access watch in this region */
3826 
3827 /* Register: MWU_REGIONENCLR */
3828 /* Description: Disable regions watch */
3829 
3830 /* Bit 27 : Disable read access watch in PREGION[1] */
3831 #define MWU_REGIONENCLR_PRGN1RA_Pos (27UL) /*!< Position of PRGN1RA field. */
3832 #define MWU_REGIONENCLR_PRGN1RA_Msk (0x1UL << MWU_REGIONENCLR_PRGN1RA_Pos) /*!< Bit mask of PRGN1RA field. */
3833 #define MWU_REGIONENCLR_PRGN1RA_Disabled (0UL) /*!< Read access watch in this PREGION is disabled */
3834 #define MWU_REGIONENCLR_PRGN1RA_Enabled (1UL) /*!< Read access watch in this PREGION is enabled */
3835 #define MWU_REGIONENCLR_PRGN1RA_Clear (1UL) /*!< Disable read access watch in this PREGION */
3836 
3837 /* Bit 26 : Disable write access watch in PREGION[1] */
3838 #define MWU_REGIONENCLR_PRGN1WA_Pos (26UL) /*!< Position of PRGN1WA field. */
3839 #define MWU_REGIONENCLR_PRGN1WA_Msk (0x1UL << MWU_REGIONENCLR_PRGN1WA_Pos) /*!< Bit mask of PRGN1WA field. */
3840 #define MWU_REGIONENCLR_PRGN1WA_Disabled (0UL) /*!< Write access watch in this PREGION is disabled */
3841 #define MWU_REGIONENCLR_PRGN1WA_Enabled (1UL) /*!< Write access watch in this PREGION is enabled */
3842 #define MWU_REGIONENCLR_PRGN1WA_Clear (1UL) /*!< Disable write access watch in this PREGION */
3843 
3844 /* Bit 25 : Disable read access watch in PREGION[0] */
3845 #define MWU_REGIONENCLR_PRGN0RA_Pos (25UL) /*!< Position of PRGN0RA field. */
3846 #define MWU_REGIONENCLR_PRGN0RA_Msk (0x1UL << MWU_REGIONENCLR_PRGN0RA_Pos) /*!< Bit mask of PRGN0RA field. */
3847 #define MWU_REGIONENCLR_PRGN0RA_Disabled (0UL) /*!< Read access watch in this PREGION is disabled */
3848 #define MWU_REGIONENCLR_PRGN0RA_Enabled (1UL) /*!< Read access watch in this PREGION is enabled */
3849 #define MWU_REGIONENCLR_PRGN0RA_Clear (1UL) /*!< Disable read access watch in this PREGION */
3850 
3851 /* Bit 24 : Disable write access watch in PREGION[0] */
3852 #define MWU_REGIONENCLR_PRGN0WA_Pos (24UL) /*!< Position of PRGN0WA field. */
3853 #define MWU_REGIONENCLR_PRGN0WA_Msk (0x1UL << MWU_REGIONENCLR_PRGN0WA_Pos) /*!< Bit mask of PRGN0WA field. */
3854 #define MWU_REGIONENCLR_PRGN0WA_Disabled (0UL) /*!< Write access watch in this PREGION is disabled */
3855 #define MWU_REGIONENCLR_PRGN0WA_Enabled (1UL) /*!< Write access watch in this PREGION is enabled */
3856 #define MWU_REGIONENCLR_PRGN0WA_Clear (1UL) /*!< Disable write access watch in this PREGION */
3857 
3858 /* Bit 7 : Disable read access watch in region[3] */
3859 #define MWU_REGIONENCLR_RGN3RA_Pos (7UL) /*!< Position of RGN3RA field. */
3860 #define MWU_REGIONENCLR_RGN3RA_Msk (0x1UL << MWU_REGIONENCLR_RGN3RA_Pos) /*!< Bit mask of RGN3RA field. */
3861 #define MWU_REGIONENCLR_RGN3RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
3862 #define MWU_REGIONENCLR_RGN3RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
3863 #define MWU_REGIONENCLR_RGN3RA_Clear (1UL) /*!< Disable read access watch in this region */
3864 
3865 /* Bit 6 : Disable write access watch in region[3] */
3866 #define MWU_REGIONENCLR_RGN3WA_Pos (6UL) /*!< Position of RGN3WA field. */
3867 #define MWU_REGIONENCLR_RGN3WA_Msk (0x1UL << MWU_REGIONENCLR_RGN3WA_Pos) /*!< Bit mask of RGN3WA field. */
3868 #define MWU_REGIONENCLR_RGN3WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
3869 #define MWU_REGIONENCLR_RGN3WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
3870 #define MWU_REGIONENCLR_RGN3WA_Clear (1UL) /*!< Disable write access watch in this region */
3871 
3872 /* Bit 5 : Disable read access watch in region[2] */
3873 #define MWU_REGIONENCLR_RGN2RA_Pos (5UL) /*!< Position of RGN2RA field. */
3874 #define MWU_REGIONENCLR_RGN2RA_Msk (0x1UL << MWU_REGIONENCLR_RGN2RA_Pos) /*!< Bit mask of RGN2RA field. */
3875 #define MWU_REGIONENCLR_RGN2RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
3876 #define MWU_REGIONENCLR_RGN2RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
3877 #define MWU_REGIONENCLR_RGN2RA_Clear (1UL) /*!< Disable read access watch in this region */
3878 
3879 /* Bit 4 : Disable write access watch in region[2] */
3880 #define MWU_REGIONENCLR_RGN2WA_Pos (4UL) /*!< Position of RGN2WA field. */
3881 #define MWU_REGIONENCLR_RGN2WA_Msk (0x1UL << MWU_REGIONENCLR_RGN2WA_Pos) /*!< Bit mask of RGN2WA field. */
3882 #define MWU_REGIONENCLR_RGN2WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
3883 #define MWU_REGIONENCLR_RGN2WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
3884 #define MWU_REGIONENCLR_RGN2WA_Clear (1UL) /*!< Disable write access watch in this region */
3885 
3886 /* Bit 3 : Disable read access watch in region[1] */
3887 #define MWU_REGIONENCLR_RGN1RA_Pos (3UL) /*!< Position of RGN1RA field. */
3888 #define MWU_REGIONENCLR_RGN1RA_Msk (0x1UL << MWU_REGIONENCLR_RGN1RA_Pos) /*!< Bit mask of RGN1RA field. */
3889 #define MWU_REGIONENCLR_RGN1RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
3890 #define MWU_REGIONENCLR_RGN1RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
3891 #define MWU_REGIONENCLR_RGN1RA_Clear (1UL) /*!< Disable read access watch in this region */
3892 
3893 /* Bit 2 : Disable write access watch in region[1] */
3894 #define MWU_REGIONENCLR_RGN1WA_Pos (2UL) /*!< Position of RGN1WA field. */
3895 #define MWU_REGIONENCLR_RGN1WA_Msk (0x1UL << MWU_REGIONENCLR_RGN1WA_Pos) /*!< Bit mask of RGN1WA field. */
3896 #define MWU_REGIONENCLR_RGN1WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
3897 #define MWU_REGIONENCLR_RGN1WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
3898 #define MWU_REGIONENCLR_RGN1WA_Clear (1UL) /*!< Disable write access watch in this region */
3899 
3900 /* Bit 1 : Disable read access watch in region[0] */
3901 #define MWU_REGIONENCLR_RGN0RA_Pos (1UL) /*!< Position of RGN0RA field. */
3902 #define MWU_REGIONENCLR_RGN0RA_Msk (0x1UL << MWU_REGIONENCLR_RGN0RA_Pos) /*!< Bit mask of RGN0RA field. */
3903 #define MWU_REGIONENCLR_RGN0RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
3904 #define MWU_REGIONENCLR_RGN0RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
3905 #define MWU_REGIONENCLR_RGN0RA_Clear (1UL) /*!< Disable read access watch in this region */
3906 
3907 /* Bit 0 : Disable write access watch in region[0] */
3908 #define MWU_REGIONENCLR_RGN0WA_Pos (0UL) /*!< Position of RGN0WA field. */
3909 #define MWU_REGIONENCLR_RGN0WA_Msk (0x1UL << MWU_REGIONENCLR_RGN0WA_Pos) /*!< Bit mask of RGN0WA field. */
3910 #define MWU_REGIONENCLR_RGN0WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
3911 #define MWU_REGIONENCLR_RGN0WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
3912 #define MWU_REGIONENCLR_RGN0WA_Clear (1UL) /*!< Disable write access watch in this region */
3913 
3914 /* Register: MWU_REGION_START */
3915 /* Description: Description cluster[0]:  Start address for region 0 */
3916 
3917 /* Bits 31..0 : Start address for region */
3918 #define MWU_REGION_START_START_Pos (0UL) /*!< Position of START field. */
3919 #define MWU_REGION_START_START_Msk (0xFFFFFFFFUL << MWU_REGION_START_START_Pos) /*!< Bit mask of START field. */
3920 
3921 /* Register: MWU_REGION_END */
3922 /* Description: Description cluster[0]:  End address of region 0 */
3923 
3924 /* Bits 31..0 : End address of region. */
3925 #define MWU_REGION_END_END_Pos (0UL) /*!< Position of END field. */
3926 #define MWU_REGION_END_END_Msk (0xFFFFFFFFUL << MWU_REGION_END_END_Pos) /*!< Bit mask of END field. */
3927 
3928 /* Register: MWU_PREGION_START */
3929 /* Description: Description cluster[0]:  Reserved for future use */
3930 
3931 /* Bits 31..0 : Reserved for future use */
3932 #define MWU_PREGION_START_START_Pos (0UL) /*!< Position of START field. */
3933 #define MWU_PREGION_START_START_Msk (0xFFFFFFFFUL << MWU_PREGION_START_START_Pos) /*!< Bit mask of START field. */
3934 
3935 /* Register: MWU_PREGION_END */
3936 /* Description: Description cluster[0]:  Reserved for future use */
3937 
3938 /* Bits 31..0 : Reserved for future use */
3939 #define MWU_PREGION_END_END_Pos (0UL) /*!< Position of END field. */
3940 #define MWU_PREGION_END_END_Msk (0xFFFFFFFFUL << MWU_PREGION_END_END_Pos) /*!< Bit mask of END field. */
3941 
3942 /* Register: MWU_PREGION_SUBS */
3943 /* Description: Description cluster[0]:  Subregions of region 0 */
3944 
3945 /* Bit 31 : Include or exclude subregion 31 in region */
3946 #define MWU_PREGION_SUBS_SR31_Pos (31UL) /*!< Position of SR31 field. */
3947 #define MWU_PREGION_SUBS_SR31_Msk (0x1UL << MWU_PREGION_SUBS_SR31_Pos) /*!< Bit mask of SR31 field. */
3948 #define MWU_PREGION_SUBS_SR31_Exclude (0UL) /*!< Exclude */
3949 #define MWU_PREGION_SUBS_SR31_Include (1UL) /*!< Include */
3950 
3951 /* Bit 30 : Include or exclude subregion 30 in region */
3952 #define MWU_PREGION_SUBS_SR30_Pos (30UL) /*!< Position of SR30 field. */
3953 #define MWU_PREGION_SUBS_SR30_Msk (0x1UL << MWU_PREGION_SUBS_SR30_Pos) /*!< Bit mask of SR30 field. */
3954 #define MWU_PREGION_SUBS_SR30_Exclude (0UL) /*!< Exclude */
3955 #define MWU_PREGION_SUBS_SR30_Include (1UL) /*!< Include */
3956 
3957 /* Bit 29 : Include or exclude subregion 29 in region */
3958 #define MWU_PREGION_SUBS_SR29_Pos (29UL) /*!< Position of SR29 field. */
3959 #define MWU_PREGION_SUBS_SR29_Msk (0x1UL << MWU_PREGION_SUBS_SR29_Pos) /*!< Bit mask of SR29 field. */
3960 #define MWU_PREGION_SUBS_SR29_Exclude (0UL) /*!< Exclude */
3961 #define MWU_PREGION_SUBS_SR29_Include (1UL) /*!< Include */
3962 
3963 /* Bit 28 : Include or exclude subregion 28 in region */
3964 #define MWU_PREGION_SUBS_SR28_Pos (28UL) /*!< Position of SR28 field. */
3965 #define MWU_PREGION_SUBS_SR28_Msk (0x1UL << MWU_PREGION_SUBS_SR28_Pos) /*!< Bit mask of SR28 field. */
3966 #define MWU_PREGION_SUBS_SR28_Exclude (0UL) /*!< Exclude */
3967 #define MWU_PREGION_SUBS_SR28_Include (1UL) /*!< Include */
3968 
3969 /* Bit 27 : Include or exclude subregion 27 in region */
3970 #define MWU_PREGION_SUBS_SR27_Pos (27UL) /*!< Position of SR27 field. */
3971 #define MWU_PREGION_SUBS_SR27_Msk (0x1UL << MWU_PREGION_SUBS_SR27_Pos) /*!< Bit mask of SR27 field. */
3972 #define MWU_PREGION_SUBS_SR27_Exclude (0UL) /*!< Exclude */
3973 #define MWU_PREGION_SUBS_SR27_Include (1UL) /*!< Include */
3974 
3975 /* Bit 26 : Include or exclude subregion 26 in region */
3976 #define MWU_PREGION_SUBS_SR26_Pos (26UL) /*!< Position of SR26 field. */
3977 #define MWU_PREGION_SUBS_SR26_Msk (0x1UL << MWU_PREGION_SUBS_SR26_Pos) /*!< Bit mask of SR26 field. */
3978 #define MWU_PREGION_SUBS_SR26_Exclude (0UL) /*!< Exclude */
3979 #define MWU_PREGION_SUBS_SR26_Include (1UL) /*!< Include */
3980 
3981 /* Bit 25 : Include or exclude subregion 25 in region */
3982 #define MWU_PREGION_SUBS_SR25_Pos (25UL) /*!< Position of SR25 field. */
3983 #define MWU_PREGION_SUBS_SR25_Msk (0x1UL << MWU_PREGION_SUBS_SR25_Pos) /*!< Bit mask of SR25 field. */
3984 #define MWU_PREGION_SUBS_SR25_Exclude (0UL) /*!< Exclude */
3985 #define MWU_PREGION_SUBS_SR25_Include (1UL) /*!< Include */
3986 
3987 /* Bit 24 : Include or exclude subregion 24 in region */
3988 #define MWU_PREGION_SUBS_SR24_Pos (24UL) /*!< Position of SR24 field. */
3989 #define MWU_PREGION_SUBS_SR24_Msk (0x1UL << MWU_PREGION_SUBS_SR24_Pos) /*!< Bit mask of SR24 field. */
3990 #define MWU_PREGION_SUBS_SR24_Exclude (0UL) /*!< Exclude */
3991 #define MWU_PREGION_SUBS_SR24_Include (1UL) /*!< Include */
3992 
3993 /* Bit 23 : Include or exclude subregion 23 in region */
3994 #define MWU_PREGION_SUBS_SR23_Pos (23UL) /*!< Position of SR23 field. */
3995 #define MWU_PREGION_SUBS_SR23_Msk (0x1UL << MWU_PREGION_SUBS_SR23_Pos) /*!< Bit mask of SR23 field. */
3996 #define MWU_PREGION_SUBS_SR23_Exclude (0UL) /*!< Exclude */
3997 #define MWU_PREGION_SUBS_SR23_Include (1UL) /*!< Include */
3998 
3999 /* Bit 22 : Include or exclude subregion 22 in region */
4000 #define MWU_PREGION_SUBS_SR22_Pos (22UL) /*!< Position of SR22 field. */
4001 #define MWU_PREGION_SUBS_SR22_Msk (0x1UL << MWU_PREGION_SUBS_SR22_Pos) /*!< Bit mask of SR22 field. */
4002 #define MWU_PREGION_SUBS_SR22_Exclude (0UL) /*!< Exclude */
4003 #define MWU_PREGION_SUBS_SR22_Include (1UL) /*!< Include */
4004 
4005 /* Bit 21 : Include or exclude subregion 21 in region */
4006 #define MWU_PREGION_SUBS_SR21_Pos (21UL) /*!< Position of SR21 field. */
4007 #define MWU_PREGION_SUBS_SR21_Msk (0x1UL << MWU_PREGION_SUBS_SR21_Pos) /*!< Bit mask of SR21 field. */
4008 #define MWU_PREGION_SUBS_SR21_Exclude (0UL) /*!< Exclude */
4009 #define MWU_PREGION_SUBS_SR21_Include (1UL) /*!< Include */
4010 
4011 /* Bit 20 : Include or exclude subregion 20 in region */
4012 #define MWU_PREGION_SUBS_SR20_Pos (20UL) /*!< Position of SR20 field. */
4013 #define MWU_PREGION_SUBS_SR20_Msk (0x1UL << MWU_PREGION_SUBS_SR20_Pos) /*!< Bit mask of SR20 field. */
4014 #define MWU_PREGION_SUBS_SR20_Exclude (0UL) /*!< Exclude */
4015 #define MWU_PREGION_SUBS_SR20_Include (1UL) /*!< Include */
4016 
4017 /* Bit 19 : Include or exclude subregion 19 in region */
4018 #define MWU_PREGION_SUBS_SR19_Pos (19UL) /*!< Position of SR19 field. */
4019 #define MWU_PREGION_SUBS_SR19_Msk (0x1UL << MWU_PREGION_SUBS_SR19_Pos) /*!< Bit mask of SR19 field. */
4020 #define MWU_PREGION_SUBS_SR19_Exclude (0UL) /*!< Exclude */
4021 #define MWU_PREGION_SUBS_SR19_Include (1UL) /*!< Include */
4022 
4023 /* Bit 18 : Include or exclude subregion 18 in region */
4024 #define MWU_PREGION_SUBS_SR18_Pos (18UL) /*!< Position of SR18 field. */
4025 #define MWU_PREGION_SUBS_SR18_Msk (0x1UL << MWU_PREGION_SUBS_SR18_Pos) /*!< Bit mask of SR18 field. */
4026 #define MWU_PREGION_SUBS_SR18_Exclude (0UL) /*!< Exclude */
4027 #define MWU_PREGION_SUBS_SR18_Include (1UL) /*!< Include */
4028 
4029 /* Bit 17 : Include or exclude subregion 17 in region */
4030 #define MWU_PREGION_SUBS_SR17_Pos (17UL) /*!< Position of SR17 field. */
4031 #define MWU_PREGION_SUBS_SR17_Msk (0x1UL << MWU_PREGION_SUBS_SR17_Pos) /*!< Bit mask of SR17 field. */
4032 #define MWU_PREGION_SUBS_SR17_Exclude (0UL) /*!< Exclude */
4033 #define MWU_PREGION_SUBS_SR17_Include (1UL) /*!< Include */
4034 
4035 /* Bit 16 : Include or exclude subregion 16 in region */
4036 #define MWU_PREGION_SUBS_SR16_Pos (16UL) /*!< Position of SR16 field. */
4037 #define MWU_PREGION_SUBS_SR16_Msk (0x1UL << MWU_PREGION_SUBS_SR16_Pos) /*!< Bit mask of SR16 field. */
4038 #define MWU_PREGION_SUBS_SR16_Exclude (0UL) /*!< Exclude */
4039 #define MWU_PREGION_SUBS_SR16_Include (1UL) /*!< Include */
4040 
4041 /* Bit 15 : Include or exclude subregion 15 in region */
4042 #define MWU_PREGION_SUBS_SR15_Pos (15UL) /*!< Position of SR15 field. */
4043 #define MWU_PREGION_SUBS_SR15_Msk (0x1UL << MWU_PREGION_SUBS_SR15_Pos) /*!< Bit mask of SR15 field. */
4044 #define MWU_PREGION_SUBS_SR15_Exclude (0UL) /*!< Exclude */
4045 #define MWU_PREGION_SUBS_SR15_Include (1UL) /*!< Include */
4046 
4047 /* Bit 14 : Include or exclude subregion 14 in region */
4048 #define MWU_PREGION_SUBS_SR14_Pos (14UL) /*!< Position of SR14 field. */
4049 #define MWU_PREGION_SUBS_SR14_Msk (0x1UL << MWU_PREGION_SUBS_SR14_Pos) /*!< Bit mask of SR14 field. */
4050 #define MWU_PREGION_SUBS_SR14_Exclude (0UL) /*!< Exclude */
4051 #define MWU_PREGION_SUBS_SR14_Include (1UL) /*!< Include */
4052 
4053 /* Bit 13 : Include or exclude subregion 13 in region */
4054 #define MWU_PREGION_SUBS_SR13_Pos (13UL) /*!< Position of SR13 field. */
4055 #define MWU_PREGION_SUBS_SR13_Msk (0x1UL << MWU_PREGION_SUBS_SR13_Pos) /*!< Bit mask of SR13 field. */
4056 #define MWU_PREGION_SUBS_SR13_Exclude (0UL) /*!< Exclude */
4057 #define MWU_PREGION_SUBS_SR13_Include (1UL) /*!< Include */
4058 
4059 /* Bit 12 : Include or exclude subregion 12 in region */
4060 #define MWU_PREGION_SUBS_SR12_Pos (12UL) /*!< Position of SR12 field. */
4061 #define MWU_PREGION_SUBS_SR12_Msk (0x1UL << MWU_PREGION_SUBS_SR12_Pos) /*!< Bit mask of SR12 field. */
4062 #define MWU_PREGION_SUBS_SR12_Exclude (0UL) /*!< Exclude */
4063 #define MWU_PREGION_SUBS_SR12_Include (1UL) /*!< Include */
4064 
4065 /* Bit 11 : Include or exclude subregion 11 in region */
4066 #define MWU_PREGION_SUBS_SR11_Pos (11UL) /*!< Position of SR11 field. */
4067 #define MWU_PREGION_SUBS_SR11_Msk (0x1UL << MWU_PREGION_SUBS_SR11_Pos) /*!< Bit mask of SR11 field. */
4068 #define MWU_PREGION_SUBS_SR11_Exclude (0UL) /*!< Exclude */
4069 #define MWU_PREGION_SUBS_SR11_Include (1UL) /*!< Include */
4070 
4071 /* Bit 10 : Include or exclude subregion 10 in region */
4072 #define MWU_PREGION_SUBS_SR10_Pos (10UL) /*!< Position of SR10 field. */
4073 #define MWU_PREGION_SUBS_SR10_Msk (0x1UL << MWU_PREGION_SUBS_SR10_Pos) /*!< Bit mask of SR10 field. */
4074 #define MWU_PREGION_SUBS_SR10_Exclude (0UL) /*!< Exclude */
4075 #define MWU_PREGION_SUBS_SR10_Include (1UL) /*!< Include */
4076 
4077 /* Bit 9 : Include or exclude subregion 9 in region */
4078 #define MWU_PREGION_SUBS_SR9_Pos (9UL) /*!< Position of SR9 field. */
4079 #define MWU_PREGION_SUBS_SR9_Msk (0x1UL << MWU_PREGION_SUBS_SR9_Pos) /*!< Bit mask of SR9 field. */
4080 #define MWU_PREGION_SUBS_SR9_Exclude (0UL) /*!< Exclude */
4081 #define MWU_PREGION_SUBS_SR9_Include (1UL) /*!< Include */
4082 
4083 /* Bit 8 : Include or exclude subregion 8 in region */
4084 #define MWU_PREGION_SUBS_SR8_Pos (8UL) /*!< Position of SR8 field. */
4085 #define MWU_PREGION_SUBS_SR8_Msk (0x1UL << MWU_PREGION_SUBS_SR8_Pos) /*!< Bit mask of SR8 field. */
4086 #define MWU_PREGION_SUBS_SR8_Exclude (0UL) /*!< Exclude */
4087 #define MWU_PREGION_SUBS_SR8_Include (1UL) /*!< Include */
4088 
4089 /* Bit 7 : Include or exclude subregion 7 in region */
4090 #define MWU_PREGION_SUBS_SR7_Pos (7UL) /*!< Position of SR7 field. */
4091 #define MWU_PREGION_SUBS_SR7_Msk (0x1UL << MWU_PREGION_SUBS_SR7_Pos) /*!< Bit mask of SR7 field. */
4092 #define MWU_PREGION_SUBS_SR7_Exclude (0UL) /*!< Exclude */
4093 #define MWU_PREGION_SUBS_SR7_Include (1UL) /*!< Include */
4094 
4095 /* Bit 6 : Include or exclude subregion 6 in region */
4096 #define MWU_PREGION_SUBS_SR6_Pos (6UL) /*!< Position of SR6 field. */
4097 #define MWU_PREGION_SUBS_SR6_Msk (0x1UL << MWU_PREGION_SUBS_SR6_Pos) /*!< Bit mask of SR6 field. */
4098 #define MWU_PREGION_SUBS_SR6_Exclude (0UL) /*!< Exclude */
4099 #define MWU_PREGION_SUBS_SR6_Include (1UL) /*!< Include */
4100 
4101 /* Bit 5 : Include or exclude subregion 5 in region */
4102 #define MWU_PREGION_SUBS_SR5_Pos (5UL) /*!< Position of SR5 field. */
4103 #define MWU_PREGION_SUBS_SR5_Msk (0x1UL << MWU_PREGION_SUBS_SR5_Pos) /*!< Bit mask of SR5 field. */
4104 #define MWU_PREGION_SUBS_SR5_Exclude (0UL) /*!< Exclude */
4105 #define MWU_PREGION_SUBS_SR5_Include (1UL) /*!< Include */
4106 
4107 /* Bit 4 : Include or exclude subregion 4 in region */
4108 #define MWU_PREGION_SUBS_SR4_Pos (4UL) /*!< Position of SR4 field. */
4109 #define MWU_PREGION_SUBS_SR4_Msk (0x1UL << MWU_PREGION_SUBS_SR4_Pos) /*!< Bit mask of SR4 field. */
4110 #define MWU_PREGION_SUBS_SR4_Exclude (0UL) /*!< Exclude */
4111 #define MWU_PREGION_SUBS_SR4_Include (1UL) /*!< Include */
4112 
4113 /* Bit 3 : Include or exclude subregion 3 in region */
4114 #define MWU_PREGION_SUBS_SR3_Pos (3UL) /*!< Position of SR3 field. */
4115 #define MWU_PREGION_SUBS_SR3_Msk (0x1UL << MWU_PREGION_SUBS_SR3_Pos) /*!< Bit mask of SR3 field. */
4116 #define MWU_PREGION_SUBS_SR3_Exclude (0UL) /*!< Exclude */
4117 #define MWU_PREGION_SUBS_SR3_Include (1UL) /*!< Include */
4118 
4119 /* Bit 2 : Include or exclude subregion 2 in region */
4120 #define MWU_PREGION_SUBS_SR2_Pos (2UL) /*!< Position of SR2 field. */
4121 #define MWU_PREGION_SUBS_SR2_Msk (0x1UL << MWU_PREGION_SUBS_SR2_Pos) /*!< Bit mask of SR2 field. */
4122 #define MWU_PREGION_SUBS_SR2_Exclude (0UL) /*!< Exclude */
4123 #define MWU_PREGION_SUBS_SR2_Include (1UL) /*!< Include */
4124 
4125 /* Bit 1 : Include or exclude subregion 1 in region */
4126 #define MWU_PREGION_SUBS_SR1_Pos (1UL) /*!< Position of SR1 field. */
4127 #define MWU_PREGION_SUBS_SR1_Msk (0x1UL << MWU_PREGION_SUBS_SR1_Pos) /*!< Bit mask of SR1 field. */
4128 #define MWU_PREGION_SUBS_SR1_Exclude (0UL) /*!< Exclude */
4129 #define MWU_PREGION_SUBS_SR1_Include (1UL) /*!< Include */
4130 
4131 /* Bit 0 : Include or exclude subregion 0 in region */
4132 #define MWU_PREGION_SUBS_SR0_Pos (0UL) /*!< Position of SR0 field. */
4133 #define MWU_PREGION_SUBS_SR0_Msk (0x1UL << MWU_PREGION_SUBS_SR0_Pos) /*!< Bit mask of SR0 field. */
4134 #define MWU_PREGION_SUBS_SR0_Exclude (0UL) /*!< Exclude */
4135 #define MWU_PREGION_SUBS_SR0_Include (1UL) /*!< Include */
4136 
4137 
4138 /* Peripheral: NFCT */
4139 /* Description: NFC-A compatible radio */
4140 
4141 /* Register: NFCT_SHORTS */
4142 /* Description: Shortcut register */
4143 
4144 /* Bit 1 : Shortcut between FIELDLOST event and SENSE task */
4145 #define NFCT_SHORTS_FIELDLOST_SENSE_Pos (1UL) /*!< Position of FIELDLOST_SENSE field. */
4146 #define NFCT_SHORTS_FIELDLOST_SENSE_Msk (0x1UL << NFCT_SHORTS_FIELDLOST_SENSE_Pos) /*!< Bit mask of FIELDLOST_SENSE field. */
4147 #define NFCT_SHORTS_FIELDLOST_SENSE_Disabled (0UL) /*!< Disable shortcut */
4148 #define NFCT_SHORTS_FIELDLOST_SENSE_Enabled (1UL) /*!< Enable shortcut */
4149 
4150 /* Bit 0 : Shortcut between FIELDDETECTED event and ACTIVATE task */
4151 #define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Pos (0UL) /*!< Position of FIELDDETECTED_ACTIVATE field. */
4152 #define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Msk (0x1UL << NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Pos) /*!< Bit mask of FIELDDETECTED_ACTIVATE field. */
4153 #define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Disabled (0UL) /*!< Disable shortcut */
4154 #define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Enabled (1UL) /*!< Enable shortcut */
4155 
4156 /* Register: NFCT_INTEN */
4157 /* Description: Enable or disable interrupt */
4158 
4159 /* Bit 20 : Enable or disable interrupt for STARTED event */
4160 #define NFCT_INTEN_STARTED_Pos (20UL) /*!< Position of STARTED field. */
4161 #define NFCT_INTEN_STARTED_Msk (0x1UL << NFCT_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */
4162 #define NFCT_INTEN_STARTED_Disabled (0UL) /*!< Disable */
4163 #define NFCT_INTEN_STARTED_Enabled (1UL) /*!< Enable */
4164 
4165 /* Bit 19 : Enable or disable interrupt for SELECTED event */
4166 #define NFCT_INTEN_SELECTED_Pos (19UL) /*!< Position of SELECTED field. */
4167 #define NFCT_INTEN_SELECTED_Msk (0x1UL << NFCT_INTEN_SELECTED_Pos) /*!< Bit mask of SELECTED field. */
4168 #define NFCT_INTEN_SELECTED_Disabled (0UL) /*!< Disable */
4169 #define NFCT_INTEN_SELECTED_Enabled (1UL) /*!< Enable */
4170 
4171 /* Bit 18 : Enable or disable interrupt for COLLISION event */
4172 #define NFCT_INTEN_COLLISION_Pos (18UL) /*!< Position of COLLISION field. */
4173 #define NFCT_INTEN_COLLISION_Msk (0x1UL << NFCT_INTEN_COLLISION_Pos) /*!< Bit mask of COLLISION field. */
4174 #define NFCT_INTEN_COLLISION_Disabled (0UL) /*!< Disable */
4175 #define NFCT_INTEN_COLLISION_Enabled (1UL) /*!< Enable */
4176 
4177 /* Bit 14 : Enable or disable interrupt for AUTOCOLRESSTARTED event */
4178 #define NFCT_INTEN_AUTOCOLRESSTARTED_Pos (14UL) /*!< Position of AUTOCOLRESSTARTED field. */
4179 #define NFCT_INTEN_AUTOCOLRESSTARTED_Msk (0x1UL << NFCT_INTEN_AUTOCOLRESSTARTED_Pos) /*!< Bit mask of AUTOCOLRESSTARTED field. */
4180 #define NFCT_INTEN_AUTOCOLRESSTARTED_Disabled (0UL) /*!< Disable */
4181 #define NFCT_INTEN_AUTOCOLRESSTARTED_Enabled (1UL) /*!< Enable */
4182 
4183 /* Bit 12 : Enable or disable interrupt for ENDTX event */
4184 #define NFCT_INTEN_ENDTX_Pos (12UL) /*!< Position of ENDTX field. */
4185 #define NFCT_INTEN_ENDTX_Msk (0x1UL << NFCT_INTEN_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
4186 #define NFCT_INTEN_ENDTX_Disabled (0UL) /*!< Disable */
4187 #define NFCT_INTEN_ENDTX_Enabled (1UL) /*!< Enable */
4188 
4189 /* Bit 11 : Enable or disable interrupt for ENDRX event */
4190 #define NFCT_INTEN_ENDRX_Pos (11UL) /*!< Position of ENDRX field. */
4191 #define NFCT_INTEN_ENDRX_Msk (0x1UL << NFCT_INTEN_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
4192 #define NFCT_INTEN_ENDRX_Disabled (0UL) /*!< Disable */
4193 #define NFCT_INTEN_ENDRX_Enabled (1UL) /*!< Enable */
4194 
4195 /* Bit 10 : Enable or disable interrupt for RXERROR event */
4196 #define NFCT_INTEN_RXERROR_Pos (10UL) /*!< Position of RXERROR field. */
4197 #define NFCT_INTEN_RXERROR_Msk (0x1UL << NFCT_INTEN_RXERROR_Pos) /*!< Bit mask of RXERROR field. */
4198 #define NFCT_INTEN_RXERROR_Disabled (0UL) /*!< Disable */
4199 #define NFCT_INTEN_RXERROR_Enabled (1UL) /*!< Enable */
4200 
4201 /* Bit 7 : Enable or disable interrupt for ERROR event */
4202 #define NFCT_INTEN_ERROR_Pos (7UL) /*!< Position of ERROR field. */
4203 #define NFCT_INTEN_ERROR_Msk (0x1UL << NFCT_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */
4204 #define NFCT_INTEN_ERROR_Disabled (0UL) /*!< Disable */
4205 #define NFCT_INTEN_ERROR_Enabled (1UL) /*!< Enable */
4206 
4207 /* Bit 6 : Enable or disable interrupt for RXFRAMEEND event */
4208 #define NFCT_INTEN_RXFRAMEEND_Pos (6UL) /*!< Position of RXFRAMEEND field. */
4209 #define NFCT_INTEN_RXFRAMEEND_Msk (0x1UL << NFCT_INTEN_RXFRAMEEND_Pos) /*!< Bit mask of RXFRAMEEND field. */
4210 #define NFCT_INTEN_RXFRAMEEND_Disabled (0UL) /*!< Disable */
4211 #define NFCT_INTEN_RXFRAMEEND_Enabled (1UL) /*!< Enable */
4212 
4213 /* Bit 5 : Enable or disable interrupt for RXFRAMESTART event */
4214 #define NFCT_INTEN_RXFRAMESTART_Pos (5UL) /*!< Position of RXFRAMESTART field. */
4215 #define NFCT_INTEN_RXFRAMESTART_Msk (0x1UL << NFCT_INTEN_RXFRAMESTART_Pos) /*!< Bit mask of RXFRAMESTART field. */
4216 #define NFCT_INTEN_RXFRAMESTART_Disabled (0UL) /*!< Disable */
4217 #define NFCT_INTEN_RXFRAMESTART_Enabled (1UL) /*!< Enable */
4218 
4219 /* Bit 4 : Enable or disable interrupt for TXFRAMEEND event */
4220 #define NFCT_INTEN_TXFRAMEEND_Pos (4UL) /*!< Position of TXFRAMEEND field. */
4221 #define NFCT_INTEN_TXFRAMEEND_Msk (0x1UL << NFCT_INTEN_TXFRAMEEND_Pos) /*!< Bit mask of TXFRAMEEND field. */
4222 #define NFCT_INTEN_TXFRAMEEND_Disabled (0UL) /*!< Disable */
4223 #define NFCT_INTEN_TXFRAMEEND_Enabled (1UL) /*!< Enable */
4224 
4225 /* Bit 3 : Enable or disable interrupt for TXFRAMESTART event */
4226 #define NFCT_INTEN_TXFRAMESTART_Pos (3UL) /*!< Position of TXFRAMESTART field. */
4227 #define NFCT_INTEN_TXFRAMESTART_Msk (0x1UL << NFCT_INTEN_TXFRAMESTART_Pos) /*!< Bit mask of TXFRAMESTART field. */
4228 #define NFCT_INTEN_TXFRAMESTART_Disabled (0UL) /*!< Disable */
4229 #define NFCT_INTEN_TXFRAMESTART_Enabled (1UL) /*!< Enable */
4230 
4231 /* Bit 2 : Enable or disable interrupt for FIELDLOST event */
4232 #define NFCT_INTEN_FIELDLOST_Pos (2UL) /*!< Position of FIELDLOST field. */
4233 #define NFCT_INTEN_FIELDLOST_Msk (0x1UL << NFCT_INTEN_FIELDLOST_Pos) /*!< Bit mask of FIELDLOST field. */
4234 #define NFCT_INTEN_FIELDLOST_Disabled (0UL) /*!< Disable */
4235 #define NFCT_INTEN_FIELDLOST_Enabled (1UL) /*!< Enable */
4236 
4237 /* Bit 1 : Enable or disable interrupt for FIELDDETECTED event */
4238 #define NFCT_INTEN_FIELDDETECTED_Pos (1UL) /*!< Position of FIELDDETECTED field. */
4239 #define NFCT_INTEN_FIELDDETECTED_Msk (0x1UL << NFCT_INTEN_FIELDDETECTED_Pos) /*!< Bit mask of FIELDDETECTED field. */
4240 #define NFCT_INTEN_FIELDDETECTED_Disabled (0UL) /*!< Disable */
4241 #define NFCT_INTEN_FIELDDETECTED_Enabled (1UL) /*!< Enable */
4242 
4243 /* Bit 0 : Enable or disable interrupt for READY event */
4244 #define NFCT_INTEN_READY_Pos (0UL) /*!< Position of READY field. */
4245 #define NFCT_INTEN_READY_Msk (0x1UL << NFCT_INTEN_READY_Pos) /*!< Bit mask of READY field. */
4246 #define NFCT_INTEN_READY_Disabled (0UL) /*!< Disable */
4247 #define NFCT_INTEN_READY_Enabled (1UL) /*!< Enable */
4248 
4249 /* Register: NFCT_INTENSET */
4250 /* Description: Enable interrupt */
4251 
4252 /* Bit 20 : Write '1' to Enable interrupt for STARTED event */
4253 #define NFCT_INTENSET_STARTED_Pos (20UL) /*!< Position of STARTED field. */
4254 #define NFCT_INTENSET_STARTED_Msk (0x1UL << NFCT_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */
4255 #define NFCT_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */
4256 #define NFCT_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */
4257 #define NFCT_INTENSET_STARTED_Set (1UL) /*!< Enable */
4258 
4259 /* Bit 19 : Write '1' to Enable interrupt for SELECTED event */
4260 #define NFCT_INTENSET_SELECTED_Pos (19UL) /*!< Position of SELECTED field. */
4261 #define NFCT_INTENSET_SELECTED_Msk (0x1UL << NFCT_INTENSET_SELECTED_Pos) /*!< Bit mask of SELECTED field. */
4262 #define NFCT_INTENSET_SELECTED_Disabled (0UL) /*!< Read: Disabled */
4263 #define NFCT_INTENSET_SELECTED_Enabled (1UL) /*!< Read: Enabled */
4264 #define NFCT_INTENSET_SELECTED_Set (1UL) /*!< Enable */
4265 
4266 /* Bit 18 : Write '1' to Enable interrupt for COLLISION event */
4267 #define NFCT_INTENSET_COLLISION_Pos (18UL) /*!< Position of COLLISION field. */
4268 #define NFCT_INTENSET_COLLISION_Msk (0x1UL << NFCT_INTENSET_COLLISION_Pos) /*!< Bit mask of COLLISION field. */
4269 #define NFCT_INTENSET_COLLISION_Disabled (0UL) /*!< Read: Disabled */
4270 #define NFCT_INTENSET_COLLISION_Enabled (1UL) /*!< Read: Enabled */
4271 #define NFCT_INTENSET_COLLISION_Set (1UL) /*!< Enable */
4272 
4273 /* Bit 14 : Write '1' to Enable interrupt for AUTOCOLRESSTARTED event */
4274 #define NFCT_INTENSET_AUTOCOLRESSTARTED_Pos (14UL) /*!< Position of AUTOCOLRESSTARTED field. */
4275 #define NFCT_INTENSET_AUTOCOLRESSTARTED_Msk (0x1UL << NFCT_INTENSET_AUTOCOLRESSTARTED_Pos) /*!< Bit mask of AUTOCOLRESSTARTED field. */
4276 #define NFCT_INTENSET_AUTOCOLRESSTARTED_Disabled (0UL) /*!< Read: Disabled */
4277 #define NFCT_INTENSET_AUTOCOLRESSTARTED_Enabled (1UL) /*!< Read: Enabled */
4278 #define NFCT_INTENSET_AUTOCOLRESSTARTED_Set (1UL) /*!< Enable */
4279 
4280 /* Bit 12 : Write '1' to Enable interrupt for ENDTX event */
4281 #define NFCT_INTENSET_ENDTX_Pos (12UL) /*!< Position of ENDTX field. */
4282 #define NFCT_INTENSET_ENDTX_Msk (0x1UL << NFCT_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
4283 #define NFCT_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */
4284 #define NFCT_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */
4285 #define NFCT_INTENSET_ENDTX_Set (1UL) /*!< Enable */
4286 
4287 /* Bit 11 : Write '1' to Enable interrupt for ENDRX event */
4288 #define NFCT_INTENSET_ENDRX_Pos (11UL) /*!< Position of ENDRX field. */
4289 #define NFCT_INTENSET_ENDRX_Msk (0x1UL << NFCT_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
4290 #define NFCT_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */
4291 #define NFCT_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */
4292 #define NFCT_INTENSET_ENDRX_Set (1UL) /*!< Enable */
4293 
4294 /* Bit 10 : Write '1' to Enable interrupt for RXERROR event */
4295 #define NFCT_INTENSET_RXERROR_Pos (10UL) /*!< Position of RXERROR field. */
4296 #define NFCT_INTENSET_RXERROR_Msk (0x1UL << NFCT_INTENSET_RXERROR_Pos) /*!< Bit mask of RXERROR field. */
4297 #define NFCT_INTENSET_RXERROR_Disabled (0UL) /*!< Read: Disabled */
4298 #define NFCT_INTENSET_RXERROR_Enabled (1UL) /*!< Read: Enabled */
4299 #define NFCT_INTENSET_RXERROR_Set (1UL) /*!< Enable */
4300 
4301 /* Bit 7 : Write '1' to Enable interrupt for ERROR event */
4302 #define NFCT_INTENSET_ERROR_Pos (7UL) /*!< Position of ERROR field. */
4303 #define NFCT_INTENSET_ERROR_Msk (0x1UL << NFCT_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
4304 #define NFCT_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
4305 #define NFCT_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
4306 #define NFCT_INTENSET_ERROR_Set (1UL) /*!< Enable */
4307 
4308 /* Bit 6 : Write '1' to Enable interrupt for RXFRAMEEND event */
4309 #define NFCT_INTENSET_RXFRAMEEND_Pos (6UL) /*!< Position of RXFRAMEEND field. */
4310 #define NFCT_INTENSET_RXFRAMEEND_Msk (0x1UL << NFCT_INTENSET_RXFRAMEEND_Pos) /*!< Bit mask of RXFRAMEEND field. */
4311 #define NFCT_INTENSET_RXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */
4312 #define NFCT_INTENSET_RXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */
4313 #define NFCT_INTENSET_RXFRAMEEND_Set (1UL) /*!< Enable */
4314 
4315 /* Bit 5 : Write '1' to Enable interrupt for RXFRAMESTART event */
4316 #define NFCT_INTENSET_RXFRAMESTART_Pos (5UL) /*!< Position of RXFRAMESTART field. */
4317 #define NFCT_INTENSET_RXFRAMESTART_Msk (0x1UL << NFCT_INTENSET_RXFRAMESTART_Pos) /*!< Bit mask of RXFRAMESTART field. */
4318 #define NFCT_INTENSET_RXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */
4319 #define NFCT_INTENSET_RXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */
4320 #define NFCT_INTENSET_RXFRAMESTART_Set (1UL) /*!< Enable */
4321 
4322 /* Bit 4 : Write '1' to Enable interrupt for TXFRAMEEND event */
4323 #define NFCT_INTENSET_TXFRAMEEND_Pos (4UL) /*!< Position of TXFRAMEEND field. */
4324 #define NFCT_INTENSET_TXFRAMEEND_Msk (0x1UL << NFCT_INTENSET_TXFRAMEEND_Pos) /*!< Bit mask of TXFRAMEEND field. */
4325 #define NFCT_INTENSET_TXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */
4326 #define NFCT_INTENSET_TXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */
4327 #define NFCT_INTENSET_TXFRAMEEND_Set (1UL) /*!< Enable */
4328 
4329 /* Bit 3 : Write '1' to Enable interrupt for TXFRAMESTART event */
4330 #define NFCT_INTENSET_TXFRAMESTART_Pos (3UL) /*!< Position of TXFRAMESTART field. */
4331 #define NFCT_INTENSET_TXFRAMESTART_Msk (0x1UL << NFCT_INTENSET_TXFRAMESTART_Pos) /*!< Bit mask of TXFRAMESTART field. */
4332 #define NFCT_INTENSET_TXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */
4333 #define NFCT_INTENSET_TXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */
4334 #define NFCT_INTENSET_TXFRAMESTART_Set (1UL) /*!< Enable */
4335 
4336 /* Bit 2 : Write '1' to Enable interrupt for FIELDLOST event */
4337 #define NFCT_INTENSET_FIELDLOST_Pos (2UL) /*!< Position of FIELDLOST field. */
4338 #define NFCT_INTENSET_FIELDLOST_Msk (0x1UL << NFCT_INTENSET_FIELDLOST_Pos) /*!< Bit mask of FIELDLOST field. */
4339 #define NFCT_INTENSET_FIELDLOST_Disabled (0UL) /*!< Read: Disabled */
4340 #define NFCT_INTENSET_FIELDLOST_Enabled (1UL) /*!< Read: Enabled */
4341 #define NFCT_INTENSET_FIELDLOST_Set (1UL) /*!< Enable */
4342 
4343 /* Bit 1 : Write '1' to Enable interrupt for FIELDDETECTED event */
4344 #define NFCT_INTENSET_FIELDDETECTED_Pos (1UL) /*!< Position of FIELDDETECTED field. */
4345 #define NFCT_INTENSET_FIELDDETECTED_Msk (0x1UL << NFCT_INTENSET_FIELDDETECTED_Pos) /*!< Bit mask of FIELDDETECTED field. */
4346 #define NFCT_INTENSET_FIELDDETECTED_Disabled (0UL) /*!< Read: Disabled */
4347 #define NFCT_INTENSET_FIELDDETECTED_Enabled (1UL) /*!< Read: Enabled */
4348 #define NFCT_INTENSET_FIELDDETECTED_Set (1UL) /*!< Enable */
4349 
4350 /* Bit 0 : Write '1' to Enable interrupt for READY event */
4351 #define NFCT_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */
4352 #define NFCT_INTENSET_READY_Msk (0x1UL << NFCT_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
4353 #define NFCT_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */
4354 #define NFCT_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */
4355 #define NFCT_INTENSET_READY_Set (1UL) /*!< Enable */
4356 
4357 /* Register: NFCT_INTENCLR */
4358 /* Description: Disable interrupt */
4359 
4360 /* Bit 20 : Write '1' to Disable interrupt for STARTED event */
4361 #define NFCT_INTENCLR_STARTED_Pos (20UL) /*!< Position of STARTED field. */
4362 #define NFCT_INTENCLR_STARTED_Msk (0x1UL << NFCT_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */
4363 #define NFCT_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */
4364 #define NFCT_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */
4365 #define NFCT_INTENCLR_STARTED_Clear (1UL) /*!< Disable */
4366 
4367 /* Bit 19 : Write '1' to Disable interrupt for SELECTED event */
4368 #define NFCT_INTENCLR_SELECTED_Pos (19UL) /*!< Position of SELECTED field. */
4369 #define NFCT_INTENCLR_SELECTED_Msk (0x1UL << NFCT_INTENCLR_SELECTED_Pos) /*!< Bit mask of SELECTED field. */
4370 #define NFCT_INTENCLR_SELECTED_Disabled (0UL) /*!< Read: Disabled */
4371 #define NFCT_INTENCLR_SELECTED_Enabled (1UL) /*!< Read: Enabled */
4372 #define NFCT_INTENCLR_SELECTED_Clear (1UL) /*!< Disable */
4373 
4374 /* Bit 18 : Write '1' to Disable interrupt for COLLISION event */
4375 #define NFCT_INTENCLR_COLLISION_Pos (18UL) /*!< Position of COLLISION field. */
4376 #define NFCT_INTENCLR_COLLISION_Msk (0x1UL << NFCT_INTENCLR_COLLISION_Pos) /*!< Bit mask of COLLISION field. */
4377 #define NFCT_INTENCLR_COLLISION_Disabled (0UL) /*!< Read: Disabled */
4378 #define NFCT_INTENCLR_COLLISION_Enabled (1UL) /*!< Read: Enabled */
4379 #define NFCT_INTENCLR_COLLISION_Clear (1UL) /*!< Disable */
4380 
4381 /* Bit 14 : Write '1' to Disable interrupt for AUTOCOLRESSTARTED event */
4382 #define NFCT_INTENCLR_AUTOCOLRESSTARTED_Pos (14UL) /*!< Position of AUTOCOLRESSTARTED field. */
4383 #define NFCT_INTENCLR_AUTOCOLRESSTARTED_Msk (0x1UL << NFCT_INTENCLR_AUTOCOLRESSTARTED_Pos) /*!< Bit mask of AUTOCOLRESSTARTED field. */
4384 #define NFCT_INTENCLR_AUTOCOLRESSTARTED_Disabled (0UL) /*!< Read: Disabled */
4385 #define NFCT_INTENCLR_AUTOCOLRESSTARTED_Enabled (1UL) /*!< Read: Enabled */
4386 #define NFCT_INTENCLR_AUTOCOLRESSTARTED_Clear (1UL) /*!< Disable */
4387 
4388 /* Bit 12 : Write '1' to Disable interrupt for ENDTX event */
4389 #define NFCT_INTENCLR_ENDTX_Pos (12UL) /*!< Position of ENDTX field. */
4390 #define NFCT_INTENCLR_ENDTX_Msk (0x1UL << NFCT_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
4391 #define NFCT_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */
4392 #define NFCT_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */
4393 #define NFCT_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */
4394 
4395 /* Bit 11 : Write '1' to Disable interrupt for ENDRX event */
4396 #define NFCT_INTENCLR_ENDRX_Pos (11UL) /*!< Position of ENDRX field. */
4397 #define NFCT_INTENCLR_ENDRX_Msk (0x1UL << NFCT_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
4398 #define NFCT_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */
4399 #define NFCT_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */
4400 #define NFCT_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */
4401 
4402 /* Bit 10 : Write '1' to Disable interrupt for RXERROR event */
4403 #define NFCT_INTENCLR_RXERROR_Pos (10UL) /*!< Position of RXERROR field. */
4404 #define NFCT_INTENCLR_RXERROR_Msk (0x1UL << NFCT_INTENCLR_RXERROR_Pos) /*!< Bit mask of RXERROR field. */
4405 #define NFCT_INTENCLR_RXERROR_Disabled (0UL) /*!< Read: Disabled */
4406 #define NFCT_INTENCLR_RXERROR_Enabled (1UL) /*!< Read: Enabled */
4407 #define NFCT_INTENCLR_RXERROR_Clear (1UL) /*!< Disable */
4408 
4409 /* Bit 7 : Write '1' to Disable interrupt for ERROR event */
4410 #define NFCT_INTENCLR_ERROR_Pos (7UL) /*!< Position of ERROR field. */
4411 #define NFCT_INTENCLR_ERROR_Msk (0x1UL << NFCT_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
4412 #define NFCT_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
4413 #define NFCT_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
4414 #define NFCT_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
4415 
4416 /* Bit 6 : Write '1' to Disable interrupt for RXFRAMEEND event */
4417 #define NFCT_INTENCLR_RXFRAMEEND_Pos (6UL) /*!< Position of RXFRAMEEND field. */
4418 #define NFCT_INTENCLR_RXFRAMEEND_Msk (0x1UL << NFCT_INTENCLR_RXFRAMEEND_Pos) /*!< Bit mask of RXFRAMEEND field. */
4419 #define NFCT_INTENCLR_RXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */
4420 #define NFCT_INTENCLR_RXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */
4421 #define NFCT_INTENCLR_RXFRAMEEND_Clear (1UL) /*!< Disable */
4422 
4423 /* Bit 5 : Write '1' to Disable interrupt for RXFRAMESTART event */
4424 #define NFCT_INTENCLR_RXFRAMESTART_Pos (5UL) /*!< Position of RXFRAMESTART field. */
4425 #define NFCT_INTENCLR_RXFRAMESTART_Msk (0x1UL << NFCT_INTENCLR_RXFRAMESTART_Pos) /*!< Bit mask of RXFRAMESTART field. */
4426 #define NFCT_INTENCLR_RXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */
4427 #define NFCT_INTENCLR_RXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */
4428 #define NFCT_INTENCLR_RXFRAMESTART_Clear (1UL) /*!< Disable */
4429 
4430 /* Bit 4 : Write '1' to Disable interrupt for TXFRAMEEND event */
4431 #define NFCT_INTENCLR_TXFRAMEEND_Pos (4UL) /*!< Position of TXFRAMEEND field. */
4432 #define NFCT_INTENCLR_TXFRAMEEND_Msk (0x1UL << NFCT_INTENCLR_TXFRAMEEND_Pos) /*!< Bit mask of TXFRAMEEND field. */
4433 #define NFCT_INTENCLR_TXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */
4434 #define NFCT_INTENCLR_TXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */
4435 #define NFCT_INTENCLR_TXFRAMEEND_Clear (1UL) /*!< Disable */
4436 
4437 /* Bit 3 : Write '1' to Disable interrupt for TXFRAMESTART event */
4438 #define NFCT_INTENCLR_TXFRAMESTART_Pos (3UL) /*!< Position of TXFRAMESTART field. */
4439 #define NFCT_INTENCLR_TXFRAMESTART_Msk (0x1UL << NFCT_INTENCLR_TXFRAMESTART_Pos) /*!< Bit mask of TXFRAMESTART field. */
4440 #define NFCT_INTENCLR_TXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */
4441 #define NFCT_INTENCLR_TXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */
4442 #define NFCT_INTENCLR_TXFRAMESTART_Clear (1UL) /*!< Disable */
4443 
4444 /* Bit 2 : Write '1' to Disable interrupt for FIELDLOST event */
4445 #define NFCT_INTENCLR_FIELDLOST_Pos (2UL) /*!< Position of FIELDLOST field. */
4446 #define NFCT_INTENCLR_FIELDLOST_Msk (0x1UL << NFCT_INTENCLR_FIELDLOST_Pos) /*!< Bit mask of FIELDLOST field. */
4447 #define NFCT_INTENCLR_FIELDLOST_Disabled (0UL) /*!< Read: Disabled */
4448 #define NFCT_INTENCLR_FIELDLOST_Enabled (1UL) /*!< Read: Enabled */
4449 #define NFCT_INTENCLR_FIELDLOST_Clear (1UL) /*!< Disable */
4450 
4451 /* Bit 1 : Write '1' to Disable interrupt for FIELDDETECTED event */
4452 #define NFCT_INTENCLR_FIELDDETECTED_Pos (1UL) /*!< Position of FIELDDETECTED field. */
4453 #define NFCT_INTENCLR_FIELDDETECTED_Msk (0x1UL << NFCT_INTENCLR_FIELDDETECTED_Pos) /*!< Bit mask of FIELDDETECTED field. */
4454 #define NFCT_INTENCLR_FIELDDETECTED_Disabled (0UL) /*!< Read: Disabled */
4455 #define NFCT_INTENCLR_FIELDDETECTED_Enabled (1UL) /*!< Read: Enabled */
4456 #define NFCT_INTENCLR_FIELDDETECTED_Clear (1UL) /*!< Disable */
4457 
4458 /* Bit 0 : Write '1' to Disable interrupt for READY event */
4459 #define NFCT_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */
4460 #define NFCT_INTENCLR_READY_Msk (0x1UL << NFCT_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
4461 #define NFCT_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */
4462 #define NFCT_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */
4463 #define NFCT_INTENCLR_READY_Clear (1UL) /*!< Disable */
4464 
4465 /* Register: NFCT_ERRORSTATUS */
4466 /* Description: NFC Error Status register */
4467 
4468 /* Bit 3 : Field level is too low at min load resistance */
4469 #define NFCT_ERRORSTATUS_NFCFIELDTOOWEAK_Pos (3UL) /*!< Position of NFCFIELDTOOWEAK field. */
4470 #define NFCT_ERRORSTATUS_NFCFIELDTOOWEAK_Msk (0x1UL << NFCT_ERRORSTATUS_NFCFIELDTOOWEAK_Pos) /*!< Bit mask of NFCFIELDTOOWEAK field. */
4471 
4472 /* Bit 2 : Field level is too high at max load resistance */
4473 #define NFCT_ERRORSTATUS_NFCFIELDTOOSTRONG_Pos (2UL) /*!< Position of NFCFIELDTOOSTRONG field. */
4474 #define NFCT_ERRORSTATUS_NFCFIELDTOOSTRONG_Msk (0x1UL << NFCT_ERRORSTATUS_NFCFIELDTOOSTRONG_Pos) /*!< Bit mask of NFCFIELDTOOSTRONG field. */
4475 
4476 /* Bit 0 : No STARTTX task triggered before expiration of the time set in FRAMEDELAYMAX */
4477 #define NFCT_ERRORSTATUS_FRAMEDELAYTIMEOUT_Pos (0UL) /*!< Position of FRAMEDELAYTIMEOUT field. */
4478 #define NFCT_ERRORSTATUS_FRAMEDELAYTIMEOUT_Msk (0x1UL << NFCT_ERRORSTATUS_FRAMEDELAYTIMEOUT_Pos) /*!< Bit mask of FRAMEDELAYTIMEOUT field. */
4479 
4480 /* Register: NFCT_FRAMESTATUS_RX */
4481 /* Description: Result of last incoming frames */
4482 
4483 /* Bit 3 : Overrun detected */
4484 #define NFCT_FRAMESTATUS_RX_OVERRUN_Pos (3UL) /*!< Position of OVERRUN field. */
4485 #define NFCT_FRAMESTATUS_RX_OVERRUN_Msk (0x1UL << NFCT_FRAMESTATUS_RX_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */
4486 #define NFCT_FRAMESTATUS_RX_OVERRUN_NoOverrun (0UL) /*!< No overrun detected */
4487 #define NFCT_FRAMESTATUS_RX_OVERRUN_Overrun (1UL) /*!< Overrun error */
4488 
4489 /* Bit 2 : Parity status of received frame */
4490 #define NFCT_FRAMESTATUS_RX_PARITYSTATUS_Pos (2UL) /*!< Position of PARITYSTATUS field. */
4491 #define NFCT_FRAMESTATUS_RX_PARITYSTATUS_Msk (0x1UL << NFCT_FRAMESTATUS_RX_PARITYSTATUS_Pos) /*!< Bit mask of PARITYSTATUS field. */
4492 #define NFCT_FRAMESTATUS_RX_PARITYSTATUS_ParityOK (0UL) /*!< Frame received with parity OK */
4493 #define NFCT_FRAMESTATUS_RX_PARITYSTATUS_ParityError (1UL) /*!< Frame received with parity error */
4494 
4495 /* Bit 0 : No valid End of Frame detected */
4496 #define NFCT_FRAMESTATUS_RX_CRCERROR_Pos (0UL) /*!< Position of CRCERROR field. */
4497 #define NFCT_FRAMESTATUS_RX_CRCERROR_Msk (0x1UL << NFCT_FRAMESTATUS_RX_CRCERROR_Pos) /*!< Bit mask of CRCERROR field. */
4498 #define NFCT_FRAMESTATUS_RX_CRCERROR_CRCCorrect (0UL) /*!< Valid CRC detected */
4499 #define NFCT_FRAMESTATUS_RX_CRCERROR_CRCError (1UL) /*!< CRC received does not match local check */
4500 
4501 /* Register: NFCT_CURRENTLOADCTRL */
4502 /* Description: Current value driven to the NFC Load Control */
4503 
4504 /* Bits 5..0 : Current value driven to the NFC Load Control */
4505 #define NFCT_CURRENTLOADCTRL_CURRENTLOADCTRL_Pos (0UL) /*!< Position of CURRENTLOADCTRL field. */
4506 #define NFCT_CURRENTLOADCTRL_CURRENTLOADCTRL_Msk (0x3FUL << NFCT_CURRENTLOADCTRL_CURRENTLOADCTRL_Pos) /*!< Bit mask of CURRENTLOADCTRL field. */
4507 
4508 /* Register: NFCT_FIELDPRESENT */
4509 /* Description: Indicates the presence or not of a valid field */
4510 
4511 /* Bit 1 : Indicates if the low level has locked to the field */
4512 #define NFCT_FIELDPRESENT_LOCKDETECT_Pos (1UL) /*!< Position of LOCKDETECT field. */
4513 #define NFCT_FIELDPRESENT_LOCKDETECT_Msk (0x1UL << NFCT_FIELDPRESENT_LOCKDETECT_Pos) /*!< Bit mask of LOCKDETECT field. */
4514 #define NFCT_FIELDPRESENT_LOCKDETECT_NotLocked (0UL) /*!< Not locked to field */
4515 #define NFCT_FIELDPRESENT_LOCKDETECT_Locked (1UL) /*!< Locked to field */
4516 
4517 /* Bit 0 : Indicates the presence or not of a valid field. Available only in the activated state. */
4518 #define NFCT_FIELDPRESENT_FIELDPRESENT_Pos (0UL) /*!< Position of FIELDPRESENT field. */
4519 #define NFCT_FIELDPRESENT_FIELDPRESENT_Msk (0x1UL << NFCT_FIELDPRESENT_FIELDPRESENT_Pos) /*!< Bit mask of FIELDPRESENT field. */
4520 #define NFCT_FIELDPRESENT_FIELDPRESENT_NoField (0UL) /*!< No valid field detected */
4521 #define NFCT_FIELDPRESENT_FIELDPRESENT_FieldPresent (1UL) /*!< Valid field detected */
4522 
4523 /* Register: NFCT_FRAMEDELAYMIN */
4524 /* Description: Minimum frame delay */
4525 
4526 /* Bits 15..0 : Minimum frame delay in number of 13.56 MHz clocks */
4527 #define NFCT_FRAMEDELAYMIN_FRAMEDELAYMIN_Pos (0UL) /*!< Position of FRAMEDELAYMIN field. */
4528 #define NFCT_FRAMEDELAYMIN_FRAMEDELAYMIN_Msk (0xFFFFUL << NFCT_FRAMEDELAYMIN_FRAMEDELAYMIN_Pos) /*!< Bit mask of FRAMEDELAYMIN field. */
4529 
4530 /* Register: NFCT_FRAMEDELAYMAX */
4531 /* Description: Maximum frame delay */
4532 
4533 /* Bits 15..0 : Maximum frame delay in number of 13.56 MHz clocks */
4534 #define NFCT_FRAMEDELAYMAX_FRAMEDELAYMAX_Pos (0UL) /*!< Position of FRAMEDELAYMAX field. */
4535 #define NFCT_FRAMEDELAYMAX_FRAMEDELAYMAX_Msk (0xFFFFUL << NFCT_FRAMEDELAYMAX_FRAMEDELAYMAX_Pos) /*!< Bit mask of FRAMEDELAYMAX field. */
4536 
4537 /* Register: NFCT_FRAMEDELAYMODE */
4538 /* Description: Configuration register for the Frame Delay Timer */
4539 
4540 /* Bits 1..0 : Configuration register for the Frame Delay Timer */
4541 #define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Pos (0UL) /*!< Position of FRAMEDELAYMODE field. */
4542 #define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Msk (0x3UL << NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Pos) /*!< Bit mask of FRAMEDELAYMODE field. */
4543 #define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_FreeRun (0UL) /*!< Transmission is independent of frame timer and will start when the STARTTX task is triggered. No timeout. */
4544 #define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Window (1UL) /*!< Frame is transmitted between FRAMEDELAYMIN and FRAMEDELAYMAX */
4545 #define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_ExactVal (2UL) /*!< Frame is transmitted exactly at FRAMEDELAYMAX */
4546 #define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_WindowGrid (3UL) /*!< Frame is transmitted on a bit grid between FRAMEDELAYMIN and FRAMEDELAYMAX */
4547 
4548 /* Register: NFCT_PACKETPTR */
4549 /* Description: Packet pointer for TXD and RXD data storage in Data RAM */
4550 
4551 /* Bits 31..0 : Packet pointer for TXD and RXD data storage in Data RAM. This address is a byte aligned RAM address. */
4552 #define NFCT_PACKETPTR_PTR_Pos (0UL) /*!< Position of PTR field. */
4553 #define NFCT_PACKETPTR_PTR_Msk (0xFFFFFFFFUL << NFCT_PACKETPTR_PTR_Pos) /*!< Bit mask of PTR field. */
4554 
4555 /* Register: NFCT_MAXLEN */
4556 /* Description: Size of allocated for TXD and RXD data storage buffer in Data RAM */
4557 
4558 /* Bits 8..0 : Size of allocated for TXD and RXD data storage buffer in Data RAM */
4559 #define NFCT_MAXLEN_MAXLEN_Pos (0UL) /*!< Position of MAXLEN field. */
4560 #define NFCT_MAXLEN_MAXLEN_Msk (0x1FFUL << NFCT_MAXLEN_MAXLEN_Pos) /*!< Bit mask of MAXLEN field. */
4561 
4562 /* Register: NFCT_TXD_FRAMECONFIG */
4563 /* Description: Configuration of outgoing frames */
4564 
4565 /* Bit 4 : CRC mode for outgoing frames */
4566 #define NFCT_TXD_FRAMECONFIG_CRCMODETX_Pos (4UL) /*!< Position of CRCMODETX field. */
4567 #define NFCT_TXD_FRAMECONFIG_CRCMODETX_Msk (0x1UL << NFCT_TXD_FRAMECONFIG_CRCMODETX_Pos) /*!< Bit mask of CRCMODETX field. */
4568 #define NFCT_TXD_FRAMECONFIG_CRCMODETX_NoCRCTX (0UL) /*!< CRC is not added to the frame */
4569 #define NFCT_TXD_FRAMECONFIG_CRCMODETX_CRC16TX (1UL) /*!< 16 bit CRC added to the frame based on all the data read from RAM that is used in the frame */
4570 
4571 /* Bit 2 : Adding SoF or not in TX frames */
4572 #define NFCT_TXD_FRAMECONFIG_SOF_Pos (2UL) /*!< Position of SOF field. */
4573 #define NFCT_TXD_FRAMECONFIG_SOF_Msk (0x1UL << NFCT_TXD_FRAMECONFIG_SOF_Pos) /*!< Bit mask of SOF field. */
4574 #define NFCT_TXD_FRAMECONFIG_SOF_NoSoF (0UL) /*!< Start of Frame symbol not added */
4575 #define NFCT_TXD_FRAMECONFIG_SOF_SoF (1UL) /*!< Start of Frame symbol added */
4576 
4577 /* Bit 1 : Discarding unused bits in start or at end of a Frame */
4578 #define NFCT_TXD_FRAMECONFIG_DISCARDMODE_Pos (1UL) /*!< Position of DISCARDMODE field. */
4579 #define NFCT_TXD_FRAMECONFIG_DISCARDMODE_Msk (0x1UL << NFCT_TXD_FRAMECONFIG_DISCARDMODE_Pos) /*!< Bit mask of DISCARDMODE field. */
4580 #define NFCT_TXD_FRAMECONFIG_DISCARDMODE_DiscardEnd (0UL) /*!< Unused bits is discarded at end of frame */
4581 #define NFCT_TXD_FRAMECONFIG_DISCARDMODE_DiscardStart (1UL) /*!< Unused bits is discarded at start of frame */
4582 
4583 /* Bit 0 : Adding parity or not in the frame */
4584 #define NFCT_TXD_FRAMECONFIG_PARITY_Pos (0UL) /*!< Position of PARITY field. */
4585 #define NFCT_TXD_FRAMECONFIG_PARITY_Msk (0x1UL << NFCT_TXD_FRAMECONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */
4586 #define NFCT_TXD_FRAMECONFIG_PARITY_NoParity (0UL) /*!< Parity is not added in TX frames */
4587 #define NFCT_TXD_FRAMECONFIG_PARITY_Parity (1UL) /*!< Parity is added TX frames */
4588 
4589 /* Register: NFCT_TXD_AMOUNT */
4590 /* Description: Size of outgoing frame */
4591 
4592 /* Bits 11..3 : Number of complete bytes that shall be included in the frame, excluding CRC, parity and framing */
4593 #define NFCT_TXD_AMOUNT_TXDATABYTES_Pos (3UL) /*!< Position of TXDATABYTES field. */
4594 #define NFCT_TXD_AMOUNT_TXDATABYTES_Msk (0x1FFUL << NFCT_TXD_AMOUNT_TXDATABYTES_Pos) /*!< Bit mask of TXDATABYTES field. */
4595 
4596 /* Bits 2..0 : Number of bits in the last or first byte read from RAM that shall be included in the frame (excluding parity bit). */
4597 #define NFCT_TXD_AMOUNT_TXDATABITS_Pos (0UL) /*!< Position of TXDATABITS field. */
4598 #define NFCT_TXD_AMOUNT_TXDATABITS_Msk (0x7UL << NFCT_TXD_AMOUNT_TXDATABITS_Pos) /*!< Bit mask of TXDATABITS field. */
4599 
4600 /* Register: NFCT_RXD_FRAMECONFIG */
4601 /* Description: Configuration of incoming frames */
4602 
4603 /* Bit 4 : CRC mode for incoming frames */
4604 #define NFCT_RXD_FRAMECONFIG_CRCMODERX_Pos (4UL) /*!< Position of CRCMODERX field. */
4605 #define NFCT_RXD_FRAMECONFIG_CRCMODERX_Msk (0x1UL << NFCT_RXD_FRAMECONFIG_CRCMODERX_Pos) /*!< Bit mask of CRCMODERX field. */
4606 #define NFCT_RXD_FRAMECONFIG_CRCMODERX_NoCRCRX (0UL) /*!< CRC is not expected in RX frames */
4607 #define NFCT_RXD_FRAMECONFIG_CRCMODERX_CRC16RX (1UL) /*!< Last 16 bits in RX frame is CRC, CRC is checked and CRCSTATUS updated */
4608 
4609 /* Bit 2 : SoF expected or not in RX frames */
4610 #define NFCT_RXD_FRAMECONFIG_SOF_Pos (2UL) /*!< Position of SOF field. */
4611 #define NFCT_RXD_FRAMECONFIG_SOF_Msk (0x1UL << NFCT_RXD_FRAMECONFIG_SOF_Pos) /*!< Bit mask of SOF field. */
4612 #define NFCT_RXD_FRAMECONFIG_SOF_NoSoF (0UL) /*!< Start of Frame symbol is not expected in RX frames */
4613 #define NFCT_RXD_FRAMECONFIG_SOF_SoF (1UL) /*!< Start of Frame symbol is expected in RX frames */
4614 
4615 /* Bit 0 : Parity expected or not in RX frame */
4616 #define NFCT_RXD_FRAMECONFIG_PARITY_Pos (0UL) /*!< Position of PARITY field. */
4617 #define NFCT_RXD_FRAMECONFIG_PARITY_Msk (0x1UL << NFCT_RXD_FRAMECONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */
4618 #define NFCT_RXD_FRAMECONFIG_PARITY_NoParity (0UL) /*!< Parity is not expected in RX frames */
4619 #define NFCT_RXD_FRAMECONFIG_PARITY_Parity (1UL) /*!< Parity is expected in RX frames */
4620 
4621 /* Register: NFCT_RXD_AMOUNT */
4622 /* Description: Size of last incoming frame */
4623 
4624 /* Bits 11..3 : Number of complete bytes received in the frame (including CRC, but excluding parity and SoF/EoF framing) */
4625 #define NFCT_RXD_AMOUNT_RXDATABYTES_Pos (3UL) /*!< Position of RXDATABYTES field. */
4626 #define NFCT_RXD_AMOUNT_RXDATABYTES_Msk (0x1FFUL << NFCT_RXD_AMOUNT_RXDATABYTES_Pos) /*!< Bit mask of RXDATABYTES field. */
4627 
4628 /* Bits 2..0 : Number of bits in the last byte in the frame, if less than 8 (including CRC, but excluding parity and SoF/EoF framing). */
4629 #define NFCT_RXD_AMOUNT_RXDATABITS_Pos (0UL) /*!< Position of RXDATABITS field. */
4630 #define NFCT_RXD_AMOUNT_RXDATABITS_Msk (0x7UL << NFCT_RXD_AMOUNT_RXDATABITS_Pos) /*!< Bit mask of RXDATABITS field. */
4631 
4632 /* Register: NFCT_NFCID1_LAST */
4633 /* Description: Last NFCID1 part (4, 7 or 10 bytes ID) */
4634 
4635 /* Bits 31..24 : NFCID1 byte W */
4636 #define NFCT_NFCID1_LAST_NFCID1_W_Pos (24UL) /*!< Position of NFCID1_W field. */
4637 #define NFCT_NFCID1_LAST_NFCID1_W_Msk (0xFFUL << NFCT_NFCID1_LAST_NFCID1_W_Pos) /*!< Bit mask of NFCID1_W field. */
4638 
4639 /* Bits 23..16 : NFCID1 byte X */
4640 #define NFCT_NFCID1_LAST_NFCID1_X_Pos (16UL) /*!< Position of NFCID1_X field. */
4641 #define NFCT_NFCID1_LAST_NFCID1_X_Msk (0xFFUL << NFCT_NFCID1_LAST_NFCID1_X_Pos) /*!< Bit mask of NFCID1_X field. */
4642 
4643 /* Bits 15..8 : NFCID1 byte Y */
4644 #define NFCT_NFCID1_LAST_NFCID1_Y_Pos (8UL) /*!< Position of NFCID1_Y field. */
4645 #define NFCT_NFCID1_LAST_NFCID1_Y_Msk (0xFFUL << NFCT_NFCID1_LAST_NFCID1_Y_Pos) /*!< Bit mask of NFCID1_Y field. */
4646 
4647 /* Bits 7..0 : NFCID1 byte Z (very last byte sent) */
4648 #define NFCT_NFCID1_LAST_NFCID1_Z_Pos (0UL) /*!< Position of NFCID1_Z field. */
4649 #define NFCT_NFCID1_LAST_NFCID1_Z_Msk (0xFFUL << NFCT_NFCID1_LAST_NFCID1_Z_Pos) /*!< Bit mask of NFCID1_Z field. */
4650 
4651 /* Register: NFCT_NFCID1_2ND_LAST */
4652 /* Description: Second last NFCID1 part (7 or 10 bytes ID) */
4653 
4654 /* Bits 23..16 : NFCID1 byte T */
4655 #define NFCT_NFCID1_2ND_LAST_NFCID1_T_Pos (16UL) /*!< Position of NFCID1_T field. */
4656 #define NFCT_NFCID1_2ND_LAST_NFCID1_T_Msk (0xFFUL << NFCT_NFCID1_2ND_LAST_NFCID1_T_Pos) /*!< Bit mask of NFCID1_T field. */
4657 
4658 /* Bits 15..8 : NFCID1 byte U */
4659 #define NFCT_NFCID1_2ND_LAST_NFCID1_U_Pos (8UL) /*!< Position of NFCID1_U field. */
4660 #define NFCT_NFCID1_2ND_LAST_NFCID1_U_Msk (0xFFUL << NFCT_NFCID1_2ND_LAST_NFCID1_U_Pos) /*!< Bit mask of NFCID1_U field. */
4661 
4662 /* Bits 7..0 : NFCID1 byte V */
4663 #define NFCT_NFCID1_2ND_LAST_NFCID1_V_Pos (0UL) /*!< Position of NFCID1_V field. */
4664 #define NFCT_NFCID1_2ND_LAST_NFCID1_V_Msk (0xFFUL << NFCT_NFCID1_2ND_LAST_NFCID1_V_Pos) /*!< Bit mask of NFCID1_V field. */
4665 
4666 /* Register: NFCT_NFCID1_3RD_LAST */
4667 /* Description: Third last NFCID1 part (10 bytes ID) */
4668 
4669 /* Bits 23..16 : NFCID1 byte Q */
4670 #define NFCT_NFCID1_3RD_LAST_NFCID1_Q_Pos (16UL) /*!< Position of NFCID1_Q field. */
4671 #define NFCT_NFCID1_3RD_LAST_NFCID1_Q_Msk (0xFFUL << NFCT_NFCID1_3RD_LAST_NFCID1_Q_Pos) /*!< Bit mask of NFCID1_Q field. */
4672 
4673 /* Bits 15..8 : NFCID1 byte R */
4674 #define NFCT_NFCID1_3RD_LAST_NFCID1_R_Pos (8UL) /*!< Position of NFCID1_R field. */
4675 #define NFCT_NFCID1_3RD_LAST_NFCID1_R_Msk (0xFFUL << NFCT_NFCID1_3RD_LAST_NFCID1_R_Pos) /*!< Bit mask of NFCID1_R field. */
4676 
4677 /* Bits 7..0 : NFCID1 byte S */
4678 #define NFCT_NFCID1_3RD_LAST_NFCID1_S_Pos (0UL) /*!< Position of NFCID1_S field. */
4679 #define NFCT_NFCID1_3RD_LAST_NFCID1_S_Msk (0xFFUL << NFCT_NFCID1_3RD_LAST_NFCID1_S_Pos) /*!< Bit mask of NFCID1_S field. */
4680 
4681 /* Register: NFCT_SENSRES */
4682 /* Description: NFC-A SENS_RES auto-response settings */
4683 
4684 /* Bits 15..12 : Reserved for future use. Shall be 0. */
4685 #define NFCT_SENSRES_RFU74_Pos (12UL) /*!< Position of RFU74 field. */
4686 #define NFCT_SENSRES_RFU74_Msk (0xFUL << NFCT_SENSRES_RFU74_Pos) /*!< Bit mask of RFU74 field. */
4687 
4688 /* Bits 11..8 : Tag platform configuration as defined by the b4:b1 of byte 2 in SENS_RES response in the NFC Forum, NFC Digital Protocol Technical Specification */
4689 #define NFCT_SENSRES_PLATFCONFIG_Pos (8UL) /*!< Position of PLATFCONFIG field. */
4690 #define NFCT_SENSRES_PLATFCONFIG_Msk (0xFUL << NFCT_SENSRES_PLATFCONFIG_Pos) /*!< Bit mask of PLATFCONFIG field. */
4691 
4692 /* Bits 7..6 : NFCID1 size. This value is used by the Auto collision resolution engine. */
4693 #define NFCT_SENSRES_NFCIDSIZE_Pos (6UL) /*!< Position of NFCIDSIZE field. */
4694 #define NFCT_SENSRES_NFCIDSIZE_Msk (0x3UL << NFCT_SENSRES_NFCIDSIZE_Pos) /*!< Bit mask of NFCIDSIZE field. */
4695 #define NFCT_SENSRES_NFCIDSIZE_NFCID1Single (0UL) /*!< NFCID1 size: single (4 bytes) */
4696 #define NFCT_SENSRES_NFCIDSIZE_NFCID1Double (1UL) /*!< NFCID1 size: double (7 bytes) */
4697 #define NFCT_SENSRES_NFCIDSIZE_NFCID1Triple (2UL) /*!< NFCID1 size: triple (10 bytes) */
4698 
4699 /* Bit 5 : Reserved for future use. Shall be 0. */
4700 #define NFCT_SENSRES_RFU5_Pos (5UL) /*!< Position of RFU5 field. */
4701 #define NFCT_SENSRES_RFU5_Msk (0x1UL << NFCT_SENSRES_RFU5_Pos) /*!< Bit mask of RFU5 field. */
4702 
4703 /* Bits 4..0 : Bit frame SDD as defined by the b5:b1 of byte 1 in SENS_RES response in the NFC Forum, NFC Digital Protocol Technical Specification */
4704 #define NFCT_SENSRES_BITFRAMESDD_Pos (0UL) /*!< Position of BITFRAMESDD field. */
4705 #define NFCT_SENSRES_BITFRAMESDD_Msk (0x1FUL << NFCT_SENSRES_BITFRAMESDD_Pos) /*!< Bit mask of BITFRAMESDD field. */
4706 #define NFCT_SENSRES_BITFRAMESDD_SDD00000 (0UL) /*!< SDD pattern 00000 */
4707 #define NFCT_SENSRES_BITFRAMESDD_SDD00001 (1UL) /*!< SDD pattern 00001 */
4708 #define NFCT_SENSRES_BITFRAMESDD_SDD00010 (2UL) /*!< SDD pattern 00010 */
4709 #define NFCT_SENSRES_BITFRAMESDD_SDD00100 (4UL) /*!< SDD pattern 00100 */
4710 #define NFCT_SENSRES_BITFRAMESDD_SDD01000 (8UL) /*!< SDD pattern 01000 */
4711 #define NFCT_SENSRES_BITFRAMESDD_SDD10000 (16UL) /*!< SDD pattern 10000 */
4712 
4713 /* Register: NFCT_SELRES */
4714 /* Description: NFC-A SEL_RES auto-response settings */
4715 
4716 /* Bit 7 : Reserved for future use. Shall be 0. */
4717 #define NFCT_SELRES_RFU7_Pos (7UL) /*!< Position of RFU7 field. */
4718 #define NFCT_SELRES_RFU7_Msk (0x1UL << NFCT_SELRES_RFU7_Pos) /*!< Bit mask of RFU7 field. */
4719 
4720 /* Bits 6..5 : Protocol as defined by the b7:b6 of SEL_RES response in the NFC Forum, NFC Digital Protocol Technical Specification */
4721 #define NFCT_SELRES_PROTOCOL_Pos (5UL) /*!< Position of PROTOCOL field. */
4722 #define NFCT_SELRES_PROTOCOL_Msk (0x3UL << NFCT_SELRES_PROTOCOL_Pos) /*!< Bit mask of PROTOCOL field. */
4723 
4724 /* Bits 4..3 : Reserved for future use. Shall be 0. */
4725 #define NFCT_SELRES_RFU43_Pos (3UL) /*!< Position of RFU43 field. */
4726 #define NFCT_SELRES_RFU43_Msk (0x3UL << NFCT_SELRES_RFU43_Pos) /*!< Bit mask of RFU43 field. */
4727 
4728 /* Bit 2 : Cascade bit (controlled by hardware, write has no effect) */
4729 #define NFCT_SELRES_CASCADE_Pos (2UL) /*!< Position of CASCADE field. */
4730 #define NFCT_SELRES_CASCADE_Msk (0x1UL << NFCT_SELRES_CASCADE_Pos) /*!< Bit mask of CASCADE field. */
4731 #define NFCT_SELRES_CASCADE_Complete (0UL) /*!< NFCID1 complete */
4732 #define NFCT_SELRES_CASCADE_NotComplete (1UL) /*!< NFCID1 not complete */
4733 
4734 /* Bits 1..0 : Reserved for future use. Shall be 0. */
4735 #define NFCT_SELRES_RFU10_Pos (0UL) /*!< Position of RFU10 field. */
4736 #define NFCT_SELRES_RFU10_Msk (0x3UL << NFCT_SELRES_RFU10_Pos) /*!< Bit mask of RFU10 field. */
4737 
4738 
4739 /* Peripheral: NVMC */
4740 /* Description: Non Volatile Memory Controller */
4741 
4742 /* Register: NVMC_READY */
4743 /* Description: Ready flag */
4744 
4745 /* Bit 0 : NVMC is ready or busy */
4746 #define NVMC_READY_READY_Pos (0UL) /*!< Position of READY field. */
4747 #define NVMC_READY_READY_Msk (0x1UL << NVMC_READY_READY_Pos) /*!< Bit mask of READY field. */
4748 #define NVMC_READY_READY_Busy (0UL) /*!< NVMC is busy (on-going write or erase operation) */
4749 #define NVMC_READY_READY_Ready (1UL) /*!< NVMC is ready */
4750 
4751 /* Register: NVMC_CONFIG */
4752 /* Description: Configuration register */
4753 
4754 /* Bits 1..0 : Program memory access mode. It is strongly recommended to only activate erase and write modes when they are actively used. Enabling write or erase will invalidate the cache and keep it invalidated. */
4755 #define NVMC_CONFIG_WEN_Pos (0UL) /*!< Position of WEN field. */
4756 #define NVMC_CONFIG_WEN_Msk (0x3UL << NVMC_CONFIG_WEN_Pos) /*!< Bit mask of WEN field. */
4757 #define NVMC_CONFIG_WEN_Ren (0UL) /*!< Read only access */
4758 #define NVMC_CONFIG_WEN_Wen (1UL) /*!< Write Enabled */
4759 #define NVMC_CONFIG_WEN_Een (2UL) /*!< Erase enabled */
4760 
4761 /* Register: NVMC_ERASEPAGE */
4762 /* Description: Register for erasing a page in Code area */
4763 
4764 /* Bits 31..0 : Register for starting erase of a page in Code area */
4765 #define NVMC_ERASEPAGE_ERASEPAGE_Pos (0UL) /*!< Position of ERASEPAGE field. */
4766 #define NVMC_ERASEPAGE_ERASEPAGE_Msk (0xFFFFFFFFUL << NVMC_ERASEPAGE_ERASEPAGE_Pos) /*!< Bit mask of ERASEPAGE field. */
4767 
4768 /* Register: NVMC_ERASEPCR1 */
4769 /* Description: Deprecated register -  Register for erasing a page in Code area. Equivalent to ERASEPAGE. */
4770 
4771 /* Bits 31..0 : Register for erasing a page in Code area. Equivalent to ERASEPAGE. */
4772 #define NVMC_ERASEPCR1_ERASEPCR1_Pos (0UL) /*!< Position of ERASEPCR1 field. */
4773 #define NVMC_ERASEPCR1_ERASEPCR1_Msk (0xFFFFFFFFUL << NVMC_ERASEPCR1_ERASEPCR1_Pos) /*!< Bit mask of ERASEPCR1 field. */
4774 
4775 /* Register: NVMC_ERASEALL */
4776 /* Description: Register for erasing all non-volatile user memory */
4777 
4778 /* Bit 0 : Erase all non-volatile memory including UICR registers. Note that code erase has to be enabled by CONFIG.EEN before the UICR can be erased. */
4779 #define NVMC_ERASEALL_ERASEALL_Pos (0UL) /*!< Position of ERASEALL field. */
4780 #define NVMC_ERASEALL_ERASEALL_Msk (0x1UL << NVMC_ERASEALL_ERASEALL_Pos) /*!< Bit mask of ERASEALL field. */
4781 #define NVMC_ERASEALL_ERASEALL_NoOperation (0UL) /*!< No operation */
4782 #define NVMC_ERASEALL_ERASEALL_Erase (1UL) /*!< Start chip erase */
4783 
4784 /* Register: NVMC_ERASEPCR0 */
4785 /* Description: Deprecated register -  Register for erasing a page in Code area. Equivalent to ERASEPAGE. */
4786 
4787 /* Bits 31..0 : Register for starting erase of a page in Code area. Equivalent to ERASEPAGE. */
4788 #define NVMC_ERASEPCR0_ERASEPCR0_Pos (0UL) /*!< Position of ERASEPCR0 field. */
4789 #define NVMC_ERASEPCR0_ERASEPCR0_Msk (0xFFFFFFFFUL << NVMC_ERASEPCR0_ERASEPCR0_Pos) /*!< Bit mask of ERASEPCR0 field. */
4790 
4791 /* Register: NVMC_ERASEUICR */
4792 /* Description: Register for erasing User Information Configuration Registers */
4793 
4794 /* Bit 0 : Register starting erase of all User Information Configuration Registers. Note that code erase has to be enabled by CONFIG.EEN before the UICR can be erased. */
4795 #define NVMC_ERASEUICR_ERASEUICR_Pos (0UL) /*!< Position of ERASEUICR field. */
4796 #define NVMC_ERASEUICR_ERASEUICR_Msk (0x1UL << NVMC_ERASEUICR_ERASEUICR_Pos) /*!< Bit mask of ERASEUICR field. */
4797 #define NVMC_ERASEUICR_ERASEUICR_NoOperation (0UL) /*!< No operation */
4798 #define NVMC_ERASEUICR_ERASEUICR_Erase (1UL) /*!< Start erase of UICR */
4799 
4800 /* Register: NVMC_ICACHECNF */
4801 /* Description: I-Code cache configuration register. */
4802 
4803 /* Bit 8 : Cache profiling enable */
4804 #define NVMC_ICACHECNF_CACHEPROFEN_Pos (8UL) /*!< Position of CACHEPROFEN field. */
4805 #define NVMC_ICACHECNF_CACHEPROFEN_Msk (0x1UL << NVMC_ICACHECNF_CACHEPROFEN_Pos) /*!< Bit mask of CACHEPROFEN field. */
4806 #define NVMC_ICACHECNF_CACHEPROFEN_Disabled (0UL) /*!< Disable cache profiling */
4807 #define NVMC_ICACHECNF_CACHEPROFEN_Enabled (1UL) /*!< Enable cache profiling */
4808 
4809 /* Bit 0 : Cache enable */
4810 #define NVMC_ICACHECNF_CACHEEN_Pos (0UL) /*!< Position of CACHEEN field. */
4811 #define NVMC_ICACHECNF_CACHEEN_Msk (0x1UL << NVMC_ICACHECNF_CACHEEN_Pos) /*!< Bit mask of CACHEEN field. */
4812 #define NVMC_ICACHECNF_CACHEEN_Disabled (0UL) /*!< Disable cache. Invalidates all cache entries. */
4813 #define NVMC_ICACHECNF_CACHEEN_Enabled (1UL) /*!< Enable cache */
4814 
4815 /* Register: NVMC_IHIT */
4816 /* Description: I-Code cache hit counter. */
4817 
4818 /* Bits 31..0 : Number of cache hits */
4819 #define NVMC_IHIT_HITS_Pos (0UL) /*!< Position of HITS field. */
4820 #define NVMC_IHIT_HITS_Msk (0xFFFFFFFFUL << NVMC_IHIT_HITS_Pos) /*!< Bit mask of HITS field. */
4821 
4822 /* Register: NVMC_IMISS */
4823 /* Description: I-Code cache miss counter. */
4824 
4825 /* Bits 31..0 : Number of cache misses */
4826 #define NVMC_IMISS_MISSES_Pos (0UL) /*!< Position of MISSES field. */
4827 #define NVMC_IMISS_MISSES_Msk (0xFFFFFFFFUL << NVMC_IMISS_MISSES_Pos) /*!< Bit mask of MISSES field. */
4828 
4829 
4830 /* Peripheral: GPIO */
4831 /* Description: GPIO Port 1 */
4832 
4833 /* Register: GPIO_OUT */
4834 /* Description: Write GPIO port */
4835 
4836 /* Bit 31 : Pin 31 */
4837 #define GPIO_OUT_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
4838 #define GPIO_OUT_PIN31_Msk (0x1UL << GPIO_OUT_PIN31_Pos) /*!< Bit mask of PIN31 field. */
4839 #define GPIO_OUT_PIN31_Low (0UL) /*!< Pin driver is low */
4840 #define GPIO_OUT_PIN31_High (1UL) /*!< Pin driver is high */
4841 
4842 /* Bit 30 : Pin 30 */
4843 #define GPIO_OUT_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
4844 #define GPIO_OUT_PIN30_Msk (0x1UL << GPIO_OUT_PIN30_Pos) /*!< Bit mask of PIN30 field. */
4845 #define GPIO_OUT_PIN30_Low (0UL) /*!< Pin driver is low */
4846 #define GPIO_OUT_PIN30_High (1UL) /*!< Pin driver is high */
4847 
4848 /* Bit 29 : Pin 29 */
4849 #define GPIO_OUT_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
4850 #define GPIO_OUT_PIN29_Msk (0x1UL << GPIO_OUT_PIN29_Pos) /*!< Bit mask of PIN29 field. */
4851 #define GPIO_OUT_PIN29_Low (0UL) /*!< Pin driver is low */
4852 #define GPIO_OUT_PIN29_High (1UL) /*!< Pin driver is high */
4853 
4854 /* Bit 28 : Pin 28 */
4855 #define GPIO_OUT_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
4856 #define GPIO_OUT_PIN28_Msk (0x1UL << GPIO_OUT_PIN28_Pos) /*!< Bit mask of PIN28 field. */
4857 #define GPIO_OUT_PIN28_Low (0UL) /*!< Pin driver is low */
4858 #define GPIO_OUT_PIN28_High (1UL) /*!< Pin driver is high */
4859 
4860 /* Bit 27 : Pin 27 */
4861 #define GPIO_OUT_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
4862 #define GPIO_OUT_PIN27_Msk (0x1UL << GPIO_OUT_PIN27_Pos) /*!< Bit mask of PIN27 field. */
4863 #define GPIO_OUT_PIN27_Low (0UL) /*!< Pin driver is low */
4864 #define GPIO_OUT_PIN27_High (1UL) /*!< Pin driver is high */
4865 
4866 /* Bit 26 : Pin 26 */
4867 #define GPIO_OUT_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
4868 #define GPIO_OUT_PIN26_Msk (0x1UL << GPIO_OUT_PIN26_Pos) /*!< Bit mask of PIN26 field. */
4869 #define GPIO_OUT_PIN26_Low (0UL) /*!< Pin driver is low */
4870 #define GPIO_OUT_PIN26_High (1UL) /*!< Pin driver is high */
4871 
4872 /* Bit 25 : Pin 25 */
4873 #define GPIO_OUT_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
4874 #define GPIO_OUT_PIN25_Msk (0x1UL << GPIO_OUT_PIN25_Pos) /*!< Bit mask of PIN25 field. */
4875 #define GPIO_OUT_PIN25_Low (0UL) /*!< Pin driver is low */
4876 #define GPIO_OUT_PIN25_High (1UL) /*!< Pin driver is high */
4877 
4878 /* Bit 24 : Pin 24 */
4879 #define GPIO_OUT_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
4880 #define GPIO_OUT_PIN24_Msk (0x1UL << GPIO_OUT_PIN24_Pos) /*!< Bit mask of PIN24 field. */
4881 #define GPIO_OUT_PIN24_Low (0UL) /*!< Pin driver is low */
4882 #define GPIO_OUT_PIN24_High (1UL) /*!< Pin driver is high */
4883 
4884 /* Bit 23 : Pin 23 */
4885 #define GPIO_OUT_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
4886 #define GPIO_OUT_PIN23_Msk (0x1UL << GPIO_OUT_PIN23_Pos) /*!< Bit mask of PIN23 field. */
4887 #define GPIO_OUT_PIN23_Low (0UL) /*!< Pin driver is low */
4888 #define GPIO_OUT_PIN23_High (1UL) /*!< Pin driver is high */
4889 
4890 /* Bit 22 : Pin 22 */
4891 #define GPIO_OUT_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
4892 #define GPIO_OUT_PIN22_Msk (0x1UL << GPIO_OUT_PIN22_Pos) /*!< Bit mask of PIN22 field. */
4893 #define GPIO_OUT_PIN22_Low (0UL) /*!< Pin driver is low */
4894 #define GPIO_OUT_PIN22_High (1UL) /*!< Pin driver is high */
4895 
4896 /* Bit 21 : Pin 21 */
4897 #define GPIO_OUT_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
4898 #define GPIO_OUT_PIN21_Msk (0x1UL << GPIO_OUT_PIN21_Pos) /*!< Bit mask of PIN21 field. */
4899 #define GPIO_OUT_PIN21_Low (0UL) /*!< Pin driver is low */
4900 #define GPIO_OUT_PIN21_High (1UL) /*!< Pin driver is high */
4901 
4902 /* Bit 20 : Pin 20 */
4903 #define GPIO_OUT_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
4904 #define GPIO_OUT_PIN20_Msk (0x1UL << GPIO_OUT_PIN20_Pos) /*!< Bit mask of PIN20 field. */
4905 #define GPIO_OUT_PIN20_Low (0UL) /*!< Pin driver is low */
4906 #define GPIO_OUT_PIN20_High (1UL) /*!< Pin driver is high */
4907 
4908 /* Bit 19 : Pin 19 */
4909 #define GPIO_OUT_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
4910 #define GPIO_OUT_PIN19_Msk (0x1UL << GPIO_OUT_PIN19_Pos) /*!< Bit mask of PIN19 field. */
4911 #define GPIO_OUT_PIN19_Low (0UL) /*!< Pin driver is low */
4912 #define GPIO_OUT_PIN19_High (1UL) /*!< Pin driver is high */
4913 
4914 /* Bit 18 : Pin 18 */
4915 #define GPIO_OUT_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
4916 #define GPIO_OUT_PIN18_Msk (0x1UL << GPIO_OUT_PIN18_Pos) /*!< Bit mask of PIN18 field. */
4917 #define GPIO_OUT_PIN18_Low (0UL) /*!< Pin driver is low */
4918 #define GPIO_OUT_PIN18_High (1UL) /*!< Pin driver is high */
4919 
4920 /* Bit 17 : Pin 17 */
4921 #define GPIO_OUT_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
4922 #define GPIO_OUT_PIN17_Msk (0x1UL << GPIO_OUT_PIN17_Pos) /*!< Bit mask of PIN17 field. */
4923 #define GPIO_OUT_PIN17_Low (0UL) /*!< Pin driver is low */
4924 #define GPIO_OUT_PIN17_High (1UL) /*!< Pin driver is high */
4925 
4926 /* Bit 16 : Pin 16 */
4927 #define GPIO_OUT_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
4928 #define GPIO_OUT_PIN16_Msk (0x1UL << GPIO_OUT_PIN16_Pos) /*!< Bit mask of PIN16 field. */
4929 #define GPIO_OUT_PIN16_Low (0UL) /*!< Pin driver is low */
4930 #define GPIO_OUT_PIN16_High (1UL) /*!< Pin driver is high */
4931 
4932 /* Bit 15 : Pin 15 */
4933 #define GPIO_OUT_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
4934 #define GPIO_OUT_PIN15_Msk (0x1UL << GPIO_OUT_PIN15_Pos) /*!< Bit mask of PIN15 field. */
4935 #define GPIO_OUT_PIN15_Low (0UL) /*!< Pin driver is low */
4936 #define GPIO_OUT_PIN15_High (1UL) /*!< Pin driver is high */
4937 
4938 /* Bit 14 : Pin 14 */
4939 #define GPIO_OUT_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
4940 #define GPIO_OUT_PIN14_Msk (0x1UL << GPIO_OUT_PIN14_Pos) /*!< Bit mask of PIN14 field. */
4941 #define GPIO_OUT_PIN14_Low (0UL) /*!< Pin driver is low */
4942 #define GPIO_OUT_PIN14_High (1UL) /*!< Pin driver is high */
4943 
4944 /* Bit 13 : Pin 13 */
4945 #define GPIO_OUT_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
4946 #define GPIO_OUT_PIN13_Msk (0x1UL << GPIO_OUT_PIN13_Pos) /*!< Bit mask of PIN13 field. */
4947 #define GPIO_OUT_PIN13_Low (0UL) /*!< Pin driver is low */
4948 #define GPIO_OUT_PIN13_High (1UL) /*!< Pin driver is high */
4949 
4950 /* Bit 12 : Pin 12 */
4951 #define GPIO_OUT_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
4952 #define GPIO_OUT_PIN12_Msk (0x1UL << GPIO_OUT_PIN12_Pos) /*!< Bit mask of PIN12 field. */
4953 #define GPIO_OUT_PIN12_Low (0UL) /*!< Pin driver is low */
4954 #define GPIO_OUT_PIN12_High (1UL) /*!< Pin driver is high */
4955 
4956 /* Bit 11 : Pin 11 */
4957 #define GPIO_OUT_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
4958 #define GPIO_OUT_PIN11_Msk (0x1UL << GPIO_OUT_PIN11_Pos) /*!< Bit mask of PIN11 field. */
4959 #define GPIO_OUT_PIN11_Low (0UL) /*!< Pin driver is low */
4960 #define GPIO_OUT_PIN11_High (1UL) /*!< Pin driver is high */
4961 
4962 /* Bit 10 : Pin 10 */
4963 #define GPIO_OUT_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
4964 #define GPIO_OUT_PIN10_Msk (0x1UL << GPIO_OUT_PIN10_Pos) /*!< Bit mask of PIN10 field. */
4965 #define GPIO_OUT_PIN10_Low (0UL) /*!< Pin driver is low */
4966 #define GPIO_OUT_PIN10_High (1UL) /*!< Pin driver is high */
4967 
4968 /* Bit 9 : Pin 9 */
4969 #define GPIO_OUT_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
4970 #define GPIO_OUT_PIN9_Msk (0x1UL << GPIO_OUT_PIN9_Pos) /*!< Bit mask of PIN9 field. */
4971 #define GPIO_OUT_PIN9_Low (0UL) /*!< Pin driver is low */
4972 #define GPIO_OUT_PIN9_High (1UL) /*!< Pin driver is high */
4973 
4974 /* Bit 8 : Pin 8 */
4975 #define GPIO_OUT_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
4976 #define GPIO_OUT_PIN8_Msk (0x1UL << GPIO_OUT_PIN8_Pos) /*!< Bit mask of PIN8 field. */
4977 #define GPIO_OUT_PIN8_Low (0UL) /*!< Pin driver is low */
4978 #define GPIO_OUT_PIN8_High (1UL) /*!< Pin driver is high */
4979 
4980 /* Bit 7 : Pin 7 */
4981 #define GPIO_OUT_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
4982 #define GPIO_OUT_PIN7_Msk (0x1UL << GPIO_OUT_PIN7_Pos) /*!< Bit mask of PIN7 field. */
4983 #define GPIO_OUT_PIN7_Low (0UL) /*!< Pin driver is low */
4984 #define GPIO_OUT_PIN7_High (1UL) /*!< Pin driver is high */
4985 
4986 /* Bit 6 : Pin 6 */
4987 #define GPIO_OUT_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
4988 #define GPIO_OUT_PIN6_Msk (0x1UL << GPIO_OUT_PIN6_Pos) /*!< Bit mask of PIN6 field. */
4989 #define GPIO_OUT_PIN6_Low (0UL) /*!< Pin driver is low */
4990 #define GPIO_OUT_PIN6_High (1UL) /*!< Pin driver is high */
4991 
4992 /* Bit 5 : Pin 5 */
4993 #define GPIO_OUT_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
4994 #define GPIO_OUT_PIN5_Msk (0x1UL << GPIO_OUT_PIN5_Pos) /*!< Bit mask of PIN5 field. */
4995 #define GPIO_OUT_PIN5_Low (0UL) /*!< Pin driver is low */
4996 #define GPIO_OUT_PIN5_High (1UL) /*!< Pin driver is high */
4997 
4998 /* Bit 4 : Pin 4 */
4999 #define GPIO_OUT_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
5000 #define GPIO_OUT_PIN4_Msk (0x1UL << GPIO_OUT_PIN4_Pos) /*!< Bit mask of PIN4 field. */
5001 #define GPIO_OUT_PIN4_Low (0UL) /*!< Pin driver is low */
5002 #define GPIO_OUT_PIN4_High (1UL) /*!< Pin driver is high */
5003 
5004 /* Bit 3 : Pin 3 */
5005 #define GPIO_OUT_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
5006 #define GPIO_OUT_PIN3_Msk (0x1UL << GPIO_OUT_PIN3_Pos) /*!< Bit mask of PIN3 field. */
5007 #define GPIO_OUT_PIN3_Low (0UL) /*!< Pin driver is low */
5008 #define GPIO_OUT_PIN3_High (1UL) /*!< Pin driver is high */
5009 
5010 /* Bit 2 : Pin 2 */
5011 #define GPIO_OUT_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
5012 #define GPIO_OUT_PIN2_Msk (0x1UL << GPIO_OUT_PIN2_Pos) /*!< Bit mask of PIN2 field. */
5013 #define GPIO_OUT_PIN2_Low (0UL) /*!< Pin driver is low */
5014 #define GPIO_OUT_PIN2_High (1UL) /*!< Pin driver is high */
5015 
5016 /* Bit 1 : Pin 1 */
5017 #define GPIO_OUT_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
5018 #define GPIO_OUT_PIN1_Msk (0x1UL << GPIO_OUT_PIN1_Pos) /*!< Bit mask of PIN1 field. */
5019 #define GPIO_OUT_PIN1_Low (0UL) /*!< Pin driver is low */
5020 #define GPIO_OUT_PIN1_High (1UL) /*!< Pin driver is high */
5021 
5022 /* Bit 0 : Pin 0 */
5023 #define GPIO_OUT_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
5024 #define GPIO_OUT_PIN0_Msk (0x1UL << GPIO_OUT_PIN0_Pos) /*!< Bit mask of PIN0 field. */
5025 #define GPIO_OUT_PIN0_Low (0UL) /*!< Pin driver is low */
5026 #define GPIO_OUT_PIN0_High (1UL) /*!< Pin driver is high */
5027 
5028 /* Register: GPIO_OUTSET */
5029 /* Description: Set individual bits in GPIO port */
5030 
5031 /* Bit 31 : Pin 31 */
5032 #define GPIO_OUTSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
5033 #define GPIO_OUTSET_PIN31_Msk (0x1UL << GPIO_OUTSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */
5034 #define GPIO_OUTSET_PIN31_Low (0UL) /*!< Read: pin driver is low */
5035 #define GPIO_OUTSET_PIN31_High (1UL) /*!< Read: pin driver is high */
5036 #define GPIO_OUTSET_PIN31_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
5037 
5038 /* Bit 30 : Pin 30 */
5039 #define GPIO_OUTSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
5040 #define GPIO_OUTSET_PIN30_Msk (0x1UL << GPIO_OUTSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */
5041 #define GPIO_OUTSET_PIN30_Low (0UL) /*!< Read: pin driver is low */
5042 #define GPIO_OUTSET_PIN30_High (1UL) /*!< Read: pin driver is high */
5043 #define GPIO_OUTSET_PIN30_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
5044 
5045 /* Bit 29 : Pin 29 */
5046 #define GPIO_OUTSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
5047 #define GPIO_OUTSET_PIN29_Msk (0x1UL << GPIO_OUTSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */
5048 #define GPIO_OUTSET_PIN29_Low (0UL) /*!< Read: pin driver is low */
5049 #define GPIO_OUTSET_PIN29_High (1UL) /*!< Read: pin driver is high */
5050 #define GPIO_OUTSET_PIN29_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
5051 
5052 /* Bit 28 : Pin 28 */
5053 #define GPIO_OUTSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
5054 #define GPIO_OUTSET_PIN28_Msk (0x1UL << GPIO_OUTSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */
5055 #define GPIO_OUTSET_PIN28_Low (0UL) /*!< Read: pin driver is low */
5056 #define GPIO_OUTSET_PIN28_High (1UL) /*!< Read: pin driver is high */
5057 #define GPIO_OUTSET_PIN28_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
5058 
5059 /* Bit 27 : Pin 27 */
5060 #define GPIO_OUTSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
5061 #define GPIO_OUTSET_PIN27_Msk (0x1UL << GPIO_OUTSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */
5062 #define GPIO_OUTSET_PIN27_Low (0UL) /*!< Read: pin driver is low */
5063 #define GPIO_OUTSET_PIN27_High (1UL) /*!< Read: pin driver is high */
5064 #define GPIO_OUTSET_PIN27_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
5065 
5066 /* Bit 26 : Pin 26 */
5067 #define GPIO_OUTSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
5068 #define GPIO_OUTSET_PIN26_Msk (0x1UL << GPIO_OUTSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */
5069 #define GPIO_OUTSET_PIN26_Low (0UL) /*!< Read: pin driver is low */
5070 #define GPIO_OUTSET_PIN26_High (1UL) /*!< Read: pin driver is high */
5071 #define GPIO_OUTSET_PIN26_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
5072 
5073 /* Bit 25 : Pin 25 */
5074 #define GPIO_OUTSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
5075 #define GPIO_OUTSET_PIN25_Msk (0x1UL << GPIO_OUTSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */
5076 #define GPIO_OUTSET_PIN25_Low (0UL) /*!< Read: pin driver is low */
5077 #define GPIO_OUTSET_PIN25_High (1UL) /*!< Read: pin driver is high */
5078 #define GPIO_OUTSET_PIN25_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
5079 
5080 /* Bit 24 : Pin 24 */
5081 #define GPIO_OUTSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
5082 #define GPIO_OUTSET_PIN24_Msk (0x1UL << GPIO_OUTSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */
5083 #define GPIO_OUTSET_PIN24_Low (0UL) /*!< Read: pin driver is low */
5084 #define GPIO_OUTSET_PIN24_High (1UL) /*!< Read: pin driver is high */
5085 #define GPIO_OUTSET_PIN24_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
5086 
5087 /* Bit 23 : Pin 23 */
5088 #define GPIO_OUTSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
5089 #define GPIO_OUTSET_PIN23_Msk (0x1UL << GPIO_OUTSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */
5090 #define GPIO_OUTSET_PIN23_Low (0UL) /*!< Read: pin driver is low */
5091 #define GPIO_OUTSET_PIN23_High (1UL) /*!< Read: pin driver is high */
5092 #define GPIO_OUTSET_PIN23_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
5093 
5094 /* Bit 22 : Pin 22 */
5095 #define GPIO_OUTSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
5096 #define GPIO_OUTSET_PIN22_Msk (0x1UL << GPIO_OUTSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */
5097 #define GPIO_OUTSET_PIN22_Low (0UL) /*!< Read: pin driver is low */
5098 #define GPIO_OUTSET_PIN22_High (1UL) /*!< Read: pin driver is high */
5099 #define GPIO_OUTSET_PIN22_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
5100 
5101 /* Bit 21 : Pin 21 */
5102 #define GPIO_OUTSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
5103 #define GPIO_OUTSET_PIN21_Msk (0x1UL << GPIO_OUTSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */
5104 #define GPIO_OUTSET_PIN21_Low (0UL) /*!< Read: pin driver is low */
5105 #define GPIO_OUTSET_PIN21_High (1UL) /*!< Read: pin driver is high */
5106 #define GPIO_OUTSET_PIN21_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
5107 
5108 /* Bit 20 : Pin 20 */
5109 #define GPIO_OUTSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
5110 #define GPIO_OUTSET_PIN20_Msk (0x1UL << GPIO_OUTSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */
5111 #define GPIO_OUTSET_PIN20_Low (0UL) /*!< Read: pin driver is low */
5112 #define GPIO_OUTSET_PIN20_High (1UL) /*!< Read: pin driver is high */
5113 #define GPIO_OUTSET_PIN20_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
5114 
5115 /* Bit 19 : Pin 19 */
5116 #define GPIO_OUTSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
5117 #define GPIO_OUTSET_PIN19_Msk (0x1UL << GPIO_OUTSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */
5118 #define GPIO_OUTSET_PIN19_Low (0UL) /*!< Read: pin driver is low */
5119 #define GPIO_OUTSET_PIN19_High (1UL) /*!< Read: pin driver is high */
5120 #define GPIO_OUTSET_PIN19_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
5121 
5122 /* Bit 18 : Pin 18 */
5123 #define GPIO_OUTSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
5124 #define GPIO_OUTSET_PIN18_Msk (0x1UL << GPIO_OUTSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */
5125 #define GPIO_OUTSET_PIN18_Low (0UL) /*!< Read: pin driver is low */
5126 #define GPIO_OUTSET_PIN18_High (1UL) /*!< Read: pin driver is high */
5127 #define GPIO_OUTSET_PIN18_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
5128 
5129 /* Bit 17 : Pin 17 */
5130 #define GPIO_OUTSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
5131 #define GPIO_OUTSET_PIN17_Msk (0x1UL << GPIO_OUTSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */
5132 #define GPIO_OUTSET_PIN17_Low (0UL) /*!< Read: pin driver is low */
5133 #define GPIO_OUTSET_PIN17_High (1UL) /*!< Read: pin driver is high */
5134 #define GPIO_OUTSET_PIN17_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
5135 
5136 /* Bit 16 : Pin 16 */
5137 #define GPIO_OUTSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
5138 #define GPIO_OUTSET_PIN16_Msk (0x1UL << GPIO_OUTSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */
5139 #define GPIO_OUTSET_PIN16_Low (0UL) /*!< Read: pin driver is low */
5140 #define GPIO_OUTSET_PIN16_High (1UL) /*!< Read: pin driver is high */
5141 #define GPIO_OUTSET_PIN16_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
5142 
5143 /* Bit 15 : Pin 15 */
5144 #define GPIO_OUTSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
5145 #define GPIO_OUTSET_PIN15_Msk (0x1UL << GPIO_OUTSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */
5146 #define GPIO_OUTSET_PIN15_Low (0UL) /*!< Read: pin driver is low */
5147 #define GPIO_OUTSET_PIN15_High (1UL) /*!< Read: pin driver is high */
5148 #define GPIO_OUTSET_PIN15_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
5149 
5150 /* Bit 14 : Pin 14 */
5151 #define GPIO_OUTSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
5152 #define GPIO_OUTSET_PIN14_Msk (0x1UL << GPIO_OUTSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */
5153 #define GPIO_OUTSET_PIN14_Low (0UL) /*!< Read: pin driver is low */
5154 #define GPIO_OUTSET_PIN14_High (1UL) /*!< Read: pin driver is high */
5155 #define GPIO_OUTSET_PIN14_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
5156 
5157 /* Bit 13 : Pin 13 */
5158 #define GPIO_OUTSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
5159 #define GPIO_OUTSET_PIN13_Msk (0x1UL << GPIO_OUTSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */
5160 #define GPIO_OUTSET_PIN13_Low (0UL) /*!< Read: pin driver is low */
5161 #define GPIO_OUTSET_PIN13_High (1UL) /*!< Read: pin driver is high */
5162 #define GPIO_OUTSET_PIN13_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
5163 
5164 /* Bit 12 : Pin 12 */
5165 #define GPIO_OUTSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
5166 #define GPIO_OUTSET_PIN12_Msk (0x1UL << GPIO_OUTSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */
5167 #define GPIO_OUTSET_PIN12_Low (0UL) /*!< Read: pin driver is low */
5168 #define GPIO_OUTSET_PIN12_High (1UL) /*!< Read: pin driver is high */
5169 #define GPIO_OUTSET_PIN12_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
5170 
5171 /* Bit 11 : Pin 11 */
5172 #define GPIO_OUTSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
5173 #define GPIO_OUTSET_PIN11_Msk (0x1UL << GPIO_OUTSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */
5174 #define GPIO_OUTSET_PIN11_Low (0UL) /*!< Read: pin driver is low */
5175 #define GPIO_OUTSET_PIN11_High (1UL) /*!< Read: pin driver is high */
5176 #define GPIO_OUTSET_PIN11_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
5177 
5178 /* Bit 10 : Pin 10 */
5179 #define GPIO_OUTSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
5180 #define GPIO_OUTSET_PIN10_Msk (0x1UL << GPIO_OUTSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */
5181 #define GPIO_OUTSET_PIN10_Low (0UL) /*!< Read: pin driver is low */
5182 #define GPIO_OUTSET_PIN10_High (1UL) /*!< Read: pin driver is high */
5183 #define GPIO_OUTSET_PIN10_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
5184 
5185 /* Bit 9 : Pin 9 */
5186 #define GPIO_OUTSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
5187 #define GPIO_OUTSET_PIN9_Msk (0x1UL << GPIO_OUTSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */
5188 #define GPIO_OUTSET_PIN9_Low (0UL) /*!< Read: pin driver is low */
5189 #define GPIO_OUTSET_PIN9_High (1UL) /*!< Read: pin driver is high */
5190 #define GPIO_OUTSET_PIN9_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
5191 
5192 /* Bit 8 : Pin 8 */
5193 #define GPIO_OUTSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
5194 #define GPIO_OUTSET_PIN8_Msk (0x1UL << GPIO_OUTSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */
5195 #define GPIO_OUTSET_PIN8_Low (0UL) /*!< Read: pin driver is low */
5196 #define GPIO_OUTSET_PIN8_High (1UL) /*!< Read: pin driver is high */
5197 #define GPIO_OUTSET_PIN8_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
5198 
5199 /* Bit 7 : Pin 7 */
5200 #define GPIO_OUTSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
5201 #define GPIO_OUTSET_PIN7_Msk (0x1UL << GPIO_OUTSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */
5202 #define GPIO_OUTSET_PIN7_Low (0UL) /*!< Read: pin driver is low */
5203 #define GPIO_OUTSET_PIN7_High (1UL) /*!< Read: pin driver is high */
5204 #define GPIO_OUTSET_PIN7_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
5205 
5206 /* Bit 6 : Pin 6 */
5207 #define GPIO_OUTSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
5208 #define GPIO_OUTSET_PIN6_Msk (0x1UL << GPIO_OUTSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */
5209 #define GPIO_OUTSET_PIN6_Low (0UL) /*!< Read: pin driver is low */
5210 #define GPIO_OUTSET_PIN6_High (1UL) /*!< Read: pin driver is high */
5211 #define GPIO_OUTSET_PIN6_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
5212 
5213 /* Bit 5 : Pin 5 */
5214 #define GPIO_OUTSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
5215 #define GPIO_OUTSET_PIN5_Msk (0x1UL << GPIO_OUTSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */
5216 #define GPIO_OUTSET_PIN5_Low (0UL) /*!< Read: pin driver is low */
5217 #define GPIO_OUTSET_PIN5_High (1UL) /*!< Read: pin driver is high */
5218 #define GPIO_OUTSET_PIN5_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
5219 
5220 /* Bit 4 : Pin 4 */
5221 #define GPIO_OUTSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
5222 #define GPIO_OUTSET_PIN4_Msk (0x1UL << GPIO_OUTSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */
5223 #define GPIO_OUTSET_PIN4_Low (0UL) /*!< Read: pin driver is low */
5224 #define GPIO_OUTSET_PIN4_High (1UL) /*!< Read: pin driver is high */
5225 #define GPIO_OUTSET_PIN4_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
5226 
5227 /* Bit 3 : Pin 3 */
5228 #define GPIO_OUTSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
5229 #define GPIO_OUTSET_PIN3_Msk (0x1UL << GPIO_OUTSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */
5230 #define GPIO_OUTSET_PIN3_Low (0UL) /*!< Read: pin driver is low */
5231 #define GPIO_OUTSET_PIN3_High (1UL) /*!< Read: pin driver is high */
5232 #define GPIO_OUTSET_PIN3_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
5233 
5234 /* Bit 2 : Pin 2 */
5235 #define GPIO_OUTSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
5236 #define GPIO_OUTSET_PIN2_Msk (0x1UL << GPIO_OUTSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */
5237 #define GPIO_OUTSET_PIN2_Low (0UL) /*!< Read: pin driver is low */
5238 #define GPIO_OUTSET_PIN2_High (1UL) /*!< Read: pin driver is high */
5239 #define GPIO_OUTSET_PIN2_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
5240 
5241 /* Bit 1 : Pin 1 */
5242 #define GPIO_OUTSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
5243 #define GPIO_OUTSET_PIN1_Msk (0x1UL << GPIO_OUTSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */
5244 #define GPIO_OUTSET_PIN1_Low (0UL) /*!< Read: pin driver is low */
5245 #define GPIO_OUTSET_PIN1_High (1UL) /*!< Read: pin driver is high */
5246 #define GPIO_OUTSET_PIN1_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
5247 
5248 /* Bit 0 : Pin 0 */
5249 #define GPIO_OUTSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
5250 #define GPIO_OUTSET_PIN0_Msk (0x1UL << GPIO_OUTSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */
5251 #define GPIO_OUTSET_PIN0_Low (0UL) /*!< Read: pin driver is low */
5252 #define GPIO_OUTSET_PIN0_High (1UL) /*!< Read: pin driver is high */
5253 #define GPIO_OUTSET_PIN0_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
5254 
5255 /* Register: GPIO_OUTCLR */
5256 /* Description: Clear individual bits in GPIO port */
5257 
5258 /* Bit 31 : Pin 31 */
5259 #define GPIO_OUTCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
5260 #define GPIO_OUTCLR_PIN31_Msk (0x1UL << GPIO_OUTCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */
5261 #define GPIO_OUTCLR_PIN31_Low (0UL) /*!< Read: pin driver is low */
5262 #define GPIO_OUTCLR_PIN31_High (1UL) /*!< Read: pin driver is high */
5263 #define GPIO_OUTCLR_PIN31_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
5264 
5265 /* Bit 30 : Pin 30 */
5266 #define GPIO_OUTCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
5267 #define GPIO_OUTCLR_PIN30_Msk (0x1UL << GPIO_OUTCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */
5268 #define GPIO_OUTCLR_PIN30_Low (0UL) /*!< Read: pin driver is low */
5269 #define GPIO_OUTCLR_PIN30_High (1UL) /*!< Read: pin driver is high */
5270 #define GPIO_OUTCLR_PIN30_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
5271 
5272 /* Bit 29 : Pin 29 */
5273 #define GPIO_OUTCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
5274 #define GPIO_OUTCLR_PIN29_Msk (0x1UL << GPIO_OUTCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */
5275 #define GPIO_OUTCLR_PIN29_Low (0UL) /*!< Read: pin driver is low */
5276 #define GPIO_OUTCLR_PIN29_High (1UL) /*!< Read: pin driver is high */
5277 #define GPIO_OUTCLR_PIN29_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
5278 
5279 /* Bit 28 : Pin 28 */
5280 #define GPIO_OUTCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
5281 #define GPIO_OUTCLR_PIN28_Msk (0x1UL << GPIO_OUTCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */
5282 #define GPIO_OUTCLR_PIN28_Low (0UL) /*!< Read: pin driver is low */
5283 #define GPIO_OUTCLR_PIN28_High (1UL) /*!< Read: pin driver is high */
5284 #define GPIO_OUTCLR_PIN28_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
5285 
5286 /* Bit 27 : Pin 27 */
5287 #define GPIO_OUTCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
5288 #define GPIO_OUTCLR_PIN27_Msk (0x1UL << GPIO_OUTCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */
5289 #define GPIO_OUTCLR_PIN27_Low (0UL) /*!< Read: pin driver is low */
5290 #define GPIO_OUTCLR_PIN27_High (1UL) /*!< Read: pin driver is high */
5291 #define GPIO_OUTCLR_PIN27_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
5292 
5293 /* Bit 26 : Pin 26 */
5294 #define GPIO_OUTCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
5295 #define GPIO_OUTCLR_PIN26_Msk (0x1UL << GPIO_OUTCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */
5296 #define GPIO_OUTCLR_PIN26_Low (0UL) /*!< Read: pin driver is low */
5297 #define GPIO_OUTCLR_PIN26_High (1UL) /*!< Read: pin driver is high */
5298 #define GPIO_OUTCLR_PIN26_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
5299 
5300 /* Bit 25 : Pin 25 */
5301 #define GPIO_OUTCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
5302 #define GPIO_OUTCLR_PIN25_Msk (0x1UL << GPIO_OUTCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */
5303 #define GPIO_OUTCLR_PIN25_Low (0UL) /*!< Read: pin driver is low */
5304 #define GPIO_OUTCLR_PIN25_High (1UL) /*!< Read: pin driver is high */
5305 #define GPIO_OUTCLR_PIN25_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
5306 
5307 /* Bit 24 : Pin 24 */
5308 #define GPIO_OUTCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
5309 #define GPIO_OUTCLR_PIN24_Msk (0x1UL << GPIO_OUTCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */
5310 #define GPIO_OUTCLR_PIN24_Low (0UL) /*!< Read: pin driver is low */
5311 #define GPIO_OUTCLR_PIN24_High (1UL) /*!< Read: pin driver is high */
5312 #define GPIO_OUTCLR_PIN24_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
5313 
5314 /* Bit 23 : Pin 23 */
5315 #define GPIO_OUTCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
5316 #define GPIO_OUTCLR_PIN23_Msk (0x1UL << GPIO_OUTCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */
5317 #define GPIO_OUTCLR_PIN23_Low (0UL) /*!< Read: pin driver is low */
5318 #define GPIO_OUTCLR_PIN23_High (1UL) /*!< Read: pin driver is high */
5319 #define GPIO_OUTCLR_PIN23_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
5320 
5321 /* Bit 22 : Pin 22 */
5322 #define GPIO_OUTCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
5323 #define GPIO_OUTCLR_PIN22_Msk (0x1UL << GPIO_OUTCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */
5324 #define GPIO_OUTCLR_PIN22_Low (0UL) /*!< Read: pin driver is low */
5325 #define GPIO_OUTCLR_PIN22_High (1UL) /*!< Read: pin driver is high */
5326 #define GPIO_OUTCLR_PIN22_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
5327 
5328 /* Bit 21 : Pin 21 */
5329 #define GPIO_OUTCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
5330 #define GPIO_OUTCLR_PIN21_Msk (0x1UL << GPIO_OUTCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */
5331 #define GPIO_OUTCLR_PIN21_Low (0UL) /*!< Read: pin driver is low */
5332 #define GPIO_OUTCLR_PIN21_High (1UL) /*!< Read: pin driver is high */
5333 #define GPIO_OUTCLR_PIN21_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
5334 
5335 /* Bit 20 : Pin 20 */
5336 #define GPIO_OUTCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
5337 #define GPIO_OUTCLR_PIN20_Msk (0x1UL << GPIO_OUTCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */
5338 #define GPIO_OUTCLR_PIN20_Low (0UL) /*!< Read: pin driver is low */
5339 #define GPIO_OUTCLR_PIN20_High (1UL) /*!< Read: pin driver is high */
5340 #define GPIO_OUTCLR_PIN20_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
5341 
5342 /* Bit 19 : Pin 19 */
5343 #define GPIO_OUTCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
5344 #define GPIO_OUTCLR_PIN19_Msk (0x1UL << GPIO_OUTCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */
5345 #define GPIO_OUTCLR_PIN19_Low (0UL) /*!< Read: pin driver is low */
5346 #define GPIO_OUTCLR_PIN19_High (1UL) /*!< Read: pin driver is high */
5347 #define GPIO_OUTCLR_PIN19_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
5348 
5349 /* Bit 18 : Pin 18 */
5350 #define GPIO_OUTCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
5351 #define GPIO_OUTCLR_PIN18_Msk (0x1UL << GPIO_OUTCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */
5352 #define GPIO_OUTCLR_PIN18_Low (0UL) /*!< Read: pin driver is low */
5353 #define GPIO_OUTCLR_PIN18_High (1UL) /*!< Read: pin driver is high */
5354 #define GPIO_OUTCLR_PIN18_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
5355 
5356 /* Bit 17 : Pin 17 */
5357 #define GPIO_OUTCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
5358 #define GPIO_OUTCLR_PIN17_Msk (0x1UL << GPIO_OUTCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */
5359 #define GPIO_OUTCLR_PIN17_Low (0UL) /*!< Read: pin driver is low */
5360 #define GPIO_OUTCLR_PIN17_High (1UL) /*!< Read: pin driver is high */
5361 #define GPIO_OUTCLR_PIN17_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
5362 
5363 /* Bit 16 : Pin 16 */
5364 #define GPIO_OUTCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
5365 #define GPIO_OUTCLR_PIN16_Msk (0x1UL << GPIO_OUTCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */
5366 #define GPIO_OUTCLR_PIN16_Low (0UL) /*!< Read: pin driver is low */
5367 #define GPIO_OUTCLR_PIN16_High (1UL) /*!< Read: pin driver is high */
5368 #define GPIO_OUTCLR_PIN16_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
5369 
5370 /* Bit 15 : Pin 15 */
5371 #define GPIO_OUTCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
5372 #define GPIO_OUTCLR_PIN15_Msk (0x1UL << GPIO_OUTCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */
5373 #define GPIO_OUTCLR_PIN15_Low (0UL) /*!< Read: pin driver is low */
5374 #define GPIO_OUTCLR_PIN15_High (1UL) /*!< Read: pin driver is high */
5375 #define GPIO_OUTCLR_PIN15_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
5376 
5377 /* Bit 14 : Pin 14 */
5378 #define GPIO_OUTCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
5379 #define GPIO_OUTCLR_PIN14_Msk (0x1UL << GPIO_OUTCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */
5380 #define GPIO_OUTCLR_PIN14_Low (0UL) /*!< Read: pin driver is low */
5381 #define GPIO_OUTCLR_PIN14_High (1UL) /*!< Read: pin driver is high */
5382 #define GPIO_OUTCLR_PIN14_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
5383 
5384 /* Bit 13 : Pin 13 */
5385 #define GPIO_OUTCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
5386 #define GPIO_OUTCLR_PIN13_Msk (0x1UL << GPIO_OUTCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */
5387 #define GPIO_OUTCLR_PIN13_Low (0UL) /*!< Read: pin driver is low */
5388 #define GPIO_OUTCLR_PIN13_High (1UL) /*!< Read: pin driver is high */
5389 #define GPIO_OUTCLR_PIN13_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
5390 
5391 /* Bit 12 : Pin 12 */
5392 #define GPIO_OUTCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
5393 #define GPIO_OUTCLR_PIN12_Msk (0x1UL << GPIO_OUTCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */
5394 #define GPIO_OUTCLR_PIN12_Low (0UL) /*!< Read: pin driver is low */
5395 #define GPIO_OUTCLR_PIN12_High (1UL) /*!< Read: pin driver is high */
5396 #define GPIO_OUTCLR_PIN12_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
5397 
5398 /* Bit 11 : Pin 11 */
5399 #define GPIO_OUTCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
5400 #define GPIO_OUTCLR_PIN11_Msk (0x1UL << GPIO_OUTCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */
5401 #define GPIO_OUTCLR_PIN11_Low (0UL) /*!< Read: pin driver is low */
5402 #define GPIO_OUTCLR_PIN11_High (1UL) /*!< Read: pin driver is high */
5403 #define GPIO_OUTCLR_PIN11_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
5404 
5405 /* Bit 10 : Pin 10 */
5406 #define GPIO_OUTCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
5407 #define GPIO_OUTCLR_PIN10_Msk (0x1UL << GPIO_OUTCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */
5408 #define GPIO_OUTCLR_PIN10_Low (0UL) /*!< Read: pin driver is low */
5409 #define GPIO_OUTCLR_PIN10_High (1UL) /*!< Read: pin driver is high */
5410 #define GPIO_OUTCLR_PIN10_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
5411 
5412 /* Bit 9 : Pin 9 */
5413 #define GPIO_OUTCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
5414 #define GPIO_OUTCLR_PIN9_Msk (0x1UL << GPIO_OUTCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */
5415 #define GPIO_OUTCLR_PIN9_Low (0UL) /*!< Read: pin driver is low */
5416 #define GPIO_OUTCLR_PIN9_High (1UL) /*!< Read: pin driver is high */
5417 #define GPIO_OUTCLR_PIN9_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
5418 
5419 /* Bit 8 : Pin 8 */
5420 #define GPIO_OUTCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
5421 #define GPIO_OUTCLR_PIN8_Msk (0x1UL << GPIO_OUTCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */
5422 #define GPIO_OUTCLR_PIN8_Low (0UL) /*!< Read: pin driver is low */
5423 #define GPIO_OUTCLR_PIN8_High (1UL) /*!< Read: pin driver is high */
5424 #define GPIO_OUTCLR_PIN8_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
5425 
5426 /* Bit 7 : Pin 7 */
5427 #define GPIO_OUTCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
5428 #define GPIO_OUTCLR_PIN7_Msk (0x1UL << GPIO_OUTCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */
5429 #define GPIO_OUTCLR_PIN7_Low (0UL) /*!< Read: pin driver is low */
5430 #define GPIO_OUTCLR_PIN7_High (1UL) /*!< Read: pin driver is high */
5431 #define GPIO_OUTCLR_PIN7_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
5432 
5433 /* Bit 6 : Pin 6 */
5434 #define GPIO_OUTCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
5435 #define GPIO_OUTCLR_PIN6_Msk (0x1UL << GPIO_OUTCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */
5436 #define GPIO_OUTCLR_PIN6_Low (0UL) /*!< Read: pin driver is low */
5437 #define GPIO_OUTCLR_PIN6_High (1UL) /*!< Read: pin driver is high */
5438 #define GPIO_OUTCLR_PIN6_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
5439 
5440 /* Bit 5 : Pin 5 */
5441 #define GPIO_OUTCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
5442 #define GPIO_OUTCLR_PIN5_Msk (0x1UL << GPIO_OUTCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */
5443 #define GPIO_OUTCLR_PIN5_Low (0UL) /*!< Read: pin driver is low */
5444 #define GPIO_OUTCLR_PIN5_High (1UL) /*!< Read: pin driver is high */
5445 #define GPIO_OUTCLR_PIN5_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
5446 
5447 /* Bit 4 : Pin 4 */
5448 #define GPIO_OUTCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
5449 #define GPIO_OUTCLR_PIN4_Msk (0x1UL << GPIO_OUTCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */
5450 #define GPIO_OUTCLR_PIN4_Low (0UL) /*!< Read: pin driver is low */
5451 #define GPIO_OUTCLR_PIN4_High (1UL) /*!< Read: pin driver is high */
5452 #define GPIO_OUTCLR_PIN4_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
5453 
5454 /* Bit 3 : Pin 3 */
5455 #define GPIO_OUTCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
5456 #define GPIO_OUTCLR_PIN3_Msk (0x1UL << GPIO_OUTCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */
5457 #define GPIO_OUTCLR_PIN3_Low (0UL) /*!< Read: pin driver is low */
5458 #define GPIO_OUTCLR_PIN3_High (1UL) /*!< Read: pin driver is high */
5459 #define GPIO_OUTCLR_PIN3_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
5460 
5461 /* Bit 2 : Pin 2 */
5462 #define GPIO_OUTCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
5463 #define GPIO_OUTCLR_PIN2_Msk (0x1UL << GPIO_OUTCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */
5464 #define GPIO_OUTCLR_PIN2_Low (0UL) /*!< Read: pin driver is low */
5465 #define GPIO_OUTCLR_PIN2_High (1UL) /*!< Read: pin driver is high */
5466 #define GPIO_OUTCLR_PIN2_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
5467 
5468 /* Bit 1 : Pin 1 */
5469 #define GPIO_OUTCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
5470 #define GPIO_OUTCLR_PIN1_Msk (0x1UL << GPIO_OUTCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */
5471 #define GPIO_OUTCLR_PIN1_Low (0UL) /*!< Read: pin driver is low */
5472 #define GPIO_OUTCLR_PIN1_High (1UL) /*!< Read: pin driver is high */
5473 #define GPIO_OUTCLR_PIN1_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
5474 
5475 /* Bit 0 : Pin 0 */
5476 #define GPIO_OUTCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
5477 #define GPIO_OUTCLR_PIN0_Msk (0x1UL << GPIO_OUTCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */
5478 #define GPIO_OUTCLR_PIN0_Low (0UL) /*!< Read: pin driver is low */
5479 #define GPIO_OUTCLR_PIN0_High (1UL) /*!< Read: pin driver is high */
5480 #define GPIO_OUTCLR_PIN0_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
5481 
5482 /* Register: GPIO_IN */
5483 /* Description: Read GPIO port */
5484 
5485 /* Bit 31 : Pin 31 */
5486 #define GPIO_IN_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
5487 #define GPIO_IN_PIN31_Msk (0x1UL << GPIO_IN_PIN31_Pos) /*!< Bit mask of PIN31 field. */
5488 #define GPIO_IN_PIN31_Low (0UL) /*!< Pin input is low */
5489 #define GPIO_IN_PIN31_High (1UL) /*!< Pin input is high */
5490 
5491 /* Bit 30 : Pin 30 */
5492 #define GPIO_IN_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
5493 #define GPIO_IN_PIN30_Msk (0x1UL << GPIO_IN_PIN30_Pos) /*!< Bit mask of PIN30 field. */
5494 #define GPIO_IN_PIN30_Low (0UL) /*!< Pin input is low */
5495 #define GPIO_IN_PIN30_High (1UL) /*!< Pin input is high */
5496 
5497 /* Bit 29 : Pin 29 */
5498 #define GPIO_IN_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
5499 #define GPIO_IN_PIN29_Msk (0x1UL << GPIO_IN_PIN29_Pos) /*!< Bit mask of PIN29 field. */
5500 #define GPIO_IN_PIN29_Low (0UL) /*!< Pin input is low */
5501 #define GPIO_IN_PIN29_High (1UL) /*!< Pin input is high */
5502 
5503 /* Bit 28 : Pin 28 */
5504 #define GPIO_IN_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
5505 #define GPIO_IN_PIN28_Msk (0x1UL << GPIO_IN_PIN28_Pos) /*!< Bit mask of PIN28 field. */
5506 #define GPIO_IN_PIN28_Low (0UL) /*!< Pin input is low */
5507 #define GPIO_IN_PIN28_High (1UL) /*!< Pin input is high */
5508 
5509 /* Bit 27 : Pin 27 */
5510 #define GPIO_IN_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
5511 #define GPIO_IN_PIN27_Msk (0x1UL << GPIO_IN_PIN27_Pos) /*!< Bit mask of PIN27 field. */
5512 #define GPIO_IN_PIN27_Low (0UL) /*!< Pin input is low */
5513 #define GPIO_IN_PIN27_High (1UL) /*!< Pin input is high */
5514 
5515 /* Bit 26 : Pin 26 */
5516 #define GPIO_IN_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
5517 #define GPIO_IN_PIN26_Msk (0x1UL << GPIO_IN_PIN26_Pos) /*!< Bit mask of PIN26 field. */
5518 #define GPIO_IN_PIN26_Low (0UL) /*!< Pin input is low */
5519 #define GPIO_IN_PIN26_High (1UL) /*!< Pin input is high */
5520 
5521 /* Bit 25 : Pin 25 */
5522 #define GPIO_IN_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
5523 #define GPIO_IN_PIN25_Msk (0x1UL << GPIO_IN_PIN25_Pos) /*!< Bit mask of PIN25 field. */
5524 #define GPIO_IN_PIN25_Low (0UL) /*!< Pin input is low */
5525 #define GPIO_IN_PIN25_High (1UL) /*!< Pin input is high */
5526 
5527 /* Bit 24 : Pin 24 */
5528 #define GPIO_IN_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
5529 #define GPIO_IN_PIN24_Msk (0x1UL << GPIO_IN_PIN24_Pos) /*!< Bit mask of PIN24 field. */
5530 #define GPIO_IN_PIN24_Low (0UL) /*!< Pin input is low */
5531 #define GPIO_IN_PIN24_High (1UL) /*!< Pin input is high */
5532 
5533 /* Bit 23 : Pin 23 */
5534 #define GPIO_IN_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
5535 #define GPIO_IN_PIN23_Msk (0x1UL << GPIO_IN_PIN23_Pos) /*!< Bit mask of PIN23 field. */
5536 #define GPIO_IN_PIN23_Low (0UL) /*!< Pin input is low */
5537 #define GPIO_IN_PIN23_High (1UL) /*!< Pin input is high */
5538 
5539 /* Bit 22 : Pin 22 */
5540 #define GPIO_IN_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
5541 #define GPIO_IN_PIN22_Msk (0x1UL << GPIO_IN_PIN22_Pos) /*!< Bit mask of PIN22 field. */
5542 #define GPIO_IN_PIN22_Low (0UL) /*!< Pin input is low */
5543 #define GPIO_IN_PIN22_High (1UL) /*!< Pin input is high */
5544 
5545 /* Bit 21 : Pin 21 */
5546 #define GPIO_IN_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
5547 #define GPIO_IN_PIN21_Msk (0x1UL << GPIO_IN_PIN21_Pos) /*!< Bit mask of PIN21 field. */
5548 #define GPIO_IN_PIN21_Low (0UL) /*!< Pin input is low */
5549 #define GPIO_IN_PIN21_High (1UL) /*!< Pin input is high */
5550 
5551 /* Bit 20 : Pin 20 */
5552 #define GPIO_IN_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
5553 #define GPIO_IN_PIN20_Msk (0x1UL << GPIO_IN_PIN20_Pos) /*!< Bit mask of PIN20 field. */
5554 #define GPIO_IN_PIN20_Low (0UL) /*!< Pin input is low */
5555 #define GPIO_IN_PIN20_High (1UL) /*!< Pin input is high */
5556 
5557 /* Bit 19 : Pin 19 */
5558 #define GPIO_IN_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
5559 #define GPIO_IN_PIN19_Msk (0x1UL << GPIO_IN_PIN19_Pos) /*!< Bit mask of PIN19 field. */
5560 #define GPIO_IN_PIN19_Low (0UL) /*!< Pin input is low */
5561 #define GPIO_IN_PIN19_High (1UL) /*!< Pin input is high */
5562 
5563 /* Bit 18 : Pin 18 */
5564 #define GPIO_IN_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
5565 #define GPIO_IN_PIN18_Msk (0x1UL << GPIO_IN_PIN18_Pos) /*!< Bit mask of PIN18 field. */
5566 #define GPIO_IN_PIN18_Low (0UL) /*!< Pin input is low */
5567 #define GPIO_IN_PIN18_High (1UL) /*!< Pin input is high */
5568 
5569 /* Bit 17 : Pin 17 */
5570 #define GPIO_IN_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
5571 #define GPIO_IN_PIN17_Msk (0x1UL << GPIO_IN_PIN17_Pos) /*!< Bit mask of PIN17 field. */
5572 #define GPIO_IN_PIN17_Low (0UL) /*!< Pin input is low */
5573 #define GPIO_IN_PIN17_High (1UL) /*!< Pin input is high */
5574 
5575 /* Bit 16 : Pin 16 */
5576 #define GPIO_IN_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
5577 #define GPIO_IN_PIN16_Msk (0x1UL << GPIO_IN_PIN16_Pos) /*!< Bit mask of PIN16 field. */
5578 #define GPIO_IN_PIN16_Low (0UL) /*!< Pin input is low */
5579 #define GPIO_IN_PIN16_High (1UL) /*!< Pin input is high */
5580 
5581 /* Bit 15 : Pin 15 */
5582 #define GPIO_IN_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
5583 #define GPIO_IN_PIN15_Msk (0x1UL << GPIO_IN_PIN15_Pos) /*!< Bit mask of PIN15 field. */
5584 #define GPIO_IN_PIN15_Low (0UL) /*!< Pin input is low */
5585 #define GPIO_IN_PIN15_High (1UL) /*!< Pin input is high */
5586 
5587 /* Bit 14 : Pin 14 */
5588 #define GPIO_IN_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
5589 #define GPIO_IN_PIN14_Msk (0x1UL << GPIO_IN_PIN14_Pos) /*!< Bit mask of PIN14 field. */
5590 #define GPIO_IN_PIN14_Low (0UL) /*!< Pin input is low */
5591 #define GPIO_IN_PIN14_High (1UL) /*!< Pin input is high */
5592 
5593 /* Bit 13 : Pin 13 */
5594 #define GPIO_IN_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
5595 #define GPIO_IN_PIN13_Msk (0x1UL << GPIO_IN_PIN13_Pos) /*!< Bit mask of PIN13 field. */
5596 #define GPIO_IN_PIN13_Low (0UL) /*!< Pin input is low */
5597 #define GPIO_IN_PIN13_High (1UL) /*!< Pin input is high */
5598 
5599 /* Bit 12 : Pin 12 */
5600 #define GPIO_IN_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
5601 #define GPIO_IN_PIN12_Msk (0x1UL << GPIO_IN_PIN12_Pos) /*!< Bit mask of PIN12 field. */
5602 #define GPIO_IN_PIN12_Low (0UL) /*!< Pin input is low */
5603 #define GPIO_IN_PIN12_High (1UL) /*!< Pin input is high */
5604 
5605 /* Bit 11 : Pin 11 */
5606 #define GPIO_IN_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
5607 #define GPIO_IN_PIN11_Msk (0x1UL << GPIO_IN_PIN11_Pos) /*!< Bit mask of PIN11 field. */
5608 #define GPIO_IN_PIN11_Low (0UL) /*!< Pin input is low */
5609 #define GPIO_IN_PIN11_High (1UL) /*!< Pin input is high */
5610 
5611 /* Bit 10 : Pin 10 */
5612 #define GPIO_IN_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
5613 #define GPIO_IN_PIN10_Msk (0x1UL << GPIO_IN_PIN10_Pos) /*!< Bit mask of PIN10 field. */
5614 #define GPIO_IN_PIN10_Low (0UL) /*!< Pin input is low */
5615 #define GPIO_IN_PIN10_High (1UL) /*!< Pin input is high */
5616 
5617 /* Bit 9 : Pin 9 */
5618 #define GPIO_IN_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
5619 #define GPIO_IN_PIN9_Msk (0x1UL << GPIO_IN_PIN9_Pos) /*!< Bit mask of PIN9 field. */
5620 #define GPIO_IN_PIN9_Low (0UL) /*!< Pin input is low */
5621 #define GPIO_IN_PIN9_High (1UL) /*!< Pin input is high */
5622 
5623 /* Bit 8 : Pin 8 */
5624 #define GPIO_IN_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
5625 #define GPIO_IN_PIN8_Msk (0x1UL << GPIO_IN_PIN8_Pos) /*!< Bit mask of PIN8 field. */
5626 #define GPIO_IN_PIN8_Low (0UL) /*!< Pin input is low */
5627 #define GPIO_IN_PIN8_High (1UL) /*!< Pin input is high */
5628 
5629 /* Bit 7 : Pin 7 */
5630 #define GPIO_IN_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
5631 #define GPIO_IN_PIN7_Msk (0x1UL << GPIO_IN_PIN7_Pos) /*!< Bit mask of PIN7 field. */
5632 #define GPIO_IN_PIN7_Low (0UL) /*!< Pin input is low */
5633 #define GPIO_IN_PIN7_High (1UL) /*!< Pin input is high */
5634 
5635 /* Bit 6 : Pin 6 */
5636 #define GPIO_IN_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
5637 #define GPIO_IN_PIN6_Msk (0x1UL << GPIO_IN_PIN6_Pos) /*!< Bit mask of PIN6 field. */
5638 #define GPIO_IN_PIN6_Low (0UL) /*!< Pin input is low */
5639 #define GPIO_IN_PIN6_High (1UL) /*!< Pin input is high */
5640 
5641 /* Bit 5 : Pin 5 */
5642 #define GPIO_IN_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
5643 #define GPIO_IN_PIN5_Msk (0x1UL << GPIO_IN_PIN5_Pos) /*!< Bit mask of PIN5 field. */
5644 #define GPIO_IN_PIN5_Low (0UL) /*!< Pin input is low */
5645 #define GPIO_IN_PIN5_High (1UL) /*!< Pin input is high */
5646 
5647 /* Bit 4 : Pin 4 */
5648 #define GPIO_IN_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
5649 #define GPIO_IN_PIN4_Msk (0x1UL << GPIO_IN_PIN4_Pos) /*!< Bit mask of PIN4 field. */
5650 #define GPIO_IN_PIN4_Low (0UL) /*!< Pin input is low */
5651 #define GPIO_IN_PIN4_High (1UL) /*!< Pin input is high */
5652 
5653 /* Bit 3 : Pin 3 */
5654 #define GPIO_IN_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
5655 #define GPIO_IN_PIN3_Msk (0x1UL << GPIO_IN_PIN3_Pos) /*!< Bit mask of PIN3 field. */
5656 #define GPIO_IN_PIN3_Low (0UL) /*!< Pin input is low */
5657 #define GPIO_IN_PIN3_High (1UL) /*!< Pin input is high */
5658 
5659 /* Bit 2 : Pin 2 */
5660 #define GPIO_IN_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
5661 #define GPIO_IN_PIN2_Msk (0x1UL << GPIO_IN_PIN2_Pos) /*!< Bit mask of PIN2 field. */
5662 #define GPIO_IN_PIN2_Low (0UL) /*!< Pin input is low */
5663 #define GPIO_IN_PIN2_High (1UL) /*!< Pin input is high */
5664 
5665 /* Bit 1 : Pin 1 */
5666 #define GPIO_IN_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
5667 #define GPIO_IN_PIN1_Msk (0x1UL << GPIO_IN_PIN1_Pos) /*!< Bit mask of PIN1 field. */
5668 #define GPIO_IN_PIN1_Low (0UL) /*!< Pin input is low */
5669 #define GPIO_IN_PIN1_High (1UL) /*!< Pin input is high */
5670 
5671 /* Bit 0 : Pin 0 */
5672 #define GPIO_IN_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
5673 #define GPIO_IN_PIN0_Msk (0x1UL << GPIO_IN_PIN0_Pos) /*!< Bit mask of PIN0 field. */
5674 #define GPIO_IN_PIN0_Low (0UL) /*!< Pin input is low */
5675 #define GPIO_IN_PIN0_High (1UL) /*!< Pin input is high */
5676 
5677 /* Register: GPIO_DIR */
5678 /* Description: Direction of GPIO pins */
5679 
5680 /* Bit 31 : Pin 31 */
5681 #define GPIO_DIR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
5682 #define GPIO_DIR_PIN31_Msk (0x1UL << GPIO_DIR_PIN31_Pos) /*!< Bit mask of PIN31 field. */
5683 #define GPIO_DIR_PIN31_Input (0UL) /*!< Pin set as input */
5684 #define GPIO_DIR_PIN31_Output (1UL) /*!< Pin set as output */
5685 
5686 /* Bit 30 : Pin 30 */
5687 #define GPIO_DIR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
5688 #define GPIO_DIR_PIN30_Msk (0x1UL << GPIO_DIR_PIN30_Pos) /*!< Bit mask of PIN30 field. */
5689 #define GPIO_DIR_PIN30_Input (0UL) /*!< Pin set as input */
5690 #define GPIO_DIR_PIN30_Output (1UL) /*!< Pin set as output */
5691 
5692 /* Bit 29 : Pin 29 */
5693 #define GPIO_DIR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
5694 #define GPIO_DIR_PIN29_Msk (0x1UL << GPIO_DIR_PIN29_Pos) /*!< Bit mask of PIN29 field. */
5695 #define GPIO_DIR_PIN29_Input (0UL) /*!< Pin set as input */
5696 #define GPIO_DIR_PIN29_Output (1UL) /*!< Pin set as output */
5697 
5698 /* Bit 28 : Pin 28 */
5699 #define GPIO_DIR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
5700 #define GPIO_DIR_PIN28_Msk (0x1UL << GPIO_DIR_PIN28_Pos) /*!< Bit mask of PIN28 field. */
5701 #define GPIO_DIR_PIN28_Input (0UL) /*!< Pin set as input */
5702 #define GPIO_DIR_PIN28_Output (1UL) /*!< Pin set as output */
5703 
5704 /* Bit 27 : Pin 27 */
5705 #define GPIO_DIR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
5706 #define GPIO_DIR_PIN27_Msk (0x1UL << GPIO_DIR_PIN27_Pos) /*!< Bit mask of PIN27 field. */
5707 #define GPIO_DIR_PIN27_Input (0UL) /*!< Pin set as input */
5708 #define GPIO_DIR_PIN27_Output (1UL) /*!< Pin set as output */
5709 
5710 /* Bit 26 : Pin 26 */
5711 #define GPIO_DIR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
5712 #define GPIO_DIR_PIN26_Msk (0x1UL << GPIO_DIR_PIN26_Pos) /*!< Bit mask of PIN26 field. */
5713 #define GPIO_DIR_PIN26_Input (0UL) /*!< Pin set as input */
5714 #define GPIO_DIR_PIN26_Output (1UL) /*!< Pin set as output */
5715 
5716 /* Bit 25 : Pin 25 */
5717 #define GPIO_DIR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
5718 #define GPIO_DIR_PIN25_Msk (0x1UL << GPIO_DIR_PIN25_Pos) /*!< Bit mask of PIN25 field. */
5719 #define GPIO_DIR_PIN25_Input (0UL) /*!< Pin set as input */
5720 #define GPIO_DIR_PIN25_Output (1UL) /*!< Pin set as output */
5721 
5722 /* Bit 24 : Pin 24 */
5723 #define GPIO_DIR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
5724 #define GPIO_DIR_PIN24_Msk (0x1UL << GPIO_DIR_PIN24_Pos) /*!< Bit mask of PIN24 field. */
5725 #define GPIO_DIR_PIN24_Input (0UL) /*!< Pin set as input */
5726 #define GPIO_DIR_PIN24_Output (1UL) /*!< Pin set as output */
5727 
5728 /* Bit 23 : Pin 23 */
5729 #define GPIO_DIR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
5730 #define GPIO_DIR_PIN23_Msk (0x1UL << GPIO_DIR_PIN23_Pos) /*!< Bit mask of PIN23 field. */
5731 #define GPIO_DIR_PIN23_Input (0UL) /*!< Pin set as input */
5732 #define GPIO_DIR_PIN23_Output (1UL) /*!< Pin set as output */
5733 
5734 /* Bit 22 : Pin 22 */
5735 #define GPIO_DIR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
5736 #define GPIO_DIR_PIN22_Msk (0x1UL << GPIO_DIR_PIN22_Pos) /*!< Bit mask of PIN22 field. */
5737 #define GPIO_DIR_PIN22_Input (0UL) /*!< Pin set as input */
5738 #define GPIO_DIR_PIN22_Output (1UL) /*!< Pin set as output */
5739 
5740 /* Bit 21 : Pin 21 */
5741 #define GPIO_DIR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
5742 #define GPIO_DIR_PIN21_Msk (0x1UL << GPIO_DIR_PIN21_Pos) /*!< Bit mask of PIN21 field. */
5743 #define GPIO_DIR_PIN21_Input (0UL) /*!< Pin set as input */
5744 #define GPIO_DIR_PIN21_Output (1UL) /*!< Pin set as output */
5745 
5746 /* Bit 20 : Pin 20 */
5747 #define GPIO_DIR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
5748 #define GPIO_DIR_PIN20_Msk (0x1UL << GPIO_DIR_PIN20_Pos) /*!< Bit mask of PIN20 field. */
5749 #define GPIO_DIR_PIN20_Input (0UL) /*!< Pin set as input */
5750 #define GPIO_DIR_PIN20_Output (1UL) /*!< Pin set as output */
5751 
5752 /* Bit 19 : Pin 19 */
5753 #define GPIO_DIR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
5754 #define GPIO_DIR_PIN19_Msk (0x1UL << GPIO_DIR_PIN19_Pos) /*!< Bit mask of PIN19 field. */
5755 #define GPIO_DIR_PIN19_Input (0UL) /*!< Pin set as input */
5756 #define GPIO_DIR_PIN19_Output (1UL) /*!< Pin set as output */
5757 
5758 /* Bit 18 : Pin 18 */
5759 #define GPIO_DIR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
5760 #define GPIO_DIR_PIN18_Msk (0x1UL << GPIO_DIR_PIN18_Pos) /*!< Bit mask of PIN18 field. */
5761 #define GPIO_DIR_PIN18_Input (0UL) /*!< Pin set as input */
5762 #define GPIO_DIR_PIN18_Output (1UL) /*!< Pin set as output */
5763 
5764 /* Bit 17 : Pin 17 */
5765 #define GPIO_DIR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
5766 #define GPIO_DIR_PIN17_Msk (0x1UL << GPIO_DIR_PIN17_Pos) /*!< Bit mask of PIN17 field. */
5767 #define GPIO_DIR_PIN17_Input (0UL) /*!< Pin set as input */
5768 #define GPIO_DIR_PIN17_Output (1UL) /*!< Pin set as output */
5769 
5770 /* Bit 16 : Pin 16 */
5771 #define GPIO_DIR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
5772 #define GPIO_DIR_PIN16_Msk (0x1UL << GPIO_DIR_PIN16_Pos) /*!< Bit mask of PIN16 field. */
5773 #define GPIO_DIR_PIN16_Input (0UL) /*!< Pin set as input */
5774 #define GPIO_DIR_PIN16_Output (1UL) /*!< Pin set as output */
5775 
5776 /* Bit 15 : Pin 15 */
5777 #define GPIO_DIR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
5778 #define GPIO_DIR_PIN15_Msk (0x1UL << GPIO_DIR_PIN15_Pos) /*!< Bit mask of PIN15 field. */
5779 #define GPIO_DIR_PIN15_Input (0UL) /*!< Pin set as input */
5780 #define GPIO_DIR_PIN15_Output (1UL) /*!< Pin set as output */
5781 
5782 /* Bit 14 : Pin 14 */
5783 #define GPIO_DIR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
5784 #define GPIO_DIR_PIN14_Msk (0x1UL << GPIO_DIR_PIN14_Pos) /*!< Bit mask of PIN14 field. */
5785 #define GPIO_DIR_PIN14_Input (0UL) /*!< Pin set as input */
5786 #define GPIO_DIR_PIN14_Output (1UL) /*!< Pin set as output */
5787 
5788 /* Bit 13 : Pin 13 */
5789 #define GPIO_DIR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
5790 #define GPIO_DIR_PIN13_Msk (0x1UL << GPIO_DIR_PIN13_Pos) /*!< Bit mask of PIN13 field. */
5791 #define GPIO_DIR_PIN13_Input (0UL) /*!< Pin set as input */
5792 #define GPIO_DIR_PIN13_Output (1UL) /*!< Pin set as output */
5793 
5794 /* Bit 12 : Pin 12 */
5795 #define GPIO_DIR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
5796 #define GPIO_DIR_PIN12_Msk (0x1UL << GPIO_DIR_PIN12_Pos) /*!< Bit mask of PIN12 field. */
5797 #define GPIO_DIR_PIN12_Input (0UL) /*!< Pin set as input */
5798 #define GPIO_DIR_PIN12_Output (1UL) /*!< Pin set as output */
5799 
5800 /* Bit 11 : Pin 11 */
5801 #define GPIO_DIR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
5802 #define GPIO_DIR_PIN11_Msk (0x1UL << GPIO_DIR_PIN11_Pos) /*!< Bit mask of PIN11 field. */
5803 #define GPIO_DIR_PIN11_Input (0UL) /*!< Pin set as input */
5804 #define GPIO_DIR_PIN11_Output (1UL) /*!< Pin set as output */
5805 
5806 /* Bit 10 : Pin 10 */
5807 #define GPIO_DIR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
5808 #define GPIO_DIR_PIN10_Msk (0x1UL << GPIO_DIR_PIN10_Pos) /*!< Bit mask of PIN10 field. */
5809 #define GPIO_DIR_PIN10_Input (0UL) /*!< Pin set as input */
5810 #define GPIO_DIR_PIN10_Output (1UL) /*!< Pin set as output */
5811 
5812 /* Bit 9 : Pin 9 */
5813 #define GPIO_DIR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
5814 #define GPIO_DIR_PIN9_Msk (0x1UL << GPIO_DIR_PIN9_Pos) /*!< Bit mask of PIN9 field. */
5815 #define GPIO_DIR_PIN9_Input (0UL) /*!< Pin set as input */
5816 #define GPIO_DIR_PIN9_Output (1UL) /*!< Pin set as output */
5817 
5818 /* Bit 8 : Pin 8 */
5819 #define GPIO_DIR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
5820 #define GPIO_DIR_PIN8_Msk (0x1UL << GPIO_DIR_PIN8_Pos) /*!< Bit mask of PIN8 field. */
5821 #define GPIO_DIR_PIN8_Input (0UL) /*!< Pin set as input */
5822 #define GPIO_DIR_PIN8_Output (1UL) /*!< Pin set as output */
5823 
5824 /* Bit 7 : Pin 7 */
5825 #define GPIO_DIR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
5826 #define GPIO_DIR_PIN7_Msk (0x1UL << GPIO_DIR_PIN7_Pos) /*!< Bit mask of PIN7 field. */
5827 #define GPIO_DIR_PIN7_Input (0UL) /*!< Pin set as input */
5828 #define GPIO_DIR_PIN7_Output (1UL) /*!< Pin set as output */
5829 
5830 /* Bit 6 : Pin 6 */
5831 #define GPIO_DIR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
5832 #define GPIO_DIR_PIN6_Msk (0x1UL << GPIO_DIR_PIN6_Pos) /*!< Bit mask of PIN6 field. */
5833 #define GPIO_DIR_PIN6_Input (0UL) /*!< Pin set as input */
5834 #define GPIO_DIR_PIN6_Output (1UL) /*!< Pin set as output */
5835 
5836 /* Bit 5 : Pin 5 */
5837 #define GPIO_DIR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
5838 #define GPIO_DIR_PIN5_Msk (0x1UL << GPIO_DIR_PIN5_Pos) /*!< Bit mask of PIN5 field. */
5839 #define GPIO_DIR_PIN5_Input (0UL) /*!< Pin set as input */
5840 #define GPIO_DIR_PIN5_Output (1UL) /*!< Pin set as output */
5841 
5842 /* Bit 4 : Pin 4 */
5843 #define GPIO_DIR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
5844 #define GPIO_DIR_PIN4_Msk (0x1UL << GPIO_DIR_PIN4_Pos) /*!< Bit mask of PIN4 field. */
5845 #define GPIO_DIR_PIN4_Input (0UL) /*!< Pin set as input */
5846 #define GPIO_DIR_PIN4_Output (1UL) /*!< Pin set as output */
5847 
5848 /* Bit 3 : Pin 3 */
5849 #define GPIO_DIR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
5850 #define GPIO_DIR_PIN3_Msk (0x1UL << GPIO_DIR_PIN3_Pos) /*!< Bit mask of PIN3 field. */
5851 #define GPIO_DIR_PIN3_Input (0UL) /*!< Pin set as input */
5852 #define GPIO_DIR_PIN3_Output (1UL) /*!< Pin set as output */
5853 
5854 /* Bit 2 : Pin 2 */
5855 #define GPIO_DIR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
5856 #define GPIO_DIR_PIN2_Msk (0x1UL << GPIO_DIR_PIN2_Pos) /*!< Bit mask of PIN2 field. */
5857 #define GPIO_DIR_PIN2_Input (0UL) /*!< Pin set as input */
5858 #define GPIO_DIR_PIN2_Output (1UL) /*!< Pin set as output */
5859 
5860 /* Bit 1 : Pin 1 */
5861 #define GPIO_DIR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
5862 #define GPIO_DIR_PIN1_Msk (0x1UL << GPIO_DIR_PIN1_Pos) /*!< Bit mask of PIN1 field. */
5863 #define GPIO_DIR_PIN1_Input (0UL) /*!< Pin set as input */
5864 #define GPIO_DIR_PIN1_Output (1UL) /*!< Pin set as output */
5865 
5866 /* Bit 0 : Pin 0 */
5867 #define GPIO_DIR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
5868 #define GPIO_DIR_PIN0_Msk (0x1UL << GPIO_DIR_PIN0_Pos) /*!< Bit mask of PIN0 field. */
5869 #define GPIO_DIR_PIN0_Input (0UL) /*!< Pin set as input */
5870 #define GPIO_DIR_PIN0_Output (1UL) /*!< Pin set as output */
5871 
5872 /* Register: GPIO_DIRSET */
5873 /* Description: DIR set register */
5874 
5875 /* Bit 31 : Set as output pin 31 */
5876 #define GPIO_DIRSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
5877 #define GPIO_DIRSET_PIN31_Msk (0x1UL << GPIO_DIRSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */
5878 #define GPIO_DIRSET_PIN31_Input (0UL) /*!< Read: pin set as input */
5879 #define GPIO_DIRSET_PIN31_Output (1UL) /*!< Read: pin set as output */
5880 #define GPIO_DIRSET_PIN31_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
5881 
5882 /* Bit 30 : Set as output pin 30 */
5883 #define GPIO_DIRSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
5884 #define GPIO_DIRSET_PIN30_Msk (0x1UL << GPIO_DIRSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */
5885 #define GPIO_DIRSET_PIN30_Input (0UL) /*!< Read: pin set as input */
5886 #define GPIO_DIRSET_PIN30_Output (1UL) /*!< Read: pin set as output */
5887 #define GPIO_DIRSET_PIN30_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
5888 
5889 /* Bit 29 : Set as output pin 29 */
5890 #define GPIO_DIRSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
5891 #define GPIO_DIRSET_PIN29_Msk (0x1UL << GPIO_DIRSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */
5892 #define GPIO_DIRSET_PIN29_Input (0UL) /*!< Read: pin set as input */
5893 #define GPIO_DIRSET_PIN29_Output (1UL) /*!< Read: pin set as output */
5894 #define GPIO_DIRSET_PIN29_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
5895 
5896 /* Bit 28 : Set as output pin 28 */
5897 #define GPIO_DIRSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
5898 #define GPIO_DIRSET_PIN28_Msk (0x1UL << GPIO_DIRSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */
5899 #define GPIO_DIRSET_PIN28_Input (0UL) /*!< Read: pin set as input */
5900 #define GPIO_DIRSET_PIN28_Output (1UL) /*!< Read: pin set as output */
5901 #define GPIO_DIRSET_PIN28_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
5902 
5903 /* Bit 27 : Set as output pin 27 */
5904 #define GPIO_DIRSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
5905 #define GPIO_DIRSET_PIN27_Msk (0x1UL << GPIO_DIRSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */
5906 #define GPIO_DIRSET_PIN27_Input (0UL) /*!< Read: pin set as input */
5907 #define GPIO_DIRSET_PIN27_Output (1UL) /*!< Read: pin set as output */
5908 #define GPIO_DIRSET_PIN27_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
5909 
5910 /* Bit 26 : Set as output pin 26 */
5911 #define GPIO_DIRSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
5912 #define GPIO_DIRSET_PIN26_Msk (0x1UL << GPIO_DIRSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */
5913 #define GPIO_DIRSET_PIN26_Input (0UL) /*!< Read: pin set as input */
5914 #define GPIO_DIRSET_PIN26_Output (1UL) /*!< Read: pin set as output */
5915 #define GPIO_DIRSET_PIN26_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
5916 
5917 /* Bit 25 : Set as output pin 25 */
5918 #define GPIO_DIRSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
5919 #define GPIO_DIRSET_PIN25_Msk (0x1UL << GPIO_DIRSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */
5920 #define GPIO_DIRSET_PIN25_Input (0UL) /*!< Read: pin set as input */
5921 #define GPIO_DIRSET_PIN25_Output (1UL) /*!< Read: pin set as output */
5922 #define GPIO_DIRSET_PIN25_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
5923 
5924 /* Bit 24 : Set as output pin 24 */
5925 #define GPIO_DIRSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
5926 #define GPIO_DIRSET_PIN24_Msk (0x1UL << GPIO_DIRSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */
5927 #define GPIO_DIRSET_PIN24_Input (0UL) /*!< Read: pin set as input */
5928 #define GPIO_DIRSET_PIN24_Output (1UL) /*!< Read: pin set as output */
5929 #define GPIO_DIRSET_PIN24_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
5930 
5931 /* Bit 23 : Set as output pin 23 */
5932 #define GPIO_DIRSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
5933 #define GPIO_DIRSET_PIN23_Msk (0x1UL << GPIO_DIRSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */
5934 #define GPIO_DIRSET_PIN23_Input (0UL) /*!< Read: pin set as input */
5935 #define GPIO_DIRSET_PIN23_Output (1UL) /*!< Read: pin set as output */
5936 #define GPIO_DIRSET_PIN23_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
5937 
5938 /* Bit 22 : Set as output pin 22 */
5939 #define GPIO_DIRSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
5940 #define GPIO_DIRSET_PIN22_Msk (0x1UL << GPIO_DIRSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */
5941 #define GPIO_DIRSET_PIN22_Input (0UL) /*!< Read: pin set as input */
5942 #define GPIO_DIRSET_PIN22_Output (1UL) /*!< Read: pin set as output */
5943 #define GPIO_DIRSET_PIN22_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
5944 
5945 /* Bit 21 : Set as output pin 21 */
5946 #define GPIO_DIRSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
5947 #define GPIO_DIRSET_PIN21_Msk (0x1UL << GPIO_DIRSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */
5948 #define GPIO_DIRSET_PIN21_Input (0UL) /*!< Read: pin set as input */
5949 #define GPIO_DIRSET_PIN21_Output (1UL) /*!< Read: pin set as output */
5950 #define GPIO_DIRSET_PIN21_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
5951 
5952 /* Bit 20 : Set as output pin 20 */
5953 #define GPIO_DIRSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
5954 #define GPIO_DIRSET_PIN20_Msk (0x1UL << GPIO_DIRSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */
5955 #define GPIO_DIRSET_PIN20_Input (0UL) /*!< Read: pin set as input */
5956 #define GPIO_DIRSET_PIN20_Output (1UL) /*!< Read: pin set as output */
5957 #define GPIO_DIRSET_PIN20_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
5958 
5959 /* Bit 19 : Set as output pin 19 */
5960 #define GPIO_DIRSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
5961 #define GPIO_DIRSET_PIN19_Msk (0x1UL << GPIO_DIRSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */
5962 #define GPIO_DIRSET_PIN19_Input (0UL) /*!< Read: pin set as input */
5963 #define GPIO_DIRSET_PIN19_Output (1UL) /*!< Read: pin set as output */
5964 #define GPIO_DIRSET_PIN19_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
5965 
5966 /* Bit 18 : Set as output pin 18 */
5967 #define GPIO_DIRSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
5968 #define GPIO_DIRSET_PIN18_Msk (0x1UL << GPIO_DIRSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */
5969 #define GPIO_DIRSET_PIN18_Input (0UL) /*!< Read: pin set as input */
5970 #define GPIO_DIRSET_PIN18_Output (1UL) /*!< Read: pin set as output */
5971 #define GPIO_DIRSET_PIN18_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
5972 
5973 /* Bit 17 : Set as output pin 17 */
5974 #define GPIO_DIRSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
5975 #define GPIO_DIRSET_PIN17_Msk (0x1UL << GPIO_DIRSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */
5976 #define GPIO_DIRSET_PIN17_Input (0UL) /*!< Read: pin set as input */
5977 #define GPIO_DIRSET_PIN17_Output (1UL) /*!< Read: pin set as output */
5978 #define GPIO_DIRSET_PIN17_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
5979 
5980 /* Bit 16 : Set as output pin 16 */
5981 #define GPIO_DIRSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
5982 #define GPIO_DIRSET_PIN16_Msk (0x1UL << GPIO_DIRSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */
5983 #define GPIO_DIRSET_PIN16_Input (0UL) /*!< Read: pin set as input */
5984 #define GPIO_DIRSET_PIN16_Output (1UL) /*!< Read: pin set as output */
5985 #define GPIO_DIRSET_PIN16_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
5986 
5987 /* Bit 15 : Set as output pin 15 */
5988 #define GPIO_DIRSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
5989 #define GPIO_DIRSET_PIN15_Msk (0x1UL << GPIO_DIRSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */
5990 #define GPIO_DIRSET_PIN15_Input (0UL) /*!< Read: pin set as input */
5991 #define GPIO_DIRSET_PIN15_Output (1UL) /*!< Read: pin set as output */
5992 #define GPIO_DIRSET_PIN15_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
5993 
5994 /* Bit 14 : Set as output pin 14 */
5995 #define GPIO_DIRSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
5996 #define GPIO_DIRSET_PIN14_Msk (0x1UL << GPIO_DIRSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */
5997 #define GPIO_DIRSET_PIN14_Input (0UL) /*!< Read: pin set as input */
5998 #define GPIO_DIRSET_PIN14_Output (1UL) /*!< Read: pin set as output */
5999 #define GPIO_DIRSET_PIN14_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
6000 
6001 /* Bit 13 : Set as output pin 13 */
6002 #define GPIO_DIRSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
6003 #define GPIO_DIRSET_PIN13_Msk (0x1UL << GPIO_DIRSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */
6004 #define GPIO_DIRSET_PIN13_Input (0UL) /*!< Read: pin set as input */
6005 #define GPIO_DIRSET_PIN13_Output (1UL) /*!< Read: pin set as output */
6006 #define GPIO_DIRSET_PIN13_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
6007 
6008 /* Bit 12 : Set as output pin 12 */
6009 #define GPIO_DIRSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
6010 #define GPIO_DIRSET_PIN12_Msk (0x1UL << GPIO_DIRSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */
6011 #define GPIO_DIRSET_PIN12_Input (0UL) /*!< Read: pin set as input */
6012 #define GPIO_DIRSET_PIN12_Output (1UL) /*!< Read: pin set as output */
6013 #define GPIO_DIRSET_PIN12_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
6014 
6015 /* Bit 11 : Set as output pin 11 */
6016 #define GPIO_DIRSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
6017 #define GPIO_DIRSET_PIN11_Msk (0x1UL << GPIO_DIRSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */
6018 #define GPIO_DIRSET_PIN11_Input (0UL) /*!< Read: pin set as input */
6019 #define GPIO_DIRSET_PIN11_Output (1UL) /*!< Read: pin set as output */
6020 #define GPIO_DIRSET_PIN11_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
6021 
6022 /* Bit 10 : Set as output pin 10 */
6023 #define GPIO_DIRSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
6024 #define GPIO_DIRSET_PIN10_Msk (0x1UL << GPIO_DIRSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */
6025 #define GPIO_DIRSET_PIN10_Input (0UL) /*!< Read: pin set as input */
6026 #define GPIO_DIRSET_PIN10_Output (1UL) /*!< Read: pin set as output */
6027 #define GPIO_DIRSET_PIN10_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
6028 
6029 /* Bit 9 : Set as output pin 9 */
6030 #define GPIO_DIRSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
6031 #define GPIO_DIRSET_PIN9_Msk (0x1UL << GPIO_DIRSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */
6032 #define GPIO_DIRSET_PIN9_Input (0UL) /*!< Read: pin set as input */
6033 #define GPIO_DIRSET_PIN9_Output (1UL) /*!< Read: pin set as output */
6034 #define GPIO_DIRSET_PIN9_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
6035 
6036 /* Bit 8 : Set as output pin 8 */
6037 #define GPIO_DIRSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
6038 #define GPIO_DIRSET_PIN8_Msk (0x1UL << GPIO_DIRSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */
6039 #define GPIO_DIRSET_PIN8_Input (0UL) /*!< Read: pin set as input */
6040 #define GPIO_DIRSET_PIN8_Output (1UL) /*!< Read: pin set as output */
6041 #define GPIO_DIRSET_PIN8_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
6042 
6043 /* Bit 7 : Set as output pin 7 */
6044 #define GPIO_DIRSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
6045 #define GPIO_DIRSET_PIN7_Msk (0x1UL << GPIO_DIRSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */
6046 #define GPIO_DIRSET_PIN7_Input (0UL) /*!< Read: pin set as input */
6047 #define GPIO_DIRSET_PIN7_Output (1UL) /*!< Read: pin set as output */
6048 #define GPIO_DIRSET_PIN7_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
6049 
6050 /* Bit 6 : Set as output pin 6 */
6051 #define GPIO_DIRSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
6052 #define GPIO_DIRSET_PIN6_Msk (0x1UL << GPIO_DIRSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */
6053 #define GPIO_DIRSET_PIN6_Input (0UL) /*!< Read: pin set as input */
6054 #define GPIO_DIRSET_PIN6_Output (1UL) /*!< Read: pin set as output */
6055 #define GPIO_DIRSET_PIN6_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
6056 
6057 /* Bit 5 : Set as output pin 5 */
6058 #define GPIO_DIRSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
6059 #define GPIO_DIRSET_PIN5_Msk (0x1UL << GPIO_DIRSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */
6060 #define GPIO_DIRSET_PIN5_Input (0UL) /*!< Read: pin set as input */
6061 #define GPIO_DIRSET_PIN5_Output (1UL) /*!< Read: pin set as output */
6062 #define GPIO_DIRSET_PIN5_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
6063 
6064 /* Bit 4 : Set as output pin 4 */
6065 #define GPIO_DIRSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
6066 #define GPIO_DIRSET_PIN4_Msk (0x1UL << GPIO_DIRSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */
6067 #define GPIO_DIRSET_PIN4_Input (0UL) /*!< Read: pin set as input */
6068 #define GPIO_DIRSET_PIN4_Output (1UL) /*!< Read: pin set as output */
6069 #define GPIO_DIRSET_PIN4_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
6070 
6071 /* Bit 3 : Set as output pin 3 */
6072 #define GPIO_DIRSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
6073 #define GPIO_DIRSET_PIN3_Msk (0x1UL << GPIO_DIRSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */
6074 #define GPIO_DIRSET_PIN3_Input (0UL) /*!< Read: pin set as input */
6075 #define GPIO_DIRSET_PIN3_Output (1UL) /*!< Read: pin set as output */
6076 #define GPIO_DIRSET_PIN3_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
6077 
6078 /* Bit 2 : Set as output pin 2 */
6079 #define GPIO_DIRSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
6080 #define GPIO_DIRSET_PIN2_Msk (0x1UL << GPIO_DIRSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */
6081 #define GPIO_DIRSET_PIN2_Input (0UL) /*!< Read: pin set as input */
6082 #define GPIO_DIRSET_PIN2_Output (1UL) /*!< Read: pin set as output */
6083 #define GPIO_DIRSET_PIN2_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
6084 
6085 /* Bit 1 : Set as output pin 1 */
6086 #define GPIO_DIRSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
6087 #define GPIO_DIRSET_PIN1_Msk (0x1UL << GPIO_DIRSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */
6088 #define GPIO_DIRSET_PIN1_Input (0UL) /*!< Read: pin set as input */
6089 #define GPIO_DIRSET_PIN1_Output (1UL) /*!< Read: pin set as output */
6090 #define GPIO_DIRSET_PIN1_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
6091 
6092 /* Bit 0 : Set as output pin 0 */
6093 #define GPIO_DIRSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
6094 #define GPIO_DIRSET_PIN0_Msk (0x1UL << GPIO_DIRSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */
6095 #define GPIO_DIRSET_PIN0_Input (0UL) /*!< Read: pin set as input */
6096 #define GPIO_DIRSET_PIN0_Output (1UL) /*!< Read: pin set as output */
6097 #define GPIO_DIRSET_PIN0_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
6098 
6099 /* Register: GPIO_DIRCLR */
6100 /* Description: DIR clear register */
6101 
6102 /* Bit 31 : Set as input pin 31 */
6103 #define GPIO_DIRCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
6104 #define GPIO_DIRCLR_PIN31_Msk (0x1UL << GPIO_DIRCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */
6105 #define GPIO_DIRCLR_PIN31_Input (0UL) /*!< Read: pin set as input */
6106 #define GPIO_DIRCLR_PIN31_Output (1UL) /*!< Read: pin set as output */
6107 #define GPIO_DIRCLR_PIN31_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
6108 
6109 /* Bit 30 : Set as input pin 30 */
6110 #define GPIO_DIRCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
6111 #define GPIO_DIRCLR_PIN30_Msk (0x1UL << GPIO_DIRCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */
6112 #define GPIO_DIRCLR_PIN30_Input (0UL) /*!< Read: pin set as input */
6113 #define GPIO_DIRCLR_PIN30_Output (1UL) /*!< Read: pin set as output */
6114 #define GPIO_DIRCLR_PIN30_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
6115 
6116 /* Bit 29 : Set as input pin 29 */
6117 #define GPIO_DIRCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
6118 #define GPIO_DIRCLR_PIN29_Msk (0x1UL << GPIO_DIRCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */
6119 #define GPIO_DIRCLR_PIN29_Input (0UL) /*!< Read: pin set as input */
6120 #define GPIO_DIRCLR_PIN29_Output (1UL) /*!< Read: pin set as output */
6121 #define GPIO_DIRCLR_PIN29_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
6122 
6123 /* Bit 28 : Set as input pin 28 */
6124 #define GPIO_DIRCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
6125 #define GPIO_DIRCLR_PIN28_Msk (0x1UL << GPIO_DIRCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */
6126 #define GPIO_DIRCLR_PIN28_Input (0UL) /*!< Read: pin set as input */
6127 #define GPIO_DIRCLR_PIN28_Output (1UL) /*!< Read: pin set as output */
6128 #define GPIO_DIRCLR_PIN28_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
6129 
6130 /* Bit 27 : Set as input pin 27 */
6131 #define GPIO_DIRCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
6132 #define GPIO_DIRCLR_PIN27_Msk (0x1UL << GPIO_DIRCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */
6133 #define GPIO_DIRCLR_PIN27_Input (0UL) /*!< Read: pin set as input */
6134 #define GPIO_DIRCLR_PIN27_Output (1UL) /*!< Read: pin set as output */
6135 #define GPIO_DIRCLR_PIN27_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
6136 
6137 /* Bit 26 : Set as input pin 26 */
6138 #define GPIO_DIRCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
6139 #define GPIO_DIRCLR_PIN26_Msk (0x1UL << GPIO_DIRCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */
6140 #define GPIO_DIRCLR_PIN26_Input (0UL) /*!< Read: pin set as input */
6141 #define GPIO_DIRCLR_PIN26_Output (1UL) /*!< Read: pin set as output */
6142 #define GPIO_DIRCLR_PIN26_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
6143 
6144 /* Bit 25 : Set as input pin 25 */
6145 #define GPIO_DIRCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
6146 #define GPIO_DIRCLR_PIN25_Msk (0x1UL << GPIO_DIRCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */
6147 #define GPIO_DIRCLR_PIN25_Input (0UL) /*!< Read: pin set as input */
6148 #define GPIO_DIRCLR_PIN25_Output (1UL) /*!< Read: pin set as output */
6149 #define GPIO_DIRCLR_PIN25_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
6150 
6151 /* Bit 24 : Set as input pin 24 */
6152 #define GPIO_DIRCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
6153 #define GPIO_DIRCLR_PIN24_Msk (0x1UL << GPIO_DIRCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */
6154 #define GPIO_DIRCLR_PIN24_Input (0UL) /*!< Read: pin set as input */
6155 #define GPIO_DIRCLR_PIN24_Output (1UL) /*!< Read: pin set as output */
6156 #define GPIO_DIRCLR_PIN24_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
6157 
6158 /* Bit 23 : Set as input pin 23 */
6159 #define GPIO_DIRCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
6160 #define GPIO_DIRCLR_PIN23_Msk (0x1UL << GPIO_DIRCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */
6161 #define GPIO_DIRCLR_PIN23_Input (0UL) /*!< Read: pin set as input */
6162 #define GPIO_DIRCLR_PIN23_Output (1UL) /*!< Read: pin set as output */
6163 #define GPIO_DIRCLR_PIN23_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
6164 
6165 /* Bit 22 : Set as input pin 22 */
6166 #define GPIO_DIRCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
6167 #define GPIO_DIRCLR_PIN22_Msk (0x1UL << GPIO_DIRCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */
6168 #define GPIO_DIRCLR_PIN22_Input (0UL) /*!< Read: pin set as input */
6169 #define GPIO_DIRCLR_PIN22_Output (1UL) /*!< Read: pin set as output */
6170 #define GPIO_DIRCLR_PIN22_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
6171 
6172 /* Bit 21 : Set as input pin 21 */
6173 #define GPIO_DIRCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
6174 #define GPIO_DIRCLR_PIN21_Msk (0x1UL << GPIO_DIRCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */
6175 #define GPIO_DIRCLR_PIN21_Input (0UL) /*!< Read: pin set as input */
6176 #define GPIO_DIRCLR_PIN21_Output (1UL) /*!< Read: pin set as output */
6177 #define GPIO_DIRCLR_PIN21_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
6178 
6179 /* Bit 20 : Set as input pin 20 */
6180 #define GPIO_DIRCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
6181 #define GPIO_DIRCLR_PIN20_Msk (0x1UL << GPIO_DIRCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */
6182 #define GPIO_DIRCLR_PIN20_Input (0UL) /*!< Read: pin set as input */
6183 #define GPIO_DIRCLR_PIN20_Output (1UL) /*!< Read: pin set as output */
6184 #define GPIO_DIRCLR_PIN20_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
6185 
6186 /* Bit 19 : Set as input pin 19 */
6187 #define GPIO_DIRCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
6188 #define GPIO_DIRCLR_PIN19_Msk (0x1UL << GPIO_DIRCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */
6189 #define GPIO_DIRCLR_PIN19_Input (0UL) /*!< Read: pin set as input */
6190 #define GPIO_DIRCLR_PIN19_Output (1UL) /*!< Read: pin set as output */
6191 #define GPIO_DIRCLR_PIN19_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
6192 
6193 /* Bit 18 : Set as input pin 18 */
6194 #define GPIO_DIRCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
6195 #define GPIO_DIRCLR_PIN18_Msk (0x1UL << GPIO_DIRCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */
6196 #define GPIO_DIRCLR_PIN18_Input (0UL) /*!< Read: pin set as input */
6197 #define GPIO_DIRCLR_PIN18_Output (1UL) /*!< Read: pin set as output */
6198 #define GPIO_DIRCLR_PIN18_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
6199 
6200 /* Bit 17 : Set as input pin 17 */
6201 #define GPIO_DIRCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
6202 #define GPIO_DIRCLR_PIN17_Msk (0x1UL << GPIO_DIRCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */
6203 #define GPIO_DIRCLR_PIN17_Input (0UL) /*!< Read: pin set as input */
6204 #define GPIO_DIRCLR_PIN17_Output (1UL) /*!< Read: pin set as output */
6205 #define GPIO_DIRCLR_PIN17_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
6206 
6207 /* Bit 16 : Set as input pin 16 */
6208 #define GPIO_DIRCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
6209 #define GPIO_DIRCLR_PIN16_Msk (0x1UL << GPIO_DIRCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */
6210 #define GPIO_DIRCLR_PIN16_Input (0UL) /*!< Read: pin set as input */
6211 #define GPIO_DIRCLR_PIN16_Output (1UL) /*!< Read: pin set as output */
6212 #define GPIO_DIRCLR_PIN16_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
6213 
6214 /* Bit 15 : Set as input pin 15 */
6215 #define GPIO_DIRCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
6216 #define GPIO_DIRCLR_PIN15_Msk (0x1UL << GPIO_DIRCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */
6217 #define GPIO_DIRCLR_PIN15_Input (0UL) /*!< Read: pin set as input */
6218 #define GPIO_DIRCLR_PIN15_Output (1UL) /*!< Read: pin set as output */
6219 #define GPIO_DIRCLR_PIN15_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
6220 
6221 /* Bit 14 : Set as input pin 14 */
6222 #define GPIO_DIRCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
6223 #define GPIO_DIRCLR_PIN14_Msk (0x1UL << GPIO_DIRCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */
6224 #define GPIO_DIRCLR_PIN14_Input (0UL) /*!< Read: pin set as input */
6225 #define GPIO_DIRCLR_PIN14_Output (1UL) /*!< Read: pin set as output */
6226 #define GPIO_DIRCLR_PIN14_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
6227 
6228 /* Bit 13 : Set as input pin 13 */
6229 #define GPIO_DIRCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
6230 #define GPIO_DIRCLR_PIN13_Msk (0x1UL << GPIO_DIRCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */
6231 #define GPIO_DIRCLR_PIN13_Input (0UL) /*!< Read: pin set as input */
6232 #define GPIO_DIRCLR_PIN13_Output (1UL) /*!< Read: pin set as output */
6233 #define GPIO_DIRCLR_PIN13_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
6234 
6235 /* Bit 12 : Set as input pin 12 */
6236 #define GPIO_DIRCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
6237 #define GPIO_DIRCLR_PIN12_Msk (0x1UL << GPIO_DIRCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */
6238 #define GPIO_DIRCLR_PIN12_Input (0UL) /*!< Read: pin set as input */
6239 #define GPIO_DIRCLR_PIN12_Output (1UL) /*!< Read: pin set as output */
6240 #define GPIO_DIRCLR_PIN12_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
6241 
6242 /* Bit 11 : Set as input pin 11 */
6243 #define GPIO_DIRCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
6244 #define GPIO_DIRCLR_PIN11_Msk (0x1UL << GPIO_DIRCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */
6245 #define GPIO_DIRCLR_PIN11_Input (0UL) /*!< Read: pin set as input */
6246 #define GPIO_DIRCLR_PIN11_Output (1UL) /*!< Read: pin set as output */
6247 #define GPIO_DIRCLR_PIN11_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
6248 
6249 /* Bit 10 : Set as input pin 10 */
6250 #define GPIO_DIRCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
6251 #define GPIO_DIRCLR_PIN10_Msk (0x1UL << GPIO_DIRCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */
6252 #define GPIO_DIRCLR_PIN10_Input (0UL) /*!< Read: pin set as input */
6253 #define GPIO_DIRCLR_PIN10_Output (1UL) /*!< Read: pin set as output */
6254 #define GPIO_DIRCLR_PIN10_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
6255 
6256 /* Bit 9 : Set as input pin 9 */
6257 #define GPIO_DIRCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
6258 #define GPIO_DIRCLR_PIN9_Msk (0x1UL << GPIO_DIRCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */
6259 #define GPIO_DIRCLR_PIN9_Input (0UL) /*!< Read: pin set as input */
6260 #define GPIO_DIRCLR_PIN9_Output (1UL) /*!< Read: pin set as output */
6261 #define GPIO_DIRCLR_PIN9_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
6262 
6263 /* Bit 8 : Set as input pin 8 */
6264 #define GPIO_DIRCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
6265 #define GPIO_DIRCLR_PIN8_Msk (0x1UL << GPIO_DIRCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */
6266 #define GPIO_DIRCLR_PIN8_Input (0UL) /*!< Read: pin set as input */
6267 #define GPIO_DIRCLR_PIN8_Output (1UL) /*!< Read: pin set as output */
6268 #define GPIO_DIRCLR_PIN8_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
6269 
6270 /* Bit 7 : Set as input pin 7 */
6271 #define GPIO_DIRCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
6272 #define GPIO_DIRCLR_PIN7_Msk (0x1UL << GPIO_DIRCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */
6273 #define GPIO_DIRCLR_PIN7_Input (0UL) /*!< Read: pin set as input */
6274 #define GPIO_DIRCLR_PIN7_Output (1UL) /*!< Read: pin set as output */
6275 #define GPIO_DIRCLR_PIN7_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
6276 
6277 /* Bit 6 : Set as input pin 6 */
6278 #define GPIO_DIRCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
6279 #define GPIO_DIRCLR_PIN6_Msk (0x1UL << GPIO_DIRCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */
6280 #define GPIO_DIRCLR_PIN6_Input (0UL) /*!< Read: pin set as input */
6281 #define GPIO_DIRCLR_PIN6_Output (1UL) /*!< Read: pin set as output */
6282 #define GPIO_DIRCLR_PIN6_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
6283 
6284 /* Bit 5 : Set as input pin 5 */
6285 #define GPIO_DIRCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
6286 #define GPIO_DIRCLR_PIN5_Msk (0x1UL << GPIO_DIRCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */
6287 #define GPIO_DIRCLR_PIN5_Input (0UL) /*!< Read: pin set as input */
6288 #define GPIO_DIRCLR_PIN5_Output (1UL) /*!< Read: pin set as output */
6289 #define GPIO_DIRCLR_PIN5_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
6290 
6291 /* Bit 4 : Set as input pin 4 */
6292 #define GPIO_DIRCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
6293 #define GPIO_DIRCLR_PIN4_Msk (0x1UL << GPIO_DIRCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */
6294 #define GPIO_DIRCLR_PIN4_Input (0UL) /*!< Read: pin set as input */
6295 #define GPIO_DIRCLR_PIN4_Output (1UL) /*!< Read: pin set as output */
6296 #define GPIO_DIRCLR_PIN4_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
6297 
6298 /* Bit 3 : Set as input pin 3 */
6299 #define GPIO_DIRCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
6300 #define GPIO_DIRCLR_PIN3_Msk (0x1UL << GPIO_DIRCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */
6301 #define GPIO_DIRCLR_PIN3_Input (0UL) /*!< Read: pin set as input */
6302 #define GPIO_DIRCLR_PIN3_Output (1UL) /*!< Read: pin set as output */
6303 #define GPIO_DIRCLR_PIN3_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
6304 
6305 /* Bit 2 : Set as input pin 2 */
6306 #define GPIO_DIRCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
6307 #define GPIO_DIRCLR_PIN2_Msk (0x1UL << GPIO_DIRCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */
6308 #define GPIO_DIRCLR_PIN2_Input (0UL) /*!< Read: pin set as input */
6309 #define GPIO_DIRCLR_PIN2_Output (1UL) /*!< Read: pin set as output */
6310 #define GPIO_DIRCLR_PIN2_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
6311 
6312 /* Bit 1 : Set as input pin 1 */
6313 #define GPIO_DIRCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
6314 #define GPIO_DIRCLR_PIN1_Msk (0x1UL << GPIO_DIRCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */
6315 #define GPIO_DIRCLR_PIN1_Input (0UL) /*!< Read: pin set as input */
6316 #define GPIO_DIRCLR_PIN1_Output (1UL) /*!< Read: pin set as output */
6317 #define GPIO_DIRCLR_PIN1_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
6318 
6319 /* Bit 0 : Set as input pin 0 */
6320 #define GPIO_DIRCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
6321 #define GPIO_DIRCLR_PIN0_Msk (0x1UL << GPIO_DIRCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */
6322 #define GPIO_DIRCLR_PIN0_Input (0UL) /*!< Read: pin set as input */
6323 #define GPIO_DIRCLR_PIN0_Output (1UL) /*!< Read: pin set as output */
6324 #define GPIO_DIRCLR_PIN0_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
6325 
6326 /* Register: GPIO_LATCH */
6327 /* Description: Latch register indicating what GPIO pins that have met the criteria set in the PIN_CNF[n].SENSE registers */
6328 
6329 /* Bit 31 : Status on whether PIN31 has met criteria set in PIN_CNF31.SENSE register. Write '1' to clear. */
6330 #define GPIO_LATCH_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
6331 #define GPIO_LATCH_PIN31_Msk (0x1UL << GPIO_LATCH_PIN31_Pos) /*!< Bit mask of PIN31 field. */
6332 #define GPIO_LATCH_PIN31_NotLatched (0UL) /*!< Criteria has not been met */
6333 #define GPIO_LATCH_PIN31_Latched (1UL) /*!< Criteria has been met */
6334 
6335 /* Bit 30 : Status on whether PIN30 has met criteria set in PIN_CNF30.SENSE register. Write '1' to clear. */
6336 #define GPIO_LATCH_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
6337 #define GPIO_LATCH_PIN30_Msk (0x1UL << GPIO_LATCH_PIN30_Pos) /*!< Bit mask of PIN30 field. */
6338 #define GPIO_LATCH_PIN30_NotLatched (0UL) /*!< Criteria has not been met */
6339 #define GPIO_LATCH_PIN30_Latched (1UL) /*!< Criteria has been met */
6340 
6341 /* Bit 29 : Status on whether PIN29 has met criteria set in PIN_CNF29.SENSE register. Write '1' to clear. */
6342 #define GPIO_LATCH_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
6343 #define GPIO_LATCH_PIN29_Msk (0x1UL << GPIO_LATCH_PIN29_Pos) /*!< Bit mask of PIN29 field. */
6344 #define GPIO_LATCH_PIN29_NotLatched (0UL) /*!< Criteria has not been met */
6345 #define GPIO_LATCH_PIN29_Latched (1UL) /*!< Criteria has been met */
6346 
6347 /* Bit 28 : Status on whether PIN28 has met criteria set in PIN_CNF28.SENSE register. Write '1' to clear. */
6348 #define GPIO_LATCH_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
6349 #define GPIO_LATCH_PIN28_Msk (0x1UL << GPIO_LATCH_PIN28_Pos) /*!< Bit mask of PIN28 field. */
6350 #define GPIO_LATCH_PIN28_NotLatched (0UL) /*!< Criteria has not been met */
6351 #define GPIO_LATCH_PIN28_Latched (1UL) /*!< Criteria has been met */
6352 
6353 /* Bit 27 : Status on whether PIN27 has met criteria set in PIN_CNF27.SENSE register. Write '1' to clear. */
6354 #define GPIO_LATCH_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
6355 #define GPIO_LATCH_PIN27_Msk (0x1UL << GPIO_LATCH_PIN27_Pos) /*!< Bit mask of PIN27 field. */
6356 #define GPIO_LATCH_PIN27_NotLatched (0UL) /*!< Criteria has not been met */
6357 #define GPIO_LATCH_PIN27_Latched (1UL) /*!< Criteria has been met */
6358 
6359 /* Bit 26 : Status on whether PIN26 has met criteria set in PIN_CNF26.SENSE register. Write '1' to clear. */
6360 #define GPIO_LATCH_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
6361 #define GPIO_LATCH_PIN26_Msk (0x1UL << GPIO_LATCH_PIN26_Pos) /*!< Bit mask of PIN26 field. */
6362 #define GPIO_LATCH_PIN26_NotLatched (0UL) /*!< Criteria has not been met */
6363 #define GPIO_LATCH_PIN26_Latched (1UL) /*!< Criteria has been met */
6364 
6365 /* Bit 25 : Status on whether PIN25 has met criteria set in PIN_CNF25.SENSE register. Write '1' to clear. */
6366 #define GPIO_LATCH_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
6367 #define GPIO_LATCH_PIN25_Msk (0x1UL << GPIO_LATCH_PIN25_Pos) /*!< Bit mask of PIN25 field. */
6368 #define GPIO_LATCH_PIN25_NotLatched (0UL) /*!< Criteria has not been met */
6369 #define GPIO_LATCH_PIN25_Latched (1UL) /*!< Criteria has been met */
6370 
6371 /* Bit 24 : Status on whether PIN24 has met criteria set in PIN_CNF24.SENSE register. Write '1' to clear. */
6372 #define GPIO_LATCH_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
6373 #define GPIO_LATCH_PIN24_Msk (0x1UL << GPIO_LATCH_PIN24_Pos) /*!< Bit mask of PIN24 field. */
6374 #define GPIO_LATCH_PIN24_NotLatched (0UL) /*!< Criteria has not been met */
6375 #define GPIO_LATCH_PIN24_Latched (1UL) /*!< Criteria has been met */
6376 
6377 /* Bit 23 : Status on whether PIN23 has met criteria set in PIN_CNF23.SENSE register. Write '1' to clear. */
6378 #define GPIO_LATCH_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
6379 #define GPIO_LATCH_PIN23_Msk (0x1UL << GPIO_LATCH_PIN23_Pos) /*!< Bit mask of PIN23 field. */
6380 #define GPIO_LATCH_PIN23_NotLatched (0UL) /*!< Criteria has not been met */
6381 #define GPIO_LATCH_PIN23_Latched (1UL) /*!< Criteria has been met */
6382 
6383 /* Bit 22 : Status on whether PIN22 has met criteria set in PIN_CNF22.SENSE register. Write '1' to clear. */
6384 #define GPIO_LATCH_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
6385 #define GPIO_LATCH_PIN22_Msk (0x1UL << GPIO_LATCH_PIN22_Pos) /*!< Bit mask of PIN22 field. */
6386 #define GPIO_LATCH_PIN22_NotLatched (0UL) /*!< Criteria has not been met */
6387 #define GPIO_LATCH_PIN22_Latched (1UL) /*!< Criteria has been met */
6388 
6389 /* Bit 21 : Status on whether PIN21 has met criteria set in PIN_CNF21.SENSE register. Write '1' to clear. */
6390 #define GPIO_LATCH_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
6391 #define GPIO_LATCH_PIN21_Msk (0x1UL << GPIO_LATCH_PIN21_Pos) /*!< Bit mask of PIN21 field. */
6392 #define GPIO_LATCH_PIN21_NotLatched (0UL) /*!< Criteria has not been met */
6393 #define GPIO_LATCH_PIN21_Latched (1UL) /*!< Criteria has been met */
6394 
6395 /* Bit 20 : Status on whether PIN20 has met criteria set in PIN_CNF20.SENSE register. Write '1' to clear. */
6396 #define GPIO_LATCH_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
6397 #define GPIO_LATCH_PIN20_Msk (0x1UL << GPIO_LATCH_PIN20_Pos) /*!< Bit mask of PIN20 field. */
6398 #define GPIO_LATCH_PIN20_NotLatched (0UL) /*!< Criteria has not been met */
6399 #define GPIO_LATCH_PIN20_Latched (1UL) /*!< Criteria has been met */
6400 
6401 /* Bit 19 : Status on whether PIN19 has met criteria set in PIN_CNF19.SENSE register. Write '1' to clear. */
6402 #define GPIO_LATCH_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
6403 #define GPIO_LATCH_PIN19_Msk (0x1UL << GPIO_LATCH_PIN19_Pos) /*!< Bit mask of PIN19 field. */
6404 #define GPIO_LATCH_PIN19_NotLatched (0UL) /*!< Criteria has not been met */
6405 #define GPIO_LATCH_PIN19_Latched (1UL) /*!< Criteria has been met */
6406 
6407 /* Bit 18 : Status on whether PIN18 has met criteria set in PIN_CNF18.SENSE register. Write '1' to clear. */
6408 #define GPIO_LATCH_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
6409 #define GPIO_LATCH_PIN18_Msk (0x1UL << GPIO_LATCH_PIN18_Pos) /*!< Bit mask of PIN18 field. */
6410 #define GPIO_LATCH_PIN18_NotLatched (0UL) /*!< Criteria has not been met */
6411 #define GPIO_LATCH_PIN18_Latched (1UL) /*!< Criteria has been met */
6412 
6413 /* Bit 17 : Status on whether PIN17 has met criteria set in PIN_CNF17.SENSE register. Write '1' to clear. */
6414 #define GPIO_LATCH_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
6415 #define GPIO_LATCH_PIN17_Msk (0x1UL << GPIO_LATCH_PIN17_Pos) /*!< Bit mask of PIN17 field. */
6416 #define GPIO_LATCH_PIN17_NotLatched (0UL) /*!< Criteria has not been met */
6417 #define GPIO_LATCH_PIN17_Latched (1UL) /*!< Criteria has been met */
6418 
6419 /* Bit 16 : Status on whether PIN16 has met criteria set in PIN_CNF16.SENSE register. Write '1' to clear. */
6420 #define GPIO_LATCH_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
6421 #define GPIO_LATCH_PIN16_Msk (0x1UL << GPIO_LATCH_PIN16_Pos) /*!< Bit mask of PIN16 field. */
6422 #define GPIO_LATCH_PIN16_NotLatched (0UL) /*!< Criteria has not been met */
6423 #define GPIO_LATCH_PIN16_Latched (1UL) /*!< Criteria has been met */
6424 
6425 /* Bit 15 : Status on whether PIN15 has met criteria set in PIN_CNF15.SENSE register. Write '1' to clear. */
6426 #define GPIO_LATCH_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
6427 #define GPIO_LATCH_PIN15_Msk (0x1UL << GPIO_LATCH_PIN15_Pos) /*!< Bit mask of PIN15 field. */
6428 #define GPIO_LATCH_PIN15_NotLatched (0UL) /*!< Criteria has not been met */
6429 #define GPIO_LATCH_PIN15_Latched (1UL) /*!< Criteria has been met */
6430 
6431 /* Bit 14 : Status on whether PIN14 has met criteria set in PIN_CNF14.SENSE register. Write '1' to clear. */
6432 #define GPIO_LATCH_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
6433 #define GPIO_LATCH_PIN14_Msk (0x1UL << GPIO_LATCH_PIN14_Pos) /*!< Bit mask of PIN14 field. */
6434 #define GPIO_LATCH_PIN14_NotLatched (0UL) /*!< Criteria has not been met */
6435 #define GPIO_LATCH_PIN14_Latched (1UL) /*!< Criteria has been met */
6436 
6437 /* Bit 13 : Status on whether PIN13 has met criteria set in PIN_CNF13.SENSE register. Write '1' to clear. */
6438 #define GPIO_LATCH_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
6439 #define GPIO_LATCH_PIN13_Msk (0x1UL << GPIO_LATCH_PIN13_Pos) /*!< Bit mask of PIN13 field. */
6440 #define GPIO_LATCH_PIN13_NotLatched (0UL) /*!< Criteria has not been met */
6441 #define GPIO_LATCH_PIN13_Latched (1UL) /*!< Criteria has been met */
6442 
6443 /* Bit 12 : Status on whether PIN12 has met criteria set in PIN_CNF12.SENSE register. Write '1' to clear. */
6444 #define GPIO_LATCH_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
6445 #define GPIO_LATCH_PIN12_Msk (0x1UL << GPIO_LATCH_PIN12_Pos) /*!< Bit mask of PIN12 field. */
6446 #define GPIO_LATCH_PIN12_NotLatched (0UL) /*!< Criteria has not been met */
6447 #define GPIO_LATCH_PIN12_Latched (1UL) /*!< Criteria has been met */
6448 
6449 /* Bit 11 : Status on whether PIN11 has met criteria set in PIN_CNF11.SENSE register. Write '1' to clear. */
6450 #define GPIO_LATCH_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
6451 #define GPIO_LATCH_PIN11_Msk (0x1UL << GPIO_LATCH_PIN11_Pos) /*!< Bit mask of PIN11 field. */
6452 #define GPIO_LATCH_PIN11_NotLatched (0UL) /*!< Criteria has not been met */
6453 #define GPIO_LATCH_PIN11_Latched (1UL) /*!< Criteria has been met */
6454 
6455 /* Bit 10 : Status on whether PIN10 has met criteria set in PIN_CNF10.SENSE register. Write '1' to clear. */
6456 #define GPIO_LATCH_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
6457 #define GPIO_LATCH_PIN10_Msk (0x1UL << GPIO_LATCH_PIN10_Pos) /*!< Bit mask of PIN10 field. */
6458 #define GPIO_LATCH_PIN10_NotLatched (0UL) /*!< Criteria has not been met */
6459 #define GPIO_LATCH_PIN10_Latched (1UL) /*!< Criteria has been met */
6460 
6461 /* Bit 9 : Status on whether PIN9 has met criteria set in PIN_CNF9.SENSE register. Write '1' to clear. */
6462 #define GPIO_LATCH_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
6463 #define GPIO_LATCH_PIN9_Msk (0x1UL << GPIO_LATCH_PIN9_Pos) /*!< Bit mask of PIN9 field. */
6464 #define GPIO_LATCH_PIN9_NotLatched (0UL) /*!< Criteria has not been met */
6465 #define GPIO_LATCH_PIN9_Latched (1UL) /*!< Criteria has been met */
6466 
6467 /* Bit 8 : Status on whether PIN8 has met criteria set in PIN_CNF8.SENSE register. Write '1' to clear. */
6468 #define GPIO_LATCH_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
6469 #define GPIO_LATCH_PIN8_Msk (0x1UL << GPIO_LATCH_PIN8_Pos) /*!< Bit mask of PIN8 field. */
6470 #define GPIO_LATCH_PIN8_NotLatched (0UL) /*!< Criteria has not been met */
6471 #define GPIO_LATCH_PIN8_Latched (1UL) /*!< Criteria has been met */
6472 
6473 /* Bit 7 : Status on whether PIN7 has met criteria set in PIN_CNF7.SENSE register. Write '1' to clear. */
6474 #define GPIO_LATCH_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
6475 #define GPIO_LATCH_PIN7_Msk (0x1UL << GPIO_LATCH_PIN7_Pos) /*!< Bit mask of PIN7 field. */
6476 #define GPIO_LATCH_PIN7_NotLatched (0UL) /*!< Criteria has not been met */
6477 #define GPIO_LATCH_PIN7_Latched (1UL) /*!< Criteria has been met */
6478 
6479 /* Bit 6 : Status on whether PIN6 has met criteria set in PIN_CNF6.SENSE register. Write '1' to clear. */
6480 #define GPIO_LATCH_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
6481 #define GPIO_LATCH_PIN6_Msk (0x1UL << GPIO_LATCH_PIN6_Pos) /*!< Bit mask of PIN6 field. */
6482 #define GPIO_LATCH_PIN6_NotLatched (0UL) /*!< Criteria has not been met */
6483 #define GPIO_LATCH_PIN6_Latched (1UL) /*!< Criteria has been met */
6484 
6485 /* Bit 5 : Status on whether PIN5 has met criteria set in PIN_CNF5.SENSE register. Write '1' to clear. */
6486 #define GPIO_LATCH_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
6487 #define GPIO_LATCH_PIN5_Msk (0x1UL << GPIO_LATCH_PIN5_Pos) /*!< Bit mask of PIN5 field. */
6488 #define GPIO_LATCH_PIN5_NotLatched (0UL) /*!< Criteria has not been met */
6489 #define GPIO_LATCH_PIN5_Latched (1UL) /*!< Criteria has been met */
6490 
6491 /* Bit 4 : Status on whether PIN4 has met criteria set in PIN_CNF4.SENSE register. Write '1' to clear. */
6492 #define GPIO_LATCH_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
6493 #define GPIO_LATCH_PIN4_Msk (0x1UL << GPIO_LATCH_PIN4_Pos) /*!< Bit mask of PIN4 field. */
6494 #define GPIO_LATCH_PIN4_NotLatched (0UL) /*!< Criteria has not been met */
6495 #define GPIO_LATCH_PIN4_Latched (1UL) /*!< Criteria has been met */
6496 
6497 /* Bit 3 : Status on whether PIN3 has met criteria set in PIN_CNF3.SENSE register. Write '1' to clear. */
6498 #define GPIO_LATCH_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
6499 #define GPIO_LATCH_PIN3_Msk (0x1UL << GPIO_LATCH_PIN3_Pos) /*!< Bit mask of PIN3 field. */
6500 #define GPIO_LATCH_PIN3_NotLatched (0UL) /*!< Criteria has not been met */
6501 #define GPIO_LATCH_PIN3_Latched (1UL) /*!< Criteria has been met */
6502 
6503 /* Bit 2 : Status on whether PIN2 has met criteria set in PIN_CNF2.SENSE register. Write '1' to clear. */
6504 #define GPIO_LATCH_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
6505 #define GPIO_LATCH_PIN2_Msk (0x1UL << GPIO_LATCH_PIN2_Pos) /*!< Bit mask of PIN2 field. */
6506 #define GPIO_LATCH_PIN2_NotLatched (0UL) /*!< Criteria has not been met */
6507 #define GPIO_LATCH_PIN2_Latched (1UL) /*!< Criteria has been met */
6508 
6509 /* Bit 1 : Status on whether PIN1 has met criteria set in PIN_CNF1.SENSE register. Write '1' to clear. */
6510 #define GPIO_LATCH_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
6511 #define GPIO_LATCH_PIN1_Msk (0x1UL << GPIO_LATCH_PIN1_Pos) /*!< Bit mask of PIN1 field. */
6512 #define GPIO_LATCH_PIN1_NotLatched (0UL) /*!< Criteria has not been met */
6513 #define GPIO_LATCH_PIN1_Latched (1UL) /*!< Criteria has been met */
6514 
6515 /* Bit 0 : Status on whether PIN0 has met criteria set in PIN_CNF0.SENSE register. Write '1' to clear. */
6516 #define GPIO_LATCH_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
6517 #define GPIO_LATCH_PIN0_Msk (0x1UL << GPIO_LATCH_PIN0_Pos) /*!< Bit mask of PIN0 field. */
6518 #define GPIO_LATCH_PIN0_NotLatched (0UL) /*!< Criteria has not been met */
6519 #define GPIO_LATCH_PIN0_Latched (1UL) /*!< Criteria has been met */
6520 
6521 /* Register: GPIO_DETECTMODE */
6522 /* Description: Select between default DETECT signal behaviour and LDETECT mode */
6523 
6524 /* Bit 0 : Select between default DETECT signal behaviour and LDETECT mode */
6525 #define GPIO_DETECTMODE_DETECTMODE_Pos (0UL) /*!< Position of DETECTMODE field. */
6526 #define GPIO_DETECTMODE_DETECTMODE_Msk (0x1UL << GPIO_DETECTMODE_DETECTMODE_Pos) /*!< Bit mask of DETECTMODE field. */
6527 #define GPIO_DETECTMODE_DETECTMODE_Default (0UL) /*!< DETECT directly connected to PIN DETECT signals */
6528 #define GPIO_DETECTMODE_DETECTMODE_LDETECT (1UL) /*!< Use the latched LDETECT behaviour */
6529 
6530 /* Register: GPIO_PIN_CNF */
6531 /* Description: Description collection[0]:  Configuration of GPIO pins */
6532 
6533 /* Bits 17..16 : Pin sensing mechanism */
6534 #define GPIO_PIN_CNF_SENSE_Pos (16UL) /*!< Position of SENSE field. */
6535 #define GPIO_PIN_CNF_SENSE_Msk (0x3UL << GPIO_PIN_CNF_SENSE_Pos) /*!< Bit mask of SENSE field. */
6536 #define GPIO_PIN_CNF_SENSE_Disabled (0UL) /*!< Disabled */
6537 #define GPIO_PIN_CNF_SENSE_High (2UL) /*!< Sense for high level */
6538 #define GPIO_PIN_CNF_SENSE_Low (3UL) /*!< Sense for low level */
6539 
6540 /* Bits 10..8 : Drive configuration */
6541 #define GPIO_PIN_CNF_DRIVE_Pos (8UL) /*!< Position of DRIVE field. */
6542 #define GPIO_PIN_CNF_DRIVE_Msk (0x7UL << GPIO_PIN_CNF_DRIVE_Pos) /*!< Bit mask of DRIVE field. */
6543 #define GPIO_PIN_CNF_DRIVE_S0S1 (0UL) /*!< Standard '0', standard '1' */
6544 #define GPIO_PIN_CNF_DRIVE_H0S1 (1UL) /*!< High drive '0', standard '1' */
6545 #define GPIO_PIN_CNF_DRIVE_S0H1 (2UL) /*!< Standard '0', high drive '1' */
6546 #define GPIO_PIN_CNF_DRIVE_H0H1 (3UL) /*!< High drive '0', high 'drive '1'' */
6547 #define GPIO_PIN_CNF_DRIVE_D0S1 (4UL) /*!< Disconnect '0' standard '1' (normally used for wired-or connections) */
6548 #define GPIO_PIN_CNF_DRIVE_D0H1 (5UL) /*!< Disconnect '0', high drive '1' (normally used for wired-or connections) */
6549 #define GPIO_PIN_CNF_DRIVE_S0D1 (6UL) /*!< Standard '0'. disconnect '1' (normally used for wired-and connections) */
6550 #define GPIO_PIN_CNF_DRIVE_H0D1 (7UL) /*!< High drive '0', disconnect '1' (normally used for wired-and connections) */
6551 
6552 /* Bits 3..2 : Pull configuration */
6553 #define GPIO_PIN_CNF_PULL_Pos (2UL) /*!< Position of PULL field. */
6554 #define GPIO_PIN_CNF_PULL_Msk (0x3UL << GPIO_PIN_CNF_PULL_Pos) /*!< Bit mask of PULL field. */
6555 #define GPIO_PIN_CNF_PULL_Disabled (0UL) /*!< No pull */
6556 #define GPIO_PIN_CNF_PULL_Pulldown (1UL) /*!< Pull down on pin */
6557 #define GPIO_PIN_CNF_PULL_Pullup (3UL) /*!< Pull up on pin */
6558 
6559 /* Bit 1 : Connect or disconnect input buffer */
6560 #define GPIO_PIN_CNF_INPUT_Pos (1UL) /*!< Position of INPUT field. */
6561 #define GPIO_PIN_CNF_INPUT_Msk (0x1UL << GPIO_PIN_CNF_INPUT_Pos) /*!< Bit mask of INPUT field. */
6562 #define GPIO_PIN_CNF_INPUT_Connect (0UL) /*!< Connect input buffer */
6563 #define GPIO_PIN_CNF_INPUT_Disconnect (1UL) /*!< Disconnect input buffer */
6564 
6565 /* Bit 0 : Pin direction. Same physical register as DIR register */
6566 #define GPIO_PIN_CNF_DIR_Pos (0UL) /*!< Position of DIR field. */
6567 #define GPIO_PIN_CNF_DIR_Msk (0x1UL << GPIO_PIN_CNF_DIR_Pos) /*!< Bit mask of DIR field. */
6568 #define GPIO_PIN_CNF_DIR_Input (0UL) /*!< Configure pin as an input pin */
6569 #define GPIO_PIN_CNF_DIR_Output (1UL) /*!< Configure pin as an output pin */
6570 
6571 
6572 /* Peripheral: PDM */
6573 /* Description: Pulse Density Modulation (Digital Microphone) Interface */
6574 
6575 /* Register: PDM_INTEN */
6576 /* Description: Enable or disable interrupt */
6577 
6578 /* Bit 2 : Enable or disable interrupt for END event */
6579 #define PDM_INTEN_END_Pos (2UL) /*!< Position of END field. */
6580 #define PDM_INTEN_END_Msk (0x1UL << PDM_INTEN_END_Pos) /*!< Bit mask of END field. */
6581 #define PDM_INTEN_END_Disabled (0UL) /*!< Disable */
6582 #define PDM_INTEN_END_Enabled (1UL) /*!< Enable */
6583 
6584 /* Bit 1 : Enable or disable interrupt for STOPPED event */
6585 #define PDM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
6586 #define PDM_INTEN_STOPPED_Msk (0x1UL << PDM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
6587 #define PDM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
6588 #define PDM_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
6589 
6590 /* Bit 0 : Enable or disable interrupt for STARTED event */
6591 #define PDM_INTEN_STARTED_Pos (0UL) /*!< Position of STARTED field. */
6592 #define PDM_INTEN_STARTED_Msk (0x1UL << PDM_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */
6593 #define PDM_INTEN_STARTED_Disabled (0UL) /*!< Disable */
6594 #define PDM_INTEN_STARTED_Enabled (1UL) /*!< Enable */
6595 
6596 /* Register: PDM_INTENSET */
6597 /* Description: Enable interrupt */
6598 
6599 /* Bit 2 : Write '1' to Enable interrupt for END event */
6600 #define PDM_INTENSET_END_Pos (2UL) /*!< Position of END field. */
6601 #define PDM_INTENSET_END_Msk (0x1UL << PDM_INTENSET_END_Pos) /*!< Bit mask of END field. */
6602 #define PDM_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
6603 #define PDM_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
6604 #define PDM_INTENSET_END_Set (1UL) /*!< Enable */
6605 
6606 /* Bit 1 : Write '1' to Enable interrupt for STOPPED event */
6607 #define PDM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
6608 #define PDM_INTENSET_STOPPED_Msk (0x1UL << PDM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
6609 #define PDM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
6610 #define PDM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
6611 #define PDM_INTENSET_STOPPED_Set (1UL) /*!< Enable */
6612 
6613 /* Bit 0 : Write '1' to Enable interrupt for STARTED event */
6614 #define PDM_INTENSET_STARTED_Pos (0UL) /*!< Position of STARTED field. */
6615 #define PDM_INTENSET_STARTED_Msk (0x1UL << PDM_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */
6616 #define PDM_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */
6617 #define PDM_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */
6618 #define PDM_INTENSET_STARTED_Set (1UL) /*!< Enable */
6619 
6620 /* Register: PDM_INTENCLR */
6621 /* Description: Disable interrupt */
6622 
6623 /* Bit 2 : Write '1' to Disable interrupt for END event */
6624 #define PDM_INTENCLR_END_Pos (2UL) /*!< Position of END field. */
6625 #define PDM_INTENCLR_END_Msk (0x1UL << PDM_INTENCLR_END_Pos) /*!< Bit mask of END field. */
6626 #define PDM_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
6627 #define PDM_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
6628 #define PDM_INTENCLR_END_Clear (1UL) /*!< Disable */
6629 
6630 /* Bit 1 : Write '1' to Disable interrupt for STOPPED event */
6631 #define PDM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
6632 #define PDM_INTENCLR_STOPPED_Msk (0x1UL << PDM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
6633 #define PDM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
6634 #define PDM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
6635 #define PDM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
6636 
6637 /* Bit 0 : Write '1' to Disable interrupt for STARTED event */
6638 #define PDM_INTENCLR_STARTED_Pos (0UL) /*!< Position of STARTED field. */
6639 #define PDM_INTENCLR_STARTED_Msk (0x1UL << PDM_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */
6640 #define PDM_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */
6641 #define PDM_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */
6642 #define PDM_INTENCLR_STARTED_Clear (1UL) /*!< Disable */
6643 
6644 /* Register: PDM_ENABLE */
6645 /* Description: PDM module enable register */
6646 
6647 /* Bit 0 : Enable or disable PDM module */
6648 #define PDM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
6649 #define PDM_ENABLE_ENABLE_Msk (0x1UL << PDM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
6650 #define PDM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
6651 #define PDM_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */
6652 
6653 /* Register: PDM_PDMCLKCTRL */
6654 /* Description: PDM clock generator control */
6655 
6656 /* Bits 31..0 : PDM_CLK frequency */
6657 #define PDM_PDMCLKCTRL_FREQ_Pos (0UL) /*!< Position of FREQ field. */
6658 #define PDM_PDMCLKCTRL_FREQ_Msk (0xFFFFFFFFUL << PDM_PDMCLKCTRL_FREQ_Pos) /*!< Bit mask of FREQ field. */
6659 #define PDM_PDMCLKCTRL_FREQ_1000K (0x08000000UL) /*!< PDM_CLK = 32 MHz / 32 = 1.000 MHz */
6660 #define PDM_PDMCLKCTRL_FREQ_Default (0x08400000UL) /*!< PDM_CLK = 32 MHz / 31 = 1.032 MHz */
6661 #define PDM_PDMCLKCTRL_FREQ_1067K (0x08800000UL) /*!< PDM_CLK = 32 MHz / 30 = 1.067 MHz */
6662 
6663 /* Register: PDM_MODE */
6664 /* Description: Defines the routing of the connected PDM microphones' signals */
6665 
6666 /* Bit 1 : Defines on which PDM_CLK edge Left (or mono) is sampled */
6667 #define PDM_MODE_EDGE_Pos (1UL) /*!< Position of EDGE field. */
6668 #define PDM_MODE_EDGE_Msk (0x1UL << PDM_MODE_EDGE_Pos) /*!< Bit mask of EDGE field. */
6669 #define PDM_MODE_EDGE_LeftFalling (0UL) /*!< Left (or mono) is sampled on falling edge of PDM_CLK */
6670 #define PDM_MODE_EDGE_LeftRising (1UL) /*!< Left (or mono) is sampled on rising edge of PDM_CLK */
6671 
6672 /* Bit 0 : Mono or stereo operation */
6673 #define PDM_MODE_OPERATION_Pos (0UL) /*!< Position of OPERATION field. */
6674 #define PDM_MODE_OPERATION_Msk (0x1UL << PDM_MODE_OPERATION_Pos) /*!< Bit mask of OPERATION field. */
6675 #define PDM_MODE_OPERATION_Stereo (0UL) /*!< Sample and store one pair (Left + Right) of 16bit samples per RAM word R=[31:16]; L=[15:0] */
6676 #define PDM_MODE_OPERATION_Mono (1UL) /*!< Sample and store two successive Left samples (16 bit each) per RAM word L1=[31:16]; L0=[15:0] */
6677 
6678 /* Register: PDM_GAINL */
6679 /* Description: Left output gain adjustment */
6680 
6681 /* Bits 6..0 : Left output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) 0x00    -20 dB gain adjust 0x01  -19.5 dB gain adjust (...) 0x27   -0.5 dB gain adjust 0x28      0 dB gain adjust 0x29   +0.5 dB gain adjust (...) 0x4F  +19.5 dB gain adjust 0x50    +20 dB gain adjust */
6682 #define PDM_GAINL_GAINL_Pos (0UL) /*!< Position of GAINL field. */
6683 #define PDM_GAINL_GAINL_Msk (0x7FUL << PDM_GAINL_GAINL_Pos) /*!< Bit mask of GAINL field. */
6684 #define PDM_GAINL_GAINL_MinGain (0x00UL) /*!< -20dB gain adjustment (minimum) */
6685 #define PDM_GAINL_GAINL_DefaultGain (0x28UL) /*!< 0dB gain adjustment ('2500 RMS' requirement) */
6686 #define PDM_GAINL_GAINL_MaxGain (0x50UL) /*!< +20dB gain adjustment (maximum) */
6687 
6688 /* Register: PDM_GAINR */
6689 /* Description: Right output gain adjustment */
6690 
6691 /* Bits 7..0 : Right output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) */
6692 #define PDM_GAINR_GAINR_Pos (0UL) /*!< Position of GAINR field. */
6693 #define PDM_GAINR_GAINR_Msk (0xFFUL << PDM_GAINR_GAINR_Pos) /*!< Bit mask of GAINR field. */
6694 #define PDM_GAINR_GAINR_MinGain (0x00UL) /*!< -20dB gain adjustment (minimum) */
6695 #define PDM_GAINR_GAINR_DefaultGain (0x28UL) /*!< 0dB gain adjustment ('2500 RMS' requirement) */
6696 #define PDM_GAINR_GAINR_MaxGain (0x50UL) /*!< +20dB gain adjustment (maximum) */
6697 
6698 /* Register: PDM_PSEL_CLK */
6699 /* Description: Pin number configuration for PDM CLK signal */
6700 
6701 /* Bit 31 : Connection */
6702 #define PDM_PSEL_CLK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
6703 #define PDM_PSEL_CLK_CONNECT_Msk (0x1UL << PDM_PSEL_CLK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
6704 #define PDM_PSEL_CLK_CONNECT_Connected (0UL) /*!< Connect */
6705 #define PDM_PSEL_CLK_CONNECT_Disconnected (1UL) /*!< Disconnect */
6706 
6707 /* Bits 4..0 : Pin number */
6708 #define PDM_PSEL_CLK_PIN_Pos (0UL) /*!< Position of PIN field. */
6709 #define PDM_PSEL_CLK_PIN_Msk (0x1FUL << PDM_PSEL_CLK_PIN_Pos) /*!< Bit mask of PIN field. */
6710 
6711 /* Register: PDM_PSEL_DIN */
6712 /* Description: Pin number configuration for PDM DIN signal */
6713 
6714 /* Bit 31 : Connection */
6715 #define PDM_PSEL_DIN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
6716 #define PDM_PSEL_DIN_CONNECT_Msk (0x1UL << PDM_PSEL_DIN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
6717 #define PDM_PSEL_DIN_CONNECT_Connected (0UL) /*!< Connect */
6718 #define PDM_PSEL_DIN_CONNECT_Disconnected (1UL) /*!< Disconnect */
6719 
6720 /* Bits 4..0 : Pin number */
6721 #define PDM_PSEL_DIN_PIN_Pos (0UL) /*!< Position of PIN field. */
6722 #define PDM_PSEL_DIN_PIN_Msk (0x1FUL << PDM_PSEL_DIN_PIN_Pos) /*!< Bit mask of PIN field. */
6723 
6724 /* Register: PDM_SAMPLE_PTR */
6725 /* Description: RAM address pointer to write samples to with EasyDMA */
6726 
6727 /* Bits 31..0 : Address to write PDM samples to over DMA */
6728 #define PDM_SAMPLE_PTR_SAMPLEPTR_Pos (0UL) /*!< Position of SAMPLEPTR field. */
6729 #define PDM_SAMPLE_PTR_SAMPLEPTR_Msk (0xFFFFFFFFUL << PDM_SAMPLE_PTR_SAMPLEPTR_Pos) /*!< Bit mask of SAMPLEPTR field. */
6730 
6731 /* Register: PDM_SAMPLE_MAXCNT */
6732 /* Description: Number of samples to allocate memory for in EasyDMA mode */
6733 
6734 /* Bits 14..0 : Length of DMA RAM allocation in number of samples */
6735 #define PDM_SAMPLE_MAXCNT_BUFFSIZE_Pos (0UL) /*!< Position of BUFFSIZE field. */
6736 #define PDM_SAMPLE_MAXCNT_BUFFSIZE_Msk (0x7FFFUL << PDM_SAMPLE_MAXCNT_BUFFSIZE_Pos) /*!< Bit mask of BUFFSIZE field. */
6737 
6738 
6739 /* Peripheral: POWER */
6740 /* Description: Power control */
6741 
6742 /* Register: POWER_INTENSET */
6743 /* Description: Enable interrupt */
6744 
6745 /* Bit 6 : Write '1' to Enable interrupt for SLEEPEXIT event */
6746 #define POWER_INTENSET_SLEEPEXIT_Pos (6UL) /*!< Position of SLEEPEXIT field. */
6747 #define POWER_INTENSET_SLEEPEXIT_Msk (0x1UL << POWER_INTENSET_SLEEPEXIT_Pos) /*!< Bit mask of SLEEPEXIT field. */
6748 #define POWER_INTENSET_SLEEPEXIT_Disabled (0UL) /*!< Read: Disabled */
6749 #define POWER_INTENSET_SLEEPEXIT_Enabled (1UL) /*!< Read: Enabled */
6750 #define POWER_INTENSET_SLEEPEXIT_Set (1UL) /*!< Enable */
6751 
6752 /* Bit 5 : Write '1' to Enable interrupt for SLEEPENTER event */
6753 #define POWER_INTENSET_SLEEPENTER_Pos (5UL) /*!< Position of SLEEPENTER field. */
6754 #define POWER_INTENSET_SLEEPENTER_Msk (0x1UL << POWER_INTENSET_SLEEPENTER_Pos) /*!< Bit mask of SLEEPENTER field. */
6755 #define POWER_INTENSET_SLEEPENTER_Disabled (0UL) /*!< Read: Disabled */
6756 #define POWER_INTENSET_SLEEPENTER_Enabled (1UL) /*!< Read: Enabled */
6757 #define POWER_INTENSET_SLEEPENTER_Set (1UL) /*!< Enable */
6758 
6759 /* Bit 2 : Write '1' to Enable interrupt for POFWARN event */
6760 #define POWER_INTENSET_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */
6761 #define POWER_INTENSET_POFWARN_Msk (0x1UL << POWER_INTENSET_POFWARN_Pos) /*!< Bit mask of POFWARN field. */
6762 #define POWER_INTENSET_POFWARN_Disabled (0UL) /*!< Read: Disabled */
6763 #define POWER_INTENSET_POFWARN_Enabled (1UL) /*!< Read: Enabled */
6764 #define POWER_INTENSET_POFWARN_Set (1UL) /*!< Enable */
6765 
6766 /* Register: POWER_INTENCLR */
6767 /* Description: Disable interrupt */
6768 
6769 /* Bit 6 : Write '1' to Disable interrupt for SLEEPEXIT event */
6770 #define POWER_INTENCLR_SLEEPEXIT_Pos (6UL) /*!< Position of SLEEPEXIT field. */
6771 #define POWER_INTENCLR_SLEEPEXIT_Msk (0x1UL << POWER_INTENCLR_SLEEPEXIT_Pos) /*!< Bit mask of SLEEPEXIT field. */
6772 #define POWER_INTENCLR_SLEEPEXIT_Disabled (0UL) /*!< Read: Disabled */
6773 #define POWER_INTENCLR_SLEEPEXIT_Enabled (1UL) /*!< Read: Enabled */
6774 #define POWER_INTENCLR_SLEEPEXIT_Clear (1UL) /*!< Disable */
6775 
6776 /* Bit 5 : Write '1' to Disable interrupt for SLEEPENTER event */
6777 #define POWER_INTENCLR_SLEEPENTER_Pos (5UL) /*!< Position of SLEEPENTER field. */
6778 #define POWER_INTENCLR_SLEEPENTER_Msk (0x1UL << POWER_INTENCLR_SLEEPENTER_Pos) /*!< Bit mask of SLEEPENTER field. */
6779 #define POWER_INTENCLR_SLEEPENTER_Disabled (0UL) /*!< Read: Disabled */
6780 #define POWER_INTENCLR_SLEEPENTER_Enabled (1UL) /*!< Read: Enabled */
6781 #define POWER_INTENCLR_SLEEPENTER_Clear (1UL) /*!< Disable */
6782 
6783 /* Bit 2 : Write '1' to Disable interrupt for POFWARN event */
6784 #define POWER_INTENCLR_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */
6785 #define POWER_INTENCLR_POFWARN_Msk (0x1UL << POWER_INTENCLR_POFWARN_Pos) /*!< Bit mask of POFWARN field. */
6786 #define POWER_INTENCLR_POFWARN_Disabled (0UL) /*!< Read: Disabled */
6787 #define POWER_INTENCLR_POFWARN_Enabled (1UL) /*!< Read: Enabled */
6788 #define POWER_INTENCLR_POFWARN_Clear (1UL) /*!< Disable */
6789 
6790 /* Register: POWER_RESETREAS */
6791 /* Description: Reset reason */
6792 
6793 /* Bit 19 : Reset due to wake up from System OFF mode by NFC field detect */
6794 #define POWER_RESETREAS_NFC_Pos (19UL) /*!< Position of NFC field. */
6795 #define POWER_RESETREAS_NFC_Msk (0x1UL << POWER_RESETREAS_NFC_Pos) /*!< Bit mask of NFC field. */
6796 #define POWER_RESETREAS_NFC_NotDetected (0UL) /*!< Not detected */
6797 #define POWER_RESETREAS_NFC_Detected (1UL) /*!< Detected */
6798 
6799 /* Bit 18 : Reset due to wake up from System OFF mode when wakeup is triggered from entering into debug interface mode */
6800 #define POWER_RESETREAS_DIF_Pos (18UL) /*!< Position of DIF field. */
6801 #define POWER_RESETREAS_DIF_Msk (0x1UL << POWER_RESETREAS_DIF_Pos) /*!< Bit mask of DIF field. */
6802 #define POWER_RESETREAS_DIF_NotDetected (0UL) /*!< Not detected */
6803 #define POWER_RESETREAS_DIF_Detected (1UL) /*!< Detected */
6804 
6805 /* Bit 17 : Reset due to wake up from System OFF mode when wakeup is triggered from ANADETECT signal from LPCOMP */
6806 #define POWER_RESETREAS_LPCOMP_Pos (17UL) /*!< Position of LPCOMP field. */
6807 #define POWER_RESETREAS_LPCOMP_Msk (0x1UL << POWER_RESETREAS_LPCOMP_Pos) /*!< Bit mask of LPCOMP field. */
6808 #define POWER_RESETREAS_LPCOMP_NotDetected (0UL) /*!< Not detected */
6809 #define POWER_RESETREAS_LPCOMP_Detected (1UL) /*!< Detected */
6810 
6811 /* Bit 16 : Reset due to wake up from System OFF mode when wakeup is triggered from DETECT signal from GPIO */
6812 #define POWER_RESETREAS_OFF_Pos (16UL) /*!< Position of OFF field. */
6813 #define POWER_RESETREAS_OFF_Msk (0x1UL << POWER_RESETREAS_OFF_Pos) /*!< Bit mask of OFF field. */
6814 #define POWER_RESETREAS_OFF_NotDetected (0UL) /*!< Not detected */
6815 #define POWER_RESETREAS_OFF_Detected (1UL) /*!< Detected */
6816 
6817 /* Bit 3 : Reset from CPU lock-up detected */
6818 #define POWER_RESETREAS_LOCKUP_Pos (3UL) /*!< Position of LOCKUP field. */
6819 #define POWER_RESETREAS_LOCKUP_Msk (0x1UL << POWER_RESETREAS_LOCKUP_Pos) /*!< Bit mask of LOCKUP field. */
6820 #define POWER_RESETREAS_LOCKUP_NotDetected (0UL) /*!< Not detected */
6821 #define POWER_RESETREAS_LOCKUP_Detected (1UL) /*!< Detected */
6822 
6823 /* Bit 2 : Reset from soft reset detected */
6824 #define POWER_RESETREAS_SREQ_Pos (2UL) /*!< Position of SREQ field. */
6825 #define POWER_RESETREAS_SREQ_Msk (0x1UL << POWER_RESETREAS_SREQ_Pos) /*!< Bit mask of SREQ field. */
6826 #define POWER_RESETREAS_SREQ_NotDetected (0UL) /*!< Not detected */
6827 #define POWER_RESETREAS_SREQ_Detected (1UL) /*!< Detected */
6828 
6829 /* Bit 1 : Reset from watchdog detected */
6830 #define POWER_RESETREAS_DOG_Pos (1UL) /*!< Position of DOG field. */
6831 #define POWER_RESETREAS_DOG_Msk (0x1UL << POWER_RESETREAS_DOG_Pos) /*!< Bit mask of DOG field. */
6832 #define POWER_RESETREAS_DOG_NotDetected (0UL) /*!< Not detected */
6833 #define POWER_RESETREAS_DOG_Detected (1UL) /*!< Detected */
6834 
6835 /* Bit 0 : Reset from pin-reset detected */
6836 #define POWER_RESETREAS_RESETPIN_Pos (0UL) /*!< Position of RESETPIN field. */
6837 #define POWER_RESETREAS_RESETPIN_Msk (0x1UL << POWER_RESETREAS_RESETPIN_Pos) /*!< Bit mask of RESETPIN field. */
6838 #define POWER_RESETREAS_RESETPIN_NotDetected (0UL) /*!< Not detected */
6839 #define POWER_RESETREAS_RESETPIN_Detected (1UL) /*!< Detected */
6840 
6841 /* Register: POWER_RAMSTATUS */
6842 /* Description: Deprecated register -  RAM status register */
6843 
6844 /* Bit 3 : RAM block 3 is on or off/powering up */
6845 #define POWER_RAMSTATUS_RAMBLOCK3_Pos (3UL) /*!< Position of RAMBLOCK3 field. */
6846 #define POWER_RAMSTATUS_RAMBLOCK3_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK3_Pos) /*!< Bit mask of RAMBLOCK3 field. */
6847 #define POWER_RAMSTATUS_RAMBLOCK3_Off (0UL) /*!< Off */
6848 #define POWER_RAMSTATUS_RAMBLOCK3_On (1UL) /*!< On */
6849 
6850 /* Bit 2 : RAM block 2 is on or off/powering up */
6851 #define POWER_RAMSTATUS_RAMBLOCK2_Pos (2UL) /*!< Position of RAMBLOCK2 field. */
6852 #define POWER_RAMSTATUS_RAMBLOCK2_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK2_Pos) /*!< Bit mask of RAMBLOCK2 field. */
6853 #define POWER_RAMSTATUS_RAMBLOCK2_Off (0UL) /*!< Off */
6854 #define POWER_RAMSTATUS_RAMBLOCK2_On (1UL) /*!< On */
6855 
6856 /* Bit 1 : RAM block 1 is on or off/powering up */
6857 #define POWER_RAMSTATUS_RAMBLOCK1_Pos (1UL) /*!< Position of RAMBLOCK1 field. */
6858 #define POWER_RAMSTATUS_RAMBLOCK1_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK1_Pos) /*!< Bit mask of RAMBLOCK1 field. */
6859 #define POWER_RAMSTATUS_RAMBLOCK1_Off (0UL) /*!< Off */
6860 #define POWER_RAMSTATUS_RAMBLOCK1_On (1UL) /*!< On */
6861 
6862 /* Bit 0 : RAM block 0 is on or off/powering up */
6863 #define POWER_RAMSTATUS_RAMBLOCK0_Pos (0UL) /*!< Position of RAMBLOCK0 field. */
6864 #define POWER_RAMSTATUS_RAMBLOCK0_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK0_Pos) /*!< Bit mask of RAMBLOCK0 field. */
6865 #define POWER_RAMSTATUS_RAMBLOCK0_Off (0UL) /*!< Off */
6866 #define POWER_RAMSTATUS_RAMBLOCK0_On (1UL) /*!< On */
6867 
6868 /* Register: POWER_SYSTEMOFF */
6869 /* Description: System OFF register */
6870 
6871 /* Bit 0 : Enable System OFF mode */
6872 #define POWER_SYSTEMOFF_SYSTEMOFF_Pos (0UL) /*!< Position of SYSTEMOFF field. */
6873 #define POWER_SYSTEMOFF_SYSTEMOFF_Msk (0x1UL << POWER_SYSTEMOFF_SYSTEMOFF_Pos) /*!< Bit mask of SYSTEMOFF field. */
6874 #define POWER_SYSTEMOFF_SYSTEMOFF_Enter (1UL) /*!< Enable System OFF mode */
6875 
6876 /* Register: POWER_POFCON */
6877 /* Description: Power failure comparator configuration */
6878 
6879 /* Bits 4..1 : Power failure comparator threshold setting */
6880 #define POWER_POFCON_THRESHOLD_Pos (1UL) /*!< Position of THRESHOLD field. */
6881 #define POWER_POFCON_THRESHOLD_Msk (0xFUL << POWER_POFCON_THRESHOLD_Pos) /*!< Bit mask of THRESHOLD field. */
6882 #define POWER_POFCON_THRESHOLD_V17 (4UL) /*!< Set threshold to 1.7 V */
6883 #define POWER_POFCON_THRESHOLD_V18 (5UL) /*!< Set threshold to 1.8 V */
6884 #define POWER_POFCON_THRESHOLD_V19 (6UL) /*!< Set threshold to 1.9 V */
6885 #define POWER_POFCON_THRESHOLD_V20 (7UL) /*!< Set threshold to 2.0 V */
6886 #define POWER_POFCON_THRESHOLD_V21 (8UL) /*!< Set threshold to 2.1 V */
6887 #define POWER_POFCON_THRESHOLD_V22 (9UL) /*!< Set threshold to 2.2 V */
6888 #define POWER_POFCON_THRESHOLD_V23 (10UL) /*!< Set threshold to 2.3 V */
6889 #define POWER_POFCON_THRESHOLD_V24 (11UL) /*!< Set threshold to 2.4 V */
6890 #define POWER_POFCON_THRESHOLD_V25 (12UL) /*!< Set threshold to 2.5 V */
6891 #define POWER_POFCON_THRESHOLD_V26 (13UL) /*!< Set threshold to 2.6 V */
6892 #define POWER_POFCON_THRESHOLD_V27 (14UL) /*!< Set threshold to 2.7 V */
6893 #define POWER_POFCON_THRESHOLD_V28 (15UL) /*!< Set threshold to 2.8 V */
6894 
6895 /* Bit 0 : Enable or disable power failure comparator */
6896 #define POWER_POFCON_POF_Pos (0UL) /*!< Position of POF field. */
6897 #define POWER_POFCON_POF_Msk (0x1UL << POWER_POFCON_POF_Pos) /*!< Bit mask of POF field. */
6898 #define POWER_POFCON_POF_Disabled (0UL) /*!< Disable */
6899 #define POWER_POFCON_POF_Enabled (1UL) /*!< Enable */
6900 
6901 /* Register: POWER_GPREGRET */
6902 /* Description: General purpose retention register */
6903 
6904 /* Bits 7..0 : General purpose retention register */
6905 #define POWER_GPREGRET_GPREGRET_Pos (0UL) /*!< Position of GPREGRET field. */
6906 #define POWER_GPREGRET_GPREGRET_Msk (0xFFUL << POWER_GPREGRET_GPREGRET_Pos) /*!< Bit mask of GPREGRET field. */
6907 
6908 /* Register: POWER_GPREGRET2 */
6909 /* Description: General purpose retention register */
6910 
6911 /* Bits 7..0 : General purpose retention register */
6912 #define POWER_GPREGRET2_GPREGRET_Pos (0UL) /*!< Position of GPREGRET field. */
6913 #define POWER_GPREGRET2_GPREGRET_Msk (0xFFUL << POWER_GPREGRET2_GPREGRET_Pos) /*!< Bit mask of GPREGRET field. */
6914 
6915 /* Register: POWER_RAMON */
6916 /* Description: Deprecated register -  RAM on/off register (this register is retained) */
6917 
6918 /* Bit 17 : Keep retention on RAM block 1 when RAM block is switched off */
6919 #define POWER_RAMON_OFFRAM1_Pos (17UL) /*!< Position of OFFRAM1 field. */
6920 #define POWER_RAMON_OFFRAM1_Msk (0x1UL << POWER_RAMON_OFFRAM1_Pos) /*!< Bit mask of OFFRAM1 field. */
6921 #define POWER_RAMON_OFFRAM1_RAM1Off (0UL) /*!< Off */
6922 #define POWER_RAMON_OFFRAM1_RAM1On (1UL) /*!< On */
6923 
6924 /* Bit 16 : Keep retention on RAM block 0 when RAM block is switched off */
6925 #define POWER_RAMON_OFFRAM0_Pos (16UL) /*!< Position of OFFRAM0 field. */
6926 #define POWER_RAMON_OFFRAM0_Msk (0x1UL << POWER_RAMON_OFFRAM0_Pos) /*!< Bit mask of OFFRAM0 field. */
6927 #define POWER_RAMON_OFFRAM0_RAM0Off (0UL) /*!< Off */
6928 #define POWER_RAMON_OFFRAM0_RAM0On (1UL) /*!< On */
6929 
6930 /* Bit 1 : Keep RAM block 1 on or off in system ON Mode */
6931 #define POWER_RAMON_ONRAM1_Pos (1UL) /*!< Position of ONRAM1 field. */
6932 #define POWER_RAMON_ONRAM1_Msk (0x1UL << POWER_RAMON_ONRAM1_Pos) /*!< Bit mask of ONRAM1 field. */
6933 #define POWER_RAMON_ONRAM1_RAM1Off (0UL) /*!< Off */
6934 #define POWER_RAMON_ONRAM1_RAM1On (1UL) /*!< On */
6935 
6936 /* Bit 0 : Keep RAM block 0 on or off in system ON Mode */
6937 #define POWER_RAMON_ONRAM0_Pos (0UL) /*!< Position of ONRAM0 field. */
6938 #define POWER_RAMON_ONRAM0_Msk (0x1UL << POWER_RAMON_ONRAM0_Pos) /*!< Bit mask of ONRAM0 field. */
6939 #define POWER_RAMON_ONRAM0_RAM0Off (0UL) /*!< Off */
6940 #define POWER_RAMON_ONRAM0_RAM0On (1UL) /*!< On */
6941 
6942 /* Register: POWER_RAMONB */
6943 /* Description: Deprecated register -  RAM on/off register (this register is retained) */
6944 
6945 /* Bit 17 : Keep retention on RAM block 3 when RAM block is switched off */
6946 #define POWER_RAMONB_OFFRAM3_Pos (17UL) /*!< Position of OFFRAM3 field. */
6947 #define POWER_RAMONB_OFFRAM3_Msk (0x1UL << POWER_RAMONB_OFFRAM3_Pos) /*!< Bit mask of OFFRAM3 field. */
6948 #define POWER_RAMONB_OFFRAM3_RAM3Off (0UL) /*!< Off */
6949 #define POWER_RAMONB_OFFRAM3_RAM3On (1UL) /*!< On */
6950 
6951 /* Bit 16 : Keep retention on RAM block 2 when RAM block is switched off */
6952 #define POWER_RAMONB_OFFRAM2_Pos (16UL) /*!< Position of OFFRAM2 field. */
6953 #define POWER_RAMONB_OFFRAM2_Msk (0x1UL << POWER_RAMONB_OFFRAM2_Pos) /*!< Bit mask of OFFRAM2 field. */
6954 #define POWER_RAMONB_OFFRAM2_RAM2Off (0UL) /*!< Off */
6955 #define POWER_RAMONB_OFFRAM2_RAM2On (1UL) /*!< On */
6956 
6957 /* Bit 1 : Keep RAM block 3 on or off in system ON Mode */
6958 #define POWER_RAMONB_ONRAM3_Pos (1UL) /*!< Position of ONRAM3 field. */
6959 #define POWER_RAMONB_ONRAM3_Msk (0x1UL << POWER_RAMONB_ONRAM3_Pos) /*!< Bit mask of ONRAM3 field. */
6960 #define POWER_RAMONB_ONRAM3_RAM3Off (0UL) /*!< Off */
6961 #define POWER_RAMONB_ONRAM3_RAM3On (1UL) /*!< On */
6962 
6963 /* Bit 0 : Keep RAM block 2 on or off in system ON Mode */
6964 #define POWER_RAMONB_ONRAM2_Pos (0UL) /*!< Position of ONRAM2 field. */
6965 #define POWER_RAMONB_ONRAM2_Msk (0x1UL << POWER_RAMONB_ONRAM2_Pos) /*!< Bit mask of ONRAM2 field. */
6966 #define POWER_RAMONB_ONRAM2_RAM2Off (0UL) /*!< Off */
6967 #define POWER_RAMONB_ONRAM2_RAM2On (1UL) /*!< On */
6968 
6969 /* Register: POWER_DCDCEN */
6970 /* Description: DC/DC enable register */
6971 
6972 /* Bit 0 : Enable or disable DC/DC converter */
6973 #define POWER_DCDCEN_DCDCEN_Pos (0UL) /*!< Position of DCDCEN field. */
6974 #define POWER_DCDCEN_DCDCEN_Msk (0x1UL << POWER_DCDCEN_DCDCEN_Pos) /*!< Bit mask of DCDCEN field. */
6975 #define POWER_DCDCEN_DCDCEN_Disabled (0UL) /*!< Disable */
6976 #define POWER_DCDCEN_DCDCEN_Enabled (1UL) /*!< Enable */
6977 
6978 /* Register: POWER_RAM_POWER */
6979 /* Description: Description cluster[0]:  RAM0 power control register */
6980 
6981 /* Bit 17 : Keep retention on RAM section S1 when RAM section is in OFF */
6982 #define POWER_RAM_POWER_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */
6983 #define POWER_RAM_POWER_S1RETENTION_Msk (0x1UL << POWER_RAM_POWER_S1RETENTION_Pos) /*!< Bit mask of S1RETENTION field. */
6984 #define POWER_RAM_POWER_S1RETENTION_Off (0UL) /*!< Off */
6985 #define POWER_RAM_POWER_S1RETENTION_On (1UL) /*!< On */
6986 
6987 /* Bit 16 : Keep retention on RAM section S0 when RAM section is in OFF */
6988 #define POWER_RAM_POWER_S0RETENTION_Pos (16UL) /*!< Position of S0RETENTION field. */
6989 #define POWER_RAM_POWER_S0RETENTION_Msk (0x1UL << POWER_RAM_POWER_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */
6990 #define POWER_RAM_POWER_S0RETENTION_Off (0UL) /*!< Off */
6991 #define POWER_RAM_POWER_S0RETENTION_On (1UL) /*!< On */
6992 
6993 /* Bit 1 : Keep RAM section S1 ON or OFF in System ON mode. */
6994 #define POWER_RAM_POWER_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */
6995 #define POWER_RAM_POWER_S1POWER_Msk (0x1UL << POWER_RAM_POWER_S1POWER_Pos) /*!< Bit mask of S1POWER field. */
6996 #define POWER_RAM_POWER_S1POWER_Off (0UL) /*!< Off */
6997 #define POWER_RAM_POWER_S1POWER_On (1UL) /*!< On */
6998 
6999 /* Bit 0 : Keep RAM section S0 ON or OFF in System ON mode. */
7000 #define POWER_RAM_POWER_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */
7001 #define POWER_RAM_POWER_S0POWER_Msk (0x1UL << POWER_RAM_POWER_S0POWER_Pos) /*!< Bit mask of S0POWER field. */
7002 #define POWER_RAM_POWER_S0POWER_Off (0UL) /*!< Off */
7003 #define POWER_RAM_POWER_S0POWER_On (1UL) /*!< On */
7004 
7005 /* Register: POWER_RAM_POWERSET */
7006 /* Description: Description cluster[0]:  RAM0 power control set register */
7007 
7008 /* Bit 17 : Keep retention on RAM section S1 when RAM section is switched off */
7009 #define POWER_RAM_POWERSET_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */
7010 #define POWER_RAM_POWERSET_S1RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S1RETENTION_Pos) /*!< Bit mask of S1RETENTION field. */
7011 #define POWER_RAM_POWERSET_S1RETENTION_On (1UL) /*!< On */
7012 
7013 /* Bit 16 : Keep retention on RAM section S0 when RAM section is switched off */
7014 #define POWER_RAM_POWERSET_S0RETENTION_Pos (16UL) /*!< Position of S0RETENTION field. */
7015 #define POWER_RAM_POWERSET_S0RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */
7016 #define POWER_RAM_POWERSET_S0RETENTION_On (1UL) /*!< On */
7017 
7018 /* Bit 1 : Keep RAM section S1 of RAM0 on or off in System ON mode */
7019 #define POWER_RAM_POWERSET_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */
7020 #define POWER_RAM_POWERSET_S1POWER_Msk (0x1UL << POWER_RAM_POWERSET_S1POWER_Pos) /*!< Bit mask of S1POWER field. */
7021 #define POWER_RAM_POWERSET_S1POWER_On (1UL) /*!< On */
7022 
7023 /* Bit 0 : Keep RAM section S0 of RAM0 on or off in System ON mode */
7024 #define POWER_RAM_POWERSET_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */
7025 #define POWER_RAM_POWERSET_S0POWER_Msk (0x1UL << POWER_RAM_POWERSET_S0POWER_Pos) /*!< Bit mask of S0POWER field. */
7026 #define POWER_RAM_POWERSET_S0POWER_On (1UL) /*!< On */
7027 
7028 /* Register: POWER_RAM_POWERCLR */
7029 /* Description: Description cluster[0]:  RAM0 power control clear register */
7030 
7031 /* Bit 17 : Keep retention on RAM section S1 when RAM section is switched off */
7032 #define POWER_RAM_POWERCLR_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */
7033 #define POWER_RAM_POWERCLR_S1RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S1RETENTION_Pos) /*!< Bit mask of S1RETENTION field. */
7034 #define POWER_RAM_POWERCLR_S1RETENTION_Off (1UL) /*!< Off */
7035 
7036 /* Bit 16 : Keep retention on RAM section S0 when RAM section is switched off */
7037 #define POWER_RAM_POWERCLR_S0RETENTION_Pos (16UL) /*!< Position of S0RETENTION field. */
7038 #define POWER_RAM_POWERCLR_S0RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */
7039 #define POWER_RAM_POWERCLR_S0RETENTION_Off (1UL) /*!< Off */
7040 
7041 /* Bit 1 : Keep RAM section S1 of RAM0 on or off in System ON mode */
7042 #define POWER_RAM_POWERCLR_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */
7043 #define POWER_RAM_POWERCLR_S1POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S1POWER_Pos) /*!< Bit mask of S1POWER field. */
7044 #define POWER_RAM_POWERCLR_S1POWER_Off (1UL) /*!< Off */
7045 
7046 /* Bit 0 : Keep RAM section S0 of RAM0 on or off in System ON mode */
7047 #define POWER_RAM_POWERCLR_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */
7048 #define POWER_RAM_POWERCLR_S0POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S0POWER_Pos) /*!< Bit mask of S0POWER field. */
7049 #define POWER_RAM_POWERCLR_S0POWER_Off (1UL) /*!< Off */
7050 
7051 
7052 /* Peripheral: PPI */
7053 /* Description: Programmable Peripheral Interconnect */
7054 
7055 /* Register: PPI_CHEN */
7056 /* Description: Channel enable register */
7057 
7058 /* Bit 31 : Enable or disable channel 31 */
7059 #define PPI_CHEN_CH31_Pos (31UL) /*!< Position of CH31 field. */
7060 #define PPI_CHEN_CH31_Msk (0x1UL << PPI_CHEN_CH31_Pos) /*!< Bit mask of CH31 field. */
7061 #define PPI_CHEN_CH31_Disabled (0UL) /*!< Disable channel */
7062 #define PPI_CHEN_CH31_Enabled (1UL) /*!< Enable channel */
7063 
7064 /* Bit 30 : Enable or disable channel 30 */
7065 #define PPI_CHEN_CH30_Pos (30UL) /*!< Position of CH30 field. */
7066 #define PPI_CHEN_CH30_Msk (0x1UL << PPI_CHEN_CH30_Pos) /*!< Bit mask of CH30 field. */
7067 #define PPI_CHEN_CH30_Disabled (0UL) /*!< Disable channel */
7068 #define PPI_CHEN_CH30_Enabled (1UL) /*!< Enable channel */
7069 
7070 /* Bit 29 : Enable or disable channel 29 */
7071 #define PPI_CHEN_CH29_Pos (29UL) /*!< Position of CH29 field. */
7072 #define PPI_CHEN_CH29_Msk (0x1UL << PPI_CHEN_CH29_Pos) /*!< Bit mask of CH29 field. */
7073 #define PPI_CHEN_CH29_Disabled (0UL) /*!< Disable channel */
7074 #define PPI_CHEN_CH29_Enabled (1UL) /*!< Enable channel */
7075 
7076 /* Bit 28 : Enable or disable channel 28 */
7077 #define PPI_CHEN_CH28_Pos (28UL) /*!< Position of CH28 field. */
7078 #define PPI_CHEN_CH28_Msk (0x1UL << PPI_CHEN_CH28_Pos) /*!< Bit mask of CH28 field. */
7079 #define PPI_CHEN_CH28_Disabled (0UL) /*!< Disable channel */
7080 #define PPI_CHEN_CH28_Enabled (1UL) /*!< Enable channel */
7081 
7082 /* Bit 27 : Enable or disable channel 27 */
7083 #define PPI_CHEN_CH27_Pos (27UL) /*!< Position of CH27 field. */
7084 #define PPI_CHEN_CH27_Msk (0x1UL << PPI_CHEN_CH27_Pos) /*!< Bit mask of CH27 field. */
7085 #define PPI_CHEN_CH27_Disabled (0UL) /*!< Disable channel */
7086 #define PPI_CHEN_CH27_Enabled (1UL) /*!< Enable channel */
7087 
7088 /* Bit 26 : Enable or disable channel 26 */
7089 #define PPI_CHEN_CH26_Pos (26UL) /*!< Position of CH26 field. */
7090 #define PPI_CHEN_CH26_Msk (0x1UL << PPI_CHEN_CH26_Pos) /*!< Bit mask of CH26 field. */
7091 #define PPI_CHEN_CH26_Disabled (0UL) /*!< Disable channel */
7092 #define PPI_CHEN_CH26_Enabled (1UL) /*!< Enable channel */
7093 
7094 /* Bit 25 : Enable or disable channel 25 */
7095 #define PPI_CHEN_CH25_Pos (25UL) /*!< Position of CH25 field. */
7096 #define PPI_CHEN_CH25_Msk (0x1UL << PPI_CHEN_CH25_Pos) /*!< Bit mask of CH25 field. */
7097 #define PPI_CHEN_CH25_Disabled (0UL) /*!< Disable channel */
7098 #define PPI_CHEN_CH25_Enabled (1UL) /*!< Enable channel */
7099 
7100 /* Bit 24 : Enable or disable channel 24 */
7101 #define PPI_CHEN_CH24_Pos (24UL) /*!< Position of CH24 field. */
7102 #define PPI_CHEN_CH24_Msk (0x1UL << PPI_CHEN_CH24_Pos) /*!< Bit mask of CH24 field. */
7103 #define PPI_CHEN_CH24_Disabled (0UL) /*!< Disable channel */
7104 #define PPI_CHEN_CH24_Enabled (1UL) /*!< Enable channel */
7105 
7106 /* Bit 23 : Enable or disable channel 23 */
7107 #define PPI_CHEN_CH23_Pos (23UL) /*!< Position of CH23 field. */
7108 #define PPI_CHEN_CH23_Msk (0x1UL << PPI_CHEN_CH23_Pos) /*!< Bit mask of CH23 field. */
7109 #define PPI_CHEN_CH23_Disabled (0UL) /*!< Disable channel */
7110 #define PPI_CHEN_CH23_Enabled (1UL) /*!< Enable channel */
7111 
7112 /* Bit 22 : Enable or disable channel 22 */
7113 #define PPI_CHEN_CH22_Pos (22UL) /*!< Position of CH22 field. */
7114 #define PPI_CHEN_CH22_Msk (0x1UL << PPI_CHEN_CH22_Pos) /*!< Bit mask of CH22 field. */
7115 #define PPI_CHEN_CH22_Disabled (0UL) /*!< Disable channel */
7116 #define PPI_CHEN_CH22_Enabled (1UL) /*!< Enable channel */
7117 
7118 /* Bit 21 : Enable or disable channel 21 */
7119 #define PPI_CHEN_CH21_Pos (21UL) /*!< Position of CH21 field. */
7120 #define PPI_CHEN_CH21_Msk (0x1UL << PPI_CHEN_CH21_Pos) /*!< Bit mask of CH21 field. */
7121 #define PPI_CHEN_CH21_Disabled (0UL) /*!< Disable channel */
7122 #define PPI_CHEN_CH21_Enabled (1UL) /*!< Enable channel */
7123 
7124 /* Bit 20 : Enable or disable channel 20 */
7125 #define PPI_CHEN_CH20_Pos (20UL) /*!< Position of CH20 field. */
7126 #define PPI_CHEN_CH20_Msk (0x1UL << PPI_CHEN_CH20_Pos) /*!< Bit mask of CH20 field. */
7127 #define PPI_CHEN_CH20_Disabled (0UL) /*!< Disable channel */
7128 #define PPI_CHEN_CH20_Enabled (1UL) /*!< Enable channel */
7129 
7130 /* Bit 19 : Enable or disable channel 19 */
7131 #define PPI_CHEN_CH19_Pos (19UL) /*!< Position of CH19 field. */
7132 #define PPI_CHEN_CH19_Msk (0x1UL << PPI_CHEN_CH19_Pos) /*!< Bit mask of CH19 field. */
7133 #define PPI_CHEN_CH19_Disabled (0UL) /*!< Disable channel */
7134 #define PPI_CHEN_CH19_Enabled (1UL) /*!< Enable channel */
7135 
7136 /* Bit 18 : Enable or disable channel 18 */
7137 #define PPI_CHEN_CH18_Pos (18UL) /*!< Position of CH18 field. */
7138 #define PPI_CHEN_CH18_Msk (0x1UL << PPI_CHEN_CH18_Pos) /*!< Bit mask of CH18 field. */
7139 #define PPI_CHEN_CH18_Disabled (0UL) /*!< Disable channel */
7140 #define PPI_CHEN_CH18_Enabled (1UL) /*!< Enable channel */
7141 
7142 /* Bit 17 : Enable or disable channel 17 */
7143 #define PPI_CHEN_CH17_Pos (17UL) /*!< Position of CH17 field. */
7144 #define PPI_CHEN_CH17_Msk (0x1UL << PPI_CHEN_CH17_Pos) /*!< Bit mask of CH17 field. */
7145 #define PPI_CHEN_CH17_Disabled (0UL) /*!< Disable channel */
7146 #define PPI_CHEN_CH17_Enabled (1UL) /*!< Enable channel */
7147 
7148 /* Bit 16 : Enable or disable channel 16 */
7149 #define PPI_CHEN_CH16_Pos (16UL) /*!< Position of CH16 field. */
7150 #define PPI_CHEN_CH16_Msk (0x1UL << PPI_CHEN_CH16_Pos) /*!< Bit mask of CH16 field. */
7151 #define PPI_CHEN_CH16_Disabled (0UL) /*!< Disable channel */
7152 #define PPI_CHEN_CH16_Enabled (1UL) /*!< Enable channel */
7153 
7154 /* Bit 15 : Enable or disable channel 15 */
7155 #define PPI_CHEN_CH15_Pos (15UL) /*!< Position of CH15 field. */
7156 #define PPI_CHEN_CH15_Msk (0x1UL << PPI_CHEN_CH15_Pos) /*!< Bit mask of CH15 field. */
7157 #define PPI_CHEN_CH15_Disabled (0UL) /*!< Disable channel */
7158 #define PPI_CHEN_CH15_Enabled (1UL) /*!< Enable channel */
7159 
7160 /* Bit 14 : Enable or disable channel 14 */
7161 #define PPI_CHEN_CH14_Pos (14UL) /*!< Position of CH14 field. */
7162 #define PPI_CHEN_CH14_Msk (0x1UL << PPI_CHEN_CH14_Pos) /*!< Bit mask of CH14 field. */
7163 #define PPI_CHEN_CH14_Disabled (0UL) /*!< Disable channel */
7164 #define PPI_CHEN_CH14_Enabled (1UL) /*!< Enable channel */
7165 
7166 /* Bit 13 : Enable or disable channel 13 */
7167 #define PPI_CHEN_CH13_Pos (13UL) /*!< Position of CH13 field. */
7168 #define PPI_CHEN_CH13_Msk (0x1UL << PPI_CHEN_CH13_Pos) /*!< Bit mask of CH13 field. */
7169 #define PPI_CHEN_CH13_Disabled (0UL) /*!< Disable channel */
7170 #define PPI_CHEN_CH13_Enabled (1UL) /*!< Enable channel */
7171 
7172 /* Bit 12 : Enable or disable channel 12 */
7173 #define PPI_CHEN_CH12_Pos (12UL) /*!< Position of CH12 field. */
7174 #define PPI_CHEN_CH12_Msk (0x1UL << PPI_CHEN_CH12_Pos) /*!< Bit mask of CH12 field. */
7175 #define PPI_CHEN_CH12_Disabled (0UL) /*!< Disable channel */
7176 #define PPI_CHEN_CH12_Enabled (1UL) /*!< Enable channel */
7177 
7178 /* Bit 11 : Enable or disable channel 11 */
7179 #define PPI_CHEN_CH11_Pos (11UL) /*!< Position of CH11 field. */
7180 #define PPI_CHEN_CH11_Msk (0x1UL << PPI_CHEN_CH11_Pos) /*!< Bit mask of CH11 field. */
7181 #define PPI_CHEN_CH11_Disabled (0UL) /*!< Disable channel */
7182 #define PPI_CHEN_CH11_Enabled (1UL) /*!< Enable channel */
7183 
7184 /* Bit 10 : Enable or disable channel 10 */
7185 #define PPI_CHEN_CH10_Pos (10UL) /*!< Position of CH10 field. */
7186 #define PPI_CHEN_CH10_Msk (0x1UL << PPI_CHEN_CH10_Pos) /*!< Bit mask of CH10 field. */
7187 #define PPI_CHEN_CH10_Disabled (0UL) /*!< Disable channel */
7188 #define PPI_CHEN_CH10_Enabled (1UL) /*!< Enable channel */
7189 
7190 /* Bit 9 : Enable or disable channel 9 */
7191 #define PPI_CHEN_CH9_Pos (9UL) /*!< Position of CH9 field. */
7192 #define PPI_CHEN_CH9_Msk (0x1UL << PPI_CHEN_CH9_Pos) /*!< Bit mask of CH9 field. */
7193 #define PPI_CHEN_CH9_Disabled (0UL) /*!< Disable channel */
7194 #define PPI_CHEN_CH9_Enabled (1UL) /*!< Enable channel */
7195 
7196 /* Bit 8 : Enable or disable channel 8 */
7197 #define PPI_CHEN_CH8_Pos (8UL) /*!< Position of CH8 field. */
7198 #define PPI_CHEN_CH8_Msk (0x1UL << PPI_CHEN_CH8_Pos) /*!< Bit mask of CH8 field. */
7199 #define PPI_CHEN_CH8_Disabled (0UL) /*!< Disable channel */
7200 #define PPI_CHEN_CH8_Enabled (1UL) /*!< Enable channel */
7201 
7202 /* Bit 7 : Enable or disable channel 7 */
7203 #define PPI_CHEN_CH7_Pos (7UL) /*!< Position of CH7 field. */
7204 #define PPI_CHEN_CH7_Msk (0x1UL << PPI_CHEN_CH7_Pos) /*!< Bit mask of CH7 field. */
7205 #define PPI_CHEN_CH7_Disabled (0UL) /*!< Disable channel */
7206 #define PPI_CHEN_CH7_Enabled (1UL) /*!< Enable channel */
7207 
7208 /* Bit 6 : Enable or disable channel 6 */
7209 #define PPI_CHEN_CH6_Pos (6UL) /*!< Position of CH6 field. */
7210 #define PPI_CHEN_CH6_Msk (0x1UL << PPI_CHEN_CH6_Pos) /*!< Bit mask of CH6 field. */
7211 #define PPI_CHEN_CH6_Disabled (0UL) /*!< Disable channel */
7212 #define PPI_CHEN_CH6_Enabled (1UL) /*!< Enable channel */
7213 
7214 /* Bit 5 : Enable or disable channel 5 */
7215 #define PPI_CHEN_CH5_Pos (5UL) /*!< Position of CH5 field. */
7216 #define PPI_CHEN_CH5_Msk (0x1UL << PPI_CHEN_CH5_Pos) /*!< Bit mask of CH5 field. */
7217 #define PPI_CHEN_CH5_Disabled (0UL) /*!< Disable channel */
7218 #define PPI_CHEN_CH5_Enabled (1UL) /*!< Enable channel */
7219 
7220 /* Bit 4 : Enable or disable channel 4 */
7221 #define PPI_CHEN_CH4_Pos (4UL) /*!< Position of CH4 field. */
7222 #define PPI_CHEN_CH4_Msk (0x1UL << PPI_CHEN_CH4_Pos) /*!< Bit mask of CH4 field. */
7223 #define PPI_CHEN_CH4_Disabled (0UL) /*!< Disable channel */
7224 #define PPI_CHEN_CH4_Enabled (1UL) /*!< Enable channel */
7225 
7226 /* Bit 3 : Enable or disable channel 3 */
7227 #define PPI_CHEN_CH3_Pos (3UL) /*!< Position of CH3 field. */
7228 #define PPI_CHEN_CH3_Msk (0x1UL << PPI_CHEN_CH3_Pos) /*!< Bit mask of CH3 field. */
7229 #define PPI_CHEN_CH3_Disabled (0UL) /*!< Disable channel */
7230 #define PPI_CHEN_CH3_Enabled (1UL) /*!< Enable channel */
7231 
7232 /* Bit 2 : Enable or disable channel 2 */
7233 #define PPI_CHEN_CH2_Pos (2UL) /*!< Position of CH2 field. */
7234 #define PPI_CHEN_CH2_Msk (0x1UL << PPI_CHEN_CH2_Pos) /*!< Bit mask of CH2 field. */
7235 #define PPI_CHEN_CH2_Disabled (0UL) /*!< Disable channel */
7236 #define PPI_CHEN_CH2_Enabled (1UL) /*!< Enable channel */
7237 
7238 /* Bit 1 : Enable or disable channel 1 */
7239 #define PPI_CHEN_CH1_Pos (1UL) /*!< Position of CH1 field. */
7240 #define PPI_CHEN_CH1_Msk (0x1UL << PPI_CHEN_CH1_Pos) /*!< Bit mask of CH1 field. */
7241 #define PPI_CHEN_CH1_Disabled (0UL) /*!< Disable channel */
7242 #define PPI_CHEN_CH1_Enabled (1UL) /*!< Enable channel */
7243 
7244 /* Bit 0 : Enable or disable channel 0 */
7245 #define PPI_CHEN_CH0_Pos (0UL) /*!< Position of CH0 field. */
7246 #define PPI_CHEN_CH0_Msk (0x1UL << PPI_CHEN_CH0_Pos) /*!< Bit mask of CH0 field. */
7247 #define PPI_CHEN_CH0_Disabled (0UL) /*!< Disable channel */
7248 #define PPI_CHEN_CH0_Enabled (1UL) /*!< Enable channel */
7249 
7250 /* Register: PPI_CHENSET */
7251 /* Description: Channel enable set register */
7252 
7253 /* Bit 31 : Channel 31 enable set register.  Writing '0' has no effect */
7254 #define PPI_CHENSET_CH31_Pos (31UL) /*!< Position of CH31 field. */
7255 #define PPI_CHENSET_CH31_Msk (0x1UL << PPI_CHENSET_CH31_Pos) /*!< Bit mask of CH31 field. */
7256 #define PPI_CHENSET_CH31_Disabled (0UL) /*!< Read: channel disabled */
7257 #define PPI_CHENSET_CH31_Enabled (1UL) /*!< Read: channel enabled */
7258 #define PPI_CHENSET_CH31_Set (1UL) /*!< Write: Enable channel */
7259 
7260 /* Bit 30 : Channel 30 enable set register.  Writing '0' has no effect */
7261 #define PPI_CHENSET_CH30_Pos (30UL) /*!< Position of CH30 field. */
7262 #define PPI_CHENSET_CH30_Msk (0x1UL << PPI_CHENSET_CH30_Pos) /*!< Bit mask of CH30 field. */
7263 #define PPI_CHENSET_CH30_Disabled (0UL) /*!< Read: channel disabled */
7264 #define PPI_CHENSET_CH30_Enabled (1UL) /*!< Read: channel enabled */
7265 #define PPI_CHENSET_CH30_Set (1UL) /*!< Write: Enable channel */
7266 
7267 /* Bit 29 : Channel 29 enable set register.  Writing '0' has no effect */
7268 #define PPI_CHENSET_CH29_Pos (29UL) /*!< Position of CH29 field. */
7269 #define PPI_CHENSET_CH29_Msk (0x1UL << PPI_CHENSET_CH29_Pos) /*!< Bit mask of CH29 field. */
7270 #define PPI_CHENSET_CH29_Disabled (0UL) /*!< Read: channel disabled */
7271 #define PPI_CHENSET_CH29_Enabled (1UL) /*!< Read: channel enabled */
7272 #define PPI_CHENSET_CH29_Set (1UL) /*!< Write: Enable channel */
7273 
7274 /* Bit 28 : Channel 28 enable set register.  Writing '0' has no effect */
7275 #define PPI_CHENSET_CH28_Pos (28UL) /*!< Position of CH28 field. */
7276 #define PPI_CHENSET_CH28_Msk (0x1UL << PPI_CHENSET_CH28_Pos) /*!< Bit mask of CH28 field. */
7277 #define PPI_CHENSET_CH28_Disabled (0UL) /*!< Read: channel disabled */
7278 #define PPI_CHENSET_CH28_Enabled (1UL) /*!< Read: channel enabled */
7279 #define PPI_CHENSET_CH28_Set (1UL) /*!< Write: Enable channel */
7280 
7281 /* Bit 27 : Channel 27 enable set register.  Writing '0' has no effect */
7282 #define PPI_CHENSET_CH27_Pos (27UL) /*!< Position of CH27 field. */
7283 #define PPI_CHENSET_CH27_Msk (0x1UL << PPI_CHENSET_CH27_Pos) /*!< Bit mask of CH27 field. */
7284 #define PPI_CHENSET_CH27_Disabled (0UL) /*!< Read: channel disabled */
7285 #define PPI_CHENSET_CH27_Enabled (1UL) /*!< Read: channel enabled */
7286 #define PPI_CHENSET_CH27_Set (1UL) /*!< Write: Enable channel */
7287 
7288 /* Bit 26 : Channel 26 enable set register.  Writing '0' has no effect */
7289 #define PPI_CHENSET_CH26_Pos (26UL) /*!< Position of CH26 field. */
7290 #define PPI_CHENSET_CH26_Msk (0x1UL << PPI_CHENSET_CH26_Pos) /*!< Bit mask of CH26 field. */
7291 #define PPI_CHENSET_CH26_Disabled (0UL) /*!< Read: channel disabled */
7292 #define PPI_CHENSET_CH26_Enabled (1UL) /*!< Read: channel enabled */
7293 #define PPI_CHENSET_CH26_Set (1UL) /*!< Write: Enable channel */
7294 
7295 /* Bit 25 : Channel 25 enable set register.  Writing '0' has no effect */
7296 #define PPI_CHENSET_CH25_Pos (25UL) /*!< Position of CH25 field. */
7297 #define PPI_CHENSET_CH25_Msk (0x1UL << PPI_CHENSET_CH25_Pos) /*!< Bit mask of CH25 field. */
7298 #define PPI_CHENSET_CH25_Disabled (0UL) /*!< Read: channel disabled */
7299 #define PPI_CHENSET_CH25_Enabled (1UL) /*!< Read: channel enabled */
7300 #define PPI_CHENSET_CH25_Set (1UL) /*!< Write: Enable channel */
7301 
7302 /* Bit 24 : Channel 24 enable set register.  Writing '0' has no effect */
7303 #define PPI_CHENSET_CH24_Pos (24UL) /*!< Position of CH24 field. */
7304 #define PPI_CHENSET_CH24_Msk (0x1UL << PPI_CHENSET_CH24_Pos) /*!< Bit mask of CH24 field. */
7305 #define PPI_CHENSET_CH24_Disabled (0UL) /*!< Read: channel disabled */
7306 #define PPI_CHENSET_CH24_Enabled (1UL) /*!< Read: channel enabled */
7307 #define PPI_CHENSET_CH24_Set (1UL) /*!< Write: Enable channel */
7308 
7309 /* Bit 23 : Channel 23 enable set register.  Writing '0' has no effect */
7310 #define PPI_CHENSET_CH23_Pos (23UL) /*!< Position of CH23 field. */
7311 #define PPI_CHENSET_CH23_Msk (0x1UL << PPI_CHENSET_CH23_Pos) /*!< Bit mask of CH23 field. */
7312 #define PPI_CHENSET_CH23_Disabled (0UL) /*!< Read: channel disabled */
7313 #define PPI_CHENSET_CH23_Enabled (1UL) /*!< Read: channel enabled */
7314 #define PPI_CHENSET_CH23_Set (1UL) /*!< Write: Enable channel */
7315 
7316 /* Bit 22 : Channel 22 enable set register.  Writing '0' has no effect */
7317 #define PPI_CHENSET_CH22_Pos (22UL) /*!< Position of CH22 field. */
7318 #define PPI_CHENSET_CH22_Msk (0x1UL << PPI_CHENSET_CH22_Pos) /*!< Bit mask of CH22 field. */
7319 #define PPI_CHENSET_CH22_Disabled (0UL) /*!< Read: channel disabled */
7320 #define PPI_CHENSET_CH22_Enabled (1UL) /*!< Read: channel enabled */
7321 #define PPI_CHENSET_CH22_Set (1UL) /*!< Write: Enable channel */
7322 
7323 /* Bit 21 : Channel 21 enable set register.  Writing '0' has no effect */
7324 #define PPI_CHENSET_CH21_Pos (21UL) /*!< Position of CH21 field. */
7325 #define PPI_CHENSET_CH21_Msk (0x1UL << PPI_CHENSET_CH21_Pos) /*!< Bit mask of CH21 field. */
7326 #define PPI_CHENSET_CH21_Disabled (0UL) /*!< Read: channel disabled */
7327 #define PPI_CHENSET_CH21_Enabled (1UL) /*!< Read: channel enabled */
7328 #define PPI_CHENSET_CH21_Set (1UL) /*!< Write: Enable channel */
7329 
7330 /* Bit 20 : Channel 20 enable set register.  Writing '0' has no effect */
7331 #define PPI_CHENSET_CH20_Pos (20UL) /*!< Position of CH20 field. */
7332 #define PPI_CHENSET_CH20_Msk (0x1UL << PPI_CHENSET_CH20_Pos) /*!< Bit mask of CH20 field. */
7333 #define PPI_CHENSET_CH20_Disabled (0UL) /*!< Read: channel disabled */
7334 #define PPI_CHENSET_CH20_Enabled (1UL) /*!< Read: channel enabled */
7335 #define PPI_CHENSET_CH20_Set (1UL) /*!< Write: Enable channel */
7336 
7337 /* Bit 19 : Channel 19 enable set register.  Writing '0' has no effect */
7338 #define PPI_CHENSET_CH19_Pos (19UL) /*!< Position of CH19 field. */
7339 #define PPI_CHENSET_CH19_Msk (0x1UL << PPI_CHENSET_CH19_Pos) /*!< Bit mask of CH19 field. */
7340 #define PPI_CHENSET_CH19_Disabled (0UL) /*!< Read: channel disabled */
7341 #define PPI_CHENSET_CH19_Enabled (1UL) /*!< Read: channel enabled */
7342 #define PPI_CHENSET_CH19_Set (1UL) /*!< Write: Enable channel */
7343 
7344 /* Bit 18 : Channel 18 enable set register.  Writing '0' has no effect */
7345 #define PPI_CHENSET_CH18_Pos (18UL) /*!< Position of CH18 field. */
7346 #define PPI_CHENSET_CH18_Msk (0x1UL << PPI_CHENSET_CH18_Pos) /*!< Bit mask of CH18 field. */
7347 #define PPI_CHENSET_CH18_Disabled (0UL) /*!< Read: channel disabled */
7348 #define PPI_CHENSET_CH18_Enabled (1UL) /*!< Read: channel enabled */
7349 #define PPI_CHENSET_CH18_Set (1UL) /*!< Write: Enable channel */
7350 
7351 /* Bit 17 : Channel 17 enable set register.  Writing '0' has no effect */
7352 #define PPI_CHENSET_CH17_Pos (17UL) /*!< Position of CH17 field. */
7353 #define PPI_CHENSET_CH17_Msk (0x1UL << PPI_CHENSET_CH17_Pos) /*!< Bit mask of CH17 field. */
7354 #define PPI_CHENSET_CH17_Disabled (0UL) /*!< Read: channel disabled */
7355 #define PPI_CHENSET_CH17_Enabled (1UL) /*!< Read: channel enabled */
7356 #define PPI_CHENSET_CH17_Set (1UL) /*!< Write: Enable channel */
7357 
7358 /* Bit 16 : Channel 16 enable set register.  Writing '0' has no effect */
7359 #define PPI_CHENSET_CH16_Pos (16UL) /*!< Position of CH16 field. */
7360 #define PPI_CHENSET_CH16_Msk (0x1UL << PPI_CHENSET_CH16_Pos) /*!< Bit mask of CH16 field. */
7361 #define PPI_CHENSET_CH16_Disabled (0UL) /*!< Read: channel disabled */
7362 #define PPI_CHENSET_CH16_Enabled (1UL) /*!< Read: channel enabled */
7363 #define PPI_CHENSET_CH16_Set (1UL) /*!< Write: Enable channel */
7364 
7365 /* Bit 15 : Channel 15 enable set register.  Writing '0' has no effect */
7366 #define PPI_CHENSET_CH15_Pos (15UL) /*!< Position of CH15 field. */
7367 #define PPI_CHENSET_CH15_Msk (0x1UL << PPI_CHENSET_CH15_Pos) /*!< Bit mask of CH15 field. */
7368 #define PPI_CHENSET_CH15_Disabled (0UL) /*!< Read: channel disabled */
7369 #define PPI_CHENSET_CH15_Enabled (1UL) /*!< Read: channel enabled */
7370 #define PPI_CHENSET_CH15_Set (1UL) /*!< Write: Enable channel */
7371 
7372 /* Bit 14 : Channel 14 enable set register.  Writing '0' has no effect */
7373 #define PPI_CHENSET_CH14_Pos (14UL) /*!< Position of CH14 field. */
7374 #define PPI_CHENSET_CH14_Msk (0x1UL << PPI_CHENSET_CH14_Pos) /*!< Bit mask of CH14 field. */
7375 #define PPI_CHENSET_CH14_Disabled (0UL) /*!< Read: channel disabled */
7376 #define PPI_CHENSET_CH14_Enabled (1UL) /*!< Read: channel enabled */
7377 #define PPI_CHENSET_CH14_Set (1UL) /*!< Write: Enable channel */
7378 
7379 /* Bit 13 : Channel 13 enable set register.  Writing '0' has no effect */
7380 #define PPI_CHENSET_CH13_Pos (13UL) /*!< Position of CH13 field. */
7381 #define PPI_CHENSET_CH13_Msk (0x1UL << PPI_CHENSET_CH13_Pos) /*!< Bit mask of CH13 field. */
7382 #define PPI_CHENSET_CH13_Disabled (0UL) /*!< Read: channel disabled */
7383 #define PPI_CHENSET_CH13_Enabled (1UL) /*!< Read: channel enabled */
7384 #define PPI_CHENSET_CH13_Set (1UL) /*!< Write: Enable channel */
7385 
7386 /* Bit 12 : Channel 12 enable set register.  Writing '0' has no effect */
7387 #define PPI_CHENSET_CH12_Pos (12UL) /*!< Position of CH12 field. */
7388 #define PPI_CHENSET_CH12_Msk (0x1UL << PPI_CHENSET_CH12_Pos) /*!< Bit mask of CH12 field. */
7389 #define PPI_CHENSET_CH12_Disabled (0UL) /*!< Read: channel disabled */
7390 #define PPI_CHENSET_CH12_Enabled (1UL) /*!< Read: channel enabled */
7391 #define PPI_CHENSET_CH12_Set (1UL) /*!< Write: Enable channel */
7392 
7393 /* Bit 11 : Channel 11 enable set register.  Writing '0' has no effect */
7394 #define PPI_CHENSET_CH11_Pos (11UL) /*!< Position of CH11 field. */
7395 #define PPI_CHENSET_CH11_Msk (0x1UL << PPI_CHENSET_CH11_Pos) /*!< Bit mask of CH11 field. */
7396 #define PPI_CHENSET_CH11_Disabled (0UL) /*!< Read: channel disabled */
7397 #define PPI_CHENSET_CH11_Enabled (1UL) /*!< Read: channel enabled */
7398 #define PPI_CHENSET_CH11_Set (1UL) /*!< Write: Enable channel */
7399 
7400 /* Bit 10 : Channel 10 enable set register.  Writing '0' has no effect */
7401 #define PPI_CHENSET_CH10_Pos (10UL) /*!< Position of CH10 field. */
7402 #define PPI_CHENSET_CH10_Msk (0x1UL << PPI_CHENSET_CH10_Pos) /*!< Bit mask of CH10 field. */
7403 #define PPI_CHENSET_CH10_Disabled (0UL) /*!< Read: channel disabled */
7404 #define PPI_CHENSET_CH10_Enabled (1UL) /*!< Read: channel enabled */
7405 #define PPI_CHENSET_CH10_Set (1UL) /*!< Write: Enable channel */
7406 
7407 /* Bit 9 : Channel 9 enable set register.  Writing '0' has no effect */
7408 #define PPI_CHENSET_CH9_Pos (9UL) /*!< Position of CH9 field. */
7409 #define PPI_CHENSET_CH9_Msk (0x1UL << PPI_CHENSET_CH9_Pos) /*!< Bit mask of CH9 field. */
7410 #define PPI_CHENSET_CH9_Disabled (0UL) /*!< Read: channel disabled */
7411 #define PPI_CHENSET_CH9_Enabled (1UL) /*!< Read: channel enabled */
7412 #define PPI_CHENSET_CH9_Set (1UL) /*!< Write: Enable channel */
7413 
7414 /* Bit 8 : Channel 8 enable set register.  Writing '0' has no effect */
7415 #define PPI_CHENSET_CH8_Pos (8UL) /*!< Position of CH8 field. */
7416 #define PPI_CHENSET_CH8_Msk (0x1UL << PPI_CHENSET_CH8_Pos) /*!< Bit mask of CH8 field. */
7417 #define PPI_CHENSET_CH8_Disabled (0UL) /*!< Read: channel disabled */
7418 #define PPI_CHENSET_CH8_Enabled (1UL) /*!< Read: channel enabled */
7419 #define PPI_CHENSET_CH8_Set (1UL) /*!< Write: Enable channel */
7420 
7421 /* Bit 7 : Channel 7 enable set register.  Writing '0' has no effect */
7422 #define PPI_CHENSET_CH7_Pos (7UL) /*!< Position of CH7 field. */
7423 #define PPI_CHENSET_CH7_Msk (0x1UL << PPI_CHENSET_CH7_Pos) /*!< Bit mask of CH7 field. */
7424 #define PPI_CHENSET_CH7_Disabled (0UL) /*!< Read: channel disabled */
7425 #define PPI_CHENSET_CH7_Enabled (1UL) /*!< Read: channel enabled */
7426 #define PPI_CHENSET_CH7_Set (1UL) /*!< Write: Enable channel */
7427 
7428 /* Bit 6 : Channel 6 enable set register.  Writing '0' has no effect */
7429 #define PPI_CHENSET_CH6_Pos (6UL) /*!< Position of CH6 field. */
7430 #define PPI_CHENSET_CH6_Msk (0x1UL << PPI_CHENSET_CH6_Pos) /*!< Bit mask of CH6 field. */
7431 #define PPI_CHENSET_CH6_Disabled (0UL) /*!< Read: channel disabled */
7432 #define PPI_CHENSET_CH6_Enabled (1UL) /*!< Read: channel enabled */
7433 #define PPI_CHENSET_CH6_Set (1UL) /*!< Write: Enable channel */
7434 
7435 /* Bit 5 : Channel 5 enable set register.  Writing '0' has no effect */
7436 #define PPI_CHENSET_CH5_Pos (5UL) /*!< Position of CH5 field. */
7437 #define PPI_CHENSET_CH5_Msk (0x1UL << PPI_CHENSET_CH5_Pos) /*!< Bit mask of CH5 field. */
7438 #define PPI_CHENSET_CH5_Disabled (0UL) /*!< Read: channel disabled */
7439 #define PPI_CHENSET_CH5_Enabled (1UL) /*!< Read: channel enabled */
7440 #define PPI_CHENSET_CH5_Set (1UL) /*!< Write: Enable channel */
7441 
7442 /* Bit 4 : Channel 4 enable set register.  Writing '0' has no effect */
7443 #define PPI_CHENSET_CH4_Pos (4UL) /*!< Position of CH4 field. */
7444 #define PPI_CHENSET_CH4_Msk (0x1UL << PPI_CHENSET_CH4_Pos) /*!< Bit mask of CH4 field. */
7445 #define PPI_CHENSET_CH4_Disabled (0UL) /*!< Read: channel disabled */
7446 #define PPI_CHENSET_CH4_Enabled (1UL) /*!< Read: channel enabled */
7447 #define PPI_CHENSET_CH4_Set (1UL) /*!< Write: Enable channel */
7448 
7449 /* Bit 3 : Channel 3 enable set register.  Writing '0' has no effect */
7450 #define PPI_CHENSET_CH3_Pos (3UL) /*!< Position of CH3 field. */
7451 #define PPI_CHENSET_CH3_Msk (0x1UL << PPI_CHENSET_CH3_Pos) /*!< Bit mask of CH3 field. */
7452 #define PPI_CHENSET_CH3_Disabled (0UL) /*!< Read: channel disabled */
7453 #define PPI_CHENSET_CH3_Enabled (1UL) /*!< Read: channel enabled */
7454 #define PPI_CHENSET_CH3_Set (1UL) /*!< Write: Enable channel */
7455 
7456 /* Bit 2 : Channel 2 enable set register.  Writing '0' has no effect */
7457 #define PPI_CHENSET_CH2_Pos (2UL) /*!< Position of CH2 field. */
7458 #define PPI_CHENSET_CH2_Msk (0x1UL << PPI_CHENSET_CH2_Pos) /*!< Bit mask of CH2 field. */
7459 #define PPI_CHENSET_CH2_Disabled (0UL) /*!< Read: channel disabled */
7460 #define PPI_CHENSET_CH2_Enabled (1UL) /*!< Read: channel enabled */
7461 #define PPI_CHENSET_CH2_Set (1UL) /*!< Write: Enable channel */
7462 
7463 /* Bit 1 : Channel 1 enable set register.  Writing '0' has no effect */
7464 #define PPI_CHENSET_CH1_Pos (1UL) /*!< Position of CH1 field. */
7465 #define PPI_CHENSET_CH1_Msk (0x1UL << PPI_CHENSET_CH1_Pos) /*!< Bit mask of CH1 field. */
7466 #define PPI_CHENSET_CH1_Disabled (0UL) /*!< Read: channel disabled */
7467 #define PPI_CHENSET_CH1_Enabled (1UL) /*!< Read: channel enabled */
7468 #define PPI_CHENSET_CH1_Set (1UL) /*!< Write: Enable channel */
7469 
7470 /* Bit 0 : Channel 0 enable set register.  Writing '0' has no effect */
7471 #define PPI_CHENSET_CH0_Pos (0UL) /*!< Position of CH0 field. */
7472 #define PPI_CHENSET_CH0_Msk (0x1UL << PPI_CHENSET_CH0_Pos) /*!< Bit mask of CH0 field. */
7473 #define PPI_CHENSET_CH0_Disabled (0UL) /*!< Read: channel disabled */
7474 #define PPI_CHENSET_CH0_Enabled (1UL) /*!< Read: channel enabled */
7475 #define PPI_CHENSET_CH0_Set (1UL) /*!< Write: Enable channel */
7476 
7477 /* Register: PPI_CHENCLR */
7478 /* Description: Channel enable clear register */
7479 
7480 /* Bit 31 : Channel 31 enable clear register.  Writing '0' has no effect */
7481 #define PPI_CHENCLR_CH31_Pos (31UL) /*!< Position of CH31 field. */
7482 #define PPI_CHENCLR_CH31_Msk (0x1UL << PPI_CHENCLR_CH31_Pos) /*!< Bit mask of CH31 field. */
7483 #define PPI_CHENCLR_CH31_Disabled (0UL) /*!< Read: channel disabled */
7484 #define PPI_CHENCLR_CH31_Enabled (1UL) /*!< Read: channel enabled */
7485 #define PPI_CHENCLR_CH31_Clear (1UL) /*!< Write: disable channel */
7486 
7487 /* Bit 30 : Channel 30 enable clear register.  Writing '0' has no effect */
7488 #define PPI_CHENCLR_CH30_Pos (30UL) /*!< Position of CH30 field. */
7489 #define PPI_CHENCLR_CH30_Msk (0x1UL << PPI_CHENCLR_CH30_Pos) /*!< Bit mask of CH30 field. */
7490 #define PPI_CHENCLR_CH30_Disabled (0UL) /*!< Read: channel disabled */
7491 #define PPI_CHENCLR_CH30_Enabled (1UL) /*!< Read: channel enabled */
7492 #define PPI_CHENCLR_CH30_Clear (1UL) /*!< Write: disable channel */
7493 
7494 /* Bit 29 : Channel 29 enable clear register.  Writing '0' has no effect */
7495 #define PPI_CHENCLR_CH29_Pos (29UL) /*!< Position of CH29 field. */
7496 #define PPI_CHENCLR_CH29_Msk (0x1UL << PPI_CHENCLR_CH29_Pos) /*!< Bit mask of CH29 field. */
7497 #define PPI_CHENCLR_CH29_Disabled (0UL) /*!< Read: channel disabled */
7498 #define PPI_CHENCLR_CH29_Enabled (1UL) /*!< Read: channel enabled */
7499 #define PPI_CHENCLR_CH29_Clear (1UL) /*!< Write: disable channel */
7500 
7501 /* Bit 28 : Channel 28 enable clear register.  Writing '0' has no effect */
7502 #define PPI_CHENCLR_CH28_Pos (28UL) /*!< Position of CH28 field. */
7503 #define PPI_CHENCLR_CH28_Msk (0x1UL << PPI_CHENCLR_CH28_Pos) /*!< Bit mask of CH28 field. */
7504 #define PPI_CHENCLR_CH28_Disabled (0UL) /*!< Read: channel disabled */
7505 #define PPI_CHENCLR_CH28_Enabled (1UL) /*!< Read: channel enabled */
7506 #define PPI_CHENCLR_CH28_Clear (1UL) /*!< Write: disable channel */
7507 
7508 /* Bit 27 : Channel 27 enable clear register.  Writing '0' has no effect */
7509 #define PPI_CHENCLR_CH27_Pos (27UL) /*!< Position of CH27 field. */
7510 #define PPI_CHENCLR_CH27_Msk (0x1UL << PPI_CHENCLR_CH27_Pos) /*!< Bit mask of CH27 field. */
7511 #define PPI_CHENCLR_CH27_Disabled (0UL) /*!< Read: channel disabled */
7512 #define PPI_CHENCLR_CH27_Enabled (1UL) /*!< Read: channel enabled */
7513 #define PPI_CHENCLR_CH27_Clear (1UL) /*!< Write: disable channel */
7514 
7515 /* Bit 26 : Channel 26 enable clear register.  Writing '0' has no effect */
7516 #define PPI_CHENCLR_CH26_Pos (26UL) /*!< Position of CH26 field. */
7517 #define PPI_CHENCLR_CH26_Msk (0x1UL << PPI_CHENCLR_CH26_Pos) /*!< Bit mask of CH26 field. */
7518 #define PPI_CHENCLR_CH26_Disabled (0UL) /*!< Read: channel disabled */
7519 #define PPI_CHENCLR_CH26_Enabled (1UL) /*!< Read: channel enabled */
7520 #define PPI_CHENCLR_CH26_Clear (1UL) /*!< Write: disable channel */
7521 
7522 /* Bit 25 : Channel 25 enable clear register.  Writing '0' has no effect */
7523 #define PPI_CHENCLR_CH25_Pos (25UL) /*!< Position of CH25 field. */
7524 #define PPI_CHENCLR_CH25_Msk (0x1UL << PPI_CHENCLR_CH25_Pos) /*!< Bit mask of CH25 field. */
7525 #define PPI_CHENCLR_CH25_Disabled (0UL) /*!< Read: channel disabled */
7526 #define PPI_CHENCLR_CH25_Enabled (1UL) /*!< Read: channel enabled */
7527 #define PPI_CHENCLR_CH25_Clear (1UL) /*!< Write: disable channel */
7528 
7529 /* Bit 24 : Channel 24 enable clear register.  Writing '0' has no effect */
7530 #define PPI_CHENCLR_CH24_Pos (24UL) /*!< Position of CH24 field. */
7531 #define PPI_CHENCLR_CH24_Msk (0x1UL << PPI_CHENCLR_CH24_Pos) /*!< Bit mask of CH24 field. */
7532 #define PPI_CHENCLR_CH24_Disabled (0UL) /*!< Read: channel disabled */
7533 #define PPI_CHENCLR_CH24_Enabled (1UL) /*!< Read: channel enabled */
7534 #define PPI_CHENCLR_CH24_Clear (1UL) /*!< Write: disable channel */
7535 
7536 /* Bit 23 : Channel 23 enable clear register.  Writing '0' has no effect */
7537 #define PPI_CHENCLR_CH23_Pos (23UL) /*!< Position of CH23 field. */
7538 #define PPI_CHENCLR_CH23_Msk (0x1UL << PPI_CHENCLR_CH23_Pos) /*!< Bit mask of CH23 field. */
7539 #define PPI_CHENCLR_CH23_Disabled (0UL) /*!< Read: channel disabled */
7540 #define PPI_CHENCLR_CH23_Enabled (1UL) /*!< Read: channel enabled */
7541 #define PPI_CHENCLR_CH23_Clear (1UL) /*!< Write: disable channel */
7542 
7543 /* Bit 22 : Channel 22 enable clear register.  Writing '0' has no effect */
7544 #define PPI_CHENCLR_CH22_Pos (22UL) /*!< Position of CH22 field. */
7545 #define PPI_CHENCLR_CH22_Msk (0x1UL << PPI_CHENCLR_CH22_Pos) /*!< Bit mask of CH22 field. */
7546 #define PPI_CHENCLR_CH22_Disabled (0UL) /*!< Read: channel disabled */
7547 #define PPI_CHENCLR_CH22_Enabled (1UL) /*!< Read: channel enabled */
7548 #define PPI_CHENCLR_CH22_Clear (1UL) /*!< Write: disable channel */
7549 
7550 /* Bit 21 : Channel 21 enable clear register.  Writing '0' has no effect */
7551 #define PPI_CHENCLR_CH21_Pos (21UL) /*!< Position of CH21 field. */
7552 #define PPI_CHENCLR_CH21_Msk (0x1UL << PPI_CHENCLR_CH21_Pos) /*!< Bit mask of CH21 field. */
7553 #define PPI_CHENCLR_CH21_Disabled (0UL) /*!< Read: channel disabled */
7554 #define PPI_CHENCLR_CH21_Enabled (1UL) /*!< Read: channel enabled */
7555 #define PPI_CHENCLR_CH21_Clear (1UL) /*!< Write: disable channel */
7556 
7557 /* Bit 20 : Channel 20 enable clear register.  Writing '0' has no effect */
7558 #define PPI_CHENCLR_CH20_Pos (20UL) /*!< Position of CH20 field. */
7559 #define PPI_CHENCLR_CH20_Msk (0x1UL << PPI_CHENCLR_CH20_Pos) /*!< Bit mask of CH20 field. */
7560 #define PPI_CHENCLR_CH20_Disabled (0UL) /*!< Read: channel disabled */
7561 #define PPI_CHENCLR_CH20_Enabled (1UL) /*!< Read: channel enabled */
7562 #define PPI_CHENCLR_CH20_Clear (1UL) /*!< Write: disable channel */
7563 
7564 /* Bit 19 : Channel 19 enable clear register.  Writing '0' has no effect */
7565 #define PPI_CHENCLR_CH19_Pos (19UL) /*!< Position of CH19 field. */
7566 #define PPI_CHENCLR_CH19_Msk (0x1UL << PPI_CHENCLR_CH19_Pos) /*!< Bit mask of CH19 field. */
7567 #define PPI_CHENCLR_CH19_Disabled (0UL) /*!< Read: channel disabled */
7568 #define PPI_CHENCLR_CH19_Enabled (1UL) /*!< Read: channel enabled */
7569 #define PPI_CHENCLR_CH19_Clear (1UL) /*!< Write: disable channel */
7570 
7571 /* Bit 18 : Channel 18 enable clear register.  Writing '0' has no effect */
7572 #define PPI_CHENCLR_CH18_Pos (18UL) /*!< Position of CH18 field. */
7573 #define PPI_CHENCLR_CH18_Msk (0x1UL << PPI_CHENCLR_CH18_Pos) /*!< Bit mask of CH18 field. */
7574 #define PPI_CHENCLR_CH18_Disabled (0UL) /*!< Read: channel disabled */
7575 #define PPI_CHENCLR_CH18_Enabled (1UL) /*!< Read: channel enabled */
7576 #define PPI_CHENCLR_CH18_Clear (1UL) /*!< Write: disable channel */
7577 
7578 /* Bit 17 : Channel 17 enable clear register.  Writing '0' has no effect */
7579 #define PPI_CHENCLR_CH17_Pos (17UL) /*!< Position of CH17 field. */
7580 #define PPI_CHENCLR_CH17_Msk (0x1UL << PPI_CHENCLR_CH17_Pos) /*!< Bit mask of CH17 field. */
7581 #define PPI_CHENCLR_CH17_Disabled (0UL) /*!< Read: channel disabled */
7582 #define PPI_CHENCLR_CH17_Enabled (1UL) /*!< Read: channel enabled */
7583 #define PPI_CHENCLR_CH17_Clear (1UL) /*!< Write: disable channel */
7584 
7585 /* Bit 16 : Channel 16 enable clear register.  Writing '0' has no effect */
7586 #define PPI_CHENCLR_CH16_Pos (16UL) /*!< Position of CH16 field. */
7587 #define PPI_CHENCLR_CH16_Msk (0x1UL << PPI_CHENCLR_CH16_Pos) /*!< Bit mask of CH16 field. */
7588 #define PPI_CHENCLR_CH16_Disabled (0UL) /*!< Read: channel disabled */
7589 #define PPI_CHENCLR_CH16_Enabled (1UL) /*!< Read: channel enabled */
7590 #define PPI_CHENCLR_CH16_Clear (1UL) /*!< Write: disable channel */
7591 
7592 /* Bit 15 : Channel 15 enable clear register.  Writing '0' has no effect */
7593 #define PPI_CHENCLR_CH15_Pos (15UL) /*!< Position of CH15 field. */
7594 #define PPI_CHENCLR_CH15_Msk (0x1UL << PPI_CHENCLR_CH15_Pos) /*!< Bit mask of CH15 field. */
7595 #define PPI_CHENCLR_CH15_Disabled (0UL) /*!< Read: channel disabled */
7596 #define PPI_CHENCLR_CH15_Enabled (1UL) /*!< Read: channel enabled */
7597 #define PPI_CHENCLR_CH15_Clear (1UL) /*!< Write: disable channel */
7598 
7599 /* Bit 14 : Channel 14 enable clear register.  Writing '0' has no effect */
7600 #define PPI_CHENCLR_CH14_Pos (14UL) /*!< Position of CH14 field. */
7601 #define PPI_CHENCLR_CH14_Msk (0x1UL << PPI_CHENCLR_CH14_Pos) /*!< Bit mask of CH14 field. */
7602 #define PPI_CHENCLR_CH14_Disabled (0UL) /*!< Read: channel disabled */
7603 #define PPI_CHENCLR_CH14_Enabled (1UL) /*!< Read: channel enabled */
7604 #define PPI_CHENCLR_CH14_Clear (1UL) /*!< Write: disable channel */
7605 
7606 /* Bit 13 : Channel 13 enable clear register.  Writing '0' has no effect */
7607 #define PPI_CHENCLR_CH13_Pos (13UL) /*!< Position of CH13 field. */
7608 #define PPI_CHENCLR_CH13_Msk (0x1UL << PPI_CHENCLR_CH13_Pos) /*!< Bit mask of CH13 field. */
7609 #define PPI_CHENCLR_CH13_Disabled (0UL) /*!< Read: channel disabled */
7610 #define PPI_CHENCLR_CH13_Enabled (1UL) /*!< Read: channel enabled */
7611 #define PPI_CHENCLR_CH13_Clear (1UL) /*!< Write: disable channel */
7612 
7613 /* Bit 12 : Channel 12 enable clear register.  Writing '0' has no effect */
7614 #define PPI_CHENCLR_CH12_Pos (12UL) /*!< Position of CH12 field. */
7615 #define PPI_CHENCLR_CH12_Msk (0x1UL << PPI_CHENCLR_CH12_Pos) /*!< Bit mask of CH12 field. */
7616 #define PPI_CHENCLR_CH12_Disabled (0UL) /*!< Read: channel disabled */
7617 #define PPI_CHENCLR_CH12_Enabled (1UL) /*!< Read: channel enabled */
7618 #define PPI_CHENCLR_CH12_Clear (1UL) /*!< Write: disable channel */
7619 
7620 /* Bit 11 : Channel 11 enable clear register.  Writing '0' has no effect */
7621 #define PPI_CHENCLR_CH11_Pos (11UL) /*!< Position of CH11 field. */
7622 #define PPI_CHENCLR_CH11_Msk (0x1UL << PPI_CHENCLR_CH11_Pos) /*!< Bit mask of CH11 field. */
7623 #define PPI_CHENCLR_CH11_Disabled (0UL) /*!< Read: channel disabled */
7624 #define PPI_CHENCLR_CH11_Enabled (1UL) /*!< Read: channel enabled */
7625 #define PPI_CHENCLR_CH11_Clear (1UL) /*!< Write: disable channel */
7626 
7627 /* Bit 10 : Channel 10 enable clear register.  Writing '0' has no effect */
7628 #define PPI_CHENCLR_CH10_Pos (10UL) /*!< Position of CH10 field. */
7629 #define PPI_CHENCLR_CH10_Msk (0x1UL << PPI_CHENCLR_CH10_Pos) /*!< Bit mask of CH10 field. */
7630 #define PPI_CHENCLR_CH10_Disabled (0UL) /*!< Read: channel disabled */
7631 #define PPI_CHENCLR_CH10_Enabled (1UL) /*!< Read: channel enabled */
7632 #define PPI_CHENCLR_CH10_Clear (1UL) /*!< Write: disable channel */
7633 
7634 /* Bit 9 : Channel 9 enable clear register.  Writing '0' has no effect */
7635 #define PPI_CHENCLR_CH9_Pos (9UL) /*!< Position of CH9 field. */
7636 #define PPI_CHENCLR_CH9_Msk (0x1UL << PPI_CHENCLR_CH9_Pos) /*!< Bit mask of CH9 field. */
7637 #define PPI_CHENCLR_CH9_Disabled (0UL) /*!< Read: channel disabled */
7638 #define PPI_CHENCLR_CH9_Enabled (1UL) /*!< Read: channel enabled */
7639 #define PPI_CHENCLR_CH9_Clear (1UL) /*!< Write: disable channel */
7640 
7641 /* Bit 8 : Channel 8 enable clear register.  Writing '0' has no effect */
7642 #define PPI_CHENCLR_CH8_Pos (8UL) /*!< Position of CH8 field. */
7643 #define PPI_CHENCLR_CH8_Msk (0x1UL << PPI_CHENCLR_CH8_Pos) /*!< Bit mask of CH8 field. */
7644 #define PPI_CHENCLR_CH8_Disabled (0UL) /*!< Read: channel disabled */
7645 #define PPI_CHENCLR_CH8_Enabled (1UL) /*!< Read: channel enabled */
7646 #define PPI_CHENCLR_CH8_Clear (1UL) /*!< Write: disable channel */
7647 
7648 /* Bit 7 : Channel 7 enable clear register.  Writing '0' has no effect */
7649 #define PPI_CHENCLR_CH7_Pos (7UL) /*!< Position of CH7 field. */
7650 #define PPI_CHENCLR_CH7_Msk (0x1UL << PPI_CHENCLR_CH7_Pos) /*!< Bit mask of CH7 field. */
7651 #define PPI_CHENCLR_CH7_Disabled (0UL) /*!< Read: channel disabled */
7652 #define PPI_CHENCLR_CH7_Enabled (1UL) /*!< Read: channel enabled */
7653 #define PPI_CHENCLR_CH7_Clear (1UL) /*!< Write: disable channel */
7654 
7655 /* Bit 6 : Channel 6 enable clear register.  Writing '0' has no effect */
7656 #define PPI_CHENCLR_CH6_Pos (6UL) /*!< Position of CH6 field. */
7657 #define PPI_CHENCLR_CH6_Msk (0x1UL << PPI_CHENCLR_CH6_Pos) /*!< Bit mask of CH6 field. */
7658 #define PPI_CHENCLR_CH6_Disabled (0UL) /*!< Read: channel disabled */
7659 #define PPI_CHENCLR_CH6_Enabled (1UL) /*!< Read: channel enabled */
7660 #define PPI_CHENCLR_CH6_Clear (1UL) /*!< Write: disable channel */
7661 
7662 /* Bit 5 : Channel 5 enable clear register.  Writing '0' has no effect */
7663 #define PPI_CHENCLR_CH5_Pos (5UL) /*!< Position of CH5 field. */
7664 #define PPI_CHENCLR_CH5_Msk (0x1UL << PPI_CHENCLR_CH5_Pos) /*!< Bit mask of CH5 field. */
7665 #define PPI_CHENCLR_CH5_Disabled (0UL) /*!< Read: channel disabled */
7666 #define PPI_CHENCLR_CH5_Enabled (1UL) /*!< Read: channel enabled */
7667 #define PPI_CHENCLR_CH5_Clear (1UL) /*!< Write: disable channel */
7668 
7669 /* Bit 4 : Channel 4 enable clear register.  Writing '0' has no effect */
7670 #define PPI_CHENCLR_CH4_Pos (4UL) /*!< Position of CH4 field. */
7671 #define PPI_CHENCLR_CH4_Msk (0x1UL << PPI_CHENCLR_CH4_Pos) /*!< Bit mask of CH4 field. */
7672 #define PPI_CHENCLR_CH4_Disabled (0UL) /*!< Read: channel disabled */
7673 #define PPI_CHENCLR_CH4_Enabled (1UL) /*!< Read: channel enabled */
7674 #define PPI_CHENCLR_CH4_Clear (1UL) /*!< Write: disable channel */
7675 
7676 /* Bit 3 : Channel 3 enable clear register.  Writing '0' has no effect */
7677 #define PPI_CHENCLR_CH3_Pos (3UL) /*!< Position of CH3 field. */
7678 #define PPI_CHENCLR_CH3_Msk (0x1UL << PPI_CHENCLR_CH3_Pos) /*!< Bit mask of CH3 field. */
7679 #define PPI_CHENCLR_CH3_Disabled (0UL) /*!< Read: channel disabled */
7680 #define PPI_CHENCLR_CH3_Enabled (1UL) /*!< Read: channel enabled */
7681 #define PPI_CHENCLR_CH3_Clear (1UL) /*!< Write: disable channel */
7682 
7683 /* Bit 2 : Channel 2 enable clear register.  Writing '0' has no effect */
7684 #define PPI_CHENCLR_CH2_Pos (2UL) /*!< Position of CH2 field. */
7685 #define PPI_CHENCLR_CH2_Msk (0x1UL << PPI_CHENCLR_CH2_Pos) /*!< Bit mask of CH2 field. */
7686 #define PPI_CHENCLR_CH2_Disabled (0UL) /*!< Read: channel disabled */
7687 #define PPI_CHENCLR_CH2_Enabled (1UL) /*!< Read: channel enabled */
7688 #define PPI_CHENCLR_CH2_Clear (1UL) /*!< Write: disable channel */
7689 
7690 /* Bit 1 : Channel 1 enable clear register.  Writing '0' has no effect */
7691 #define PPI_CHENCLR_CH1_Pos (1UL) /*!< Position of CH1 field. */
7692 #define PPI_CHENCLR_CH1_Msk (0x1UL << PPI_CHENCLR_CH1_Pos) /*!< Bit mask of CH1 field. */
7693 #define PPI_CHENCLR_CH1_Disabled (0UL) /*!< Read: channel disabled */
7694 #define PPI_CHENCLR_CH1_Enabled (1UL) /*!< Read: channel enabled */
7695 #define PPI_CHENCLR_CH1_Clear (1UL) /*!< Write: disable channel */
7696 
7697 /* Bit 0 : Channel 0 enable clear register.  Writing '0' has no effect */
7698 #define PPI_CHENCLR_CH0_Pos (0UL) /*!< Position of CH0 field. */
7699 #define PPI_CHENCLR_CH0_Msk (0x1UL << PPI_CHENCLR_CH0_Pos) /*!< Bit mask of CH0 field. */
7700 #define PPI_CHENCLR_CH0_Disabled (0UL) /*!< Read: channel disabled */
7701 #define PPI_CHENCLR_CH0_Enabled (1UL) /*!< Read: channel enabled */
7702 #define PPI_CHENCLR_CH0_Clear (1UL) /*!< Write: disable channel */
7703 
7704 /* Register: PPI_CH_EEP */
7705 /* Description: Description cluster[0]:  Channel 0 event end-point */
7706 
7707 /* Bits 31..0 : Pointer to event register. Accepts only addresses to registers from the Event group. */
7708 #define PPI_CH_EEP_EEP_Pos (0UL) /*!< Position of EEP field. */
7709 #define PPI_CH_EEP_EEP_Msk (0xFFFFFFFFUL << PPI_CH_EEP_EEP_Pos) /*!< Bit mask of EEP field. */
7710 
7711 /* Register: PPI_CH_TEP */
7712 /* Description: Description cluster[0]:  Channel 0 task end-point */
7713 
7714 /* Bits 31..0 : Pointer to task register. Accepts only addresses to registers from the Task group. */
7715 #define PPI_CH_TEP_TEP_Pos (0UL) /*!< Position of TEP field. */
7716 #define PPI_CH_TEP_TEP_Msk (0xFFFFFFFFUL << PPI_CH_TEP_TEP_Pos) /*!< Bit mask of TEP field. */
7717 
7718 /* Register: PPI_CHG */
7719 /* Description: Description collection[0]:  Channel group 0 */
7720 
7721 /* Bit 31 : Include or exclude channel 31 */
7722 #define PPI_CHG_CH31_Pos (31UL) /*!< Position of CH31 field. */
7723 #define PPI_CHG_CH31_Msk (0x1UL << PPI_CHG_CH31_Pos) /*!< Bit mask of CH31 field. */
7724 #define PPI_CHG_CH31_Excluded (0UL) /*!< Exclude */
7725 #define PPI_CHG_CH31_Included (1UL) /*!< Include */
7726 
7727 /* Bit 30 : Include or exclude channel 30 */
7728 #define PPI_CHG_CH30_Pos (30UL) /*!< Position of CH30 field. */
7729 #define PPI_CHG_CH30_Msk (0x1UL << PPI_CHG_CH30_Pos) /*!< Bit mask of CH30 field. */
7730 #define PPI_CHG_CH30_Excluded (0UL) /*!< Exclude */
7731 #define PPI_CHG_CH30_Included (1UL) /*!< Include */
7732 
7733 /* Bit 29 : Include or exclude channel 29 */
7734 #define PPI_CHG_CH29_Pos (29UL) /*!< Position of CH29 field. */
7735 #define PPI_CHG_CH29_Msk (0x1UL << PPI_CHG_CH29_Pos) /*!< Bit mask of CH29 field. */
7736 #define PPI_CHG_CH29_Excluded (0UL) /*!< Exclude */
7737 #define PPI_CHG_CH29_Included (1UL) /*!< Include */
7738 
7739 /* Bit 28 : Include or exclude channel 28 */
7740 #define PPI_CHG_CH28_Pos (28UL) /*!< Position of CH28 field. */
7741 #define PPI_CHG_CH28_Msk (0x1UL << PPI_CHG_CH28_Pos) /*!< Bit mask of CH28 field. */
7742 #define PPI_CHG_CH28_Excluded (0UL) /*!< Exclude */
7743 #define PPI_CHG_CH28_Included (1UL) /*!< Include */
7744 
7745 /* Bit 27 : Include or exclude channel 27 */
7746 #define PPI_CHG_CH27_Pos (27UL) /*!< Position of CH27 field. */
7747 #define PPI_CHG_CH27_Msk (0x1UL << PPI_CHG_CH27_Pos) /*!< Bit mask of CH27 field. */
7748 #define PPI_CHG_CH27_Excluded (0UL) /*!< Exclude */
7749 #define PPI_CHG_CH27_Included (1UL) /*!< Include */
7750 
7751 /* Bit 26 : Include or exclude channel 26 */
7752 #define PPI_CHG_CH26_Pos (26UL) /*!< Position of CH26 field. */
7753 #define PPI_CHG_CH26_Msk (0x1UL << PPI_CHG_CH26_Pos) /*!< Bit mask of CH26 field. */
7754 #define PPI_CHG_CH26_Excluded (0UL) /*!< Exclude */
7755 #define PPI_CHG_CH26_Included (1UL) /*!< Include */
7756 
7757 /* Bit 25 : Include or exclude channel 25 */
7758 #define PPI_CHG_CH25_Pos (25UL) /*!< Position of CH25 field. */
7759 #define PPI_CHG_CH25_Msk (0x1UL << PPI_CHG_CH25_Pos) /*!< Bit mask of CH25 field. */
7760 #define PPI_CHG_CH25_Excluded (0UL) /*!< Exclude */
7761 #define PPI_CHG_CH25_Included (1UL) /*!< Include */
7762 
7763 /* Bit 24 : Include or exclude channel 24 */
7764 #define PPI_CHG_CH24_Pos (24UL) /*!< Position of CH24 field. */
7765 #define PPI_CHG_CH24_Msk (0x1UL << PPI_CHG_CH24_Pos) /*!< Bit mask of CH24 field. */
7766 #define PPI_CHG_CH24_Excluded (0UL) /*!< Exclude */
7767 #define PPI_CHG_CH24_Included (1UL) /*!< Include */
7768 
7769 /* Bit 23 : Include or exclude channel 23 */
7770 #define PPI_CHG_CH23_Pos (23UL) /*!< Position of CH23 field. */
7771 #define PPI_CHG_CH23_Msk (0x1UL << PPI_CHG_CH23_Pos) /*!< Bit mask of CH23 field. */
7772 #define PPI_CHG_CH23_Excluded (0UL) /*!< Exclude */
7773 #define PPI_CHG_CH23_Included (1UL) /*!< Include */
7774 
7775 /* Bit 22 : Include or exclude channel 22 */
7776 #define PPI_CHG_CH22_Pos (22UL) /*!< Position of CH22 field. */
7777 #define PPI_CHG_CH22_Msk (0x1UL << PPI_CHG_CH22_Pos) /*!< Bit mask of CH22 field. */
7778 #define PPI_CHG_CH22_Excluded (0UL) /*!< Exclude */
7779 #define PPI_CHG_CH22_Included (1UL) /*!< Include */
7780 
7781 /* Bit 21 : Include or exclude channel 21 */
7782 #define PPI_CHG_CH21_Pos (21UL) /*!< Position of CH21 field. */
7783 #define PPI_CHG_CH21_Msk (0x1UL << PPI_CHG_CH21_Pos) /*!< Bit mask of CH21 field. */
7784 #define PPI_CHG_CH21_Excluded (0UL) /*!< Exclude */
7785 #define PPI_CHG_CH21_Included (1UL) /*!< Include */
7786 
7787 /* Bit 20 : Include or exclude channel 20 */
7788 #define PPI_CHG_CH20_Pos (20UL) /*!< Position of CH20 field. */
7789 #define PPI_CHG_CH20_Msk (0x1UL << PPI_CHG_CH20_Pos) /*!< Bit mask of CH20 field. */
7790 #define PPI_CHG_CH20_Excluded (0UL) /*!< Exclude */
7791 #define PPI_CHG_CH20_Included (1UL) /*!< Include */
7792 
7793 /* Bit 19 : Include or exclude channel 19 */
7794 #define PPI_CHG_CH19_Pos (19UL) /*!< Position of CH19 field. */
7795 #define PPI_CHG_CH19_Msk (0x1UL << PPI_CHG_CH19_Pos) /*!< Bit mask of CH19 field. */
7796 #define PPI_CHG_CH19_Excluded (0UL) /*!< Exclude */
7797 #define PPI_CHG_CH19_Included (1UL) /*!< Include */
7798 
7799 /* Bit 18 : Include or exclude channel 18 */
7800 #define PPI_CHG_CH18_Pos (18UL) /*!< Position of CH18 field. */
7801 #define PPI_CHG_CH18_Msk (0x1UL << PPI_CHG_CH18_Pos) /*!< Bit mask of CH18 field. */
7802 #define PPI_CHG_CH18_Excluded (0UL) /*!< Exclude */
7803 #define PPI_CHG_CH18_Included (1UL) /*!< Include */
7804 
7805 /* Bit 17 : Include or exclude channel 17 */
7806 #define PPI_CHG_CH17_Pos (17UL) /*!< Position of CH17 field. */
7807 #define PPI_CHG_CH17_Msk (0x1UL << PPI_CHG_CH17_Pos) /*!< Bit mask of CH17 field. */
7808 #define PPI_CHG_CH17_Excluded (0UL) /*!< Exclude */
7809 #define PPI_CHG_CH17_Included (1UL) /*!< Include */
7810 
7811 /* Bit 16 : Include or exclude channel 16 */
7812 #define PPI_CHG_CH16_Pos (16UL) /*!< Position of CH16 field. */
7813 #define PPI_CHG_CH16_Msk (0x1UL << PPI_CHG_CH16_Pos) /*!< Bit mask of CH16 field. */
7814 #define PPI_CHG_CH16_Excluded (0UL) /*!< Exclude */
7815 #define PPI_CHG_CH16_Included (1UL) /*!< Include */
7816 
7817 /* Bit 15 : Include or exclude channel 15 */
7818 #define PPI_CHG_CH15_Pos (15UL) /*!< Position of CH15 field. */
7819 #define PPI_CHG_CH15_Msk (0x1UL << PPI_CHG_CH15_Pos) /*!< Bit mask of CH15 field. */
7820 #define PPI_CHG_CH15_Excluded (0UL) /*!< Exclude */
7821 #define PPI_CHG_CH15_Included (1UL) /*!< Include */
7822 
7823 /* Bit 14 : Include or exclude channel 14 */
7824 #define PPI_CHG_CH14_Pos (14UL) /*!< Position of CH14 field. */
7825 #define PPI_CHG_CH14_Msk (0x1UL << PPI_CHG_CH14_Pos) /*!< Bit mask of CH14 field. */
7826 #define PPI_CHG_CH14_Excluded (0UL) /*!< Exclude */
7827 #define PPI_CHG_CH14_Included (1UL) /*!< Include */
7828 
7829 /* Bit 13 : Include or exclude channel 13 */
7830 #define PPI_CHG_CH13_Pos (13UL) /*!< Position of CH13 field. */
7831 #define PPI_CHG_CH13_Msk (0x1UL << PPI_CHG_CH13_Pos) /*!< Bit mask of CH13 field. */
7832 #define PPI_CHG_CH13_Excluded (0UL) /*!< Exclude */
7833 #define PPI_CHG_CH13_Included (1UL) /*!< Include */
7834 
7835 /* Bit 12 : Include or exclude channel 12 */
7836 #define PPI_CHG_CH12_Pos (12UL) /*!< Position of CH12 field. */
7837 #define PPI_CHG_CH12_Msk (0x1UL << PPI_CHG_CH12_Pos) /*!< Bit mask of CH12 field. */
7838 #define PPI_CHG_CH12_Excluded (0UL) /*!< Exclude */
7839 #define PPI_CHG_CH12_Included (1UL) /*!< Include */
7840 
7841 /* Bit 11 : Include or exclude channel 11 */
7842 #define PPI_CHG_CH11_Pos (11UL) /*!< Position of CH11 field. */
7843 #define PPI_CHG_CH11_Msk (0x1UL << PPI_CHG_CH11_Pos) /*!< Bit mask of CH11 field. */
7844 #define PPI_CHG_CH11_Excluded (0UL) /*!< Exclude */
7845 #define PPI_CHG_CH11_Included (1UL) /*!< Include */
7846 
7847 /* Bit 10 : Include or exclude channel 10 */
7848 #define PPI_CHG_CH10_Pos (10UL) /*!< Position of CH10 field. */
7849 #define PPI_CHG_CH10_Msk (0x1UL << PPI_CHG_CH10_Pos) /*!< Bit mask of CH10 field. */
7850 #define PPI_CHG_CH10_Excluded (0UL) /*!< Exclude */
7851 #define PPI_CHG_CH10_Included (1UL) /*!< Include */
7852 
7853 /* Bit 9 : Include or exclude channel 9 */
7854 #define PPI_CHG_CH9_Pos (9UL) /*!< Position of CH9 field. */
7855 #define PPI_CHG_CH9_Msk (0x1UL << PPI_CHG_CH9_Pos) /*!< Bit mask of CH9 field. */
7856 #define PPI_CHG_CH9_Excluded (0UL) /*!< Exclude */
7857 #define PPI_CHG_CH9_Included (1UL) /*!< Include */
7858 
7859 /* Bit 8 : Include or exclude channel 8 */
7860 #define PPI_CHG_CH8_Pos (8UL) /*!< Position of CH8 field. */
7861 #define PPI_CHG_CH8_Msk (0x1UL << PPI_CHG_CH8_Pos) /*!< Bit mask of CH8 field. */
7862 #define PPI_CHG_CH8_Excluded (0UL) /*!< Exclude */
7863 #define PPI_CHG_CH8_Included (1UL) /*!< Include */
7864 
7865 /* Bit 7 : Include or exclude channel 7 */
7866 #define PPI_CHG_CH7_Pos (7UL) /*!< Position of CH7 field. */
7867 #define PPI_CHG_CH7_Msk (0x1UL << PPI_CHG_CH7_Pos) /*!< Bit mask of CH7 field. */
7868 #define PPI_CHG_CH7_Excluded (0UL) /*!< Exclude */
7869 #define PPI_CHG_CH7_Included (1UL) /*!< Include */
7870 
7871 /* Bit 6 : Include or exclude channel 6 */
7872 #define PPI_CHG_CH6_Pos (6UL) /*!< Position of CH6 field. */
7873 #define PPI_CHG_CH6_Msk (0x1UL << PPI_CHG_CH6_Pos) /*!< Bit mask of CH6 field. */
7874 #define PPI_CHG_CH6_Excluded (0UL) /*!< Exclude */
7875 #define PPI_CHG_CH6_Included (1UL) /*!< Include */
7876 
7877 /* Bit 5 : Include or exclude channel 5 */
7878 #define PPI_CHG_CH5_Pos (5UL) /*!< Position of CH5 field. */
7879 #define PPI_CHG_CH5_Msk (0x1UL << PPI_CHG_CH5_Pos) /*!< Bit mask of CH5 field. */
7880 #define PPI_CHG_CH5_Excluded (0UL) /*!< Exclude */
7881 #define PPI_CHG_CH5_Included (1UL) /*!< Include */
7882 
7883 /* Bit 4 : Include or exclude channel 4 */
7884 #define PPI_CHG_CH4_Pos (4UL) /*!< Position of CH4 field. */
7885 #define PPI_CHG_CH4_Msk (0x1UL << PPI_CHG_CH4_Pos) /*!< Bit mask of CH4 field. */
7886 #define PPI_CHG_CH4_Excluded (0UL) /*!< Exclude */
7887 #define PPI_CHG_CH4_Included (1UL) /*!< Include */
7888 
7889 /* Bit 3 : Include or exclude channel 3 */
7890 #define PPI_CHG_CH3_Pos (3UL) /*!< Position of CH3 field. */
7891 #define PPI_CHG_CH3_Msk (0x1UL << PPI_CHG_CH3_Pos) /*!< Bit mask of CH3 field. */
7892 #define PPI_CHG_CH3_Excluded (0UL) /*!< Exclude */
7893 #define PPI_CHG_CH3_Included (1UL) /*!< Include */
7894 
7895 /* Bit 2 : Include or exclude channel 2 */
7896 #define PPI_CHG_CH2_Pos (2UL) /*!< Position of CH2 field. */
7897 #define PPI_CHG_CH2_Msk (0x1UL << PPI_CHG_CH2_Pos) /*!< Bit mask of CH2 field. */
7898 #define PPI_CHG_CH2_Excluded (0UL) /*!< Exclude */
7899 #define PPI_CHG_CH2_Included (1UL) /*!< Include */
7900 
7901 /* Bit 1 : Include or exclude channel 1 */
7902 #define PPI_CHG_CH1_Pos (1UL) /*!< Position of CH1 field. */
7903 #define PPI_CHG_CH1_Msk (0x1UL << PPI_CHG_CH1_Pos) /*!< Bit mask of CH1 field. */
7904 #define PPI_CHG_CH1_Excluded (0UL) /*!< Exclude */
7905 #define PPI_CHG_CH1_Included (1UL) /*!< Include */
7906 
7907 /* Bit 0 : Include or exclude channel 0 */
7908 #define PPI_CHG_CH0_Pos (0UL) /*!< Position of CH0 field. */
7909 #define PPI_CHG_CH0_Msk (0x1UL << PPI_CHG_CH0_Pos) /*!< Bit mask of CH0 field. */
7910 #define PPI_CHG_CH0_Excluded (0UL) /*!< Exclude */
7911 #define PPI_CHG_CH0_Included (1UL) /*!< Include */
7912 
7913 /* Register: PPI_FORK_TEP */
7914 /* Description: Description cluster[0]:  Channel 0 task end-point */
7915 
7916 /* Bits 31..0 : Pointer to task register */
7917 #define PPI_FORK_TEP_TEP_Pos (0UL) /*!< Position of TEP field. */
7918 #define PPI_FORK_TEP_TEP_Msk (0xFFFFFFFFUL << PPI_FORK_TEP_TEP_Pos) /*!< Bit mask of TEP field. */
7919 
7920 
7921 /* Peripheral: PWM */
7922 /* Description: Pulse Width Modulation Unit 0 */
7923 
7924 /* Register: PWM_SHORTS */
7925 /* Description: Shortcut register */
7926 
7927 /* Bit 4 : Shortcut between LOOPSDONE event and STOP task */
7928 #define PWM_SHORTS_LOOPSDONE_STOP_Pos (4UL) /*!< Position of LOOPSDONE_STOP field. */
7929 #define PWM_SHORTS_LOOPSDONE_STOP_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_STOP_Pos) /*!< Bit mask of LOOPSDONE_STOP field. */
7930 #define PWM_SHORTS_LOOPSDONE_STOP_Disabled (0UL) /*!< Disable shortcut */
7931 #define PWM_SHORTS_LOOPSDONE_STOP_Enabled (1UL) /*!< Enable shortcut */
7932 
7933 /* Bit 3 : Shortcut between LOOPSDONE event and SEQSTART[1] task */
7934 #define PWM_SHORTS_LOOPSDONE_SEQSTART1_Pos (3UL) /*!< Position of LOOPSDONE_SEQSTART1 field. */
7935 #define PWM_SHORTS_LOOPSDONE_SEQSTART1_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_SEQSTART1_Pos) /*!< Bit mask of LOOPSDONE_SEQSTART1 field. */
7936 #define PWM_SHORTS_LOOPSDONE_SEQSTART1_Disabled (0UL) /*!< Disable shortcut */
7937 #define PWM_SHORTS_LOOPSDONE_SEQSTART1_Enabled (1UL) /*!< Enable shortcut */
7938 
7939 /* Bit 2 : Shortcut between LOOPSDONE event and SEQSTART[0] task */
7940 #define PWM_SHORTS_LOOPSDONE_SEQSTART0_Pos (2UL) /*!< Position of LOOPSDONE_SEQSTART0 field. */
7941 #define PWM_SHORTS_LOOPSDONE_SEQSTART0_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_SEQSTART0_Pos) /*!< Bit mask of LOOPSDONE_SEQSTART0 field. */
7942 #define PWM_SHORTS_LOOPSDONE_SEQSTART0_Disabled (0UL) /*!< Disable shortcut */
7943 #define PWM_SHORTS_LOOPSDONE_SEQSTART0_Enabled (1UL) /*!< Enable shortcut */
7944 
7945 /* Bit 1 : Shortcut between SEQEND[1] event and STOP task */
7946 #define PWM_SHORTS_SEQEND1_STOP_Pos (1UL) /*!< Position of SEQEND1_STOP field. */
7947 #define PWM_SHORTS_SEQEND1_STOP_Msk (0x1UL << PWM_SHORTS_SEQEND1_STOP_Pos) /*!< Bit mask of SEQEND1_STOP field. */
7948 #define PWM_SHORTS_SEQEND1_STOP_Disabled (0UL) /*!< Disable shortcut */
7949 #define PWM_SHORTS_SEQEND1_STOP_Enabled (1UL) /*!< Enable shortcut */
7950 
7951 /* Bit 0 : Shortcut between SEQEND[0] event and STOP task */
7952 #define PWM_SHORTS_SEQEND0_STOP_Pos (0UL) /*!< Position of SEQEND0_STOP field. */
7953 #define PWM_SHORTS_SEQEND0_STOP_Msk (0x1UL << PWM_SHORTS_SEQEND0_STOP_Pos) /*!< Bit mask of SEQEND0_STOP field. */
7954 #define PWM_SHORTS_SEQEND0_STOP_Disabled (0UL) /*!< Disable shortcut */
7955 #define PWM_SHORTS_SEQEND0_STOP_Enabled (1UL) /*!< Enable shortcut */
7956 
7957 /* Register: PWM_INTEN */
7958 /* Description: Enable or disable interrupt */
7959 
7960 /* Bit 7 : Enable or disable interrupt for LOOPSDONE event */
7961 #define PWM_INTEN_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */
7962 #define PWM_INTEN_LOOPSDONE_Msk (0x1UL << PWM_INTEN_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */
7963 #define PWM_INTEN_LOOPSDONE_Disabled (0UL) /*!< Disable */
7964 #define PWM_INTEN_LOOPSDONE_Enabled (1UL) /*!< Enable */
7965 
7966 /* Bit 6 : Enable or disable interrupt for PWMPERIODEND event */
7967 #define PWM_INTEN_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */
7968 #define PWM_INTEN_PWMPERIODEND_Msk (0x1UL << PWM_INTEN_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */
7969 #define PWM_INTEN_PWMPERIODEND_Disabled (0UL) /*!< Disable */
7970 #define PWM_INTEN_PWMPERIODEND_Enabled (1UL) /*!< Enable */
7971 
7972 /* Bit 5 : Enable or disable interrupt for SEQEND[1] event */
7973 #define PWM_INTEN_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */
7974 #define PWM_INTEN_SEQEND1_Msk (0x1UL << PWM_INTEN_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */
7975 #define PWM_INTEN_SEQEND1_Disabled (0UL) /*!< Disable */
7976 #define PWM_INTEN_SEQEND1_Enabled (1UL) /*!< Enable */
7977 
7978 /* Bit 4 : Enable or disable interrupt for SEQEND[0] event */
7979 #define PWM_INTEN_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */
7980 #define PWM_INTEN_SEQEND0_Msk (0x1UL << PWM_INTEN_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */
7981 #define PWM_INTEN_SEQEND0_Disabled (0UL) /*!< Disable */
7982 #define PWM_INTEN_SEQEND0_Enabled (1UL) /*!< Enable */
7983 
7984 /* Bit 3 : Enable or disable interrupt for SEQSTARTED[1] event */
7985 #define PWM_INTEN_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */
7986 #define PWM_INTEN_SEQSTARTED1_Msk (0x1UL << PWM_INTEN_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */
7987 #define PWM_INTEN_SEQSTARTED1_Disabled (0UL) /*!< Disable */
7988 #define PWM_INTEN_SEQSTARTED1_Enabled (1UL) /*!< Enable */
7989 
7990 /* Bit 2 : Enable or disable interrupt for SEQSTARTED[0] event */
7991 #define PWM_INTEN_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */
7992 #define PWM_INTEN_SEQSTARTED0_Msk (0x1UL << PWM_INTEN_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */
7993 #define PWM_INTEN_SEQSTARTED0_Disabled (0UL) /*!< Disable */
7994 #define PWM_INTEN_SEQSTARTED0_Enabled (1UL) /*!< Enable */
7995 
7996 /* Bit 1 : Enable or disable interrupt for STOPPED event */
7997 #define PWM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
7998 #define PWM_INTEN_STOPPED_Msk (0x1UL << PWM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
7999 #define PWM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
8000 #define PWM_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
8001 
8002 /* Register: PWM_INTENSET */
8003 /* Description: Enable interrupt */
8004 
8005 /* Bit 7 : Write '1' to Enable interrupt for LOOPSDONE event */
8006 #define PWM_INTENSET_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */
8007 #define PWM_INTENSET_LOOPSDONE_Msk (0x1UL << PWM_INTENSET_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */
8008 #define PWM_INTENSET_LOOPSDONE_Disabled (0UL) /*!< Read: Disabled */
8009 #define PWM_INTENSET_LOOPSDONE_Enabled (1UL) /*!< Read: Enabled */
8010 #define PWM_INTENSET_LOOPSDONE_Set (1UL) /*!< Enable */
8011 
8012 /* Bit 6 : Write '1' to Enable interrupt for PWMPERIODEND event */
8013 #define PWM_INTENSET_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */
8014 #define PWM_INTENSET_PWMPERIODEND_Msk (0x1UL << PWM_INTENSET_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */
8015 #define PWM_INTENSET_PWMPERIODEND_Disabled (0UL) /*!< Read: Disabled */
8016 #define PWM_INTENSET_PWMPERIODEND_Enabled (1UL) /*!< Read: Enabled */
8017 #define PWM_INTENSET_PWMPERIODEND_Set (1UL) /*!< Enable */
8018 
8019 /* Bit 5 : Write '1' to Enable interrupt for SEQEND[1] event */
8020 #define PWM_INTENSET_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */
8021 #define PWM_INTENSET_SEQEND1_Msk (0x1UL << PWM_INTENSET_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */
8022 #define PWM_INTENSET_SEQEND1_Disabled (0UL) /*!< Read: Disabled */
8023 #define PWM_INTENSET_SEQEND1_Enabled (1UL) /*!< Read: Enabled */
8024 #define PWM_INTENSET_SEQEND1_Set (1UL) /*!< Enable */
8025 
8026 /* Bit 4 : Write '1' to Enable interrupt for SEQEND[0] event */
8027 #define PWM_INTENSET_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */
8028 #define PWM_INTENSET_SEQEND0_Msk (0x1UL << PWM_INTENSET_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */
8029 #define PWM_INTENSET_SEQEND0_Disabled (0UL) /*!< Read: Disabled */
8030 #define PWM_INTENSET_SEQEND0_Enabled (1UL) /*!< Read: Enabled */
8031 #define PWM_INTENSET_SEQEND0_Set (1UL) /*!< Enable */
8032 
8033 /* Bit 3 : Write '1' to Enable interrupt for SEQSTARTED[1] event */
8034 #define PWM_INTENSET_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */
8035 #define PWM_INTENSET_SEQSTARTED1_Msk (0x1UL << PWM_INTENSET_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */
8036 #define PWM_INTENSET_SEQSTARTED1_Disabled (0UL) /*!< Read: Disabled */
8037 #define PWM_INTENSET_SEQSTARTED1_Enabled (1UL) /*!< Read: Enabled */
8038 #define PWM_INTENSET_SEQSTARTED1_Set (1UL) /*!< Enable */
8039 
8040 /* Bit 2 : Write '1' to Enable interrupt for SEQSTARTED[0] event */
8041 #define PWM_INTENSET_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */
8042 #define PWM_INTENSET_SEQSTARTED0_Msk (0x1UL << PWM_INTENSET_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */
8043 #define PWM_INTENSET_SEQSTARTED0_Disabled (0UL) /*!< Read: Disabled */
8044 #define PWM_INTENSET_SEQSTARTED0_Enabled (1UL) /*!< Read: Enabled */
8045 #define PWM_INTENSET_SEQSTARTED0_Set (1UL) /*!< Enable */
8046 
8047 /* Bit 1 : Write '1' to Enable interrupt for STOPPED event */
8048 #define PWM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
8049 #define PWM_INTENSET_STOPPED_Msk (0x1UL << PWM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
8050 #define PWM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
8051 #define PWM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
8052 #define PWM_INTENSET_STOPPED_Set (1UL) /*!< Enable */
8053 
8054 /* Register: PWM_INTENCLR */
8055 /* Description: Disable interrupt */
8056 
8057 /* Bit 7 : Write '1' to Disable interrupt for LOOPSDONE event */
8058 #define PWM_INTENCLR_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */
8059 #define PWM_INTENCLR_LOOPSDONE_Msk (0x1UL << PWM_INTENCLR_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */
8060 #define PWM_INTENCLR_LOOPSDONE_Disabled (0UL) /*!< Read: Disabled */
8061 #define PWM_INTENCLR_LOOPSDONE_Enabled (1UL) /*!< Read: Enabled */
8062 #define PWM_INTENCLR_LOOPSDONE_Clear (1UL) /*!< Disable */
8063 
8064 /* Bit 6 : Write '1' to Disable interrupt for PWMPERIODEND event */
8065 #define PWM_INTENCLR_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */
8066 #define PWM_INTENCLR_PWMPERIODEND_Msk (0x1UL << PWM_INTENCLR_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */
8067 #define PWM_INTENCLR_PWMPERIODEND_Disabled (0UL) /*!< Read: Disabled */
8068 #define PWM_INTENCLR_PWMPERIODEND_Enabled (1UL) /*!< Read: Enabled */
8069 #define PWM_INTENCLR_PWMPERIODEND_Clear (1UL) /*!< Disable */
8070 
8071 /* Bit 5 : Write '1' to Disable interrupt for SEQEND[1] event */
8072 #define PWM_INTENCLR_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */
8073 #define PWM_INTENCLR_SEQEND1_Msk (0x1UL << PWM_INTENCLR_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */
8074 #define PWM_INTENCLR_SEQEND1_Disabled (0UL) /*!< Read: Disabled */
8075 #define PWM_INTENCLR_SEQEND1_Enabled (1UL) /*!< Read: Enabled */
8076 #define PWM_INTENCLR_SEQEND1_Clear (1UL) /*!< Disable */
8077 
8078 /* Bit 4 : Write '1' to Disable interrupt for SEQEND[0] event */
8079 #define PWM_INTENCLR_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */
8080 #define PWM_INTENCLR_SEQEND0_Msk (0x1UL << PWM_INTENCLR_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */
8081 #define PWM_INTENCLR_SEQEND0_Disabled (0UL) /*!< Read: Disabled */
8082 #define PWM_INTENCLR_SEQEND0_Enabled (1UL) /*!< Read: Enabled */
8083 #define PWM_INTENCLR_SEQEND0_Clear (1UL) /*!< Disable */
8084 
8085 /* Bit 3 : Write '1' to Disable interrupt for SEQSTARTED[1] event */
8086 #define PWM_INTENCLR_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */
8087 #define PWM_INTENCLR_SEQSTARTED1_Msk (0x1UL << PWM_INTENCLR_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */
8088 #define PWM_INTENCLR_SEQSTARTED1_Disabled (0UL) /*!< Read: Disabled */
8089 #define PWM_INTENCLR_SEQSTARTED1_Enabled (1UL) /*!< Read: Enabled */
8090 #define PWM_INTENCLR_SEQSTARTED1_Clear (1UL) /*!< Disable */
8091 
8092 /* Bit 2 : Write '1' to Disable interrupt for SEQSTARTED[0] event */
8093 #define PWM_INTENCLR_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */
8094 #define PWM_INTENCLR_SEQSTARTED0_Msk (0x1UL << PWM_INTENCLR_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */
8095 #define PWM_INTENCLR_SEQSTARTED0_Disabled (0UL) /*!< Read: Disabled */
8096 #define PWM_INTENCLR_SEQSTARTED0_Enabled (1UL) /*!< Read: Enabled */
8097 #define PWM_INTENCLR_SEQSTARTED0_Clear (1UL) /*!< Disable */
8098 
8099 /* Bit 1 : Write '1' to Disable interrupt for STOPPED event */
8100 #define PWM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
8101 #define PWM_INTENCLR_STOPPED_Msk (0x1UL << PWM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
8102 #define PWM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
8103 #define PWM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
8104 #define PWM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
8105 
8106 /* Register: PWM_ENABLE */
8107 /* Description: PWM module enable register */
8108 
8109 /* Bit 0 : Enable or disable PWM module */
8110 #define PWM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
8111 #define PWM_ENABLE_ENABLE_Msk (0x1UL << PWM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
8112 #define PWM_ENABLE_ENABLE_Disabled (0UL) /*!< Disabled */
8113 #define PWM_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */
8114 
8115 /* Register: PWM_MODE */
8116 /* Description: Selects operating mode of the wave counter */
8117 
8118 /* Bit 0 : Selects up or up and down as wave counter mode */
8119 #define PWM_MODE_UPDOWN_Pos (0UL) /*!< Position of UPDOWN field. */
8120 #define PWM_MODE_UPDOWN_Msk (0x1UL << PWM_MODE_UPDOWN_Pos) /*!< Bit mask of UPDOWN field. */
8121 #define PWM_MODE_UPDOWN_Up (0UL) /*!< Up counter - edge aligned PWM duty-cycle */
8122 #define PWM_MODE_UPDOWN_UpAndDown (1UL) /*!< Up and down counter - center aligned PWM duty cycle */
8123 
8124 /* Register: PWM_COUNTERTOP */
8125 /* Description: Value up to which the pulse generator counter counts */
8126 
8127 /* Bits 14..0 : Value up to which the pulse generator counter counts. This register is ignored when DECODER.MODE=WaveForm and only values from RAM will be used. */
8128 #define PWM_COUNTERTOP_COUNTERTOP_Pos (0UL) /*!< Position of COUNTERTOP field. */
8129 #define PWM_COUNTERTOP_COUNTERTOP_Msk (0x7FFFUL << PWM_COUNTERTOP_COUNTERTOP_Pos) /*!< Bit mask of COUNTERTOP field. */
8130 
8131 /* Register: PWM_PRESCALER */
8132 /* Description: Configuration for PWM_CLK */
8133 
8134 /* Bits 2..0 : Pre-scaler of PWM_CLK */
8135 #define PWM_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */
8136 #define PWM_PRESCALER_PRESCALER_Msk (0x7UL << PWM_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */
8137 #define PWM_PRESCALER_PRESCALER_DIV_1 (0UL) /*!< Divide by   1 (16MHz) */
8138 #define PWM_PRESCALER_PRESCALER_DIV_2 (1UL) /*!< Divide by   2 ( 8MHz) */
8139 #define PWM_PRESCALER_PRESCALER_DIV_4 (2UL) /*!< Divide by   4 ( 4MHz) */
8140 #define PWM_PRESCALER_PRESCALER_DIV_8 (3UL) /*!< Divide by   8 ( 2MHz) */
8141 #define PWM_PRESCALER_PRESCALER_DIV_16 (4UL) /*!< Divide by  16 ( 1MHz) */
8142 #define PWM_PRESCALER_PRESCALER_DIV_32 (5UL) /*!< Divide by  32 ( 500kHz) */
8143 #define PWM_PRESCALER_PRESCALER_DIV_64 (6UL) /*!< Divide by  64 ( 250kHz) */
8144 #define PWM_PRESCALER_PRESCALER_DIV_128 (7UL) /*!< Divide by 128 ( 125kHz) */
8145 
8146 /* Register: PWM_DECODER */
8147 /* Description: Configuration of the decoder */
8148 
8149 /* Bit 8 : Selects source for advancing the active sequence */
8150 #define PWM_DECODER_MODE_Pos (8UL) /*!< Position of MODE field. */
8151 #define PWM_DECODER_MODE_Msk (0x1UL << PWM_DECODER_MODE_Pos) /*!< Bit mask of MODE field. */
8152 #define PWM_DECODER_MODE_RefreshCount (0UL) /*!< SEQ[n].REFRESH is used to determine loading internal compare registers */
8153 #define PWM_DECODER_MODE_NextStep (1UL) /*!< NEXTSTEP task causes a new value to be loaded to internal compare registers */
8154 
8155 /* Bits 2..0 : How a sequence is read from RAM and spread to the compare register */
8156 #define PWM_DECODER_LOAD_Pos (0UL) /*!< Position of LOAD field. */
8157 #define PWM_DECODER_LOAD_Msk (0x7UL << PWM_DECODER_LOAD_Pos) /*!< Bit mask of LOAD field. */
8158 #define PWM_DECODER_LOAD_Common (0UL) /*!< 1st half word (16-bit) used in all PWM channels 0..3 */
8159 #define PWM_DECODER_LOAD_Grouped (1UL) /*!< 1st half word (16-bit) used in channel 0..1; 2nd word in channel 2..3 */
8160 #define PWM_DECODER_LOAD_Individual (2UL) /*!< 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in ch.3 */
8161 #define PWM_DECODER_LOAD_WaveForm (3UL) /*!< 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in COUNTERTOP */
8162 
8163 /* Register: PWM_LOOP */
8164 /* Description: Amount of playback of a loop */
8165 
8166 /* Bits 15..0 : Amount of playback of pattern cycles */
8167 #define PWM_LOOP_CNT_Pos (0UL) /*!< Position of CNT field. */
8168 #define PWM_LOOP_CNT_Msk (0xFFFFUL << PWM_LOOP_CNT_Pos) /*!< Bit mask of CNT field. */
8169 #define PWM_LOOP_CNT_Disabled (0UL) /*!< Looping disabled (stop at the end of the sequence) */
8170 
8171 /* Register: PWM_SEQ_PTR */
8172 /* Description: Description cluster[0]:  Beginning address in Data RAM of this sequence */
8173 
8174 /* Bits 31..0 : Beginning address in Data RAM of this sequence */
8175 #define PWM_SEQ_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
8176 #define PWM_SEQ_PTR_PTR_Msk (0xFFFFFFFFUL << PWM_SEQ_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
8177 
8178 /* Register: PWM_SEQ_CNT */
8179 /* Description: Description cluster[0]:  Amount of values (duty cycles) in this sequence */
8180 
8181 /* Bits 14..0 : Amount of values (duty cycles) in this sequence */
8182 #define PWM_SEQ_CNT_CNT_Pos (0UL) /*!< Position of CNT field. */
8183 #define PWM_SEQ_CNT_CNT_Msk (0x7FFFUL << PWM_SEQ_CNT_CNT_Pos) /*!< Bit mask of CNT field. */
8184 #define PWM_SEQ_CNT_CNT_Disabled (0UL) /*!< Sequence is disabled, and shall not be started as it is empty */
8185 
8186 /* Register: PWM_SEQ_REFRESH */
8187 /* Description: Description cluster[0]:  Amount of additional PWM periods between samples loaded into compare register */
8188 
8189 /* Bits 23..0 : Amount of additional PWM periods between samples loaded into compare register (load every REFRESH.CNT+1 PWM periods) */
8190 #define PWM_SEQ_REFRESH_CNT_Pos (0UL) /*!< Position of CNT field. */
8191 #define PWM_SEQ_REFRESH_CNT_Msk (0xFFFFFFUL << PWM_SEQ_REFRESH_CNT_Pos) /*!< Bit mask of CNT field. */
8192 #define PWM_SEQ_REFRESH_CNT_Continuous (0UL) /*!< Update every PWM period */
8193 
8194 /* Register: PWM_SEQ_ENDDELAY */
8195 /* Description: Description cluster[0]:  Time added after the sequence */
8196 
8197 /* Bits 23..0 : Time added after the sequence in PWM periods */
8198 #define PWM_SEQ_ENDDELAY_CNT_Pos (0UL) /*!< Position of CNT field. */
8199 #define PWM_SEQ_ENDDELAY_CNT_Msk (0xFFFFFFUL << PWM_SEQ_ENDDELAY_CNT_Pos) /*!< Bit mask of CNT field. */
8200 
8201 /* Register: PWM_PSEL_OUT */
8202 /* Description: Description collection[0]:  Output pin select for PWM channel 0 */
8203 
8204 /* Bit 31 : Connection */
8205 #define PWM_PSEL_OUT_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
8206 #define PWM_PSEL_OUT_CONNECT_Msk (0x1UL << PWM_PSEL_OUT_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
8207 #define PWM_PSEL_OUT_CONNECT_Connected (0UL) /*!< Connect */
8208 #define PWM_PSEL_OUT_CONNECT_Disconnected (1UL) /*!< Disconnect */
8209 
8210 /* Bits 4..0 : Pin number */
8211 #define PWM_PSEL_OUT_PIN_Pos (0UL) /*!< Position of PIN field. */
8212 #define PWM_PSEL_OUT_PIN_Msk (0x1FUL << PWM_PSEL_OUT_PIN_Pos) /*!< Bit mask of PIN field. */
8213 
8214 
8215 /* Peripheral: QDEC */
8216 /* Description: Quadrature Decoder */
8217 
8218 /* Register: QDEC_SHORTS */
8219 /* Description: Shortcut register */
8220 
8221 /* Bit 6 : Shortcut between SAMPLERDY event and READCLRACC task */
8222 #define QDEC_SHORTS_SAMPLERDY_READCLRACC_Pos (6UL) /*!< Position of SAMPLERDY_READCLRACC field. */
8223 #define QDEC_SHORTS_SAMPLERDY_READCLRACC_Msk (0x1UL << QDEC_SHORTS_SAMPLERDY_READCLRACC_Pos) /*!< Bit mask of SAMPLERDY_READCLRACC field. */
8224 #define QDEC_SHORTS_SAMPLERDY_READCLRACC_Disabled (0UL) /*!< Disable shortcut */
8225 #define QDEC_SHORTS_SAMPLERDY_READCLRACC_Enabled (1UL) /*!< Enable shortcut */
8226 
8227 /* Bit 5 : Shortcut between DBLRDY event and STOP task */
8228 #define QDEC_SHORTS_DBLRDY_STOP_Pos (5UL) /*!< Position of DBLRDY_STOP field. */
8229 #define QDEC_SHORTS_DBLRDY_STOP_Msk (0x1UL << QDEC_SHORTS_DBLRDY_STOP_Pos) /*!< Bit mask of DBLRDY_STOP field. */
8230 #define QDEC_SHORTS_DBLRDY_STOP_Disabled (0UL) /*!< Disable shortcut */
8231 #define QDEC_SHORTS_DBLRDY_STOP_Enabled (1UL) /*!< Enable shortcut */
8232 
8233 /* Bit 4 : Shortcut between DBLRDY event and RDCLRDBL task */
8234 #define QDEC_SHORTS_DBLRDY_RDCLRDBL_Pos (4UL) /*!< Position of DBLRDY_RDCLRDBL field. */
8235 #define QDEC_SHORTS_DBLRDY_RDCLRDBL_Msk (0x1UL << QDEC_SHORTS_DBLRDY_RDCLRDBL_Pos) /*!< Bit mask of DBLRDY_RDCLRDBL field. */
8236 #define QDEC_SHORTS_DBLRDY_RDCLRDBL_Disabled (0UL) /*!< Disable shortcut */
8237 #define QDEC_SHORTS_DBLRDY_RDCLRDBL_Enabled (1UL) /*!< Enable shortcut */
8238 
8239 /* Bit 3 : Shortcut between REPORTRDY event and STOP task */
8240 #define QDEC_SHORTS_REPORTRDY_STOP_Pos (3UL) /*!< Position of REPORTRDY_STOP field. */
8241 #define QDEC_SHORTS_REPORTRDY_STOP_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_STOP_Pos) /*!< Bit mask of REPORTRDY_STOP field. */
8242 #define QDEC_SHORTS_REPORTRDY_STOP_Disabled (0UL) /*!< Disable shortcut */
8243 #define QDEC_SHORTS_REPORTRDY_STOP_Enabled (1UL) /*!< Enable shortcut */
8244 
8245 /* Bit 2 : Shortcut between REPORTRDY event and RDCLRACC task */
8246 #define QDEC_SHORTS_REPORTRDY_RDCLRACC_Pos (2UL) /*!< Position of REPORTRDY_RDCLRACC field. */
8247 #define QDEC_SHORTS_REPORTRDY_RDCLRACC_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_RDCLRACC_Pos) /*!< Bit mask of REPORTRDY_RDCLRACC field. */
8248 #define QDEC_SHORTS_REPORTRDY_RDCLRACC_Disabled (0UL) /*!< Disable shortcut */
8249 #define QDEC_SHORTS_REPORTRDY_RDCLRACC_Enabled (1UL) /*!< Enable shortcut */
8250 
8251 /* Bit 1 : Shortcut between SAMPLERDY event and STOP task */
8252 #define QDEC_SHORTS_SAMPLERDY_STOP_Pos (1UL) /*!< Position of SAMPLERDY_STOP field. */
8253 #define QDEC_SHORTS_SAMPLERDY_STOP_Msk (0x1UL << QDEC_SHORTS_SAMPLERDY_STOP_Pos) /*!< Bit mask of SAMPLERDY_STOP field. */
8254 #define QDEC_SHORTS_SAMPLERDY_STOP_Disabled (0UL) /*!< Disable shortcut */
8255 #define QDEC_SHORTS_SAMPLERDY_STOP_Enabled (1UL) /*!< Enable shortcut */
8256 
8257 /* Bit 0 : Shortcut between REPORTRDY event and READCLRACC task */
8258 #define QDEC_SHORTS_REPORTRDY_READCLRACC_Pos (0UL) /*!< Position of REPORTRDY_READCLRACC field. */
8259 #define QDEC_SHORTS_REPORTRDY_READCLRACC_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_READCLRACC_Pos) /*!< Bit mask of REPORTRDY_READCLRACC field. */
8260 #define QDEC_SHORTS_REPORTRDY_READCLRACC_Disabled (0UL) /*!< Disable shortcut */
8261 #define QDEC_SHORTS_REPORTRDY_READCLRACC_Enabled (1UL) /*!< Enable shortcut */
8262 
8263 /* Register: QDEC_INTENSET */
8264 /* Description: Enable interrupt */
8265 
8266 /* Bit 4 : Write '1' to Enable interrupt for STOPPED event */
8267 #define QDEC_INTENSET_STOPPED_Pos (4UL) /*!< Position of STOPPED field. */
8268 #define QDEC_INTENSET_STOPPED_Msk (0x1UL << QDEC_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
8269 #define QDEC_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
8270 #define QDEC_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
8271 #define QDEC_INTENSET_STOPPED_Set (1UL) /*!< Enable */
8272 
8273 /* Bit 3 : Write '1' to Enable interrupt for DBLRDY event */
8274 #define QDEC_INTENSET_DBLRDY_Pos (3UL) /*!< Position of DBLRDY field. */
8275 #define QDEC_INTENSET_DBLRDY_Msk (0x1UL << QDEC_INTENSET_DBLRDY_Pos) /*!< Bit mask of DBLRDY field. */
8276 #define QDEC_INTENSET_DBLRDY_Disabled (0UL) /*!< Read: Disabled */
8277 #define QDEC_INTENSET_DBLRDY_Enabled (1UL) /*!< Read: Enabled */
8278 #define QDEC_INTENSET_DBLRDY_Set (1UL) /*!< Enable */
8279 
8280 /* Bit 2 : Write '1' to Enable interrupt for ACCOF event */
8281 #define QDEC_INTENSET_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */
8282 #define QDEC_INTENSET_ACCOF_Msk (0x1UL << QDEC_INTENSET_ACCOF_Pos) /*!< Bit mask of ACCOF field. */
8283 #define QDEC_INTENSET_ACCOF_Disabled (0UL) /*!< Read: Disabled */
8284 #define QDEC_INTENSET_ACCOF_Enabled (1UL) /*!< Read: Enabled */
8285 #define QDEC_INTENSET_ACCOF_Set (1UL) /*!< Enable */
8286 
8287 /* Bit 1 : Write '1' to Enable interrupt for REPORTRDY event */
8288 #define QDEC_INTENSET_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */
8289 #define QDEC_INTENSET_REPORTRDY_Msk (0x1UL << QDEC_INTENSET_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */
8290 #define QDEC_INTENSET_REPORTRDY_Disabled (0UL) /*!< Read: Disabled */
8291 #define QDEC_INTENSET_REPORTRDY_Enabled (1UL) /*!< Read: Enabled */
8292 #define QDEC_INTENSET_REPORTRDY_Set (1UL) /*!< Enable */
8293 
8294 /* Bit 0 : Write '1' to Enable interrupt for SAMPLERDY event */
8295 #define QDEC_INTENSET_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */
8296 #define QDEC_INTENSET_SAMPLERDY_Msk (0x1UL << QDEC_INTENSET_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */
8297 #define QDEC_INTENSET_SAMPLERDY_Disabled (0UL) /*!< Read: Disabled */
8298 #define QDEC_INTENSET_SAMPLERDY_Enabled (1UL) /*!< Read: Enabled */
8299 #define QDEC_INTENSET_SAMPLERDY_Set (1UL) /*!< Enable */
8300 
8301 /* Register: QDEC_INTENCLR */
8302 /* Description: Disable interrupt */
8303 
8304 /* Bit 4 : Write '1' to Disable interrupt for STOPPED event */
8305 #define QDEC_INTENCLR_STOPPED_Pos (4UL) /*!< Position of STOPPED field. */
8306 #define QDEC_INTENCLR_STOPPED_Msk (0x1UL << QDEC_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
8307 #define QDEC_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
8308 #define QDEC_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
8309 #define QDEC_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
8310 
8311 /* Bit 3 : Write '1' to Disable interrupt for DBLRDY event */
8312 #define QDEC_INTENCLR_DBLRDY_Pos (3UL) /*!< Position of DBLRDY field. */
8313 #define QDEC_INTENCLR_DBLRDY_Msk (0x1UL << QDEC_INTENCLR_DBLRDY_Pos) /*!< Bit mask of DBLRDY field. */
8314 #define QDEC_INTENCLR_DBLRDY_Disabled (0UL) /*!< Read: Disabled */
8315 #define QDEC_INTENCLR_DBLRDY_Enabled (1UL) /*!< Read: Enabled */
8316 #define QDEC_INTENCLR_DBLRDY_Clear (1UL) /*!< Disable */
8317 
8318 /* Bit 2 : Write '1' to Disable interrupt for ACCOF event */
8319 #define QDEC_INTENCLR_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */
8320 #define QDEC_INTENCLR_ACCOF_Msk (0x1UL << QDEC_INTENCLR_ACCOF_Pos) /*!< Bit mask of ACCOF field. */
8321 #define QDEC_INTENCLR_ACCOF_Disabled (0UL) /*!< Read: Disabled */
8322 #define QDEC_INTENCLR_ACCOF_Enabled (1UL) /*!< Read: Enabled */
8323 #define QDEC_INTENCLR_ACCOF_Clear (1UL) /*!< Disable */
8324 
8325 /* Bit 1 : Write '1' to Disable interrupt for REPORTRDY event */
8326 #define QDEC_INTENCLR_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */
8327 #define QDEC_INTENCLR_REPORTRDY_Msk (0x1UL << QDEC_INTENCLR_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */
8328 #define QDEC_INTENCLR_REPORTRDY_Disabled (0UL) /*!< Read: Disabled */
8329 #define QDEC_INTENCLR_REPORTRDY_Enabled (1UL) /*!< Read: Enabled */
8330 #define QDEC_INTENCLR_REPORTRDY_Clear (1UL) /*!< Disable */
8331 
8332 /* Bit 0 : Write '1' to Disable interrupt for SAMPLERDY event */
8333 #define QDEC_INTENCLR_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */
8334 #define QDEC_INTENCLR_SAMPLERDY_Msk (0x1UL << QDEC_INTENCLR_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */
8335 #define QDEC_INTENCLR_SAMPLERDY_Disabled (0UL) /*!< Read: Disabled */
8336 #define QDEC_INTENCLR_SAMPLERDY_Enabled (1UL) /*!< Read: Enabled */
8337 #define QDEC_INTENCLR_SAMPLERDY_Clear (1UL) /*!< Disable */
8338 
8339 /* Register: QDEC_ENABLE */
8340 /* Description: Enable the quadrature decoder */
8341 
8342 /* Bit 0 : Enable or disable the quadrature decoder */
8343 #define QDEC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
8344 #define QDEC_ENABLE_ENABLE_Msk (0x1UL << QDEC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
8345 #define QDEC_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
8346 #define QDEC_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */
8347 
8348 /* Register: QDEC_LEDPOL */
8349 /* Description: LED output pin polarity */
8350 
8351 /* Bit 0 : LED output pin polarity */
8352 #define QDEC_LEDPOL_LEDPOL_Pos (0UL) /*!< Position of LEDPOL field. */
8353 #define QDEC_LEDPOL_LEDPOL_Msk (0x1UL << QDEC_LEDPOL_LEDPOL_Pos) /*!< Bit mask of LEDPOL field. */
8354 #define QDEC_LEDPOL_LEDPOL_ActiveLow (0UL) /*!< Led active on output pin low */
8355 #define QDEC_LEDPOL_LEDPOL_ActiveHigh (1UL) /*!< Led active on output pin high */
8356 
8357 /* Register: QDEC_SAMPLEPER */
8358 /* Description: Sample period */
8359 
8360 /* Bits 3..0 : Sample period. The SAMPLE register will be updated for every new sample */
8361 #define QDEC_SAMPLEPER_SAMPLEPER_Pos (0UL) /*!< Position of SAMPLEPER field. */
8362 #define QDEC_SAMPLEPER_SAMPLEPER_Msk (0xFUL << QDEC_SAMPLEPER_SAMPLEPER_Pos) /*!< Bit mask of SAMPLEPER field. */
8363 #define QDEC_SAMPLEPER_SAMPLEPER_128us (0UL) /*!< 128 us */
8364 #define QDEC_SAMPLEPER_SAMPLEPER_256us (1UL) /*!< 256 us */
8365 #define QDEC_SAMPLEPER_SAMPLEPER_512us (2UL) /*!< 512 us */
8366 #define QDEC_SAMPLEPER_SAMPLEPER_1024us (3UL) /*!< 1024 us */
8367 #define QDEC_SAMPLEPER_SAMPLEPER_2048us (4UL) /*!< 2048 us */
8368 #define QDEC_SAMPLEPER_SAMPLEPER_4096us (5UL) /*!< 4096 us */
8369 #define QDEC_SAMPLEPER_SAMPLEPER_8192us (6UL) /*!< 8192 us */
8370 #define QDEC_SAMPLEPER_SAMPLEPER_16384us (7UL) /*!< 16384 us */
8371 #define QDEC_SAMPLEPER_SAMPLEPER_32ms (8UL) /*!< 32768 us */
8372 #define QDEC_SAMPLEPER_SAMPLEPER_65ms (9UL) /*!< 65536 us */
8373 #define QDEC_SAMPLEPER_SAMPLEPER_131ms (10UL) /*!< 131072 us */
8374 
8375 /* Register: QDEC_SAMPLE */
8376 /* Description: Motion sample value */
8377 
8378 /* Bits 31..0 : Last motion sample */
8379 #define QDEC_SAMPLE_SAMPLE_Pos (0UL) /*!< Position of SAMPLE field. */
8380 #define QDEC_SAMPLE_SAMPLE_Msk (0xFFFFFFFFUL << QDEC_SAMPLE_SAMPLE_Pos) /*!< Bit mask of SAMPLE field. */
8381 
8382 /* Register: QDEC_REPORTPER */
8383 /* Description: Number of samples to be taken before REPORTRDY and DBLRDY events can be generated */
8384 
8385 /* Bits 3..0 : Specifies the number of samples to be accumulated in the ACC register before the REPORTRDY and DBLRDY events can be generated */
8386 #define QDEC_REPORTPER_REPORTPER_Pos (0UL) /*!< Position of REPORTPER field. */
8387 #define QDEC_REPORTPER_REPORTPER_Msk (0xFUL << QDEC_REPORTPER_REPORTPER_Pos) /*!< Bit mask of REPORTPER field. */
8388 #define QDEC_REPORTPER_REPORTPER_10Smpl (0UL) /*!< 10 samples / report */
8389 #define QDEC_REPORTPER_REPORTPER_40Smpl (1UL) /*!< 40 samples / report */
8390 #define QDEC_REPORTPER_REPORTPER_80Smpl (2UL) /*!< 80 samples / report */
8391 #define QDEC_REPORTPER_REPORTPER_120Smpl (3UL) /*!< 120 samples / report */
8392 #define QDEC_REPORTPER_REPORTPER_160Smpl (4UL) /*!< 160 samples / report */
8393 #define QDEC_REPORTPER_REPORTPER_200Smpl (5UL) /*!< 200 samples / report */
8394 #define QDEC_REPORTPER_REPORTPER_240Smpl (6UL) /*!< 240 samples / report */
8395 #define QDEC_REPORTPER_REPORTPER_280Smpl (7UL) /*!< 280 samples / report */
8396 #define QDEC_REPORTPER_REPORTPER_1Smpl (8UL) /*!< 1 sample / report */
8397 
8398 /* Register: QDEC_ACC */
8399 /* Description: Register accumulating the valid transitions */
8400 
8401 /* Bits 31..0 : Register accumulating all valid samples (not double transition) read from the SAMPLE register */
8402 #define QDEC_ACC_ACC_Pos (0UL) /*!< Position of ACC field. */
8403 #define QDEC_ACC_ACC_Msk (0xFFFFFFFFUL << QDEC_ACC_ACC_Pos) /*!< Bit mask of ACC field. */
8404 
8405 /* Register: QDEC_ACCREAD */
8406 /* Description: Snapshot of the ACC register, updated by the READCLRACC or RDCLRACC task */
8407 
8408 /* Bits 31..0 : Snapshot of the ACC register. */
8409 #define QDEC_ACCREAD_ACCREAD_Pos (0UL) /*!< Position of ACCREAD field. */
8410 #define QDEC_ACCREAD_ACCREAD_Msk (0xFFFFFFFFUL << QDEC_ACCREAD_ACCREAD_Pos) /*!< Bit mask of ACCREAD field. */
8411 
8412 /* Register: QDEC_PSEL_LED */
8413 /* Description: Pin select for LED signal */
8414 
8415 /* Bit 31 : Connection */
8416 #define QDEC_PSEL_LED_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
8417 #define QDEC_PSEL_LED_CONNECT_Msk (0x1UL << QDEC_PSEL_LED_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
8418 #define QDEC_PSEL_LED_CONNECT_Connected (0UL) /*!< Connect */
8419 #define QDEC_PSEL_LED_CONNECT_Disconnected (1UL) /*!< Disconnect */
8420 
8421 /* Bits 4..0 : Pin number */
8422 #define QDEC_PSEL_LED_PIN_Pos (0UL) /*!< Position of PIN field. */
8423 #define QDEC_PSEL_LED_PIN_Msk (0x1FUL << QDEC_PSEL_LED_PIN_Pos) /*!< Bit mask of PIN field. */
8424 
8425 /* Register: QDEC_PSEL_A */
8426 /* Description: Pin select for A signal */
8427 
8428 /* Bit 31 : Connection */
8429 #define QDEC_PSEL_A_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
8430 #define QDEC_PSEL_A_CONNECT_Msk (0x1UL << QDEC_PSEL_A_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
8431 #define QDEC_PSEL_A_CONNECT_Connected (0UL) /*!< Connect */
8432 #define QDEC_PSEL_A_CONNECT_Disconnected (1UL) /*!< Disconnect */
8433 
8434 /* Bits 4..0 : Pin number */
8435 #define QDEC_PSEL_A_PIN_Pos (0UL) /*!< Position of PIN field. */
8436 #define QDEC_PSEL_A_PIN_Msk (0x1FUL << QDEC_PSEL_A_PIN_Pos) /*!< Bit mask of PIN field. */
8437 
8438 /* Register: QDEC_PSEL_B */
8439 /* Description: Pin select for B signal */
8440 
8441 /* Bit 31 : Connection */
8442 #define QDEC_PSEL_B_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
8443 #define QDEC_PSEL_B_CONNECT_Msk (0x1UL << QDEC_PSEL_B_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
8444 #define QDEC_PSEL_B_CONNECT_Connected (0UL) /*!< Connect */
8445 #define QDEC_PSEL_B_CONNECT_Disconnected (1UL) /*!< Disconnect */
8446 
8447 /* Bits 4..0 : Pin number */
8448 #define QDEC_PSEL_B_PIN_Pos (0UL) /*!< Position of PIN field. */
8449 #define QDEC_PSEL_B_PIN_Msk (0x1FUL << QDEC_PSEL_B_PIN_Pos) /*!< Bit mask of PIN field. */
8450 
8451 /* Register: QDEC_DBFEN */
8452 /* Description: Enable input debounce filters */
8453 
8454 /* Bit 0 : Enable input debounce filters */
8455 #define QDEC_DBFEN_DBFEN_Pos (0UL) /*!< Position of DBFEN field. */
8456 #define QDEC_DBFEN_DBFEN_Msk (0x1UL << QDEC_DBFEN_DBFEN_Pos) /*!< Bit mask of DBFEN field. */
8457 #define QDEC_DBFEN_DBFEN_Disabled (0UL) /*!< Debounce input filters disabled */
8458 #define QDEC_DBFEN_DBFEN_Enabled (1UL) /*!< Debounce input filters enabled */
8459 
8460 /* Register: QDEC_LEDPRE */
8461 /* Description: Time period the LED is switched ON prior to sampling */
8462 
8463 /* Bits 8..0 : Period in us the LED is switched on prior to sampling */
8464 #define QDEC_LEDPRE_LEDPRE_Pos (0UL) /*!< Position of LEDPRE field. */
8465 #define QDEC_LEDPRE_LEDPRE_Msk (0x1FFUL << QDEC_LEDPRE_LEDPRE_Pos) /*!< Bit mask of LEDPRE field. */
8466 
8467 /* Register: QDEC_ACCDBL */
8468 /* Description: Register accumulating the number of detected double transitions */
8469 
8470 /* Bits 3..0 : Register accumulating the number of detected double or illegal transitions. ( SAMPLE = 2 ). */
8471 #define QDEC_ACCDBL_ACCDBL_Pos (0UL) /*!< Position of ACCDBL field. */
8472 #define QDEC_ACCDBL_ACCDBL_Msk (0xFUL << QDEC_ACCDBL_ACCDBL_Pos) /*!< Bit mask of ACCDBL field. */
8473 
8474 /* Register: QDEC_ACCDBLREAD */
8475 /* Description: Snapshot of the ACCDBL, updated by the READCLRACC or RDCLRDBL task */
8476 
8477 /* Bits 3..0 : Snapshot of the ACCDBL register. This field is updated when the READCLRACC or RDCLRDBL task is triggered. */
8478 #define QDEC_ACCDBLREAD_ACCDBLREAD_Pos (0UL) /*!< Position of ACCDBLREAD field. */
8479 #define QDEC_ACCDBLREAD_ACCDBLREAD_Msk (0xFUL << QDEC_ACCDBLREAD_ACCDBLREAD_Pos) /*!< Bit mask of ACCDBLREAD field. */
8480 
8481 
8482 /* Peripheral: RADIO */
8483 /* Description: 2.4 GHz Radio */
8484 
8485 /* Register: RADIO_SHORTS */
8486 /* Description: Shortcut register */
8487 
8488 /* Bit 8 : Shortcut between DISABLED event and RSSISTOP task */
8489 #define RADIO_SHORTS_DISABLED_RSSISTOP_Pos (8UL) /*!< Position of DISABLED_RSSISTOP field. */
8490 #define RADIO_SHORTS_DISABLED_RSSISTOP_Msk (0x1UL << RADIO_SHORTS_DISABLED_RSSISTOP_Pos) /*!< Bit mask of DISABLED_RSSISTOP field. */
8491 #define RADIO_SHORTS_DISABLED_RSSISTOP_Disabled (0UL) /*!< Disable shortcut */
8492 #define RADIO_SHORTS_DISABLED_RSSISTOP_Enabled (1UL) /*!< Enable shortcut */
8493 
8494 /* Bit 6 : Shortcut between ADDRESS event and BCSTART task */
8495 #define RADIO_SHORTS_ADDRESS_BCSTART_Pos (6UL) /*!< Position of ADDRESS_BCSTART field. */
8496 #define RADIO_SHORTS_ADDRESS_BCSTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_BCSTART_Pos) /*!< Bit mask of ADDRESS_BCSTART field. */
8497 #define RADIO_SHORTS_ADDRESS_BCSTART_Disabled (0UL) /*!< Disable shortcut */
8498 #define RADIO_SHORTS_ADDRESS_BCSTART_Enabled (1UL) /*!< Enable shortcut */
8499 
8500 /* Bit 5 : Shortcut between END event and START task */
8501 #define RADIO_SHORTS_END_START_Pos (5UL) /*!< Position of END_START field. */
8502 #define RADIO_SHORTS_END_START_Msk (0x1UL << RADIO_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */
8503 #define RADIO_SHORTS_END_START_Disabled (0UL) /*!< Disable shortcut */
8504 #define RADIO_SHORTS_END_START_Enabled (1UL) /*!< Enable shortcut */
8505 
8506 /* Bit 4 : Shortcut between ADDRESS event and RSSISTART task */
8507 #define RADIO_SHORTS_ADDRESS_RSSISTART_Pos (4UL) /*!< Position of ADDRESS_RSSISTART field. */
8508 #define RADIO_SHORTS_ADDRESS_RSSISTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_RSSISTART_Pos) /*!< Bit mask of ADDRESS_RSSISTART field. */
8509 #define RADIO_SHORTS_ADDRESS_RSSISTART_Disabled (0UL) /*!< Disable shortcut */
8510 #define RADIO_SHORTS_ADDRESS_RSSISTART_Enabled (1UL) /*!< Enable shortcut */
8511 
8512 /* Bit 3 : Shortcut between DISABLED event and RXEN task */
8513 #define RADIO_SHORTS_DISABLED_RXEN_Pos (3UL) /*!< Position of DISABLED_RXEN field. */
8514 #define RADIO_SHORTS_DISABLED_RXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_RXEN_Pos) /*!< Bit mask of DISABLED_RXEN field. */
8515 #define RADIO_SHORTS_DISABLED_RXEN_Disabled (0UL) /*!< Disable shortcut */
8516 #define RADIO_SHORTS_DISABLED_RXEN_Enabled (1UL) /*!< Enable shortcut */
8517 
8518 /* Bit 2 : Shortcut between DISABLED event and TXEN task */
8519 #define RADIO_SHORTS_DISABLED_TXEN_Pos (2UL) /*!< Position of DISABLED_TXEN field. */
8520 #define RADIO_SHORTS_DISABLED_TXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_TXEN_Pos) /*!< Bit mask of DISABLED_TXEN field. */
8521 #define RADIO_SHORTS_DISABLED_TXEN_Disabled (0UL) /*!< Disable shortcut */
8522 #define RADIO_SHORTS_DISABLED_TXEN_Enabled (1UL) /*!< Enable shortcut */
8523 
8524 /* Bit 1 : Shortcut between END event and DISABLE task */
8525 #define RADIO_SHORTS_END_DISABLE_Pos (1UL) /*!< Position of END_DISABLE field. */
8526 #define RADIO_SHORTS_END_DISABLE_Msk (0x1UL << RADIO_SHORTS_END_DISABLE_Pos) /*!< Bit mask of END_DISABLE field. */
8527 #define RADIO_SHORTS_END_DISABLE_Disabled (0UL) /*!< Disable shortcut */
8528 #define RADIO_SHORTS_END_DISABLE_Enabled (1UL) /*!< Enable shortcut */
8529 
8530 /* Bit 0 : Shortcut between READY event and START task */
8531 #define RADIO_SHORTS_READY_START_Pos (0UL) /*!< Position of READY_START field. */
8532 #define RADIO_SHORTS_READY_START_Msk (0x1UL << RADIO_SHORTS_READY_START_Pos) /*!< Bit mask of READY_START field. */
8533 #define RADIO_SHORTS_READY_START_Disabled (0UL) /*!< Disable shortcut */
8534 #define RADIO_SHORTS_READY_START_Enabled (1UL) /*!< Enable shortcut */
8535 
8536 /* Register: RADIO_INTENSET */
8537 /* Description: Enable interrupt */
8538 
8539 /* Bit 13 : Write '1' to Enable interrupt for CRCERROR event */
8540 #define RADIO_INTENSET_CRCERROR_Pos (13UL) /*!< Position of CRCERROR field. */
8541 #define RADIO_INTENSET_CRCERROR_Msk (0x1UL << RADIO_INTENSET_CRCERROR_Pos) /*!< Bit mask of CRCERROR field. */
8542 #define RADIO_INTENSET_CRCERROR_Disabled (0UL) /*!< Read: Disabled */
8543 #define RADIO_INTENSET_CRCERROR_Enabled (1UL) /*!< Read: Enabled */
8544 #define RADIO_INTENSET_CRCERROR_Set (1UL) /*!< Enable */
8545 
8546 /* Bit 12 : Write '1' to Enable interrupt for CRCOK event */
8547 #define RADIO_INTENSET_CRCOK_Pos (12UL) /*!< Position of CRCOK field. */
8548 #define RADIO_INTENSET_CRCOK_Msk (0x1UL << RADIO_INTENSET_CRCOK_Pos) /*!< Bit mask of CRCOK field. */
8549 #define RADIO_INTENSET_CRCOK_Disabled (0UL) /*!< Read: Disabled */
8550 #define RADIO_INTENSET_CRCOK_Enabled (1UL) /*!< Read: Enabled */
8551 #define RADIO_INTENSET_CRCOK_Set (1UL) /*!< Enable */
8552 
8553 /* Bit 10 : Write '1' to Enable interrupt for BCMATCH event */
8554 #define RADIO_INTENSET_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */
8555 #define RADIO_INTENSET_BCMATCH_Msk (0x1UL << RADIO_INTENSET_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */
8556 #define RADIO_INTENSET_BCMATCH_Disabled (0UL) /*!< Read: Disabled */
8557 #define RADIO_INTENSET_BCMATCH_Enabled (1UL) /*!< Read: Enabled */
8558 #define RADIO_INTENSET_BCMATCH_Set (1UL) /*!< Enable */
8559 
8560 /* Bit 7 : Write '1' to Enable interrupt for RSSIEND event */
8561 #define RADIO_INTENSET_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */
8562 #define RADIO_INTENSET_RSSIEND_Msk (0x1UL << RADIO_INTENSET_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */
8563 #define RADIO_INTENSET_RSSIEND_Disabled (0UL) /*!< Read: Disabled */
8564 #define RADIO_INTENSET_RSSIEND_Enabled (1UL) /*!< Read: Enabled */
8565 #define RADIO_INTENSET_RSSIEND_Set (1UL) /*!< Enable */
8566 
8567 /* Bit 6 : Write '1' to Enable interrupt for DEVMISS event */
8568 #define RADIO_INTENSET_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */
8569 #define RADIO_INTENSET_DEVMISS_Msk (0x1UL << RADIO_INTENSET_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */
8570 #define RADIO_INTENSET_DEVMISS_Disabled (0UL) /*!< Read: Disabled */
8571 #define RADIO_INTENSET_DEVMISS_Enabled (1UL) /*!< Read: Enabled */
8572 #define RADIO_INTENSET_DEVMISS_Set (1UL) /*!< Enable */
8573 
8574 /* Bit 5 : Write '1' to Enable interrupt for DEVMATCH event */
8575 #define RADIO_INTENSET_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */
8576 #define RADIO_INTENSET_DEVMATCH_Msk (0x1UL << RADIO_INTENSET_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */
8577 #define RADIO_INTENSET_DEVMATCH_Disabled (0UL) /*!< Read: Disabled */
8578 #define RADIO_INTENSET_DEVMATCH_Enabled (1UL) /*!< Read: Enabled */
8579 #define RADIO_INTENSET_DEVMATCH_Set (1UL) /*!< Enable */
8580 
8581 /* Bit 4 : Write '1' to Enable interrupt for DISABLED event */
8582 #define RADIO_INTENSET_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */
8583 #define RADIO_INTENSET_DISABLED_Msk (0x1UL << RADIO_INTENSET_DISABLED_Pos) /*!< Bit mask of DISABLED field. */
8584 #define RADIO_INTENSET_DISABLED_Disabled (0UL) /*!< Read: Disabled */
8585 #define RADIO_INTENSET_DISABLED_Enabled (1UL) /*!< Read: Enabled */
8586 #define RADIO_INTENSET_DISABLED_Set (1UL) /*!< Enable */
8587 
8588 /* Bit 3 : Write '1' to Enable interrupt for END event */
8589 #define RADIO_INTENSET_END_Pos (3UL) /*!< Position of END field. */
8590 #define RADIO_INTENSET_END_Msk (0x1UL << RADIO_INTENSET_END_Pos) /*!< Bit mask of END field. */
8591 #define RADIO_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
8592 #define RADIO_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
8593 #define RADIO_INTENSET_END_Set (1UL) /*!< Enable */
8594 
8595 /* Bit 2 : Write '1' to Enable interrupt for PAYLOAD event */
8596 #define RADIO_INTENSET_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */
8597 #define RADIO_INTENSET_PAYLOAD_Msk (0x1UL << RADIO_INTENSET_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */
8598 #define RADIO_INTENSET_PAYLOAD_Disabled (0UL) /*!< Read: Disabled */
8599 #define RADIO_INTENSET_PAYLOAD_Enabled (1UL) /*!< Read: Enabled */
8600 #define RADIO_INTENSET_PAYLOAD_Set (1UL) /*!< Enable */
8601 
8602 /* Bit 1 : Write '1' to Enable interrupt for ADDRESS event */
8603 #define RADIO_INTENSET_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */
8604 #define RADIO_INTENSET_ADDRESS_Msk (0x1UL << RADIO_INTENSET_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
8605 #define RADIO_INTENSET_ADDRESS_Disabled (0UL) /*!< Read: Disabled */
8606 #define RADIO_INTENSET_ADDRESS_Enabled (1UL) /*!< Read: Enabled */
8607 #define RADIO_INTENSET_ADDRESS_Set (1UL) /*!< Enable */
8608 
8609 /* Bit 0 : Write '1' to Enable interrupt for READY event */
8610 #define RADIO_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */
8611 #define RADIO_INTENSET_READY_Msk (0x1UL << RADIO_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
8612 #define RADIO_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */
8613 #define RADIO_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */
8614 #define RADIO_INTENSET_READY_Set (1UL) /*!< Enable */
8615 
8616 /* Register: RADIO_INTENCLR */
8617 /* Description: Disable interrupt */
8618 
8619 /* Bit 13 : Write '1' to Disable interrupt for CRCERROR event */
8620 #define RADIO_INTENCLR_CRCERROR_Pos (13UL) /*!< Position of CRCERROR field. */
8621 #define RADIO_INTENCLR_CRCERROR_Msk (0x1UL << RADIO_INTENCLR_CRCERROR_Pos) /*!< Bit mask of CRCERROR field. */
8622 #define RADIO_INTENCLR_CRCERROR_Disabled (0UL) /*!< Read: Disabled */
8623 #define RADIO_INTENCLR_CRCERROR_Enabled (1UL) /*!< Read: Enabled */
8624 #define RADIO_INTENCLR_CRCERROR_Clear (1UL) /*!< Disable */
8625 
8626 /* Bit 12 : Write '1' to Disable interrupt for CRCOK event */
8627 #define RADIO_INTENCLR_CRCOK_Pos (12UL) /*!< Position of CRCOK field. */
8628 #define RADIO_INTENCLR_CRCOK_Msk (0x1UL << RADIO_INTENCLR_CRCOK_Pos) /*!< Bit mask of CRCOK field. */
8629 #define RADIO_INTENCLR_CRCOK_Disabled (0UL) /*!< Read: Disabled */
8630 #define RADIO_INTENCLR_CRCOK_Enabled (1UL) /*!< Read: Enabled */
8631 #define RADIO_INTENCLR_CRCOK_Clear (1UL) /*!< Disable */
8632 
8633 /* Bit 10 : Write '1' to Disable interrupt for BCMATCH event */
8634 #define RADIO_INTENCLR_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */
8635 #define RADIO_INTENCLR_BCMATCH_Msk (0x1UL << RADIO_INTENCLR_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */
8636 #define RADIO_INTENCLR_BCMATCH_Disabled (0UL) /*!< Read: Disabled */
8637 #define RADIO_INTENCLR_BCMATCH_Enabled (1UL) /*!< Read: Enabled */
8638 #define RADIO_INTENCLR_BCMATCH_Clear (1UL) /*!< Disable */
8639 
8640 /* Bit 7 : Write '1' to Disable interrupt for RSSIEND event */
8641 #define RADIO_INTENCLR_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */
8642 #define RADIO_INTENCLR_RSSIEND_Msk (0x1UL << RADIO_INTENCLR_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */
8643 #define RADIO_INTENCLR_RSSIEND_Disabled (0UL) /*!< Read: Disabled */
8644 #define RADIO_INTENCLR_RSSIEND_Enabled (1UL) /*!< Read: Enabled */
8645 #define RADIO_INTENCLR_RSSIEND_Clear (1UL) /*!< Disable */
8646 
8647 /* Bit 6 : Write '1' to Disable interrupt for DEVMISS event */
8648 #define RADIO_INTENCLR_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */
8649 #define RADIO_INTENCLR_DEVMISS_Msk (0x1UL << RADIO_INTENCLR_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */
8650 #define RADIO_INTENCLR_DEVMISS_Disabled (0UL) /*!< Read: Disabled */
8651 #define RADIO_INTENCLR_DEVMISS_Enabled (1UL) /*!< Read: Enabled */
8652 #define RADIO_INTENCLR_DEVMISS_Clear (1UL) /*!< Disable */
8653 
8654 /* Bit 5 : Write '1' to Disable interrupt for DEVMATCH event */
8655 #define RADIO_INTENCLR_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */
8656 #define RADIO_INTENCLR_DEVMATCH_Msk (0x1UL << RADIO_INTENCLR_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */
8657 #define RADIO_INTENCLR_DEVMATCH_Disabled (0UL) /*!< Read: Disabled */
8658 #define RADIO_INTENCLR_DEVMATCH_Enabled (1UL) /*!< Read: Enabled */
8659 #define RADIO_INTENCLR_DEVMATCH_Clear (1UL) /*!< Disable */
8660 
8661 /* Bit 4 : Write '1' to Disable interrupt for DISABLED event */
8662 #define RADIO_INTENCLR_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */
8663 #define RADIO_INTENCLR_DISABLED_Msk (0x1UL << RADIO_INTENCLR_DISABLED_Pos) /*!< Bit mask of DISABLED field. */
8664 #define RADIO_INTENCLR_DISABLED_Disabled (0UL) /*!< Read: Disabled */
8665 #define RADIO_INTENCLR_DISABLED_Enabled (1UL) /*!< Read: Enabled */
8666 #define RADIO_INTENCLR_DISABLED_Clear (1UL) /*!< Disable */
8667 
8668 /* Bit 3 : Write '1' to Disable interrupt for END event */
8669 #define RADIO_INTENCLR_END_Pos (3UL) /*!< Position of END field. */
8670 #define RADIO_INTENCLR_END_Msk (0x1UL << RADIO_INTENCLR_END_Pos) /*!< Bit mask of END field. */
8671 #define RADIO_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
8672 #define RADIO_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
8673 #define RADIO_INTENCLR_END_Clear (1UL) /*!< Disable */
8674 
8675 /* Bit 2 : Write '1' to Disable interrupt for PAYLOAD event */
8676 #define RADIO_INTENCLR_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */
8677 #define RADIO_INTENCLR_PAYLOAD_Msk (0x1UL << RADIO_INTENCLR_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */
8678 #define RADIO_INTENCLR_PAYLOAD_Disabled (0UL) /*!< Read: Disabled */
8679 #define RADIO_INTENCLR_PAYLOAD_Enabled (1UL) /*!< Read: Enabled */
8680 #define RADIO_INTENCLR_PAYLOAD_Clear (1UL) /*!< Disable */
8681 
8682 /* Bit 1 : Write '1' to Disable interrupt for ADDRESS event */
8683 #define RADIO_INTENCLR_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */
8684 #define RADIO_INTENCLR_ADDRESS_Msk (0x1UL << RADIO_INTENCLR_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
8685 #define RADIO_INTENCLR_ADDRESS_Disabled (0UL) /*!< Read: Disabled */
8686 #define RADIO_INTENCLR_ADDRESS_Enabled (1UL) /*!< Read: Enabled */
8687 #define RADIO_INTENCLR_ADDRESS_Clear (1UL) /*!< Disable */
8688 
8689 /* Bit 0 : Write '1' to Disable interrupt for READY event */
8690 #define RADIO_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */
8691 #define RADIO_INTENCLR_READY_Msk (0x1UL << RADIO_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
8692 #define RADIO_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */
8693 #define RADIO_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */
8694 #define RADIO_INTENCLR_READY_Clear (1UL) /*!< Disable */
8695 
8696 /* Register: RADIO_CRCSTATUS */
8697 /* Description: CRC status */
8698 
8699 /* Bit 0 : CRC status of packet received */
8700 #define RADIO_CRCSTATUS_CRCSTATUS_Pos (0UL) /*!< Position of CRCSTATUS field. */
8701 #define RADIO_CRCSTATUS_CRCSTATUS_Msk (0x1UL << RADIO_CRCSTATUS_CRCSTATUS_Pos) /*!< Bit mask of CRCSTATUS field. */
8702 #define RADIO_CRCSTATUS_CRCSTATUS_CRCError (0UL) /*!< Packet received with CRC error */
8703 #define RADIO_CRCSTATUS_CRCSTATUS_CRCOk (1UL) /*!< Packet received with CRC ok */
8704 
8705 /* Register: RADIO_RXMATCH */
8706 /* Description: Received address */
8707 
8708 /* Bits 2..0 : Received address */
8709 #define RADIO_RXMATCH_RXMATCH_Pos (0UL) /*!< Position of RXMATCH field. */
8710 #define RADIO_RXMATCH_RXMATCH_Msk (0x7UL << RADIO_RXMATCH_RXMATCH_Pos) /*!< Bit mask of RXMATCH field. */
8711 
8712 /* Register: RADIO_RXCRC */
8713 /* Description: CRC field of previously received packet */
8714 
8715 /* Bits 23..0 : CRC field of previously received packet */
8716 #define RADIO_RXCRC_RXCRC_Pos (0UL) /*!< Position of RXCRC field. */
8717 #define RADIO_RXCRC_RXCRC_Msk (0xFFFFFFUL << RADIO_RXCRC_RXCRC_Pos) /*!< Bit mask of RXCRC field. */
8718 
8719 /* Register: RADIO_DAI */
8720 /* Description: Device address match index */
8721 
8722 /* Bits 2..0 : Device address match index */
8723 #define RADIO_DAI_DAI_Pos (0UL) /*!< Position of DAI field. */
8724 #define RADIO_DAI_DAI_Msk (0x7UL << RADIO_DAI_DAI_Pos) /*!< Bit mask of DAI field. */
8725 
8726 /* Register: RADIO_PACKETPTR */
8727 /* Description: Packet pointer */
8728 
8729 /* Bits 31..0 : Packet pointer */
8730 #define RADIO_PACKETPTR_PACKETPTR_Pos (0UL) /*!< Position of PACKETPTR field. */
8731 #define RADIO_PACKETPTR_PACKETPTR_Msk (0xFFFFFFFFUL << RADIO_PACKETPTR_PACKETPTR_Pos) /*!< Bit mask of PACKETPTR field. */
8732 
8733 /* Register: RADIO_FREQUENCY */
8734 /* Description: Frequency */
8735 
8736 /* Bit 8 : Channel map selection. */
8737 #define RADIO_FREQUENCY_MAP_Pos (8UL) /*!< Position of MAP field. */
8738 #define RADIO_FREQUENCY_MAP_Msk (0x1UL << RADIO_FREQUENCY_MAP_Pos) /*!< Bit mask of MAP field. */
8739 #define RADIO_FREQUENCY_MAP_Default (0UL) /*!< Channel map between 2400 MHZ .. 2500 MHz */
8740 #define RADIO_FREQUENCY_MAP_Low (1UL) /*!< Channel map between 2360 MHZ .. 2460 MHz */
8741 
8742 /* Bits 6..0 : Radio channel frequency */
8743 #define RADIO_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
8744 #define RADIO_FREQUENCY_FREQUENCY_Msk (0x7FUL << RADIO_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
8745 
8746 /* Register: RADIO_TXPOWER */
8747 /* Description: Output power */
8748 
8749 /* Bits 7..0 : RADIO output power. */
8750 #define RADIO_TXPOWER_TXPOWER_Pos (0UL) /*!< Position of TXPOWER field. */
8751 #define RADIO_TXPOWER_TXPOWER_Msk (0xFFUL << RADIO_TXPOWER_TXPOWER_Pos) /*!< Bit mask of TXPOWER field. */
8752 #define RADIO_TXPOWER_TXPOWER_0dBm (0x00UL) /*!< 0 dBm */
8753 #define RADIO_TXPOWER_TXPOWER_Pos3dBm (0x03UL) /*!< +3 dBm */
8754 #define RADIO_TXPOWER_TXPOWER_Pos4dBm (0x04UL) /*!< +4 dBm */
8755 #define RADIO_TXPOWER_TXPOWER_Neg30dBm (0xD8UL) /*!< Deprecated enumerator -  -40 dBm */
8756 #define RADIO_TXPOWER_TXPOWER_Neg40dBm (0xD8UL) /*!< -40 dBm */
8757 #define RADIO_TXPOWER_TXPOWER_Neg20dBm (0xECUL) /*!< -20 dBm */
8758 #define RADIO_TXPOWER_TXPOWER_Neg16dBm (0xF0UL) /*!< -16 dBm */
8759 #define RADIO_TXPOWER_TXPOWER_Neg12dBm (0xF4UL) /*!< -12 dBm */
8760 #define RADIO_TXPOWER_TXPOWER_Neg8dBm (0xF8UL) /*!< -8 dBm */
8761 #define RADIO_TXPOWER_TXPOWER_Neg4dBm (0xFCUL) /*!< -4 dBm */
8762 
8763 /* Register: RADIO_MODE */
8764 /* Description: Data rate and modulation */
8765 
8766 /* Bits 3..0 : Radio data rate and modulation setting. The radio supports Frequency-shift Keying (FSK) modulation. */
8767 #define RADIO_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
8768 #define RADIO_MODE_MODE_Msk (0xFUL << RADIO_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
8769 #define RADIO_MODE_MODE_Nrf_1Mbit (0UL) /*!< 1 Mbit/s Nordic proprietary radio mode */
8770 #define RADIO_MODE_MODE_Nrf_2Mbit (1UL) /*!< 2 Mbit/s Nordic proprietary radio mode */
8771 #define RADIO_MODE_MODE_Nrf_250Kbit (2UL) /*!< Deprecated enumerator -  250 kbit/s Nordic proprietary radio mode */
8772 #define RADIO_MODE_MODE_Ble_1Mbit (3UL) /*!< 1 Mbit/s Bluetooth Low Energy */
8773 #define RADIO_MODE_MODE_Ble_2Mbit (4UL) /*!< 2 Mbit/s Bluetooth Low Energy */
8774 
8775 /* Register: RADIO_PCNF0 */
8776 /* Description: Packet configuration register 0 */
8777 
8778 /* Bit 24 : Length of preamble on air. Decision point: TASKS_START task */
8779 #define RADIO_PCNF0_PLEN_Pos (24UL) /*!< Position of PLEN field. */
8780 #define RADIO_PCNF0_PLEN_Msk (0x1UL << RADIO_PCNF0_PLEN_Pos) /*!< Bit mask of PLEN field. */
8781 #define RADIO_PCNF0_PLEN_8bit (0UL) /*!< 8-bit preamble */
8782 #define RADIO_PCNF0_PLEN_16bit (1UL) /*!< 16-bit preamble */
8783 
8784 /* Bit 20 : Include or exclude S1 field in RAM */
8785 #define RADIO_PCNF0_S1INCL_Pos (20UL) /*!< Position of S1INCL field. */
8786 #define RADIO_PCNF0_S1INCL_Msk (0x1UL << RADIO_PCNF0_S1INCL_Pos) /*!< Bit mask of S1INCL field. */
8787 #define RADIO_PCNF0_S1INCL_Automatic (0UL) /*!< Include S1 field in RAM only if S1LEN &gt; 0 */
8788 #define RADIO_PCNF0_S1INCL_Include (1UL) /*!< Always include S1 field in RAM independent of S1LEN */
8789 
8790 /* Bits 19..16 : Length on air of S1 field in number of bits. */
8791 #define RADIO_PCNF0_S1LEN_Pos (16UL) /*!< Position of S1LEN field. */
8792 #define RADIO_PCNF0_S1LEN_Msk (0xFUL << RADIO_PCNF0_S1LEN_Pos) /*!< Bit mask of S1LEN field. */
8793 
8794 /* Bit 8 : Length on air of S0 field in number of bytes. */
8795 #define RADIO_PCNF0_S0LEN_Pos (8UL) /*!< Position of S0LEN field. */
8796 #define RADIO_PCNF0_S0LEN_Msk (0x1UL << RADIO_PCNF0_S0LEN_Pos) /*!< Bit mask of S0LEN field. */
8797 
8798 /* Bits 3..0 : Length on air of LENGTH field in number of bits. */
8799 #define RADIO_PCNF0_LFLEN_Pos (0UL) /*!< Position of LFLEN field. */
8800 #define RADIO_PCNF0_LFLEN_Msk (0xFUL << RADIO_PCNF0_LFLEN_Pos) /*!< Bit mask of LFLEN field. */
8801 
8802 /* Register: RADIO_PCNF1 */
8803 /* Description: Packet configuration register 1 */
8804 
8805 /* Bit 25 : Enable or disable packet whitening */
8806 #define RADIO_PCNF1_WHITEEN_Pos (25UL) /*!< Position of WHITEEN field. */
8807 #define RADIO_PCNF1_WHITEEN_Msk (0x1UL << RADIO_PCNF1_WHITEEN_Pos) /*!< Bit mask of WHITEEN field. */
8808 #define RADIO_PCNF1_WHITEEN_Disabled (0UL) /*!< Disable */
8809 #define RADIO_PCNF1_WHITEEN_Enabled (1UL) /*!< Enable */
8810 
8811 /* Bit 24 : On air endianness of packet, this applies to the S0, LENGTH, S1 and the PAYLOAD fields. */
8812 #define RADIO_PCNF1_ENDIAN_Pos (24UL) /*!< Position of ENDIAN field. */
8813 #define RADIO_PCNF1_ENDIAN_Msk (0x1UL << RADIO_PCNF1_ENDIAN_Pos) /*!< Bit mask of ENDIAN field. */
8814 #define RADIO_PCNF1_ENDIAN_Little (0UL) /*!< Least Significant bit on air first */
8815 #define RADIO_PCNF1_ENDIAN_Big (1UL) /*!< Most significant bit on air first */
8816 
8817 /* Bits 18..16 : Base address length in number of bytes */
8818 #define RADIO_PCNF1_BALEN_Pos (16UL) /*!< Position of BALEN field. */
8819 #define RADIO_PCNF1_BALEN_Msk (0x7UL << RADIO_PCNF1_BALEN_Pos) /*!< Bit mask of BALEN field. */
8820 
8821 /* Bits 15..8 : Static length in number of bytes */
8822 #define RADIO_PCNF1_STATLEN_Pos (8UL) /*!< Position of STATLEN field. */
8823 #define RADIO_PCNF1_STATLEN_Msk (0xFFUL << RADIO_PCNF1_STATLEN_Pos) /*!< Bit mask of STATLEN field. */
8824 
8825 /* Bits 7..0 : Maximum length of packet payload. If the packet payload is larger than MAXLEN, the radio will truncate the payload to MAXLEN. */
8826 #define RADIO_PCNF1_MAXLEN_Pos (0UL) /*!< Position of MAXLEN field. */
8827 #define RADIO_PCNF1_MAXLEN_Msk (0xFFUL << RADIO_PCNF1_MAXLEN_Pos) /*!< Bit mask of MAXLEN field. */
8828 
8829 /* Register: RADIO_BASE0 */
8830 /* Description: Base address 0 */
8831 
8832 /* Bits 31..0 : Base address 0 */
8833 #define RADIO_BASE0_BASE0_Pos (0UL) /*!< Position of BASE0 field. */
8834 #define RADIO_BASE0_BASE0_Msk (0xFFFFFFFFUL << RADIO_BASE0_BASE0_Pos) /*!< Bit mask of BASE0 field. */
8835 
8836 /* Register: RADIO_BASE1 */
8837 /* Description: Base address 1 */
8838 
8839 /* Bits 31..0 : Base address 1 */
8840 #define RADIO_BASE1_BASE1_Pos (0UL) /*!< Position of BASE1 field. */
8841 #define RADIO_BASE1_BASE1_Msk (0xFFFFFFFFUL << RADIO_BASE1_BASE1_Pos) /*!< Bit mask of BASE1 field. */
8842 
8843 /* Register: RADIO_PREFIX0 */
8844 /* Description: Prefixes bytes for logical addresses 0-3 */
8845 
8846 /* Bits 31..24 : Address prefix 3. */
8847 #define RADIO_PREFIX0_AP3_Pos (24UL) /*!< Position of AP3 field. */
8848 #define RADIO_PREFIX0_AP3_Msk (0xFFUL << RADIO_PREFIX0_AP3_Pos) /*!< Bit mask of AP3 field. */
8849 
8850 /* Bits 23..16 : Address prefix 2. */
8851 #define RADIO_PREFIX0_AP2_Pos (16UL) /*!< Position of AP2 field. */
8852 #define RADIO_PREFIX0_AP2_Msk (0xFFUL << RADIO_PREFIX0_AP2_Pos) /*!< Bit mask of AP2 field. */
8853 
8854 /* Bits 15..8 : Address prefix 1. */
8855 #define RADIO_PREFIX0_AP1_Pos (8UL) /*!< Position of AP1 field. */
8856 #define RADIO_PREFIX0_AP1_Msk (0xFFUL << RADIO_PREFIX0_AP1_Pos) /*!< Bit mask of AP1 field. */
8857 
8858 /* Bits 7..0 : Address prefix 0. */
8859 #define RADIO_PREFIX0_AP0_Pos (0UL) /*!< Position of AP0 field. */
8860 #define RADIO_PREFIX0_AP0_Msk (0xFFUL << RADIO_PREFIX0_AP0_Pos) /*!< Bit mask of AP0 field. */
8861 
8862 /* Register: RADIO_PREFIX1 */
8863 /* Description: Prefixes bytes for logical addresses 4-7 */
8864 
8865 /* Bits 31..24 : Address prefix 7. */
8866 #define RADIO_PREFIX1_AP7_Pos (24UL) /*!< Position of AP7 field. */
8867 #define RADIO_PREFIX1_AP7_Msk (0xFFUL << RADIO_PREFIX1_AP7_Pos) /*!< Bit mask of AP7 field. */
8868 
8869 /* Bits 23..16 : Address prefix 6. */
8870 #define RADIO_PREFIX1_AP6_Pos (16UL) /*!< Position of AP6 field. */
8871 #define RADIO_PREFIX1_AP6_Msk (0xFFUL << RADIO_PREFIX1_AP6_Pos) /*!< Bit mask of AP6 field. */
8872 
8873 /* Bits 15..8 : Address prefix 5. */
8874 #define RADIO_PREFIX1_AP5_Pos (8UL) /*!< Position of AP5 field. */
8875 #define RADIO_PREFIX1_AP5_Msk (0xFFUL << RADIO_PREFIX1_AP5_Pos) /*!< Bit mask of AP5 field. */
8876 
8877 /* Bits 7..0 : Address prefix 4. */
8878 #define RADIO_PREFIX1_AP4_Pos (0UL) /*!< Position of AP4 field. */
8879 #define RADIO_PREFIX1_AP4_Msk (0xFFUL << RADIO_PREFIX1_AP4_Pos) /*!< Bit mask of AP4 field. */
8880 
8881 /* Register: RADIO_TXADDRESS */
8882 /* Description: Transmit address select */
8883 
8884 /* Bits 2..0 : Transmit address select */
8885 #define RADIO_TXADDRESS_TXADDRESS_Pos (0UL) /*!< Position of TXADDRESS field. */
8886 #define RADIO_TXADDRESS_TXADDRESS_Msk (0x7UL << RADIO_TXADDRESS_TXADDRESS_Pos) /*!< Bit mask of TXADDRESS field. */
8887 
8888 /* Register: RADIO_RXADDRESSES */
8889 /* Description: Receive address select */
8890 
8891 /* Bit 7 : Enable or disable reception on logical address 7. */
8892 #define RADIO_RXADDRESSES_ADDR7_Pos (7UL) /*!< Position of ADDR7 field. */
8893 #define RADIO_RXADDRESSES_ADDR7_Msk (0x1UL << RADIO_RXADDRESSES_ADDR7_Pos) /*!< Bit mask of ADDR7 field. */
8894 #define RADIO_RXADDRESSES_ADDR7_Disabled (0UL) /*!< Disable */
8895 #define RADIO_RXADDRESSES_ADDR7_Enabled (1UL) /*!< Enable */
8896 
8897 /* Bit 6 : Enable or disable reception on logical address 6. */
8898 #define RADIO_RXADDRESSES_ADDR6_Pos (6UL) /*!< Position of ADDR6 field. */
8899 #define RADIO_RXADDRESSES_ADDR6_Msk (0x1UL << RADIO_RXADDRESSES_ADDR6_Pos) /*!< Bit mask of ADDR6 field. */
8900 #define RADIO_RXADDRESSES_ADDR6_Disabled (0UL) /*!< Disable */
8901 #define RADIO_RXADDRESSES_ADDR6_Enabled (1UL) /*!< Enable */
8902 
8903 /* Bit 5 : Enable or disable reception on logical address 5. */
8904 #define RADIO_RXADDRESSES_ADDR5_Pos (5UL) /*!< Position of ADDR5 field. */
8905 #define RADIO_RXADDRESSES_ADDR5_Msk (0x1UL << RADIO_RXADDRESSES_ADDR5_Pos) /*!< Bit mask of ADDR5 field. */
8906 #define RADIO_RXADDRESSES_ADDR5_Disabled (0UL) /*!< Disable */
8907 #define RADIO_RXADDRESSES_ADDR5_Enabled (1UL) /*!< Enable */
8908 
8909 /* Bit 4 : Enable or disable reception on logical address 4. */
8910 #define RADIO_RXADDRESSES_ADDR4_Pos (4UL) /*!< Position of ADDR4 field. */
8911 #define RADIO_RXADDRESSES_ADDR4_Msk (0x1UL << RADIO_RXADDRESSES_ADDR4_Pos) /*!< Bit mask of ADDR4 field. */
8912 #define RADIO_RXADDRESSES_ADDR4_Disabled (0UL) /*!< Disable */
8913 #define RADIO_RXADDRESSES_ADDR4_Enabled (1UL) /*!< Enable */
8914 
8915 /* Bit 3 : Enable or disable reception on logical address 3. */
8916 #define RADIO_RXADDRESSES_ADDR3_Pos (3UL) /*!< Position of ADDR3 field. */
8917 #define RADIO_RXADDRESSES_ADDR3_Msk (0x1UL << RADIO_RXADDRESSES_ADDR3_Pos) /*!< Bit mask of ADDR3 field. */
8918 #define RADIO_RXADDRESSES_ADDR3_Disabled (0UL) /*!< Disable */
8919 #define RADIO_RXADDRESSES_ADDR3_Enabled (1UL) /*!< Enable */
8920 
8921 /* Bit 2 : Enable or disable reception on logical address 2. */
8922 #define RADIO_RXADDRESSES_ADDR2_Pos (2UL) /*!< Position of ADDR2 field. */
8923 #define RADIO_RXADDRESSES_ADDR2_Msk (0x1UL << RADIO_RXADDRESSES_ADDR2_Pos) /*!< Bit mask of ADDR2 field. */
8924 #define RADIO_RXADDRESSES_ADDR2_Disabled (0UL) /*!< Disable */
8925 #define RADIO_RXADDRESSES_ADDR2_Enabled (1UL) /*!< Enable */
8926 
8927 /* Bit 1 : Enable or disable reception on logical address 1. */
8928 #define RADIO_RXADDRESSES_ADDR1_Pos (1UL) /*!< Position of ADDR1 field. */
8929 #define RADIO_RXADDRESSES_ADDR1_Msk (0x1UL << RADIO_RXADDRESSES_ADDR1_Pos) /*!< Bit mask of ADDR1 field. */
8930 #define RADIO_RXADDRESSES_ADDR1_Disabled (0UL) /*!< Disable */
8931 #define RADIO_RXADDRESSES_ADDR1_Enabled (1UL) /*!< Enable */
8932 
8933 /* Bit 0 : Enable or disable reception on logical address 0. */
8934 #define RADIO_RXADDRESSES_ADDR0_Pos (0UL) /*!< Position of ADDR0 field. */
8935 #define RADIO_RXADDRESSES_ADDR0_Msk (0x1UL << RADIO_RXADDRESSES_ADDR0_Pos) /*!< Bit mask of ADDR0 field. */
8936 #define RADIO_RXADDRESSES_ADDR0_Disabled (0UL) /*!< Disable */
8937 #define RADIO_RXADDRESSES_ADDR0_Enabled (1UL) /*!< Enable */
8938 
8939 /* Register: RADIO_CRCCNF */
8940 /* Description: CRC configuration */
8941 
8942 /* Bit 8 : Include or exclude packet address field out of CRC calculation. */
8943 #define RADIO_CRCCNF_SKIPADDR_Pos (8UL) /*!< Position of SKIPADDR field. */
8944 #define RADIO_CRCCNF_SKIPADDR_Msk (0x1UL << RADIO_CRCCNF_SKIPADDR_Pos) /*!< Bit mask of SKIPADDR field. */
8945 #define RADIO_CRCCNF_SKIPADDR_Include (0UL) /*!< CRC calculation includes address field */
8946 #define RADIO_CRCCNF_SKIPADDR_Skip (1UL) /*!< CRC calculation does not include address field. The CRC calculation will start at the first byte after the address. */
8947 
8948 /* Bits 1..0 : CRC length in number of bytes. */
8949 #define RADIO_CRCCNF_LEN_Pos (0UL) /*!< Position of LEN field. */
8950 #define RADIO_CRCCNF_LEN_Msk (0x3UL << RADIO_CRCCNF_LEN_Pos) /*!< Bit mask of LEN field. */
8951 #define RADIO_CRCCNF_LEN_Disabled (0UL) /*!< CRC length is zero and CRC calculation is disabled */
8952 #define RADIO_CRCCNF_LEN_One (1UL) /*!< CRC length is one byte and CRC calculation is enabled */
8953 #define RADIO_CRCCNF_LEN_Two (2UL) /*!< CRC length is two bytes and CRC calculation is enabled */
8954 #define RADIO_CRCCNF_LEN_Three (3UL) /*!< CRC length is three bytes and CRC calculation is enabled */
8955 
8956 /* Register: RADIO_CRCPOLY */
8957 /* Description: CRC polynomial */
8958 
8959 /* Bits 23..0 : CRC polynomial */
8960 #define RADIO_CRCPOLY_CRCPOLY_Pos (0UL) /*!< Position of CRCPOLY field. */
8961 #define RADIO_CRCPOLY_CRCPOLY_Msk (0xFFFFFFUL << RADIO_CRCPOLY_CRCPOLY_Pos) /*!< Bit mask of CRCPOLY field. */
8962 
8963 /* Register: RADIO_CRCINIT */
8964 /* Description: CRC initial value */
8965 
8966 /* Bits 23..0 : CRC initial value */
8967 #define RADIO_CRCINIT_CRCINIT_Pos (0UL) /*!< Position of CRCINIT field. */
8968 #define RADIO_CRCINIT_CRCINIT_Msk (0xFFFFFFUL << RADIO_CRCINIT_CRCINIT_Pos) /*!< Bit mask of CRCINIT field. */
8969 
8970 /* Register: RADIO_TIFS */
8971 /* Description: Inter Frame Spacing in us */
8972 
8973 /* Bits 7..0 : Inter Frame Spacing in us */
8974 #define RADIO_TIFS_TIFS_Pos (0UL) /*!< Position of TIFS field. */
8975 #define RADIO_TIFS_TIFS_Msk (0xFFUL << RADIO_TIFS_TIFS_Pos) /*!< Bit mask of TIFS field. */
8976 
8977 /* Register: RADIO_RSSISAMPLE */
8978 /* Description: RSSI sample */
8979 
8980 /* Bits 6..0 : RSSI sample */
8981 #define RADIO_RSSISAMPLE_RSSISAMPLE_Pos (0UL) /*!< Position of RSSISAMPLE field. */
8982 #define RADIO_RSSISAMPLE_RSSISAMPLE_Msk (0x7FUL << RADIO_RSSISAMPLE_RSSISAMPLE_Pos) /*!< Bit mask of RSSISAMPLE field. */
8983 
8984 /* Register: RADIO_STATE */
8985 /* Description: Current radio state */
8986 
8987 /* Bits 3..0 : Current radio state */
8988 #define RADIO_STATE_STATE_Pos (0UL) /*!< Position of STATE field. */
8989 #define RADIO_STATE_STATE_Msk (0xFUL << RADIO_STATE_STATE_Pos) /*!< Bit mask of STATE field. */
8990 #define RADIO_STATE_STATE_Disabled (0UL) /*!< RADIO is in the Disabled state */
8991 #define RADIO_STATE_STATE_RxRu (1UL) /*!< RADIO is in the RXRU state */
8992 #define RADIO_STATE_STATE_RxIdle (2UL) /*!< RADIO is in the RXIDLE state */
8993 #define RADIO_STATE_STATE_Rx (3UL) /*!< RADIO is in the RX state */
8994 #define RADIO_STATE_STATE_RxDisable (4UL) /*!< RADIO is in the RXDISABLED state */
8995 #define RADIO_STATE_STATE_TxRu (9UL) /*!< RADIO is in the TXRU state */
8996 #define RADIO_STATE_STATE_TxIdle (10UL) /*!< RADIO is in the TXIDLE state */
8997 #define RADIO_STATE_STATE_Tx (11UL) /*!< RADIO is in the TX state */
8998 #define RADIO_STATE_STATE_TxDisable (12UL) /*!< RADIO is in the TXDISABLED state */
8999 
9000 /* Register: RADIO_DATAWHITEIV */
9001 /* Description: Data whitening initial value */
9002 
9003 /* Bits 6..0 : Data whitening initial value. Bit 6 is hard-wired to '1', writing '0' to it has no effect, and it will always be read back and used by the device as '1'. */
9004 #define RADIO_DATAWHITEIV_DATAWHITEIV_Pos (0UL) /*!< Position of DATAWHITEIV field. */
9005 #define RADIO_DATAWHITEIV_DATAWHITEIV_Msk (0x7FUL << RADIO_DATAWHITEIV_DATAWHITEIV_Pos) /*!< Bit mask of DATAWHITEIV field. */
9006 
9007 /* Register: RADIO_BCC */
9008 /* Description: Bit counter compare */
9009 
9010 /* Bits 31..0 : Bit counter compare */
9011 #define RADIO_BCC_BCC_Pos (0UL) /*!< Position of BCC field. */
9012 #define RADIO_BCC_BCC_Msk (0xFFFFFFFFUL << RADIO_BCC_BCC_Pos) /*!< Bit mask of BCC field. */
9013 
9014 /* Register: RADIO_DAB */
9015 /* Description: Description collection[0]:  Device address base segment 0 */
9016 
9017 /* Bits 31..0 : Device address base segment 0 */
9018 #define RADIO_DAB_DAB_Pos (0UL) /*!< Position of DAB field. */
9019 #define RADIO_DAB_DAB_Msk (0xFFFFFFFFUL << RADIO_DAB_DAB_Pos) /*!< Bit mask of DAB field. */
9020 
9021 /* Register: RADIO_DAP */
9022 /* Description: Description collection[0]:  Device address prefix 0 */
9023 
9024 /* Bits 15..0 : Device address prefix 0 */
9025 #define RADIO_DAP_DAP_Pos (0UL) /*!< Position of DAP field. */
9026 #define RADIO_DAP_DAP_Msk (0xFFFFUL << RADIO_DAP_DAP_Pos) /*!< Bit mask of DAP field. */
9027 
9028 /* Register: RADIO_DACNF */
9029 /* Description: Device address match configuration */
9030 
9031 /* Bit 15 : TxAdd for device address 7 */
9032 #define RADIO_DACNF_TXADD7_Pos (15UL) /*!< Position of TXADD7 field. */
9033 #define RADIO_DACNF_TXADD7_Msk (0x1UL << RADIO_DACNF_TXADD7_Pos) /*!< Bit mask of TXADD7 field. */
9034 
9035 /* Bit 14 : TxAdd for device address 6 */
9036 #define RADIO_DACNF_TXADD6_Pos (14UL) /*!< Position of TXADD6 field. */
9037 #define RADIO_DACNF_TXADD6_Msk (0x1UL << RADIO_DACNF_TXADD6_Pos) /*!< Bit mask of TXADD6 field. */
9038 
9039 /* Bit 13 : TxAdd for device address 5 */
9040 #define RADIO_DACNF_TXADD5_Pos (13UL) /*!< Position of TXADD5 field. */
9041 #define RADIO_DACNF_TXADD5_Msk (0x1UL << RADIO_DACNF_TXADD5_Pos) /*!< Bit mask of TXADD5 field. */
9042 
9043 /* Bit 12 : TxAdd for device address 4 */
9044 #define RADIO_DACNF_TXADD4_Pos (12UL) /*!< Position of TXADD4 field. */
9045 #define RADIO_DACNF_TXADD4_Msk (0x1UL << RADIO_DACNF_TXADD4_Pos) /*!< Bit mask of TXADD4 field. */
9046 
9047 /* Bit 11 : TxAdd for device address 3 */
9048 #define RADIO_DACNF_TXADD3_Pos (11UL) /*!< Position of TXADD3 field. */
9049 #define RADIO_DACNF_TXADD3_Msk (0x1UL << RADIO_DACNF_TXADD3_Pos) /*!< Bit mask of TXADD3 field. */
9050 
9051 /* Bit 10 : TxAdd for device address 2 */
9052 #define RADIO_DACNF_TXADD2_Pos (10UL) /*!< Position of TXADD2 field. */
9053 #define RADIO_DACNF_TXADD2_Msk (0x1UL << RADIO_DACNF_TXADD2_Pos) /*!< Bit mask of TXADD2 field. */
9054 
9055 /* Bit 9 : TxAdd for device address 1 */
9056 #define RADIO_DACNF_TXADD1_Pos (9UL) /*!< Position of TXADD1 field. */
9057 #define RADIO_DACNF_TXADD1_Msk (0x1UL << RADIO_DACNF_TXADD1_Pos) /*!< Bit mask of TXADD1 field. */
9058 
9059 /* Bit 8 : TxAdd for device address 0 */
9060 #define RADIO_DACNF_TXADD0_Pos (8UL) /*!< Position of TXADD0 field. */
9061 #define RADIO_DACNF_TXADD0_Msk (0x1UL << RADIO_DACNF_TXADD0_Pos) /*!< Bit mask of TXADD0 field. */
9062 
9063 /* Bit 7 : Enable or disable device address matching using device address 7 */
9064 #define RADIO_DACNF_ENA7_Pos (7UL) /*!< Position of ENA7 field. */
9065 #define RADIO_DACNF_ENA7_Msk (0x1UL << RADIO_DACNF_ENA7_Pos) /*!< Bit mask of ENA7 field. */
9066 #define RADIO_DACNF_ENA7_Disabled (0UL) /*!< Disabled */
9067 #define RADIO_DACNF_ENA7_Enabled (1UL) /*!< Enabled */
9068 
9069 /* Bit 6 : Enable or disable device address matching using device address 6 */
9070 #define RADIO_DACNF_ENA6_Pos (6UL) /*!< Position of ENA6 field. */
9071 #define RADIO_DACNF_ENA6_Msk (0x1UL << RADIO_DACNF_ENA6_Pos) /*!< Bit mask of ENA6 field. */
9072 #define RADIO_DACNF_ENA6_Disabled (0UL) /*!< Disabled */
9073 #define RADIO_DACNF_ENA6_Enabled (1UL) /*!< Enabled */
9074 
9075 /* Bit 5 : Enable or disable device address matching using device address 5 */
9076 #define RADIO_DACNF_ENA5_Pos (5UL) /*!< Position of ENA5 field. */
9077 #define RADIO_DACNF_ENA5_Msk (0x1UL << RADIO_DACNF_ENA5_Pos) /*!< Bit mask of ENA5 field. */
9078 #define RADIO_DACNF_ENA5_Disabled (0UL) /*!< Disabled */
9079 #define RADIO_DACNF_ENA5_Enabled (1UL) /*!< Enabled */
9080 
9081 /* Bit 4 : Enable or disable device address matching using device address 4 */
9082 #define RADIO_DACNF_ENA4_Pos (4UL) /*!< Position of ENA4 field. */
9083 #define RADIO_DACNF_ENA4_Msk (0x1UL << RADIO_DACNF_ENA4_Pos) /*!< Bit mask of ENA4 field. */
9084 #define RADIO_DACNF_ENA4_Disabled (0UL) /*!< Disabled */
9085 #define RADIO_DACNF_ENA4_Enabled (1UL) /*!< Enabled */
9086 
9087 /* Bit 3 : Enable or disable device address matching using device address 3 */
9088 #define RADIO_DACNF_ENA3_Pos (3UL) /*!< Position of ENA3 field. */
9089 #define RADIO_DACNF_ENA3_Msk (0x1UL << RADIO_DACNF_ENA3_Pos) /*!< Bit mask of ENA3 field. */
9090 #define RADIO_DACNF_ENA3_Disabled (0UL) /*!< Disabled */
9091 #define RADIO_DACNF_ENA3_Enabled (1UL) /*!< Enabled */
9092 
9093 /* Bit 2 : Enable or disable device address matching using device address 2 */
9094 #define RADIO_DACNF_ENA2_Pos (2UL) /*!< Position of ENA2 field. */
9095 #define RADIO_DACNF_ENA2_Msk (0x1UL << RADIO_DACNF_ENA2_Pos) /*!< Bit mask of ENA2 field. */
9096 #define RADIO_DACNF_ENA2_Disabled (0UL) /*!< Disabled */
9097 #define RADIO_DACNF_ENA2_Enabled (1UL) /*!< Enabled */
9098 
9099 /* Bit 1 : Enable or disable device address matching using device address 1 */
9100 #define RADIO_DACNF_ENA1_Pos (1UL) /*!< Position of ENA1 field. */
9101 #define RADIO_DACNF_ENA1_Msk (0x1UL << RADIO_DACNF_ENA1_Pos) /*!< Bit mask of ENA1 field. */
9102 #define RADIO_DACNF_ENA1_Disabled (0UL) /*!< Disabled */
9103 #define RADIO_DACNF_ENA1_Enabled (1UL) /*!< Enabled */
9104 
9105 /* Bit 0 : Enable or disable device address matching using device address 0 */
9106 #define RADIO_DACNF_ENA0_Pos (0UL) /*!< Position of ENA0 field. */
9107 #define RADIO_DACNF_ENA0_Msk (0x1UL << RADIO_DACNF_ENA0_Pos) /*!< Bit mask of ENA0 field. */
9108 #define RADIO_DACNF_ENA0_Disabled (0UL) /*!< Disabled */
9109 #define RADIO_DACNF_ENA0_Enabled (1UL) /*!< Enabled */
9110 
9111 /* Register: RADIO_MODECNF0 */
9112 /* Description: Radio mode configuration register 0 */
9113 
9114 /* Bits 9..8 : Default TX value */
9115 #define RADIO_MODECNF0_DTX_Pos (8UL) /*!< Position of DTX field. */
9116 #define RADIO_MODECNF0_DTX_Msk (0x3UL << RADIO_MODECNF0_DTX_Pos) /*!< Bit mask of DTX field. */
9117 #define RADIO_MODECNF0_DTX_B1 (0UL) /*!< Transmit '1' */
9118 #define RADIO_MODECNF0_DTX_B0 (1UL) /*!< Transmit '0' */
9119 #define RADIO_MODECNF0_DTX_Center (2UL) /*!< Transmit center frequency */
9120 
9121 /* Bit 0 : Radio ramp-up time */
9122 #define RADIO_MODECNF0_RU_Pos (0UL) /*!< Position of RU field. */
9123 #define RADIO_MODECNF0_RU_Msk (0x1UL << RADIO_MODECNF0_RU_Pos) /*!< Bit mask of RU field. */
9124 #define RADIO_MODECNF0_RU_Default (0UL) /*!< Default ramp-up time (tRXEN), compatible with firmware written for nRF51 */
9125 #define RADIO_MODECNF0_RU_Fast (1UL) /*!< Fast ramp-up (tRXEN,FAST), see electrical specification for more information */
9126 
9127 /* Register: RADIO_POWER */
9128 /* Description: Peripheral power control */
9129 
9130 /* Bit 0 : Peripheral power control. The peripheral and its registers will be reset to its initial state by switching the peripheral off and then back on again. */
9131 #define RADIO_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
9132 #define RADIO_POWER_POWER_Msk (0x1UL << RADIO_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
9133 #define RADIO_POWER_POWER_Disabled (0UL) /*!< Peripheral is powered off */
9134 #define RADIO_POWER_POWER_Enabled (1UL) /*!< Peripheral is powered on */
9135 
9136 
9137 /* Peripheral: RNG */
9138 /* Description: Random Number Generator */
9139 
9140 /* Register: RNG_SHORTS */
9141 /* Description: Shortcut register */
9142 
9143 /* Bit 0 : Shortcut between VALRDY event and STOP task */
9144 #define RNG_SHORTS_VALRDY_STOP_Pos (0UL) /*!< Position of VALRDY_STOP field. */
9145 #define RNG_SHORTS_VALRDY_STOP_Msk (0x1UL << RNG_SHORTS_VALRDY_STOP_Pos) /*!< Bit mask of VALRDY_STOP field. */
9146 #define RNG_SHORTS_VALRDY_STOP_Disabled (0UL) /*!< Disable shortcut */
9147 #define RNG_SHORTS_VALRDY_STOP_Enabled (1UL) /*!< Enable shortcut */
9148 
9149 /* Register: RNG_INTENSET */
9150 /* Description: Enable interrupt */
9151 
9152 /* Bit 0 : Write '1' to Enable interrupt for VALRDY event */
9153 #define RNG_INTENSET_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */
9154 #define RNG_INTENSET_VALRDY_Msk (0x1UL << RNG_INTENSET_VALRDY_Pos) /*!< Bit mask of VALRDY field. */
9155 #define RNG_INTENSET_VALRDY_Disabled (0UL) /*!< Read: Disabled */
9156 #define RNG_INTENSET_VALRDY_Enabled (1UL) /*!< Read: Enabled */
9157 #define RNG_INTENSET_VALRDY_Set (1UL) /*!< Enable */
9158 
9159 /* Register: RNG_INTENCLR */
9160 /* Description: Disable interrupt */
9161 
9162 /* Bit 0 : Write '1' to Disable interrupt for VALRDY event */
9163 #define RNG_INTENCLR_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */
9164 #define RNG_INTENCLR_VALRDY_Msk (0x1UL << RNG_INTENCLR_VALRDY_Pos) /*!< Bit mask of VALRDY field. */
9165 #define RNG_INTENCLR_VALRDY_Disabled (0UL) /*!< Read: Disabled */
9166 #define RNG_INTENCLR_VALRDY_Enabled (1UL) /*!< Read: Enabled */
9167 #define RNG_INTENCLR_VALRDY_Clear (1UL) /*!< Disable */
9168 
9169 /* Register: RNG_CONFIG */
9170 /* Description: Configuration register */
9171 
9172 /* Bit 0 : Bias correction */
9173 #define RNG_CONFIG_DERCEN_Pos (0UL) /*!< Position of DERCEN field. */
9174 #define RNG_CONFIG_DERCEN_Msk (0x1UL << RNG_CONFIG_DERCEN_Pos) /*!< Bit mask of DERCEN field. */
9175 #define RNG_CONFIG_DERCEN_Disabled (0UL) /*!< Disabled */
9176 #define RNG_CONFIG_DERCEN_Enabled (1UL) /*!< Enabled */
9177 
9178 /* Register: RNG_VALUE */
9179 /* Description: Output random number */
9180 
9181 /* Bits 7..0 : Generated random number */
9182 #define RNG_VALUE_VALUE_Pos (0UL) /*!< Position of VALUE field. */
9183 #define RNG_VALUE_VALUE_Msk (0xFFUL << RNG_VALUE_VALUE_Pos) /*!< Bit mask of VALUE field. */
9184 
9185 
9186 /* Peripheral: RTC */
9187 /* Description: Real time counter 0 */
9188 
9189 /* Register: RTC_INTENSET */
9190 /* Description: Enable interrupt */
9191 
9192 /* Bit 19 : Write '1' to Enable interrupt for COMPARE[3] event */
9193 #define RTC_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
9194 #define RTC_INTENSET_COMPARE3_Msk (0x1UL << RTC_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
9195 #define RTC_INTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
9196 #define RTC_INTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
9197 #define RTC_INTENSET_COMPARE3_Set (1UL) /*!< Enable */
9198 
9199 /* Bit 18 : Write '1' to Enable interrupt for COMPARE[2] event */
9200 #define RTC_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
9201 #define RTC_INTENSET_COMPARE2_Msk (0x1UL << RTC_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
9202 #define RTC_INTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
9203 #define RTC_INTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
9204 #define RTC_INTENSET_COMPARE2_Set (1UL) /*!< Enable */
9205 
9206 /* Bit 17 : Write '1' to Enable interrupt for COMPARE[1] event */
9207 #define RTC_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
9208 #define RTC_INTENSET_COMPARE1_Msk (0x1UL << RTC_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
9209 #define RTC_INTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
9210 #define RTC_INTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
9211 #define RTC_INTENSET_COMPARE1_Set (1UL) /*!< Enable */
9212 
9213 /* Bit 16 : Write '1' to Enable interrupt for COMPARE[0] event */
9214 #define RTC_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
9215 #define RTC_INTENSET_COMPARE0_Msk (0x1UL << RTC_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
9216 #define RTC_INTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
9217 #define RTC_INTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
9218 #define RTC_INTENSET_COMPARE0_Set (1UL) /*!< Enable */
9219 
9220 /* Bit 1 : Write '1' to Enable interrupt for OVRFLW event */
9221 #define RTC_INTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
9222 #define RTC_INTENSET_OVRFLW_Msk (0x1UL << RTC_INTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
9223 #define RTC_INTENSET_OVRFLW_Disabled (0UL) /*!< Read: Disabled */
9224 #define RTC_INTENSET_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
9225 #define RTC_INTENSET_OVRFLW_Set (1UL) /*!< Enable */
9226 
9227 /* Bit 0 : Write '1' to Enable interrupt for TICK event */
9228 #define RTC_INTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */
9229 #define RTC_INTENSET_TICK_Msk (0x1UL << RTC_INTENSET_TICK_Pos) /*!< Bit mask of TICK field. */
9230 #define RTC_INTENSET_TICK_Disabled (0UL) /*!< Read: Disabled */
9231 #define RTC_INTENSET_TICK_Enabled (1UL) /*!< Read: Enabled */
9232 #define RTC_INTENSET_TICK_Set (1UL) /*!< Enable */
9233 
9234 /* Register: RTC_INTENCLR */
9235 /* Description: Disable interrupt */
9236 
9237 /* Bit 19 : Write '1' to Disable interrupt for COMPARE[3] event */
9238 #define RTC_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
9239 #define RTC_INTENCLR_COMPARE3_Msk (0x1UL << RTC_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
9240 #define RTC_INTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
9241 #define RTC_INTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
9242 #define RTC_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable */
9243 
9244 /* Bit 18 : Write '1' to Disable interrupt for COMPARE[2] event */
9245 #define RTC_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
9246 #define RTC_INTENCLR_COMPARE2_Msk (0x1UL << RTC_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
9247 #define RTC_INTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
9248 #define RTC_INTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
9249 #define RTC_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable */
9250 
9251 /* Bit 17 : Write '1' to Disable interrupt for COMPARE[1] event */
9252 #define RTC_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
9253 #define RTC_INTENCLR_COMPARE1_Msk (0x1UL << RTC_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
9254 #define RTC_INTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
9255 #define RTC_INTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
9256 #define RTC_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable */
9257 
9258 /* Bit 16 : Write '1' to Disable interrupt for COMPARE[0] event */
9259 #define RTC_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
9260 #define RTC_INTENCLR_COMPARE0_Msk (0x1UL << RTC_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
9261 #define RTC_INTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
9262 #define RTC_INTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
9263 #define RTC_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable */
9264 
9265 /* Bit 1 : Write '1' to Disable interrupt for OVRFLW event */
9266 #define RTC_INTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
9267 #define RTC_INTENCLR_OVRFLW_Msk (0x1UL << RTC_INTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
9268 #define RTC_INTENCLR_OVRFLW_Disabled (0UL) /*!< Read: Disabled */
9269 #define RTC_INTENCLR_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
9270 #define RTC_INTENCLR_OVRFLW_Clear (1UL) /*!< Disable */
9271 
9272 /* Bit 0 : Write '1' to Disable interrupt for TICK event */
9273 #define RTC_INTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */
9274 #define RTC_INTENCLR_TICK_Msk (0x1UL << RTC_INTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */
9275 #define RTC_INTENCLR_TICK_Disabled (0UL) /*!< Read: Disabled */
9276 #define RTC_INTENCLR_TICK_Enabled (1UL) /*!< Read: Enabled */
9277 #define RTC_INTENCLR_TICK_Clear (1UL) /*!< Disable */
9278 
9279 /* Register: RTC_EVTEN */
9280 /* Description: Enable or disable event routing */
9281 
9282 /* Bit 19 : Enable or disable event routing for COMPARE[3] event */
9283 #define RTC_EVTEN_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
9284 #define RTC_EVTEN_COMPARE3_Msk (0x1UL << RTC_EVTEN_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
9285 #define RTC_EVTEN_COMPARE3_Disabled (0UL) /*!< Disable */
9286 #define RTC_EVTEN_COMPARE3_Enabled (1UL) /*!< Enable */
9287 
9288 /* Bit 18 : Enable or disable event routing for COMPARE[2] event */
9289 #define RTC_EVTEN_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
9290 #define RTC_EVTEN_COMPARE2_Msk (0x1UL << RTC_EVTEN_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
9291 #define RTC_EVTEN_COMPARE2_Disabled (0UL) /*!< Disable */
9292 #define RTC_EVTEN_COMPARE2_Enabled (1UL) /*!< Enable */
9293 
9294 /* Bit 17 : Enable or disable event routing for COMPARE[1] event */
9295 #define RTC_EVTEN_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
9296 #define RTC_EVTEN_COMPARE1_Msk (0x1UL << RTC_EVTEN_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
9297 #define RTC_EVTEN_COMPARE1_Disabled (0UL) /*!< Disable */
9298 #define RTC_EVTEN_COMPARE1_Enabled (1UL) /*!< Enable */
9299 
9300 /* Bit 16 : Enable or disable event routing for COMPARE[0] event */
9301 #define RTC_EVTEN_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
9302 #define RTC_EVTEN_COMPARE0_Msk (0x1UL << RTC_EVTEN_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
9303 #define RTC_EVTEN_COMPARE0_Disabled (0UL) /*!< Disable */
9304 #define RTC_EVTEN_COMPARE0_Enabled (1UL) /*!< Enable */
9305 
9306 /* Bit 1 : Enable or disable event routing for OVRFLW event */
9307 #define RTC_EVTEN_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
9308 #define RTC_EVTEN_OVRFLW_Msk (0x1UL << RTC_EVTEN_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
9309 #define RTC_EVTEN_OVRFLW_Disabled (0UL) /*!< Disable */
9310 #define RTC_EVTEN_OVRFLW_Enabled (1UL) /*!< Enable */
9311 
9312 /* Bit 0 : Enable or disable event routing for TICK event */
9313 #define RTC_EVTEN_TICK_Pos (0UL) /*!< Position of TICK field. */
9314 #define RTC_EVTEN_TICK_Msk (0x1UL << RTC_EVTEN_TICK_Pos) /*!< Bit mask of TICK field. */
9315 #define RTC_EVTEN_TICK_Disabled (0UL) /*!< Disable */
9316 #define RTC_EVTEN_TICK_Enabled (1UL) /*!< Enable */
9317 
9318 /* Register: RTC_EVTENSET */
9319 /* Description: Enable event routing */
9320 
9321 /* Bit 19 : Write '1' to Enable event routing for COMPARE[3] event */
9322 #define RTC_EVTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
9323 #define RTC_EVTENSET_COMPARE3_Msk (0x1UL << RTC_EVTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
9324 #define RTC_EVTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
9325 #define RTC_EVTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
9326 #define RTC_EVTENSET_COMPARE3_Set (1UL) /*!< Enable */
9327 
9328 /* Bit 18 : Write '1' to Enable event routing for COMPARE[2] event */
9329 #define RTC_EVTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
9330 #define RTC_EVTENSET_COMPARE2_Msk (0x1UL << RTC_EVTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
9331 #define RTC_EVTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
9332 #define RTC_EVTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
9333 #define RTC_EVTENSET_COMPARE2_Set (1UL) /*!< Enable */
9334 
9335 /* Bit 17 : Write '1' to Enable event routing for COMPARE[1] event */
9336 #define RTC_EVTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
9337 #define RTC_EVTENSET_COMPARE1_Msk (0x1UL << RTC_EVTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
9338 #define RTC_EVTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
9339 #define RTC_EVTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
9340 #define RTC_EVTENSET_COMPARE1_Set (1UL) /*!< Enable */
9341 
9342 /* Bit 16 : Write '1' to Enable event routing for COMPARE[0] event */
9343 #define RTC_EVTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
9344 #define RTC_EVTENSET_COMPARE0_Msk (0x1UL << RTC_EVTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
9345 #define RTC_EVTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
9346 #define RTC_EVTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
9347 #define RTC_EVTENSET_COMPARE0_Set (1UL) /*!< Enable */
9348 
9349 /* Bit 1 : Write '1' to Enable event routing for OVRFLW event */
9350 #define RTC_EVTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
9351 #define RTC_EVTENSET_OVRFLW_Msk (0x1UL << RTC_EVTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
9352 #define RTC_EVTENSET_OVRFLW_Disabled (0UL) /*!< Read: Disabled */
9353 #define RTC_EVTENSET_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
9354 #define RTC_EVTENSET_OVRFLW_Set (1UL) /*!< Enable */
9355 
9356 /* Bit 0 : Write '1' to Enable event routing for TICK event */
9357 #define RTC_EVTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */
9358 #define RTC_EVTENSET_TICK_Msk (0x1UL << RTC_EVTENSET_TICK_Pos) /*!< Bit mask of TICK field. */
9359 #define RTC_EVTENSET_TICK_Disabled (0UL) /*!< Read: Disabled */
9360 #define RTC_EVTENSET_TICK_Enabled (1UL) /*!< Read: Enabled */
9361 #define RTC_EVTENSET_TICK_Set (1UL) /*!< Enable */
9362 
9363 /* Register: RTC_EVTENCLR */
9364 /* Description: Disable event routing */
9365 
9366 /* Bit 19 : Write '1' to Disable event routing for COMPARE[3] event */
9367 #define RTC_EVTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
9368 #define RTC_EVTENCLR_COMPARE3_Msk (0x1UL << RTC_EVTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
9369 #define RTC_EVTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
9370 #define RTC_EVTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
9371 #define RTC_EVTENCLR_COMPARE3_Clear (1UL) /*!< Disable */
9372 
9373 /* Bit 18 : Write '1' to Disable event routing for COMPARE[2] event */
9374 #define RTC_EVTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
9375 #define RTC_EVTENCLR_COMPARE2_Msk (0x1UL << RTC_EVTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
9376 #define RTC_EVTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
9377 #define RTC_EVTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
9378 #define RTC_EVTENCLR_COMPARE2_Clear (1UL) /*!< Disable */
9379 
9380 /* Bit 17 : Write '1' to Disable event routing for COMPARE[1] event */
9381 #define RTC_EVTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
9382 #define RTC_EVTENCLR_COMPARE1_Msk (0x1UL << RTC_EVTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
9383 #define RTC_EVTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
9384 #define RTC_EVTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
9385 #define RTC_EVTENCLR_COMPARE1_Clear (1UL) /*!< Disable */
9386 
9387 /* Bit 16 : Write '1' to Disable event routing for COMPARE[0] event */
9388 #define RTC_EVTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
9389 #define RTC_EVTENCLR_COMPARE0_Msk (0x1UL << RTC_EVTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
9390 #define RTC_EVTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
9391 #define RTC_EVTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
9392 #define RTC_EVTENCLR_COMPARE0_Clear (1UL) /*!< Disable */
9393 
9394 /* Bit 1 : Write '1' to Disable event routing for OVRFLW event */
9395 #define RTC_EVTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
9396 #define RTC_EVTENCLR_OVRFLW_Msk (0x1UL << RTC_EVTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
9397 #define RTC_EVTENCLR_OVRFLW_Disabled (0UL) /*!< Read: Disabled */
9398 #define RTC_EVTENCLR_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
9399 #define RTC_EVTENCLR_OVRFLW_Clear (1UL) /*!< Disable */
9400 
9401 /* Bit 0 : Write '1' to Disable event routing for TICK event */
9402 #define RTC_EVTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */
9403 #define RTC_EVTENCLR_TICK_Msk (0x1UL << RTC_EVTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */
9404 #define RTC_EVTENCLR_TICK_Disabled (0UL) /*!< Read: Disabled */
9405 #define RTC_EVTENCLR_TICK_Enabled (1UL) /*!< Read: Enabled */
9406 #define RTC_EVTENCLR_TICK_Clear (1UL) /*!< Disable */
9407 
9408 /* Register: RTC_COUNTER */
9409 /* Description: Current COUNTER value */
9410 
9411 /* Bits 23..0 : Counter value */
9412 #define RTC_COUNTER_COUNTER_Pos (0UL) /*!< Position of COUNTER field. */
9413 #define RTC_COUNTER_COUNTER_Msk (0xFFFFFFUL << RTC_COUNTER_COUNTER_Pos) /*!< Bit mask of COUNTER field. */
9414 
9415 /* Register: RTC_PRESCALER */
9416 /* Description: 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Must be written when RTC is stopped */
9417 
9418 /* Bits 11..0 : Prescaler value */
9419 #define RTC_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */
9420 #define RTC_PRESCALER_PRESCALER_Msk (0xFFFUL << RTC_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */
9421 
9422 /* Register: RTC_CC */
9423 /* Description: Description collection[0]:  Compare register 0 */
9424 
9425 /* Bits 23..0 : Compare value */
9426 #define RTC_CC_COMPARE_Pos (0UL) /*!< Position of COMPARE field. */
9427 #define RTC_CC_COMPARE_Msk (0xFFFFFFUL << RTC_CC_COMPARE_Pos) /*!< Bit mask of COMPARE field. */
9428 
9429 
9430 /* Peripheral: SAADC */
9431 /* Description: Analog to Digital Converter */
9432 
9433 /* Register: SAADC_INTEN */
9434 /* Description: Enable or disable interrupt */
9435 
9436 /* Bit 21 : Enable or disable interrupt for CH[7].LIMITL event */
9437 #define SAADC_INTEN_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */
9438 #define SAADC_INTEN_CH7LIMITL_Msk (0x1UL << SAADC_INTEN_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */
9439 #define SAADC_INTEN_CH7LIMITL_Disabled (0UL) /*!< Disable */
9440 #define SAADC_INTEN_CH7LIMITL_Enabled (1UL) /*!< Enable */
9441 
9442 /* Bit 20 : Enable or disable interrupt for CH[7].LIMITH event */
9443 #define SAADC_INTEN_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */
9444 #define SAADC_INTEN_CH7LIMITH_Msk (0x1UL << SAADC_INTEN_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */
9445 #define SAADC_INTEN_CH7LIMITH_Disabled (0UL) /*!< Disable */
9446 #define SAADC_INTEN_CH7LIMITH_Enabled (1UL) /*!< Enable */
9447 
9448 /* Bit 19 : Enable or disable interrupt for CH[6].LIMITL event */
9449 #define SAADC_INTEN_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */
9450 #define SAADC_INTEN_CH6LIMITL_Msk (0x1UL << SAADC_INTEN_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */
9451 #define SAADC_INTEN_CH6LIMITL_Disabled (0UL) /*!< Disable */
9452 #define SAADC_INTEN_CH6LIMITL_Enabled (1UL) /*!< Enable */
9453 
9454 /* Bit 18 : Enable or disable interrupt for CH[6].LIMITH event */
9455 #define SAADC_INTEN_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */
9456 #define SAADC_INTEN_CH6LIMITH_Msk (0x1UL << SAADC_INTEN_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */
9457 #define SAADC_INTEN_CH6LIMITH_Disabled (0UL) /*!< Disable */
9458 #define SAADC_INTEN_CH6LIMITH_Enabled (1UL) /*!< Enable */
9459 
9460 /* Bit 17 : Enable or disable interrupt for CH[5].LIMITL event */
9461 #define SAADC_INTEN_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */
9462 #define SAADC_INTEN_CH5LIMITL_Msk (0x1UL << SAADC_INTEN_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */
9463 #define SAADC_INTEN_CH5LIMITL_Disabled (0UL) /*!< Disable */
9464 #define SAADC_INTEN_CH5LIMITL_Enabled (1UL) /*!< Enable */
9465 
9466 /* Bit 16 : Enable or disable interrupt for CH[5].LIMITH event */
9467 #define SAADC_INTEN_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */
9468 #define SAADC_INTEN_CH5LIMITH_Msk (0x1UL << SAADC_INTEN_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */
9469 #define SAADC_INTEN_CH5LIMITH_Disabled (0UL) /*!< Disable */
9470 #define SAADC_INTEN_CH5LIMITH_Enabled (1UL) /*!< Enable */
9471 
9472 /* Bit 15 : Enable or disable interrupt for CH[4].LIMITL event */
9473 #define SAADC_INTEN_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */
9474 #define SAADC_INTEN_CH4LIMITL_Msk (0x1UL << SAADC_INTEN_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */
9475 #define SAADC_INTEN_CH4LIMITL_Disabled (0UL) /*!< Disable */
9476 #define SAADC_INTEN_CH4LIMITL_Enabled (1UL) /*!< Enable */
9477 
9478 /* Bit 14 : Enable or disable interrupt for CH[4].LIMITH event */
9479 #define SAADC_INTEN_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */
9480 #define SAADC_INTEN_CH4LIMITH_Msk (0x1UL << SAADC_INTEN_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */
9481 #define SAADC_INTEN_CH4LIMITH_Disabled (0UL) /*!< Disable */
9482 #define SAADC_INTEN_CH4LIMITH_Enabled (1UL) /*!< Enable */
9483 
9484 /* Bit 13 : Enable or disable interrupt for CH[3].LIMITL event */
9485 #define SAADC_INTEN_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */
9486 #define SAADC_INTEN_CH3LIMITL_Msk (0x1UL << SAADC_INTEN_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */
9487 #define SAADC_INTEN_CH3LIMITL_Disabled (0UL) /*!< Disable */
9488 #define SAADC_INTEN_CH3LIMITL_Enabled (1UL) /*!< Enable */
9489 
9490 /* Bit 12 : Enable or disable interrupt for CH[3].LIMITH event */
9491 #define SAADC_INTEN_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */
9492 #define SAADC_INTEN_CH3LIMITH_Msk (0x1UL << SAADC_INTEN_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */
9493 #define SAADC_INTEN_CH3LIMITH_Disabled (0UL) /*!< Disable */
9494 #define SAADC_INTEN_CH3LIMITH_Enabled (1UL) /*!< Enable */
9495 
9496 /* Bit 11 : Enable or disable interrupt for CH[2].LIMITL event */
9497 #define SAADC_INTEN_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */
9498 #define SAADC_INTEN_CH2LIMITL_Msk (0x1UL << SAADC_INTEN_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */
9499 #define SAADC_INTEN_CH2LIMITL_Disabled (0UL) /*!< Disable */
9500 #define SAADC_INTEN_CH2LIMITL_Enabled (1UL) /*!< Enable */
9501 
9502 /* Bit 10 : Enable or disable interrupt for CH[2].LIMITH event */
9503 #define SAADC_INTEN_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */
9504 #define SAADC_INTEN_CH2LIMITH_Msk (0x1UL << SAADC_INTEN_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */
9505 #define SAADC_INTEN_CH2LIMITH_Disabled (0UL) /*!< Disable */
9506 #define SAADC_INTEN_CH2LIMITH_Enabled (1UL) /*!< Enable */
9507 
9508 /* Bit 9 : Enable or disable interrupt for CH[1].LIMITL event */
9509 #define SAADC_INTEN_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */
9510 #define SAADC_INTEN_CH1LIMITL_Msk (0x1UL << SAADC_INTEN_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */
9511 #define SAADC_INTEN_CH1LIMITL_Disabled (0UL) /*!< Disable */
9512 #define SAADC_INTEN_CH1LIMITL_Enabled (1UL) /*!< Enable */
9513 
9514 /* Bit 8 : Enable or disable interrupt for CH[1].LIMITH event */
9515 #define SAADC_INTEN_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */
9516 #define SAADC_INTEN_CH1LIMITH_Msk (0x1UL << SAADC_INTEN_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */
9517 #define SAADC_INTEN_CH1LIMITH_Disabled (0UL) /*!< Disable */
9518 #define SAADC_INTEN_CH1LIMITH_Enabled (1UL) /*!< Enable */
9519 
9520 /* Bit 7 : Enable or disable interrupt for CH[0].LIMITL event */
9521 #define SAADC_INTEN_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */
9522 #define SAADC_INTEN_CH0LIMITL_Msk (0x1UL << SAADC_INTEN_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */
9523 #define SAADC_INTEN_CH0LIMITL_Disabled (0UL) /*!< Disable */
9524 #define SAADC_INTEN_CH0LIMITL_Enabled (1UL) /*!< Enable */
9525 
9526 /* Bit 6 : Enable or disable interrupt for CH[0].LIMITH event */
9527 #define SAADC_INTEN_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */
9528 #define SAADC_INTEN_CH0LIMITH_Msk (0x1UL << SAADC_INTEN_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */
9529 #define SAADC_INTEN_CH0LIMITH_Disabled (0UL) /*!< Disable */
9530 #define SAADC_INTEN_CH0LIMITH_Enabled (1UL) /*!< Enable */
9531 
9532 /* Bit 5 : Enable or disable interrupt for STOPPED event */
9533 #define SAADC_INTEN_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */
9534 #define SAADC_INTEN_STOPPED_Msk (0x1UL << SAADC_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
9535 #define SAADC_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
9536 #define SAADC_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
9537 
9538 /* Bit 4 : Enable or disable interrupt for CALIBRATEDONE event */
9539 #define SAADC_INTEN_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */
9540 #define SAADC_INTEN_CALIBRATEDONE_Msk (0x1UL << SAADC_INTEN_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */
9541 #define SAADC_INTEN_CALIBRATEDONE_Disabled (0UL) /*!< Disable */
9542 #define SAADC_INTEN_CALIBRATEDONE_Enabled (1UL) /*!< Enable */
9543 
9544 /* Bit 3 : Enable or disable interrupt for RESULTDONE event */
9545 #define SAADC_INTEN_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */
9546 #define SAADC_INTEN_RESULTDONE_Msk (0x1UL << SAADC_INTEN_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */
9547 #define SAADC_INTEN_RESULTDONE_Disabled (0UL) /*!< Disable */
9548 #define SAADC_INTEN_RESULTDONE_Enabled (1UL) /*!< Enable */
9549 
9550 /* Bit 2 : Enable or disable interrupt for DONE event */
9551 #define SAADC_INTEN_DONE_Pos (2UL) /*!< Position of DONE field. */
9552 #define SAADC_INTEN_DONE_Msk (0x1UL << SAADC_INTEN_DONE_Pos) /*!< Bit mask of DONE field. */
9553 #define SAADC_INTEN_DONE_Disabled (0UL) /*!< Disable */
9554 #define SAADC_INTEN_DONE_Enabled (1UL) /*!< Enable */
9555 
9556 /* Bit 1 : Enable or disable interrupt for END event */
9557 #define SAADC_INTEN_END_Pos (1UL) /*!< Position of END field. */
9558 #define SAADC_INTEN_END_Msk (0x1UL << SAADC_INTEN_END_Pos) /*!< Bit mask of END field. */
9559 #define SAADC_INTEN_END_Disabled (0UL) /*!< Disable */
9560 #define SAADC_INTEN_END_Enabled (1UL) /*!< Enable */
9561 
9562 /* Bit 0 : Enable or disable interrupt for STARTED event */
9563 #define SAADC_INTEN_STARTED_Pos (0UL) /*!< Position of STARTED field. */
9564 #define SAADC_INTEN_STARTED_Msk (0x1UL << SAADC_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */
9565 #define SAADC_INTEN_STARTED_Disabled (0UL) /*!< Disable */
9566 #define SAADC_INTEN_STARTED_Enabled (1UL) /*!< Enable */
9567 
9568 /* Register: SAADC_INTENSET */
9569 /* Description: Enable interrupt */
9570 
9571 /* Bit 21 : Write '1' to Enable interrupt for CH[7].LIMITL event */
9572 #define SAADC_INTENSET_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */
9573 #define SAADC_INTENSET_CH7LIMITL_Msk (0x1UL << SAADC_INTENSET_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */
9574 #define SAADC_INTENSET_CH7LIMITL_Disabled (0UL) /*!< Read: Disabled */
9575 #define SAADC_INTENSET_CH7LIMITL_Enabled (1UL) /*!< Read: Enabled */
9576 #define SAADC_INTENSET_CH7LIMITL_Set (1UL) /*!< Enable */
9577 
9578 /* Bit 20 : Write '1' to Enable interrupt for CH[7].LIMITH event */
9579 #define SAADC_INTENSET_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */
9580 #define SAADC_INTENSET_CH7LIMITH_Msk (0x1UL << SAADC_INTENSET_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */
9581 #define SAADC_INTENSET_CH7LIMITH_Disabled (0UL) /*!< Read: Disabled */
9582 #define SAADC_INTENSET_CH7LIMITH_Enabled (1UL) /*!< Read: Enabled */
9583 #define SAADC_INTENSET_CH7LIMITH_Set (1UL) /*!< Enable */
9584 
9585 /* Bit 19 : Write '1' to Enable interrupt for CH[6].LIMITL event */
9586 #define SAADC_INTENSET_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */
9587 #define SAADC_INTENSET_CH6LIMITL_Msk (0x1UL << SAADC_INTENSET_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */
9588 #define SAADC_INTENSET_CH6LIMITL_Disabled (0UL) /*!< Read: Disabled */
9589 #define SAADC_INTENSET_CH6LIMITL_Enabled (1UL) /*!< Read: Enabled */
9590 #define SAADC_INTENSET_CH6LIMITL_Set (1UL) /*!< Enable */
9591 
9592 /* Bit 18 : Write '1' to Enable interrupt for CH[6].LIMITH event */
9593 #define SAADC_INTENSET_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */
9594 #define SAADC_INTENSET_CH6LIMITH_Msk (0x1UL << SAADC_INTENSET_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */
9595 #define SAADC_INTENSET_CH6LIMITH_Disabled (0UL) /*!< Read: Disabled */
9596 #define SAADC_INTENSET_CH6LIMITH_Enabled (1UL) /*!< Read: Enabled */
9597 #define SAADC_INTENSET_CH6LIMITH_Set (1UL) /*!< Enable */
9598 
9599 /* Bit 17 : Write '1' to Enable interrupt for CH[5].LIMITL event */
9600 #define SAADC_INTENSET_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */
9601 #define SAADC_INTENSET_CH5LIMITL_Msk (0x1UL << SAADC_INTENSET_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */
9602 #define SAADC_INTENSET_CH5LIMITL_Disabled (0UL) /*!< Read: Disabled */
9603 #define SAADC_INTENSET_CH5LIMITL_Enabled (1UL) /*!< Read: Enabled */
9604 #define SAADC_INTENSET_CH5LIMITL_Set (1UL) /*!< Enable */
9605 
9606 /* Bit 16 : Write '1' to Enable interrupt for CH[5].LIMITH event */
9607 #define SAADC_INTENSET_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */
9608 #define SAADC_INTENSET_CH5LIMITH_Msk (0x1UL << SAADC_INTENSET_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */
9609 #define SAADC_INTENSET_CH5LIMITH_Disabled (0UL) /*!< Read: Disabled */
9610 #define SAADC_INTENSET_CH5LIMITH_Enabled (1UL) /*!< Read: Enabled */
9611 #define SAADC_INTENSET_CH5LIMITH_Set (1UL) /*!< Enable */
9612 
9613 /* Bit 15 : Write '1' to Enable interrupt for CH[4].LIMITL event */
9614 #define SAADC_INTENSET_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */
9615 #define SAADC_INTENSET_CH4LIMITL_Msk (0x1UL << SAADC_INTENSET_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */
9616 #define SAADC_INTENSET_CH4LIMITL_Disabled (0UL) /*!< Read: Disabled */
9617 #define SAADC_INTENSET_CH4LIMITL_Enabled (1UL) /*!< Read: Enabled */
9618 #define SAADC_INTENSET_CH4LIMITL_Set (1UL) /*!< Enable */
9619 
9620 /* Bit 14 : Write '1' to Enable interrupt for CH[4].LIMITH event */
9621 #define SAADC_INTENSET_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */
9622 #define SAADC_INTENSET_CH4LIMITH_Msk (0x1UL << SAADC_INTENSET_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */
9623 #define SAADC_INTENSET_CH4LIMITH_Disabled (0UL) /*!< Read: Disabled */
9624 #define SAADC_INTENSET_CH4LIMITH_Enabled (1UL) /*!< Read: Enabled */
9625 #define SAADC_INTENSET_CH4LIMITH_Set (1UL) /*!< Enable */
9626 
9627 /* Bit 13 : Write '1' to Enable interrupt for CH[3].LIMITL event */
9628 #define SAADC_INTENSET_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */
9629 #define SAADC_INTENSET_CH3LIMITL_Msk (0x1UL << SAADC_INTENSET_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */
9630 #define SAADC_INTENSET_CH3LIMITL_Disabled (0UL) /*!< Read: Disabled */
9631 #define SAADC_INTENSET_CH3LIMITL_Enabled (1UL) /*!< Read: Enabled */
9632 #define SAADC_INTENSET_CH3LIMITL_Set (1UL) /*!< Enable */
9633 
9634 /* Bit 12 : Write '1' to Enable interrupt for CH[3].LIMITH event */
9635 #define SAADC_INTENSET_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */
9636 #define SAADC_INTENSET_CH3LIMITH_Msk (0x1UL << SAADC_INTENSET_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */
9637 #define SAADC_INTENSET_CH3LIMITH_Disabled (0UL) /*!< Read: Disabled */
9638 #define SAADC_INTENSET_CH3LIMITH_Enabled (1UL) /*!< Read: Enabled */
9639 #define SAADC_INTENSET_CH3LIMITH_Set (1UL) /*!< Enable */
9640 
9641 /* Bit 11 : Write '1' to Enable interrupt for CH[2].LIMITL event */
9642 #define SAADC_INTENSET_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */
9643 #define SAADC_INTENSET_CH2LIMITL_Msk (0x1UL << SAADC_INTENSET_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */
9644 #define SAADC_INTENSET_CH2LIMITL_Disabled (0UL) /*!< Read: Disabled */
9645 #define SAADC_INTENSET_CH2LIMITL_Enabled (1UL) /*!< Read: Enabled */
9646 #define SAADC_INTENSET_CH2LIMITL_Set (1UL) /*!< Enable */
9647 
9648 /* Bit 10 : Write '1' to Enable interrupt for CH[2].LIMITH event */
9649 #define SAADC_INTENSET_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */
9650 #define SAADC_INTENSET_CH2LIMITH_Msk (0x1UL << SAADC_INTENSET_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */
9651 #define SAADC_INTENSET_CH2LIMITH_Disabled (0UL) /*!< Read: Disabled */
9652 #define SAADC_INTENSET_CH2LIMITH_Enabled (1UL) /*!< Read: Enabled */
9653 #define SAADC_INTENSET_CH2LIMITH_Set (1UL) /*!< Enable */
9654 
9655 /* Bit 9 : Write '1' to Enable interrupt for CH[1].LIMITL event */
9656 #define SAADC_INTENSET_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */
9657 #define SAADC_INTENSET_CH1LIMITL_Msk (0x1UL << SAADC_INTENSET_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */
9658 #define SAADC_INTENSET_CH1LIMITL_Disabled (0UL) /*!< Read: Disabled */
9659 #define SAADC_INTENSET_CH1LIMITL_Enabled (1UL) /*!< Read: Enabled */
9660 #define SAADC_INTENSET_CH1LIMITL_Set (1UL) /*!< Enable */
9661 
9662 /* Bit 8 : Write '1' to Enable interrupt for CH[1].LIMITH event */
9663 #define SAADC_INTENSET_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */
9664 #define SAADC_INTENSET_CH1LIMITH_Msk (0x1UL << SAADC_INTENSET_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */
9665 #define SAADC_INTENSET_CH1LIMITH_Disabled (0UL) /*!< Read: Disabled */
9666 #define SAADC_INTENSET_CH1LIMITH_Enabled (1UL) /*!< Read: Enabled */
9667 #define SAADC_INTENSET_CH1LIMITH_Set (1UL) /*!< Enable */
9668 
9669 /* Bit 7 : Write '1' to Enable interrupt for CH[0].LIMITL event */
9670 #define SAADC_INTENSET_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */
9671 #define SAADC_INTENSET_CH0LIMITL_Msk (0x1UL << SAADC_INTENSET_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */
9672 #define SAADC_INTENSET_CH0LIMITL_Disabled (0UL) /*!< Read: Disabled */
9673 #define SAADC_INTENSET_CH0LIMITL_Enabled (1UL) /*!< Read: Enabled */
9674 #define SAADC_INTENSET_CH0LIMITL_Set (1UL) /*!< Enable */
9675 
9676 /* Bit 6 : Write '1' to Enable interrupt for CH[0].LIMITH event */
9677 #define SAADC_INTENSET_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */
9678 #define SAADC_INTENSET_CH0LIMITH_Msk (0x1UL << SAADC_INTENSET_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */
9679 #define SAADC_INTENSET_CH0LIMITH_Disabled (0UL) /*!< Read: Disabled */
9680 #define SAADC_INTENSET_CH0LIMITH_Enabled (1UL) /*!< Read: Enabled */
9681 #define SAADC_INTENSET_CH0LIMITH_Set (1UL) /*!< Enable */
9682 
9683 /* Bit 5 : Write '1' to Enable interrupt for STOPPED event */
9684 #define SAADC_INTENSET_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */
9685 #define SAADC_INTENSET_STOPPED_Msk (0x1UL << SAADC_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
9686 #define SAADC_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
9687 #define SAADC_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
9688 #define SAADC_INTENSET_STOPPED_Set (1UL) /*!< Enable */
9689 
9690 /* Bit 4 : Write '1' to Enable interrupt for CALIBRATEDONE event */
9691 #define SAADC_INTENSET_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */
9692 #define SAADC_INTENSET_CALIBRATEDONE_Msk (0x1UL << SAADC_INTENSET_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */
9693 #define SAADC_INTENSET_CALIBRATEDONE_Disabled (0UL) /*!< Read: Disabled */
9694 #define SAADC_INTENSET_CALIBRATEDONE_Enabled (1UL) /*!< Read: Enabled */
9695 #define SAADC_INTENSET_CALIBRATEDONE_Set (1UL) /*!< Enable */
9696 
9697 /* Bit 3 : Write '1' to Enable interrupt for RESULTDONE event */
9698 #define SAADC_INTENSET_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */
9699 #define SAADC_INTENSET_RESULTDONE_Msk (0x1UL << SAADC_INTENSET_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */
9700 #define SAADC_INTENSET_RESULTDONE_Disabled (0UL) /*!< Read: Disabled */
9701 #define SAADC_INTENSET_RESULTDONE_Enabled (1UL) /*!< Read: Enabled */
9702 #define SAADC_INTENSET_RESULTDONE_Set (1UL) /*!< Enable */
9703 
9704 /* Bit 2 : Write '1' to Enable interrupt for DONE event */
9705 #define SAADC_INTENSET_DONE_Pos (2UL) /*!< Position of DONE field. */
9706 #define SAADC_INTENSET_DONE_Msk (0x1UL << SAADC_INTENSET_DONE_Pos) /*!< Bit mask of DONE field. */
9707 #define SAADC_INTENSET_DONE_Disabled (0UL) /*!< Read: Disabled */
9708 #define SAADC_INTENSET_DONE_Enabled (1UL) /*!< Read: Enabled */
9709 #define SAADC_INTENSET_DONE_Set (1UL) /*!< Enable */
9710 
9711 /* Bit 1 : Write '1' to Enable interrupt for END event */
9712 #define SAADC_INTENSET_END_Pos (1UL) /*!< Position of END field. */
9713 #define SAADC_INTENSET_END_Msk (0x1UL << SAADC_INTENSET_END_Pos) /*!< Bit mask of END field. */
9714 #define SAADC_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
9715 #define SAADC_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
9716 #define SAADC_INTENSET_END_Set (1UL) /*!< Enable */
9717 
9718 /* Bit 0 : Write '1' to Enable interrupt for STARTED event */
9719 #define SAADC_INTENSET_STARTED_Pos (0UL) /*!< Position of STARTED field. */
9720 #define SAADC_INTENSET_STARTED_Msk (0x1UL << SAADC_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */
9721 #define SAADC_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */
9722 #define SAADC_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */
9723 #define SAADC_INTENSET_STARTED_Set (1UL) /*!< Enable */
9724 
9725 /* Register: SAADC_INTENCLR */
9726 /* Description: Disable interrupt */
9727 
9728 /* Bit 21 : Write '1' to Disable interrupt for CH[7].LIMITL event */
9729 #define SAADC_INTENCLR_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */
9730 #define SAADC_INTENCLR_CH7LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */
9731 #define SAADC_INTENCLR_CH7LIMITL_Disabled (0UL) /*!< Read: Disabled */
9732 #define SAADC_INTENCLR_CH7LIMITL_Enabled (1UL) /*!< Read: Enabled */
9733 #define SAADC_INTENCLR_CH7LIMITL_Clear (1UL) /*!< Disable */
9734 
9735 /* Bit 20 : Write '1' to Disable interrupt for CH[7].LIMITH event */
9736 #define SAADC_INTENCLR_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */
9737 #define SAADC_INTENCLR_CH7LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */
9738 #define SAADC_INTENCLR_CH7LIMITH_Disabled (0UL) /*!< Read: Disabled */
9739 #define SAADC_INTENCLR_CH7LIMITH_Enabled (1UL) /*!< Read: Enabled */
9740 #define SAADC_INTENCLR_CH7LIMITH_Clear (1UL) /*!< Disable */
9741 
9742 /* Bit 19 : Write '1' to Disable interrupt for CH[6].LIMITL event */
9743 #define SAADC_INTENCLR_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */
9744 #define SAADC_INTENCLR_CH6LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */
9745 #define SAADC_INTENCLR_CH6LIMITL_Disabled (0UL) /*!< Read: Disabled */
9746 #define SAADC_INTENCLR_CH6LIMITL_Enabled (1UL) /*!< Read: Enabled */
9747 #define SAADC_INTENCLR_CH6LIMITL_Clear (1UL) /*!< Disable */
9748 
9749 /* Bit 18 : Write '1' to Disable interrupt for CH[6].LIMITH event */
9750 #define SAADC_INTENCLR_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */
9751 #define SAADC_INTENCLR_CH6LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */
9752 #define SAADC_INTENCLR_CH6LIMITH_Disabled (0UL) /*!< Read: Disabled */
9753 #define SAADC_INTENCLR_CH6LIMITH_Enabled (1UL) /*!< Read: Enabled */
9754 #define SAADC_INTENCLR_CH6LIMITH_Clear (1UL) /*!< Disable */
9755 
9756 /* Bit 17 : Write '1' to Disable interrupt for CH[5].LIMITL event */
9757 #define SAADC_INTENCLR_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */
9758 #define SAADC_INTENCLR_CH5LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */
9759 #define SAADC_INTENCLR_CH5LIMITL_Disabled (0UL) /*!< Read: Disabled */
9760 #define SAADC_INTENCLR_CH5LIMITL_Enabled (1UL) /*!< Read: Enabled */
9761 #define SAADC_INTENCLR_CH5LIMITL_Clear (1UL) /*!< Disable */
9762 
9763 /* Bit 16 : Write '1' to Disable interrupt for CH[5].LIMITH event */
9764 #define SAADC_INTENCLR_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */
9765 #define SAADC_INTENCLR_CH5LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */
9766 #define SAADC_INTENCLR_CH5LIMITH_Disabled (0UL) /*!< Read: Disabled */
9767 #define SAADC_INTENCLR_CH5LIMITH_Enabled (1UL) /*!< Read: Enabled */
9768 #define SAADC_INTENCLR_CH5LIMITH_Clear (1UL) /*!< Disable */
9769 
9770 /* Bit 15 : Write '1' to Disable interrupt for CH[4].LIMITL event */
9771 #define SAADC_INTENCLR_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */
9772 #define SAADC_INTENCLR_CH4LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */
9773 #define SAADC_INTENCLR_CH4LIMITL_Disabled (0UL) /*!< Read: Disabled */
9774 #define SAADC_INTENCLR_CH4LIMITL_Enabled (1UL) /*!< Read: Enabled */
9775 #define SAADC_INTENCLR_CH4LIMITL_Clear (1UL) /*!< Disable */
9776 
9777 /* Bit 14 : Write '1' to Disable interrupt for CH[4].LIMITH event */
9778 #define SAADC_INTENCLR_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */
9779 #define SAADC_INTENCLR_CH4LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */
9780 #define SAADC_INTENCLR_CH4LIMITH_Disabled (0UL) /*!< Read: Disabled */
9781 #define SAADC_INTENCLR_CH4LIMITH_Enabled (1UL) /*!< Read: Enabled */
9782 #define SAADC_INTENCLR_CH4LIMITH_Clear (1UL) /*!< Disable */
9783 
9784 /* Bit 13 : Write '1' to Disable interrupt for CH[3].LIMITL event */
9785 #define SAADC_INTENCLR_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */
9786 #define SAADC_INTENCLR_CH3LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */
9787 #define SAADC_INTENCLR_CH3LIMITL_Disabled (0UL) /*!< Read: Disabled */
9788 #define SAADC_INTENCLR_CH3LIMITL_Enabled (1UL) /*!< Read: Enabled */
9789 #define SAADC_INTENCLR_CH3LIMITL_Clear (1UL) /*!< Disable */
9790 
9791 /* Bit 12 : Write '1' to Disable interrupt for CH[3].LIMITH event */
9792 #define SAADC_INTENCLR_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */
9793 #define SAADC_INTENCLR_CH3LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */
9794 #define SAADC_INTENCLR_CH3LIMITH_Disabled (0UL) /*!< Read: Disabled */
9795 #define SAADC_INTENCLR_CH3LIMITH_Enabled (1UL) /*!< Read: Enabled */
9796 #define SAADC_INTENCLR_CH3LIMITH_Clear (1UL) /*!< Disable */
9797 
9798 /* Bit 11 : Write '1' to Disable interrupt for CH[2].LIMITL event */
9799 #define SAADC_INTENCLR_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */
9800 #define SAADC_INTENCLR_CH2LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */
9801 #define SAADC_INTENCLR_CH2LIMITL_Disabled (0UL) /*!< Read: Disabled */
9802 #define SAADC_INTENCLR_CH2LIMITL_Enabled (1UL) /*!< Read: Enabled */
9803 #define SAADC_INTENCLR_CH2LIMITL_Clear (1UL) /*!< Disable */
9804 
9805 /* Bit 10 : Write '1' to Disable interrupt for CH[2].LIMITH event */
9806 #define SAADC_INTENCLR_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */
9807 #define SAADC_INTENCLR_CH2LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */
9808 #define SAADC_INTENCLR_CH2LIMITH_Disabled (0UL) /*!< Read: Disabled */
9809 #define SAADC_INTENCLR_CH2LIMITH_Enabled (1UL) /*!< Read: Enabled */
9810 #define SAADC_INTENCLR_CH2LIMITH_Clear (1UL) /*!< Disable */
9811 
9812 /* Bit 9 : Write '1' to Disable interrupt for CH[1].LIMITL event */
9813 #define SAADC_INTENCLR_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */
9814 #define SAADC_INTENCLR_CH1LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */
9815 #define SAADC_INTENCLR_CH1LIMITL_Disabled (0UL) /*!< Read: Disabled */
9816 #define SAADC_INTENCLR_CH1LIMITL_Enabled (1UL) /*!< Read: Enabled */
9817 #define SAADC_INTENCLR_CH1LIMITL_Clear (1UL) /*!< Disable */
9818 
9819 /* Bit 8 : Write '1' to Disable interrupt for CH[1].LIMITH event */
9820 #define SAADC_INTENCLR_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */
9821 #define SAADC_INTENCLR_CH1LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */
9822 #define SAADC_INTENCLR_CH1LIMITH_Disabled (0UL) /*!< Read: Disabled */
9823 #define SAADC_INTENCLR_CH1LIMITH_Enabled (1UL) /*!< Read: Enabled */
9824 #define SAADC_INTENCLR_CH1LIMITH_Clear (1UL) /*!< Disable */
9825 
9826 /* Bit 7 : Write '1' to Disable interrupt for CH[0].LIMITL event */
9827 #define SAADC_INTENCLR_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */
9828 #define SAADC_INTENCLR_CH0LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */
9829 #define SAADC_INTENCLR_CH0LIMITL_Disabled (0UL) /*!< Read: Disabled */
9830 #define SAADC_INTENCLR_CH0LIMITL_Enabled (1UL) /*!< Read: Enabled */
9831 #define SAADC_INTENCLR_CH0LIMITL_Clear (1UL) /*!< Disable */
9832 
9833 /* Bit 6 : Write '1' to Disable interrupt for CH[0].LIMITH event */
9834 #define SAADC_INTENCLR_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */
9835 #define SAADC_INTENCLR_CH0LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */
9836 #define SAADC_INTENCLR_CH0LIMITH_Disabled (0UL) /*!< Read: Disabled */
9837 #define SAADC_INTENCLR_CH0LIMITH_Enabled (1UL) /*!< Read: Enabled */
9838 #define SAADC_INTENCLR_CH0LIMITH_Clear (1UL) /*!< Disable */
9839 
9840 /* Bit 5 : Write '1' to Disable interrupt for STOPPED event */
9841 #define SAADC_INTENCLR_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */
9842 #define SAADC_INTENCLR_STOPPED_Msk (0x1UL << SAADC_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
9843 #define SAADC_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
9844 #define SAADC_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
9845 #define SAADC_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
9846 
9847 /* Bit 4 : Write '1' to Disable interrupt for CALIBRATEDONE event */
9848 #define SAADC_INTENCLR_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */
9849 #define SAADC_INTENCLR_CALIBRATEDONE_Msk (0x1UL << SAADC_INTENCLR_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */
9850 #define SAADC_INTENCLR_CALIBRATEDONE_Disabled (0UL) /*!< Read: Disabled */
9851 #define SAADC_INTENCLR_CALIBRATEDONE_Enabled (1UL) /*!< Read: Enabled */
9852 #define SAADC_INTENCLR_CALIBRATEDONE_Clear (1UL) /*!< Disable */
9853 
9854 /* Bit 3 : Write '1' to Disable interrupt for RESULTDONE event */
9855 #define SAADC_INTENCLR_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */
9856 #define SAADC_INTENCLR_RESULTDONE_Msk (0x1UL << SAADC_INTENCLR_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */
9857 #define SAADC_INTENCLR_RESULTDONE_Disabled (0UL) /*!< Read: Disabled */
9858 #define SAADC_INTENCLR_RESULTDONE_Enabled (1UL) /*!< Read: Enabled */
9859 #define SAADC_INTENCLR_RESULTDONE_Clear (1UL) /*!< Disable */
9860 
9861 /* Bit 2 : Write '1' to Disable interrupt for DONE event */
9862 #define SAADC_INTENCLR_DONE_Pos (2UL) /*!< Position of DONE field. */
9863 #define SAADC_INTENCLR_DONE_Msk (0x1UL << SAADC_INTENCLR_DONE_Pos) /*!< Bit mask of DONE field. */
9864 #define SAADC_INTENCLR_DONE_Disabled (0UL) /*!< Read: Disabled */
9865 #define SAADC_INTENCLR_DONE_Enabled (1UL) /*!< Read: Enabled */
9866 #define SAADC_INTENCLR_DONE_Clear (1UL) /*!< Disable */
9867 
9868 /* Bit 1 : Write '1' to Disable interrupt for END event */
9869 #define SAADC_INTENCLR_END_Pos (1UL) /*!< Position of END field. */
9870 #define SAADC_INTENCLR_END_Msk (0x1UL << SAADC_INTENCLR_END_Pos) /*!< Bit mask of END field. */
9871 #define SAADC_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
9872 #define SAADC_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
9873 #define SAADC_INTENCLR_END_Clear (1UL) /*!< Disable */
9874 
9875 /* Bit 0 : Write '1' to Disable interrupt for STARTED event */
9876 #define SAADC_INTENCLR_STARTED_Pos (0UL) /*!< Position of STARTED field. */
9877 #define SAADC_INTENCLR_STARTED_Msk (0x1UL << SAADC_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */
9878 #define SAADC_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */
9879 #define SAADC_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */
9880 #define SAADC_INTENCLR_STARTED_Clear (1UL) /*!< Disable */
9881 
9882 /* Register: SAADC_STATUS */
9883 /* Description: Status */
9884 
9885 /* Bit 0 : Status */
9886 #define SAADC_STATUS_STATUS_Pos (0UL) /*!< Position of STATUS field. */
9887 #define SAADC_STATUS_STATUS_Msk (0x1UL << SAADC_STATUS_STATUS_Pos) /*!< Bit mask of STATUS field. */
9888 #define SAADC_STATUS_STATUS_Ready (0UL) /*!< ADC is ready. No on-going conversion. */
9889 #define SAADC_STATUS_STATUS_Busy (1UL) /*!< ADC is busy. Conversion in progress. */
9890 
9891 /* Register: SAADC_ENABLE */
9892 /* Description: Enable or disable ADC */
9893 
9894 /* Bit 0 : Enable or disable ADC */
9895 #define SAADC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
9896 #define SAADC_ENABLE_ENABLE_Msk (0x1UL << SAADC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
9897 #define SAADC_ENABLE_ENABLE_Disabled (0UL) /*!< Disable ADC */
9898 #define SAADC_ENABLE_ENABLE_Enabled (1UL) /*!< Enable ADC */
9899 
9900 /* Register: SAADC_CH_PSELP */
9901 /* Description: Description cluster[0]:  Input positive pin selection for CH[0] */
9902 
9903 /* Bits 4..0 : Analog positive input channel */
9904 #define SAADC_CH_PSELP_PSELP_Pos (0UL) /*!< Position of PSELP field. */
9905 #define SAADC_CH_PSELP_PSELP_Msk (0x1FUL << SAADC_CH_PSELP_PSELP_Pos) /*!< Bit mask of PSELP field. */
9906 #define SAADC_CH_PSELP_PSELP_NC (0UL) /*!< Not connected */
9907 #define SAADC_CH_PSELP_PSELP_AnalogInput0 (1UL) /*!< AIN0 */
9908 #define SAADC_CH_PSELP_PSELP_AnalogInput1 (2UL) /*!< AIN1 */
9909 #define SAADC_CH_PSELP_PSELP_AnalogInput2 (3UL) /*!< AIN2 */
9910 #define SAADC_CH_PSELP_PSELP_AnalogInput3 (4UL) /*!< AIN3 */
9911 #define SAADC_CH_PSELP_PSELP_AnalogInput4 (5UL) /*!< AIN4 */
9912 #define SAADC_CH_PSELP_PSELP_AnalogInput5 (6UL) /*!< AIN5 */
9913 #define SAADC_CH_PSELP_PSELP_AnalogInput6 (7UL) /*!< AIN6 */
9914 #define SAADC_CH_PSELP_PSELP_AnalogInput7 (8UL) /*!< AIN7 */
9915 #define SAADC_CH_PSELP_PSELP_VDD (9UL) /*!< VDD */
9916 
9917 /* Register: SAADC_CH_PSELN */
9918 /* Description: Description cluster[0]:  Input negative pin selection for CH[0] */
9919 
9920 /* Bits 4..0 : Analog negative input, enables differential channel */
9921 #define SAADC_CH_PSELN_PSELN_Pos (0UL) /*!< Position of PSELN field. */
9922 #define SAADC_CH_PSELN_PSELN_Msk (0x1FUL << SAADC_CH_PSELN_PSELN_Pos) /*!< Bit mask of PSELN field. */
9923 #define SAADC_CH_PSELN_PSELN_NC (0UL) /*!< Not connected */
9924 #define SAADC_CH_PSELN_PSELN_AnalogInput0 (1UL) /*!< AIN0 */
9925 #define SAADC_CH_PSELN_PSELN_AnalogInput1 (2UL) /*!< AIN1 */
9926 #define SAADC_CH_PSELN_PSELN_AnalogInput2 (3UL) /*!< AIN2 */
9927 #define SAADC_CH_PSELN_PSELN_AnalogInput3 (4UL) /*!< AIN3 */
9928 #define SAADC_CH_PSELN_PSELN_AnalogInput4 (5UL) /*!< AIN4 */
9929 #define SAADC_CH_PSELN_PSELN_AnalogInput5 (6UL) /*!< AIN5 */
9930 #define SAADC_CH_PSELN_PSELN_AnalogInput6 (7UL) /*!< AIN6 */
9931 #define SAADC_CH_PSELN_PSELN_AnalogInput7 (8UL) /*!< AIN7 */
9932 #define SAADC_CH_PSELN_PSELN_VDD (9UL) /*!< VDD */
9933 
9934 /* Register: SAADC_CH_CONFIG */
9935 /* Description: Description cluster[0]:  Input configuration for CH[0] */
9936 
9937 /* Bit 24 : Enable burst mode */
9938 #define SAADC_CH_CONFIG_BURST_Pos (24UL) /*!< Position of BURST field. */
9939 #define SAADC_CH_CONFIG_BURST_Msk (0x1UL << SAADC_CH_CONFIG_BURST_Pos) /*!< Bit mask of BURST field. */
9940 #define SAADC_CH_CONFIG_BURST_Disabled (0UL) /*!< Burst mode is disabled (normal operation) */
9941 #define SAADC_CH_CONFIG_BURST_Enabled (1UL) /*!< Burst mode is enabled. SAADC takes 2^OVERSAMPLE number of samples as fast as it can, and sends the average to Data RAM. */
9942 
9943 /* Bit 20 : Enable differential mode */
9944 #define SAADC_CH_CONFIG_MODE_Pos (20UL) /*!< Position of MODE field. */
9945 #define SAADC_CH_CONFIG_MODE_Msk (0x1UL << SAADC_CH_CONFIG_MODE_Pos) /*!< Bit mask of MODE field. */
9946 #define SAADC_CH_CONFIG_MODE_SE (0UL) /*!< Single ended, PSELN will be ignored, negative input to ADC shorted to GND */
9947 #define SAADC_CH_CONFIG_MODE_Diff (1UL) /*!< Differential */
9948 
9949 /* Bits 18..16 : Acquisition time, the time the ADC uses to sample the input voltage */
9950 #define SAADC_CH_CONFIG_TACQ_Pos (16UL) /*!< Position of TACQ field. */
9951 #define SAADC_CH_CONFIG_TACQ_Msk (0x7UL << SAADC_CH_CONFIG_TACQ_Pos) /*!< Bit mask of TACQ field. */
9952 #define SAADC_CH_CONFIG_TACQ_3us (0UL) /*!< 3 us */
9953 #define SAADC_CH_CONFIG_TACQ_5us (1UL) /*!< 5 us */
9954 #define SAADC_CH_CONFIG_TACQ_10us (2UL) /*!< 10 us */
9955 #define SAADC_CH_CONFIG_TACQ_15us (3UL) /*!< 15 us */
9956 #define SAADC_CH_CONFIG_TACQ_20us (4UL) /*!< 20 us */
9957 #define SAADC_CH_CONFIG_TACQ_40us (5UL) /*!< 40 us */
9958 
9959 /* Bit 12 : Reference control */
9960 #define SAADC_CH_CONFIG_REFSEL_Pos (12UL) /*!< Position of REFSEL field. */
9961 #define SAADC_CH_CONFIG_REFSEL_Msk (0x1UL << SAADC_CH_CONFIG_REFSEL_Pos) /*!< Bit mask of REFSEL field. */
9962 #define SAADC_CH_CONFIG_REFSEL_Internal (0UL) /*!< Internal reference (0.6 V) */
9963 #define SAADC_CH_CONFIG_REFSEL_VDD1_4 (1UL) /*!< VDD/4 as reference */
9964 
9965 /* Bits 10..8 : Gain control */
9966 #define SAADC_CH_CONFIG_GAIN_Pos (8UL) /*!< Position of GAIN field. */
9967 #define SAADC_CH_CONFIG_GAIN_Msk (0x7UL << SAADC_CH_CONFIG_GAIN_Pos) /*!< Bit mask of GAIN field. */
9968 #define SAADC_CH_CONFIG_GAIN_Gain1_6 (0UL) /*!< 1/6 */
9969 #define SAADC_CH_CONFIG_GAIN_Gain1_5 (1UL) /*!< 1/5 */
9970 #define SAADC_CH_CONFIG_GAIN_Gain1_4 (2UL) /*!< 1/4 */
9971 #define SAADC_CH_CONFIG_GAIN_Gain1_3 (3UL) /*!< 1/3 */
9972 #define SAADC_CH_CONFIG_GAIN_Gain1_2 (4UL) /*!< 1/2 */
9973 #define SAADC_CH_CONFIG_GAIN_Gain1 (5UL) /*!< 1 */
9974 #define SAADC_CH_CONFIG_GAIN_Gain2 (6UL) /*!< 2 */
9975 #define SAADC_CH_CONFIG_GAIN_Gain4 (7UL) /*!< 4 */
9976 
9977 /* Bits 5..4 : Negative channel resistor control */
9978 #define SAADC_CH_CONFIG_RESN_Pos (4UL) /*!< Position of RESN field. */
9979 #define SAADC_CH_CONFIG_RESN_Msk (0x3UL << SAADC_CH_CONFIG_RESN_Pos) /*!< Bit mask of RESN field. */
9980 #define SAADC_CH_CONFIG_RESN_Bypass (0UL) /*!< Bypass resistor ladder */
9981 #define SAADC_CH_CONFIG_RESN_Pulldown (1UL) /*!< Pull-down to GND */
9982 #define SAADC_CH_CONFIG_RESN_Pullup (2UL) /*!< Pull-up to VDD */
9983 #define SAADC_CH_CONFIG_RESN_VDD1_2 (3UL) /*!< Set input at VDD/2 */
9984 
9985 /* Bits 1..0 : Positive channel resistor control */
9986 #define SAADC_CH_CONFIG_RESP_Pos (0UL) /*!< Position of RESP field. */
9987 #define SAADC_CH_CONFIG_RESP_Msk (0x3UL << SAADC_CH_CONFIG_RESP_Pos) /*!< Bit mask of RESP field. */
9988 #define SAADC_CH_CONFIG_RESP_Bypass (0UL) /*!< Bypass resistor ladder */
9989 #define SAADC_CH_CONFIG_RESP_Pulldown (1UL) /*!< Pull-down to GND */
9990 #define SAADC_CH_CONFIG_RESP_Pullup (2UL) /*!< Pull-up to VDD */
9991 #define SAADC_CH_CONFIG_RESP_VDD1_2 (3UL) /*!< Set input at VDD/2 */
9992 
9993 /* Register: SAADC_CH_LIMIT */
9994 /* Description: Description cluster[0]:  High/low limits for event monitoring a channel */
9995 
9996 /* Bits 31..16 : High level limit */
9997 #define SAADC_CH_LIMIT_HIGH_Pos (16UL) /*!< Position of HIGH field. */
9998 #define SAADC_CH_LIMIT_HIGH_Msk (0xFFFFUL << SAADC_CH_LIMIT_HIGH_Pos) /*!< Bit mask of HIGH field. */
9999 
10000 /* Bits 15..0 : Low level limit */
10001 #define SAADC_CH_LIMIT_LOW_Pos (0UL) /*!< Position of LOW field. */
10002 #define SAADC_CH_LIMIT_LOW_Msk (0xFFFFUL << SAADC_CH_LIMIT_LOW_Pos) /*!< Bit mask of LOW field. */
10003 
10004 /* Register: SAADC_RESOLUTION */
10005 /* Description: Resolution configuration */
10006 
10007 /* Bits 2..0 : Set the resolution */
10008 #define SAADC_RESOLUTION_VAL_Pos (0UL) /*!< Position of VAL field. */
10009 #define SAADC_RESOLUTION_VAL_Msk (0x7UL << SAADC_RESOLUTION_VAL_Pos) /*!< Bit mask of VAL field. */
10010 #define SAADC_RESOLUTION_VAL_8bit (0UL) /*!< 8 bit */
10011 #define SAADC_RESOLUTION_VAL_10bit (1UL) /*!< 10 bit */
10012 #define SAADC_RESOLUTION_VAL_12bit (2UL) /*!< 12 bit */
10013 #define SAADC_RESOLUTION_VAL_14bit (3UL) /*!< 14 bit */
10014 
10015 /* Register: SAADC_OVERSAMPLE */
10016 /* Description: Oversampling configuration. OVERSAMPLE should not be combined with SCAN. The RESOLUTION is applied before averaging, thus for high OVERSAMPLE a higher RESOLUTION should be used. */
10017 
10018 /* Bits 3..0 : Oversample control */
10019 #define SAADC_OVERSAMPLE_OVERSAMPLE_Pos (0UL) /*!< Position of OVERSAMPLE field. */
10020 #define SAADC_OVERSAMPLE_OVERSAMPLE_Msk (0xFUL << SAADC_OVERSAMPLE_OVERSAMPLE_Pos) /*!< Bit mask of OVERSAMPLE field. */
10021 #define SAADC_OVERSAMPLE_OVERSAMPLE_Bypass (0UL) /*!< Bypass oversampling */
10022 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over2x (1UL) /*!< Oversample 2x */
10023 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over4x (2UL) /*!< Oversample 4x */
10024 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over8x (3UL) /*!< Oversample 8x */
10025 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over16x (4UL) /*!< Oversample 16x */
10026 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over32x (5UL) /*!< Oversample 32x */
10027 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over64x (6UL) /*!< Oversample 64x */
10028 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over128x (7UL) /*!< Oversample 128x */
10029 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over256x (8UL) /*!< Oversample 256x */
10030 
10031 /* Register: SAADC_SAMPLERATE */
10032 /* Description: Controls normal or continuous sample rate */
10033 
10034 /* Bit 12 : Select mode for sample rate control */
10035 #define SAADC_SAMPLERATE_MODE_Pos (12UL) /*!< Position of MODE field. */
10036 #define SAADC_SAMPLERATE_MODE_Msk (0x1UL << SAADC_SAMPLERATE_MODE_Pos) /*!< Bit mask of MODE field. */
10037 #define SAADC_SAMPLERATE_MODE_Task (0UL) /*!< Rate is controlled from SAMPLE task */
10038 #define SAADC_SAMPLERATE_MODE_Timers (1UL) /*!< Rate is controlled from local timer (use CC to control the rate) */
10039 
10040 /* Bits 10..0 : Capture and compare value. Sample rate is 16 MHz/CC */
10041 #define SAADC_SAMPLERATE_CC_Pos (0UL) /*!< Position of CC field. */
10042 #define SAADC_SAMPLERATE_CC_Msk (0x7FFUL << SAADC_SAMPLERATE_CC_Pos) /*!< Bit mask of CC field. */
10043 
10044 /* Register: SAADC_RESULT_PTR */
10045 /* Description: Data pointer */
10046 
10047 /* Bits 31..0 : Data pointer */
10048 #define SAADC_RESULT_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
10049 #define SAADC_RESULT_PTR_PTR_Msk (0xFFFFFFFFUL << SAADC_RESULT_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
10050 
10051 /* Register: SAADC_RESULT_MAXCNT */
10052 /* Description: Maximum number of buffer words to transfer */
10053 
10054 /* Bits 14..0 : Maximum number of buffer words to transfer */
10055 #define SAADC_RESULT_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
10056 #define SAADC_RESULT_MAXCNT_MAXCNT_Msk (0x7FFFUL << SAADC_RESULT_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
10057 
10058 /* Register: SAADC_RESULT_AMOUNT */
10059 /* Description: Number of buffer words transferred since last START */
10060 
10061 /* Bits 14..0 : Number of buffer words transferred since last START. This register can be read after an END or STOPPED event. */
10062 #define SAADC_RESULT_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
10063 #define SAADC_RESULT_AMOUNT_AMOUNT_Msk (0x7FFFUL << SAADC_RESULT_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
10064 
10065 
10066 /* Peripheral: SPI */
10067 /* Description: Serial Peripheral Interface 0 */
10068 
10069 /* Register: SPI_INTENSET */
10070 /* Description: Enable interrupt */
10071 
10072 /* Bit 2 : Write '1' to Enable interrupt for READY event */
10073 #define SPI_INTENSET_READY_Pos (2UL) /*!< Position of READY field. */
10074 #define SPI_INTENSET_READY_Msk (0x1UL << SPI_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
10075 #define SPI_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */
10076 #define SPI_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */
10077 #define SPI_INTENSET_READY_Set (1UL) /*!< Enable */
10078 
10079 /* Register: SPI_INTENCLR */
10080 /* Description: Disable interrupt */
10081 
10082 /* Bit 2 : Write '1' to Disable interrupt for READY event */
10083 #define SPI_INTENCLR_READY_Pos (2UL) /*!< Position of READY field. */
10084 #define SPI_INTENCLR_READY_Msk (0x1UL << SPI_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
10085 #define SPI_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */
10086 #define SPI_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */
10087 #define SPI_INTENCLR_READY_Clear (1UL) /*!< Disable */
10088 
10089 /* Register: SPI_ENABLE */
10090 /* Description: Enable SPI */
10091 
10092 /* Bits 3..0 : Enable or disable SPI */
10093 #define SPI_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
10094 #define SPI_ENABLE_ENABLE_Msk (0xFUL << SPI_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
10095 #define SPI_ENABLE_ENABLE_Disabled (0UL) /*!< Disable SPI */
10096 #define SPI_ENABLE_ENABLE_Enabled (1UL) /*!< Enable SPI */
10097 
10098 /* Register: SPI_PSEL_SCK */
10099 /* Description: Pin select for SCK */
10100 
10101 /* Bits 31..0 : Pin number configuration for SPI SCK signal */
10102 #define SPI_PSEL_SCK_PSELSCK_Pos (0UL) /*!< Position of PSELSCK field. */
10103 #define SPI_PSEL_SCK_PSELSCK_Msk (0xFFFFFFFFUL << SPI_PSEL_SCK_PSELSCK_Pos) /*!< Bit mask of PSELSCK field. */
10104 #define SPI_PSEL_SCK_PSELSCK_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */
10105 
10106 /* Register: SPI_PSEL_MOSI */
10107 /* Description: Pin select for MOSI */
10108 
10109 /* Bits 31..0 : Pin number configuration for SPI MOSI signal */
10110 #define SPI_PSEL_MOSI_PSELMOSI_Pos (0UL) /*!< Position of PSELMOSI field. */
10111 #define SPI_PSEL_MOSI_PSELMOSI_Msk (0xFFFFFFFFUL << SPI_PSEL_MOSI_PSELMOSI_Pos) /*!< Bit mask of PSELMOSI field. */
10112 #define SPI_PSEL_MOSI_PSELMOSI_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */
10113 
10114 /* Register: SPI_PSEL_MISO */
10115 /* Description: Pin select for MISO */
10116 
10117 /* Bits 31..0 : Pin number configuration for SPI MISO signal */
10118 #define SPI_PSEL_MISO_PSELMISO_Pos (0UL) /*!< Position of PSELMISO field. */
10119 #define SPI_PSEL_MISO_PSELMISO_Msk (0xFFFFFFFFUL << SPI_PSEL_MISO_PSELMISO_Pos) /*!< Bit mask of PSELMISO field. */
10120 #define SPI_PSEL_MISO_PSELMISO_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */
10121 
10122 /* Register: SPI_RXD */
10123 /* Description: RXD register */
10124 
10125 /* Bits 7..0 : RX data received. Double buffered */
10126 #define SPI_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */
10127 #define SPI_RXD_RXD_Msk (0xFFUL << SPI_RXD_RXD_Pos) /*!< Bit mask of RXD field. */
10128 
10129 /* Register: SPI_TXD */
10130 /* Description: TXD register */
10131 
10132 /* Bits 7..0 : TX data to send. Double buffered */
10133 #define SPI_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */
10134 #define SPI_TXD_TXD_Msk (0xFFUL << SPI_TXD_TXD_Pos) /*!< Bit mask of TXD field. */
10135 
10136 /* Register: SPI_FREQUENCY */
10137 /* Description: SPI frequency */
10138 
10139 /* Bits 31..0 : SPI master data rate */
10140 #define SPI_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
10141 #define SPI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPI_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
10142 #define SPI_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /*!< 125 kbps */
10143 #define SPI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */
10144 #define SPI_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /*!< 500 kbps */
10145 #define SPI_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /*!< 1 Mbps */
10146 #define SPI_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /*!< 2 Mbps */
10147 #define SPI_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /*!< 4 Mbps */
10148 #define SPI_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /*!< 8 Mbps */
10149 
10150 /* Register: SPI_CONFIG */
10151 /* Description: Configuration register */
10152 
10153 /* Bit 2 : Serial clock (SCK) polarity */
10154 #define SPI_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */
10155 #define SPI_CONFIG_CPOL_Msk (0x1UL << SPI_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */
10156 #define SPI_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high */
10157 #define SPI_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low */
10158 
10159 /* Bit 1 : Serial clock (SCK) phase */
10160 #define SPI_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */
10161 #define SPI_CONFIG_CPHA_Msk (0x1UL << SPI_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */
10162 #define SPI_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of clock, shift serial data on trailing edge */
10163 #define SPI_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of clock, shift serial data on leading edge */
10164 
10165 /* Bit 0 : Bit order */
10166 #define SPI_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */
10167 #define SPI_CONFIG_ORDER_Msk (0x1UL << SPI_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */
10168 #define SPI_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit shifted out first */
10169 #define SPI_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit shifted out first */
10170 
10171 
10172 /* Peripheral: SPIM */
10173 /* Description: Serial Peripheral Interface Master with EasyDMA 0 */
10174 
10175 /* Register: SPIM_SHORTS */
10176 /* Description: Shortcut register */
10177 
10178 /* Bit 17 : Shortcut between END event and START task */
10179 #define SPIM_SHORTS_END_START_Pos (17UL) /*!< Position of END_START field. */
10180 #define SPIM_SHORTS_END_START_Msk (0x1UL << SPIM_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */
10181 #define SPIM_SHORTS_END_START_Disabled (0UL) /*!< Disable shortcut */
10182 #define SPIM_SHORTS_END_START_Enabled (1UL) /*!< Enable shortcut */
10183 
10184 /* Register: SPIM_INTENSET */
10185 /* Description: Enable interrupt */
10186 
10187 /* Bit 19 : Write '1' to Enable interrupt for STARTED event */
10188 #define SPIM_INTENSET_STARTED_Pos (19UL) /*!< Position of STARTED field. */
10189 #define SPIM_INTENSET_STARTED_Msk (0x1UL << SPIM_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */
10190 #define SPIM_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */
10191 #define SPIM_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */
10192 #define SPIM_INTENSET_STARTED_Set (1UL) /*!< Enable */
10193 
10194 /* Bit 8 : Write '1' to Enable interrupt for ENDTX event */
10195 #define SPIM_INTENSET_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
10196 #define SPIM_INTENSET_ENDTX_Msk (0x1UL << SPIM_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
10197 #define SPIM_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */
10198 #define SPIM_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */
10199 #define SPIM_INTENSET_ENDTX_Set (1UL) /*!< Enable */
10200 
10201 /* Bit 6 : Write '1' to Enable interrupt for END event */
10202 #define SPIM_INTENSET_END_Pos (6UL) /*!< Position of END field. */
10203 #define SPIM_INTENSET_END_Msk (0x1UL << SPIM_INTENSET_END_Pos) /*!< Bit mask of END field. */
10204 #define SPIM_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
10205 #define SPIM_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
10206 #define SPIM_INTENSET_END_Set (1UL) /*!< Enable */
10207 
10208 /* Bit 4 : Write '1' to Enable interrupt for ENDRX event */
10209 #define SPIM_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
10210 #define SPIM_INTENSET_ENDRX_Msk (0x1UL << SPIM_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
10211 #define SPIM_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */
10212 #define SPIM_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */
10213 #define SPIM_INTENSET_ENDRX_Set (1UL) /*!< Enable */
10214 
10215 /* Bit 1 : Write '1' to Enable interrupt for STOPPED event */
10216 #define SPIM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
10217 #define SPIM_INTENSET_STOPPED_Msk (0x1UL << SPIM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
10218 #define SPIM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
10219 #define SPIM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
10220 #define SPIM_INTENSET_STOPPED_Set (1UL) /*!< Enable */
10221 
10222 /* Register: SPIM_INTENCLR */
10223 /* Description: Disable interrupt */
10224 
10225 /* Bit 19 : Write '1' to Disable interrupt for STARTED event */
10226 #define SPIM_INTENCLR_STARTED_Pos (19UL) /*!< Position of STARTED field. */
10227 #define SPIM_INTENCLR_STARTED_Msk (0x1UL << SPIM_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */
10228 #define SPIM_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */
10229 #define SPIM_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */
10230 #define SPIM_INTENCLR_STARTED_Clear (1UL) /*!< Disable */
10231 
10232 /* Bit 8 : Write '1' to Disable interrupt for ENDTX event */
10233 #define SPIM_INTENCLR_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
10234 #define SPIM_INTENCLR_ENDTX_Msk (0x1UL << SPIM_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
10235 #define SPIM_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */
10236 #define SPIM_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */
10237 #define SPIM_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */
10238 
10239 /* Bit 6 : Write '1' to Disable interrupt for END event */
10240 #define SPIM_INTENCLR_END_Pos (6UL) /*!< Position of END field. */
10241 #define SPIM_INTENCLR_END_Msk (0x1UL << SPIM_INTENCLR_END_Pos) /*!< Bit mask of END field. */
10242 #define SPIM_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
10243 #define SPIM_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
10244 #define SPIM_INTENCLR_END_Clear (1UL) /*!< Disable */
10245 
10246 /* Bit 4 : Write '1' to Disable interrupt for ENDRX event */
10247 #define SPIM_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
10248 #define SPIM_INTENCLR_ENDRX_Msk (0x1UL << SPIM_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
10249 #define SPIM_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */
10250 #define SPIM_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */
10251 #define SPIM_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */
10252 
10253 /* Bit 1 : Write '1' to Disable interrupt for STOPPED event */
10254 #define SPIM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
10255 #define SPIM_INTENCLR_STOPPED_Msk (0x1UL << SPIM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
10256 #define SPIM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
10257 #define SPIM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
10258 #define SPIM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
10259 
10260 /* Register: SPIM_ENABLE */
10261 /* Description: Enable SPIM */
10262 
10263 /* Bits 3..0 : Enable or disable SPIM */
10264 #define SPIM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
10265 #define SPIM_ENABLE_ENABLE_Msk (0xFUL << SPIM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
10266 #define SPIM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable SPIM */
10267 #define SPIM_ENABLE_ENABLE_Enabled (7UL) /*!< Enable SPIM */
10268 
10269 /* Register: SPIM_PSEL_SCK */
10270 /* Description: Pin select for SCK */
10271 
10272 /* Bit 31 : Connection */
10273 #define SPIM_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
10274 #define SPIM_PSEL_SCK_CONNECT_Msk (0x1UL << SPIM_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
10275 #define SPIM_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */
10276 #define SPIM_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */
10277 
10278 /* Bits 4..0 : Pin number */
10279 #define SPIM_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */
10280 #define SPIM_PSEL_SCK_PIN_Msk (0x1FUL << SPIM_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */
10281 
10282 /* Register: SPIM_PSEL_MOSI */
10283 /* Description: Pin select for MOSI signal */
10284 
10285 /* Bit 31 : Connection */
10286 #define SPIM_PSEL_MOSI_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
10287 #define SPIM_PSEL_MOSI_CONNECT_Msk (0x1UL << SPIM_PSEL_MOSI_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
10288 #define SPIM_PSEL_MOSI_CONNECT_Connected (0UL) /*!< Connect */
10289 #define SPIM_PSEL_MOSI_CONNECT_Disconnected (1UL) /*!< Disconnect */
10290 
10291 /* Bits 4..0 : Pin number */
10292 #define SPIM_PSEL_MOSI_PIN_Pos (0UL) /*!< Position of PIN field. */
10293 #define SPIM_PSEL_MOSI_PIN_Msk (0x1FUL << SPIM_PSEL_MOSI_PIN_Pos) /*!< Bit mask of PIN field. */
10294 
10295 /* Register: SPIM_PSEL_MISO */
10296 /* Description: Pin select for MISO signal */
10297 
10298 /* Bit 31 : Connection */
10299 #define SPIM_PSEL_MISO_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
10300 #define SPIM_PSEL_MISO_CONNECT_Msk (0x1UL << SPIM_PSEL_MISO_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
10301 #define SPIM_PSEL_MISO_CONNECT_Connected (0UL) /*!< Connect */
10302 #define SPIM_PSEL_MISO_CONNECT_Disconnected (1UL) /*!< Disconnect */
10303 
10304 /* Bits 4..0 : Pin number */
10305 #define SPIM_PSEL_MISO_PIN_Pos (0UL) /*!< Position of PIN field. */
10306 #define SPIM_PSEL_MISO_PIN_Msk (0x1FUL << SPIM_PSEL_MISO_PIN_Pos) /*!< Bit mask of PIN field. */
10307 
10308 /* Register: SPIM_FREQUENCY */
10309 /* Description: SPI frequency */
10310 
10311 /* Bits 31..0 : SPI master data rate */
10312 #define SPIM_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
10313 #define SPIM_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPIM_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
10314 #define SPIM_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /*!< 125 kbps */
10315 #define SPIM_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */
10316 #define SPIM_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /*!< 500 kbps */
10317 #define SPIM_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /*!< 1 Mbps */
10318 #define SPIM_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /*!< 2 Mbps */
10319 #define SPIM_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /*!< 4 Mbps */
10320 #define SPIM_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /*!< 8 Mbps */
10321 
10322 /* Register: SPIM_RXD_PTR */
10323 /* Description: Data pointer */
10324 
10325 /* Bits 31..0 : Data pointer */
10326 #define SPIM_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
10327 #define SPIM_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
10328 
10329 /* Register: SPIM_RXD_MAXCNT */
10330 /* Description: Maximum number of bytes in receive buffer */
10331 
10332 /* Bits 7..0 : Maximum number of bytes in receive buffer */
10333 #define SPIM_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
10334 #define SPIM_RXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIM_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
10335 
10336 /* Register: SPIM_RXD_AMOUNT */
10337 /* Description: Number of bytes transferred in the last transaction */
10338 
10339 /* Bits 7..0 : Number of bytes transferred in the last transaction */
10340 #define SPIM_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
10341 #define SPIM_RXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIM_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
10342 
10343 /* Register: SPIM_RXD_LIST */
10344 /* Description: EasyDMA list type */
10345 
10346 /* Bits 2..0 : List type */
10347 #define SPIM_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
10348 #define SPIM_RXD_LIST_LIST_Msk (0x7UL << SPIM_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
10349 #define SPIM_RXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
10350 #define SPIM_RXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
10351 
10352 /* Register: SPIM_TXD_PTR */
10353 /* Description: Data pointer */
10354 
10355 /* Bits 31..0 : Data pointer */
10356 #define SPIM_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
10357 #define SPIM_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
10358 
10359 /* Register: SPIM_TXD_MAXCNT */
10360 /* Description: Maximum number of bytes in transmit buffer */
10361 
10362 /* Bits 7..0 : Maximum number of bytes in transmit buffer */
10363 #define SPIM_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
10364 #define SPIM_TXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIM_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
10365 
10366 /* Register: SPIM_TXD_AMOUNT */
10367 /* Description: Number of bytes transferred in the last transaction */
10368 
10369 /* Bits 7..0 : Number of bytes transferred in the last transaction */
10370 #define SPIM_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
10371 #define SPIM_TXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIM_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
10372 
10373 /* Register: SPIM_TXD_LIST */
10374 /* Description: EasyDMA list type */
10375 
10376 /* Bits 2..0 : List type */
10377 #define SPIM_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
10378 #define SPIM_TXD_LIST_LIST_Msk (0x7UL << SPIM_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
10379 #define SPIM_TXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
10380 #define SPIM_TXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
10381 
10382 /* Register: SPIM_CONFIG */
10383 /* Description: Configuration register */
10384 
10385 /* Bit 2 : Serial clock (SCK) polarity */
10386 #define SPIM_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */
10387 #define SPIM_CONFIG_CPOL_Msk (0x1UL << SPIM_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */
10388 #define SPIM_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high */
10389 #define SPIM_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low */
10390 
10391 /* Bit 1 : Serial clock (SCK) phase */
10392 #define SPIM_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */
10393 #define SPIM_CONFIG_CPHA_Msk (0x1UL << SPIM_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */
10394 #define SPIM_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of clock, shift serial data on trailing edge */
10395 #define SPIM_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of clock, shift serial data on leading edge */
10396 
10397 /* Bit 0 : Bit order */
10398 #define SPIM_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */
10399 #define SPIM_CONFIG_ORDER_Msk (0x1UL << SPIM_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */
10400 #define SPIM_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit shifted out first */
10401 #define SPIM_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit shifted out first */
10402 
10403 /* Register: SPIM_ORC */
10404 /* Description: Over-read character. Character clocked out in case and over-read of the TXD buffer. */
10405 
10406 /* Bits 7..0 : Over-read character. Character clocked out in case and over-read of the TXD buffer. */
10407 #define SPIM_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */
10408 #define SPIM_ORC_ORC_Msk (0xFFUL << SPIM_ORC_ORC_Pos) /*!< Bit mask of ORC field. */
10409 
10410 
10411 /* Peripheral: SPIS */
10412 /* Description: SPI Slave 0 */
10413 
10414 /* Register: SPIS_SHORTS */
10415 /* Description: Shortcut register */
10416 
10417 /* Bit 2 : Shortcut between END event and ACQUIRE task */
10418 #define SPIS_SHORTS_END_ACQUIRE_Pos (2UL) /*!< Position of END_ACQUIRE field. */
10419 #define SPIS_SHORTS_END_ACQUIRE_Msk (0x1UL << SPIS_SHORTS_END_ACQUIRE_Pos) /*!< Bit mask of END_ACQUIRE field. */
10420 #define SPIS_SHORTS_END_ACQUIRE_Disabled (0UL) /*!< Disable shortcut */
10421 #define SPIS_SHORTS_END_ACQUIRE_Enabled (1UL) /*!< Enable shortcut */
10422 
10423 /* Register: SPIS_INTENSET */
10424 /* Description: Enable interrupt */
10425 
10426 /* Bit 10 : Write '1' to Enable interrupt for ACQUIRED event */
10427 #define SPIS_INTENSET_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */
10428 #define SPIS_INTENSET_ACQUIRED_Msk (0x1UL << SPIS_INTENSET_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */
10429 #define SPIS_INTENSET_ACQUIRED_Disabled (0UL) /*!< Read: Disabled */
10430 #define SPIS_INTENSET_ACQUIRED_Enabled (1UL) /*!< Read: Enabled */
10431 #define SPIS_INTENSET_ACQUIRED_Set (1UL) /*!< Enable */
10432 
10433 /* Bit 4 : Write '1' to Enable interrupt for ENDRX event */
10434 #define SPIS_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
10435 #define SPIS_INTENSET_ENDRX_Msk (0x1UL << SPIS_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
10436 #define SPIS_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */
10437 #define SPIS_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */
10438 #define SPIS_INTENSET_ENDRX_Set (1UL) /*!< Enable */
10439 
10440 /* Bit 1 : Write '1' to Enable interrupt for END event */
10441 #define SPIS_INTENSET_END_Pos (1UL) /*!< Position of END field. */
10442 #define SPIS_INTENSET_END_Msk (0x1UL << SPIS_INTENSET_END_Pos) /*!< Bit mask of END field. */
10443 #define SPIS_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
10444 #define SPIS_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
10445 #define SPIS_INTENSET_END_Set (1UL) /*!< Enable */
10446 
10447 /* Register: SPIS_INTENCLR */
10448 /* Description: Disable interrupt */
10449 
10450 /* Bit 10 : Write '1' to Disable interrupt for ACQUIRED event */
10451 #define SPIS_INTENCLR_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */
10452 #define SPIS_INTENCLR_ACQUIRED_Msk (0x1UL << SPIS_INTENCLR_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */
10453 #define SPIS_INTENCLR_ACQUIRED_Disabled (0UL) /*!< Read: Disabled */
10454 #define SPIS_INTENCLR_ACQUIRED_Enabled (1UL) /*!< Read: Enabled */
10455 #define SPIS_INTENCLR_ACQUIRED_Clear (1UL) /*!< Disable */
10456 
10457 /* Bit 4 : Write '1' to Disable interrupt for ENDRX event */
10458 #define SPIS_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
10459 #define SPIS_INTENCLR_ENDRX_Msk (0x1UL << SPIS_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
10460 #define SPIS_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */
10461 #define SPIS_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */
10462 #define SPIS_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */
10463 
10464 /* Bit 1 : Write '1' to Disable interrupt for END event */
10465 #define SPIS_INTENCLR_END_Pos (1UL) /*!< Position of END field. */
10466 #define SPIS_INTENCLR_END_Msk (0x1UL << SPIS_INTENCLR_END_Pos) /*!< Bit mask of END field. */
10467 #define SPIS_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
10468 #define SPIS_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
10469 #define SPIS_INTENCLR_END_Clear (1UL) /*!< Disable */
10470 
10471 /* Register: SPIS_SEMSTAT */
10472 /* Description: Semaphore status register */
10473 
10474 /* Bits 1..0 : Semaphore status */
10475 #define SPIS_SEMSTAT_SEMSTAT_Pos (0UL) /*!< Position of SEMSTAT field. */
10476 #define SPIS_SEMSTAT_SEMSTAT_Msk (0x3UL << SPIS_SEMSTAT_SEMSTAT_Pos) /*!< Bit mask of SEMSTAT field. */
10477 #define SPIS_SEMSTAT_SEMSTAT_Free (0UL) /*!< Semaphore is free */
10478 #define SPIS_SEMSTAT_SEMSTAT_CPU (1UL) /*!< Semaphore is assigned to CPU */
10479 #define SPIS_SEMSTAT_SEMSTAT_SPIS (2UL) /*!< Semaphore is assigned to SPI slave */
10480 #define SPIS_SEMSTAT_SEMSTAT_CPUPending (3UL) /*!< Semaphore is assigned to SPI but a handover to the CPU is pending */
10481 
10482 /* Register: SPIS_STATUS */
10483 /* Description: Status from last transaction */
10484 
10485 /* Bit 1 : RX buffer overflow detected, and prevented */
10486 #define SPIS_STATUS_OVERFLOW_Pos (1UL) /*!< Position of OVERFLOW field. */
10487 #define SPIS_STATUS_OVERFLOW_Msk (0x1UL << SPIS_STATUS_OVERFLOW_Pos) /*!< Bit mask of OVERFLOW field. */
10488 #define SPIS_STATUS_OVERFLOW_NotPresent (0UL) /*!< Read: error not present */
10489 #define SPIS_STATUS_OVERFLOW_Present (1UL) /*!< Read: error present */
10490 #define SPIS_STATUS_OVERFLOW_Clear (1UL) /*!< Write: clear error on writing '1' */
10491 
10492 /* Bit 0 : TX buffer over-read detected, and prevented */
10493 #define SPIS_STATUS_OVERREAD_Pos (0UL) /*!< Position of OVERREAD field. */
10494 #define SPIS_STATUS_OVERREAD_Msk (0x1UL << SPIS_STATUS_OVERREAD_Pos) /*!< Bit mask of OVERREAD field. */
10495 #define SPIS_STATUS_OVERREAD_NotPresent (0UL) /*!< Read: error not present */
10496 #define SPIS_STATUS_OVERREAD_Present (1UL) /*!< Read: error present */
10497 #define SPIS_STATUS_OVERREAD_Clear (1UL) /*!< Write: clear error on writing '1' */
10498 
10499 /* Register: SPIS_ENABLE */
10500 /* Description: Enable SPI slave */
10501 
10502 /* Bits 3..0 : Enable or disable SPI slave */
10503 #define SPIS_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
10504 #define SPIS_ENABLE_ENABLE_Msk (0xFUL << SPIS_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
10505 #define SPIS_ENABLE_ENABLE_Disabled (0UL) /*!< Disable SPI slave */
10506 #define SPIS_ENABLE_ENABLE_Enabled (2UL) /*!< Enable SPI slave */
10507 
10508 /* Register: SPIS_PSEL_SCK */
10509 /* Description: Pin select for SCK */
10510 
10511 /* Bit 31 : Connection */
10512 #define SPIS_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
10513 #define SPIS_PSEL_SCK_CONNECT_Msk (0x1UL << SPIS_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
10514 #define SPIS_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */
10515 #define SPIS_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */
10516 
10517 /* Bits 4..0 : Pin number */
10518 #define SPIS_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */
10519 #define SPIS_PSEL_SCK_PIN_Msk (0x1FUL << SPIS_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */
10520 
10521 /* Register: SPIS_PSEL_MISO */
10522 /* Description: Pin select for MISO signal */
10523 
10524 /* Bit 31 : Connection */
10525 #define SPIS_PSEL_MISO_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
10526 #define SPIS_PSEL_MISO_CONNECT_Msk (0x1UL << SPIS_PSEL_MISO_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
10527 #define SPIS_PSEL_MISO_CONNECT_Connected (0UL) /*!< Connect */
10528 #define SPIS_PSEL_MISO_CONNECT_Disconnected (1UL) /*!< Disconnect */
10529 
10530 /* Bits 4..0 : Pin number */
10531 #define SPIS_PSEL_MISO_PIN_Pos (0UL) /*!< Position of PIN field. */
10532 #define SPIS_PSEL_MISO_PIN_Msk (0x1FUL << SPIS_PSEL_MISO_PIN_Pos) /*!< Bit mask of PIN field. */
10533 
10534 /* Register: SPIS_PSEL_MOSI */
10535 /* Description: Pin select for MOSI signal */
10536 
10537 /* Bit 31 : Connection */
10538 #define SPIS_PSEL_MOSI_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
10539 #define SPIS_PSEL_MOSI_CONNECT_Msk (0x1UL << SPIS_PSEL_MOSI_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
10540 #define SPIS_PSEL_MOSI_CONNECT_Connected (0UL) /*!< Connect */
10541 #define SPIS_PSEL_MOSI_CONNECT_Disconnected (1UL) /*!< Disconnect */
10542 
10543 /* Bits 4..0 : Pin number */
10544 #define SPIS_PSEL_MOSI_PIN_Pos (0UL) /*!< Position of PIN field. */
10545 #define SPIS_PSEL_MOSI_PIN_Msk (0x1FUL << SPIS_PSEL_MOSI_PIN_Pos) /*!< Bit mask of PIN field. */
10546 
10547 /* Register: SPIS_PSEL_CSN */
10548 /* Description: Pin select for CSN signal */
10549 
10550 /* Bit 31 : Connection */
10551 #define SPIS_PSEL_CSN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
10552 #define SPIS_PSEL_CSN_CONNECT_Msk (0x1UL << SPIS_PSEL_CSN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
10553 #define SPIS_PSEL_CSN_CONNECT_Connected (0UL) /*!< Connect */
10554 #define SPIS_PSEL_CSN_CONNECT_Disconnected (1UL) /*!< Disconnect */
10555 
10556 /* Bits 4..0 : Pin number */
10557 #define SPIS_PSEL_CSN_PIN_Pos (0UL) /*!< Position of PIN field. */
10558 #define SPIS_PSEL_CSN_PIN_Msk (0x1FUL << SPIS_PSEL_CSN_PIN_Pos) /*!< Bit mask of PIN field. */
10559 
10560 /* Register: SPIS_RXD_PTR */
10561 /* Description: RXD data pointer */
10562 
10563 /* Bits 31..0 : RXD data pointer */
10564 #define SPIS_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
10565 #define SPIS_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIS_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
10566 
10567 /* Register: SPIS_RXD_MAXCNT */
10568 /* Description: Maximum number of bytes in receive buffer */
10569 
10570 /* Bits 7..0 : Maximum number of bytes in receive buffer */
10571 #define SPIS_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
10572 #define SPIS_RXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIS_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
10573 
10574 /* Register: SPIS_RXD_AMOUNT */
10575 /* Description: Number of bytes received in last granted transaction */
10576 
10577 /* Bits 7..0 : Number of bytes received in the last granted transaction */
10578 #define SPIS_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
10579 #define SPIS_RXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIS_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
10580 
10581 /* Register: SPIS_TXD_PTR */
10582 /* Description: TXD data pointer */
10583 
10584 /* Bits 31..0 : TXD data pointer */
10585 #define SPIS_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
10586 #define SPIS_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIS_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
10587 
10588 /* Register: SPIS_TXD_MAXCNT */
10589 /* Description: Maximum number of bytes in transmit buffer */
10590 
10591 /* Bits 7..0 : Maximum number of bytes in transmit buffer */
10592 #define SPIS_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
10593 #define SPIS_TXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIS_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
10594 
10595 /* Register: SPIS_TXD_AMOUNT */
10596 /* Description: Number of bytes transmitted in last granted transaction */
10597 
10598 /* Bits 7..0 : Number of bytes transmitted in last granted transaction */
10599 #define SPIS_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
10600 #define SPIS_TXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIS_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
10601 
10602 /* Register: SPIS_CONFIG */
10603 /* Description: Configuration register */
10604 
10605 /* Bit 2 : Serial clock (SCK) polarity */
10606 #define SPIS_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */
10607 #define SPIS_CONFIG_CPOL_Msk (0x1UL << SPIS_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */
10608 #define SPIS_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high */
10609 #define SPIS_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low */
10610 
10611 /* Bit 1 : Serial clock (SCK) phase */
10612 #define SPIS_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */
10613 #define SPIS_CONFIG_CPHA_Msk (0x1UL << SPIS_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */
10614 #define SPIS_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of clock, shift serial data on trailing edge */
10615 #define SPIS_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of clock, shift serial data on leading edge */
10616 
10617 /* Bit 0 : Bit order */
10618 #define SPIS_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */
10619 #define SPIS_CONFIG_ORDER_Msk (0x1UL << SPIS_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */
10620 #define SPIS_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit shifted out first */
10621 #define SPIS_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit shifted out first */
10622 
10623 /* Register: SPIS_DEF */
10624 /* Description: Default character. Character clocked out in case of an ignored transaction. */
10625 
10626 /* Bits 7..0 : Default character. Character clocked out in case of an ignored transaction. */
10627 #define SPIS_DEF_DEF_Pos (0UL) /*!< Position of DEF field. */
10628 #define SPIS_DEF_DEF_Msk (0xFFUL << SPIS_DEF_DEF_Pos) /*!< Bit mask of DEF field. */
10629 
10630 /* Register: SPIS_ORC */
10631 /* Description: Over-read character */
10632 
10633 /* Bits 7..0 : Over-read character. Character clocked out after an over-read of the transmit buffer. */
10634 #define SPIS_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */
10635 #define SPIS_ORC_ORC_Msk (0xFFUL << SPIS_ORC_ORC_Pos) /*!< Bit mask of ORC field. */
10636 
10637 
10638 /* Peripheral: TEMP */
10639 /* Description: Temperature Sensor */
10640 
10641 /* Register: TEMP_INTENSET */
10642 /* Description: Enable interrupt */
10643 
10644 /* Bit 0 : Write '1' to Enable interrupt for DATARDY event */
10645 #define TEMP_INTENSET_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */
10646 #define TEMP_INTENSET_DATARDY_Msk (0x1UL << TEMP_INTENSET_DATARDY_Pos) /*!< Bit mask of DATARDY field. */
10647 #define TEMP_INTENSET_DATARDY_Disabled (0UL) /*!< Read: Disabled */
10648 #define TEMP_INTENSET_DATARDY_Enabled (1UL) /*!< Read: Enabled */
10649 #define TEMP_INTENSET_DATARDY_Set (1UL) /*!< Enable */
10650 
10651 /* Register: TEMP_INTENCLR */
10652 /* Description: Disable interrupt */
10653 
10654 /* Bit 0 : Write '1' to Disable interrupt for DATARDY event */
10655 #define TEMP_INTENCLR_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */
10656 #define TEMP_INTENCLR_DATARDY_Msk (0x1UL << TEMP_INTENCLR_DATARDY_Pos) /*!< Bit mask of DATARDY field. */
10657 #define TEMP_INTENCLR_DATARDY_Disabled (0UL) /*!< Read: Disabled */
10658 #define TEMP_INTENCLR_DATARDY_Enabled (1UL) /*!< Read: Enabled */
10659 #define TEMP_INTENCLR_DATARDY_Clear (1UL) /*!< Disable */
10660 
10661 /* Register: TEMP_TEMP */
10662 /* Description: Temperature in degC (0.25deg steps) */
10663 
10664 /* Bits 31..0 : Temperature in degC (0.25deg steps) */
10665 #define TEMP_TEMP_TEMP_Pos (0UL) /*!< Position of TEMP field. */
10666 #define TEMP_TEMP_TEMP_Msk (0xFFFFFFFFUL << TEMP_TEMP_TEMP_Pos) /*!< Bit mask of TEMP field. */
10667 
10668 /* Register: TEMP_A0 */
10669 /* Description: Slope of 1st piece wise linear function */
10670 
10671 /* Bits 11..0 : Slope of 1st piece wise linear function */
10672 #define TEMP_A0_A0_Pos (0UL) /*!< Position of A0 field. */
10673 #define TEMP_A0_A0_Msk (0xFFFUL << TEMP_A0_A0_Pos) /*!< Bit mask of A0 field. */
10674 
10675 /* Register: TEMP_A1 */
10676 /* Description: Slope of 2nd piece wise linear function */
10677 
10678 /* Bits 11..0 : Slope of 2nd piece wise linear function */
10679 #define TEMP_A1_A1_Pos (0UL) /*!< Position of A1 field. */
10680 #define TEMP_A1_A1_Msk (0xFFFUL << TEMP_A1_A1_Pos) /*!< Bit mask of A1 field. */
10681 
10682 /* Register: TEMP_A2 */
10683 /* Description: Slope of 3rd piece wise linear function */
10684 
10685 /* Bits 11..0 : Slope of 3rd piece wise linear function */
10686 #define TEMP_A2_A2_Pos (0UL) /*!< Position of A2 field. */
10687 #define TEMP_A2_A2_Msk (0xFFFUL << TEMP_A2_A2_Pos) /*!< Bit mask of A2 field. */
10688 
10689 /* Register: TEMP_A3 */
10690 /* Description: Slope of 4th piece wise linear function */
10691 
10692 /* Bits 11..0 : Slope of 4th piece wise linear function */
10693 #define TEMP_A3_A3_Pos (0UL) /*!< Position of A3 field. */
10694 #define TEMP_A3_A3_Msk (0xFFFUL << TEMP_A3_A3_Pos) /*!< Bit mask of A3 field. */
10695 
10696 /* Register: TEMP_A4 */
10697 /* Description: Slope of 5th piece wise linear function */
10698 
10699 /* Bits 11..0 : Slope of 5th piece wise linear function */
10700 #define TEMP_A4_A4_Pos (0UL) /*!< Position of A4 field. */
10701 #define TEMP_A4_A4_Msk (0xFFFUL << TEMP_A4_A4_Pos) /*!< Bit mask of A4 field. */
10702 
10703 /* Register: TEMP_A5 */
10704 /* Description: Slope of 6th piece wise linear function */
10705 
10706 /* Bits 11..0 : Slope of 6th piece wise linear function */
10707 #define TEMP_A5_A5_Pos (0UL) /*!< Position of A5 field. */
10708 #define TEMP_A5_A5_Msk (0xFFFUL << TEMP_A5_A5_Pos) /*!< Bit mask of A5 field. */
10709 
10710 /* Register: TEMP_B0 */
10711 /* Description: y-intercept of 1st piece wise linear function */
10712 
10713 /* Bits 13..0 : y-intercept of 1st piece wise linear function */
10714 #define TEMP_B0_B0_Pos (0UL) /*!< Position of B0 field. */
10715 #define TEMP_B0_B0_Msk (0x3FFFUL << TEMP_B0_B0_Pos) /*!< Bit mask of B0 field. */
10716 
10717 /* Register: TEMP_B1 */
10718 /* Description: y-intercept of 2nd piece wise linear function */
10719 
10720 /* Bits 13..0 : y-intercept of 2nd piece wise linear function */
10721 #define TEMP_B1_B1_Pos (0UL) /*!< Position of B1 field. */
10722 #define TEMP_B1_B1_Msk (0x3FFFUL << TEMP_B1_B1_Pos) /*!< Bit mask of B1 field. */
10723 
10724 /* Register: TEMP_B2 */
10725 /* Description: y-intercept of 3rd piece wise linear function */
10726 
10727 /* Bits 13..0 : y-intercept of 3rd piece wise linear function */
10728 #define TEMP_B2_B2_Pos (0UL) /*!< Position of B2 field. */
10729 #define TEMP_B2_B2_Msk (0x3FFFUL << TEMP_B2_B2_Pos) /*!< Bit mask of B2 field. */
10730 
10731 /* Register: TEMP_B3 */
10732 /* Description: y-intercept of 4th piece wise linear function */
10733 
10734 /* Bits 13..0 : y-intercept of 4th piece wise linear function */
10735 #define TEMP_B3_B3_Pos (0UL) /*!< Position of B3 field. */
10736 #define TEMP_B3_B3_Msk (0x3FFFUL << TEMP_B3_B3_Pos) /*!< Bit mask of B3 field. */
10737 
10738 /* Register: TEMP_B4 */
10739 /* Description: y-intercept of 5th piece wise linear function */
10740 
10741 /* Bits 13..0 : y-intercept of 5th piece wise linear function */
10742 #define TEMP_B4_B4_Pos (0UL) /*!< Position of B4 field. */
10743 #define TEMP_B4_B4_Msk (0x3FFFUL << TEMP_B4_B4_Pos) /*!< Bit mask of B4 field. */
10744 
10745 /* Register: TEMP_B5 */
10746 /* Description: y-intercept of 6th piece wise linear function */
10747 
10748 /* Bits 13..0 : y-intercept of 6th piece wise linear function */
10749 #define TEMP_B5_B5_Pos (0UL) /*!< Position of B5 field. */
10750 #define TEMP_B5_B5_Msk (0x3FFFUL << TEMP_B5_B5_Pos) /*!< Bit mask of B5 field. */
10751 
10752 /* Register: TEMP_T0 */
10753 /* Description: End point of 1st piece wise linear function */
10754 
10755 /* Bits 7..0 : End point of 1st piece wise linear function */
10756 #define TEMP_T0_T0_Pos (0UL) /*!< Position of T0 field. */
10757 #define TEMP_T0_T0_Msk (0xFFUL << TEMP_T0_T0_Pos) /*!< Bit mask of T0 field. */
10758 
10759 /* Register: TEMP_T1 */
10760 /* Description: End point of 2nd piece wise linear function */
10761 
10762 /* Bits 7..0 : End point of 2nd piece wise linear function */
10763 #define TEMP_T1_T1_Pos (0UL) /*!< Position of T1 field. */
10764 #define TEMP_T1_T1_Msk (0xFFUL << TEMP_T1_T1_Pos) /*!< Bit mask of T1 field. */
10765 
10766 /* Register: TEMP_T2 */
10767 /* Description: End point of 3rd piece wise linear function */
10768 
10769 /* Bits 7..0 : End point of 3rd piece wise linear function */
10770 #define TEMP_T2_T2_Pos (0UL) /*!< Position of T2 field. */
10771 #define TEMP_T2_T2_Msk (0xFFUL << TEMP_T2_T2_Pos) /*!< Bit mask of T2 field. */
10772 
10773 /* Register: TEMP_T3 */
10774 /* Description: End point of 4th piece wise linear function */
10775 
10776 /* Bits 7..0 : End point of 4th piece wise linear function */
10777 #define TEMP_T3_T3_Pos (0UL) /*!< Position of T3 field. */
10778 #define TEMP_T3_T3_Msk (0xFFUL << TEMP_T3_T3_Pos) /*!< Bit mask of T3 field. */
10779 
10780 /* Register: TEMP_T4 */
10781 /* Description: End point of 5th piece wise linear function */
10782 
10783 /* Bits 7..0 : End point of 5th piece wise linear function */
10784 #define TEMP_T4_T4_Pos (0UL) /*!< Position of T4 field. */
10785 #define TEMP_T4_T4_Msk (0xFFUL << TEMP_T4_T4_Pos) /*!< Bit mask of T4 field. */
10786 
10787 
10788 /* Peripheral: TIMER */
10789 /* Description: Timer/Counter 0 */
10790 
10791 /* Register: TIMER_SHORTS */
10792 /* Description: Shortcut register */
10793 
10794 /* Bit 13 : Shortcut between COMPARE[5] event and STOP task */
10795 #define TIMER_SHORTS_COMPARE5_STOP_Pos (13UL) /*!< Position of COMPARE5_STOP field. */
10796 #define TIMER_SHORTS_COMPARE5_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE5_STOP_Pos) /*!< Bit mask of COMPARE5_STOP field. */
10797 #define TIMER_SHORTS_COMPARE5_STOP_Disabled (0UL) /*!< Disable shortcut */
10798 #define TIMER_SHORTS_COMPARE5_STOP_Enabled (1UL) /*!< Enable shortcut */
10799 
10800 /* Bit 12 : Shortcut between COMPARE[4] event and STOP task */
10801 #define TIMER_SHORTS_COMPARE4_STOP_Pos (12UL) /*!< Position of COMPARE4_STOP field. */
10802 #define TIMER_SHORTS_COMPARE4_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE4_STOP_Pos) /*!< Bit mask of COMPARE4_STOP field. */
10803 #define TIMER_SHORTS_COMPARE4_STOP_Disabled (0UL) /*!< Disable shortcut */
10804 #define TIMER_SHORTS_COMPARE4_STOP_Enabled (1UL) /*!< Enable shortcut */
10805 
10806 /* Bit 11 : Shortcut between COMPARE[3] event and STOP task */
10807 #define TIMER_SHORTS_COMPARE3_STOP_Pos (11UL) /*!< Position of COMPARE3_STOP field. */
10808 #define TIMER_SHORTS_COMPARE3_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE3_STOP_Pos) /*!< Bit mask of COMPARE3_STOP field. */
10809 #define TIMER_SHORTS_COMPARE3_STOP_Disabled (0UL) /*!< Disable shortcut */
10810 #define TIMER_SHORTS_COMPARE3_STOP_Enabled (1UL) /*!< Enable shortcut */
10811 
10812 /* Bit 10 : Shortcut between COMPARE[2] event and STOP task */
10813 #define TIMER_SHORTS_COMPARE2_STOP_Pos (10UL) /*!< Position of COMPARE2_STOP field. */
10814 #define TIMER_SHORTS_COMPARE2_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE2_STOP_Pos) /*!< Bit mask of COMPARE2_STOP field. */
10815 #define TIMER_SHORTS_COMPARE2_STOP_Disabled (0UL) /*!< Disable shortcut */
10816 #define TIMER_SHORTS_COMPARE2_STOP_Enabled (1UL) /*!< Enable shortcut */
10817 
10818 /* Bit 9 : Shortcut between COMPARE[1] event and STOP task */
10819 #define TIMER_SHORTS_COMPARE1_STOP_Pos (9UL) /*!< Position of COMPARE1_STOP field. */
10820 #define TIMER_SHORTS_COMPARE1_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE1_STOP_Pos) /*!< Bit mask of COMPARE1_STOP field. */
10821 #define TIMER_SHORTS_COMPARE1_STOP_Disabled (0UL) /*!< Disable shortcut */
10822 #define TIMER_SHORTS_COMPARE1_STOP_Enabled (1UL) /*!< Enable shortcut */
10823 
10824 /* Bit 8 : Shortcut between COMPARE[0] event and STOP task */
10825 #define TIMER_SHORTS_COMPARE0_STOP_Pos (8UL) /*!< Position of COMPARE0_STOP field. */
10826 #define TIMER_SHORTS_COMPARE0_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE0_STOP_Pos) /*!< Bit mask of COMPARE0_STOP field. */
10827 #define TIMER_SHORTS_COMPARE0_STOP_Disabled (0UL) /*!< Disable shortcut */
10828 #define TIMER_SHORTS_COMPARE0_STOP_Enabled (1UL) /*!< Enable shortcut */
10829 
10830 /* Bit 5 : Shortcut between COMPARE[5] event and CLEAR task */
10831 #define TIMER_SHORTS_COMPARE5_CLEAR_Pos (5UL) /*!< Position of COMPARE5_CLEAR field. */
10832 #define TIMER_SHORTS_COMPARE5_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE5_CLEAR_Pos) /*!< Bit mask of COMPARE5_CLEAR field. */
10833 #define TIMER_SHORTS_COMPARE5_CLEAR_Disabled (0UL) /*!< Disable shortcut */
10834 #define TIMER_SHORTS_COMPARE5_CLEAR_Enabled (1UL) /*!< Enable shortcut */
10835 
10836 /* Bit 4 : Shortcut between COMPARE[4] event and CLEAR task */
10837 #define TIMER_SHORTS_COMPARE4_CLEAR_Pos (4UL) /*!< Position of COMPARE4_CLEAR field. */
10838 #define TIMER_SHORTS_COMPARE4_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE4_CLEAR_Pos) /*!< Bit mask of COMPARE4_CLEAR field. */
10839 #define TIMER_SHORTS_COMPARE4_CLEAR_Disabled (0UL) /*!< Disable shortcut */
10840 #define TIMER_SHORTS_COMPARE4_CLEAR_Enabled (1UL) /*!< Enable shortcut */
10841 
10842 /* Bit 3 : Shortcut between COMPARE[3] event and CLEAR task */
10843 #define TIMER_SHORTS_COMPARE3_CLEAR_Pos (3UL) /*!< Position of COMPARE3_CLEAR field. */
10844 #define TIMER_SHORTS_COMPARE3_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE3_CLEAR_Pos) /*!< Bit mask of COMPARE3_CLEAR field. */
10845 #define TIMER_SHORTS_COMPARE3_CLEAR_Disabled (0UL) /*!< Disable shortcut */
10846 #define TIMER_SHORTS_COMPARE3_CLEAR_Enabled (1UL) /*!< Enable shortcut */
10847 
10848 /* Bit 2 : Shortcut between COMPARE[2] event and CLEAR task */
10849 #define TIMER_SHORTS_COMPARE2_CLEAR_Pos (2UL) /*!< Position of COMPARE2_CLEAR field. */
10850 #define TIMER_SHORTS_COMPARE2_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE2_CLEAR_Pos) /*!< Bit mask of COMPARE2_CLEAR field. */
10851 #define TIMER_SHORTS_COMPARE2_CLEAR_Disabled (0UL) /*!< Disable shortcut */
10852 #define TIMER_SHORTS_COMPARE2_CLEAR_Enabled (1UL) /*!< Enable shortcut */
10853 
10854 /* Bit 1 : Shortcut between COMPARE[1] event and CLEAR task */
10855 #define TIMER_SHORTS_COMPARE1_CLEAR_Pos (1UL) /*!< Position of COMPARE1_CLEAR field. */
10856 #define TIMER_SHORTS_COMPARE1_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE1_CLEAR_Pos) /*!< Bit mask of COMPARE1_CLEAR field. */
10857 #define TIMER_SHORTS_COMPARE1_CLEAR_Disabled (0UL) /*!< Disable shortcut */
10858 #define TIMER_SHORTS_COMPARE1_CLEAR_Enabled (1UL) /*!< Enable shortcut */
10859 
10860 /* Bit 0 : Shortcut between COMPARE[0] event and CLEAR task */
10861 #define TIMER_SHORTS_COMPARE0_CLEAR_Pos (0UL) /*!< Position of COMPARE0_CLEAR field. */
10862 #define TIMER_SHORTS_COMPARE0_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE0_CLEAR_Pos) /*!< Bit mask of COMPARE0_CLEAR field. */
10863 #define TIMER_SHORTS_COMPARE0_CLEAR_Disabled (0UL) /*!< Disable shortcut */
10864 #define TIMER_SHORTS_COMPARE0_CLEAR_Enabled (1UL) /*!< Enable shortcut */
10865 
10866 /* Register: TIMER_INTENSET */
10867 /* Description: Enable interrupt */
10868 
10869 /* Bit 21 : Write '1' to Enable interrupt for COMPARE[5] event */
10870 #define TIMER_INTENSET_COMPARE5_Pos (21UL) /*!< Position of COMPARE5 field. */
10871 #define TIMER_INTENSET_COMPARE5_Msk (0x1UL << TIMER_INTENSET_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */
10872 #define TIMER_INTENSET_COMPARE5_Disabled (0UL) /*!< Read: Disabled */
10873 #define TIMER_INTENSET_COMPARE5_Enabled (1UL) /*!< Read: Enabled */
10874 #define TIMER_INTENSET_COMPARE5_Set (1UL) /*!< Enable */
10875 
10876 /* Bit 20 : Write '1' to Enable interrupt for COMPARE[4] event */
10877 #define TIMER_INTENSET_COMPARE4_Pos (20UL) /*!< Position of COMPARE4 field. */
10878 #define TIMER_INTENSET_COMPARE4_Msk (0x1UL << TIMER_INTENSET_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */
10879 #define TIMER_INTENSET_COMPARE4_Disabled (0UL) /*!< Read: Disabled */
10880 #define TIMER_INTENSET_COMPARE4_Enabled (1UL) /*!< Read: Enabled */
10881 #define TIMER_INTENSET_COMPARE4_Set (1UL) /*!< Enable */
10882 
10883 /* Bit 19 : Write '1' to Enable interrupt for COMPARE[3] event */
10884 #define TIMER_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
10885 #define TIMER_INTENSET_COMPARE3_Msk (0x1UL << TIMER_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
10886 #define TIMER_INTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
10887 #define TIMER_INTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
10888 #define TIMER_INTENSET_COMPARE3_Set (1UL) /*!< Enable */
10889 
10890 /* Bit 18 : Write '1' to Enable interrupt for COMPARE[2] event */
10891 #define TIMER_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
10892 #define TIMER_INTENSET_COMPARE2_Msk (0x1UL << TIMER_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
10893 #define TIMER_INTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
10894 #define TIMER_INTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
10895 #define TIMER_INTENSET_COMPARE2_Set (1UL) /*!< Enable */
10896 
10897 /* Bit 17 : Write '1' to Enable interrupt for COMPARE[1] event */
10898 #define TIMER_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
10899 #define TIMER_INTENSET_COMPARE1_Msk (0x1UL << TIMER_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
10900 #define TIMER_INTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
10901 #define TIMER_INTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
10902 #define TIMER_INTENSET_COMPARE1_Set (1UL) /*!< Enable */
10903 
10904 /* Bit 16 : Write '1' to Enable interrupt for COMPARE[0] event */
10905 #define TIMER_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
10906 #define TIMER_INTENSET_COMPARE0_Msk (0x1UL << TIMER_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
10907 #define TIMER_INTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
10908 #define TIMER_INTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
10909 #define TIMER_INTENSET_COMPARE0_Set (1UL) /*!< Enable */
10910 
10911 /* Register: TIMER_INTENCLR */
10912 /* Description: Disable interrupt */
10913 
10914 /* Bit 21 : Write '1' to Disable interrupt for COMPARE[5] event */
10915 #define TIMER_INTENCLR_COMPARE5_Pos (21UL) /*!< Position of COMPARE5 field. */
10916 #define TIMER_INTENCLR_COMPARE5_Msk (0x1UL << TIMER_INTENCLR_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */
10917 #define TIMER_INTENCLR_COMPARE5_Disabled (0UL) /*!< Read: Disabled */
10918 #define TIMER_INTENCLR_COMPARE5_Enabled (1UL) /*!< Read: Enabled */
10919 #define TIMER_INTENCLR_COMPARE5_Clear (1UL) /*!< Disable */
10920 
10921 /* Bit 20 : Write '1' to Disable interrupt for COMPARE[4] event */
10922 #define TIMER_INTENCLR_COMPARE4_Pos (20UL) /*!< Position of COMPARE4 field. */
10923 #define TIMER_INTENCLR_COMPARE4_Msk (0x1UL << TIMER_INTENCLR_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */
10924 #define TIMER_INTENCLR_COMPARE4_Disabled (0UL) /*!< Read: Disabled */
10925 #define TIMER_INTENCLR_COMPARE4_Enabled (1UL) /*!< Read: Enabled */
10926 #define TIMER_INTENCLR_COMPARE4_Clear (1UL) /*!< Disable */
10927 
10928 /* Bit 19 : Write '1' to Disable interrupt for COMPARE[3] event */
10929 #define TIMER_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
10930 #define TIMER_INTENCLR_COMPARE3_Msk (0x1UL << TIMER_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
10931 #define TIMER_INTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
10932 #define TIMER_INTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
10933 #define TIMER_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable */
10934 
10935 /* Bit 18 : Write '1' to Disable interrupt for COMPARE[2] event */
10936 #define TIMER_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
10937 #define TIMER_INTENCLR_COMPARE2_Msk (0x1UL << TIMER_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
10938 #define TIMER_INTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
10939 #define TIMER_INTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
10940 #define TIMER_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable */
10941 
10942 /* Bit 17 : Write '1' to Disable interrupt for COMPARE[1] event */
10943 #define TIMER_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
10944 #define TIMER_INTENCLR_COMPARE1_Msk (0x1UL << TIMER_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
10945 #define TIMER_INTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
10946 #define TIMER_INTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
10947 #define TIMER_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable */
10948 
10949 /* Bit 16 : Write '1' to Disable interrupt for COMPARE[0] event */
10950 #define TIMER_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
10951 #define TIMER_INTENCLR_COMPARE0_Msk (0x1UL << TIMER_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
10952 #define TIMER_INTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
10953 #define TIMER_INTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
10954 #define TIMER_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable */
10955 
10956 /* Register: TIMER_MODE */
10957 /* Description: Timer mode selection */
10958 
10959 /* Bits 1..0 : Timer mode */
10960 #define TIMER_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
10961 #define TIMER_MODE_MODE_Msk (0x3UL << TIMER_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
10962 #define TIMER_MODE_MODE_Timer (0UL) /*!< Select Timer mode */
10963 #define TIMER_MODE_MODE_Counter (1UL) /*!< Deprecated enumerator -  Select Counter mode */
10964 #define TIMER_MODE_MODE_LowPowerCounter (2UL) /*!< Select Low Power Counter mode */
10965 
10966 /* Register: TIMER_BITMODE */
10967 /* Description: Configure the number of bits used by the TIMER */
10968 
10969 /* Bits 1..0 : Timer bit width */
10970 #define TIMER_BITMODE_BITMODE_Pos (0UL) /*!< Position of BITMODE field. */
10971 #define TIMER_BITMODE_BITMODE_Msk (0x3UL << TIMER_BITMODE_BITMODE_Pos) /*!< Bit mask of BITMODE field. */
10972 #define TIMER_BITMODE_BITMODE_16Bit (0UL) /*!< 16 bit timer bit width */
10973 #define TIMER_BITMODE_BITMODE_08Bit (1UL) /*!< 8 bit timer bit width */
10974 #define TIMER_BITMODE_BITMODE_24Bit (2UL) /*!< 24 bit timer bit width */
10975 #define TIMER_BITMODE_BITMODE_32Bit (3UL) /*!< 32 bit timer bit width */
10976 
10977 /* Register: TIMER_PRESCALER */
10978 /* Description: Timer prescaler register */
10979 
10980 /* Bits 3..0 : Prescaler value */
10981 #define TIMER_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */
10982 #define TIMER_PRESCALER_PRESCALER_Msk (0xFUL << TIMER_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */
10983 
10984 /* Register: TIMER_CC */
10985 /* Description: Description collection[0]:  Capture/Compare register 0 */
10986 
10987 /* Bits 31..0 : Capture/Compare value */
10988 #define TIMER_CC_CC_Pos (0UL) /*!< Position of CC field. */
10989 #define TIMER_CC_CC_Msk (0xFFFFFFFFUL << TIMER_CC_CC_Pos) /*!< Bit mask of CC field. */
10990 
10991 
10992 /* Peripheral: TWI */
10993 /* Description: I2C compatible Two-Wire Interface 0 */
10994 
10995 /* Register: TWI_SHORTS */
10996 /* Description: Shortcut register */
10997 
10998 /* Bit 1 : Shortcut between BB event and STOP task */
10999 #define TWI_SHORTS_BB_STOP_Pos (1UL) /*!< Position of BB_STOP field. */
11000 #define TWI_SHORTS_BB_STOP_Msk (0x1UL << TWI_SHORTS_BB_STOP_Pos) /*!< Bit mask of BB_STOP field. */
11001 #define TWI_SHORTS_BB_STOP_Disabled (0UL) /*!< Disable shortcut */
11002 #define TWI_SHORTS_BB_STOP_Enabled (1UL) /*!< Enable shortcut */
11003 
11004 /* Bit 0 : Shortcut between BB event and SUSPEND task */
11005 #define TWI_SHORTS_BB_SUSPEND_Pos (0UL) /*!< Position of BB_SUSPEND field. */
11006 #define TWI_SHORTS_BB_SUSPEND_Msk (0x1UL << TWI_SHORTS_BB_SUSPEND_Pos) /*!< Bit mask of BB_SUSPEND field. */
11007 #define TWI_SHORTS_BB_SUSPEND_Disabled (0UL) /*!< Disable shortcut */
11008 #define TWI_SHORTS_BB_SUSPEND_Enabled (1UL) /*!< Enable shortcut */
11009 
11010 /* Register: TWI_INTENSET */
11011 /* Description: Enable interrupt */
11012 
11013 /* Bit 18 : Write '1' to Enable interrupt for SUSPENDED event */
11014 #define TWI_INTENSET_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
11015 #define TWI_INTENSET_SUSPENDED_Msk (0x1UL << TWI_INTENSET_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
11016 #define TWI_INTENSET_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */
11017 #define TWI_INTENSET_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */
11018 #define TWI_INTENSET_SUSPENDED_Set (1UL) /*!< Enable */
11019 
11020 /* Bit 14 : Write '1' to Enable interrupt for BB event */
11021 #define TWI_INTENSET_BB_Pos (14UL) /*!< Position of BB field. */
11022 #define TWI_INTENSET_BB_Msk (0x1UL << TWI_INTENSET_BB_Pos) /*!< Bit mask of BB field. */
11023 #define TWI_INTENSET_BB_Disabled (0UL) /*!< Read: Disabled */
11024 #define TWI_INTENSET_BB_Enabled (1UL) /*!< Read: Enabled */
11025 #define TWI_INTENSET_BB_Set (1UL) /*!< Enable */
11026 
11027 /* Bit 9 : Write '1' to Enable interrupt for ERROR event */
11028 #define TWI_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
11029 #define TWI_INTENSET_ERROR_Msk (0x1UL << TWI_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
11030 #define TWI_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
11031 #define TWI_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
11032 #define TWI_INTENSET_ERROR_Set (1UL) /*!< Enable */
11033 
11034 /* Bit 7 : Write '1' to Enable interrupt for TXDSENT event */
11035 #define TWI_INTENSET_TXDSENT_Pos (7UL) /*!< Position of TXDSENT field. */
11036 #define TWI_INTENSET_TXDSENT_Msk (0x1UL << TWI_INTENSET_TXDSENT_Pos) /*!< Bit mask of TXDSENT field. */
11037 #define TWI_INTENSET_TXDSENT_Disabled (0UL) /*!< Read: Disabled */
11038 #define TWI_INTENSET_TXDSENT_Enabled (1UL) /*!< Read: Enabled */
11039 #define TWI_INTENSET_TXDSENT_Set (1UL) /*!< Enable */
11040 
11041 /* Bit 2 : Write '1' to Enable interrupt for RXDREADY event */
11042 #define TWI_INTENSET_RXDREADY_Pos (2UL) /*!< Position of RXDREADY field. */
11043 #define TWI_INTENSET_RXDREADY_Msk (0x1UL << TWI_INTENSET_RXDREADY_Pos) /*!< Bit mask of RXDREADY field. */
11044 #define TWI_INTENSET_RXDREADY_Disabled (0UL) /*!< Read: Disabled */
11045 #define TWI_INTENSET_RXDREADY_Enabled (1UL) /*!< Read: Enabled */
11046 #define TWI_INTENSET_RXDREADY_Set (1UL) /*!< Enable */
11047 
11048 /* Bit 1 : Write '1' to Enable interrupt for STOPPED event */
11049 #define TWI_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
11050 #define TWI_INTENSET_STOPPED_Msk (0x1UL << TWI_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
11051 #define TWI_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
11052 #define TWI_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
11053 #define TWI_INTENSET_STOPPED_Set (1UL) /*!< Enable */
11054 
11055 /* Register: TWI_INTENCLR */
11056 /* Description: Disable interrupt */
11057 
11058 /* Bit 18 : Write '1' to Disable interrupt for SUSPENDED event */
11059 #define TWI_INTENCLR_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
11060 #define TWI_INTENCLR_SUSPENDED_Msk (0x1UL << TWI_INTENCLR_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
11061 #define TWI_INTENCLR_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */
11062 #define TWI_INTENCLR_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */
11063 #define TWI_INTENCLR_SUSPENDED_Clear (1UL) /*!< Disable */
11064 
11065 /* Bit 14 : Write '1' to Disable interrupt for BB event */
11066 #define TWI_INTENCLR_BB_Pos (14UL) /*!< Position of BB field. */
11067 #define TWI_INTENCLR_BB_Msk (0x1UL << TWI_INTENCLR_BB_Pos) /*!< Bit mask of BB field. */
11068 #define TWI_INTENCLR_BB_Disabled (0UL) /*!< Read: Disabled */
11069 #define TWI_INTENCLR_BB_Enabled (1UL) /*!< Read: Enabled */
11070 #define TWI_INTENCLR_BB_Clear (1UL) /*!< Disable */
11071 
11072 /* Bit 9 : Write '1' to Disable interrupt for ERROR event */
11073 #define TWI_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
11074 #define TWI_INTENCLR_ERROR_Msk (0x1UL << TWI_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
11075 #define TWI_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
11076 #define TWI_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
11077 #define TWI_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
11078 
11079 /* Bit 7 : Write '1' to Disable interrupt for TXDSENT event */
11080 #define TWI_INTENCLR_TXDSENT_Pos (7UL) /*!< Position of TXDSENT field. */
11081 #define TWI_INTENCLR_TXDSENT_Msk (0x1UL << TWI_INTENCLR_TXDSENT_Pos) /*!< Bit mask of TXDSENT field. */
11082 #define TWI_INTENCLR_TXDSENT_Disabled (0UL) /*!< Read: Disabled */
11083 #define TWI_INTENCLR_TXDSENT_Enabled (1UL) /*!< Read: Enabled */
11084 #define TWI_INTENCLR_TXDSENT_Clear (1UL) /*!< Disable */
11085 
11086 /* Bit 2 : Write '1' to Disable interrupt for RXDREADY event */
11087 #define TWI_INTENCLR_RXDREADY_Pos (2UL) /*!< Position of RXDREADY field. */
11088 #define TWI_INTENCLR_RXDREADY_Msk (0x1UL << TWI_INTENCLR_RXDREADY_Pos) /*!< Bit mask of RXDREADY field. */
11089 #define TWI_INTENCLR_RXDREADY_Disabled (0UL) /*!< Read: Disabled */
11090 #define TWI_INTENCLR_RXDREADY_Enabled (1UL) /*!< Read: Enabled */
11091 #define TWI_INTENCLR_RXDREADY_Clear (1UL) /*!< Disable */
11092 
11093 /* Bit 1 : Write '1' to Disable interrupt for STOPPED event */
11094 #define TWI_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
11095 #define TWI_INTENCLR_STOPPED_Msk (0x1UL << TWI_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
11096 #define TWI_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
11097 #define TWI_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
11098 #define TWI_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
11099 
11100 /* Register: TWI_ERRORSRC */
11101 /* Description: Error source */
11102 
11103 /* Bit 2 : NACK received after sending a data byte (write '1' to clear) */
11104 #define TWI_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */
11105 #define TWI_ERRORSRC_DNACK_Msk (0x1UL << TWI_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */
11106 #define TWI_ERRORSRC_DNACK_NotPresent (0UL) /*!< Read: error not present */
11107 #define TWI_ERRORSRC_DNACK_Present (1UL) /*!< Read: error present */
11108 #define TWI_ERRORSRC_DNACK_Clear (1UL) /*!< Write: clear error on writing '1' */
11109 
11110 /* Bit 1 : NACK received after sending the address (write '1' to clear) */
11111 #define TWI_ERRORSRC_ANACK_Pos (1UL) /*!< Position of ANACK field. */
11112 #define TWI_ERRORSRC_ANACK_Msk (0x1UL << TWI_ERRORSRC_ANACK_Pos) /*!< Bit mask of ANACK field. */
11113 #define TWI_ERRORSRC_ANACK_NotPresent (0UL) /*!< Read: error not present */
11114 #define TWI_ERRORSRC_ANACK_Present (1UL) /*!< Read: error present */
11115 #define TWI_ERRORSRC_ANACK_Clear (1UL) /*!< Write: clear error on writing '1' */
11116 
11117 /* Bit 0 : Overrun error */
11118 #define TWI_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */
11119 #define TWI_ERRORSRC_OVERRUN_Msk (0x1UL << TWI_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */
11120 #define TWI_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Read: no overrun occured */
11121 #define TWI_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: overrun occured */
11122 #define TWI_ERRORSRC_OVERRUN_Clear (1UL) /*!< Write: clear error on writing '1' */
11123 
11124 /* Register: TWI_ENABLE */
11125 /* Description: Enable TWI */
11126 
11127 /* Bits 3..0 : Enable or disable TWI */
11128 #define TWI_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
11129 #define TWI_ENABLE_ENABLE_Msk (0xFUL << TWI_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
11130 #define TWI_ENABLE_ENABLE_Disabled (0UL) /*!< Disable TWI */
11131 #define TWI_ENABLE_ENABLE_Enabled (5UL) /*!< Enable TWI */
11132 
11133 /* Register: TWI_PSELSCL */
11134 /* Description: Pin select for SCL */
11135 
11136 /* Bits 31..0 : Pin number configuration for TWI SCL signal */
11137 #define TWI_PSELSCL_PSELSCL_Pos (0UL) /*!< Position of PSELSCL field. */
11138 #define TWI_PSELSCL_PSELSCL_Msk (0xFFFFFFFFUL << TWI_PSELSCL_PSELSCL_Pos) /*!< Bit mask of PSELSCL field. */
11139 #define TWI_PSELSCL_PSELSCL_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */
11140 
11141 /* Register: TWI_PSELSDA */
11142 /* Description: Pin select for SDA */
11143 
11144 /* Bits 31..0 : Pin number configuration for TWI SDA signal */
11145 #define TWI_PSELSDA_PSELSDA_Pos (0UL) /*!< Position of PSELSDA field. */
11146 #define TWI_PSELSDA_PSELSDA_Msk (0xFFFFFFFFUL << TWI_PSELSDA_PSELSDA_Pos) /*!< Bit mask of PSELSDA field. */
11147 #define TWI_PSELSDA_PSELSDA_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */
11148 
11149 /* Register: TWI_RXD */
11150 /* Description: RXD register */
11151 
11152 /* Bits 7..0 : RXD register */
11153 #define TWI_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */
11154 #define TWI_RXD_RXD_Msk (0xFFUL << TWI_RXD_RXD_Pos) /*!< Bit mask of RXD field. */
11155 
11156 /* Register: TWI_TXD */
11157 /* Description: TXD register */
11158 
11159 /* Bits 7..0 : TXD register */
11160 #define TWI_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */
11161 #define TWI_TXD_TXD_Msk (0xFFUL << TWI_TXD_TXD_Pos) /*!< Bit mask of TXD field. */
11162 
11163 /* Register: TWI_FREQUENCY */
11164 /* Description: TWI frequency */
11165 
11166 /* Bits 31..0 : TWI master clock frequency */
11167 #define TWI_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
11168 #define TWI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << TWI_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
11169 #define TWI_FREQUENCY_FREQUENCY_K100 (0x01980000UL) /*!< 100 kbps */
11170 #define TWI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */
11171 #define TWI_FREQUENCY_FREQUENCY_K400 (0x06680000UL) /*!< 400 kbps (actual rate 410.256 kbps) */
11172 
11173 /* Register: TWI_ADDRESS */
11174 /* Description: Address used in the TWI transfer */
11175 
11176 /* Bits 6..0 : Address used in the TWI transfer */
11177 #define TWI_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */
11178 #define TWI_ADDRESS_ADDRESS_Msk (0x7FUL << TWI_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
11179 
11180 
11181 /* Peripheral: TWIM */
11182 /* Description: I2C compatible Two-Wire Master Interface with EasyDMA 0 */
11183 
11184 /* Register: TWIM_SHORTS */
11185 /* Description: Shortcut register */
11186 
11187 /* Bit 12 : Shortcut between LASTRX event and STOP task */
11188 #define TWIM_SHORTS_LASTRX_STOP_Pos (12UL) /*!< Position of LASTRX_STOP field. */
11189 #define TWIM_SHORTS_LASTRX_STOP_Msk (0x1UL << TWIM_SHORTS_LASTRX_STOP_Pos) /*!< Bit mask of LASTRX_STOP field. */
11190 #define TWIM_SHORTS_LASTRX_STOP_Disabled (0UL) /*!< Disable shortcut */
11191 #define TWIM_SHORTS_LASTRX_STOP_Enabled (1UL) /*!< Enable shortcut */
11192 
11193 /* Bit 10 : Shortcut between LASTRX event and STARTTX task */
11194 #define TWIM_SHORTS_LASTRX_STARTTX_Pos (10UL) /*!< Position of LASTRX_STARTTX field. */
11195 #define TWIM_SHORTS_LASTRX_STARTTX_Msk (0x1UL << TWIM_SHORTS_LASTRX_STARTTX_Pos) /*!< Bit mask of LASTRX_STARTTX field. */
11196 #define TWIM_SHORTS_LASTRX_STARTTX_Disabled (0UL) /*!< Disable shortcut */
11197 #define TWIM_SHORTS_LASTRX_STARTTX_Enabled (1UL) /*!< Enable shortcut */
11198 
11199 /* Bit 9 : Shortcut between LASTTX event and STOP task */
11200 #define TWIM_SHORTS_LASTTX_STOP_Pos (9UL) /*!< Position of LASTTX_STOP field. */
11201 #define TWIM_SHORTS_LASTTX_STOP_Msk (0x1UL << TWIM_SHORTS_LASTTX_STOP_Pos) /*!< Bit mask of LASTTX_STOP field. */
11202 #define TWIM_SHORTS_LASTTX_STOP_Disabled (0UL) /*!< Disable shortcut */
11203 #define TWIM_SHORTS_LASTTX_STOP_Enabled (1UL) /*!< Enable shortcut */
11204 
11205 /* Bit 8 : Shortcut between LASTTX event and SUSPEND task */
11206 #define TWIM_SHORTS_LASTTX_SUSPEND_Pos (8UL) /*!< Position of LASTTX_SUSPEND field. */
11207 #define TWIM_SHORTS_LASTTX_SUSPEND_Msk (0x1UL << TWIM_SHORTS_LASTTX_SUSPEND_Pos) /*!< Bit mask of LASTTX_SUSPEND field. */
11208 #define TWIM_SHORTS_LASTTX_SUSPEND_Disabled (0UL) /*!< Disable shortcut */
11209 #define TWIM_SHORTS_LASTTX_SUSPEND_Enabled (1UL) /*!< Enable shortcut */
11210 
11211 /* Bit 7 : Shortcut between LASTTX event and STARTRX task */
11212 #define TWIM_SHORTS_LASTTX_STARTRX_Pos (7UL) /*!< Position of LASTTX_STARTRX field. */
11213 #define TWIM_SHORTS_LASTTX_STARTRX_Msk (0x1UL << TWIM_SHORTS_LASTTX_STARTRX_Pos) /*!< Bit mask of LASTTX_STARTRX field. */
11214 #define TWIM_SHORTS_LASTTX_STARTRX_Disabled (0UL) /*!< Disable shortcut */
11215 #define TWIM_SHORTS_LASTTX_STARTRX_Enabled (1UL) /*!< Enable shortcut */
11216 
11217 /* Register: TWIM_INTEN */
11218 /* Description: Enable or disable interrupt */
11219 
11220 /* Bit 24 : Enable or disable interrupt for LASTTX event */
11221 #define TWIM_INTEN_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */
11222 #define TWIM_INTEN_LASTTX_Msk (0x1UL << TWIM_INTEN_LASTTX_Pos) /*!< Bit mask of LASTTX field. */
11223 #define TWIM_INTEN_LASTTX_Disabled (0UL) /*!< Disable */
11224 #define TWIM_INTEN_LASTTX_Enabled (1UL) /*!< Enable */
11225 
11226 /* Bit 23 : Enable or disable interrupt for LASTRX event */
11227 #define TWIM_INTEN_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */
11228 #define TWIM_INTEN_LASTRX_Msk (0x1UL << TWIM_INTEN_LASTRX_Pos) /*!< Bit mask of LASTRX field. */
11229 #define TWIM_INTEN_LASTRX_Disabled (0UL) /*!< Disable */
11230 #define TWIM_INTEN_LASTRX_Enabled (1UL) /*!< Enable */
11231 
11232 /* Bit 20 : Enable or disable interrupt for TXSTARTED event */
11233 #define TWIM_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
11234 #define TWIM_INTEN_TXSTARTED_Msk (0x1UL << TWIM_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
11235 #define TWIM_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */
11236 #define TWIM_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */
11237 
11238 /* Bit 19 : Enable or disable interrupt for RXSTARTED event */
11239 #define TWIM_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
11240 #define TWIM_INTEN_RXSTARTED_Msk (0x1UL << TWIM_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
11241 #define TWIM_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */
11242 #define TWIM_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */
11243 
11244 /* Bit 18 : Enable or disable interrupt for SUSPENDED event */
11245 #define TWIM_INTEN_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
11246 #define TWIM_INTEN_SUSPENDED_Msk (0x1UL << TWIM_INTEN_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
11247 #define TWIM_INTEN_SUSPENDED_Disabled (0UL) /*!< Disable */
11248 #define TWIM_INTEN_SUSPENDED_Enabled (1UL) /*!< Enable */
11249 
11250 /* Bit 9 : Enable or disable interrupt for ERROR event */
11251 #define TWIM_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */
11252 #define TWIM_INTEN_ERROR_Msk (0x1UL << TWIM_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */
11253 #define TWIM_INTEN_ERROR_Disabled (0UL) /*!< Disable */
11254 #define TWIM_INTEN_ERROR_Enabled (1UL) /*!< Enable */
11255 
11256 /* Bit 1 : Enable or disable interrupt for STOPPED event */
11257 #define TWIM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
11258 #define TWIM_INTEN_STOPPED_Msk (0x1UL << TWIM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
11259 #define TWIM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
11260 #define TWIM_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
11261 
11262 /* Register: TWIM_INTENSET */
11263 /* Description: Enable interrupt */
11264 
11265 /* Bit 24 : Write '1' to Enable interrupt for LASTTX event */
11266 #define TWIM_INTENSET_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */
11267 #define TWIM_INTENSET_LASTTX_Msk (0x1UL << TWIM_INTENSET_LASTTX_Pos) /*!< Bit mask of LASTTX field. */
11268 #define TWIM_INTENSET_LASTTX_Disabled (0UL) /*!< Read: Disabled */
11269 #define TWIM_INTENSET_LASTTX_Enabled (1UL) /*!< Read: Enabled */
11270 #define TWIM_INTENSET_LASTTX_Set (1UL) /*!< Enable */
11271 
11272 /* Bit 23 : Write '1' to Enable interrupt for LASTRX event */
11273 #define TWIM_INTENSET_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */
11274 #define TWIM_INTENSET_LASTRX_Msk (0x1UL << TWIM_INTENSET_LASTRX_Pos) /*!< Bit mask of LASTRX field. */
11275 #define TWIM_INTENSET_LASTRX_Disabled (0UL) /*!< Read: Disabled */
11276 #define TWIM_INTENSET_LASTRX_Enabled (1UL) /*!< Read: Enabled */
11277 #define TWIM_INTENSET_LASTRX_Set (1UL) /*!< Enable */
11278 
11279 /* Bit 20 : Write '1' to Enable interrupt for TXSTARTED event */
11280 #define TWIM_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
11281 #define TWIM_INTENSET_TXSTARTED_Msk (0x1UL << TWIM_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
11282 #define TWIM_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
11283 #define TWIM_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
11284 #define TWIM_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */
11285 
11286 /* Bit 19 : Write '1' to Enable interrupt for RXSTARTED event */
11287 #define TWIM_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
11288 #define TWIM_INTENSET_RXSTARTED_Msk (0x1UL << TWIM_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
11289 #define TWIM_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
11290 #define TWIM_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
11291 #define TWIM_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */
11292 
11293 /* Bit 18 : Write '1' to Enable interrupt for SUSPENDED event */
11294 #define TWIM_INTENSET_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
11295 #define TWIM_INTENSET_SUSPENDED_Msk (0x1UL << TWIM_INTENSET_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
11296 #define TWIM_INTENSET_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */
11297 #define TWIM_INTENSET_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */
11298 #define TWIM_INTENSET_SUSPENDED_Set (1UL) /*!< Enable */
11299 
11300 /* Bit 9 : Write '1' to Enable interrupt for ERROR event */
11301 #define TWIM_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
11302 #define TWIM_INTENSET_ERROR_Msk (0x1UL << TWIM_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
11303 #define TWIM_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
11304 #define TWIM_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
11305 #define TWIM_INTENSET_ERROR_Set (1UL) /*!< Enable */
11306 
11307 /* Bit 1 : Write '1' to Enable interrupt for STOPPED event */
11308 #define TWIM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
11309 #define TWIM_INTENSET_STOPPED_Msk (0x1UL << TWIM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
11310 #define TWIM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
11311 #define TWIM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
11312 #define TWIM_INTENSET_STOPPED_Set (1UL) /*!< Enable */
11313 
11314 /* Register: TWIM_INTENCLR */
11315 /* Description: Disable interrupt */
11316 
11317 /* Bit 24 : Write '1' to Disable interrupt for LASTTX event */
11318 #define TWIM_INTENCLR_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */
11319 #define TWIM_INTENCLR_LASTTX_Msk (0x1UL << TWIM_INTENCLR_LASTTX_Pos) /*!< Bit mask of LASTTX field. */
11320 #define TWIM_INTENCLR_LASTTX_Disabled (0UL) /*!< Read: Disabled */
11321 #define TWIM_INTENCLR_LASTTX_Enabled (1UL) /*!< Read: Enabled */
11322 #define TWIM_INTENCLR_LASTTX_Clear (1UL) /*!< Disable */
11323 
11324 /* Bit 23 : Write '1' to Disable interrupt for LASTRX event */
11325 #define TWIM_INTENCLR_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */
11326 #define TWIM_INTENCLR_LASTRX_Msk (0x1UL << TWIM_INTENCLR_LASTRX_Pos) /*!< Bit mask of LASTRX field. */
11327 #define TWIM_INTENCLR_LASTRX_Disabled (0UL) /*!< Read: Disabled */
11328 #define TWIM_INTENCLR_LASTRX_Enabled (1UL) /*!< Read: Enabled */
11329 #define TWIM_INTENCLR_LASTRX_Clear (1UL) /*!< Disable */
11330 
11331 /* Bit 20 : Write '1' to Disable interrupt for TXSTARTED event */
11332 #define TWIM_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
11333 #define TWIM_INTENCLR_TXSTARTED_Msk (0x1UL << TWIM_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
11334 #define TWIM_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
11335 #define TWIM_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
11336 #define TWIM_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */
11337 
11338 /* Bit 19 : Write '1' to Disable interrupt for RXSTARTED event */
11339 #define TWIM_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
11340 #define TWIM_INTENCLR_RXSTARTED_Msk (0x1UL << TWIM_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
11341 #define TWIM_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
11342 #define TWIM_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
11343 #define TWIM_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */
11344 
11345 /* Bit 18 : Write '1' to Disable interrupt for SUSPENDED event */
11346 #define TWIM_INTENCLR_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
11347 #define TWIM_INTENCLR_SUSPENDED_Msk (0x1UL << TWIM_INTENCLR_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
11348 #define TWIM_INTENCLR_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */
11349 #define TWIM_INTENCLR_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */
11350 #define TWIM_INTENCLR_SUSPENDED_Clear (1UL) /*!< Disable */
11351 
11352 /* Bit 9 : Write '1' to Disable interrupt for ERROR event */
11353 #define TWIM_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
11354 #define TWIM_INTENCLR_ERROR_Msk (0x1UL << TWIM_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
11355 #define TWIM_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
11356 #define TWIM_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
11357 #define TWIM_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
11358 
11359 /* Bit 1 : Write '1' to Disable interrupt for STOPPED event */
11360 #define TWIM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
11361 #define TWIM_INTENCLR_STOPPED_Msk (0x1UL << TWIM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
11362 #define TWIM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
11363 #define TWIM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
11364 #define TWIM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
11365 
11366 /* Register: TWIM_ERRORSRC */
11367 /* Description: Error source */
11368 
11369 /* Bit 2 : NACK received after sending a data byte (write '1' to clear) */
11370 #define TWIM_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */
11371 #define TWIM_ERRORSRC_DNACK_Msk (0x1UL << TWIM_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */
11372 #define TWIM_ERRORSRC_DNACK_NotReceived (0UL) /*!< Error did not occur */
11373 #define TWIM_ERRORSRC_DNACK_Received (1UL) /*!< Error occurred */
11374 
11375 /* Bit 1 : NACK received after sending the address (write '1' to clear) */
11376 #define TWIM_ERRORSRC_ANACK_Pos (1UL) /*!< Position of ANACK field. */
11377 #define TWIM_ERRORSRC_ANACK_Msk (0x1UL << TWIM_ERRORSRC_ANACK_Pos) /*!< Bit mask of ANACK field. */
11378 #define TWIM_ERRORSRC_ANACK_NotReceived (0UL) /*!< Error did not occur */
11379 #define TWIM_ERRORSRC_ANACK_Received (1UL) /*!< Error occurred */
11380 
11381 /* Bit 0 : Overrun error */
11382 #define TWIM_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */
11383 #define TWIM_ERRORSRC_OVERRUN_Msk (0x1UL << TWIM_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */
11384 #define TWIM_ERRORSRC_OVERRUN_NotReceived (0UL) /*!< Error did not occur */
11385 #define TWIM_ERRORSRC_OVERRUN_Received (1UL) /*!< Error occurred */
11386 
11387 /* Register: TWIM_ENABLE */
11388 /* Description: Enable TWIM */
11389 
11390 /* Bits 3..0 : Enable or disable TWIM */
11391 #define TWIM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
11392 #define TWIM_ENABLE_ENABLE_Msk (0xFUL << TWIM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
11393 #define TWIM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable TWIM */
11394 #define TWIM_ENABLE_ENABLE_Enabled (6UL) /*!< Enable TWIM */
11395 
11396 /* Register: TWIM_PSEL_SCL */
11397 /* Description: Pin select for SCL signal */
11398 
11399 /* Bit 31 : Connection */
11400 #define TWIM_PSEL_SCL_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
11401 #define TWIM_PSEL_SCL_CONNECT_Msk (0x1UL << TWIM_PSEL_SCL_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
11402 #define TWIM_PSEL_SCL_CONNECT_Connected (0UL) /*!< Connect */
11403 #define TWIM_PSEL_SCL_CONNECT_Disconnected (1UL) /*!< Disconnect */
11404 
11405 /* Bits 4..0 : Pin number */
11406 #define TWIM_PSEL_SCL_PIN_Pos (0UL) /*!< Position of PIN field. */
11407 #define TWIM_PSEL_SCL_PIN_Msk (0x1FUL << TWIM_PSEL_SCL_PIN_Pos) /*!< Bit mask of PIN field. */
11408 
11409 /* Register: TWIM_PSEL_SDA */
11410 /* Description: Pin select for SDA signal */
11411 
11412 /* Bit 31 : Connection */
11413 #define TWIM_PSEL_SDA_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
11414 #define TWIM_PSEL_SDA_CONNECT_Msk (0x1UL << TWIM_PSEL_SDA_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
11415 #define TWIM_PSEL_SDA_CONNECT_Connected (0UL) /*!< Connect */
11416 #define TWIM_PSEL_SDA_CONNECT_Disconnected (1UL) /*!< Disconnect */
11417 
11418 /* Bits 4..0 : Pin number */
11419 #define TWIM_PSEL_SDA_PIN_Pos (0UL) /*!< Position of PIN field. */
11420 #define TWIM_PSEL_SDA_PIN_Msk (0x1FUL << TWIM_PSEL_SDA_PIN_Pos) /*!< Bit mask of PIN field. */
11421 
11422 /* Register: TWIM_FREQUENCY */
11423 /* Description: TWI frequency */
11424 
11425 /* Bits 31..0 : TWI master clock frequency */
11426 #define TWIM_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
11427 #define TWIM_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << TWIM_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
11428 #define TWIM_FREQUENCY_FREQUENCY_K100 (0x01980000UL) /*!< 100 kbps */
11429 #define TWIM_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */
11430 #define TWIM_FREQUENCY_FREQUENCY_K400 (0x06400000UL) /*!< 400 kbps */
11431 
11432 /* Register: TWIM_RXD_PTR */
11433 /* Description: Data pointer */
11434 
11435 /* Bits 31..0 : Data pointer */
11436 #define TWIM_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
11437 #define TWIM_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIM_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
11438 
11439 /* Register: TWIM_RXD_MAXCNT */
11440 /* Description: Maximum number of bytes in receive buffer */
11441 
11442 /* Bits 7..0 : Maximum number of bytes in receive buffer */
11443 #define TWIM_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
11444 #define TWIM_RXD_MAXCNT_MAXCNT_Msk (0xFFUL << TWIM_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
11445 
11446 /* Register: TWIM_RXD_AMOUNT */
11447 /* Description: Number of bytes transferred in the last transaction */
11448 
11449 /* Bits 7..0 : Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. */
11450 #define TWIM_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
11451 #define TWIM_RXD_AMOUNT_AMOUNT_Msk (0xFFUL << TWIM_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
11452 
11453 /* Register: TWIM_RXD_LIST */
11454 /* Description: EasyDMA list type */
11455 
11456 /* Bits 2..0 : List type */
11457 #define TWIM_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
11458 #define TWIM_RXD_LIST_LIST_Msk (0x7UL << TWIM_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
11459 #define TWIM_RXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
11460 #define TWIM_RXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
11461 
11462 /* Register: TWIM_TXD_PTR */
11463 /* Description: Data pointer */
11464 
11465 /* Bits 31..0 : Data pointer */
11466 #define TWIM_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
11467 #define TWIM_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIM_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
11468 
11469 /* Register: TWIM_TXD_MAXCNT */
11470 /* Description: Maximum number of bytes in transmit buffer */
11471 
11472 /* Bits 7..0 : Maximum number of bytes in transmit buffer */
11473 #define TWIM_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
11474 #define TWIM_TXD_MAXCNT_MAXCNT_Msk (0xFFUL << TWIM_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
11475 
11476 /* Register: TWIM_TXD_AMOUNT */
11477 /* Description: Number of bytes transferred in the last transaction */
11478 
11479 /* Bits 7..0 : Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. */
11480 #define TWIM_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
11481 #define TWIM_TXD_AMOUNT_AMOUNT_Msk (0xFFUL << TWIM_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
11482 
11483 /* Register: TWIM_TXD_LIST */
11484 /* Description: EasyDMA list type */
11485 
11486 /* Bits 2..0 : List type */
11487 #define TWIM_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
11488 #define TWIM_TXD_LIST_LIST_Msk (0x7UL << TWIM_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
11489 #define TWIM_TXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
11490 #define TWIM_TXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
11491 
11492 /* Register: TWIM_ADDRESS */
11493 /* Description: Address used in the TWI transfer */
11494 
11495 /* Bits 6..0 : Address used in the TWI transfer */
11496 #define TWIM_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */
11497 #define TWIM_ADDRESS_ADDRESS_Msk (0x7FUL << TWIM_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
11498 
11499 
11500 /* Peripheral: TWIS */
11501 /* Description: I2C compatible Two-Wire Slave Interface with EasyDMA 0 */
11502 
11503 /* Register: TWIS_SHORTS */
11504 /* Description: Shortcut register */
11505 
11506 /* Bit 14 : Shortcut between READ event and SUSPEND task */
11507 #define TWIS_SHORTS_READ_SUSPEND_Pos (14UL) /*!< Position of READ_SUSPEND field. */
11508 #define TWIS_SHORTS_READ_SUSPEND_Msk (0x1UL << TWIS_SHORTS_READ_SUSPEND_Pos) /*!< Bit mask of READ_SUSPEND field. */
11509 #define TWIS_SHORTS_READ_SUSPEND_Disabled (0UL) /*!< Disable shortcut */
11510 #define TWIS_SHORTS_READ_SUSPEND_Enabled (1UL) /*!< Enable shortcut */
11511 
11512 /* Bit 13 : Shortcut between WRITE event and SUSPEND task */
11513 #define TWIS_SHORTS_WRITE_SUSPEND_Pos (13UL) /*!< Position of WRITE_SUSPEND field. */
11514 #define TWIS_SHORTS_WRITE_SUSPEND_Msk (0x1UL << TWIS_SHORTS_WRITE_SUSPEND_Pos) /*!< Bit mask of WRITE_SUSPEND field. */
11515 #define TWIS_SHORTS_WRITE_SUSPEND_Disabled (0UL) /*!< Disable shortcut */
11516 #define TWIS_SHORTS_WRITE_SUSPEND_Enabled (1UL) /*!< Enable shortcut */
11517 
11518 /* Register: TWIS_INTEN */
11519 /* Description: Enable or disable interrupt */
11520 
11521 /* Bit 26 : Enable or disable interrupt for READ event */
11522 #define TWIS_INTEN_READ_Pos (26UL) /*!< Position of READ field. */
11523 #define TWIS_INTEN_READ_Msk (0x1UL << TWIS_INTEN_READ_Pos) /*!< Bit mask of READ field. */
11524 #define TWIS_INTEN_READ_Disabled (0UL) /*!< Disable */
11525 #define TWIS_INTEN_READ_Enabled (1UL) /*!< Enable */
11526 
11527 /* Bit 25 : Enable or disable interrupt for WRITE event */
11528 #define TWIS_INTEN_WRITE_Pos (25UL) /*!< Position of WRITE field. */
11529 #define TWIS_INTEN_WRITE_Msk (0x1UL << TWIS_INTEN_WRITE_Pos) /*!< Bit mask of WRITE field. */
11530 #define TWIS_INTEN_WRITE_Disabled (0UL) /*!< Disable */
11531 #define TWIS_INTEN_WRITE_Enabled (1UL) /*!< Enable */
11532 
11533 /* Bit 20 : Enable or disable interrupt for TXSTARTED event */
11534 #define TWIS_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
11535 #define TWIS_INTEN_TXSTARTED_Msk (0x1UL << TWIS_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
11536 #define TWIS_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */
11537 #define TWIS_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */
11538 
11539 /* Bit 19 : Enable or disable interrupt for RXSTARTED event */
11540 #define TWIS_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
11541 #define TWIS_INTEN_RXSTARTED_Msk (0x1UL << TWIS_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
11542 #define TWIS_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */
11543 #define TWIS_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */
11544 
11545 /* Bit 9 : Enable or disable interrupt for ERROR event */
11546 #define TWIS_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */
11547 #define TWIS_INTEN_ERROR_Msk (0x1UL << TWIS_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */
11548 #define TWIS_INTEN_ERROR_Disabled (0UL) /*!< Disable */
11549 #define TWIS_INTEN_ERROR_Enabled (1UL) /*!< Enable */
11550 
11551 /* Bit 1 : Enable or disable interrupt for STOPPED event */
11552 #define TWIS_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
11553 #define TWIS_INTEN_STOPPED_Msk (0x1UL << TWIS_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
11554 #define TWIS_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
11555 #define TWIS_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
11556 
11557 /* Register: TWIS_INTENSET */
11558 /* Description: Enable interrupt */
11559 
11560 /* Bit 26 : Write '1' to Enable interrupt for READ event */
11561 #define TWIS_INTENSET_READ_Pos (26UL) /*!< Position of READ field. */
11562 #define TWIS_INTENSET_READ_Msk (0x1UL << TWIS_INTENSET_READ_Pos) /*!< Bit mask of READ field. */
11563 #define TWIS_INTENSET_READ_Disabled (0UL) /*!< Read: Disabled */
11564 #define TWIS_INTENSET_READ_Enabled (1UL) /*!< Read: Enabled */
11565 #define TWIS_INTENSET_READ_Set (1UL) /*!< Enable */
11566 
11567 /* Bit 25 : Write '1' to Enable interrupt for WRITE event */
11568 #define TWIS_INTENSET_WRITE_Pos (25UL) /*!< Position of WRITE field. */
11569 #define TWIS_INTENSET_WRITE_Msk (0x1UL << TWIS_INTENSET_WRITE_Pos) /*!< Bit mask of WRITE field. */
11570 #define TWIS_INTENSET_WRITE_Disabled (0UL) /*!< Read: Disabled */
11571 #define TWIS_INTENSET_WRITE_Enabled (1UL) /*!< Read: Enabled */
11572 #define TWIS_INTENSET_WRITE_Set (1UL) /*!< Enable */
11573 
11574 /* Bit 20 : Write '1' to Enable interrupt for TXSTARTED event */
11575 #define TWIS_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
11576 #define TWIS_INTENSET_TXSTARTED_Msk (0x1UL << TWIS_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
11577 #define TWIS_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
11578 #define TWIS_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
11579 #define TWIS_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */
11580 
11581 /* Bit 19 : Write '1' to Enable interrupt for RXSTARTED event */
11582 #define TWIS_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
11583 #define TWIS_INTENSET_RXSTARTED_Msk (0x1UL << TWIS_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
11584 #define TWIS_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
11585 #define TWIS_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
11586 #define TWIS_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */
11587 
11588 /* Bit 9 : Write '1' to Enable interrupt for ERROR event */
11589 #define TWIS_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
11590 #define TWIS_INTENSET_ERROR_Msk (0x1UL << TWIS_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
11591 #define TWIS_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
11592 #define TWIS_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
11593 #define TWIS_INTENSET_ERROR_Set (1UL) /*!< Enable */
11594 
11595 /* Bit 1 : Write '1' to Enable interrupt for STOPPED event */
11596 #define TWIS_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
11597 #define TWIS_INTENSET_STOPPED_Msk (0x1UL << TWIS_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
11598 #define TWIS_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
11599 #define TWIS_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
11600 #define TWIS_INTENSET_STOPPED_Set (1UL) /*!< Enable */
11601 
11602 /* Register: TWIS_INTENCLR */
11603 /* Description: Disable interrupt */
11604 
11605 /* Bit 26 : Write '1' to Disable interrupt for READ event */
11606 #define TWIS_INTENCLR_READ_Pos (26UL) /*!< Position of READ field. */
11607 #define TWIS_INTENCLR_READ_Msk (0x1UL << TWIS_INTENCLR_READ_Pos) /*!< Bit mask of READ field. */
11608 #define TWIS_INTENCLR_READ_Disabled (0UL) /*!< Read: Disabled */
11609 #define TWIS_INTENCLR_READ_Enabled (1UL) /*!< Read: Enabled */
11610 #define TWIS_INTENCLR_READ_Clear (1UL) /*!< Disable */
11611 
11612 /* Bit 25 : Write '1' to Disable interrupt for WRITE event */
11613 #define TWIS_INTENCLR_WRITE_Pos (25UL) /*!< Position of WRITE field. */
11614 #define TWIS_INTENCLR_WRITE_Msk (0x1UL << TWIS_INTENCLR_WRITE_Pos) /*!< Bit mask of WRITE field. */
11615 #define TWIS_INTENCLR_WRITE_Disabled (0UL) /*!< Read: Disabled */
11616 #define TWIS_INTENCLR_WRITE_Enabled (1UL) /*!< Read: Enabled */
11617 #define TWIS_INTENCLR_WRITE_Clear (1UL) /*!< Disable */
11618 
11619 /* Bit 20 : Write '1' to Disable interrupt for TXSTARTED event */
11620 #define TWIS_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
11621 #define TWIS_INTENCLR_TXSTARTED_Msk (0x1UL << TWIS_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
11622 #define TWIS_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
11623 #define TWIS_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
11624 #define TWIS_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */
11625 
11626 /* Bit 19 : Write '1' to Disable interrupt for RXSTARTED event */
11627 #define TWIS_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
11628 #define TWIS_INTENCLR_RXSTARTED_Msk (0x1UL << TWIS_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
11629 #define TWIS_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
11630 #define TWIS_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
11631 #define TWIS_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */
11632 
11633 /* Bit 9 : Write '1' to Disable interrupt for ERROR event */
11634 #define TWIS_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
11635 #define TWIS_INTENCLR_ERROR_Msk (0x1UL << TWIS_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
11636 #define TWIS_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
11637 #define TWIS_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
11638 #define TWIS_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
11639 
11640 /* Bit 1 : Write '1' to Disable interrupt for STOPPED event */
11641 #define TWIS_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
11642 #define TWIS_INTENCLR_STOPPED_Msk (0x1UL << TWIS_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
11643 #define TWIS_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
11644 #define TWIS_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
11645 #define TWIS_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
11646 
11647 /* Register: TWIS_ERRORSRC */
11648 /* Description: Error source */
11649 
11650 /* Bit 3 : TX buffer over-read detected, and prevented */
11651 #define TWIS_ERRORSRC_OVERREAD_Pos (3UL) /*!< Position of OVERREAD field. */
11652 #define TWIS_ERRORSRC_OVERREAD_Msk (0x1UL << TWIS_ERRORSRC_OVERREAD_Pos) /*!< Bit mask of OVERREAD field. */
11653 #define TWIS_ERRORSRC_OVERREAD_NotDetected (0UL) /*!< Error did not occur */
11654 #define TWIS_ERRORSRC_OVERREAD_Detected (1UL) /*!< Error occurred */
11655 
11656 /* Bit 2 : NACK sent after receiving a data byte */
11657 #define TWIS_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */
11658 #define TWIS_ERRORSRC_DNACK_Msk (0x1UL << TWIS_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */
11659 #define TWIS_ERRORSRC_DNACK_NotReceived (0UL) /*!< Error did not occur */
11660 #define TWIS_ERRORSRC_DNACK_Received (1UL) /*!< Error occurred */
11661 
11662 /* Bit 0 : RX buffer overflow detected, and prevented */
11663 #define TWIS_ERRORSRC_OVERFLOW_Pos (0UL) /*!< Position of OVERFLOW field. */
11664 #define TWIS_ERRORSRC_OVERFLOW_Msk (0x1UL << TWIS_ERRORSRC_OVERFLOW_Pos) /*!< Bit mask of OVERFLOW field. */
11665 #define TWIS_ERRORSRC_OVERFLOW_NotDetected (0UL) /*!< Error did not occur */
11666 #define TWIS_ERRORSRC_OVERFLOW_Detected (1UL) /*!< Error occurred */
11667 
11668 /* Register: TWIS_MATCH */
11669 /* Description: Status register indicating which address had a match */
11670 
11671 /* Bit 0 : Which of the addresses in {ADDRESS} matched the incoming address */
11672 #define TWIS_MATCH_MATCH_Pos (0UL) /*!< Position of MATCH field. */
11673 #define TWIS_MATCH_MATCH_Msk (0x1UL << TWIS_MATCH_MATCH_Pos) /*!< Bit mask of MATCH field. */
11674 
11675 /* Register: TWIS_ENABLE */
11676 /* Description: Enable TWIS */
11677 
11678 /* Bits 3..0 : Enable or disable TWIS */
11679 #define TWIS_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
11680 #define TWIS_ENABLE_ENABLE_Msk (0xFUL << TWIS_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
11681 #define TWIS_ENABLE_ENABLE_Disabled (0UL) /*!< Disable TWIS */
11682 #define TWIS_ENABLE_ENABLE_Enabled (9UL) /*!< Enable TWIS */
11683 
11684 /* Register: TWIS_PSEL_SCL */
11685 /* Description: Pin select for SCL signal */
11686 
11687 /* Bit 31 : Connection */
11688 #define TWIS_PSEL_SCL_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
11689 #define TWIS_PSEL_SCL_CONNECT_Msk (0x1UL << TWIS_PSEL_SCL_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
11690 #define TWIS_PSEL_SCL_CONNECT_Connected (0UL) /*!< Connect */
11691 #define TWIS_PSEL_SCL_CONNECT_Disconnected (1UL) /*!< Disconnect */
11692 
11693 /* Bits 4..0 : Pin number */
11694 #define TWIS_PSEL_SCL_PIN_Pos (0UL) /*!< Position of PIN field. */
11695 #define TWIS_PSEL_SCL_PIN_Msk (0x1FUL << TWIS_PSEL_SCL_PIN_Pos) /*!< Bit mask of PIN field. */
11696 
11697 /* Register: TWIS_PSEL_SDA */
11698 /* Description: Pin select for SDA signal */
11699 
11700 /* Bit 31 : Connection */
11701 #define TWIS_PSEL_SDA_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
11702 #define TWIS_PSEL_SDA_CONNECT_Msk (0x1UL << TWIS_PSEL_SDA_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
11703 #define TWIS_PSEL_SDA_CONNECT_Connected (0UL) /*!< Connect */
11704 #define TWIS_PSEL_SDA_CONNECT_Disconnected (1UL) /*!< Disconnect */
11705 
11706 /* Bits 4..0 : Pin number */
11707 #define TWIS_PSEL_SDA_PIN_Pos (0UL) /*!< Position of PIN field. */
11708 #define TWIS_PSEL_SDA_PIN_Msk (0x1FUL << TWIS_PSEL_SDA_PIN_Pos) /*!< Bit mask of PIN field. */
11709 
11710 /* Register: TWIS_RXD_PTR */
11711 /* Description: RXD Data pointer */
11712 
11713 /* Bits 31..0 : RXD Data pointer */
11714 #define TWIS_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
11715 #define TWIS_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIS_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
11716 
11717 /* Register: TWIS_RXD_MAXCNT */
11718 /* Description: Maximum number of bytes in RXD buffer */
11719 
11720 /* Bits 7..0 : Maximum number of bytes in RXD buffer */
11721 #define TWIS_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
11722 #define TWIS_RXD_MAXCNT_MAXCNT_Msk (0xFFUL << TWIS_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
11723 
11724 /* Register: TWIS_RXD_AMOUNT */
11725 /* Description: Number of bytes transferred in the last RXD transaction */
11726 
11727 /* Bits 7..0 : Number of bytes transferred in the last RXD transaction */
11728 #define TWIS_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
11729 #define TWIS_RXD_AMOUNT_AMOUNT_Msk (0xFFUL << TWIS_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
11730 
11731 /* Register: TWIS_TXD_PTR */
11732 /* Description: TXD Data pointer */
11733 
11734 /* Bits 31..0 : TXD Data pointer */
11735 #define TWIS_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
11736 #define TWIS_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIS_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
11737 
11738 /* Register: TWIS_TXD_MAXCNT */
11739 /* Description: Maximum number of bytes in TXD buffer */
11740 
11741 /* Bits 7..0 : Maximum number of bytes in TXD buffer */
11742 #define TWIS_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
11743 #define TWIS_TXD_MAXCNT_MAXCNT_Msk (0xFFUL << TWIS_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
11744 
11745 /* Register: TWIS_TXD_AMOUNT */
11746 /* Description: Number of bytes transferred in the last TXD transaction */
11747 
11748 /* Bits 7..0 : Number of bytes transferred in the last TXD transaction */
11749 #define TWIS_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
11750 #define TWIS_TXD_AMOUNT_AMOUNT_Msk (0xFFUL << TWIS_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
11751 
11752 /* Register: TWIS_ADDRESS */
11753 /* Description: Description collection[0]:  TWI slave address 0 */
11754 
11755 /* Bits 6..0 : TWI slave address */
11756 #define TWIS_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */
11757 #define TWIS_ADDRESS_ADDRESS_Msk (0x7FUL << TWIS_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
11758 
11759 /* Register: TWIS_CONFIG */
11760 /* Description: Configuration register for the address match mechanism */
11761 
11762 /* Bit 1 : Enable or disable address matching on ADDRESS[1] */
11763 #define TWIS_CONFIG_ADDRESS1_Pos (1UL) /*!< Position of ADDRESS1 field. */
11764 #define TWIS_CONFIG_ADDRESS1_Msk (0x1UL << TWIS_CONFIG_ADDRESS1_Pos) /*!< Bit mask of ADDRESS1 field. */
11765 #define TWIS_CONFIG_ADDRESS1_Disabled (0UL) /*!< Disabled */
11766 #define TWIS_CONFIG_ADDRESS1_Enabled (1UL) /*!< Enabled */
11767 
11768 /* Bit 0 : Enable or disable address matching on ADDRESS[0] */
11769 #define TWIS_CONFIG_ADDRESS0_Pos (0UL) /*!< Position of ADDRESS0 field. */
11770 #define TWIS_CONFIG_ADDRESS0_Msk (0x1UL << TWIS_CONFIG_ADDRESS0_Pos) /*!< Bit mask of ADDRESS0 field. */
11771 #define TWIS_CONFIG_ADDRESS0_Disabled (0UL) /*!< Disabled */
11772 #define TWIS_CONFIG_ADDRESS0_Enabled (1UL) /*!< Enabled */
11773 
11774 /* Register: TWIS_ORC */
11775 /* Description: Over-read character. Character sent out in case of an over-read of the transmit buffer. */
11776 
11777 /* Bits 7..0 : Over-read character. Character sent out in case of an over-read of the transmit buffer. */
11778 #define TWIS_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */
11779 #define TWIS_ORC_ORC_Msk (0xFFUL << TWIS_ORC_ORC_Pos) /*!< Bit mask of ORC field. */
11780 
11781 
11782 /* Peripheral: UART */
11783 /* Description: Universal Asynchronous Receiver/Transmitter */
11784 
11785 /* Register: UART_SHORTS */
11786 /* Description: Shortcut register */
11787 
11788 /* Bit 4 : Shortcut between NCTS event and STOPRX task */
11789 #define UART_SHORTS_NCTS_STOPRX_Pos (4UL) /*!< Position of NCTS_STOPRX field. */
11790 #define UART_SHORTS_NCTS_STOPRX_Msk (0x1UL << UART_SHORTS_NCTS_STOPRX_Pos) /*!< Bit mask of NCTS_STOPRX field. */
11791 #define UART_SHORTS_NCTS_STOPRX_Disabled (0UL) /*!< Disable shortcut */
11792 #define UART_SHORTS_NCTS_STOPRX_Enabled (1UL) /*!< Enable shortcut */
11793 
11794 /* Bit 3 : Shortcut between CTS event and STARTRX task */
11795 #define UART_SHORTS_CTS_STARTRX_Pos (3UL) /*!< Position of CTS_STARTRX field. */
11796 #define UART_SHORTS_CTS_STARTRX_Msk (0x1UL << UART_SHORTS_CTS_STARTRX_Pos) /*!< Bit mask of CTS_STARTRX field. */
11797 #define UART_SHORTS_CTS_STARTRX_Disabled (0UL) /*!< Disable shortcut */
11798 #define UART_SHORTS_CTS_STARTRX_Enabled (1UL) /*!< Enable shortcut */
11799 
11800 /* Register: UART_INTENSET */
11801 /* Description: Enable interrupt */
11802 
11803 /* Bit 17 : Write '1' to Enable interrupt for RXTO event */
11804 #define UART_INTENSET_RXTO_Pos (17UL) /*!< Position of RXTO field. */
11805 #define UART_INTENSET_RXTO_Msk (0x1UL << UART_INTENSET_RXTO_Pos) /*!< Bit mask of RXTO field. */
11806 #define UART_INTENSET_RXTO_Disabled (0UL) /*!< Read: Disabled */
11807 #define UART_INTENSET_RXTO_Enabled (1UL) /*!< Read: Enabled */
11808 #define UART_INTENSET_RXTO_Set (1UL) /*!< Enable */
11809 
11810 /* Bit 9 : Write '1' to Enable interrupt for ERROR event */
11811 #define UART_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
11812 #define UART_INTENSET_ERROR_Msk (0x1UL << UART_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
11813 #define UART_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
11814 #define UART_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
11815 #define UART_INTENSET_ERROR_Set (1UL) /*!< Enable */
11816 
11817 /* Bit 7 : Write '1' to Enable interrupt for TXDRDY event */
11818 #define UART_INTENSET_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
11819 #define UART_INTENSET_TXDRDY_Msk (0x1UL << UART_INTENSET_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
11820 #define UART_INTENSET_TXDRDY_Disabled (0UL) /*!< Read: Disabled */
11821 #define UART_INTENSET_TXDRDY_Enabled (1UL) /*!< Read: Enabled */
11822 #define UART_INTENSET_TXDRDY_Set (1UL) /*!< Enable */
11823 
11824 /* Bit 2 : Write '1' to Enable interrupt for RXDRDY event */
11825 #define UART_INTENSET_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
11826 #define UART_INTENSET_RXDRDY_Msk (0x1UL << UART_INTENSET_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
11827 #define UART_INTENSET_RXDRDY_Disabled (0UL) /*!< Read: Disabled */
11828 #define UART_INTENSET_RXDRDY_Enabled (1UL) /*!< Read: Enabled */
11829 #define UART_INTENSET_RXDRDY_Set (1UL) /*!< Enable */
11830 
11831 /* Bit 1 : Write '1' to Enable interrupt for NCTS event */
11832 #define UART_INTENSET_NCTS_Pos (1UL) /*!< Position of NCTS field. */
11833 #define UART_INTENSET_NCTS_Msk (0x1UL << UART_INTENSET_NCTS_Pos) /*!< Bit mask of NCTS field. */
11834 #define UART_INTENSET_NCTS_Disabled (0UL) /*!< Read: Disabled */
11835 #define UART_INTENSET_NCTS_Enabled (1UL) /*!< Read: Enabled */
11836 #define UART_INTENSET_NCTS_Set (1UL) /*!< Enable */
11837 
11838 /* Bit 0 : Write '1' to Enable interrupt for CTS event */
11839 #define UART_INTENSET_CTS_Pos (0UL) /*!< Position of CTS field. */
11840 #define UART_INTENSET_CTS_Msk (0x1UL << UART_INTENSET_CTS_Pos) /*!< Bit mask of CTS field. */
11841 #define UART_INTENSET_CTS_Disabled (0UL) /*!< Read: Disabled */
11842 #define UART_INTENSET_CTS_Enabled (1UL) /*!< Read: Enabled */
11843 #define UART_INTENSET_CTS_Set (1UL) /*!< Enable */
11844 
11845 /* Register: UART_INTENCLR */
11846 /* Description: Disable interrupt */
11847 
11848 /* Bit 17 : Write '1' to Disable interrupt for RXTO event */
11849 #define UART_INTENCLR_RXTO_Pos (17UL) /*!< Position of RXTO field. */
11850 #define UART_INTENCLR_RXTO_Msk (0x1UL << UART_INTENCLR_RXTO_Pos) /*!< Bit mask of RXTO field. */
11851 #define UART_INTENCLR_RXTO_Disabled (0UL) /*!< Read: Disabled */
11852 #define UART_INTENCLR_RXTO_Enabled (1UL) /*!< Read: Enabled */
11853 #define UART_INTENCLR_RXTO_Clear (1UL) /*!< Disable */
11854 
11855 /* Bit 9 : Write '1' to Disable interrupt for ERROR event */
11856 #define UART_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
11857 #define UART_INTENCLR_ERROR_Msk (0x1UL << UART_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
11858 #define UART_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
11859 #define UART_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
11860 #define UART_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
11861 
11862 /* Bit 7 : Write '1' to Disable interrupt for TXDRDY event */
11863 #define UART_INTENCLR_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
11864 #define UART_INTENCLR_TXDRDY_Msk (0x1UL << UART_INTENCLR_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
11865 #define UART_INTENCLR_TXDRDY_Disabled (0UL) /*!< Read: Disabled */
11866 #define UART_INTENCLR_TXDRDY_Enabled (1UL) /*!< Read: Enabled */
11867 #define UART_INTENCLR_TXDRDY_Clear (1UL) /*!< Disable */
11868 
11869 /* Bit 2 : Write '1' to Disable interrupt for RXDRDY event */
11870 #define UART_INTENCLR_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
11871 #define UART_INTENCLR_RXDRDY_Msk (0x1UL << UART_INTENCLR_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
11872 #define UART_INTENCLR_RXDRDY_Disabled (0UL) /*!< Read: Disabled */
11873 #define UART_INTENCLR_RXDRDY_Enabled (1UL) /*!< Read: Enabled */
11874 #define UART_INTENCLR_RXDRDY_Clear (1UL) /*!< Disable */
11875 
11876 /* Bit 1 : Write '1' to Disable interrupt for NCTS event */
11877 #define UART_INTENCLR_NCTS_Pos (1UL) /*!< Position of NCTS field. */
11878 #define UART_INTENCLR_NCTS_Msk (0x1UL << UART_INTENCLR_NCTS_Pos) /*!< Bit mask of NCTS field. */
11879 #define UART_INTENCLR_NCTS_Disabled (0UL) /*!< Read: Disabled */
11880 #define UART_INTENCLR_NCTS_Enabled (1UL) /*!< Read: Enabled */
11881 #define UART_INTENCLR_NCTS_Clear (1UL) /*!< Disable */
11882 
11883 /* Bit 0 : Write '1' to Disable interrupt for CTS event */
11884 #define UART_INTENCLR_CTS_Pos (0UL) /*!< Position of CTS field. */
11885 #define UART_INTENCLR_CTS_Msk (0x1UL << UART_INTENCLR_CTS_Pos) /*!< Bit mask of CTS field. */
11886 #define UART_INTENCLR_CTS_Disabled (0UL) /*!< Read: Disabled */
11887 #define UART_INTENCLR_CTS_Enabled (1UL) /*!< Read: Enabled */
11888 #define UART_INTENCLR_CTS_Clear (1UL) /*!< Disable */
11889 
11890 /* Register: UART_ERRORSRC */
11891 /* Description: Error source */
11892 
11893 /* Bit 3 : Break condition */
11894 #define UART_ERRORSRC_BREAK_Pos (3UL) /*!< Position of BREAK field. */
11895 #define UART_ERRORSRC_BREAK_Msk (0x1UL << UART_ERRORSRC_BREAK_Pos) /*!< Bit mask of BREAK field. */
11896 #define UART_ERRORSRC_BREAK_NotPresent (0UL) /*!< Read: error not present */
11897 #define UART_ERRORSRC_BREAK_Present (1UL) /*!< Read: error present */
11898 
11899 /* Bit 2 : Framing error occurred */
11900 #define UART_ERRORSRC_FRAMING_Pos (2UL) /*!< Position of FRAMING field. */
11901 #define UART_ERRORSRC_FRAMING_Msk (0x1UL << UART_ERRORSRC_FRAMING_Pos) /*!< Bit mask of FRAMING field. */
11902 #define UART_ERRORSRC_FRAMING_NotPresent (0UL) /*!< Read: error not present */
11903 #define UART_ERRORSRC_FRAMING_Present (1UL) /*!< Read: error present */
11904 
11905 /* Bit 1 : Parity error */
11906 #define UART_ERRORSRC_PARITY_Pos (1UL) /*!< Position of PARITY field. */
11907 #define UART_ERRORSRC_PARITY_Msk (0x1UL << UART_ERRORSRC_PARITY_Pos) /*!< Bit mask of PARITY field. */
11908 #define UART_ERRORSRC_PARITY_NotPresent (0UL) /*!< Read: error not present */
11909 #define UART_ERRORSRC_PARITY_Present (1UL) /*!< Read: error present */
11910 
11911 /* Bit 0 : Overrun error */
11912 #define UART_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */
11913 #define UART_ERRORSRC_OVERRUN_Msk (0x1UL << UART_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */
11914 #define UART_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Read: error not present */
11915 #define UART_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: error present */
11916 
11917 /* Register: UART_ENABLE */
11918 /* Description: Enable UART */
11919 
11920 /* Bits 3..0 : Enable or disable UART */
11921 #define UART_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
11922 #define UART_ENABLE_ENABLE_Msk (0xFUL << UART_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
11923 #define UART_ENABLE_ENABLE_Disabled (0UL) /*!< Disable UART */
11924 #define UART_ENABLE_ENABLE_Enabled (4UL) /*!< Enable UART */
11925 
11926 /* Register: UART_PSELRTS */
11927 /* Description: Pin select for RTS */
11928 
11929 /* Bits 31..0 : Pin number configuration for UART RTS signal */
11930 #define UART_PSELRTS_PSELRTS_Pos (0UL) /*!< Position of PSELRTS field. */
11931 #define UART_PSELRTS_PSELRTS_Msk (0xFFFFFFFFUL << UART_PSELRTS_PSELRTS_Pos) /*!< Bit mask of PSELRTS field. */
11932 #define UART_PSELRTS_PSELRTS_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */
11933 
11934 /* Register: UART_PSELTXD */
11935 /* Description: Pin select for TXD */
11936 
11937 /* Bits 31..0 : Pin number configuration for UART TXD signal */
11938 #define UART_PSELTXD_PSELTXD_Pos (0UL) /*!< Position of PSELTXD field. */
11939 #define UART_PSELTXD_PSELTXD_Msk (0xFFFFFFFFUL << UART_PSELTXD_PSELTXD_Pos) /*!< Bit mask of PSELTXD field. */
11940 #define UART_PSELTXD_PSELTXD_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */
11941 
11942 /* Register: UART_PSELCTS */
11943 /* Description: Pin select for CTS */
11944 
11945 /* Bits 31..0 : Pin number configuration for UART CTS signal */
11946 #define UART_PSELCTS_PSELCTS_Pos (0UL) /*!< Position of PSELCTS field. */
11947 #define UART_PSELCTS_PSELCTS_Msk (0xFFFFFFFFUL << UART_PSELCTS_PSELCTS_Pos) /*!< Bit mask of PSELCTS field. */
11948 #define UART_PSELCTS_PSELCTS_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */
11949 
11950 /* Register: UART_PSELRXD */
11951 /* Description: Pin select for RXD */
11952 
11953 /* Bits 31..0 : Pin number configuration for UART RXD signal */
11954 #define UART_PSELRXD_PSELRXD_Pos (0UL) /*!< Position of PSELRXD field. */
11955 #define UART_PSELRXD_PSELRXD_Msk (0xFFFFFFFFUL << UART_PSELRXD_PSELRXD_Pos) /*!< Bit mask of PSELRXD field. */
11956 #define UART_PSELRXD_PSELRXD_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */
11957 
11958 /* Register: UART_RXD */
11959 /* Description: RXD register */
11960 
11961 /* Bits 7..0 : RX data received in previous transfers, double buffered */
11962 #define UART_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */
11963 #define UART_RXD_RXD_Msk (0xFFUL << UART_RXD_RXD_Pos) /*!< Bit mask of RXD field. */
11964 
11965 /* Register: UART_TXD */
11966 /* Description: TXD register */
11967 
11968 /* Bits 7..0 : TX data to be transferred */
11969 #define UART_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */
11970 #define UART_TXD_TXD_Msk (0xFFUL << UART_TXD_TXD_Pos) /*!< Bit mask of TXD field. */
11971 
11972 /* Register: UART_BAUDRATE */
11973 /* Description: Baud rate */
11974 
11975 /* Bits 31..0 : Baud rate */
11976 #define UART_BAUDRATE_BAUDRATE_Pos (0UL) /*!< Position of BAUDRATE field. */
11977 #define UART_BAUDRATE_BAUDRATE_Msk (0xFFFFFFFFUL << UART_BAUDRATE_BAUDRATE_Pos) /*!< Bit mask of BAUDRATE field. */
11978 #define UART_BAUDRATE_BAUDRATE_Baud1200 (0x0004F000UL) /*!< 1200 baud (actual rate: 1205) */
11979 #define UART_BAUDRATE_BAUDRATE_Baud2400 (0x0009D000UL) /*!< 2400 baud (actual rate: 2396) */
11980 #define UART_BAUDRATE_BAUDRATE_Baud4800 (0x0013B000UL) /*!< 4800 baud (actual rate: 4808) */
11981 #define UART_BAUDRATE_BAUDRATE_Baud9600 (0x00275000UL) /*!< 9600 baud (actual rate: 9598) */
11982 #define UART_BAUDRATE_BAUDRATE_Baud14400 (0x003B0000UL) /*!< 14400 baud (actual rate: 14414) */
11983 #define UART_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL) /*!< 19200 baud (actual rate: 19208) */
11984 #define UART_BAUDRATE_BAUDRATE_Baud28800 (0x0075F000UL) /*!< 28800 baud (actual rate: 28829) */
11985 #define UART_BAUDRATE_BAUDRATE_Baud31250 (0x00800000UL) /*!< 31250 baud */
11986 #define UART_BAUDRATE_BAUDRATE_Baud38400 (0x009D5000UL) /*!< 38400 baud (actual rate: 38462) */
11987 #define UART_BAUDRATE_BAUDRATE_Baud56000 (0x00E50000UL) /*!< 56000 baud (actual rate: 55944) */
11988 #define UART_BAUDRATE_BAUDRATE_Baud57600 (0x00EBF000UL) /*!< 57600 baud (actual rate: 57762) */
11989 #define UART_BAUDRATE_BAUDRATE_Baud76800 (0x013A9000UL) /*!< 76800 baud (actual rate: 76923) */
11990 #define UART_BAUDRATE_BAUDRATE_Baud115200 (0x01D7E000UL) /*!< 115200 baud (actual rate: 115942) */
11991 #define UART_BAUDRATE_BAUDRATE_Baud230400 (0x03AFB000UL) /*!< 230400 baud (actual rate: 231884) */
11992 #define UART_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL) /*!< 250000 baud */
11993 #define UART_BAUDRATE_BAUDRATE_Baud460800 (0x075F7000UL) /*!< 460800 baud (actual rate: 470588) */
11994 #define UART_BAUDRATE_BAUDRATE_Baud921600 (0x0EBED000UL) /*!< 921600 baud (actual rate: 941176) */
11995 #define UART_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /*!< 1Mega baud */
11996 
11997 /* Register: UART_CONFIG */
11998 /* Description: Configuration of parity and hardware flow control */
11999 
12000 /* Bits 3..1 : Parity */
12001 #define UART_CONFIG_PARITY_Pos (1UL) /*!< Position of PARITY field. */
12002 #define UART_CONFIG_PARITY_Msk (0x7UL << UART_CONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */
12003 #define UART_CONFIG_PARITY_Excluded (0x0UL) /*!< Exclude parity bit */
12004 #define UART_CONFIG_PARITY_Included (0x7UL) /*!< Include parity bit */
12005 
12006 /* Bit 0 : Hardware flow control */
12007 #define UART_CONFIG_HWFC_Pos (0UL) /*!< Position of HWFC field. */
12008 #define UART_CONFIG_HWFC_Msk (0x1UL << UART_CONFIG_HWFC_Pos) /*!< Bit mask of HWFC field. */
12009 #define UART_CONFIG_HWFC_Disabled (0UL) /*!< Disabled */
12010 #define UART_CONFIG_HWFC_Enabled (1UL) /*!< Enabled */
12011 
12012 
12013 /* Peripheral: UARTE */
12014 /* Description: UART with EasyDMA */
12015 
12016 /* Register: UARTE_SHORTS */
12017 /* Description: Shortcut register */
12018 
12019 /* Bit 6 : Shortcut between ENDRX event and STOPRX task */
12020 #define UARTE_SHORTS_ENDRX_STOPRX_Pos (6UL) /*!< Position of ENDRX_STOPRX field. */
12021 #define UARTE_SHORTS_ENDRX_STOPRX_Msk (0x1UL << UARTE_SHORTS_ENDRX_STOPRX_Pos) /*!< Bit mask of ENDRX_STOPRX field. */
12022 #define UARTE_SHORTS_ENDRX_STOPRX_Disabled (0UL) /*!< Disable shortcut */
12023 #define UARTE_SHORTS_ENDRX_STOPRX_Enabled (1UL) /*!< Enable shortcut */
12024 
12025 /* Bit 5 : Shortcut between ENDRX event and STARTRX task */
12026 #define UARTE_SHORTS_ENDRX_STARTRX_Pos (5UL) /*!< Position of ENDRX_STARTRX field. */
12027 #define UARTE_SHORTS_ENDRX_STARTRX_Msk (0x1UL << UARTE_SHORTS_ENDRX_STARTRX_Pos) /*!< Bit mask of ENDRX_STARTRX field. */
12028 #define UARTE_SHORTS_ENDRX_STARTRX_Disabled (0UL) /*!< Disable shortcut */
12029 #define UARTE_SHORTS_ENDRX_STARTRX_Enabled (1UL) /*!< Enable shortcut */
12030 
12031 /* Register: UARTE_INTEN */
12032 /* Description: Enable or disable interrupt */
12033 
12034 /* Bit 22 : Enable or disable interrupt for TXSTOPPED event */
12035 #define UARTE_INTEN_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */
12036 #define UARTE_INTEN_TXSTOPPED_Msk (0x1UL << UARTE_INTEN_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */
12037 #define UARTE_INTEN_TXSTOPPED_Disabled (0UL) /*!< Disable */
12038 #define UARTE_INTEN_TXSTOPPED_Enabled (1UL) /*!< Enable */
12039 
12040 /* Bit 20 : Enable or disable interrupt for TXSTARTED event */
12041 #define UARTE_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
12042 #define UARTE_INTEN_TXSTARTED_Msk (0x1UL << UARTE_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
12043 #define UARTE_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */
12044 #define UARTE_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */
12045 
12046 /* Bit 19 : Enable or disable interrupt for RXSTARTED event */
12047 #define UARTE_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
12048 #define UARTE_INTEN_RXSTARTED_Msk (0x1UL << UARTE_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
12049 #define UARTE_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */
12050 #define UARTE_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */
12051 
12052 /* Bit 17 : Enable or disable interrupt for RXTO event */
12053 #define UARTE_INTEN_RXTO_Pos (17UL) /*!< Position of RXTO field. */
12054 #define UARTE_INTEN_RXTO_Msk (0x1UL << UARTE_INTEN_RXTO_Pos) /*!< Bit mask of RXTO field. */
12055 #define UARTE_INTEN_RXTO_Disabled (0UL) /*!< Disable */
12056 #define UARTE_INTEN_RXTO_Enabled (1UL) /*!< Enable */
12057 
12058 /* Bit 9 : Enable or disable interrupt for ERROR event */
12059 #define UARTE_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */
12060 #define UARTE_INTEN_ERROR_Msk (0x1UL << UARTE_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */
12061 #define UARTE_INTEN_ERROR_Disabled (0UL) /*!< Disable */
12062 #define UARTE_INTEN_ERROR_Enabled (1UL) /*!< Enable */
12063 
12064 /* Bit 8 : Enable or disable interrupt for ENDTX event */
12065 #define UARTE_INTEN_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
12066 #define UARTE_INTEN_ENDTX_Msk (0x1UL << UARTE_INTEN_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
12067 #define UARTE_INTEN_ENDTX_Disabled (0UL) /*!< Disable */
12068 #define UARTE_INTEN_ENDTX_Enabled (1UL) /*!< Enable */
12069 
12070 /* Bit 7 : Enable or disable interrupt for TXDRDY event */
12071 #define UARTE_INTEN_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
12072 #define UARTE_INTEN_TXDRDY_Msk (0x1UL << UARTE_INTEN_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
12073 #define UARTE_INTEN_TXDRDY_Disabled (0UL) /*!< Disable */
12074 #define UARTE_INTEN_TXDRDY_Enabled (1UL) /*!< Enable */
12075 
12076 /* Bit 4 : Enable or disable interrupt for ENDRX event */
12077 #define UARTE_INTEN_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
12078 #define UARTE_INTEN_ENDRX_Msk (0x1UL << UARTE_INTEN_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
12079 #define UARTE_INTEN_ENDRX_Disabled (0UL) /*!< Disable */
12080 #define UARTE_INTEN_ENDRX_Enabled (1UL) /*!< Enable */
12081 
12082 /* Bit 2 : Enable or disable interrupt for RXDRDY event */
12083 #define UARTE_INTEN_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
12084 #define UARTE_INTEN_RXDRDY_Msk (0x1UL << UARTE_INTEN_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
12085 #define UARTE_INTEN_RXDRDY_Disabled (0UL) /*!< Disable */
12086 #define UARTE_INTEN_RXDRDY_Enabled (1UL) /*!< Enable */
12087 
12088 /* Bit 1 : Enable or disable interrupt for NCTS event */
12089 #define UARTE_INTEN_NCTS_Pos (1UL) /*!< Position of NCTS field. */
12090 #define UARTE_INTEN_NCTS_Msk (0x1UL << UARTE_INTEN_NCTS_Pos) /*!< Bit mask of NCTS field. */
12091 #define UARTE_INTEN_NCTS_Disabled (0UL) /*!< Disable */
12092 #define UARTE_INTEN_NCTS_Enabled (1UL) /*!< Enable */
12093 
12094 /* Bit 0 : Enable or disable interrupt for CTS event */
12095 #define UARTE_INTEN_CTS_Pos (0UL) /*!< Position of CTS field. */
12096 #define UARTE_INTEN_CTS_Msk (0x1UL << UARTE_INTEN_CTS_Pos) /*!< Bit mask of CTS field. */
12097 #define UARTE_INTEN_CTS_Disabled (0UL) /*!< Disable */
12098 #define UARTE_INTEN_CTS_Enabled (1UL) /*!< Enable */
12099 
12100 /* Register: UARTE_INTENSET */
12101 /* Description: Enable interrupt */
12102 
12103 /* Bit 22 : Write '1' to Enable interrupt for TXSTOPPED event */
12104 #define UARTE_INTENSET_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */
12105 #define UARTE_INTENSET_TXSTOPPED_Msk (0x1UL << UARTE_INTENSET_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */
12106 #define UARTE_INTENSET_TXSTOPPED_Disabled (0UL) /*!< Read: Disabled */
12107 #define UARTE_INTENSET_TXSTOPPED_Enabled (1UL) /*!< Read: Enabled */
12108 #define UARTE_INTENSET_TXSTOPPED_Set (1UL) /*!< Enable */
12109 
12110 /* Bit 20 : Write '1' to Enable interrupt for TXSTARTED event */
12111 #define UARTE_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
12112 #define UARTE_INTENSET_TXSTARTED_Msk (0x1UL << UARTE_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
12113 #define UARTE_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
12114 #define UARTE_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
12115 #define UARTE_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */
12116 
12117 /* Bit 19 : Write '1' to Enable interrupt for RXSTARTED event */
12118 #define UARTE_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
12119 #define UARTE_INTENSET_RXSTARTED_Msk (0x1UL << UARTE_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
12120 #define UARTE_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
12121 #define UARTE_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
12122 #define UARTE_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */
12123 
12124 /* Bit 17 : Write '1' to Enable interrupt for RXTO event */
12125 #define UARTE_INTENSET_RXTO_Pos (17UL) /*!< Position of RXTO field. */
12126 #define UARTE_INTENSET_RXTO_Msk (0x1UL << UARTE_INTENSET_RXTO_Pos) /*!< Bit mask of RXTO field. */
12127 #define UARTE_INTENSET_RXTO_Disabled (0UL) /*!< Read: Disabled */
12128 #define UARTE_INTENSET_RXTO_Enabled (1UL) /*!< Read: Enabled */
12129 #define UARTE_INTENSET_RXTO_Set (1UL) /*!< Enable */
12130 
12131 /* Bit 9 : Write '1' to Enable interrupt for ERROR event */
12132 #define UARTE_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
12133 #define UARTE_INTENSET_ERROR_Msk (0x1UL << UARTE_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
12134 #define UARTE_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
12135 #define UARTE_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
12136 #define UARTE_INTENSET_ERROR_Set (1UL) /*!< Enable */
12137 
12138 /* Bit 8 : Write '1' to Enable interrupt for ENDTX event */
12139 #define UARTE_INTENSET_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
12140 #define UARTE_INTENSET_ENDTX_Msk (0x1UL << UARTE_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
12141 #define UARTE_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */
12142 #define UARTE_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */
12143 #define UARTE_INTENSET_ENDTX_Set (1UL) /*!< Enable */
12144 
12145 /* Bit 7 : Write '1' to Enable interrupt for TXDRDY event */
12146 #define UARTE_INTENSET_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
12147 #define UARTE_INTENSET_TXDRDY_Msk (0x1UL << UARTE_INTENSET_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
12148 #define UARTE_INTENSET_TXDRDY_Disabled (0UL) /*!< Read: Disabled */
12149 #define UARTE_INTENSET_TXDRDY_Enabled (1UL) /*!< Read: Enabled */
12150 #define UARTE_INTENSET_TXDRDY_Set (1UL) /*!< Enable */
12151 
12152 /* Bit 4 : Write '1' to Enable interrupt for ENDRX event */
12153 #define UARTE_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
12154 #define UARTE_INTENSET_ENDRX_Msk (0x1UL << UARTE_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
12155 #define UARTE_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */
12156 #define UARTE_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */
12157 #define UARTE_INTENSET_ENDRX_Set (1UL) /*!< Enable */
12158 
12159 /* Bit 2 : Write '1' to Enable interrupt for RXDRDY event */
12160 #define UARTE_INTENSET_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
12161 #define UARTE_INTENSET_RXDRDY_Msk (0x1UL << UARTE_INTENSET_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
12162 #define UARTE_INTENSET_RXDRDY_Disabled (0UL) /*!< Read: Disabled */
12163 #define UARTE_INTENSET_RXDRDY_Enabled (1UL) /*!< Read: Enabled */
12164 #define UARTE_INTENSET_RXDRDY_Set (1UL) /*!< Enable */
12165 
12166 /* Bit 1 : Write '1' to Enable interrupt for NCTS event */
12167 #define UARTE_INTENSET_NCTS_Pos (1UL) /*!< Position of NCTS field. */
12168 #define UARTE_INTENSET_NCTS_Msk (0x1UL << UARTE_INTENSET_NCTS_Pos) /*!< Bit mask of NCTS field. */
12169 #define UARTE_INTENSET_NCTS_Disabled (0UL) /*!< Read: Disabled */
12170 #define UARTE_INTENSET_NCTS_Enabled (1UL) /*!< Read: Enabled */
12171 #define UARTE_INTENSET_NCTS_Set (1UL) /*!< Enable */
12172 
12173 /* Bit 0 : Write '1' to Enable interrupt for CTS event */
12174 #define UARTE_INTENSET_CTS_Pos (0UL) /*!< Position of CTS field. */
12175 #define UARTE_INTENSET_CTS_Msk (0x1UL << UARTE_INTENSET_CTS_Pos) /*!< Bit mask of CTS field. */
12176 #define UARTE_INTENSET_CTS_Disabled (0UL) /*!< Read: Disabled */
12177 #define UARTE_INTENSET_CTS_Enabled (1UL) /*!< Read: Enabled */
12178 #define UARTE_INTENSET_CTS_Set (1UL) /*!< Enable */
12179 
12180 /* Register: UARTE_INTENCLR */
12181 /* Description: Disable interrupt */
12182 
12183 /* Bit 22 : Write '1' to Disable interrupt for TXSTOPPED event */
12184 #define UARTE_INTENCLR_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */
12185 #define UARTE_INTENCLR_TXSTOPPED_Msk (0x1UL << UARTE_INTENCLR_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */
12186 #define UARTE_INTENCLR_TXSTOPPED_Disabled (0UL) /*!< Read: Disabled */
12187 #define UARTE_INTENCLR_TXSTOPPED_Enabled (1UL) /*!< Read: Enabled */
12188 #define UARTE_INTENCLR_TXSTOPPED_Clear (1UL) /*!< Disable */
12189 
12190 /* Bit 20 : Write '1' to Disable interrupt for TXSTARTED event */
12191 #define UARTE_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
12192 #define UARTE_INTENCLR_TXSTARTED_Msk (0x1UL << UARTE_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
12193 #define UARTE_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
12194 #define UARTE_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
12195 #define UARTE_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */
12196 
12197 /* Bit 19 : Write '1' to Disable interrupt for RXSTARTED event */
12198 #define UARTE_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
12199 #define UARTE_INTENCLR_RXSTARTED_Msk (0x1UL << UARTE_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
12200 #define UARTE_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
12201 #define UARTE_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
12202 #define UARTE_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */
12203 
12204 /* Bit 17 : Write '1' to Disable interrupt for RXTO event */
12205 #define UARTE_INTENCLR_RXTO_Pos (17UL) /*!< Position of RXTO field. */
12206 #define UARTE_INTENCLR_RXTO_Msk (0x1UL << UARTE_INTENCLR_RXTO_Pos) /*!< Bit mask of RXTO field. */
12207 #define UARTE_INTENCLR_RXTO_Disabled (0UL) /*!< Read: Disabled */
12208 #define UARTE_INTENCLR_RXTO_Enabled (1UL) /*!< Read: Enabled */
12209 #define UARTE_INTENCLR_RXTO_Clear (1UL) /*!< Disable */
12210 
12211 /* Bit 9 : Write '1' to Disable interrupt for ERROR event */
12212 #define UARTE_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
12213 #define UARTE_INTENCLR_ERROR_Msk (0x1UL << UARTE_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
12214 #define UARTE_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
12215 #define UARTE_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
12216 #define UARTE_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
12217 
12218 /* Bit 8 : Write '1' to Disable interrupt for ENDTX event */
12219 #define UARTE_INTENCLR_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
12220 #define UARTE_INTENCLR_ENDTX_Msk (0x1UL << UARTE_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
12221 #define UARTE_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */
12222 #define UARTE_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */
12223 #define UARTE_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */
12224 
12225 /* Bit 7 : Write '1' to Disable interrupt for TXDRDY event */
12226 #define UARTE_INTENCLR_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
12227 #define UARTE_INTENCLR_TXDRDY_Msk (0x1UL << UARTE_INTENCLR_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
12228 #define UARTE_INTENCLR_TXDRDY_Disabled (0UL) /*!< Read: Disabled */
12229 #define UARTE_INTENCLR_TXDRDY_Enabled (1UL) /*!< Read: Enabled */
12230 #define UARTE_INTENCLR_TXDRDY_Clear (1UL) /*!< Disable */
12231 
12232 /* Bit 4 : Write '1' to Disable interrupt for ENDRX event */
12233 #define UARTE_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
12234 #define UARTE_INTENCLR_ENDRX_Msk (0x1UL << UARTE_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
12235 #define UARTE_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */
12236 #define UARTE_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */
12237 #define UARTE_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */
12238 
12239 /* Bit 2 : Write '1' to Disable interrupt for RXDRDY event */
12240 #define UARTE_INTENCLR_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
12241 #define UARTE_INTENCLR_RXDRDY_Msk (0x1UL << UARTE_INTENCLR_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
12242 #define UARTE_INTENCLR_RXDRDY_Disabled (0UL) /*!< Read: Disabled */
12243 #define UARTE_INTENCLR_RXDRDY_Enabled (1UL) /*!< Read: Enabled */
12244 #define UARTE_INTENCLR_RXDRDY_Clear (1UL) /*!< Disable */
12245 
12246 /* Bit 1 : Write '1' to Disable interrupt for NCTS event */
12247 #define UARTE_INTENCLR_NCTS_Pos (1UL) /*!< Position of NCTS field. */
12248 #define UARTE_INTENCLR_NCTS_Msk (0x1UL << UARTE_INTENCLR_NCTS_Pos) /*!< Bit mask of NCTS field. */
12249 #define UARTE_INTENCLR_NCTS_Disabled (0UL) /*!< Read: Disabled */
12250 #define UARTE_INTENCLR_NCTS_Enabled (1UL) /*!< Read: Enabled */
12251 #define UARTE_INTENCLR_NCTS_Clear (1UL) /*!< Disable */
12252 
12253 /* Bit 0 : Write '1' to Disable interrupt for CTS event */
12254 #define UARTE_INTENCLR_CTS_Pos (0UL) /*!< Position of CTS field. */
12255 #define UARTE_INTENCLR_CTS_Msk (0x1UL << UARTE_INTENCLR_CTS_Pos) /*!< Bit mask of CTS field. */
12256 #define UARTE_INTENCLR_CTS_Disabled (0UL) /*!< Read: Disabled */
12257 #define UARTE_INTENCLR_CTS_Enabled (1UL) /*!< Read: Enabled */
12258 #define UARTE_INTENCLR_CTS_Clear (1UL) /*!< Disable */
12259 
12260 /* Register: UARTE_ERRORSRC */
12261 /* Description: Error source */
12262 
12263 /* Bit 3 : Break condition */
12264 #define UARTE_ERRORSRC_BREAK_Pos (3UL) /*!< Position of BREAK field. */
12265 #define UARTE_ERRORSRC_BREAK_Msk (0x1UL << UARTE_ERRORSRC_BREAK_Pos) /*!< Bit mask of BREAK field. */
12266 #define UARTE_ERRORSRC_BREAK_NotPresent (0UL) /*!< Read: error not present */
12267 #define UARTE_ERRORSRC_BREAK_Present (1UL) /*!< Read: error present */
12268 
12269 /* Bit 2 : Framing error occurred */
12270 #define UARTE_ERRORSRC_FRAMING_Pos (2UL) /*!< Position of FRAMING field. */
12271 #define UARTE_ERRORSRC_FRAMING_Msk (0x1UL << UARTE_ERRORSRC_FRAMING_Pos) /*!< Bit mask of FRAMING field. */
12272 #define UARTE_ERRORSRC_FRAMING_NotPresent (0UL) /*!< Read: error not present */
12273 #define UARTE_ERRORSRC_FRAMING_Present (1UL) /*!< Read: error present */
12274 
12275 /* Bit 1 : Parity error */
12276 #define UARTE_ERRORSRC_PARITY_Pos (1UL) /*!< Position of PARITY field. */
12277 #define UARTE_ERRORSRC_PARITY_Msk (0x1UL << UARTE_ERRORSRC_PARITY_Pos) /*!< Bit mask of PARITY field. */
12278 #define UARTE_ERRORSRC_PARITY_NotPresent (0UL) /*!< Read: error not present */
12279 #define UARTE_ERRORSRC_PARITY_Present (1UL) /*!< Read: error present */
12280 
12281 /* Bit 0 : Overrun error */
12282 #define UARTE_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */
12283 #define UARTE_ERRORSRC_OVERRUN_Msk (0x1UL << UARTE_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */
12284 #define UARTE_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Read: error not present */
12285 #define UARTE_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: error present */
12286 
12287 /* Register: UARTE_ENABLE */
12288 /* Description: Enable UART */
12289 
12290 /* Bits 3..0 : Enable or disable UARTE */
12291 #define UARTE_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
12292 #define UARTE_ENABLE_ENABLE_Msk (0xFUL << UARTE_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
12293 #define UARTE_ENABLE_ENABLE_Disabled (0UL) /*!< Disable UARTE */
12294 #define UARTE_ENABLE_ENABLE_Enabled (8UL) /*!< Enable UARTE */
12295 
12296 /* Register: UARTE_PSEL_RTS */
12297 /* Description: Pin select for RTS signal */
12298 
12299 /* Bit 31 : Connection */
12300 #define UARTE_PSEL_RTS_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
12301 #define UARTE_PSEL_RTS_CONNECT_Msk (0x1UL << UARTE_PSEL_RTS_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
12302 #define UARTE_PSEL_RTS_CONNECT_Connected (0UL) /*!< Connect */
12303 #define UARTE_PSEL_RTS_CONNECT_Disconnected (1UL) /*!< Disconnect */
12304 
12305 /* Bits 4..0 : Pin number */
12306 #define UARTE_PSEL_RTS_PIN_Pos (0UL) /*!< Position of PIN field. */
12307 #define UARTE_PSEL_RTS_PIN_Msk (0x1FUL << UARTE_PSEL_RTS_PIN_Pos) /*!< Bit mask of PIN field. */
12308 
12309 /* Register: UARTE_PSEL_TXD */
12310 /* Description: Pin select for TXD signal */
12311 
12312 /* Bit 31 : Connection */
12313 #define UARTE_PSEL_TXD_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
12314 #define UARTE_PSEL_TXD_CONNECT_Msk (0x1UL << UARTE_PSEL_TXD_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
12315 #define UARTE_PSEL_TXD_CONNECT_Connected (0UL) /*!< Connect */
12316 #define UARTE_PSEL_TXD_CONNECT_Disconnected (1UL) /*!< Disconnect */
12317 
12318 /* Bits 4..0 : Pin number */
12319 #define UARTE_PSEL_TXD_PIN_Pos (0UL) /*!< Position of PIN field. */
12320 #define UARTE_PSEL_TXD_PIN_Msk (0x1FUL << UARTE_PSEL_TXD_PIN_Pos) /*!< Bit mask of PIN field. */
12321 
12322 /* Register: UARTE_PSEL_CTS */
12323 /* Description: Pin select for CTS signal */
12324 
12325 /* Bit 31 : Connection */
12326 #define UARTE_PSEL_CTS_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
12327 #define UARTE_PSEL_CTS_CONNECT_Msk (0x1UL << UARTE_PSEL_CTS_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
12328 #define UARTE_PSEL_CTS_CONNECT_Connected (0UL) /*!< Connect */
12329 #define UARTE_PSEL_CTS_CONNECT_Disconnected (1UL) /*!< Disconnect */
12330 
12331 /* Bits 4..0 : Pin number */
12332 #define UARTE_PSEL_CTS_PIN_Pos (0UL) /*!< Position of PIN field. */
12333 #define UARTE_PSEL_CTS_PIN_Msk (0x1FUL << UARTE_PSEL_CTS_PIN_Pos) /*!< Bit mask of PIN field. */
12334 
12335 /* Register: UARTE_PSEL_RXD */
12336 /* Description: Pin select for RXD signal */
12337 
12338 /* Bit 31 : Connection */
12339 #define UARTE_PSEL_RXD_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
12340 #define UARTE_PSEL_RXD_CONNECT_Msk (0x1UL << UARTE_PSEL_RXD_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
12341 #define UARTE_PSEL_RXD_CONNECT_Connected (0UL) /*!< Connect */
12342 #define UARTE_PSEL_RXD_CONNECT_Disconnected (1UL) /*!< Disconnect */
12343 
12344 /* Bits 4..0 : Pin number */
12345 #define UARTE_PSEL_RXD_PIN_Pos (0UL) /*!< Position of PIN field. */
12346 #define UARTE_PSEL_RXD_PIN_Msk (0x1FUL << UARTE_PSEL_RXD_PIN_Pos) /*!< Bit mask of PIN field. */
12347 
12348 /* Register: UARTE_BAUDRATE */
12349 /* Description: Baud rate. Accuracy depends on the HFCLK source selected. */
12350 
12351 /* Bits 31..0 : Baud rate */
12352 #define UARTE_BAUDRATE_BAUDRATE_Pos (0UL) /*!< Position of BAUDRATE field. */
12353 #define UARTE_BAUDRATE_BAUDRATE_Msk (0xFFFFFFFFUL << UARTE_BAUDRATE_BAUDRATE_Pos) /*!< Bit mask of BAUDRATE field. */
12354 #define UARTE_BAUDRATE_BAUDRATE_Baud1200 (0x0004F000UL) /*!< 1200 baud (actual rate: 1205) */
12355 #define UARTE_BAUDRATE_BAUDRATE_Baud2400 (0x0009D000UL) /*!< 2400 baud (actual rate: 2396) */
12356 #define UARTE_BAUDRATE_BAUDRATE_Baud4800 (0x0013B000UL) /*!< 4800 baud (actual rate: 4808) */
12357 #define UARTE_BAUDRATE_BAUDRATE_Baud9600 (0x00275000UL) /*!< 9600 baud (actual rate: 9598) */
12358 #define UARTE_BAUDRATE_BAUDRATE_Baud14400 (0x003AF000UL) /*!< 14400 baud (actual rate: 14401) */
12359 #define UARTE_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL) /*!< 19200 baud (actual rate: 19208) */
12360 #define UARTE_BAUDRATE_BAUDRATE_Baud28800 (0x0075C000UL) /*!< 28800 baud (actual rate: 28777) */
12361 #define UARTE_BAUDRATE_BAUDRATE_Baud31250 (0x00800000UL) /*!< 31250 baud */
12362 #define UARTE_BAUDRATE_BAUDRATE_Baud38400 (0x009D0000UL) /*!< 38400 baud (actual rate: 38369) */
12363 #define UARTE_BAUDRATE_BAUDRATE_Baud56000 (0x00E50000UL) /*!< 56000 baud (actual rate: 55944) */
12364 #define UARTE_BAUDRATE_BAUDRATE_Baud57600 (0x00EB0000UL) /*!< 57600 baud (actual rate: 57554) */
12365 #define UARTE_BAUDRATE_BAUDRATE_Baud76800 (0x013A9000UL) /*!< 76800 baud (actual rate: 76923) */
12366 #define UARTE_BAUDRATE_BAUDRATE_Baud115200 (0x01D60000UL) /*!< 115200 baud (actual rate: 115108) */
12367 #define UARTE_BAUDRATE_BAUDRATE_Baud230400 (0x03B00000UL) /*!< 230400 baud (actual rate: 231884) */
12368 #define UARTE_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL) /*!< 250000 baud */
12369 #define UARTE_BAUDRATE_BAUDRATE_Baud460800 (0x07400000UL) /*!< 460800 baud (actual rate: 457143) */
12370 #define UARTE_BAUDRATE_BAUDRATE_Baud921600 (0x0F000000UL) /*!< 921600 baud (actual rate: 941176) */
12371 #define UARTE_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /*!< 1Mega baud */
12372 
12373 /* Register: UARTE_RXD_PTR */
12374 /* Description: Data pointer */
12375 
12376 /* Bits 31..0 : Data pointer */
12377 #define UARTE_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
12378 #define UARTE_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << UARTE_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
12379 
12380 /* Register: UARTE_RXD_MAXCNT */
12381 /* Description: Maximum number of bytes in receive buffer */
12382 
12383 /* Bits 7..0 : Maximum number of bytes in receive buffer */
12384 #define UARTE_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
12385 #define UARTE_RXD_MAXCNT_MAXCNT_Msk (0xFFUL << UARTE_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
12386 
12387 /* Register: UARTE_RXD_AMOUNT */
12388 /* Description: Number of bytes transferred in the last transaction */
12389 
12390 /* Bits 7..0 : Number of bytes transferred in the last transaction */
12391 #define UARTE_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
12392 #define UARTE_RXD_AMOUNT_AMOUNT_Msk (0xFFUL << UARTE_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
12393 
12394 /* Register: UARTE_TXD_PTR */
12395 /* Description: Data pointer */
12396 
12397 /* Bits 31..0 : Data pointer */
12398 #define UARTE_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
12399 #define UARTE_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << UARTE_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
12400 
12401 /* Register: UARTE_TXD_MAXCNT */
12402 /* Description: Maximum number of bytes in transmit buffer */
12403 
12404 /* Bits 7..0 : Maximum number of bytes in transmit buffer */
12405 #define UARTE_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
12406 #define UARTE_TXD_MAXCNT_MAXCNT_Msk (0xFFUL << UARTE_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
12407 
12408 /* Register: UARTE_TXD_AMOUNT */
12409 /* Description: Number of bytes transferred in the last transaction */
12410 
12411 /* Bits 7..0 : Number of bytes transferred in the last transaction */
12412 #define UARTE_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
12413 #define UARTE_TXD_AMOUNT_AMOUNT_Msk (0xFFUL << UARTE_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
12414 
12415 /* Register: UARTE_CONFIG */
12416 /* Description: Configuration of parity and hardware flow control */
12417 
12418 /* Bits 3..1 : Parity */
12419 #define UARTE_CONFIG_PARITY_Pos (1UL) /*!< Position of PARITY field. */
12420 #define UARTE_CONFIG_PARITY_Msk (0x7UL << UARTE_CONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */
12421 #define UARTE_CONFIG_PARITY_Excluded (0x0UL) /*!< Exclude parity bit */
12422 #define UARTE_CONFIG_PARITY_Included (0x7UL) /*!< Include parity bit */
12423 
12424 /* Bit 0 : Hardware flow control */
12425 #define UARTE_CONFIG_HWFC_Pos (0UL) /*!< Position of HWFC field. */
12426 #define UARTE_CONFIG_HWFC_Msk (0x1UL << UARTE_CONFIG_HWFC_Pos) /*!< Bit mask of HWFC field. */
12427 #define UARTE_CONFIG_HWFC_Disabled (0UL) /*!< Disabled */
12428 #define UARTE_CONFIG_HWFC_Enabled (1UL) /*!< Enabled */
12429 
12430 
12431 /* Peripheral: UICR */
12432 /* Description: User Information Configuration Registers */
12433 
12434 /* Register: UICR_NRFFW */
12435 /* Description: Description collection[0]:  Reserved for Nordic firmware design */
12436 
12437 /* Bits 31..0 : Reserved for Nordic firmware design */
12438 #define UICR_NRFFW_NRFFW_Pos (0UL) /*!< Position of NRFFW field. */
12439 #define UICR_NRFFW_NRFFW_Msk (0xFFFFFFFFUL << UICR_NRFFW_NRFFW_Pos) /*!< Bit mask of NRFFW field. */
12440 
12441 /* Register: UICR_NRFHW */
12442 /* Description: Description collection[0]:  Reserved for Nordic hardware design */
12443 
12444 /* Bits 31..0 : Reserved for Nordic hardware design */
12445 #define UICR_NRFHW_NRFHW_Pos (0UL) /*!< Position of NRFHW field. */
12446 #define UICR_NRFHW_NRFHW_Msk (0xFFFFFFFFUL << UICR_NRFHW_NRFHW_Pos) /*!< Bit mask of NRFHW field. */
12447 
12448 /* Register: UICR_CUSTOMER */
12449 /* Description: Description collection[0]:  Reserved for customer */
12450 
12451 /* Bits 31..0 : Reserved for customer */
12452 #define UICR_CUSTOMER_CUSTOMER_Pos (0UL) /*!< Position of CUSTOMER field. */
12453 #define UICR_CUSTOMER_CUSTOMER_Msk (0xFFFFFFFFUL << UICR_CUSTOMER_CUSTOMER_Pos) /*!< Bit mask of CUSTOMER field. */
12454 
12455 /* Register: UICR_PSELRESET */
12456 /* Description: Description collection[0]:  Mapping of the nRESET function (see POWER chapter for details) */
12457 
12458 /* Bit 31 : Connection */
12459 #define UICR_PSELRESET_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
12460 #define UICR_PSELRESET_CONNECT_Msk (0x1UL << UICR_PSELRESET_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
12461 #define UICR_PSELRESET_CONNECT_Connected (0UL) /*!< Connect */
12462 #define UICR_PSELRESET_CONNECT_Disconnected (1UL) /*!< Disconnect */
12463 
12464 /* Bits 4..0 : GPIO number P0.n onto which Reset is exposed */
12465 #define UICR_PSELRESET_PIN_Pos (0UL) /*!< Position of PIN field. */
12466 #define UICR_PSELRESET_PIN_Msk (0x1FUL << UICR_PSELRESET_PIN_Pos) /*!< Bit mask of PIN field. */
12467 
12468 /* Register: UICR_APPROTECT */
12469 /* Description: Access Port protection */
12470 
12471 /* Bits 7..0 : Enable or disable Access Port protection. Any other value than 0xFF being written to this field will enable protection. */
12472 #define UICR_APPROTECT_PALL_Pos (0UL) /*!< Position of PALL field. */
12473 #define UICR_APPROTECT_PALL_Msk (0xFFUL << UICR_APPROTECT_PALL_Pos) /*!< Bit mask of PALL field. */
12474 #define UICR_APPROTECT_PALL_Enabled (0x00UL) /*!< Enable */
12475 #define UICR_APPROTECT_PALL_Disabled (0xFFUL) /*!< Disable */
12476 
12477 /* Register: UICR_NFCPINS */
12478 /* Description: Setting of pins dedicated to NFC functionality: NFC antenna or GPIO */
12479 
12480 /* Bit 0 : Setting of pins dedicated to NFC functionality */
12481 #define UICR_NFCPINS_PROTECT_Pos (0UL) /*!< Position of PROTECT field. */
12482 #define UICR_NFCPINS_PROTECT_Msk (0x1UL << UICR_NFCPINS_PROTECT_Pos) /*!< Bit mask of PROTECT field. */
12483 #define UICR_NFCPINS_PROTECT_Disabled (0UL) /*!< Operation as GPIO pins. Same protection as normal GPIO pins */
12484 #define UICR_NFCPINS_PROTECT_NFC (1UL) /*!< Operation as NFC antenna pins. Configures the protection for NFC operation */
12485 
12486 
12487 /* Peripheral: WDT */
12488 /* Description: Watchdog Timer */
12489 
12490 /* Register: WDT_INTENSET */
12491 /* Description: Enable interrupt */
12492 
12493 /* Bit 0 : Write '1' to Enable interrupt for TIMEOUT event */
12494 #define WDT_INTENSET_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */
12495 #define WDT_INTENSET_TIMEOUT_Msk (0x1UL << WDT_INTENSET_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */
12496 #define WDT_INTENSET_TIMEOUT_Disabled (0UL) /*!< Read: Disabled */
12497 #define WDT_INTENSET_TIMEOUT_Enabled (1UL) /*!< Read: Enabled */
12498 #define WDT_INTENSET_TIMEOUT_Set (1UL) /*!< Enable */
12499 
12500 /* Register: WDT_INTENCLR */
12501 /* Description: Disable interrupt */
12502 
12503 /* Bit 0 : Write '1' to Disable interrupt for TIMEOUT event */
12504 #define WDT_INTENCLR_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */
12505 #define WDT_INTENCLR_TIMEOUT_Msk (0x1UL << WDT_INTENCLR_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */
12506 #define WDT_INTENCLR_TIMEOUT_Disabled (0UL) /*!< Read: Disabled */
12507 #define WDT_INTENCLR_TIMEOUT_Enabled (1UL) /*!< Read: Enabled */
12508 #define WDT_INTENCLR_TIMEOUT_Clear (1UL) /*!< Disable */
12509 
12510 /* Register: WDT_RUNSTATUS */
12511 /* Description: Run status */
12512 
12513 /* Bit 0 : Indicates whether or not the watchdog is running */
12514 #define WDT_RUNSTATUS_RUNSTATUS_Pos (0UL) /*!< Position of RUNSTATUS field. */
12515 #define WDT_RUNSTATUS_RUNSTATUS_Msk (0x1UL << WDT_RUNSTATUS_RUNSTATUS_Pos) /*!< Bit mask of RUNSTATUS field. */
12516 #define WDT_RUNSTATUS_RUNSTATUS_NotRunning (0UL) /*!< Watchdog not running */
12517 #define WDT_RUNSTATUS_RUNSTATUS_Running (1UL) /*!< Watchdog is running */
12518 
12519 /* Register: WDT_REQSTATUS */
12520 /* Description: Request status */
12521 
12522 /* Bit 7 : Request status for RR[7] register */
12523 #define WDT_REQSTATUS_RR7_Pos (7UL) /*!< Position of RR7 field. */
12524 #define WDT_REQSTATUS_RR7_Msk (0x1UL << WDT_REQSTATUS_RR7_Pos) /*!< Bit mask of RR7 field. */
12525 #define WDT_REQSTATUS_RR7_DisabledOrRequested (0UL) /*!< RR[7] register is not enabled, or are already requesting reload */
12526 #define WDT_REQSTATUS_RR7_EnabledAndUnrequested (1UL) /*!< RR[7] register is enabled, and are not yet requesting reload */
12527 
12528 /* Bit 6 : Request status for RR[6] register */
12529 #define WDT_REQSTATUS_RR6_Pos (6UL) /*!< Position of RR6 field. */
12530 #define WDT_REQSTATUS_RR6_Msk (0x1UL << WDT_REQSTATUS_RR6_Pos) /*!< Bit mask of RR6 field. */
12531 #define WDT_REQSTATUS_RR6_DisabledOrRequested (0UL) /*!< RR[6] register is not enabled, or are already requesting reload */
12532 #define WDT_REQSTATUS_RR6_EnabledAndUnrequested (1UL) /*!< RR[6] register is enabled, and are not yet requesting reload */
12533 
12534 /* Bit 5 : Request status for RR[5] register */
12535 #define WDT_REQSTATUS_RR5_Pos (5UL) /*!< Position of RR5 field. */
12536 #define WDT_REQSTATUS_RR5_Msk (0x1UL << WDT_REQSTATUS_RR5_Pos) /*!< Bit mask of RR5 field. */
12537 #define WDT_REQSTATUS_RR5_DisabledOrRequested (0UL) /*!< RR[5] register is not enabled, or are already requesting reload */
12538 #define WDT_REQSTATUS_RR5_EnabledAndUnrequested (1UL) /*!< RR[5] register is enabled, and are not yet requesting reload */
12539 
12540 /* Bit 4 : Request status for RR[4] register */
12541 #define WDT_REQSTATUS_RR4_Pos (4UL) /*!< Position of RR4 field. */
12542 #define WDT_REQSTATUS_RR4_Msk (0x1UL << WDT_REQSTATUS_RR4_Pos) /*!< Bit mask of RR4 field. */
12543 #define WDT_REQSTATUS_RR4_DisabledOrRequested (0UL) /*!< RR[4] register is not enabled, or are already requesting reload */
12544 #define WDT_REQSTATUS_RR4_EnabledAndUnrequested (1UL) /*!< RR[4] register is enabled, and are not yet requesting reload */
12545 
12546 /* Bit 3 : Request status for RR[3] register */
12547 #define WDT_REQSTATUS_RR3_Pos (3UL) /*!< Position of RR3 field. */
12548 #define WDT_REQSTATUS_RR3_Msk (0x1UL << WDT_REQSTATUS_RR3_Pos) /*!< Bit mask of RR3 field. */
12549 #define WDT_REQSTATUS_RR3_DisabledOrRequested (0UL) /*!< RR[3] register is not enabled, or are already requesting reload */
12550 #define WDT_REQSTATUS_RR3_EnabledAndUnrequested (1UL) /*!< RR[3] register is enabled, and are not yet requesting reload */
12551 
12552 /* Bit 2 : Request status for RR[2] register */
12553 #define WDT_REQSTATUS_RR2_Pos (2UL) /*!< Position of RR2 field. */
12554 #define WDT_REQSTATUS_RR2_Msk (0x1UL << WDT_REQSTATUS_RR2_Pos) /*!< Bit mask of RR2 field. */
12555 #define WDT_REQSTATUS_RR2_DisabledOrRequested (0UL) /*!< RR[2] register is not enabled, or are already requesting reload */
12556 #define WDT_REQSTATUS_RR2_EnabledAndUnrequested (1UL) /*!< RR[2] register is enabled, and are not yet requesting reload */
12557 
12558 /* Bit 1 : Request status for RR[1] register */
12559 #define WDT_REQSTATUS_RR1_Pos (1UL) /*!< Position of RR1 field. */
12560 #define WDT_REQSTATUS_RR1_Msk (0x1UL << WDT_REQSTATUS_RR1_Pos) /*!< Bit mask of RR1 field. */
12561 #define WDT_REQSTATUS_RR1_DisabledOrRequested (0UL) /*!< RR[1] register is not enabled, or are already requesting reload */
12562 #define WDT_REQSTATUS_RR1_EnabledAndUnrequested (1UL) /*!< RR[1] register is enabled, and are not yet requesting reload */
12563 
12564 /* Bit 0 : Request status for RR[0] register */
12565 #define WDT_REQSTATUS_RR0_Pos (0UL) /*!< Position of RR0 field. */
12566 #define WDT_REQSTATUS_RR0_Msk (0x1UL << WDT_REQSTATUS_RR0_Pos) /*!< Bit mask of RR0 field. */
12567 #define WDT_REQSTATUS_RR0_DisabledOrRequested (0UL) /*!< RR[0] register is not enabled, or are already requesting reload */
12568 #define WDT_REQSTATUS_RR0_EnabledAndUnrequested (1UL) /*!< RR[0] register is enabled, and are not yet requesting reload */
12569 
12570 /* Register: WDT_CRV */
12571 /* Description: Counter reload value */
12572 
12573 /* Bits 31..0 : Counter reload value in number of cycles of the 32.768 kHz clock */
12574 #define WDT_CRV_CRV_Pos (0UL) /*!< Position of CRV field. */
12575 #define WDT_CRV_CRV_Msk (0xFFFFFFFFUL << WDT_CRV_CRV_Pos) /*!< Bit mask of CRV field. */
12576 
12577 /* Register: WDT_RREN */
12578 /* Description: Enable register for reload request registers */
12579 
12580 /* Bit 7 : Enable or disable RR[7] register */
12581 #define WDT_RREN_RR7_Pos (7UL) /*!< Position of RR7 field. */
12582 #define WDT_RREN_RR7_Msk (0x1UL << WDT_RREN_RR7_Pos) /*!< Bit mask of RR7 field. */
12583 #define WDT_RREN_RR7_Disabled (0UL) /*!< Disable RR[7] register */
12584 #define WDT_RREN_RR7_Enabled (1UL) /*!< Enable RR[7] register */
12585 
12586 /* Bit 6 : Enable or disable RR[6] register */
12587 #define WDT_RREN_RR6_Pos (6UL) /*!< Position of RR6 field. */
12588 #define WDT_RREN_RR6_Msk (0x1UL << WDT_RREN_RR6_Pos) /*!< Bit mask of RR6 field. */
12589 #define WDT_RREN_RR6_Disabled (0UL) /*!< Disable RR[6] register */
12590 #define WDT_RREN_RR6_Enabled (1UL) /*!< Enable RR[6] register */
12591 
12592 /* Bit 5 : Enable or disable RR[5] register */
12593 #define WDT_RREN_RR5_Pos (5UL) /*!< Position of RR5 field. */
12594 #define WDT_RREN_RR5_Msk (0x1UL << WDT_RREN_RR5_Pos) /*!< Bit mask of RR5 field. */
12595 #define WDT_RREN_RR5_Disabled (0UL) /*!< Disable RR[5] register */
12596 #define WDT_RREN_RR5_Enabled (1UL) /*!< Enable RR[5] register */
12597 
12598 /* Bit 4 : Enable or disable RR[4] register */
12599 #define WDT_RREN_RR4_Pos (4UL) /*!< Position of RR4 field. */
12600 #define WDT_RREN_RR4_Msk (0x1UL << WDT_RREN_RR4_Pos) /*!< Bit mask of RR4 field. */
12601 #define WDT_RREN_RR4_Disabled (0UL) /*!< Disable RR[4] register */
12602 #define WDT_RREN_RR4_Enabled (1UL) /*!< Enable RR[4] register */
12603 
12604 /* Bit 3 : Enable or disable RR[3] register */
12605 #define WDT_RREN_RR3_Pos (3UL) /*!< Position of RR3 field. */
12606 #define WDT_RREN_RR3_Msk (0x1UL << WDT_RREN_RR3_Pos) /*!< Bit mask of RR3 field. */
12607 #define WDT_RREN_RR3_Disabled (0UL) /*!< Disable RR[3] register */
12608 #define WDT_RREN_RR3_Enabled (1UL) /*!< Enable RR[3] register */
12609 
12610 /* Bit 2 : Enable or disable RR[2] register */
12611 #define WDT_RREN_RR2_Pos (2UL) /*!< Position of RR2 field. */
12612 #define WDT_RREN_RR2_Msk (0x1UL << WDT_RREN_RR2_Pos) /*!< Bit mask of RR2 field. */
12613 #define WDT_RREN_RR2_Disabled (0UL) /*!< Disable RR[2] register */
12614 #define WDT_RREN_RR2_Enabled (1UL) /*!< Enable RR[2] register */
12615 
12616 /* Bit 1 : Enable or disable RR[1] register */
12617 #define WDT_RREN_RR1_Pos (1UL) /*!< Position of RR1 field. */
12618 #define WDT_RREN_RR1_Msk (0x1UL << WDT_RREN_RR1_Pos) /*!< Bit mask of RR1 field. */
12619 #define WDT_RREN_RR1_Disabled (0UL) /*!< Disable RR[1] register */
12620 #define WDT_RREN_RR1_Enabled (1UL) /*!< Enable RR[1] register */
12621 
12622 /* Bit 0 : Enable or disable RR[0] register */
12623 #define WDT_RREN_RR0_Pos (0UL) /*!< Position of RR0 field. */
12624 #define WDT_RREN_RR0_Msk (0x1UL << WDT_RREN_RR0_Pos) /*!< Bit mask of RR0 field. */
12625 #define WDT_RREN_RR0_Disabled (0UL) /*!< Disable RR[0] register */
12626 #define WDT_RREN_RR0_Enabled (1UL) /*!< Enable RR[0] register */
12627 
12628 /* Register: WDT_CONFIG */
12629 /* Description: Configuration register */
12630 
12631 /* Bit 3 : Configure the watchdog to either be paused, or kept running, while the CPU is halted by the debugger */
12632 #define WDT_CONFIG_HALT_Pos (3UL) /*!< Position of HALT field. */
12633 #define WDT_CONFIG_HALT_Msk (0x1UL << WDT_CONFIG_HALT_Pos) /*!< Bit mask of HALT field. */
12634 #define WDT_CONFIG_HALT_Pause (0UL) /*!< Pause watchdog while the CPU is halted by the debugger */
12635 #define WDT_CONFIG_HALT_Run (1UL) /*!< Keep the watchdog running while the CPU is halted by the debugger */
12636 
12637 /* Bit 0 : Configure the watchdog to either be paused, or kept running, while the CPU is sleeping */
12638 #define WDT_CONFIG_SLEEP_Pos (0UL) /*!< Position of SLEEP field. */
12639 #define WDT_CONFIG_SLEEP_Msk (0x1UL << WDT_CONFIG_SLEEP_Pos) /*!< Bit mask of SLEEP field. */
12640 #define WDT_CONFIG_SLEEP_Pause (0UL) /*!< Pause watchdog while the CPU is sleeping */
12641 #define WDT_CONFIG_SLEEP_Run (1UL) /*!< Keep the watchdog running while the CPU is sleeping */
12642 
12643 /* Register: WDT_RR */
12644 /* Description: Description collection[0]:  Reload request 0 */
12645 
12646 /* Bits 31..0 : Reload request register */
12647 #define WDT_RR_RR_Pos (0UL) /*!< Position of RR field. */
12648 #define WDT_RR_RR_Msk (0xFFFFFFFFUL << WDT_RR_RR_Pos) /*!< Bit mask of RR field. */
12649 #define WDT_RR_RR_Reload (0x6E524635UL) /*!< Value to request a reload of the watchdog timer */
12650 
12651 
12652 /*lint --flb "Leave library region" */
12653 #endif
12654