1 /*! 2 * \file sx1276Regs-LoRa.h 3 * 4 * \brief SX1276 LoRa modem registers and bits definitions 5 * 6 * \copyright Revised BSD License, see section \ref LICENSE. 7 * 8 * \code 9 * ______ _ 10 * / _____) _ | | 11 * ( (____ _____ ____ _| |_ _____ ____| |__ 12 * \____ \| ___ | (_ _) ___ |/ ___) _ \ 13 * _____) ) ____| | | || |_| ____( (___| | | | 14 * (______/|_____)_|_|_| \__)_____)\____)_| |_| 15 * (C)2013-2017 Semtech 16 * 17 * \endcode 18 * 19 * \author Miguel Luis ( Semtech ) 20 * 21 * \author Gregory Cristian ( Semtech ) 22 */ 23 #ifndef __SX1276_REGS_LORA_H__ 24 #define __SX1276_REGS_LORA_H__ 25 26 #ifdef __cplusplus 27 extern "C" 28 { 29 #endif 30 31 /*! 32 * ============================================================================ 33 * SX1276 Internal registers Address 34 * ============================================================================ 35 */ 36 #define REG_LR_FIFO 0x00 37 // Common settings 38 #define REG_LR_OPMODE 0x01 39 #define REG_LR_FRFMSB 0x06 40 #define REG_LR_FRFMID 0x07 41 #define REG_LR_FRFLSB 0x08 42 // Tx settings 43 #define REG_LR_PACONFIG 0x09 44 #define REG_LR_PARAMP 0x0A 45 #define REG_LR_OCP 0x0B 46 // Rx settings 47 #define REG_LR_LNA 0x0C 48 // LoRa registers 49 #define REG_LR_FIFOADDRPTR 0x0D 50 #define REG_LR_FIFOTXBASEADDR 0x0E 51 #define REG_LR_FIFORXBASEADDR 0x0F 52 #define REG_LR_FIFORXCURRENTADDR 0x10 53 #define REG_LR_IRQFLAGSMASK 0x11 54 #define REG_LR_IRQFLAGS 0x12 55 #define REG_LR_RXNBBYTES 0x13 56 #define REG_LR_RXHEADERCNTVALUEMSB 0x14 57 #define REG_LR_RXHEADERCNTVALUELSB 0x15 58 #define REG_LR_RXPACKETCNTVALUEMSB 0x16 59 #define REG_LR_RXPACKETCNTVALUELSB 0x17 60 #define REG_LR_MODEMSTAT 0x18 61 #define REG_LR_PKTSNRVALUE 0x19 62 #define REG_LR_PKTRSSIVALUE 0x1A 63 #define REG_LR_RSSIVALUE 0x1B 64 #define REG_LR_HOPCHANNEL 0x1C 65 #define REG_LR_MODEMCONFIG1 0x1D 66 #define REG_LR_MODEMCONFIG2 0x1E 67 #define REG_LR_SYMBTIMEOUTLSB 0x1F 68 #define REG_LR_PREAMBLEMSB 0x20 69 #define REG_LR_PREAMBLELSB 0x21 70 #define REG_LR_PAYLOADLENGTH 0x22 71 #define REG_LR_PAYLOADMAXLENGTH 0x23 72 #define REG_LR_HOPPERIOD 0x24 73 #define REG_LR_FIFORXBYTEADDR 0x25 74 #define REG_LR_MODEMCONFIG3 0x26 75 #define REG_LR_FEIMSB 0x28 76 #define REG_LR_FEIMID 0x29 77 #define REG_LR_FEILSB 0x2A 78 #define REG_LR_RSSIWIDEBAND 0x2C 79 #define REG_LR_IFFREQ1 0x2F 80 #define REG_LR_IFFREQ2 0x30 81 #define REG_LR_DETECTOPTIMIZE 0x31 82 #define REG_LR_INVERTIQ 0x33 83 #define REG_LR_HIGHBWOPTIMIZE1 0x36 84 #define REG_LR_DETECTIONTHRESHOLD 0x37 85 #define REG_LR_SYNCWORD 0x39 86 #define REG_LR_HIGHBWOPTIMIZE2 0x3A 87 #define REG_LR_INVERTIQ2 0x3B 88 89 // end of documented register in datasheet 90 // I/O settings 91 #define REG_LR_DIOMAPPING1 0x40 92 #define REG_LR_DIOMAPPING2 0x41 93 // Version 94 #define REG_LR_VERSION 0x42 95 // Additional settings 96 #define REG_LR_PLLHOP 0x44 97 #define REG_LR_TCXO 0x4B 98 #define REG_LR_PADAC 0x4D 99 #define REG_LR_FORMERTEMP 0x5B 100 #define REG_LR_BITRATEFRAC 0x5D 101 #define REG_LR_AGCREF 0x61 102 #define REG_LR_AGCTHRESH1 0x62 103 #define REG_LR_AGCTHRESH2 0x63 104 #define REG_LR_AGCTHRESH3 0x64 105 #define REG_LR_PLL 0x70 106 107 /*! 108 * ============================================================================ 109 * SX1276 LoRa bits control definition 110 * ============================================================================ 111 */ 112 113 /*! 114 * RegFifo 115 */ 116 117 /*! 118 * RegOpMode 119 */ 120 #define RFLR_OPMODE_LONGRANGEMODE_MASK 0x7F 121 #define RFLR_OPMODE_LONGRANGEMODE_OFF 0x00 // Default 122 #define RFLR_OPMODE_LONGRANGEMODE_ON 0x80 123 124 #define RFLR_OPMODE_ACCESSSHAREDREG_MASK 0xBF 125 #define RFLR_OPMODE_ACCESSSHAREDREG_ENABLE 0x40 126 #define RFLR_OPMODE_ACCESSSHAREDREG_DISABLE 0x00 // Default 127 128 #define RFLR_OPMODE_FREQMODE_ACCESS_MASK 0xF7 129 #define RFLR_OPMODE_FREQMODE_ACCESS_LF 0x08 // Default 130 #define RFLR_OPMODE_FREQMODE_ACCESS_HF 0x00 131 132 #define RFLR_OPMODE_MASK 0xF8 133 #define RFLR_OPMODE_SLEEP 0x00 134 #define RFLR_OPMODE_STANDBY 0x01 // Default 135 #define RFLR_OPMODE_SYNTHESIZER_TX 0x02 136 #define RFLR_OPMODE_TRANSMITTER 0x03 137 #define RFLR_OPMODE_SYNTHESIZER_RX 0x04 138 #define RFLR_OPMODE_RECEIVER 0x05 139 // LoRa specific modes 140 #define RFLR_OPMODE_RECEIVER_SINGLE 0x06 141 #define RFLR_OPMODE_CAD 0x07 142 143 /*! 144 * RegFrf (MHz) 145 */ 146 #define RFLR_FRFMSB_434_MHZ 0x6C // Default 147 #define RFLR_FRFMID_434_MHZ 0x80 // Default 148 #define RFLR_FRFLSB_434_MHZ 0x00 // Default 149 150 /*! 151 * RegPaConfig 152 */ 153 #define RFLR_PACONFIG_PASELECT_MASK 0x7F 154 #define RFLR_PACONFIG_PASELECT_PABOOST 0x80 155 #define RFLR_PACONFIG_PASELECT_RFO 0x00 // Default 156 157 #define RFLR_PACONFIG_MAX_POWER_MASK 0x8F 158 159 #define RFLR_PACONFIG_OUTPUTPOWER_MASK 0xF0 160 161 /*! 162 * RegPaRamp 163 */ 164 #define RFLR_PARAMP_TXBANDFORCE_MASK 0xEF 165 #define RFLR_PARAMP_TXBANDFORCE_BAND_SEL 0x10 166 #define RFLR_PARAMP_TXBANDFORCE_AUTO 0x00 // Default 167 168 #define RFLR_PARAMP_MASK 0xF0 169 #define RFLR_PARAMP_3400_US 0x00 170 #define RFLR_PARAMP_2000_US 0x01 171 #define RFLR_PARAMP_1000_US 0x02 172 #define RFLR_PARAMP_0500_US 0x03 173 #define RFLR_PARAMP_0250_US 0x04 174 #define RFLR_PARAMP_0125_US 0x05 175 #define RFLR_PARAMP_0100_US 0x06 176 #define RFLR_PARAMP_0062_US 0x07 177 #define RFLR_PARAMP_0050_US 0x08 178 #define RFLR_PARAMP_0040_US 0x09 // Default 179 #define RFLR_PARAMP_0031_US 0x0A 180 #define RFLR_PARAMP_0025_US 0x0B 181 #define RFLR_PARAMP_0020_US 0x0C 182 #define RFLR_PARAMP_0015_US 0x0D 183 #define RFLR_PARAMP_0012_US 0x0E 184 #define RFLR_PARAMP_0010_US 0x0F 185 186 /*! 187 * RegOcp 188 */ 189 #define RFLR_OCP_MASK 0xDF 190 #define RFLR_OCP_ON 0x20 // Default 191 #define RFLR_OCP_OFF 0x00 192 193 #define RFLR_OCP_TRIM_MASK 0xE0 194 #define RFLR_OCP_TRIM_045_MA 0x00 195 #define RFLR_OCP_TRIM_050_MA 0x01 196 #define RFLR_OCP_TRIM_055_MA 0x02 197 #define RFLR_OCP_TRIM_060_MA 0x03 198 #define RFLR_OCP_TRIM_065_MA 0x04 199 #define RFLR_OCP_TRIM_070_MA 0x05 200 #define RFLR_OCP_TRIM_075_MA 0x06 201 #define RFLR_OCP_TRIM_080_MA 0x07 202 #define RFLR_OCP_TRIM_085_MA 0x08 203 #define RFLR_OCP_TRIM_090_MA 0x09 204 #define RFLR_OCP_TRIM_095_MA 0x0A 205 #define RFLR_OCP_TRIM_100_MA 0x0B // Default 206 #define RFLR_OCP_TRIM_105_MA 0x0C 207 #define RFLR_OCP_TRIM_110_MA 0x0D 208 #define RFLR_OCP_TRIM_115_MA 0x0E 209 #define RFLR_OCP_TRIM_120_MA 0x0F 210 #define RFLR_OCP_TRIM_130_MA 0x10 211 #define RFLR_OCP_TRIM_140_MA 0x11 212 #define RFLR_OCP_TRIM_150_MA 0x12 213 #define RFLR_OCP_TRIM_160_MA 0x13 214 #define RFLR_OCP_TRIM_170_MA 0x14 215 #define RFLR_OCP_TRIM_180_MA 0x15 216 #define RFLR_OCP_TRIM_190_MA 0x16 217 #define RFLR_OCP_TRIM_200_MA 0x17 218 #define RFLR_OCP_TRIM_210_MA 0x18 219 #define RFLR_OCP_TRIM_220_MA 0x19 220 #define RFLR_OCP_TRIM_230_MA 0x1A 221 #define RFLR_OCP_TRIM_240_MA 0x1B 222 223 /*! 224 * RegLna 225 */ 226 #define RFLR_LNA_GAIN_MASK 0x1F 227 #define RFLR_LNA_GAIN_G1 0x20 // Default 228 #define RFLR_LNA_GAIN_G2 0x40 229 #define RFLR_LNA_GAIN_G3 0x60 230 #define RFLR_LNA_GAIN_G4 0x80 231 #define RFLR_LNA_GAIN_G5 0xA0 232 #define RFLR_LNA_GAIN_G6 0xC0 233 234 #define RFLR_LNA_BOOST_LF_MASK 0xE7 235 #define RFLR_LNA_BOOST_LF_DEFAULT 0x00 // Default 236 237 #define RFLR_LNA_BOOST_HF_MASK 0xFC 238 #define RFLR_LNA_BOOST_HF_OFF 0x00 // Default 239 #define RFLR_LNA_BOOST_HF_ON 0x03 240 241 /*! 242 * RegFifoAddrPtr 243 */ 244 #define RFLR_FIFOADDRPTR 0x00 // Default 245 246 /*! 247 * RegFifoTxBaseAddr 248 */ 249 #define RFLR_FIFOTXBASEADDR 0x80 // Default 250 251 /*! 252 * RegFifoTxBaseAddr 253 */ 254 #define RFLR_FIFORXBASEADDR 0x00 // Default 255 256 /*! 257 * RegFifoRxCurrentAddr (Read Only) 258 */ 259 260 /*! 261 * RegIrqFlagsMask 262 */ 263 #define RFLR_IRQFLAGS_RXTIMEOUT_MASK 0x80 264 #define RFLR_IRQFLAGS_RXDONE_MASK 0x40 265 #define RFLR_IRQFLAGS_PAYLOADCRCERROR_MASK 0x20 266 #define RFLR_IRQFLAGS_VALIDHEADER_MASK 0x10 267 #define RFLR_IRQFLAGS_TXDONE_MASK 0x08 268 #define RFLR_IRQFLAGS_CADDONE_MASK 0x04 269 #define RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL_MASK 0x02 270 #define RFLR_IRQFLAGS_CADDETECTED_MASK 0x01 271 272 /*! 273 * RegIrqFlags 274 */ 275 #define RFLR_IRQFLAGS_RXTIMEOUT 0x80 276 #define RFLR_IRQFLAGS_RXDONE 0x40 277 #define RFLR_IRQFLAGS_PAYLOADCRCERROR 0x20 278 #define RFLR_IRQFLAGS_VALIDHEADER 0x10 279 #define RFLR_IRQFLAGS_TXDONE 0x08 280 #define RFLR_IRQFLAGS_CADDONE 0x04 281 #define RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL 0x02 282 #define RFLR_IRQFLAGS_CADDETECTED 0x01 283 284 /*! 285 * RegFifoRxNbBytes (Read Only) 286 */ 287 288 /*! 289 * RegRxHeaderCntValueMsb (Read Only) 290 */ 291 292 /*! 293 * RegRxHeaderCntValueLsb (Read Only) 294 */ 295 296 /*! 297 * RegRxPacketCntValueMsb (Read Only) 298 */ 299 300 /*! 301 * RegRxPacketCntValueLsb (Read Only) 302 */ 303 304 /*! 305 * RegModemStat (Read Only) 306 */ 307 #define RFLR_MODEMSTAT_RX_CR_MASK 0x1F 308 #define RFLR_MODEMSTAT_MODEM_STATUS_MASK 0xE0 309 310 /*! 311 * RegPktSnrValue (Read Only) 312 */ 313 314 /*! 315 * RegPktRssiValue (Read Only) 316 */ 317 318 /*! 319 * RegRssiValue (Read Only) 320 */ 321 322 /*! 323 * RegHopChannel (Read Only) 324 */ 325 #define RFLR_HOPCHANNEL_PLL_LOCK_TIMEOUT_MASK 0x7F 326 #define RFLR_HOPCHANNEL_PLL_LOCK_FAIL 0x80 327 #define RFLR_HOPCHANNEL_PLL_LOCK_SUCCEED 0x00 // Default 328 329 #define RFLR_HOPCHANNEL_CRCONPAYLOAD_MASK 0xBF 330 #define RFLR_HOPCHANNEL_CRCONPAYLOAD_ON 0x40 331 #define RFLR_HOPCHANNEL_CRCONPAYLOAD_OFF 0x00 // Default 332 333 #define RFLR_HOPCHANNEL_CHANNEL_MASK 0x3F 334 335 /*! 336 * RegModemConfig1 337 */ 338 #define RFLR_MODEMCONFIG1_BW_MASK 0x0F 339 #define RFLR_MODEMCONFIG1_BW_7_81_KHZ 0x00 340 #define RFLR_MODEMCONFIG1_BW_10_41_KHZ 0x10 341 #define RFLR_MODEMCONFIG1_BW_15_62_KHZ 0x20 342 #define RFLR_MODEMCONFIG1_BW_20_83_KHZ 0x30 343 #define RFLR_MODEMCONFIG1_BW_31_25_KHZ 0x40 344 #define RFLR_MODEMCONFIG1_BW_41_66_KHZ 0x50 345 #define RFLR_MODEMCONFIG1_BW_62_50_KHZ 0x60 346 #define RFLR_MODEMCONFIG1_BW_125_KHZ 0x70 // Default 347 #define RFLR_MODEMCONFIG1_BW_250_KHZ 0x80 348 #define RFLR_MODEMCONFIG1_BW_500_KHZ 0x90 349 350 #define RFLR_MODEMCONFIG1_CODINGRATE_MASK 0xF1 351 #define RFLR_MODEMCONFIG1_CODINGRATE_4_5 0x02 352 #define RFLR_MODEMCONFIG1_CODINGRATE_4_6 0x04 // Default 353 #define RFLR_MODEMCONFIG1_CODINGRATE_4_7 0x06 354 #define RFLR_MODEMCONFIG1_CODINGRATE_4_8 0x08 355 356 #define RFLR_MODEMCONFIG1_IMPLICITHEADER_MASK 0xFE 357 #define RFLR_MODEMCONFIG1_IMPLICITHEADER_ON 0x01 358 #define RFLR_MODEMCONFIG1_IMPLICITHEADER_OFF 0x00 // Default 359 360 /*! 361 * RegModemConfig2 362 */ 363 #define RFLR_MODEMCONFIG2_SF_MASK 0x0F 364 #define RFLR_MODEMCONFIG2_SF_6 0x60 365 #define RFLR_MODEMCONFIG2_SF_7 0x70 // Default 366 #define RFLR_MODEMCONFIG2_SF_8 0x80 367 #define RFLR_MODEMCONFIG2_SF_9 0x90 368 #define RFLR_MODEMCONFIG2_SF_10 0xA0 369 #define RFLR_MODEMCONFIG2_SF_11 0xB0 370 #define RFLR_MODEMCONFIG2_SF_12 0xC0 371 372 #define RFLR_MODEMCONFIG2_TXCONTINUOUSMODE_MASK 0xF7 373 #define RFLR_MODEMCONFIG2_TXCONTINUOUSMODE_ON 0x08 374 #define RFLR_MODEMCONFIG2_TXCONTINUOUSMODE_OFF 0x00 375 376 #define RFLR_MODEMCONFIG2_RXPAYLOADCRC_MASK 0xFB 377 #define RFLR_MODEMCONFIG2_RXPAYLOADCRC_ON 0x04 378 #define RFLR_MODEMCONFIG2_RXPAYLOADCRC_OFF 0x00 // Default 379 380 #define RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK 0xFC 381 #define RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB 0x00 // Default 382 383 /*! 384 * RegSymbTimeoutLsb 385 */ 386 #define RFLR_SYMBTIMEOUTLSB_SYMBTIMEOUT 0x64 // Default 387 388 /*! 389 * RegPreambleLengthMsb 390 */ 391 #define RFLR_PREAMBLELENGTHMSB 0x00 // Default 392 393 /*! 394 * RegPreambleLengthLsb 395 */ 396 #define RFLR_PREAMBLELENGTHLSB 0x08 // Default 397 398 /*! 399 * RegPayloadLength 400 */ 401 #define RFLR_PAYLOADLENGTH 0x0E // Default 402 403 /*! 404 * RegPayloadMaxLength 405 */ 406 #define RFLR_PAYLOADMAXLENGTH 0xFF // Default 407 408 /*! 409 * RegHopPeriod 410 */ 411 #define RFLR_HOPPERIOD_FREQFOPPINGPERIOD 0x00 // Default 412 413 /*! 414 * RegFifoRxByteAddr (Read Only) 415 */ 416 417 /*! 418 * RegModemConfig3 419 */ 420 #define RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_MASK 0xF7 421 #define RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_ON 0x08 422 #define RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_OFF 0x00 // Default 423 424 #define RFLR_MODEMCONFIG3_AGCAUTO_MASK 0xFB 425 #define RFLR_MODEMCONFIG3_AGCAUTO_ON 0x04 // Default 426 #define RFLR_MODEMCONFIG3_AGCAUTO_OFF 0x00 427 428 /*! 429 * RegFeiMsb (Read Only) 430 */ 431 432 /*! 433 * RegFeiMid (Read Only) 434 */ 435 436 /*! 437 * RegFeiLsb (Read Only) 438 */ 439 440 /*! 441 * RegRssiWideband (Read Only) 442 */ 443 444 /*! 445 * RegDetectOptimize 446 */ 447 #define RFLR_DETECTIONOPTIMIZE_MASK 0xF8 448 #define RFLR_DETECTIONOPTIMIZE_SF7_TO_SF12 0x03 // Default 449 #define RFLR_DETECTIONOPTIMIZE_SF6 0x05 450 451 /*! 452 * RegInvertIQ 453 */ 454 #define RFLR_INVERTIQ_RX_MASK 0xBF 455 #define RFLR_INVERTIQ_RX_OFF 0x00 456 #define RFLR_INVERTIQ_RX_ON 0x40 457 #define RFLR_INVERTIQ_TX_MASK 0xFE 458 #define RFLR_INVERTIQ_TX_OFF 0x01 459 #define RFLR_INVERTIQ_TX_ON 0x00 460 461 /*! 462 * RegDetectionThreshold 463 */ 464 #define RFLR_DETECTIONTHRESH_SF7_TO_SF12 0x0A // Default 465 #define RFLR_DETECTIONTHRESH_SF6 0x0C 466 467 /*! 468 * RegInvertIQ2 469 */ 470 #define RFLR_INVERTIQ2_ON 0x19 471 #define RFLR_INVERTIQ2_OFF 0x1D 472 473 /*! 474 * RegDioMapping1 475 */ 476 #define RFLR_DIOMAPPING1_DIO0_MASK 0x3F 477 #define RFLR_DIOMAPPING1_DIO0_00 0x00 // Default 478 #define RFLR_DIOMAPPING1_DIO0_01 0x40 479 #define RFLR_DIOMAPPING1_DIO0_10 0x80 480 #define RFLR_DIOMAPPING1_DIO0_11 0xC0 481 482 #define RFLR_DIOMAPPING1_DIO1_MASK 0xCF 483 #define RFLR_DIOMAPPING1_DIO1_00 0x00 // Default 484 #define RFLR_DIOMAPPING1_DIO1_01 0x10 485 #define RFLR_DIOMAPPING1_DIO1_10 0x20 486 #define RFLR_DIOMAPPING1_DIO1_11 0x30 487 488 #define RFLR_DIOMAPPING1_DIO2_MASK 0xF3 489 #define RFLR_DIOMAPPING1_DIO2_00 0x00 // Default 490 #define RFLR_DIOMAPPING1_DIO2_01 0x04 491 #define RFLR_DIOMAPPING1_DIO2_10 0x08 492 #define RFLR_DIOMAPPING1_DIO2_11 0x0C 493 494 #define RFLR_DIOMAPPING1_DIO3_MASK 0xFC 495 #define RFLR_DIOMAPPING1_DIO3_00 0x00 // Default 496 #define RFLR_DIOMAPPING1_DIO3_01 0x01 497 #define RFLR_DIOMAPPING1_DIO3_10 0x02 498 #define RFLR_DIOMAPPING1_DIO3_11 0x03 499 500 /*! 501 * RegDioMapping2 502 */ 503 #define RFLR_DIOMAPPING2_DIO4_MASK 0x3F 504 #define RFLR_DIOMAPPING2_DIO4_00 0x00 // Default 505 #define RFLR_DIOMAPPING2_DIO4_01 0x40 506 #define RFLR_DIOMAPPING2_DIO4_10 0x80 507 #define RFLR_DIOMAPPING2_DIO4_11 0xC0 508 509 #define RFLR_DIOMAPPING2_DIO5_MASK 0xCF 510 #define RFLR_DIOMAPPING2_DIO5_00 0x00 // Default 511 #define RFLR_DIOMAPPING2_DIO5_01 0x10 512 #define RFLR_DIOMAPPING2_DIO5_10 0x20 513 #define RFLR_DIOMAPPING2_DIO5_11 0x30 514 515 #define RFLR_DIOMAPPING2_MAP_MASK 0xFE 516 #define RFLR_DIOMAPPING2_MAP_PREAMBLEDETECT 0x01 517 #define RFLR_DIOMAPPING2_MAP_RSSI 0x00 // Default 518 519 /*! 520 * RegVersion (Read Only) 521 */ 522 523 /*! 524 * RegPllHop 525 */ 526 #define RFLR_PLLHOP_FASTHOP_MASK 0x7F 527 #define RFLR_PLLHOP_FASTHOP_ON 0x80 528 #define RFLR_PLLHOP_FASTHOP_OFF 0x00 // Default 529 530 /*! 531 * RegTcxo 532 */ 533 #define RFLR_TCXO_TCXOINPUT_MASK 0xEF 534 #define RFLR_TCXO_TCXOINPUT_ON 0x10 535 #define RFLR_TCXO_TCXOINPUT_OFF 0x00 // Default 536 537 /*! 538 * RegPaDac 539 */ 540 #define RFLR_PADAC_20DBM_MASK 0xF8 541 #define RFLR_PADAC_20DBM_ON 0x07 542 #define RFLR_PADAC_20DBM_OFF 0x04 // Default 543 544 /*! 545 * RegFormerTemp 546 */ 547 548 /*! 549 * RegBitrateFrac 550 */ 551 #define RF_BITRATEFRAC_MASK 0xF0 552 553 /*! 554 * RegAgcRef 555 */ 556 557 /*! 558 * RegAgcThresh1 559 */ 560 561 /*! 562 * RegAgcThresh2 563 */ 564 565 /*! 566 * RegAgcThresh3 567 */ 568 569 /*! 570 * RegPll 571 */ 572 #define RF_PLL_BANDWIDTH_MASK 0x3F 573 #define RF_PLL_BANDWIDTH_75 0x00 574 #define RF_PLL_BANDWIDTH_150 0x40 575 #define RF_PLL_BANDWIDTH_225 0x80 576 #define RF_PLL_BANDWIDTH_300 0xC0 // Default 577 578 #ifdef __cplusplus 579 } 580 #endif 581 582 #endif // __SX1276_REGS_LORA_H__ 583
