1 /*! 2 * \file sx1272Regs-LoRa.h 3 * 4 * \brief SX1272 LoRa modem registers and bits definitions 5 * 6 * \copyright Revised BSD License, see section \ref LICENSE. 7 * 8 * \code 9 * ______ _ 10 * / _____) _ | | 11 * ( (____ _____ ____ _| |_ _____ ____| |__ 12 * \____ \| ___ | (_ _) ___ |/ ___) _ \ 13 * _____) ) ____| | | || |_| ____( (___| | | | 14 * (______/|_____)_|_|_| \__)_____)\____)_| |_| 15 * (C)2013-2017 Semtech 16 * 17 * \endcode 18 * 19 * \author Miguel Luis ( Semtech ) 20 * 21 * \author Gregory Cristian ( Semtech ) 22 */ 23 #ifndef __SX1272_REGS_LORA_H__ 24 #define __SX1272_REGS_LORA_H__ 25 26 #ifdef __cplusplus 27 extern "C" 28 { 29 #endif 30 31 /*! 32 * ============================================================================ 33 * SX1272 Internal registers Address 34 * ============================================================================ 35 */ 36 #define REG_LR_FIFO 0x00 37 // Common settings 38 #define REG_LR_OPMODE 0x01 39 #define REG_LR_FRFMSB 0x06 40 #define REG_LR_FRFMID 0x07 41 #define REG_LR_FRFLSB 0x08 42 // Tx settings 43 #define REG_LR_PACONFIG 0x09 44 #define REG_LR_PARAMP 0x0A 45 #define REG_LR_OCP 0x0B 46 // Rx settings 47 #define REG_LR_LNA 0x0C 48 // LoRa registers 49 #define REG_LR_FIFOADDRPTR 0x0D 50 #define REG_LR_FIFOTXBASEADDR 0x0E 51 #define REG_LR_FIFORXBASEADDR 0x0F 52 #define REG_LR_FIFORXCURRENTADDR 0x10 53 #define REG_LR_IRQFLAGSMASK 0x11 54 #define REG_LR_IRQFLAGS 0x12 55 #define REG_LR_RXNBBYTES 0x13 56 #define REG_LR_RXHEADERCNTVALUEMSB 0x14 57 #define REG_LR_RXHEADERCNTVALUELSB 0x15 58 #define REG_LR_RXPACKETCNTVALUEMSB 0x16 59 #define REG_LR_RXPACKETCNTVALUELSB 0x17 60 #define REG_LR_MODEMSTAT 0x18 61 #define REG_LR_PKTSNRVALUE 0x19 62 #define REG_LR_PKTRSSIVALUE 0x1A 63 #define REG_LR_RSSIVALUE 0x1B 64 #define REG_LR_HOPCHANNEL 0x1C 65 #define REG_LR_MODEMCONFIG1 0x1D 66 #define REG_LR_MODEMCONFIG2 0x1E 67 #define REG_LR_SYMBTIMEOUTLSB 0x1F 68 #define REG_LR_PREAMBLEMSB 0x20 69 #define REG_LR_PREAMBLELSB 0x21 70 #define REG_LR_PAYLOADLENGTH 0x22 71 #define REG_LR_PAYLOADMAXLENGTH 0x23 72 #define REG_LR_HOPPERIOD 0x24 73 #define REG_LR_FIFORXBYTEADDR 0x25 74 #define REG_LR_FEIMSB 0x28 75 #define REG_LR_FEIMID 0x29 76 #define REG_LR_FEILSB 0x2A 77 #define REG_LR_RSSIWIDEBAND 0x2C 78 #define REG_LR_DETECTOPTIMIZE 0x31 79 #define REG_LR_INVERTIQ 0x33 80 #define REG_LR_DETECTIONTHRESHOLD 0x37 81 #define REG_LR_SYNCWORD 0x39 82 #define REG_LR_INVERTIQ2 0x3B 83 84 // end of documented register in datasheet 85 // I/O settings 86 #define REG_LR_DIOMAPPING1 0x40 87 #define REG_LR_DIOMAPPING2 0x41 88 // Version 89 #define REG_LR_VERSION 0x42 90 // Additional settings 91 #define REG_LR_AGCREF 0x43 92 #define REG_LR_AGCTHRESH1 0x44 93 #define REG_LR_AGCTHRESH2 0x45 94 #define REG_LR_AGCTHRESH3 0x46 95 #define REG_LR_PLLHOP 0x4B 96 #define REG_LR_TCXO 0x58 97 #define REG_LR_PADAC 0x5A 98 #define REG_LR_PLL 0x5C 99 #define REG_LR_PLLLOWPN 0x5E 100 #define REG_LR_FORMERTEMP 0x6C 101 102 /*! 103 * ============================================================================ 104 * SX1272 LoRa bits control definition 105 * ============================================================================ 106 */ 107 108 /*! 109 * RegFifo 110 */ 111 112 /*! 113 * RegOpMode 114 */ 115 #define RFLR_OPMODE_LONGRANGEMODE_MASK 0x7F 116 #define RFLR_OPMODE_LONGRANGEMODE_OFF 0x00 // Default 117 #define RFLR_OPMODE_LONGRANGEMODE_ON 0x80 118 119 #define RFLR_OPMODE_ACCESSSHAREDREG_MASK 0xBF 120 #define RFLR_OPMODE_ACCESSSHAREDREG_ENABLE 0x40 121 #define RFLR_OPMODE_ACCESSSHAREDREG_DISABLE 0x00 // Default 122 123 #define RFLR_OPMODE_MASK 0xF8 124 #define RFLR_OPMODE_SLEEP 0x00 125 #define RFLR_OPMODE_STANDBY 0x01 // Default 126 #define RFLR_OPMODE_SYNTHESIZER_TX 0x02 127 #define RFLR_OPMODE_TRANSMITTER 0x03 128 #define RFLR_OPMODE_SYNTHESIZER_RX 0x04 129 #define RFLR_OPMODE_RECEIVER 0x05 130 // LoRa specific modes 131 #define RFLR_OPMODE_RECEIVER_SINGLE 0x06 132 #define RFLR_OPMODE_CAD 0x07 133 134 /*! 135 * RegFrf (MHz) 136 */ 137 #define RFLR_FRFMSB_915_MHZ 0xE4 // Default 138 #define RFLR_FRFMID_915_MHZ 0xC0 // Default 139 #define RFLR_FRFLSB_915_MHZ 0x00 // Default 140 141 /*! 142 * RegPaConfig 143 */ 144 #define RFLR_PACONFIG_PASELECT_MASK 0x7F 145 #define RFLR_PACONFIG_PASELECT_PABOOST 0x80 146 #define RFLR_PACONFIG_PASELECT_RFO 0x00 // Default 147 148 #define RFLR_PACONFIG_OUTPUTPOWER_MASK 0xF0 149 150 /*! 151 * RegPaRamp 152 */ 153 #define RFLR_PARAMP_LOWPNTXPLL_MASK 0xE0 154 #define RFLR_PARAMP_LOWPNTXPLL_OFF 0x10 // Default 155 #define RFLR_PARAMP_LOWPNTXPLL_ON 0x00 156 157 #define RFLR_PARAMP_MASK 0xF0 158 #define RFLR_PARAMP_3400_US 0x00 159 #define RFLR_PARAMP_2000_US 0x01 160 #define RFLR_PARAMP_1000_US 0x02 161 #define RFLR_PARAMP_0500_US 0x03 162 #define RFLR_PARAMP_0250_US 0x04 163 #define RFLR_PARAMP_0125_US 0x05 164 #define RFLR_PARAMP_0100_US 0x06 165 #define RFLR_PARAMP_0062_US 0x07 166 #define RFLR_PARAMP_0050_US 0x08 167 #define RFLR_PARAMP_0040_US 0x09 // Default 168 #define RFLR_PARAMP_0031_US 0x0A 169 #define RFLR_PARAMP_0025_US 0x0B 170 #define RFLR_PARAMP_0020_US 0x0C 171 #define RFLR_PARAMP_0015_US 0x0D 172 #define RFLR_PARAMP_0012_US 0x0E 173 #define RFLR_PARAMP_0010_US 0x0F 174 175 /*! 176 * RegOcp 177 */ 178 #define RFLR_OCP_MASK 0xDF 179 #define RFLR_OCP_ON 0x20 // Default 180 #define RFLR_OCP_OFF 0x00 181 182 #define RFLR_OCP_TRIM_MASK 0xE0 183 #define RFLR_OCP_TRIM_045_MA 0x00 184 #define RFLR_OCP_TRIM_050_MA 0x01 185 #define RFLR_OCP_TRIM_055_MA 0x02 186 #define RFLR_OCP_TRIM_060_MA 0x03 187 #define RFLR_OCP_TRIM_065_MA 0x04 188 #define RFLR_OCP_TRIM_070_MA 0x05 189 #define RFLR_OCP_TRIM_075_MA 0x06 190 #define RFLR_OCP_TRIM_080_MA 0x07 191 #define RFLR_OCP_TRIM_085_MA 0x08 192 #define RFLR_OCP_TRIM_090_MA 0x09 193 #define RFLR_OCP_TRIM_095_MA 0x0A 194 #define RFLR_OCP_TRIM_100_MA 0x0B // Default 195 #define RFLR_OCP_TRIM_105_MA 0x0C 196 #define RFLR_OCP_TRIM_110_MA 0x0D 197 #define RFLR_OCP_TRIM_115_MA 0x0E 198 #define RFLR_OCP_TRIM_120_MA 0x0F 199 #define RFLR_OCP_TRIM_130_MA 0x10 200 #define RFLR_OCP_TRIM_140_MA 0x11 201 #define RFLR_OCP_TRIM_150_MA 0x12 202 #define RFLR_OCP_TRIM_160_MA 0x13 203 #define RFLR_OCP_TRIM_170_MA 0x14 204 #define RFLR_OCP_TRIM_180_MA 0x15 205 #define RFLR_OCP_TRIM_190_MA 0x16 206 #define RFLR_OCP_TRIM_200_MA 0x17 207 #define RFLR_OCP_TRIM_210_MA 0x18 208 #define RFLR_OCP_TRIM_220_MA 0x19 209 #define RFLR_OCP_TRIM_230_MA 0x1A 210 #define RFLR_OCP_TRIM_240_MA 0x1B 211 212 /*! 213 * RegLna 214 */ 215 #define RFLR_LNA_GAIN_MASK 0x1F 216 #define RFLR_LNA_GAIN_G1 0x20 // Default 217 #define RFLR_LNA_GAIN_G2 0x40 218 #define RFLR_LNA_GAIN_G3 0x60 219 #define RFLR_LNA_GAIN_G4 0x80 220 #define RFLR_LNA_GAIN_G5 0xA0 221 #define RFLR_LNA_GAIN_G6 0xC0 222 223 #define RFLR_LNA_BOOST_MASK 0xFC 224 #define RFLR_LNA_BOOST_OFF 0x00 // Default 225 #define RFLR_LNA_BOOST_ON 0x03 226 227 /*! 228 * RegFifoAddrPtr 229 */ 230 #define RFLR_FIFOADDRPTR 0x00 // Default 231 232 /*! 233 * RegFifoTxBaseAddr 234 */ 235 #define RFLR_FIFOTXBASEADDR 0x80 // Default 236 237 /*! 238 * RegFifoTxBaseAddr 239 */ 240 #define RFLR_FIFORXBASEADDR 0x00 // Default 241 242 /*! 243 * RegFifoRxCurrentAddr (Read Only) 244 */ 245 246 /*! 247 * RegIrqFlagsMask 248 */ 249 #define RFLR_IRQFLAGS_RXTIMEOUT_MASK 0x80 250 #define RFLR_IRQFLAGS_RXDONE_MASK 0x40 251 #define RFLR_IRQFLAGS_PAYLOADCRCERROR_MASK 0x20 252 #define RFLR_IRQFLAGS_VALIDHEADER_MASK 0x10 253 #define RFLR_IRQFLAGS_TXDONE_MASK 0x08 254 #define RFLR_IRQFLAGS_CADDONE_MASK 0x04 255 #define RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL_MASK 0x02 256 #define RFLR_IRQFLAGS_CADDETECTED_MASK 0x01 257 258 /*! 259 * RegIrqFlags 260 */ 261 #define RFLR_IRQFLAGS_RXTIMEOUT 0x80 262 #define RFLR_IRQFLAGS_RXDONE 0x40 263 #define RFLR_IRQFLAGS_PAYLOADCRCERROR 0x20 264 #define RFLR_IRQFLAGS_VALIDHEADER 0x10 265 #define RFLR_IRQFLAGS_TXDONE 0x08 266 #define RFLR_IRQFLAGS_CADDONE 0x04 267 #define RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL 0x02 268 #define RFLR_IRQFLAGS_CADDETECTED 0x01 269 270 /*! 271 * RegFifoRxNbBytes (Read Only) 272 */ 273 274 /*! 275 * RegRxHeaderCntValueMsb (Read Only) 276 */ 277 278 /*! 279 * RegRxHeaderCntValueLsb (Read Only) 280 */ 281 282 /*! 283 * RegRxPacketCntValueMsb (Read Only) 284 */ 285 286 /*! 287 * RegRxPacketCntValueLsb (Read Only) 288 */ 289 290 /*! 291 * RegModemStat (Read Only) 292 */ 293 #define RFLR_MODEMSTAT_RX_CR_MASK 0x1F 294 #define RFLR_MODEMSTAT_MODEM_STATUS_MASK 0xE0 295 296 /*! 297 * RegPktSnrValue (Read Only) 298 */ 299 300 /*! 301 * RegPktRssiValue (Read Only) 302 */ 303 304 /*! 305 * RegRssiValue (Read Only) 306 */ 307 308 /*! 309 * RegHopChannel (Read Only) 310 */ 311 #define RFLR_HOPCHANNEL_PLL_LOCK_TIMEOUT_MASK 0x7F 312 #define RFLR_HOPCHANNEL_PLL_LOCK_FAIL 0x80 313 #define RFLR_HOPCHANNEL_PLL_LOCK_SUCCEED 0x00 // Default 314 315 #define RFLR_HOPCHANNEL_CRCONPAYLOAD_MASK 0xBF 316 #define RFLR_HOPCHANNEL_CRCONPAYLOAD_ON 0x40 317 #define RFLR_HOPCHANNEL_CRCONPAYLOAD_OFF 0x00 // Default 318 319 #define RFLR_HOPCHANNEL_CHANNEL_MASK 0x3F 320 321 /*! 322 * RegModemConfig1 323 */ 324 #define RFLR_MODEMCONFIG1_BW_MASK 0x3F 325 #define RFLR_MODEMCONFIG1_BW_125_KHZ 0x00 // Default 326 #define RFLR_MODEMCONFIG1_BW_250_KHZ 0x40 327 #define RFLR_MODEMCONFIG1_BW_500_KHZ 0x80 328 329 #define RFLR_MODEMCONFIG1_CODINGRATE_MASK 0xC7 330 #define RFLR_MODEMCONFIG1_CODINGRATE_4_5 0x08 331 #define RFLR_MODEMCONFIG1_CODINGRATE_4_6 0x10 // Default 332 #define RFLR_MODEMCONFIG1_CODINGRATE_4_7 0x18 333 #define RFLR_MODEMCONFIG1_CODINGRATE_4_8 0x20 334 335 #define RFLR_MODEMCONFIG1_IMPLICITHEADER_MASK 0xFB 336 #define RFLR_MODEMCONFIG1_IMPLICITHEADER_ON 0x04 337 #define RFLR_MODEMCONFIG1_IMPLICITHEADER_OFF 0x00 // Default 338 339 #define RFLR_MODEMCONFIG1_RXPAYLOADCRC_MASK 0xFD 340 #define RFLR_MODEMCONFIG1_RXPAYLOADCRC_ON 0x02 341 #define RFLR_MODEMCONFIG1_RXPAYLOADCRC_OFF 0x00 // Default 342 343 #define RFLR_MODEMCONFIG1_LOWDATARATEOPTIMIZE_MASK 0xFE 344 #define RFLR_MODEMCONFIG1_LOWDATARATEOPTIMIZE_ON 0x01 345 #define RFLR_MODEMCONFIG1_LOWDATARATEOPTIMIZE_OFF 0x00 // Default 346 347 /*! 348 * RegModemConfig2 349 */ 350 #define RFLR_MODEMCONFIG2_SF_MASK 0x0F 351 #define RFLR_MODEMCONFIG2_SF_6 0x60 352 #define RFLR_MODEMCONFIG2_SF_7 0x70 // Default 353 #define RFLR_MODEMCONFIG2_SF_8 0x80 354 #define RFLR_MODEMCONFIG2_SF_9 0x90 355 #define RFLR_MODEMCONFIG2_SF_10 0xA0 356 #define RFLR_MODEMCONFIG2_SF_11 0xB0 357 #define RFLR_MODEMCONFIG2_SF_12 0xC0 358 359 #define RFLR_MODEMCONFIG2_TXCONTINUOUSMODE_MASK 0xF7 360 #define RFLR_MODEMCONFIG2_TXCONTINUOUSMODE_ON 0x08 361 #define RFLR_MODEMCONFIG2_TXCONTINUOUSMODE_OFF 0x00 362 363 #define RFLR_MODEMCONFIG2_AGCAUTO_MASK 0xFB 364 #define RFLR_MODEMCONFIG2_AGCAUTO_ON 0x04 // Default 365 #define RFLR_MODEMCONFIG2_AGCAUTO_OFF 0x00 366 367 #define RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK 0xFC 368 #define RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB 0x00 // Default 369 370 /*! 371 * RegSymbTimeoutLsb 372 */ 373 #define RFLR_SYMBTIMEOUTLSB_SYMBTIMEOUT 0x64 // Default 374 375 /*! 376 * RegPreambleLengthMsb 377 */ 378 #define RFLR_PREAMBLELENGTHMSB 0x00 // Default 379 380 /*! 381 * RegPreambleLengthLsb 382 */ 383 #define RFLR_PREAMBLELENGTHLSB 0x08 // Default 384 385 /*! 386 * RegPayloadLength 387 */ 388 #define RFLR_PAYLOADLENGTH 0x0E // Default 389 390 /*! 391 * RegPayloadMaxLength 392 */ 393 #define RFLR_PAYLOADMAXLENGTH 0xFF // Default 394 395 /*! 396 * RegHopPeriod 397 */ 398 #define RFLR_HOPPERIOD_FREQFOPPINGPERIOD 0x00 // Default 399 400 /*! 401 * RegFifoRxByteAddr (Read Only) 402 */ 403 404 /*! 405 * RegFeiMsb (Read Only) 406 */ 407 408 /*! 409 * RegFeiMid (Read Only) 410 */ 411 412 /*! 413 * RegFeiLsb (Read Only) 414 */ 415 416 /*! 417 * RegRssiWideband (Read Only) 418 */ 419 420 /*! 421 * RegDetectOptimize 422 */ 423 #define RFLR_DETECTIONOPTIMIZE_MASK 0xF8 424 #define RFLR_DETECTIONOPTIMIZE_SF7_TO_SF12 0x03 // Default 425 #define RFLR_DETECTIONOPTIMIZE_SF6 0x05 426 427 /*! 428 * RegInvertIQ 429 */ 430 #define RFLR_INVERTIQ_RX_MASK 0xBF 431 #define RFLR_INVERTIQ_RX_OFF 0x00 432 #define RFLR_INVERTIQ_RX_ON 0x40 433 #define RFLR_INVERTIQ_TX_MASK 0xFE 434 #define RFLR_INVERTIQ_TX_OFF 0x01 435 #define RFLR_INVERTIQ_TX_ON 0x00 436 437 /*! 438 * RegDetectionThreshold 439 */ 440 #define RFLR_DETECTIONTHRESH_SF7_TO_SF12 0x0A // Default 441 #define RFLR_DETECTIONTHRESH_SF6 0x0C 442 443 /*! 444 * RegInvertIQ2 445 */ 446 #define RFLR_INVERTIQ2_ON 0x19 447 #define RFLR_INVERTIQ2_OFF 0x1D 448 449 /*! 450 * RegDioMapping1 451 */ 452 #define RFLR_DIOMAPPING1_DIO0_MASK 0x3F 453 #define RFLR_DIOMAPPING1_DIO0_00 0x00 // Default 454 #define RFLR_DIOMAPPING1_DIO0_01 0x40 455 #define RFLR_DIOMAPPING1_DIO0_10 0x80 456 #define RFLR_DIOMAPPING1_DIO0_11 0xC0 457 458 #define RFLR_DIOMAPPING1_DIO1_MASK 0xCF 459 #define RFLR_DIOMAPPING1_DIO1_00 0x00 // Default 460 #define RFLR_DIOMAPPING1_DIO1_01 0x10 461 #define RFLR_DIOMAPPING1_DIO1_10 0x20 462 #define RFLR_DIOMAPPING1_DIO1_11 0x30 463 464 #define RFLR_DIOMAPPING1_DIO2_MASK 0xF3 465 #define RFLR_DIOMAPPING1_DIO2_00 0x00 // Default 466 #define RFLR_DIOMAPPING1_DIO2_01 0x04 467 #define RFLR_DIOMAPPING1_DIO2_10 0x08 468 #define RFLR_DIOMAPPING1_DIO2_11 0x0C 469 470 #define RFLR_DIOMAPPING1_DIO3_MASK 0xFC 471 #define RFLR_DIOMAPPING1_DIO3_00 0x00 // Default 472 #define RFLR_DIOMAPPING1_DIO3_01 0x01 473 #define RFLR_DIOMAPPING1_DIO3_10 0x02 474 #define RFLR_DIOMAPPING1_DIO3_11 0x03 475 476 /*! 477 * RegDioMapping2 478 */ 479 #define RFLR_DIOMAPPING2_DIO4_MASK 0x3F 480 #define RFLR_DIOMAPPING2_DIO4_00 0x00 // Default 481 #define RFLR_DIOMAPPING2_DIO4_01 0x40 482 #define RFLR_DIOMAPPING2_DIO4_10 0x80 483 #define RFLR_DIOMAPPING2_DIO4_11 0xC0 484 485 #define RFLR_DIOMAPPING2_DIO5_MASK 0xCF 486 #define RFLR_DIOMAPPING2_DIO5_00 0x00 // Default 487 #define RFLR_DIOMAPPING2_DIO5_01 0x10 488 #define RFLR_DIOMAPPING2_DIO5_10 0x20 489 #define RFLR_DIOMAPPING2_DIO5_11 0x30 490 491 #define RFLR_DIOMAPPING2_MAP_MASK 0xFE 492 #define RFLR_DIOMAPPING2_MAP_PREAMBLEDETECT 0x01 493 #define RFLR_DIOMAPPING2_MAP_RSSI 0x00 // Default 494 495 /*! 496 * RegVersion (Read Only) 497 */ 498 499 /*! 500 * RegAgcRef 501 */ 502 503 /*! 504 * RegAgcThresh1 505 */ 506 507 /*! 508 * RegAgcThresh2 509 */ 510 511 /*! 512 * RegAgcThresh3 513 */ 514 515 /*! 516 * RegPllHop 517 */ 518 #define RFLR_PLLHOP_FASTHOP_MASK 0x7F 519 #define RFLR_PLLHOP_FASTHOP_ON 0x80 520 #define RFLR_PLLHOP_FASTHOP_OFF 0x00 // Default 521 522 /*! 523 * RegTcxo 524 */ 525 #define RFLR_TCXO_TCXOINPUT_MASK 0xEF 526 #define RFLR_TCXO_TCXOINPUT_ON 0x10 527 #define RFLR_TCXO_TCXOINPUT_OFF 0x00 // Default 528 529 /*! 530 * RegPaDac 531 */ 532 #define RFLR_PADAC_20DBM_MASK 0xF8 533 #define RFLR_PADAC_20DBM_ON 0x07 534 #define RFLR_PADAC_20DBM_OFF 0x04 // Default 535 536 /*! 537 * RegPll 538 */ 539 #define RFLR_PLL_BANDWIDTH_MASK 0x3F 540 #define RFLR_PLL_BANDWIDTH_75 0x00 541 #define RFLR_PLL_BANDWIDTH_150 0x40 542 #define RFLR_PLL_BANDWIDTH_225 0x80 543 #define RFLR_PLL_BANDWIDTH_300 0xC0 // Default 544 545 /*! 546 * RegPllLowPn 547 */ 548 #define RFLR_PLLLOWPN_BANDWIDTH_MASK 0x3F 549 #define RFLR_PLLLOWPN_BANDWIDTH_75 0x00 550 #define RFLR_PLLLOWPN_BANDWIDTH_150 0x40 551 #define RFLR_PLLLOWPN_BANDWIDTH_225 0x80 552 #define RFLR_PLLLOWPN_BANDWIDTH_300 0xC0 // Default 553 554 /*! 555 * RegFormerTemp 556 */ 557 558 #ifdef __cplusplus 559 } 560 #endif 561 562 #endif // __SX1272_REGS_LORA_H__ 563
