1 /** 2 ****************************************************************************** 3 * @file stm32l081xx.h 4 * @author MCD Application Team 5 * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File. 6 * This file contains all the peripheral register's definitions, bits 7 * definitions and memory mapping for stm32l081xx devices. 8 * 9 * This file contains: 10 * - Data structures and the address mapping for all peripherals 11 * - Peripheral's registers declarations and bits definition 12 * - Macros to access peripheral's registers hardware 13 * 14 ****************************************************************************** 15 * @attention 16 * 17 * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> 18 * 19 * Redistribution and use in source and binary forms, with or without modification, 20 * are permitted provided that the following conditions are met: 21 * 1. Redistributions of source code must retain the above copyright notice, 22 * this list of conditions and the following disclaimer. 23 * 2. Redistributions in binary form must reproduce the above copyright notice, 24 * this list of conditions and the following disclaimer in the documentation 25 * and/or other materials provided with the distribution. 26 * 3. Neither the name of STMicroelectronics nor the names of its contributors 27 * may be used to endorse or promote products derived from this software 28 * without specific prior written permission. 29 * 30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 31 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 33 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 36 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 37 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 38 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 * 41 ****************************************************************************** 42 */ 43 44 /** @addtogroup CMSIS 45 * @{ 46 */ 47 48 /** @addtogroup stm32l081xx 49 * @{ 50 */ 51 52 #ifndef __STM32L081xx_H 53 #define __STM32L081xx_H 54 55 #ifdef __cplusplus 56 extern "C" { 57 #endif 58 59 60 /** @addtogroup Configuration_section_for_CMSIS 61 * @{ 62 */ 63 /** 64 * @brief Configuration of the Cortex-M0+ Processor and Core Peripherals 65 */ 66 #define __CM0PLUS_REV 0 /*!< Core Revision r0p0 */ 67 #define __MPU_PRESENT 1 /*!< STM32L0xx provides an MPU */ 68 #define __VTOR_PRESENT 1 /*!< Vector Table Register supported */ 69 #define __NVIC_PRIO_BITS 2 /*!< STM32L0xx uses 2 Bits for the Priority Levels */ 70 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ 71 72 /** 73 * @} 74 */ 75 76 /** @addtogroup Peripheral_interrupt_number_definition 77 * @{ 78 */ 79 80 /** 81 * @brief stm32l081xx Interrupt Number Definition, according to the selected device 82 * in @ref Library_configuration_section 83 */ 84 85 /*!< Interrupt Number Definition */ 86 typedef enum 87 { 88 /****** Cortex-M0 Processor Exceptions Numbers ******************************************************/ 89 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ 90 HardFault_IRQn = -13, /*!< 3 Cortex-M0+ Hard Fault Interrupt */ 91 SVC_IRQn = -5, /*!< 11 Cortex-M0+ SV Call Interrupt */ 92 PendSV_IRQn = -2, /*!< 14 Cortex-M0+ Pend SV Interrupt */ 93 SysTick_IRQn = -1, /*!< 15 Cortex-M0+ System Tick Interrupt */ 94 95 /****** STM32L-0 specific Interrupt Numbers *********************************************************/ 96 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ 97 PVD_IRQn = 1, /*!< PVD through EXTI Line detect Interrupt */ 98 RTC_IRQn = 2, /*!< RTC through EXTI Line Interrupt */ 99 FLASH_IRQn = 3, /*!< FLASH Interrupt */ 100 RCC_IRQn = 4, /*!< RCC Interrupt */ 101 EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */ 102 EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */ 103 EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */ 104 DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */ 105 DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */ 106 DMA1_Channel4_5_6_7_IRQn = 11, /*!< DMA1 Channel 4, Channel 5, Channel 6 and Channel 7 Interrupts */ 107 ADC1_COMP_IRQn = 12, /*!< ADC1, COMP1 and COMP2 Interrupts */ 108 LPTIM1_IRQn = 13, /*!< LPTIM1 Interrupt */ 109 USART4_5_IRQn = 14, /*!< USART4 and USART5 Interrupt */ 110 TIM2_IRQn = 15, /*!< TIM2 Interrupt */ 111 TIM3_IRQn = 16, /*!< TIM3 Interrupt */ 112 TIM6_IRQn = 17, /*!< TIM6 Interrupt */ 113 TIM7_IRQn = 18, /*!< TIM7 Interrupt */ 114 TIM21_IRQn = 20, /*!< TIM21 Interrupt */ 115 I2C3_IRQn = 21, /*!< I2C3 Interrupt */ 116 TIM22_IRQn = 22, /*!< TIM22 Interrupt */ 117 I2C1_IRQn = 23, /*!< I2C1 Interrupt */ 118 I2C2_IRQn = 24, /*!< I2C2 Interrupt */ 119 SPI1_IRQn = 25, /*!< SPI1 Interrupt */ 120 SPI2_IRQn = 26, /*!< SPI2 Interrupt */ 121 USART1_IRQn = 27, /*!< USART1 Interrupt */ 122 USART2_IRQn = 28, /*!< USART2 Interrupt */ 123 AES_LPUART1_IRQn = 29, /*!< AES and LPUART1 Interrupts */ 124 } IRQn_Type; 125 126 /** 127 * @} 128 */ 129 130 #include "core_cm0plus.h" 131 #include "system_stm32l0xx.h" 132 #include <stdint.h> 133 134 /** @addtogroup Peripheral_registers_structures 135 * @{ 136 */ 137 138 /** 139 * @brief Analog to Digital Converter 140 */ 141 142 typedef struct 143 { 144 __IO uint32_t ISR; /*!< ADC Interrupt and Status register, Address offset:0x00 */ 145 __IO uint32_t IER; /*!< ADC Interrupt Enable register, Address offset:0x04 */ 146 __IO uint32_t CR; /*!< ADC Control register, Address offset:0x08 */ 147 __IO uint32_t CFGR1; /*!< ADC Configuration register 1, Address offset:0x0C */ 148 __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset:0x10 */ 149 __IO uint32_t SMPR; /*!< ADC Sampling time register, Address offset:0x14 */ 150 uint32_t RESERVED1; /*!< Reserved, 0x18 */ 151 uint32_t RESERVED2; /*!< Reserved, 0x1C */ 152 __IO uint32_t TR; /*!< ADC watchdog threshold register, Address offset:0x20 */ 153 uint32_t RESERVED3; /*!< Reserved, 0x24 */ 154 __IO uint32_t CHSELR; /*!< ADC channel selection register, Address offset:0x28 */ 155 uint32_t RESERVED4[5]; /*!< Reserved, 0x2C */ 156 __IO uint32_t DR; /*!< ADC data register, Address offset:0x40 */ 157 uint32_t RESERVED5[28]; /*!< Reserved, 0x44 - 0xB0 */ 158 __IO uint32_t CALFACT; /*!< ADC data register, Address offset:0xB4 */ 159 } ADC_TypeDef; 160 161 typedef struct 162 { 163 __IO uint32_t CCR; 164 } ADC_Common_TypeDef; 165 166 /** 167 * @brief AES hardware accelerator 168 */ 169 170 typedef struct 171 { 172 __IO uint32_t CR; /*!< AES control register, Address offset: 0x00 */ 173 __IO uint32_t SR; /*!< AES status register, Address offset: 0x04 */ 174 __IO uint32_t DINR; /*!< AES data input register, Address offset: 0x08 */ 175 __IO uint32_t DOUTR; /*!< AES data output register, Address offset: 0x0C */ 176 __IO uint32_t KEYR0; /*!< AES key register 0, Address offset: 0x10 */ 177 __IO uint32_t KEYR1; /*!< AES key register 1, Address offset: 0x14 */ 178 __IO uint32_t KEYR2; /*!< AES key register 2, Address offset: 0x18 */ 179 __IO uint32_t KEYR3; /*!< AES key register 3, Address offset: 0x1C */ 180 __IO uint32_t IVR0; /*!< AES initialization vector register 0, Address offset: 0x20 */ 181 __IO uint32_t IVR1; /*!< AES initialization vector register 1, Address offset: 0x24 */ 182 __IO uint32_t IVR2; /*!< AES initialization vector register 2, Address offset: 0x28 */ 183 __IO uint32_t IVR3; /*!< AES initialization vector register 3, Address offset: 0x2C */ 184 } AES_TypeDef; 185 186 /** 187 * @brief Comparator 188 */ 189 190 typedef struct 191 { 192 __IO uint32_t CSR; /*!< COMP comparator control and status register, Address offset: 0x18 */ 193 } COMP_TypeDef; 194 195 typedef struct 196 { 197 __IO uint32_t CSR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */ 198 } COMP_Common_TypeDef; 199 200 201 /** 202 * @brief CRC calculation unit 203 */ 204 205 typedef struct 206 { 207 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ 208 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ 209 uint8_t RESERVED0; /*!< Reserved, 0x05 */ 210 uint16_t RESERVED1; /*!< Reserved, 0x06 */ 211 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ 212 uint32_t RESERVED2; /*!< Reserved, 0x0C */ 213 __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ 214 __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ 215 } CRC_TypeDef; 216 217 /** 218 * @brief Debug MCU 219 */ 220 221 typedef struct 222 { 223 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ 224 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ 225 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ 226 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ 227 }DBGMCU_TypeDef; 228 229 /** 230 * @brief DMA Controller 231 */ 232 233 typedef struct 234 { 235 __IO uint32_t CCR; /*!< DMA channel x configuration register */ 236 __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ 237 __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ 238 __IO uint32_t CMAR; /*!< DMA channel x memory address register */ 239 } DMA_Channel_TypeDef; 240 241 typedef struct 242 { 243 __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ 244 __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ 245 } DMA_TypeDef; 246 247 typedef struct 248 { 249 __IO uint32_t CSELR; /*!< DMA channel selection register, Address offset: 0xA8 */ 250 } DMA_Request_TypeDef; 251 252 /** 253 * @brief External Interrupt/Event Controller 254 */ 255 256 typedef struct 257 { 258 __IO uint32_t IMR; /*!<EXTI Interrupt mask register, Address offset: 0x00 */ 259 __IO uint32_t EMR; /*!<EXTI Event mask register, Address offset: 0x04 */ 260 __IO uint32_t RTSR; /*!<EXTI Rising trigger selection register , Address offset: 0x08 */ 261 __IO uint32_t FTSR; /*!<EXTI Falling trigger selection register, Address offset: 0x0C */ 262 __IO uint32_t SWIER; /*!<EXTI Software interrupt event register, Address offset: 0x10 */ 263 __IO uint32_t PR; /*!<EXTI Pending register, Address offset: 0x14 */ 264 }EXTI_TypeDef; 265 266 /** 267 * @brief FLASH Registers 268 */ 269 typedef struct 270 { 271 __IO uint32_t ACR; /*!< Access control register, Address offset: 0x00 */ 272 __IO uint32_t PECR; /*!< Program/erase control register, Address offset: 0x04 */ 273 __IO uint32_t PDKEYR; /*!< Power down key register, Address offset: 0x08 */ 274 __IO uint32_t PEKEYR; /*!< Program/erase key register, Address offset: 0x0c */ 275 __IO uint32_t PRGKEYR; /*!< Program memory key register, Address offset: 0x10 */ 276 __IO uint32_t OPTKEYR; /*!< Option byte key register, Address offset: 0x14 */ 277 __IO uint32_t SR; /*!< Status register, Address offset: 0x18 */ 278 __IO uint32_t OPTR; /*!< Option byte register, Address offset: 0x1c */ 279 __IO uint32_t WRPR; /*!< Write protection register, Address offset: 0x20 */ 280 __IO uint32_t RESERVED1[23]; /*!< Reserved1, Address offset: 0x24 */ 281 __IO uint32_t WRPR2; /*!< Write protection register 2, Address offset: 0x80 */ 282 } FLASH_TypeDef; 283 284 285 /** 286 * @brief Option Bytes Registers 287 */ 288 typedef struct 289 { 290 __IO uint32_t RDP; /*!< Read protection register, Address offset: 0x00 */ 291 __IO uint32_t USER; /*!< user register, Address offset: 0x04 */ 292 __IO uint32_t WRP01; /*!< write protection Bytes 0 and 1 Address offset: 0x08 */ 293 __IO uint32_t WRP23; /*!< write protection Bytes 2 and 3 Address offset: 0x0C */ 294 __IO uint32_t WRP45; /*!< write protection Bytes 4 and 5 Address offset: 0x10 */ 295 } OB_TypeDef; 296 297 298 /** 299 * @brief General Purpose IO 300 */ 301 302 typedef struct 303 { 304 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ 305 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ 306 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ 307 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ 308 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ 309 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ 310 __IO uint32_t BSRR; /*!< GPIO port bit set/reset registerBSRR, Address offset: 0x18 */ 311 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ 312 __IO uint32_t AFR[2]; /*!< GPIO alternate function register, Address offset: 0x20-0x24 */ 313 __IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */ 314 }GPIO_TypeDef; 315 316 /** 317 * @brief LPTIMIMER 318 */ 319 typedef struct 320 { 321 __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ 322 __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ 323 __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ 324 __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ 325 __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ 326 __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */ 327 __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ 328 __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ 329 } LPTIM_TypeDef; 330 331 /** 332 * @brief SysTem Configuration 333 */ 334 335 typedef struct 336 { 337 __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */ 338 __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x04 */ 339 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration register, Address offset: 0x14-0x08 */ 340 uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */ 341 __IO uint32_t CFGR3; /*!< SYSCFG configuration register 3, Address offset: 0x20 */ 342 } SYSCFG_TypeDef; 343 344 345 346 /** 347 * @brief Inter-integrated Circuit Interface 348 */ 349 350 typedef struct 351 { 352 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ 353 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ 354 __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ 355 __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ 356 __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ 357 __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ 358 __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ 359 __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ 360 __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ 361 __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ 362 __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ 363 }I2C_TypeDef; 364 365 366 /** 367 * @brief Independent WATCHDOG 368 */ 369 typedef struct 370 { 371 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ 372 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ 373 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ 374 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ 375 __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ 376 } IWDG_TypeDef; 377 378 /** 379 * @brief MIFARE Firewall 380 */ 381 typedef struct 382 { 383 __IO uint32_t CSSA; /*!< Code Segment Start Address register, Address offset: 0x00 */ 384 __IO uint32_t CSL; /*!< Code Segment Length register, Address offset: 0x04 */ 385 __IO uint32_t NVDSSA; /*!< NON volatile data Segment Start Address register, Address offset: 0x08 */ 386 __IO uint32_t NVDSL; /*!< NON volatile data Segment Length register, Address offset: 0x0C */ 387 __IO uint32_t VDSSA ; /*!< Volatile data Segment Start Address register, Address offset: 0x10 */ 388 __IO uint32_t VDSL ; /*!< Volatile data Segment Length register, Address offset: 0x14 */ 389 __IO uint32_t LSSA ; /*!< Library Segment Start Address register, Address offset: 0x18 */ 390 __IO uint32_t LSL ; /*!< Library Segment Length register, Address offset: 0x1C */ 391 __IO uint32_t CR ; /*!< Configuration register, Address offset: 0x20 */ 392 393 } FIREWALL_TypeDef; 394 395 /** 396 * @brief Power Control 397 */ 398 typedef struct 399 { 400 __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */ 401 __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */ 402 } PWR_TypeDef; 403 404 /** 405 * @brief Reset and Clock Control 406 */ 407 typedef struct 408 { 409 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */ 410 __IO uint32_t ICSCR; /*!< RCC Internal clock sources calibration register, Address offset: 0x04 */ 411 __IO uint32_t CRRCR; /*!< RCC Clock recovery RC register, Address offset: 0x08 */ 412 __IO uint32_t CFGR; /*!< RCC Clock configuration register, Address offset: 0x0C */ 413 __IO uint32_t CIER; /*!< RCC Clock interrupt enable register, Address offset: 0x10 */ 414 __IO uint32_t CIFR; /*!< RCC Clock interrupt flag register, Address offset: 0x14 */ 415 __IO uint32_t CICR; /*!< RCC Clock interrupt clear register, Address offset: 0x18 */ 416 __IO uint32_t IOPRSTR; /*!< RCC IO port reset register, Address offset: 0x1C */ 417 __IO uint32_t AHBRSTR; /*!< RCC AHB peripheral reset register, Address offset: 0x20 */ 418 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */ 419 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x28 */ 420 __IO uint32_t IOPENR; /*!< RCC Clock IO port enable register, Address offset: 0x2C */ 421 __IO uint32_t AHBENR; /*!< RCC AHB peripheral clock enable register, Address offset: 0x30 */ 422 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral enable register, Address offset: 0x34 */ 423 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral enable register, Address offset: 0x38 */ 424 __IO uint32_t IOPSMENR; /*!< RCC IO port clock enable in sleep mode register, Address offset: 0x3C */ 425 __IO uint32_t AHBSMENR; /*!< RCC AHB peripheral clock enable in sleep mode register, Address offset: 0x40 */ 426 __IO uint32_t APB2SMENR; /*!< RCC APB2 peripheral clock enable in sleep mode register, Address offset: 0x44 */ 427 __IO uint32_t APB1SMENR; /*!< RCC APB1 peripheral clock enable in sleep mode register, Address offset: 0x48 */ 428 __IO uint32_t CCIPR; /*!< RCC clock configuration register, Address offset: 0x4C */ 429 __IO uint32_t CSR; /*!< RCC Control/status register, Address offset: 0x50 */ 430 } RCC_TypeDef; 431 432 /** 433 * @brief Real-Time Clock 434 */ 435 typedef struct 436 { 437 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ 438 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ 439 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */ 440 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */ 441 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ 442 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ 443 uint32_t RESERVED; /*!< Reserved, Address offset: 0x18 */ 444 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */ 445 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */ 446 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ 447 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */ 448 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ 449 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ 450 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ 451 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ 452 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */ 453 __IO uint32_t TAMPCR; /*!< RTC tamper configuration register, Address offset: 0x40 */ 454 __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ 455 __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */ 456 __IO uint32_t OR; /*!< RTC option register, Address offset 0x4C */ 457 __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */ 458 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */ 459 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */ 460 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */ 461 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */ 462 } RTC_TypeDef; 463 464 465 /** 466 * @brief Serial Peripheral Interface 467 */ 468 typedef struct 469 { 470 __IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */ 471 __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ 472 __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */ 473 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ 474 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */ 475 __IO uint32_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */ 476 __IO uint32_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */ 477 __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */ 478 __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */ 479 } SPI_TypeDef; 480 481 /** 482 * @brief TIM 483 */ 484 typedef struct 485 { 486 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ 487 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ 488 __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */ 489 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ 490 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ 491 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ 492 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ 493 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ 494 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ 495 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ 496 __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */ 497 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ 498 uint32_t RESERVED12;/*!< Reserved Address offset: 0x30 */ 499 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ 500 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ 501 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ 502 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ 503 uint32_t RESERVED17;/*!< Reserved, Address offset: 0x44 */ 504 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ 505 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0x4C */ 506 __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */ 507 } TIM_TypeDef; 508 509 /** 510 * @brief Universal Synchronous Asynchronous Receiver Transmitter 511 */ 512 typedef struct 513 { 514 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ 515 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ 516 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ 517 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ 518 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ 519 __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ 520 __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ 521 __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ 522 __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ 523 __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ 524 __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ 525 } USART_TypeDef; 526 527 /** 528 * @brief Window WATCHDOG 529 */ 530 typedef struct 531 { 532 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ 533 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ 534 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ 535 } WWDG_TypeDef; 536 537 538 /** 539 * @} 540 */ 541 542 /** @addtogroup Peripheral_memory_map 543 * @{ 544 */ 545 #define FLASH_BASE ((uint32_t)0x08000000U) /*!< FLASH base address in the alias region */ 546 #define FLASH_BANK2_BASE ((uint32_t)0x08018000U) /*!< FLASH BANK2 base address in the alias region */ 547 #define FLASH_BANK1_END ((uint32_t)0x08017FFFU) /*!< Program end FLASH BANK1 address */ 548 #define FLASH_BANK2_END ((uint32_t)0x0802FFFFU) /*!< Program end FLASH BANK2 address */ 549 #define DATA_EEPROM_BASE ((uint32_t)0x08080000U) /*!< DATA_EEPROM base address in the alias region */ 550 #define DATA_EEPROM_BANK2_BASE ((uint32_t)0x08080C00U) /*!< DATA EEPROM BANK2 base address in the alias region */ 551 #define DATA_EEPROM_BANK1_END ((uint32_t)0x08080BFFU) /*!< Program end DATA EEPROM BANK1 address */ 552 #define DATA_EEPROM_BANK2_END ((uint32_t)0x080817FFU) /*!< Program end DATA EEPROM BANK2 address */ 553 #define SRAM_BASE ((uint32_t)0x20000000U) /*!< SRAM base address in the alias region */ 554 #define SRAM_SIZE_MAX ((uint32_t)0x00005000U) /*!< maximum SRAM size (up to 20KBytes) */ 555 556 #define PERIPH_BASE ((uint32_t)0x40000000U) /*!< Peripheral base address in the alias region */ 557 558 /*!< Peripheral memory map */ 559 #define APBPERIPH_BASE PERIPH_BASE 560 #define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000U) 561 #define IOPPERIPH_BASE (PERIPH_BASE + 0x10000000U) 562 563 #define TIM2_BASE (APBPERIPH_BASE + 0x00000000U) 564 #define TIM3_BASE (APBPERIPH_BASE + 0x00000400U) 565 #define TIM6_BASE (APBPERIPH_BASE + 0x00001000U) 566 #define TIM7_BASE (APBPERIPH_BASE + 0x00001400U) 567 #define RTC_BASE (APBPERIPH_BASE + 0x00002800U) 568 #define WWDG_BASE (APBPERIPH_BASE + 0x00002C00U) 569 #define IWDG_BASE (APBPERIPH_BASE + 0x00003000U) 570 #define SPI2_BASE (APBPERIPH_BASE + 0x00003800U) 571 #define USART2_BASE (APBPERIPH_BASE + 0x00004400U) 572 #define LPUART1_BASE (APBPERIPH_BASE + 0x00004800U) 573 #define USART4_BASE (APBPERIPH_BASE + 0x00004C00U) 574 #define USART5_BASE (APBPERIPH_BASE + 0x00005000U) 575 #define I2C1_BASE (APBPERIPH_BASE + 0x00005400U) 576 #define I2C2_BASE (APBPERIPH_BASE + 0x00005800U) 577 #define PWR_BASE (APBPERIPH_BASE + 0x00007000U) 578 #define LPTIM1_BASE (APBPERIPH_BASE + 0x00007C00U) 579 #define I2C3_BASE (APBPERIPH_BASE + 0x00007800U) 580 581 #define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000U) 582 #define COMP1_BASE (APBPERIPH_BASE + 0x00010018U) 583 #define COMP2_BASE (APBPERIPH_BASE + 0x0001001CU) 584 #define COMP12_COMMON ((COMP_Common_TypeDef *) COMP1_BASE) 585 #define EXTI_BASE (APBPERIPH_BASE + 0x00010400U) 586 #define TIM21_BASE (APBPERIPH_BASE + 0x00010800U) 587 #define TIM22_BASE (APBPERIPH_BASE + 0x00011400U) 588 #define FIREWALL_BASE (APBPERIPH_BASE + 0x00011C00U) 589 #define ADC1_BASE (APBPERIPH_BASE + 0x00012400U) 590 #define ADC_BASE (APBPERIPH_BASE + 0x00012708U) 591 #define SPI1_BASE (APBPERIPH_BASE + 0x00013000U) 592 #define USART1_BASE (APBPERIPH_BASE + 0x00013800U) 593 #define DBGMCU_BASE (APBPERIPH_BASE + 0x00015800U) 594 595 #define DMA1_BASE (AHBPERIPH_BASE + 0x00000000U) 596 #define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008U) 597 #define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001CU) 598 #define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030U) 599 #define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044U) 600 #define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058U) 601 #define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006CU) 602 #define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080U) 603 #define DMA1_CSELR_BASE (DMA1_BASE + 0x000000A8U) 604 605 606 #define RCC_BASE (AHBPERIPH_BASE + 0x00001000U) 607 #define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000U) /*!< FLASH registers base address */ 608 #define OB_BASE ((uint32_t)0x1FF80000U) /*!< FLASH Option Bytes base address */ 609 #define FLASHSIZE_BASE ((uint32_t)0x1FF8007CU) /*!< FLASH Size register base address */ 610 #define UID_BASE ((uint32_t)0x1FF80050U) /*!< Unique device ID register base address */ 611 #define CRC_BASE (AHBPERIPH_BASE + 0x00003000U) 612 #define AES_BASE (AHBPERIPH_BASE + 0x00006000U) 613 614 #define GPIOA_BASE (IOPPERIPH_BASE + 0x00000000U) 615 #define GPIOB_BASE (IOPPERIPH_BASE + 0x00000400U) 616 #define GPIOC_BASE (IOPPERIPH_BASE + 0x00000800U) 617 #define GPIOD_BASE (IOPPERIPH_BASE + 0x00000C00U) 618 #define GPIOE_BASE (IOPPERIPH_BASE + 0x00001000U) 619 #define GPIOH_BASE (IOPPERIPH_BASE + 0x00001C00U) 620 621 /** 622 * @} 623 */ 624 625 /** @addtogroup Peripheral_declaration 626 * @{ 627 */ 628 629 #define TIM2 ((TIM_TypeDef *) TIM2_BASE) 630 #define TIM3 ((TIM_TypeDef *) TIM3_BASE) 631 #define TIM6 ((TIM_TypeDef *) TIM6_BASE) 632 #define TIM7 ((TIM_TypeDef *) TIM7_BASE) 633 #define RTC ((RTC_TypeDef *) RTC_BASE) 634 #define WWDG ((WWDG_TypeDef *) WWDG_BASE) 635 #define IWDG ((IWDG_TypeDef *) IWDG_BASE) 636 #define SPI2 ((SPI_TypeDef *) SPI2_BASE) 637 #define USART2 ((USART_TypeDef *) USART2_BASE) 638 #define LPUART1 ((USART_TypeDef *) LPUART1_BASE) 639 #define I2C1 ((I2C_TypeDef *) I2C1_BASE) 640 #define I2C2 ((I2C_TypeDef *) I2C2_BASE) 641 #define I2C3 ((I2C_TypeDef *) I2C3_BASE) 642 #define PWR ((PWR_TypeDef *) PWR_BASE) 643 #define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE) 644 #define USART4 ((USART_TypeDef *) USART4_BASE) 645 #define USART5 ((USART_TypeDef *) USART5_BASE) 646 647 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) 648 #define COMP1 ((COMP_TypeDef *) COMP1_BASE) 649 #define COMP2 ((COMP_TypeDef *) COMP2_BASE) 650 #define EXTI ((EXTI_TypeDef *) EXTI_BASE) 651 #define TIM21 ((TIM_TypeDef *) TIM21_BASE) 652 #define TIM22 ((TIM_TypeDef *) TIM22_BASE) 653 #define FIREWALL ((FIREWALL_TypeDef *) FIREWALL_BASE) 654 #define ADC1 ((ADC_TypeDef *) ADC1_BASE) 655 #define ADC1_COMMON ((ADC_Common_TypeDef *) ADC_BASE) 656 /* Legacy defines */ 657 #define ADC ADC1_COMMON 658 #define SPI1 ((SPI_TypeDef *) SPI1_BASE) 659 #define USART1 ((USART_TypeDef *) USART1_BASE) 660 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) 661 662 #define DMA1 ((DMA_TypeDef *) DMA1_BASE) 663 #define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) 664 #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) 665 #define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) 666 #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) 667 #define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) 668 #define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) 669 #define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE) 670 #define DMA1_CSELR ((DMA_Request_TypeDef *) DMA1_CSELR_BASE) 671 672 673 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) 674 #define OB ((OB_TypeDef *) OB_BASE) 675 #define RCC ((RCC_TypeDef *) RCC_BASE) 676 #define CRC ((CRC_TypeDef *) CRC_BASE) 677 #define AES ((AES_TypeDef *) AES_BASE) 678 679 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) 680 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) 681 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) 682 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) 683 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) 684 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) 685 686 /** 687 * @} 688 */ 689 690 /** @addtogroup Exported_constants 691 * @{ 692 */ 693 694 /** @addtogroup Peripheral_Registers_Bits_Definition 695 * @{ 696 */ 697 698 /******************************************************************************/ 699 /* Peripheral Registers Bits Definition */ 700 /******************************************************************************/ 701 /******************************************************************************/ 702 /* */ 703 /* Analog to Digital Converter (ADC) */ 704 /* */ 705 /******************************************************************************/ 706 /******************** Bits definition for ADC_ISR register ******************/ 707 #define ADC_ISR_EOCAL_Pos (11U) 708 #define ADC_ISR_EOCAL_Msk (0x1U << ADC_ISR_EOCAL_Pos) /*!< 0x00000800 */ 709 #define ADC_ISR_EOCAL ADC_ISR_EOCAL_Msk /*!< End of calibration flag */ 710 #define ADC_ISR_AWD_Pos (7U) 711 #define ADC_ISR_AWD_Msk (0x1U << ADC_ISR_AWD_Pos) /*!< 0x00000080 */ 712 #define ADC_ISR_AWD ADC_ISR_AWD_Msk /*!< Analog watchdog flag */ 713 #define ADC_ISR_OVR_Pos (4U) 714 #define ADC_ISR_OVR_Msk (0x1U << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ 715 #define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< Overrun flag */ 716 #define ADC_ISR_EOSEQ_Pos (3U) 717 #define ADC_ISR_EOSEQ_Msk (0x1U << ADC_ISR_EOSEQ_Pos) /*!< 0x00000008 */ 718 #define ADC_ISR_EOSEQ ADC_ISR_EOSEQ_Msk /*!< End of Sequence flag */ 719 #define ADC_ISR_EOC_Pos (2U) 720 #define ADC_ISR_EOC_Msk (0x1U << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ 721 #define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< End of Conversion */ 722 #define ADC_ISR_EOSMP_Pos (1U) 723 #define ADC_ISR_EOSMP_Msk (0x1U << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ 724 #define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< End of sampling flag */ 725 #define ADC_ISR_ADRDY_Pos (0U) 726 #define ADC_ISR_ADRDY_Msk (0x1U << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ 727 #define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC Ready */ 728 729 /* Old EOSEQ bit definition, maintained for legacy purpose */ 730 #define ADC_ISR_EOS ADC_ISR_EOSEQ 731 732 /******************** Bits definition for ADC_IER register ******************/ 733 #define ADC_IER_EOCALIE_Pos (11U) 734 #define ADC_IER_EOCALIE_Msk (0x1U << ADC_IER_EOCALIE_Pos) /*!< 0x00000800 */ 735 #define ADC_IER_EOCALIE ADC_IER_EOCALIE_Msk /*!< Enf Of Calibration interrupt enable */ 736 #define ADC_IER_AWDIE_Pos (7U) 737 #define ADC_IER_AWDIE_Msk (0x1U << ADC_IER_AWDIE_Pos) /*!< 0x00000080 */ 738 #define ADC_IER_AWDIE ADC_IER_AWDIE_Msk /*!< Analog Watchdog interrupt enable */ 739 #define ADC_IER_OVRIE_Pos (4U) 740 #define ADC_IER_OVRIE_Msk (0x1U << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ 741 #define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< Overrun interrupt enable */ 742 #define ADC_IER_EOSEQIE_Pos (3U) 743 #define ADC_IER_EOSEQIE_Msk (0x1U << ADC_IER_EOSEQIE_Pos) /*!< 0x00000008 */ 744 #define ADC_IER_EOSEQIE ADC_IER_EOSEQIE_Msk /*!< End of Sequence of conversion interrupt enable */ 745 #define ADC_IER_EOCIE_Pos (2U) 746 #define ADC_IER_EOCIE_Msk (0x1U << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ 747 #define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< End of Conversion interrupt enable */ 748 #define ADC_IER_EOSMPIE_Pos (1U) 749 #define ADC_IER_EOSMPIE_Msk (0x1U << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ 750 #define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< End of sampling interrupt enable */ 751 #define ADC_IER_ADRDYIE_Pos (0U) 752 #define ADC_IER_ADRDYIE_Msk (0x1U << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ 753 #define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC Ready interrupt enable */ 754 755 /* Old EOSEQIE bit definition, maintained for legacy purpose */ 756 #define ADC_IER_EOSIE ADC_IER_EOSEQIE 757 758 /******************** Bits definition for ADC_CR register *******************/ 759 #define ADC_CR_ADCAL_Pos (31U) 760 #define ADC_CR_ADCAL_Msk (0x1U << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ 761 #define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */ 762 #define ADC_CR_ADVREGEN_Pos (28U) 763 #define ADC_CR_ADVREGEN_Msk (0x1U << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ 764 #define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC Voltage Regulator Enable */ 765 #define ADC_CR_ADSTP_Pos (4U) 766 #define ADC_CR_ADSTP_Msk (0x1U << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ 767 #define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC stop of conversion command */ 768 #define ADC_CR_ADSTART_Pos (2U) 769 #define ADC_CR_ADSTART_Msk (0x1U << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ 770 #define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC start of conversion */ 771 #define ADC_CR_ADDIS_Pos (1U) 772 #define ADC_CR_ADDIS_Msk (0x1U << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ 773 #define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable command */ 774 #define ADC_CR_ADEN_Pos (0U) 775 #define ADC_CR_ADEN_Msk (0x1U << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ 776 #define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable control */ /*#### TBV */ 777 778 /******************* Bits definition for ADC_CFGR1 register *****************/ 779 #define ADC_CFGR1_AWDCH_Pos (26U) 780 #define ADC_CFGR1_AWDCH_Msk (0x1FU << ADC_CFGR1_AWDCH_Pos) /*!< 0x7C000000 */ 781 #define ADC_CFGR1_AWDCH ADC_CFGR1_AWDCH_Msk /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */ 782 #define ADC_CFGR1_AWDCH_0 (0x01U << ADC_CFGR1_AWDCH_Pos) /*!< 0x04000000 */ 783 #define ADC_CFGR1_AWDCH_1 (0x02U << ADC_CFGR1_AWDCH_Pos) /*!< 0x08000000 */ 784 #define ADC_CFGR1_AWDCH_2 (0x04U << ADC_CFGR1_AWDCH_Pos) /*!< 0x10000000 */ 785 #define ADC_CFGR1_AWDCH_3 (0x08U << ADC_CFGR1_AWDCH_Pos) /*!< 0x20000000 */ 786 #define ADC_CFGR1_AWDCH_4 (0x10U << ADC_CFGR1_AWDCH_Pos) /*!< 0x40000000 */ 787 #define ADC_CFGR1_AWDEN_Pos (23U) 788 #define ADC_CFGR1_AWDEN_Msk (0x1U << ADC_CFGR1_AWDEN_Pos) /*!< 0x00800000 */ 789 #define ADC_CFGR1_AWDEN ADC_CFGR1_AWDEN_Msk /*!< Analog watchdog enable on regular channels */ 790 #define ADC_CFGR1_AWDSGL_Pos (22U) 791 #define ADC_CFGR1_AWDSGL_Msk (0x1U << ADC_CFGR1_AWDSGL_Pos) /*!< 0x00400000 */ 792 #define ADC_CFGR1_AWDSGL ADC_CFGR1_AWDSGL_Msk /*!< Enable the watchdog on a single channel or on all channels */ 793 #define ADC_CFGR1_DISCEN_Pos (16U) 794 #define ADC_CFGR1_DISCEN_Msk (0x1U << ADC_CFGR1_DISCEN_Pos) /*!< 0x00010000 */ 795 #define ADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk /*!< Discontinuous mode on regular channels */ 796 #define ADC_CFGR1_AUTOFF_Pos (15U) 797 #define ADC_CFGR1_AUTOFF_Msk (0x1U << ADC_CFGR1_AUTOFF_Pos) /*!< 0x00008000 */ 798 #define ADC_CFGR1_AUTOFF ADC_CFGR1_AUTOFF_Msk /*!< ADC auto power off */ 799 #define ADC_CFGR1_WAIT_Pos (14U) 800 #define ADC_CFGR1_WAIT_Msk (0x1U << ADC_CFGR1_WAIT_Pos) /*!< 0x00004000 */ 801 #define ADC_CFGR1_WAIT ADC_CFGR1_WAIT_Msk /*!< ADC wait conversion mode */ 802 #define ADC_CFGR1_CONT_Pos (13U) 803 #define ADC_CFGR1_CONT_Msk (0x1U << ADC_CFGR1_CONT_Pos) /*!< 0x00002000 */ 804 #define ADC_CFGR1_CONT ADC_CFGR1_CONT_Msk /*!< Continuous Conversion */ 805 #define ADC_CFGR1_OVRMOD_Pos (12U) 806 #define ADC_CFGR1_OVRMOD_Msk (0x1U << ADC_CFGR1_OVRMOD_Pos) /*!< 0x00001000 */ 807 #define ADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_Msk /*!< Overrun mode */ 808 #define ADC_CFGR1_EXTEN_Pos (10U) 809 #define ADC_CFGR1_EXTEN_Msk (0x3U << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000C00 */ 810 #define ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_Msk /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */ 811 #define ADC_CFGR1_EXTEN_0 (0x1U << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000400 */ 812 #define ADC_CFGR1_EXTEN_1 (0x2U << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000800 */ 813 #define ADC_CFGR1_EXTSEL_Pos (6U) 814 #define ADC_CFGR1_EXTSEL_Msk (0x7U << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000001C0 */ 815 #define ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_Msk /*!< EXTSEL[2:0] bits (External Event Select for regular group) */ 816 #define ADC_CFGR1_EXTSEL_0 (0x1U << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */ 817 #define ADC_CFGR1_EXTSEL_1 (0x2U << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */ 818 #define ADC_CFGR1_EXTSEL_2 (0x4U << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */ 819 #define ADC_CFGR1_ALIGN_Pos (5U) 820 #define ADC_CFGR1_ALIGN_Msk (0x1U << ADC_CFGR1_ALIGN_Pos) /*!< 0x00000020 */ 821 #define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< Data Alignment */ 822 #define ADC_CFGR1_RES_Pos (3U) 823 #define ADC_CFGR1_RES_Msk (0x3U << ADC_CFGR1_RES_Pos) /*!< 0x00000018 */ 824 #define ADC_CFGR1_RES ADC_CFGR1_RES_Msk /*!< RES[1:0] bits (Resolution) */ 825 #define ADC_CFGR1_RES_0 (0x1U << ADC_CFGR1_RES_Pos) /*!< 0x00000008 */ 826 #define ADC_CFGR1_RES_1 (0x2U << ADC_CFGR1_RES_Pos) /*!< 0x00000010 */ 827 #define ADC_CFGR1_SCANDIR_Pos (2U) 828 #define ADC_CFGR1_SCANDIR_Msk (0x1U << ADC_CFGR1_SCANDIR_Pos) /*!< 0x00000004 */ 829 #define ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR_Msk /*!< Sequence scan direction */ 830 #define ADC_CFGR1_DMACFG_Pos (1U) 831 #define ADC_CFGR1_DMACFG_Msk (0x1U << ADC_CFGR1_DMACFG_Pos) /*!< 0x00000002 */ 832 #define ADC_CFGR1_DMACFG ADC_CFGR1_DMACFG_Msk /*!< Direct memory access configuration */ 833 #define ADC_CFGR1_DMAEN_Pos (0U) 834 #define ADC_CFGR1_DMAEN_Msk (0x1U << ADC_CFGR1_DMAEN_Pos) /*!< 0x00000001 */ 835 #define ADC_CFGR1_DMAEN ADC_CFGR1_DMAEN_Msk /*!< Direct memory access enable */ 836 837 /* Old WAIT bit definition, maintained for legacy purpose */ 838 #define ADC_CFGR1_AUTDLY ADC_CFGR1_WAIT 839 840 /******************* Bits definition for ADC_CFGR2 register *****************/ 841 #define ADC_CFGR2_TOVS_Pos (9U) 842 #define ADC_CFGR2_TOVS_Msk (0x1U << ADC_CFGR2_TOVS_Pos) /*!< 0x80000200 */ 843 #define ADC_CFGR2_TOVS ADC_CFGR2_TOVS_Msk /*!< Triggered Oversampling */ 844 #define ADC_CFGR2_OVSS_Pos (5U) 845 #define ADC_CFGR2_OVSS_Msk (0xFU << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ 846 #define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< OVSS [3:0] bits (Oversampling shift) */ 847 #define ADC_CFGR2_OVSS_0 (0x1U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ 848 #define ADC_CFGR2_OVSS_1 (0x2U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ 849 #define ADC_CFGR2_OVSS_2 (0x4U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ 850 #define ADC_CFGR2_OVSS_3 (0x8U << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ 851 #define ADC_CFGR2_OVSR_Pos (2U) 852 #define ADC_CFGR2_OVSR_Msk (0x7U << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */ 853 #define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< OVSR [2:0] bits (Oversampling ratio) */ 854 #define ADC_CFGR2_OVSR_0 (0x1U << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */ 855 #define ADC_CFGR2_OVSR_1 (0x2U << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */ 856 #define ADC_CFGR2_OVSR_2 (0x4U << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */ 857 #define ADC_CFGR2_OVSE_Pos (0U) 858 #define ADC_CFGR2_OVSE_Msk (0x1U << ADC_CFGR2_OVSE_Pos) /*!< 0x00000001 */ 859 #define ADC_CFGR2_OVSE ADC_CFGR2_OVSE_Msk /*!< Oversampler Enable */ 860 #define ADC_CFGR2_CKMODE_Pos (30U) 861 #define ADC_CFGR2_CKMODE_Msk (0x3U << ADC_CFGR2_CKMODE_Pos) /*!< 0xC0000000 */ 862 #define ADC_CFGR2_CKMODE ADC_CFGR2_CKMODE_Msk /*!< CKMODE [1:0] bits (ADC clock mode) */ 863 #define ADC_CFGR2_CKMODE_0 (0x1U << ADC_CFGR2_CKMODE_Pos) /*!< 0x40000000 */ 864 #define ADC_CFGR2_CKMODE_1 (0x2U << ADC_CFGR2_CKMODE_Pos) /*!< 0x80000000 */ 865 866 867 /****************** Bit definition for ADC_SMPR register ********************/ 868 #define ADC_SMPR_SMP_Pos (0U) 869 #define ADC_SMPR_SMP_Msk (0x7U << ADC_SMPR_SMP_Pos) /*!< 0x00000007 */ 870 #define ADC_SMPR_SMP ADC_SMPR_SMP_Msk /*!< SMPR[2:0] bits (Sampling time selection) */ 871 #define ADC_SMPR_SMP_0 (0x1U << ADC_SMPR_SMP_Pos) /*!< 0x00000001 */ 872 #define ADC_SMPR_SMP_1 (0x2U << ADC_SMPR_SMP_Pos) /*!< 0x00000002 */ 873 #define ADC_SMPR_SMP_2 (0x4U << ADC_SMPR_SMP_Pos) /*!< 0x00000004 */ 874 875 /* Legacy defines */ 876 #define ADC_SMPR_SMPR ADC_SMPR_SMP 877 #define ADC_SMPR_SMPR_0 ADC_SMPR_SMP_0 878 #define ADC_SMPR_SMPR_1 ADC_SMPR_SMP_1 879 #define ADC_SMPR_SMPR_2 ADC_SMPR_SMP_2 880 881 /******************* Bit definition for ADC_TR register ********************/ 882 #define ADC_TR_HT_Pos (16U) 883 #define ADC_TR_HT_Msk (0xFFFU << ADC_TR_HT_Pos) /*!< 0x0FFF0000 */ 884 #define ADC_TR_HT ADC_TR_HT_Msk /*!< Analog watchdog high threshold */ 885 #define ADC_TR_LT_Pos (0U) 886 #define ADC_TR_LT_Msk (0xFFFU << ADC_TR_LT_Pos) /*!< 0x00000FFF */ 887 #define ADC_TR_LT ADC_TR_LT_Msk /*!< Analog watchdog low threshold */ 888 889 /****************** Bit definition for ADC_CHSELR register ******************/ 890 #define ADC_CHSELR_CHSEL_Pos (0U) 891 #define ADC_CHSELR_CHSEL_Msk (0x7FFFFU << ADC_CHSELR_CHSEL_Pos) /*!< 0x0007FFFF */ 892 #define ADC_CHSELR_CHSEL ADC_CHSELR_CHSEL_Msk /*!< ADC group regular sequencer channels */ 893 #define ADC_CHSELR_CHSEL18_Pos (18U) 894 #define ADC_CHSELR_CHSEL18_Msk (0x1U << ADC_CHSELR_CHSEL18_Pos) /*!< 0x00040000 */ 895 #define ADC_CHSELR_CHSEL18 ADC_CHSELR_CHSEL18_Msk /*!< Channel 18 selection */ 896 #define ADC_CHSELR_CHSEL17_Pos (17U) 897 #define ADC_CHSELR_CHSEL17_Msk (0x1U << ADC_CHSELR_CHSEL17_Pos) /*!< 0x00020000 */ 898 #define ADC_CHSELR_CHSEL17 ADC_CHSELR_CHSEL17_Msk /*!< Channel 17 selection */ 899 #define ADC_CHSELR_CHSEL15_Pos (15U) 900 #define ADC_CHSELR_CHSEL15_Msk (0x1U << ADC_CHSELR_CHSEL15_Pos) /*!< 0x00008000 */ 901 #define ADC_CHSELR_CHSEL15 ADC_CHSELR_CHSEL15_Msk /*!< Channel 15 selection */ 902 #define ADC_CHSELR_CHSEL14_Pos (14U) 903 #define ADC_CHSELR_CHSEL14_Msk (0x1U << ADC_CHSELR_CHSEL14_Pos) /*!< 0x00004000 */ 904 #define ADC_CHSELR_CHSEL14 ADC_CHSELR_CHSEL14_Msk /*!< Channel 14 selection */ 905 #define ADC_CHSELR_CHSEL13_Pos (13U) 906 #define ADC_CHSELR_CHSEL13_Msk (0x1U << ADC_CHSELR_CHSEL13_Pos) /*!< 0x00002000 */ 907 #define ADC_CHSELR_CHSEL13 ADC_CHSELR_CHSEL13_Msk /*!< Channel 13 selection */ 908 #define ADC_CHSELR_CHSEL12_Pos (12U) 909 #define ADC_CHSELR_CHSEL12_Msk (0x1U << ADC_CHSELR_CHSEL12_Pos) /*!< 0x00001000 */ 910 #define ADC_CHSELR_CHSEL12 ADC_CHSELR_CHSEL12_Msk /*!< Channel 12 selection */ 911 #define ADC_CHSELR_CHSEL11_Pos (11U) 912 #define ADC_CHSELR_CHSEL11_Msk (0x1U << ADC_CHSELR_CHSEL11_Pos) /*!< 0x00000800 */ 913 #define ADC_CHSELR_CHSEL11 ADC_CHSELR_CHSEL11_Msk /*!< Channel 11 selection */ 914 #define ADC_CHSELR_CHSEL10_Pos (10U) 915 #define ADC_CHSELR_CHSEL10_Msk (0x1U << ADC_CHSELR_CHSEL10_Pos) /*!< 0x00000400 */ 916 #define ADC_CHSELR_CHSEL10 ADC_CHSELR_CHSEL10_Msk /*!< Channel 10 selection */ 917 #define ADC_CHSELR_CHSEL9_Pos (9U) 918 #define ADC_CHSELR_CHSEL9_Msk (0x1U << ADC_CHSELR_CHSEL9_Pos) /*!< 0x00000200 */ 919 #define ADC_CHSELR_CHSEL9 ADC_CHSELR_CHSEL9_Msk /*!< Channel 9 selection */ 920 #define ADC_CHSELR_CHSEL8_Pos (8U) 921 #define ADC_CHSELR_CHSEL8_Msk (0x1U << ADC_CHSELR_CHSEL8_Pos) /*!< 0x00000100 */ 922 #define ADC_CHSELR_CHSEL8 ADC_CHSELR_CHSEL8_Msk /*!< Channel 8 selection */ 923 #define ADC_CHSELR_CHSEL7_Pos (7U) 924 #define ADC_CHSELR_CHSEL7_Msk (0x1U << ADC_CHSELR_CHSEL7_Pos) /*!< 0x00000080 */ 925 #define ADC_CHSELR_CHSEL7 ADC_CHSELR_CHSEL7_Msk /*!< Channel 7 selection */ 926 #define ADC_CHSELR_CHSEL6_Pos (6U) 927 #define ADC_CHSELR_CHSEL6_Msk (0x1U << ADC_CHSELR_CHSEL6_Pos) /*!< 0x00000040 */ 928 #define ADC_CHSELR_CHSEL6 ADC_CHSELR_CHSEL6_Msk /*!< Channel 6 selection */ 929 #define ADC_CHSELR_CHSEL5_Pos (5U) 930 #define ADC_CHSELR_CHSEL5_Msk (0x1U << ADC_CHSELR_CHSEL5_Pos) /*!< 0x00000020 */ 931 #define ADC_CHSELR_CHSEL5 ADC_CHSELR_CHSEL5_Msk /*!< Channel 5 selection */ 932 #define ADC_CHSELR_CHSEL4_Pos (4U) 933 #define ADC_CHSELR_CHSEL4_Msk (0x1U << ADC_CHSELR_CHSEL4_Pos) /*!< 0x00000010 */ 934 #define ADC_CHSELR_CHSEL4 ADC_CHSELR_CHSEL4_Msk /*!< Channel 4 selection */ 935 #define ADC_CHSELR_CHSEL3_Pos (3U) 936 #define ADC_CHSELR_CHSEL3_Msk (0x1U << ADC_CHSELR_CHSEL3_Pos) /*!< 0x00000008 */ 937 #define ADC_CHSELR_CHSEL3 ADC_CHSELR_CHSEL3_Msk /*!< Channel 3 selection */ 938 #define ADC_CHSELR_CHSEL2_Pos (2U) 939 #define ADC_CHSELR_CHSEL2_Msk (0x1U << ADC_CHSELR_CHSEL2_Pos) /*!< 0x00000004 */ 940 #define ADC_CHSELR_CHSEL2 ADC_CHSELR_CHSEL2_Msk /*!< Channel 2 selection */ 941 #define ADC_CHSELR_CHSEL1_Pos (1U) 942 #define ADC_CHSELR_CHSEL1_Msk (0x1U << ADC_CHSELR_CHSEL1_Pos) /*!< 0x00000002 */ 943 #define ADC_CHSELR_CHSEL1 ADC_CHSELR_CHSEL1_Msk /*!< Channel 1 selection */ 944 #define ADC_CHSELR_CHSEL0_Pos (0U) 945 #define ADC_CHSELR_CHSEL0_Msk (0x1U << ADC_CHSELR_CHSEL0_Pos) /*!< 0x00000001 */ 946 #define ADC_CHSELR_CHSEL0 ADC_CHSELR_CHSEL0_Msk /*!< Channel 0 selection */ 947 948 /******************** Bit definition for ADC_DR register ********************/ 949 #define ADC_DR_DATA_Pos (0U) 950 #define ADC_DR_DATA_Msk (0xFFFFU << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */ 951 #define ADC_DR_DATA ADC_DR_DATA_Msk /*!< Regular data */ 952 953 /******************** Bit definition for ADC_CALFACT register ********************/ 954 #define ADC_CALFACT_CALFACT_Pos (0U) 955 #define ADC_CALFACT_CALFACT_Msk (0x7FU << ADC_CALFACT_CALFACT_Pos) /*!< 0x0000007F */ 956 #define ADC_CALFACT_CALFACT ADC_CALFACT_CALFACT_Msk /*!< Calibration factor */ 957 958 /******************* Bit definition for ADC_CCR register ********************/ 959 #define ADC_CCR_LFMEN_Pos (25U) 960 #define ADC_CCR_LFMEN_Msk (0x1U << ADC_CCR_LFMEN_Pos) /*!< 0x02000000 */ 961 #define ADC_CCR_LFMEN ADC_CCR_LFMEN_Msk /*!< Low Frequency Mode enable */ 962 #define ADC_CCR_TSEN_Pos (23U) 963 #define ADC_CCR_TSEN_Msk (0x1U << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ 964 #define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< Temperature sensore enable */ 965 #define ADC_CCR_VREFEN_Pos (22U) 966 #define ADC_CCR_VREFEN_Msk (0x1U << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ 967 #define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< Vrefint enable */ 968 #define ADC_CCR_PRESC_Pos (18U) 969 #define ADC_CCR_PRESC_Msk (0xFU << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ 970 #define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< PRESC [3:0] bits (ADC prescaler) */ 971 #define ADC_CCR_PRESC_0 (0x1U << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ 972 #define ADC_CCR_PRESC_1 (0x2U << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */ 973 #define ADC_CCR_PRESC_2 (0x4U << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ 974 #define ADC_CCR_PRESC_3 (0x8U << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ 975 976 /******************************************************************************/ 977 /* */ 978 /* Advanced Encryption Standard (AES) */ 979 /* */ 980 /******************************************************************************/ 981 /******************* Bit definition for AES_CR register *********************/ 982 #define AES_CR_EN_Pos (0U) 983 #define AES_CR_EN_Msk (0x1U << AES_CR_EN_Pos) /*!< 0x00000001 */ 984 #define AES_CR_EN AES_CR_EN_Msk /*!< AES Enable */ 985 #define AES_CR_DATATYPE_Pos (1U) 986 #define AES_CR_DATATYPE_Msk (0x3U << AES_CR_DATATYPE_Pos) /*!< 0x00000006 */ 987 #define AES_CR_DATATYPE AES_CR_DATATYPE_Msk /*!< Data type selection */ 988 #define AES_CR_DATATYPE_0 (0x1U << AES_CR_DATATYPE_Pos) /*!< 0x00000002 */ 989 #define AES_CR_DATATYPE_1 (0x2U << AES_CR_DATATYPE_Pos) /*!< 0x00000004 */ 990 991 #define AES_CR_MODE_Pos (3U) 992 #define AES_CR_MODE_Msk (0x3U << AES_CR_MODE_Pos) /*!< 0x00000018 */ 993 #define AES_CR_MODE AES_CR_MODE_Msk /*!< AES Mode Of Operation */ 994 #define AES_CR_MODE_0 (0x1U << AES_CR_MODE_Pos) /*!< 0x00000008 */ 995 #define AES_CR_MODE_1 (0x2U << AES_CR_MODE_Pos) /*!< 0x00000010 */ 996 997 #define AES_CR_CHMOD_Pos (5U) 998 #define AES_CR_CHMOD_Msk (0x3U << AES_CR_CHMOD_Pos) /*!< 0x00000060 */ 999 #define AES_CR_CHMOD AES_CR_CHMOD_Msk /*!< AES Chaining Mode */ 1000 #define AES_CR_CHMOD_0 (0x1U << AES_CR_CHMOD_Pos) /*!< 0x00000020 */ 1001 #define AES_CR_CHMOD_1 (0x2U << AES_CR_CHMOD_Pos) /*!< 0x00000040 */ 1002 1003 #define AES_CR_CCFC_Pos (7U) 1004 #define AES_CR_CCFC_Msk (0x1U << AES_CR_CCFC_Pos) /*!< 0x00000080 */ 1005 #define AES_CR_CCFC AES_CR_CCFC_Msk /*!< Computation Complete Flag Clear */ 1006 #define AES_CR_ERRC_Pos (8U) 1007 #define AES_CR_ERRC_Msk (0x1U << AES_CR_ERRC_Pos) /*!< 0x00000100 */ 1008 #define AES_CR_ERRC AES_CR_ERRC_Msk /*!< Error Clear */ 1009 #define AES_CR_CCIE_Pos (9U) 1010 #define AES_CR_CCIE_Msk (0x1U << AES_CR_CCIE_Pos) /*!< 0x00000200 */ 1011 #define AES_CR_CCIE AES_CR_CCIE_Msk /*!< Computation Complete Interrupt Enable */ 1012 #define AES_CR_ERRIE_Pos (10U) 1013 #define AES_CR_ERRIE_Msk (0x1U << AES_CR_ERRIE_Pos) /*!< 0x00000400 */ 1014 #define AES_CR_ERRIE AES_CR_ERRIE_Msk /*!< Error Interrupt Enable */ 1015 #define AES_CR_DMAINEN_Pos (11U) 1016 #define AES_CR_DMAINEN_Msk (0x1U << AES_CR_DMAINEN_Pos) /*!< 0x00000800 */ 1017 #define AES_CR_DMAINEN AES_CR_DMAINEN_Msk /*!< DMA ENable managing the data input phase */ 1018 #define AES_CR_DMAOUTEN_Pos (12U) 1019 #define AES_CR_DMAOUTEN_Msk (0x1U << AES_CR_DMAOUTEN_Pos) /*!< 0x00001000 */ 1020 #define AES_CR_DMAOUTEN AES_CR_DMAOUTEN_Msk /*!< DMA Enable managing the data output phase */ 1021 1022 /******************* Bit definition for AES_SR register *********************/ 1023 #define AES_SR_CCF_Pos (0U) 1024 #define AES_SR_CCF_Msk (0x1U << AES_SR_CCF_Pos) /*!< 0x00000001 */ 1025 #define AES_SR_CCF AES_SR_CCF_Msk /*!< Computation Complete Flag */ 1026 #define AES_SR_RDERR_Pos (1U) 1027 #define AES_SR_RDERR_Msk (0x1U << AES_SR_RDERR_Pos) /*!< 0x00000002 */ 1028 #define AES_SR_RDERR AES_SR_RDERR_Msk /*!< Read Error Flag */ 1029 #define AES_SR_WRERR_Pos (2U) 1030 #define AES_SR_WRERR_Msk (0x1U << AES_SR_WRERR_Pos) /*!< 0x00000004 */ 1031 #define AES_SR_WRERR AES_SR_WRERR_Msk /*!< Write Error Flag */ 1032 1033 /******************* Bit definition for AES_DINR register *******************/ 1034 #define AES_DINR_Pos (0U) 1035 #define AES_DINR_Msk (0xFFFFU << AES_DINR_Pos) /*!< 0x0000FFFF */ 1036 #define AES_DINR AES_DINR_Msk /*!< AES Data Input Register */ 1037 1038 /******************* Bit definition for AES_DOUTR register ******************/ 1039 #define AES_DOUTR_Pos (0U) 1040 #define AES_DOUTR_Msk (0xFFFFU << AES_DOUTR_Pos) /*!< 0x0000FFFF */ 1041 #define AES_DOUTR AES_DOUTR_Msk /*!< AES Data Output Register */ 1042 1043 /******************* Bit definition for AES_KEYR0 register ******************/ 1044 #define AES_KEYR0_Pos (0U) 1045 #define AES_KEYR0_Msk (0xFFFFU << AES_KEYR0_Pos) /*!< 0x0000FFFF */ 1046 #define AES_KEYR0 AES_KEYR0_Msk /*!< AES Key Register 0 */ 1047 1048 /******************* Bit definition for AES_KEYR1 register ******************/ 1049 #define AES_KEYR1_Pos (0U) 1050 #define AES_KEYR1_Msk (0xFFFFU << AES_KEYR1_Pos) /*!< 0x0000FFFF */ 1051 #define AES_KEYR1 AES_KEYR1_Msk /*!< AES Key Register 1 */ 1052 1053 /******************* Bit definition for AES_KEYR2 register ******************/ 1054 #define AES_KEYR2_Pos (0U) 1055 #define AES_KEYR2_Msk (0xFFFFU << AES_KEYR2_Pos) /*!< 0x0000FFFF */ 1056 #define AES_KEYR2 AES_KEYR2_Msk /*!< AES Key Register 2 */ 1057 1058 /******************* Bit definition for AES_KEYR3 register ******************/ 1059 #define AES_KEYR3_Pos (0U) 1060 #define AES_KEYR3_Msk (0xFFFFU << AES_KEYR3_Pos) /*!< 0x0000FFFF */ 1061 #define AES_KEYR3 AES_KEYR3_Msk /*!< AES Key Register 3 */ 1062 1063 /******************* Bit definition for AES_IVR0 register *******************/ 1064 #define AES_IVR0_Pos (0U) 1065 #define AES_IVR0_Msk (0xFFFFU << AES_IVR0_Pos) /*!< 0x0000FFFF */ 1066 #define AES_IVR0 AES_IVR0_Msk /*!< AES Initialization Vector Register 0 */ 1067 1068 /******************* Bit definition for AES_IVR1 register *******************/ 1069 #define AES_IVR1_Pos (0U) 1070 #define AES_IVR1_Msk (0xFFFFU << AES_IVR1_Pos) /*!< 0x0000FFFF */ 1071 #define AES_IVR1 AES_IVR1_Msk /*!< AES Initialization Vector Register 1 */ 1072 1073 /******************* Bit definition for AES_IVR2 register *******************/ 1074 #define AES_IVR2_Pos (0U) 1075 #define AES_IVR2_Msk (0xFFFFU << AES_IVR2_Pos) /*!< 0x0000FFFF */ 1076 #define AES_IVR2 AES_IVR2_Msk /*!< AES Initialization Vector Register 2 */ 1077 1078 /******************* Bit definition for AES_IVR3 register *******************/ 1079 #define AES_IVR3_Pos (0U) 1080 #define AES_IVR3_Msk (0xFFFFU << AES_IVR3_Pos) /*!< 0x0000FFFF */ 1081 #define AES_IVR3 AES_IVR3_Msk /*!< AES Initialization Vector Register 3 */ 1082 1083 /******************************************************************************/ 1084 /* */ 1085 /* Analog Comparators (COMP) */ 1086 /* */ 1087 /******************************************************************************/ 1088 /************* Bit definition for COMP_CSR register (COMP1 and COMP2) **************/ 1089 /* COMP1 bits definition */ 1090 #define COMP_CSR_COMP1EN_Pos (0U) 1091 #define COMP_CSR_COMP1EN_Msk (0x1U << COMP_CSR_COMP1EN_Pos) /*!< 0x00000001 */ 1092 #define COMP_CSR_COMP1EN COMP_CSR_COMP1EN_Msk /*!< COMP1 enable */ 1093 #define COMP_CSR_COMP1INNSEL_Pos (4U) 1094 #define COMP_CSR_COMP1INNSEL_Msk (0x3U << COMP_CSR_COMP1INNSEL_Pos) /*!< 0x00000030 */ 1095 #define COMP_CSR_COMP1INNSEL COMP_CSR_COMP1INNSEL_Msk /*!< COMP1 inverting input select */ 1096 #define COMP_CSR_COMP1INNSEL_0 (0x1U << COMP_CSR_COMP1INNSEL_Pos) /*!< 0x00000010 */ 1097 #define COMP_CSR_COMP1INNSEL_1 (0x2U << COMP_CSR_COMP1INNSEL_Pos) /*!< 0x00000020 */ 1098 #define COMP_CSR_COMP1WM_Pos (8U) 1099 #define COMP_CSR_COMP1WM_Msk (0x1U << COMP_CSR_COMP1WM_Pos) /*!< 0x00000100 */ 1100 #define COMP_CSR_COMP1WM COMP_CSR_COMP1WM_Msk /*!< Comparators window mode enable */ 1101 #define COMP_CSR_COMP1LPTIM1IN1_Pos (12U) 1102 #define COMP_CSR_COMP1LPTIM1IN1_Msk (0x1U << COMP_CSR_COMP1LPTIM1IN1_Pos) /*!< 0x00001000 */ 1103 #define COMP_CSR_COMP1LPTIM1IN1 COMP_CSR_COMP1LPTIM1IN1_Msk /*!< COMP1 LPTIM1 IN1 connection */ 1104 #define COMP_CSR_COMP1POLARITY_Pos (15U) 1105 #define COMP_CSR_COMP1POLARITY_Msk (0x1U << COMP_CSR_COMP1POLARITY_Pos) /*!< 0x00008000 */ 1106 #define COMP_CSR_COMP1POLARITY COMP_CSR_COMP1POLARITY_Msk /*!< COMP1 output polarity */ 1107 #define COMP_CSR_COMP1VALUE_Pos (30U) 1108 #define COMP_CSR_COMP1VALUE_Msk (0x1U << COMP_CSR_COMP1VALUE_Pos) /*!< 0x40000000 */ 1109 #define COMP_CSR_COMP1VALUE COMP_CSR_COMP1VALUE_Msk /*!< COMP1 output level */ 1110 #define COMP_CSR_COMP1LOCK_Pos (31U) 1111 #define COMP_CSR_COMP1LOCK_Msk (0x1U << COMP_CSR_COMP1LOCK_Pos) /*!< 0x80000000 */ 1112 #define COMP_CSR_COMP1LOCK COMP_CSR_COMP1LOCK_Msk /*!< COMP1 lock */ 1113 /* COMP2 bits definition */ 1114 #define COMP_CSR_COMP2EN_Pos (0U) 1115 #define COMP_CSR_COMP2EN_Msk (0x1U << COMP_CSR_COMP2EN_Pos) /*!< 0x00000001 */ 1116 #define COMP_CSR_COMP2EN COMP_CSR_COMP2EN_Msk /*!< COMP2 enable */ 1117 #define COMP_CSR_COMP2SPEED_Pos (3U) 1118 #define COMP_CSR_COMP2SPEED_Msk (0x1U << COMP_CSR_COMP2SPEED_Pos) /*!< 0x00000008 */ 1119 #define COMP_CSR_COMP2SPEED COMP_CSR_COMP2SPEED_Msk /*!< COMP2 power mode */ 1120 #define COMP_CSR_COMP2INNSEL_Pos (4U) 1121 #define COMP_CSR_COMP2INNSEL_Msk (0x7U << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000070 */ 1122 #define COMP_CSR_COMP2INNSEL COMP_CSR_COMP2INNSEL_Msk /*!< COMP2 inverting input select */ 1123 #define COMP_CSR_COMP2INNSEL_0 (0x1U << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000010 */ 1124 #define COMP_CSR_COMP2INNSEL_1 (0x2U << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000020 */ 1125 #define COMP_CSR_COMP2INNSEL_2 (0x4U << COMP_CSR_COMP2INNSEL_Pos) /*!< 0x00000040 */ 1126 #define COMP_CSR_COMP2INPSEL_Pos (8U) 1127 #define COMP_CSR_COMP2INPSEL_Msk (0x7U << COMP_CSR_COMP2INPSEL_Pos) /*!< 0x00000700 */ 1128 #define COMP_CSR_COMP2INPSEL COMP_CSR_COMP2INPSEL_Msk /*!< COMPx non inverting input select */ 1129 #define COMP_CSR_COMP2INPSEL_0 (0x1U << COMP_CSR_COMP2INPSEL_Pos) /*!< 0x00000100 */ 1130 #define COMP_CSR_COMP2INPSEL_1 (0x2U << COMP_CSR_COMP2INPSEL_Pos) /*!< 0x00000200 */ 1131 #define COMP_CSR_COMP2INPSEL_2 (0x4U << COMP_CSR_COMP2INPSEL_Pos) /*!< 0x00000400 */ 1132 #define COMP_CSR_COMP2LPTIM1IN2_Pos (12U) 1133 #define COMP_CSR_COMP2LPTIM1IN2_Msk (0x1U << COMP_CSR_COMP2LPTIM1IN2_Pos) /*!< 0x00001000 */ 1134 #define COMP_CSR_COMP2LPTIM1IN2 COMP_CSR_COMP2LPTIM1IN2_Msk /*!< COMP2 LPTIM1 IN2 connection */ 1135 #define COMP_CSR_COMP2LPTIM1IN1_Pos (13U) 1136 #define COMP_CSR_COMP2LPTIM1IN1_Msk (0x1U << COMP_CSR_COMP2LPTIM1IN1_Pos) /*!< 0x00002000 */ 1137 #define COMP_CSR_COMP2LPTIM1IN1 COMP_CSR_COMP2LPTIM1IN1_Msk /*!< COMP2 LPTIM1 IN1 connection */ 1138 #define COMP_CSR_COMP2POLARITY_Pos (15U) 1139 #define COMP_CSR_COMP2POLARITY_Msk (0x1U << COMP_CSR_COMP2POLARITY_Pos) /*!< 0x00008000 */ 1140 #define COMP_CSR_COMP2POLARITY COMP_CSR_COMP2POLARITY_Msk /*!< COMP2 output polarity */ 1141 #define COMP_CSR_COMP2VALUE_Pos (30U) 1142 #define COMP_CSR_COMP2VALUE_Msk (0x1U << COMP_CSR_COMP2VALUE_Pos) /*!< 0x40000000 */ 1143 #define COMP_CSR_COMP2VALUE COMP_CSR_COMP2VALUE_Msk /*!< COMP2 output level */ 1144 #define COMP_CSR_COMP2LOCK_Pos (31U) 1145 #define COMP_CSR_COMP2LOCK_Msk (0x1U << COMP_CSR_COMP2LOCK_Pos) /*!< 0x80000000 */ 1146 #define COMP_CSR_COMP2LOCK COMP_CSR_COMP2LOCK_Msk /*!< COMP2 lock */ 1147 1148 /********************** Bit definition for COMP_CSR register common ****************/ 1149 #define COMP_CSR_COMPxEN_Pos (0U) 1150 #define COMP_CSR_COMPxEN_Msk (0x1U << COMP_CSR_COMPxEN_Pos) /*!< 0x00000001 */ 1151 #define COMP_CSR_COMPxEN COMP_CSR_COMPxEN_Msk /*!< COMPx enable */ 1152 #define COMP_CSR_COMPxPOLARITY_Pos (15U) 1153 #define COMP_CSR_COMPxPOLARITY_Msk (0x1U << COMP_CSR_COMPxPOLARITY_Pos) /*!< 0x00008000 */ 1154 #define COMP_CSR_COMPxPOLARITY COMP_CSR_COMPxPOLARITY_Msk /*!< COMPx output polarity */ 1155 #define COMP_CSR_COMPxOUTVALUE_Pos (30U) 1156 #define COMP_CSR_COMPxOUTVALUE_Msk (0x1U << COMP_CSR_COMPxOUTVALUE_Pos) /*!< 0x40000000 */ 1157 #define COMP_CSR_COMPxOUTVALUE COMP_CSR_COMPxOUTVALUE_Msk /*!< COMPx output level */ 1158 #define COMP_CSR_COMPxLOCK_Pos (31U) 1159 #define COMP_CSR_COMPxLOCK_Msk (0x1U << COMP_CSR_COMPxLOCK_Pos) /*!< 0x80000000 */ 1160 #define COMP_CSR_COMPxLOCK COMP_CSR_COMPxLOCK_Msk /*!< COMPx lock */ 1161 1162 /* Reference defines */ 1163 #define COMP_CSR_WINMODE COMP_CSR_COMP1WM /*!< Bit intended to be used with COMP common instance (COMP_Common_TypeDef) */ 1164 1165 /******************************************************************************/ 1166 /* */ 1167 /* CRC calculation unit (CRC) */ 1168 /* */ 1169 /******************************************************************************/ 1170 /******************* Bit definition for CRC_DR register *********************/ 1171 #define CRC_DR_DR_Pos (0U) 1172 #define CRC_DR_DR_Msk (0xFFFFFFFFU << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ 1173 #define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ 1174 1175 /******************* Bit definition for CRC_IDR register ********************/ 1176 #define CRC_IDR_IDR ((uint8_t)0xFFU) /*!< General-purpose 8-bit data register bits */ 1177 1178 /******************** Bit definition for CRC_CR register ********************/ 1179 #define CRC_CR_RESET_Pos (0U) 1180 #define CRC_CR_RESET_Msk (0x1U << CRC_CR_RESET_Pos) /*!< 0x00000001 */ 1181 #define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */ 1182 #define CRC_CR_POLYSIZE_Pos (3U) 1183 #define CRC_CR_POLYSIZE_Msk (0x3U << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */ 1184 #define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */ 1185 #define CRC_CR_POLYSIZE_0 (0x1U << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */ 1186 #define CRC_CR_POLYSIZE_1 (0x2U << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */ 1187 #define CRC_CR_REV_IN_Pos (5U) 1188 #define CRC_CR_REV_IN_Msk (0x3U << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */ 1189 #define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */ 1190 #define CRC_CR_REV_IN_0 (0x1U << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */ 1191 #define CRC_CR_REV_IN_1 (0x2U << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */ 1192 #define CRC_CR_REV_OUT_Pos (7U) 1193 #define CRC_CR_REV_OUT_Msk (0x1U << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */ 1194 #define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */ 1195 1196 /******************* Bit definition for CRC_INIT register *******************/ 1197 #define CRC_INIT_INIT_Pos (0U) 1198 #define CRC_INIT_INIT_Msk (0xFFFFFFFFU << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */ 1199 #define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */ 1200 1201 /******************* Bit definition for CRC_POL register ********************/ 1202 #define CRC_POL_POL_Pos (0U) 1203 #define CRC_POL_POL_Msk (0xFFFFFFFFU << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */ 1204 #define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */ 1205 1206 /******************************************************************************/ 1207 /* */ 1208 /* Debug MCU (DBGMCU) */ 1209 /* */ 1210 /******************************************************************************/ 1211 1212 /**************** Bit definition for DBGMCU_IDCODE register *****************/ 1213 #define DBGMCU_IDCODE_DEV_ID_Pos (0U) 1214 #define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */ 1215 #define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk /*!< Device Identifier */ 1216 1217 #define DBGMCU_IDCODE_REV_ID_Pos (16U) 1218 #define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */ 1219 #define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk /*!< REV_ID[15:0] bits (Revision Identifier) */ 1220 #define DBGMCU_IDCODE_REV_ID_0 (0x0001U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */ 1221 #define DBGMCU_IDCODE_REV_ID_1 (0x0002U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */ 1222 #define DBGMCU_IDCODE_REV_ID_2 (0x0004U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */ 1223 #define DBGMCU_IDCODE_REV_ID_3 (0x0008U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */ 1224 #define DBGMCU_IDCODE_REV_ID_4 (0x0010U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */ 1225 #define DBGMCU_IDCODE_REV_ID_5 (0x0020U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */ 1226 #define DBGMCU_IDCODE_REV_ID_6 (0x0040U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */ 1227 #define DBGMCU_IDCODE_REV_ID_7 (0x0080U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */ 1228 #define DBGMCU_IDCODE_REV_ID_8 (0x0100U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */ 1229 #define DBGMCU_IDCODE_REV_ID_9 (0x0200U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */ 1230 #define DBGMCU_IDCODE_REV_ID_10 (0x0400U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */ 1231 #define DBGMCU_IDCODE_REV_ID_11 (0x0800U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */ 1232 #define DBGMCU_IDCODE_REV_ID_12 (0x1000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */ 1233 #define DBGMCU_IDCODE_REV_ID_13 (0x2000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */ 1234 #define DBGMCU_IDCODE_REV_ID_14 (0x4000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */ 1235 #define DBGMCU_IDCODE_REV_ID_15 (0x8000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */ 1236 1237 /****************** Bit definition for DBGMCU_CR register *******************/ 1238 #define DBGMCU_CR_DBG_Pos (0U) 1239 #define DBGMCU_CR_DBG_Msk (0x7U << DBGMCU_CR_DBG_Pos) /*!< 0x00000007 */ 1240 #define DBGMCU_CR_DBG DBGMCU_CR_DBG_Msk /*!< Debug mode mask */ 1241 #define DBGMCU_CR_DBG_SLEEP_Pos (0U) 1242 #define DBGMCU_CR_DBG_SLEEP_Msk (0x1U << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */ 1243 #define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk /*!< Debug Sleep Mode */ 1244 #define DBGMCU_CR_DBG_STOP_Pos (1U) 1245 #define DBGMCU_CR_DBG_STOP_Msk (0x1U << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */ 1246 #define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk /*!< Debug Stop Mode */ 1247 #define DBGMCU_CR_DBG_STANDBY_Pos (2U) 1248 #define DBGMCU_CR_DBG_STANDBY_Msk (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */ 1249 #define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk /*!< Debug Standby mode */ 1250 1251 /****************** Bit definition for DBGMCU_APB1_FZ register **************/ 1252 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos (0U) 1253 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */ 1254 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk /*!< TIM2 counter stopped when core is halted */ 1255 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos (1U) 1256 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */ 1257 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk 1258 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos (4U) 1259 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */ 1260 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk /*!< TIM6 counter stopped when core is halted */ 1261 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos (5U) 1262 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */ 1263 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk 1264 #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U) 1265 #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */ 1266 #define DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk /*!< RTC Calendar frozen when core is halted */ 1267 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U) 1268 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */ 1269 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk /*!< Debug Window Watchdog stopped when Core is halted */ 1270 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U) 1271 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */ 1272 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk /*!< Debug Independent Watchdog stopped when Core is halted */ 1273 #define DBGMCU_APB1_FZ_DBG_I2C1_STOP_Pos (21U) 1274 #define DBGMCU_APB1_FZ_DBG_I2C1_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C1_STOP_Pos) /*!< 0x00200000 */ 1275 #define DBGMCU_APB1_FZ_DBG_I2C1_STOP DBGMCU_APB1_FZ_DBG_I2C1_STOP_Msk /*!< I2C1 SMBUS timeout mode stopped when Core is halted */ 1276 #define DBGMCU_APB1_FZ_DBG_I2C2_STOP_Pos (22U) 1277 #define DBGMCU_APB1_FZ_DBG_I2C2_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C2_STOP_Pos) /*!< 0x00400000 */ 1278 #define DBGMCU_APB1_FZ_DBG_I2C2_STOP DBGMCU_APB1_FZ_DBG_I2C2_STOP_Msk /*!< I2C2 SMBUS timeout mode stopped when Core is halted */ 1279 #define DBGMCU_APB1_FZ_DBG_I2C3_STOP_Pos (23U) 1280 #define DBGMCU_APB1_FZ_DBG_I2C3_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C3_STOP_Pos) /*!< 0x00800000 */ 1281 #define DBGMCU_APB1_FZ_DBG_I2C3_STOP DBGMCU_APB1_FZ_DBG_I2C3_STOP_Msk /*!< I2C3 SMBUS timeout mode stopped when Core is halted */ 1282 #define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Pos (31U) 1283 #define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Pos) /*!< 0x80000000 */ 1284 #define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP DBGMCU_APB1_FZ_DBG_LPTIMER_STOP_Msk /*!< LPTIM1 counter stopped when core is halted */ 1285 /****************** Bit definition for DBGMCU_APB2_FZ register **************/ 1286 #define DBGMCU_APB2_FZ_DBG_TIM22_STOP_Pos (5U) 1287 #define DBGMCU_APB2_FZ_DBG_TIM22_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM22_STOP_Pos) /*!< 0x00000020 */ 1288 #define DBGMCU_APB2_FZ_DBG_TIM22_STOP DBGMCU_APB2_FZ_DBG_TIM22_STOP_Msk /*!< TIM22 counter stopped when core is halted */ 1289 #define DBGMCU_APB2_FZ_DBG_TIM21_STOP_Pos (2U) 1290 #define DBGMCU_APB2_FZ_DBG_TIM21_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM21_STOP_Pos) /*!< 0x00000004 */ 1291 #define DBGMCU_APB2_FZ_DBG_TIM21_STOP DBGMCU_APB2_FZ_DBG_TIM21_STOP_Msk /*!< TIM21 counter stopped when core is halted */ 1292 1293 /******************************************************************************/ 1294 /* */ 1295 /* DMA Controller (DMA) */ 1296 /* */ 1297 /******************************************************************************/ 1298 1299 /******************* Bit definition for DMA_ISR register ********************/ 1300 #define DMA_ISR_GIF1_Pos (0U) 1301 #define DMA_ISR_GIF1_Msk (0x1U << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */ 1302 #define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */ 1303 #define DMA_ISR_TCIF1_Pos (1U) 1304 #define DMA_ISR_TCIF1_Msk (0x1U << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */ 1305 #define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */ 1306 #define DMA_ISR_HTIF1_Pos (2U) 1307 #define DMA_ISR_HTIF1_Msk (0x1U << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */ 1308 #define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */ 1309 #define DMA_ISR_TEIF1_Pos (3U) 1310 #define DMA_ISR_TEIF1_Msk (0x1U << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */ 1311 #define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */ 1312 #define DMA_ISR_GIF2_Pos (4U) 1313 #define DMA_ISR_GIF2_Msk (0x1U << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */ 1314 #define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */ 1315 #define DMA_ISR_TCIF2_Pos (5U) 1316 #define DMA_ISR_TCIF2_Msk (0x1U << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */ 1317 #define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */ 1318 #define DMA_ISR_HTIF2_Pos (6U) 1319 #define DMA_ISR_HTIF2_Msk (0x1U << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */ 1320 #define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */ 1321 #define DMA_ISR_TEIF2_Pos (7U) 1322 #define DMA_ISR_TEIF2_Msk (0x1U << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */ 1323 #define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */ 1324 #define DMA_ISR_GIF3_Pos (8U) 1325 #define DMA_ISR_GIF3_Msk (0x1U << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */ 1326 #define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */ 1327 #define DMA_ISR_TCIF3_Pos (9U) 1328 #define DMA_ISR_TCIF3_Msk (0x1U << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */ 1329 #define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */ 1330 #define DMA_ISR_HTIF3_Pos (10U) 1331 #define DMA_ISR_HTIF3_Msk (0x1U << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */ 1332 #define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */ 1333 #define DMA_ISR_TEIF3_Pos (11U) 1334 #define DMA_ISR_TEIF3_Msk (0x1U << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */ 1335 #define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */ 1336 #define DMA_ISR_GIF4_Pos (12U) 1337 #define DMA_ISR_GIF4_Msk (0x1U << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */ 1338 #define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */ 1339 #define DMA_ISR_TCIF4_Pos (13U) 1340 #define DMA_ISR_TCIF4_Msk (0x1U << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */ 1341 #define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */ 1342 #define DMA_ISR_HTIF4_Pos (14U) 1343 #define DMA_ISR_HTIF4_Msk (0x1U << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */ 1344 #define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */ 1345 #define DMA_ISR_TEIF4_Pos (15U) 1346 #define DMA_ISR_TEIF4_Msk (0x1U << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */ 1347 #define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */ 1348 #define DMA_ISR_GIF5_Pos (16U) 1349 #define DMA_ISR_GIF5_Msk (0x1U << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */ 1350 #define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */ 1351 #define DMA_ISR_TCIF5_Pos (17U) 1352 #define DMA_ISR_TCIF5_Msk (0x1U << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */ 1353 #define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */ 1354 #define DMA_ISR_HTIF5_Pos (18U) 1355 #define DMA_ISR_HTIF5_Msk (0x1U << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */ 1356 #define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */ 1357 #define DMA_ISR_TEIF5_Pos (19U) 1358 #define DMA_ISR_TEIF5_Msk (0x1U << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */ 1359 #define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */ 1360 #define DMA_ISR_GIF6_Pos (20U) 1361 #define DMA_ISR_GIF6_Msk (0x1U << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */ 1362 #define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */ 1363 #define DMA_ISR_TCIF6_Pos (21U) 1364 #define DMA_ISR_TCIF6_Msk (0x1U << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */ 1365 #define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */ 1366 #define DMA_ISR_HTIF6_Pos (22U) 1367 #define DMA_ISR_HTIF6_Msk (0x1U << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */ 1368 #define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */ 1369 #define DMA_ISR_TEIF6_Pos (23U) 1370 #define DMA_ISR_TEIF6_Msk (0x1U << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */ 1371 #define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */ 1372 #define DMA_ISR_GIF7_Pos (24U) 1373 #define DMA_ISR_GIF7_Msk (0x1U << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */ 1374 #define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */ 1375 #define DMA_ISR_TCIF7_Pos (25U) 1376 #define DMA_ISR_TCIF7_Msk (0x1U << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */ 1377 #define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */ 1378 #define DMA_ISR_HTIF7_Pos (26U) 1379 #define DMA_ISR_HTIF7_Msk (0x1U << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */ 1380 #define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */ 1381 #define DMA_ISR_TEIF7_Pos (27U) 1382 #define DMA_ISR_TEIF7_Msk (0x1U << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */ 1383 #define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */ 1384 1385 /******************* Bit definition for DMA_IFCR register *******************/ 1386 #define DMA_IFCR_CGIF1_Pos (0U) 1387 #define DMA_IFCR_CGIF1_Msk (0x1U << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */ 1388 #define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clear */ 1389 #define DMA_IFCR_CTCIF1_Pos (1U) 1390 #define DMA_IFCR_CTCIF1_Msk (0x1U << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */ 1391 #define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */ 1392 #define DMA_IFCR_CHTIF1_Pos (2U) 1393 #define DMA_IFCR_CHTIF1_Msk (0x1U << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */ 1394 #define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */ 1395 #define DMA_IFCR_CTEIF1_Pos (3U) 1396 #define DMA_IFCR_CTEIF1_Msk (0x1U << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */ 1397 #define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */ 1398 #define DMA_IFCR_CGIF2_Pos (4U) 1399 #define DMA_IFCR_CGIF2_Msk (0x1U << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */ 1400 #define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */ 1401 #define DMA_IFCR_CTCIF2_Pos (5U) 1402 #define DMA_IFCR_CTCIF2_Msk (0x1U << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */ 1403 #define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */ 1404 #define DMA_IFCR_CHTIF2_Pos (6U) 1405 #define DMA_IFCR_CHTIF2_Msk (0x1U << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */ 1406 #define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */ 1407 #define DMA_IFCR_CTEIF2_Pos (7U) 1408 #define DMA_IFCR_CTEIF2_Msk (0x1U << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */ 1409 #define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */ 1410 #define DMA_IFCR_CGIF3_Pos (8U) 1411 #define DMA_IFCR_CGIF3_Msk (0x1U << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */ 1412 #define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */ 1413 #define DMA_IFCR_CTCIF3_Pos (9U) 1414 #define DMA_IFCR_CTCIF3_Msk (0x1U << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */ 1415 #define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */ 1416 #define DMA_IFCR_CHTIF3_Pos (10U) 1417 #define DMA_IFCR_CHTIF3_Msk (0x1U << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */ 1418 #define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */ 1419 #define DMA_IFCR_CTEIF3_Pos (11U) 1420 #define DMA_IFCR_CTEIF3_Msk (0x1U << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */ 1421 #define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */ 1422 #define DMA_IFCR_CGIF4_Pos (12U) 1423 #define DMA_IFCR_CGIF4_Msk (0x1U << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */ 1424 #define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */ 1425 #define DMA_IFCR_CTCIF4_Pos (13U) 1426 #define DMA_IFCR_CTCIF4_Msk (0x1U << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */ 1427 #define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */ 1428 #define DMA_IFCR_CHTIF4_Pos (14U) 1429 #define DMA_IFCR_CHTIF4_Msk (0x1U << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */ 1430 #define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */ 1431 #define DMA_IFCR_CTEIF4_Pos (15U) 1432 #define DMA_IFCR_CTEIF4_Msk (0x1U << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */ 1433 #define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */ 1434 #define DMA_IFCR_CGIF5_Pos (16U) 1435 #define DMA_IFCR_CGIF5_Msk (0x1U << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */ 1436 #define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */ 1437 #define DMA_IFCR_CTCIF5_Pos (17U) 1438 #define DMA_IFCR_CTCIF5_Msk (0x1U << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */ 1439 #define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */ 1440 #define DMA_IFCR_CHTIF5_Pos (18U) 1441 #define DMA_IFCR_CHTIF5_Msk (0x1U << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */ 1442 #define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */ 1443 #define DMA_IFCR_CTEIF5_Pos (19U) 1444 #define DMA_IFCR_CTEIF5_Msk (0x1U << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */ 1445 #define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */ 1446 #define DMA_IFCR_CGIF6_Pos (20U) 1447 #define DMA_IFCR_CGIF6_Msk (0x1U << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */ 1448 #define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */ 1449 #define DMA_IFCR_CTCIF6_Pos (21U) 1450 #define DMA_IFCR_CTCIF6_Msk (0x1U << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */ 1451 #define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */ 1452 #define DMA_IFCR_CHTIF6_Pos (22U) 1453 #define DMA_IFCR_CHTIF6_Msk (0x1U << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */ 1454 #define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */ 1455 #define DMA_IFCR_CTEIF6_Pos (23U) 1456 #define DMA_IFCR_CTEIF6_Msk (0x1U << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */ 1457 #define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */ 1458 #define DMA_IFCR_CGIF7_Pos (24U) 1459 #define DMA_IFCR_CGIF7_Msk (0x1U << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */ 1460 #define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */ 1461 #define DMA_IFCR_CTCIF7_Pos (25U) 1462 #define DMA_IFCR_CTCIF7_Msk (0x1U << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */ 1463 #define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */ 1464 #define DMA_IFCR_CHTIF7_Pos (26U) 1465 #define DMA_IFCR_CHTIF7_Msk (0x1U << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */ 1466 #define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */ 1467 #define DMA_IFCR_CTEIF7_Pos (27U) 1468 #define DMA_IFCR_CTEIF7_Msk (0x1U << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */ 1469 #define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */ 1470 1471 /******************* Bit definition for DMA_CCR register ********************/ 1472 #define DMA_CCR_EN_Pos (0U) 1473 #define DMA_CCR_EN_Msk (0x1U << DMA_CCR_EN_Pos) /*!< 0x00000001 */ 1474 #define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */ 1475 #define DMA_CCR_TCIE_Pos (1U) 1476 #define DMA_CCR_TCIE_Msk (0x1U << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */ 1477 #define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */ 1478 #define DMA_CCR_HTIE_Pos (2U) 1479 #define DMA_CCR_HTIE_Msk (0x1U << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */ 1480 #define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */ 1481 #define DMA_CCR_TEIE_Pos (3U) 1482 #define DMA_CCR_TEIE_Msk (0x1U << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */ 1483 #define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */ 1484 #define DMA_CCR_DIR_Pos (4U) 1485 #define DMA_CCR_DIR_Msk (0x1U << DMA_CCR_DIR_Pos) /*!< 0x00000010 */ 1486 #define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */ 1487 #define DMA_CCR_CIRC_Pos (5U) 1488 #define DMA_CCR_CIRC_Msk (0x1U << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */ 1489 #define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */ 1490 #define DMA_CCR_PINC_Pos (6U) 1491 #define DMA_CCR_PINC_Msk (0x1U << DMA_CCR_PINC_Pos) /*!< 0x00000040 */ 1492 #define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */ 1493 #define DMA_CCR_MINC_Pos (7U) 1494 #define DMA_CCR_MINC_Msk (0x1U << DMA_CCR_MINC_Pos) /*!< 0x00000080 */ 1495 #define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */ 1496 1497 #define DMA_CCR_PSIZE_Pos (8U) 1498 #define DMA_CCR_PSIZE_Msk (0x3U << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */ 1499 #define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */ 1500 #define DMA_CCR_PSIZE_0 (0x1U << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */ 1501 #define DMA_CCR_PSIZE_1 (0x2U << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */ 1502 1503 #define DMA_CCR_MSIZE_Pos (10U) 1504 #define DMA_CCR_MSIZE_Msk (0x3U << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */ 1505 #define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */ 1506 #define DMA_CCR_MSIZE_0 (0x1U << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */ 1507 #define DMA_CCR_MSIZE_1 (0x2U << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */ 1508 1509 #define DMA_CCR_PL_Pos (12U) 1510 #define DMA_CCR_PL_Msk (0x3U << DMA_CCR_PL_Pos) /*!< 0x00003000 */ 1511 #define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level)*/ 1512 #define DMA_CCR_PL_0 (0x1U << DMA_CCR_PL_Pos) /*!< 0x00001000 */ 1513 #define DMA_CCR_PL_1 (0x2U << DMA_CCR_PL_Pos) /*!< 0x00002000 */ 1514 1515 #define DMA_CCR_MEM2MEM_Pos (14U) 1516 #define DMA_CCR_MEM2MEM_Msk (0x1U << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */ 1517 #define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */ 1518 1519 /****************** Bit definition for DMA_CNDTR register *******************/ 1520 #define DMA_CNDTR_NDT_Pos (0U) 1521 #define DMA_CNDTR_NDT_Msk (0xFFFFU << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */ 1522 #define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */ 1523 1524 /****************** Bit definition for DMA_CPAR register ********************/ 1525 #define DMA_CPAR_PA_Pos (0U) 1526 #define DMA_CPAR_PA_Msk (0xFFFFFFFFU << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */ 1527 #define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */ 1528 1529 /****************** Bit definition for DMA_CMAR register ********************/ 1530 #define DMA_CMAR_MA_Pos (0U) 1531 #define DMA_CMAR_MA_Msk (0xFFFFFFFFU << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */ 1532 #define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */ 1533 1534 1535 /******************* Bit definition for DMA_CSELR register *******************/ 1536 #define DMA_CSELR_C1S_Pos (0U) 1537 #define DMA_CSELR_C1S_Msk (0xFU << DMA_CSELR_C1S_Pos) /*!< 0x0000000F */ 1538 #define DMA_CSELR_C1S DMA_CSELR_C1S_Msk /*!< Channel 1 Selection */ 1539 #define DMA_CSELR_C2S_Pos (4U) 1540 #define DMA_CSELR_C2S_Msk (0xFU << DMA_CSELR_C2S_Pos) /*!< 0x000000F0 */ 1541 #define DMA_CSELR_C2S DMA_CSELR_C2S_Msk /*!< Channel 2 Selection */ 1542 #define DMA_CSELR_C3S_Pos (8U) 1543 #define DMA_CSELR_C3S_Msk (0xFU << DMA_CSELR_C3S_Pos) /*!< 0x00000F00 */ 1544 #define DMA_CSELR_C3S DMA_CSELR_C3S_Msk /*!< Channel 3 Selection */ 1545 #define DMA_CSELR_C4S_Pos (12U) 1546 #define DMA_CSELR_C4S_Msk (0xFU << DMA_CSELR_C4S_Pos) /*!< 0x0000F000 */ 1547 #define DMA_CSELR_C4S DMA_CSELR_C4S_Msk /*!< Channel 4 Selection */ 1548 #define DMA_CSELR_C5S_Pos (16U) 1549 #define DMA_CSELR_C5S_Msk (0xFU << DMA_CSELR_C5S_Pos) /*!< 0x000F0000 */ 1550 #define DMA_CSELR_C5S DMA_CSELR_C5S_Msk /*!< Channel 5 Selection */ 1551 #define DMA_CSELR_C6S_Pos (20U) 1552 #define DMA_CSELR_C6S_Msk (0xFU << DMA_CSELR_C6S_Pos) /*!< 0x00F00000 */ 1553 #define DMA_CSELR_C6S DMA_CSELR_C6S_Msk /*!< Channel 6 Selection */ 1554 #define DMA_CSELR_C7S_Pos (24U) 1555 #define DMA_CSELR_C7S_Msk (0xFU << DMA_CSELR_C7S_Pos) /*!< 0x0F000000 */ 1556 #define DMA_CSELR_C7S DMA_CSELR_C7S_Msk /*!< Channel 7 Selection */ 1557 1558 /******************************************************************************/ 1559 /* */ 1560 /* External Interrupt/Event Controller (EXTI) */ 1561 /* */ 1562 /******************************************************************************/ 1563 1564 /******************* Bit definition for EXTI_IMR register *******************/ 1565 #define EXTI_IMR_IM0_Pos (0U) 1566 #define EXTI_IMR_IM0_Msk (0x1U << EXTI_IMR_IM0_Pos) /*!< 0x00000001 */ 1567 #define EXTI_IMR_IM0 EXTI_IMR_IM0_Msk /*!< Interrupt Mask on line 0 */ 1568 #define EXTI_IMR_IM1_Pos (1U) 1569 #define EXTI_IMR_IM1_Msk (0x1U << EXTI_IMR_IM1_Pos) /*!< 0x00000002 */ 1570 #define EXTI_IMR_IM1 EXTI_IMR_IM1_Msk /*!< Interrupt Mask on line 1 */ 1571 #define EXTI_IMR_IM2_Pos (2U) 1572 #define EXTI_IMR_IM2_Msk (0x1U << EXTI_IMR_IM2_Pos) /*!< 0x00000004 */ 1573 #define EXTI_IMR_IM2 EXTI_IMR_IM2_Msk /*!< Interrupt Mask on line 2 */ 1574 #define EXTI_IMR_IM3_Pos (3U) 1575 #define EXTI_IMR_IM3_Msk (0x1U << EXTI_IMR_IM3_Pos) /*!< 0x00000008 */ 1576 #define EXTI_IMR_IM3 EXTI_IMR_IM3_Msk /*!< Interrupt Mask on line 3 */ 1577 #define EXTI_IMR_IM4_Pos (4U) 1578 #define EXTI_IMR_IM4_Msk (0x1U << EXTI_IMR_IM4_Pos) /*!< 0x00000010 */ 1579 #define EXTI_IMR_IM4 EXTI_IMR_IM4_Msk /*!< Interrupt Mask on line 4 */ 1580 #define EXTI_IMR_IM5_Pos (5U) 1581 #define EXTI_IMR_IM5_Msk (0x1U << EXTI_IMR_IM5_Pos) /*!< 0x00000020 */ 1582 #define EXTI_IMR_IM5 EXTI_IMR_IM5_Msk /*!< Interrupt Mask on line 5 */ 1583 #define EXTI_IMR_IM6_Pos (6U) 1584 #define EXTI_IMR_IM6_Msk (0x1U << EXTI_IMR_IM6_Pos) /*!< 0x00000040 */ 1585 #define EXTI_IMR_IM6 EXTI_IMR_IM6_Msk /*!< Interrupt Mask on line 6 */ 1586 #define EXTI_IMR_IM7_Pos (7U) 1587 #define EXTI_IMR_IM7_Msk (0x1U << EXTI_IMR_IM7_Pos) /*!< 0x00000080 */ 1588 #define EXTI_IMR_IM7 EXTI_IMR_IM7_Msk /*!< Interrupt Mask on line 7 */ 1589 #define EXTI_IMR_IM8_Pos (8U) 1590 #define EXTI_IMR_IM8_Msk (0x1U << EXTI_IMR_IM8_Pos) /*!< 0x00000100 */ 1591 #define EXTI_IMR_IM8 EXTI_IMR_IM8_Msk /*!< Interrupt Mask on line 8 */ 1592 #define EXTI_IMR_IM9_Pos (9U) 1593 #define EXTI_IMR_IM9_Msk (0x1U << EXTI_IMR_IM9_Pos) /*!< 0x00000200 */ 1594 #define EXTI_IMR_IM9 EXTI_IMR_IM9_Msk /*!< Interrupt Mask on line 9 */ 1595 #define EXTI_IMR_IM10_Pos (10U) 1596 #define EXTI_IMR_IM10_Msk (0x1U << EXTI_IMR_IM10_Pos) /*!< 0x00000400 */ 1597 #define EXTI_IMR_IM10 EXTI_IMR_IM10_Msk /*!< Interrupt Mask on line 10 */ 1598 #define EXTI_IMR_IM11_Pos (11U) 1599 #define EXTI_IMR_IM11_Msk (0x1U << EXTI_IMR_IM11_Pos) /*!< 0x00000800 */ 1600 #define EXTI_IMR_IM11 EXTI_IMR_IM11_Msk /*!< Interrupt Mask on line 11 */ 1601 #define EXTI_IMR_IM12_Pos (12U) 1602 #define EXTI_IMR_IM12_Msk (0x1U << EXTI_IMR_IM12_Pos) /*!< 0x00001000 */ 1603 #define EXTI_IMR_IM12 EXTI_IMR_IM12_Msk /*!< Interrupt Mask on line 12 */ 1604 #define EXTI_IMR_IM13_Pos (13U) 1605 #define EXTI_IMR_IM13_Msk (0x1U << EXTI_IMR_IM13_Pos) /*!< 0x00002000 */ 1606 #define EXTI_IMR_IM13 EXTI_IMR_IM13_Msk /*!< Interrupt Mask on line 13 */ 1607 #define EXTI_IMR_IM14_Pos (14U) 1608 #define EXTI_IMR_IM14_Msk (0x1U << EXTI_IMR_IM14_Pos) /*!< 0x00004000 */ 1609 #define EXTI_IMR_IM14 EXTI_IMR_IM14_Msk /*!< Interrupt Mask on line 14 */ 1610 #define EXTI_IMR_IM15_Pos (15U) 1611 #define EXTI_IMR_IM15_Msk (0x1U << EXTI_IMR_IM15_Pos) /*!< 0x00008000 */ 1612 #define EXTI_IMR_IM15 EXTI_IMR_IM15_Msk /*!< Interrupt Mask on line 15 */ 1613 #define EXTI_IMR_IM16_Pos (16U) 1614 #define EXTI_IMR_IM16_Msk (0x1U << EXTI_IMR_IM16_Pos) /*!< 0x00010000 */ 1615 #define EXTI_IMR_IM16 EXTI_IMR_IM16_Msk /*!< Interrupt Mask on line 16 */ 1616 #define EXTI_IMR_IM17_Pos (17U) 1617 #define EXTI_IMR_IM17_Msk (0x1U << EXTI_IMR_IM17_Pos) /*!< 0x00020000 */ 1618 #define EXTI_IMR_IM17 EXTI_IMR_IM17_Msk /*!< Interrupt Mask on line 17 */ 1619 #define EXTI_IMR_IM18_Pos (18U) 1620 #define EXTI_IMR_IM18_Msk (0x1U << EXTI_IMR_IM18_Pos) /*!< 0x00040000 */ 1621 #define EXTI_IMR_IM18 EXTI_IMR_IM18_Msk /*!< Interrupt Mask on line 18 */ 1622 #define EXTI_IMR_IM19_Pos (19U) 1623 #define EXTI_IMR_IM19_Msk (0x1U << EXTI_IMR_IM19_Pos) /*!< 0x00080000 */ 1624 #define EXTI_IMR_IM19 EXTI_IMR_IM19_Msk /*!< Interrupt Mask on line 19 */ 1625 #define EXTI_IMR_IM20_Pos (20U) 1626 #define EXTI_IMR_IM20_Msk (0x1U << EXTI_IMR_IM20_Pos) /*!< 0x00100000 */ 1627 #define EXTI_IMR_IM20 EXTI_IMR_IM20_Msk /*!< Interrupt Mask on line 20 */ 1628 #define EXTI_IMR_IM21_Pos (21U) 1629 #define EXTI_IMR_IM21_Msk (0x1U << EXTI_IMR_IM21_Pos) /*!< 0x00200000 */ 1630 #define EXTI_IMR_IM21 EXTI_IMR_IM21_Msk /*!< Interrupt Mask on line 21 */ 1631 #define EXTI_IMR_IM22_Pos (22U) 1632 #define EXTI_IMR_IM22_Msk (0x1U << EXTI_IMR_IM22_Pos) /*!< 0x00400000 */ 1633 #define EXTI_IMR_IM22 EXTI_IMR_IM22_Msk /*!< Interrupt Mask on line 22 */ 1634 #define EXTI_IMR_IM23_Pos (23U) 1635 #define EXTI_IMR_IM23_Msk (0x1U << EXTI_IMR_IM23_Pos) /*!< 0x00800000 */ 1636 #define EXTI_IMR_IM23 EXTI_IMR_IM23_Msk /*!< Interrupt Mask on line 23 */ 1637 #define EXTI_IMR_IM24_Pos (24U) 1638 #define EXTI_IMR_IM24_Msk (0x1U << EXTI_IMR_IM24_Pos) /*!< 0x01000000 */ 1639 #define EXTI_IMR_IM24 EXTI_IMR_IM24_Msk /*!< Interrupt Mask on line 24 */ 1640 #define EXTI_IMR_IM25_Pos (25U) 1641 #define EXTI_IMR_IM25_Msk (0x1U << EXTI_IMR_IM25_Pos) /*!< 0x02000000 */ 1642 #define EXTI_IMR_IM25 EXTI_IMR_IM25_Msk /*!< Interrupt Mask on line 25 */ 1643 #define EXTI_IMR_IM26_Pos (26U) 1644 #define EXTI_IMR_IM26_Msk (0x1U << EXTI_IMR_IM26_Pos) /*!< 0x04000000 */ 1645 #define EXTI_IMR_IM26 EXTI_IMR_IM26_Msk /*!< Interrupt Mask on line 26 */ 1646 #define EXTI_IMR_IM28_Pos (28U) 1647 #define EXTI_IMR_IM28_Msk (0x1U << EXTI_IMR_IM28_Pos) /*!< 0x10000000 */ 1648 #define EXTI_IMR_IM28 EXTI_IMR_IM28_Msk /*!< Interrupt Mask on line 28 */ 1649 #define EXTI_IMR_IM29_Pos (29U) 1650 #define EXTI_IMR_IM29_Msk (0x1U << EXTI_IMR_IM29_Pos) /*!< 0x20000000 */ 1651 #define EXTI_IMR_IM29 EXTI_IMR_IM29_Msk /*!< Interrupt Mask on line 29 */ 1652 1653 #define EXTI_IMR_IM_Pos (0U) 1654 #define EXTI_IMR_IM_Msk (0x37FFFFFFU << EXTI_IMR_IM_Pos) /*!< 0x37FFFFFF */ 1655 #define EXTI_IMR_IM EXTI_IMR_IM_Msk /*!< Interrupt Mask All */ 1656 1657 /****************** Bit definition for EXTI_EMR register ********************/ 1658 #define EXTI_EMR_EM0_Pos (0U) 1659 #define EXTI_EMR_EM0_Msk (0x1U << EXTI_EMR_EM0_Pos) /*!< 0x00000001 */ 1660 #define EXTI_EMR_EM0 EXTI_EMR_EM0_Msk /*!< Event Mask on line 0 */ 1661 #define EXTI_EMR_EM1_Pos (1U) 1662 #define EXTI_EMR_EM1_Msk (0x1U << EXTI_EMR_EM1_Pos) /*!< 0x00000002 */ 1663 #define EXTI_EMR_EM1 EXTI_EMR_EM1_Msk /*!< Event Mask on line 1 */ 1664 #define EXTI_EMR_EM2_Pos (2U) 1665 #define EXTI_EMR_EM2_Msk (0x1U << EXTI_EMR_EM2_Pos) /*!< 0x00000004 */ 1666 #define EXTI_EMR_EM2 EXTI_EMR_EM2_Msk /*!< Event Mask on line 2 */ 1667 #define EXTI_EMR_EM3_Pos (3U) 1668 #define EXTI_EMR_EM3_Msk (0x1U << EXTI_EMR_EM3_Pos) /*!< 0x00000008 */ 1669 #define EXTI_EMR_EM3 EXTI_EMR_EM3_Msk /*!< Event Mask on line 3 */ 1670 #define EXTI_EMR_EM4_Pos (4U) 1671 #define EXTI_EMR_EM4_Msk (0x1U << EXTI_EMR_EM4_Pos) /*!< 0x00000010 */ 1672 #define EXTI_EMR_EM4 EXTI_EMR_EM4_Msk /*!< Event Mask on line 4 */ 1673 #define EXTI_EMR_EM5_Pos (5U) 1674 #define EXTI_EMR_EM5_Msk (0x1U << EXTI_EMR_EM5_Pos) /*!< 0x00000020 */ 1675 #define EXTI_EMR_EM5 EXTI_EMR_EM5_Msk /*!< Event Mask on line 5 */ 1676 #define EXTI_EMR_EM6_Pos (6U) 1677 #define EXTI_EMR_EM6_Msk (0x1U << EXTI_EMR_EM6_Pos) /*!< 0x00000040 */ 1678 #define EXTI_EMR_EM6 EXTI_EMR_EM6_Msk /*!< Event Mask on line 6 */ 1679 #define EXTI_EMR_EM7_Pos (7U) 1680 #define EXTI_EMR_EM7_Msk (0x1U << EXTI_EMR_EM7_Pos) /*!< 0x00000080 */ 1681 #define EXTI_EMR_EM7 EXTI_EMR_EM7_Msk /*!< Event Mask on line 7 */ 1682 #define EXTI_EMR_EM8_Pos (8U) 1683 #define EXTI_EMR_EM8_Msk (0x1U << EXTI_EMR_EM8_Pos) /*!< 0x00000100 */ 1684 #define EXTI_EMR_EM8 EXTI_EMR_EM8_Msk /*!< Event Mask on line 8 */ 1685 #define EXTI_EMR_EM9_Pos (9U) 1686 #define EXTI_EMR_EM9_Msk (0x1U << EXTI_EMR_EM9_Pos) /*!< 0x00000200 */ 1687 #define EXTI_EMR_EM9 EXTI_EMR_EM9_Msk /*!< Event Mask on line 9 */ 1688 #define EXTI_EMR_EM10_Pos (10U) 1689 #define EXTI_EMR_EM10_Msk (0x1U << EXTI_EMR_EM10_Pos) /*!< 0x00000400 */ 1690 #define EXTI_EMR_EM10 EXTI_EMR_EM10_Msk /*!< Event Mask on line 10 */ 1691 #define EXTI_EMR_EM11_Pos (11U) 1692 #define EXTI_EMR_EM11_Msk (0x1U << EXTI_EMR_EM11_Pos) /*!< 0x00000800 */ 1693 #define EXTI_EMR_EM11 EXTI_EMR_EM11_Msk /*!< Event Mask on line 11 */ 1694 #define EXTI_EMR_EM12_Pos (12U) 1695 #define EXTI_EMR_EM12_Msk (0x1U << EXTI_EMR_EM12_Pos) /*!< 0x00001000 */ 1696 #define EXTI_EMR_EM12 EXTI_EMR_EM12_Msk /*!< Event Mask on line 12 */ 1697 #define EXTI_EMR_EM13_Pos (13U) 1698 #define EXTI_EMR_EM13_Msk (0x1U << EXTI_EMR_EM13_Pos) /*!< 0x00002000 */ 1699 #define EXTI_EMR_EM13 EXTI_EMR_EM13_Msk /*!< Event Mask on line 13 */ 1700 #define EXTI_EMR_EM14_Pos (14U) 1701 #define EXTI_EMR_EM14_Msk (0x1U << EXTI_EMR_EM14_Pos) /*!< 0x00004000 */ 1702 #define EXTI_EMR_EM14 EXTI_EMR_EM14_Msk /*!< Event Mask on line 14 */ 1703 #define EXTI_EMR_EM15_Pos (15U) 1704 #define EXTI_EMR_EM15_Msk (0x1U << EXTI_EMR_EM15_Pos) /*!< 0x00008000 */ 1705 #define EXTI_EMR_EM15 EXTI_EMR_EM15_Msk /*!< Event Mask on line 15 */ 1706 #define EXTI_EMR_EM16_Pos (16U) 1707 #define EXTI_EMR_EM16_Msk (0x1U << EXTI_EMR_EM16_Pos) /*!< 0x00010000 */ 1708 #define EXTI_EMR_EM16 EXTI_EMR_EM16_Msk /*!< Event Mask on line 16 */ 1709 #define EXTI_EMR_EM17_Pos (17U) 1710 #define EXTI_EMR_EM17_Msk (0x1U << EXTI_EMR_EM17_Pos) /*!< 0x00020000 */ 1711 #define EXTI_EMR_EM17 EXTI_EMR_EM17_Msk /*!< Event Mask on line 17 */ 1712 #define EXTI_EMR_EM18_Pos (18U) 1713 #define EXTI_EMR_EM18_Msk (0x1U << EXTI_EMR_EM18_Pos) /*!< 0x00040000 */ 1714 #define EXTI_EMR_EM18 EXTI_EMR_EM18_Msk /*!< Event Mask on line 18 */ 1715 #define EXTI_EMR_EM19_Pos (19U) 1716 #define EXTI_EMR_EM19_Msk (0x1U << EXTI_EMR_EM19_Pos) /*!< 0x00080000 */ 1717 #define EXTI_EMR_EM19 EXTI_EMR_EM19_Msk /*!< Event Mask on line 19 */ 1718 #define EXTI_EMR_EM20_Pos (20U) 1719 #define EXTI_EMR_EM20_Msk (0x1U << EXTI_EMR_EM20_Pos) /*!< 0x00100000 */ 1720 #define EXTI_EMR_EM20 EXTI_EMR_EM20_Msk /*!< Event Mask on line 20 */ 1721 #define EXTI_EMR_EM21_Pos (21U) 1722 #define EXTI_EMR_EM21_Msk (0x1U << EXTI_EMR_EM21_Pos) /*!< 0x00200000 */ 1723 #define EXTI_EMR_EM21 EXTI_EMR_EM21_Msk /*!< Event Mask on line 21 */ 1724 #define EXTI_EMR_EM22_Pos (22U) 1725 #define EXTI_EMR_EM22_Msk (0x1U << EXTI_EMR_EM22_Pos) /*!< 0x00400000 */ 1726 #define EXTI_EMR_EM22 EXTI_EMR_EM22_Msk /*!< Event Mask on line 22 */ 1727 #define EXTI_EMR_EM23_Pos (23U) 1728 #define EXTI_EMR_EM23_Msk (0x1U << EXTI_EMR_EM23_Pos) /*!< 0x00800000 */ 1729 #define EXTI_EMR_EM23 EXTI_EMR_EM23_Msk /*!< Event Mask on line 23 */ 1730 #define EXTI_EMR_EM24_Pos (24U) 1731 #define EXTI_EMR_EM24_Msk (0x1U << EXTI_EMR_EM24_Pos) /*!< 0x01000000 */ 1732 #define EXTI_EMR_EM24 EXTI_EMR_EM24_Msk /*!< Event Mask on line 24 */ 1733 #define EXTI_EMR_EM25_Pos (25U) 1734 #define EXTI_EMR_EM25_Msk (0x1U << EXTI_EMR_EM25_Pos) /*!< 0x02000000 */ 1735 #define EXTI_EMR_EM25 EXTI_EMR_EM25_Msk /*!< Event Mask on line 25 */ 1736 #define EXTI_EMR_EM26_Pos (26U) 1737 #define EXTI_EMR_EM26_Msk (0x1U << EXTI_EMR_EM26_Pos) /*!< 0x04000000 */ 1738 #define EXTI_EMR_EM26 EXTI_EMR_EM26_Msk /*!< Event Mask on line 26 */ 1739 #define EXTI_EMR_EM28_Pos (28U) 1740 #define EXTI_EMR_EM28_Msk (0x1U << EXTI_EMR_EM28_Pos) /*!< 0x10000000 */ 1741 #define EXTI_EMR_EM28 EXTI_EMR_EM28_Msk /*!< Event Mask on line 28 */ 1742 #define EXTI_EMR_EM29_Pos (29U) 1743 #define EXTI_EMR_EM29_Msk (0x1U << EXTI_EMR_EM29_Pos) /*!< 0x20000000 */ 1744 #define EXTI_EMR_EM29 EXTI_EMR_EM29_Msk /*!< Event Mask on line 29 */ 1745 1746 /******************* Bit definition for EXTI_RTSR register ******************/ 1747 #define EXTI_RTSR_RT0_Pos (0U) 1748 #define EXTI_RTSR_RT0_Msk (0x1U << EXTI_RTSR_RT0_Pos) /*!< 0x00000001 */ 1749 #define EXTI_RTSR_RT0 EXTI_RTSR_RT0_Msk /*!< Rising trigger event configuration bit of line 0 */ 1750 #define EXTI_RTSR_RT1_Pos (1U) 1751 #define EXTI_RTSR_RT1_Msk (0x1U << EXTI_RTSR_RT1_Pos) /*!< 0x00000002 */ 1752 #define EXTI_RTSR_RT1 EXTI_RTSR_RT1_Msk /*!< Rising trigger event configuration bit of line 1 */ 1753 #define EXTI_RTSR_RT2_Pos (2U) 1754 #define EXTI_RTSR_RT2_Msk (0x1U << EXTI_RTSR_RT2_Pos) /*!< 0x00000004 */ 1755 #define EXTI_RTSR_RT2 EXTI_RTSR_RT2_Msk /*!< Rising trigger event configuration bit of line 2 */ 1756 #define EXTI_RTSR_RT3_Pos (3U) 1757 #define EXTI_RTSR_RT3_Msk (0x1U << EXTI_RTSR_RT3_Pos) /*!< 0x00000008 */ 1758 #define EXTI_RTSR_RT3 EXTI_RTSR_RT3_Msk /*!< Rising trigger event configuration bit of line 3 */ 1759 #define EXTI_RTSR_RT4_Pos (4U) 1760 #define EXTI_RTSR_RT4_Msk (0x1U << EXTI_RTSR_RT4_Pos) /*!< 0x00000010 */ 1761 #define EXTI_RTSR_RT4 EXTI_RTSR_RT4_Msk /*!< Rising trigger event configuration bit of line 4 */ 1762 #define EXTI_RTSR_RT5_Pos (5U) 1763 #define EXTI_RTSR_RT5_Msk (0x1U << EXTI_RTSR_RT5_Pos) /*!< 0x00000020 */ 1764 #define EXTI_RTSR_RT5 EXTI_RTSR_RT5_Msk /*!< Rising trigger event configuration bit of line 5 */ 1765 #define EXTI_RTSR_RT6_Pos (6U) 1766 #define EXTI_RTSR_RT6_Msk (0x1U << EXTI_RTSR_RT6_Pos) /*!< 0x00000040 */ 1767 #define EXTI_RTSR_RT6 EXTI_RTSR_RT6_Msk /*!< Rising trigger event configuration bit of line 6 */ 1768 #define EXTI_RTSR_RT7_Pos (7U) 1769 #define EXTI_RTSR_RT7_Msk (0x1U << EXTI_RTSR_RT7_Pos) /*!< 0x00000080 */ 1770 #define EXTI_RTSR_RT7 EXTI_RTSR_RT7_Msk /*!< Rising trigger event configuration bit of line 7 */ 1771 #define EXTI_RTSR_RT8_Pos (8U) 1772 #define EXTI_RTSR_RT8_Msk (0x1U << EXTI_RTSR_RT8_Pos) /*!< 0x00000100 */ 1773 #define EXTI_RTSR_RT8 EXTI_RTSR_RT8_Msk /*!< Rising trigger event configuration bit of line 8 */ 1774 #define EXTI_RTSR_RT9_Pos (9U) 1775 #define EXTI_RTSR_RT9_Msk (0x1U << EXTI_RTSR_RT9_Pos) /*!< 0x00000200 */ 1776 #define EXTI_RTSR_RT9 EXTI_RTSR_RT9_Msk /*!< Rising trigger event configuration bit of line 9 */ 1777 #define EXTI_RTSR_RT10_Pos (10U) 1778 #define EXTI_RTSR_RT10_Msk (0x1U << EXTI_RTSR_RT10_Pos) /*!< 0x00000400 */ 1779 #define EXTI_RTSR_RT10 EXTI_RTSR_RT10_Msk /*!< Rising trigger event configuration bit of line 10 */ 1780 #define EXTI_RTSR_RT11_Pos (11U) 1781 #define EXTI_RTSR_RT11_Msk (0x1U << EXTI_RTSR_RT11_Pos) /*!< 0x00000800 */ 1782 #define EXTI_RTSR_RT11 EXTI_RTSR_RT11_Msk /*!< Rising trigger event configuration bit of line 11 */ 1783 #define EXTI_RTSR_RT12_Pos (12U) 1784 #define EXTI_RTSR_RT12_Msk (0x1U << EXTI_RTSR_RT12_Pos) /*!< 0x00001000 */ 1785 #define EXTI_RTSR_RT12 EXTI_RTSR_RT12_Msk /*!< Rising trigger event configuration bit of line 12 */ 1786 #define EXTI_RTSR_RT13_Pos (13U) 1787 #define EXTI_RTSR_RT13_Msk (0x1U << EXTI_RTSR_RT13_Pos) /*!< 0x00002000 */ 1788 #define EXTI_RTSR_RT13 EXTI_RTSR_RT13_Msk /*!< Rising trigger event configuration bit of line 13 */ 1789 #define EXTI_RTSR_RT14_Pos (14U) 1790 #define EXTI_RTSR_RT14_Msk (0x1U << EXTI_RTSR_RT14_Pos) /*!< 0x00004000 */ 1791 #define EXTI_RTSR_RT14 EXTI_RTSR_RT14_Msk /*!< Rising trigger event configuration bit of line 14 */ 1792 #define EXTI_RTSR_RT15_Pos (15U) 1793 #define EXTI_RTSR_RT15_Msk (0x1U << EXTI_RTSR_RT15_Pos) /*!< 0x00008000 */ 1794 #define EXTI_RTSR_RT15 EXTI_RTSR_RT15_Msk /*!< Rising trigger event configuration bit of line 15 */ 1795 #define EXTI_RTSR_RT16_Pos (16U) 1796 #define EXTI_RTSR_RT16_Msk (0x1U << EXTI_RTSR_RT16_Pos) /*!< 0x00010000 */ 1797 #define EXTI_RTSR_RT16 EXTI_RTSR_RT16_Msk /*!< Rising trigger event configuration bit of line 16 */ 1798 #define EXTI_RTSR_RT17_Pos (17U) 1799 #define EXTI_RTSR_RT17_Msk (0x1U << EXTI_RTSR_RT17_Pos) /*!< 0x00020000 */ 1800 #define EXTI_RTSR_RT17 EXTI_RTSR_RT17_Msk /*!< Rising trigger event configuration bit of line 17 */ 1801 #define EXTI_RTSR_RT19_Pos (19U) 1802 #define EXTI_RTSR_RT19_Msk (0x1U << EXTI_RTSR_RT19_Pos) /*!< 0x00080000 */ 1803 #define EXTI_RTSR_RT19 EXTI_RTSR_RT19_Msk /*!< Rising trigger event configuration bit of line 19 */ 1804 #define EXTI_RTSR_RT20_Pos (20U) 1805 #define EXTI_RTSR_RT20_Msk (0x1U << EXTI_RTSR_RT20_Pos) /*!< 0x00100000 */ 1806 #define EXTI_RTSR_RT20 EXTI_RTSR_RT20_Msk /*!< Rising trigger event configuration bit of line 20 */ 1807 #define EXTI_RTSR_RT21_Pos (21U) 1808 #define EXTI_RTSR_RT21_Msk (0x1U << EXTI_RTSR_RT21_Pos) /*!< 0x00200000 */ 1809 #define EXTI_RTSR_RT21 EXTI_RTSR_RT21_Msk /*!< Rising trigger event configuration bit of line 21 */ 1810 #define EXTI_RTSR_RT22_Pos (22U) 1811 #define EXTI_RTSR_RT22_Msk (0x1U << EXTI_RTSR_RT22_Pos) /*!< 0x00400000 */ 1812 #define EXTI_RTSR_RT22 EXTI_RTSR_RT22_Msk /*!< Rising trigger event configuration bit of line 22 */ 1813 1814 /* Legacy defines */ 1815 #define EXTI_RTSR_TR0 EXTI_RTSR_RT0 1816 #define EXTI_RTSR_TR1 EXTI_RTSR_RT1 1817 #define EXTI_RTSR_TR2 EXTI_RTSR_RT2 1818 #define EXTI_RTSR_TR3 EXTI_RTSR_RT3 1819 #define EXTI_RTSR_TR4 EXTI_RTSR_RT4 1820 #define EXTI_RTSR_TR5 EXTI_RTSR_RT5 1821 #define EXTI_RTSR_TR6 EXTI_RTSR_RT6 1822 #define EXTI_RTSR_TR7 EXTI_RTSR_RT7 1823 #define EXTI_RTSR_TR8 EXTI_RTSR_RT8 1824 #define EXTI_RTSR_TR9 EXTI_RTSR_RT9 1825 #define EXTI_RTSR_TR10 EXTI_RTSR_RT10 1826 #define EXTI_RTSR_TR11 EXTI_RTSR_RT11 1827 #define EXTI_RTSR_TR12 EXTI_RTSR_RT12 1828 #define EXTI_RTSR_TR13 EXTI_RTSR_RT13 1829 #define EXTI_RTSR_TR14 EXTI_RTSR_RT14 1830 #define EXTI_RTSR_TR15 EXTI_RTSR_RT15 1831 #define EXTI_RTSR_TR16 EXTI_RTSR_RT16 1832 #define EXTI_RTSR_TR17 EXTI_RTSR_RT17 1833 #define EXTI_RTSR_TR19 EXTI_RTSR_RT19 1834 #define EXTI_RTSR_TR20 EXTI_RTSR_RT20 1835 #define EXTI_RTSR_TR21 EXTI_RTSR_RT21 1836 #define EXTI_RTSR_TR22 EXTI_RTSR_RT22 1837 1838 /******************* Bit definition for EXTI_FTSR register *******************/ 1839 #define EXTI_FTSR_FT0_Pos (0U) 1840 #define EXTI_FTSR_FT0_Msk (0x1U << EXTI_FTSR_FT0_Pos) /*!< 0x00000001 */ 1841 #define EXTI_FTSR_FT0 EXTI_FTSR_FT0_Msk /*!< Falling trigger event configuration bit of line 0 */ 1842 #define EXTI_FTSR_FT1_Pos (1U) 1843 #define EXTI_FTSR_FT1_Msk (0x1U << EXTI_FTSR_FT1_Pos) /*!< 0x00000002 */ 1844 #define EXTI_FTSR_FT1 EXTI_FTSR_FT1_Msk /*!< Falling trigger event configuration bit of line 1 */ 1845 #define EXTI_FTSR_FT2_Pos (2U) 1846 #define EXTI_FTSR_FT2_Msk (0x1U << EXTI_FTSR_FT2_Pos) /*!< 0x00000004 */ 1847 #define EXTI_FTSR_FT2 EXTI_FTSR_FT2_Msk /*!< Falling trigger event configuration bit of line 2 */ 1848 #define EXTI_FTSR_FT3_Pos (3U) 1849 #define EXTI_FTSR_FT3_Msk (0x1U << EXTI_FTSR_FT3_Pos) /*!< 0x00000008 */ 1850 #define EXTI_FTSR_FT3 EXTI_FTSR_FT3_Msk /*!< Falling trigger event configuration bit of line 3 */ 1851 #define EXTI_FTSR_FT4_Pos (4U) 1852 #define EXTI_FTSR_FT4_Msk (0x1U << EXTI_FTSR_FT4_Pos) /*!< 0x00000010 */ 1853 #define EXTI_FTSR_FT4 EXTI_FTSR_FT4_Msk /*!< Falling trigger event configuration bit of line 4 */ 1854 #define EXTI_FTSR_FT5_Pos (5U) 1855 #define EXTI_FTSR_FT5_Msk (0x1U << EXTI_FTSR_FT5_Pos) /*!< 0x00000020 */ 1856 #define EXTI_FTSR_FT5 EXTI_FTSR_FT5_Msk /*!< Falling trigger event configuration bit of line 5 */ 1857 #define EXTI_FTSR_FT6_Pos (6U) 1858 #define EXTI_FTSR_FT6_Msk (0x1U << EXTI_FTSR_FT6_Pos) /*!< 0x00000040 */ 1859 #define EXTI_FTSR_FT6 EXTI_FTSR_FT6_Msk /*!< Falling trigger event configuration bit of line 6 */ 1860 #define EXTI_FTSR_FT7_Pos (7U) 1861 #define EXTI_FTSR_FT7_Msk (0x1U << EXTI_FTSR_FT7_Pos) /*!< 0x00000080 */ 1862 #define EXTI_FTSR_FT7 EXTI_FTSR_FT7_Msk /*!< Falling trigger event configuration bit of line 7 */ 1863 #define EXTI_FTSR_FT8_Pos (8U) 1864 #define EXTI_FTSR_FT8_Msk (0x1U << EXTI_FTSR_FT8_Pos) /*!< 0x00000100 */ 1865 #define EXTI_FTSR_FT8 EXTI_FTSR_FT8_Msk /*!< Falling trigger event configuration bit of line 8 */ 1866 #define EXTI_FTSR_FT9_Pos (9U) 1867 #define EXTI_FTSR_FT9_Msk (0x1U << EXTI_FTSR_FT9_Pos) /*!< 0x00000200 */ 1868 #define EXTI_FTSR_FT9 EXTI_FTSR_FT9_Msk /*!< Falling trigger event configuration bit of line 9 */ 1869 #define EXTI_FTSR_FT10_Pos (10U) 1870 #define EXTI_FTSR_FT10_Msk (0x1U << EXTI_FTSR_FT10_Pos) /*!< 0x00000400 */ 1871 #define EXTI_FTSR_FT10 EXTI_FTSR_FT10_Msk /*!< Falling trigger event configuration bit of line 10 */ 1872 #define EXTI_FTSR_FT11_Pos (11U) 1873 #define EXTI_FTSR_FT11_Msk (0x1U << EXTI_FTSR_FT11_Pos) /*!< 0x00000800 */ 1874 #define EXTI_FTSR_FT11 EXTI_FTSR_FT11_Msk /*!< Falling trigger event configuration bit of line 11 */ 1875 #define EXTI_FTSR_FT12_Pos (12U) 1876 #define EXTI_FTSR_FT12_Msk (0x1U << EXTI_FTSR_FT12_Pos) /*!< 0x00001000 */ 1877 #define EXTI_FTSR_FT12 EXTI_FTSR_FT12_Msk /*!< Falling trigger event configuration bit of line 12 */ 1878 #define EXTI_FTSR_FT13_Pos (13U) 1879 #define EXTI_FTSR_FT13_Msk (0x1U << EXTI_FTSR_FT13_Pos) /*!< 0x00002000 */ 1880 #define EXTI_FTSR_FT13 EXTI_FTSR_FT13_Msk /*!< Falling trigger event configuration bit of line 13 */ 1881 #define EXTI_FTSR_FT14_Pos (14U) 1882 #define EXTI_FTSR_FT14_Msk (0x1U << EXTI_FTSR_FT14_Pos) /*!< 0x00004000 */ 1883 #define EXTI_FTSR_FT14 EXTI_FTSR_FT14_Msk /*!< Falling trigger event configuration bit of line 14 */ 1884 #define EXTI_FTSR_FT15_Pos (15U) 1885 #define EXTI_FTSR_FT15_Msk (0x1U << EXTI_FTSR_FT15_Pos) /*!< 0x00008000 */ 1886 #define EXTI_FTSR_FT15 EXTI_FTSR_FT15_Msk /*!< Falling trigger event configuration bit of line 15 */ 1887 #define EXTI_FTSR_FT16_Pos (16U) 1888 #define EXTI_FTSR_FT16_Msk (0x1U << EXTI_FTSR_FT16_Pos) /*!< 0x00010000 */ 1889 #define EXTI_FTSR_FT16 EXTI_FTSR_FT16_Msk /*!< Falling trigger event configuration bit of line 16 */ 1890 #define EXTI_FTSR_FT17_Pos (17U) 1891 #define EXTI_FTSR_FT17_Msk (0x1U << EXTI_FTSR_FT17_Pos) /*!< 0x00020000 */ 1892 #define EXTI_FTSR_FT17 EXTI_FTSR_FT17_Msk /*!< Falling trigger event configuration bit of line 17 */ 1893 #define EXTI_FTSR_FT19_Pos (19U) 1894 #define EXTI_FTSR_FT19_Msk (0x1U << EXTI_FTSR_FT19_Pos) /*!< 0x00080000 */ 1895 #define EXTI_FTSR_FT19 EXTI_FTSR_FT19_Msk /*!< Falling trigger event configuration bit of line 19 */ 1896 #define EXTI_FTSR_FT20_Pos (20U) 1897 #define EXTI_FTSR_FT20_Msk (0x1U << EXTI_FTSR_FT20_Pos) /*!< 0x00100000 */ 1898 #define EXTI_FTSR_FT20 EXTI_FTSR_FT20_Msk /*!< Falling trigger event configuration bit of line 20 */ 1899 #define EXTI_FTSR_FT21_Pos (21U) 1900 #define EXTI_FTSR_FT21_Msk (0x1U << EXTI_FTSR_FT21_Pos) /*!< 0x00200000 */ 1901 #define EXTI_FTSR_FT21 EXTI_FTSR_FT21_Msk /*!< Falling trigger event configuration bit of line 21 */ 1902 #define EXTI_FTSR_FT22_Pos (22U) 1903 #define EXTI_FTSR_FT22_Msk (0x1U << EXTI_FTSR_FT22_Pos) /*!< 0x00400000 */ 1904 #define EXTI_FTSR_FT22 EXTI_FTSR_FT22_Msk /*!< Falling trigger event configuration bit of line 22 */ 1905 1906 /* Legacy defines */ 1907 #define EXTI_FTSR_TR0 EXTI_FTSR_FT0 1908 #define EXTI_FTSR_TR1 EXTI_FTSR_FT1 1909 #define EXTI_FTSR_TR2 EXTI_FTSR_FT2 1910 #define EXTI_FTSR_TR3 EXTI_FTSR_FT3 1911 #define EXTI_FTSR_TR4 EXTI_FTSR_FT4 1912 #define EXTI_FTSR_TR5 EXTI_FTSR_FT5 1913 #define EXTI_FTSR_TR6 EXTI_FTSR_FT6 1914 #define EXTI_FTSR_TR7 EXTI_FTSR_FT7 1915 #define EXTI_FTSR_TR8 EXTI_FTSR_FT8 1916 #define EXTI_FTSR_TR9 EXTI_FTSR_FT9 1917 #define EXTI_FTSR_TR10 EXTI_FTSR_FT10 1918 #define EXTI_FTSR_TR11 EXTI_FTSR_FT11 1919 #define EXTI_FTSR_TR12 EXTI_FTSR_FT12 1920 #define EXTI_FTSR_TR13 EXTI_FTSR_FT13 1921 #define EXTI_FTSR_TR14 EXTI_FTSR_FT14 1922 #define EXTI_FTSR_TR15 EXTI_FTSR_FT15 1923 #define EXTI_FTSR_TR16 EXTI_FTSR_FT16 1924 #define EXTI_FTSR_TR17 EXTI_FTSR_FT17 1925 #define EXTI_FTSR_TR19 EXTI_FTSR_FT19 1926 #define EXTI_FTSR_TR20 EXTI_FTSR_FT20 1927 #define EXTI_FTSR_TR21 EXTI_FTSR_FT21 1928 #define EXTI_FTSR_TR22 EXTI_FTSR_FT22 1929 1930 /******************* Bit definition for EXTI_SWIER register *******************/ 1931 #define EXTI_SWIER_SWI0_Pos (0U) 1932 #define EXTI_SWIER_SWI0_Msk (0x1U << EXTI_SWIER_SWI0_Pos) /*!< 0x00000001 */ 1933 #define EXTI_SWIER_SWI0 EXTI_SWIER_SWI0_Msk /*!< Software Interrupt on line 0 */ 1934 #define EXTI_SWIER_SWI1_Pos (1U) 1935 #define EXTI_SWIER_SWI1_Msk (0x1U << EXTI_SWIER_SWI1_Pos) /*!< 0x00000002 */ 1936 #define EXTI_SWIER_SWI1 EXTI_SWIER_SWI1_Msk /*!< Software Interrupt on line 1 */ 1937 #define EXTI_SWIER_SWI2_Pos (2U) 1938 #define EXTI_SWIER_SWI2_Msk (0x1U << EXTI_SWIER_SWI2_Pos) /*!< 0x00000004 */ 1939 #define EXTI_SWIER_SWI2 EXTI_SWIER_SWI2_Msk /*!< Software Interrupt on line 2 */ 1940 #define EXTI_SWIER_SWI3_Pos (3U) 1941 #define EXTI_SWIER_SWI3_Msk (0x1U << EXTI_SWIER_SWI3_Pos) /*!< 0x00000008 */ 1942 #define EXTI_SWIER_SWI3 EXTI_SWIER_SWI3_Msk /*!< Software Interrupt on line 3 */ 1943 #define EXTI_SWIER_SWI4_Pos (4U) 1944 #define EXTI_SWIER_SWI4_Msk (0x1U << EXTI_SWIER_SWI4_Pos) /*!< 0x00000010 */ 1945 #define EXTI_SWIER_SWI4 EXTI_SWIER_SWI4_Msk /*!< Software Interrupt on line 4 */ 1946 #define EXTI_SWIER_SWI5_Pos (5U) 1947 #define EXTI_SWIER_SWI5_Msk (0x1U << EXTI_SWIER_SWI5_Pos) /*!< 0x00000020 */ 1948 #define EXTI_SWIER_SWI5 EXTI_SWIER_SWI5_Msk /*!< Software Interrupt on line 5 */ 1949 #define EXTI_SWIER_SWI6_Pos (6U) 1950 #define EXTI_SWIER_SWI6_Msk (0x1U << EXTI_SWIER_SWI6_Pos) /*!< 0x00000040 */ 1951 #define EXTI_SWIER_SWI6 EXTI_SWIER_SWI6_Msk /*!< Software Interrupt on line 6 */ 1952 #define EXTI_SWIER_SWI7_Pos (7U) 1953 #define EXTI_SWIER_SWI7_Msk (0x1U << EXTI_SWIER_SWI7_Pos) /*!< 0x00000080 */ 1954 #define EXTI_SWIER_SWI7 EXTI_SWIER_SWI7_Msk /*!< Software Interrupt on line 7 */ 1955 #define EXTI_SWIER_SWI8_Pos (8U) 1956 #define EXTI_SWIER_SWI8_Msk (0x1U << EXTI_SWIER_SWI8_Pos) /*!< 0x00000100 */ 1957 #define EXTI_SWIER_SWI8 EXTI_SWIER_SWI8_Msk /*!< Software Interrupt on line 8 */ 1958 #define EXTI_SWIER_SWI9_Pos (9U) 1959 #define EXTI_SWIER_SWI9_Msk (0x1U << EXTI_SWIER_SWI9_Pos) /*!< 0x00000200 */ 1960 #define EXTI_SWIER_SWI9 EXTI_SWIER_SWI9_Msk /*!< Software Interrupt on line 9 */ 1961 #define EXTI_SWIER_SWI10_Pos (10U) 1962 #define EXTI_SWIER_SWI10_Msk (0x1U << EXTI_SWIER_SWI10_Pos) /*!< 0x00000400 */ 1963 #define EXTI_SWIER_SWI10 EXTI_SWIER_SWI10_Msk /*!< Software Interrupt on line 10 */ 1964 #define EXTI_SWIER_SWI11_Pos (11U) 1965 #define EXTI_SWIER_SWI11_Msk (0x1U << EXTI_SWIER_SWI11_Pos) /*!< 0x00000800 */ 1966 #define EXTI_SWIER_SWI11 EXTI_SWIER_SWI11_Msk /*!< Software Interrupt on line 11 */ 1967 #define EXTI_SWIER_SWI12_Pos (12U) 1968 #define EXTI_SWIER_SWI12_Msk (0x1U << EXTI_SWIER_SWI12_Pos) /*!< 0x00001000 */ 1969 #define EXTI_SWIER_SWI12 EXTI_SWIER_SWI12_Msk /*!< Software Interrupt on line 12 */ 1970 #define EXTI_SWIER_SWI13_Pos (13U) 1971 #define EXTI_SWIER_SWI13_Msk (0x1U << EXTI_SWIER_SWI13_Pos) /*!< 0x00002000 */ 1972 #define EXTI_SWIER_SWI13 EXTI_SWIER_SWI13_Msk /*!< Software Interrupt on line 13 */ 1973 #define EXTI_SWIER_SWI14_Pos (14U) 1974 #define EXTI_SWIER_SWI14_Msk (0x1U << EXTI_SWIER_SWI14_Pos) /*!< 0x00004000 */ 1975 #define EXTI_SWIER_SWI14 EXTI_SWIER_SWI14_Msk /*!< Software Interrupt on line 14 */ 1976 #define EXTI_SWIER_SWI15_Pos (15U) 1977 #define EXTI_SWIER_SWI15_Msk (0x1U << EXTI_SWIER_SWI15_Pos) /*!< 0x00008000 */ 1978 #define EXTI_SWIER_SWI15 EXTI_SWIER_SWI15_Msk /*!< Software Interrupt on line 15 */ 1979 #define EXTI_SWIER_SWI16_Pos (16U) 1980 #define EXTI_SWIER_SWI16_Msk (0x1U << EXTI_SWIER_SWI16_Pos) /*!< 0x00010000 */ 1981 #define EXTI_SWIER_SWI16 EXTI_SWIER_SWI16_Msk /*!< Software Interrupt on line 16 */ 1982 #define EXTI_SWIER_SWI17_Pos (17U) 1983 #define EXTI_SWIER_SWI17_Msk (0x1U << EXTI_SWIER_SWI17_Pos) /*!< 0x00020000 */ 1984 #define EXTI_SWIER_SWI17 EXTI_SWIER_SWI17_Msk /*!< Software Interrupt on line 17 */ 1985 #define EXTI_SWIER_SWI19_Pos (19U) 1986 #define EXTI_SWIER_SWI19_Msk (0x1U << EXTI_SWIER_SWI19_Pos) /*!< 0x00080000 */ 1987 #define EXTI_SWIER_SWI19 EXTI_SWIER_SWI19_Msk /*!< Software Interrupt on line 19 */ 1988 #define EXTI_SWIER_SWI20_Pos (20U) 1989 #define EXTI_SWIER_SWI20_Msk (0x1U << EXTI_SWIER_SWI20_Pos) /*!< 0x00100000 */ 1990 #define EXTI_SWIER_SWI20 EXTI_SWIER_SWI20_Msk /*!< Software Interrupt on line 20 */ 1991 #define EXTI_SWIER_SWI21_Pos (21U) 1992 #define EXTI_SWIER_SWI21_Msk (0x1U << EXTI_SWIER_SWI21_Pos) /*!< 0x00200000 */ 1993 #define EXTI_SWIER_SWI21 EXTI_SWIER_SWI21_Msk /*!< Software Interrupt on line 21 */ 1994 #define EXTI_SWIER_SWI22_Pos (22U) 1995 #define EXTI_SWIER_SWI22_Msk (0x1U << EXTI_SWIER_SWI22_Pos) /*!< 0x00400000 */ 1996 #define EXTI_SWIER_SWI22 EXTI_SWIER_SWI22_Msk /*!< Software Interrupt on line 22 */ 1997 1998 /* Legacy defines */ 1999 #define EXTI_SWIER_SWIER0 EXTI_SWIER_SWI0 2000 #define EXTI_SWIER_SWIER1 EXTI_SWIER_SWI1 2001 #define EXTI_SWIER_SWIER2 EXTI_SWIER_SWI2 2002 #define EXTI_SWIER_SWIER3 EXTI_SWIER_SWI3 2003 #define EXTI_SWIER_SWIER4 EXTI_SWIER_SWI4 2004 #define EXTI_SWIER_SWIER5 EXTI_SWIER_SWI5 2005 #define EXTI_SWIER_SWIER6 EXTI_SWIER_SWI6 2006 #define EXTI_SWIER_SWIER7 EXTI_SWIER_SWI7 2007 #define EXTI_SWIER_SWIER8 EXTI_SWIER_SWI8 2008 #define EXTI_SWIER_SWIER9 EXTI_SWIER_SWI9 2009 #define EXTI_SWIER_SWIER10 EXTI_SWIER_SWI10 2010 #define EXTI_SWIER_SWIER11 EXTI_SWIER_SWI11 2011 #define EXTI_SWIER_SWIER12 EXTI_SWIER_SWI12 2012 #define EXTI_SWIER_SWIER13 EXTI_SWIER_SWI13 2013 #define EXTI_SWIER_SWIER14 EXTI_SWIER_SWI14 2014 #define EXTI_SWIER_SWIER15 EXTI_SWIER_SWI15 2015 #define EXTI_SWIER_SWIER16 EXTI_SWIER_SWI16 2016 #define EXTI_SWIER_SWIER17 EXTI_SWIER_SWI17 2017 #define EXTI_SWIER_SWIER19 EXTI_SWIER_SWI19 2018 #define EXTI_SWIER_SWIER20 EXTI_SWIER_SWI20 2019 #define EXTI_SWIER_SWIER21 EXTI_SWIER_SWI21 2020 #define EXTI_SWIER_SWIER22 EXTI_SWIER_SWI22 2021 2022 /****************** Bit definition for EXTI_PR register *********************/ 2023 #define EXTI_PR_PIF0_Pos (0U) 2024 #define EXTI_PR_PIF0_Msk (0x1U << EXTI_PR_PIF0_Pos) /*!< 0x00000001 */ 2025 #define EXTI_PR_PIF0 EXTI_PR_PIF0_Msk /*!< Pending bit 0 */ 2026 #define EXTI_PR_PIF1_Pos (1U) 2027 #define EXTI_PR_PIF1_Msk (0x1U << EXTI_PR_PIF1_Pos) /*!< 0x00000002 */ 2028 #define EXTI_PR_PIF1 EXTI_PR_PIF1_Msk /*!< Pending bit 1 */ 2029 #define EXTI_PR_PIF2_Pos (2U) 2030 #define EXTI_PR_PIF2_Msk (0x1U << EXTI_PR_PIF2_Pos) /*!< 0x00000004 */ 2031 #define EXTI_PR_PIF2 EXTI_PR_PIF2_Msk /*!< Pending bit 2 */ 2032 #define EXTI_PR_PIF3_Pos (3U) 2033 #define EXTI_PR_PIF3_Msk (0x1U << EXTI_PR_PIF3_Pos) /*!< 0x00000008 */ 2034 #define EXTI_PR_PIF3 EXTI_PR_PIF3_Msk /*!< Pending bit 3 */ 2035 #define EXTI_PR_PIF4_Pos (4U) 2036 #define EXTI_PR_PIF4_Msk (0x1U << EXTI_PR_PIF4_Pos) /*!< 0x00000010 */ 2037 #define EXTI_PR_PIF4 EXTI_PR_PIF4_Msk /*!< Pending bit 4 */ 2038 #define EXTI_PR_PIF5_Pos (5U) 2039 #define EXTI_PR_PIF5_Msk (0x1U << EXTI_PR_PIF5_Pos) /*!< 0x00000020 */ 2040 #define EXTI_PR_PIF5 EXTI_PR_PIF5_Msk /*!< Pending bit 5 */ 2041 #define EXTI_PR_PIF6_Pos (6U) 2042 #define EXTI_PR_PIF6_Msk (0x1U << EXTI_PR_PIF6_Pos) /*!< 0x00000040 */ 2043 #define EXTI_PR_PIF6 EXTI_PR_PIF6_Msk /*!< Pending bit 6 */ 2044 #define EXTI_PR_PIF7_Pos (7U) 2045 #define EXTI_PR_PIF7_Msk (0x1U << EXTI_PR_PIF7_Pos) /*!< 0x00000080 */ 2046 #define EXTI_PR_PIF7 EXTI_PR_PIF7_Msk /*!< Pending bit 7 */ 2047 #define EXTI_PR_PIF8_Pos (8U) 2048 #define EXTI_PR_PIF8_Msk (0x1U << EXTI_PR_PIF8_Pos) /*!< 0x00000100 */ 2049 #define EXTI_PR_PIF8 EXTI_PR_PIF8_Msk /*!< Pending bit 8 */ 2050 #define EXTI_PR_PIF9_Pos (9U) 2051 #define EXTI_PR_PIF9_Msk (0x1U << EXTI_PR_PIF9_Pos) /*!< 0x00000200 */ 2052 #define EXTI_PR_PIF9 EXTI_PR_PIF9_Msk /*!< Pending bit 9 */ 2053 #define EXTI_PR_PIF10_Pos (10U) 2054 #define EXTI_PR_PIF10_Msk (0x1U << EXTI_PR_PIF10_Pos) /*!< 0x00000400 */ 2055 #define EXTI_PR_PIF10 EXTI_PR_PIF10_Msk /*!< Pending bit 10 */ 2056 #define EXTI_PR_PIF11_Pos (11U) 2057 #define EXTI_PR_PIF11_Msk (0x1U << EXTI_PR_PIF11_Pos) /*!< 0x00000800 */ 2058 #define EXTI_PR_PIF11 EXTI_PR_PIF11_Msk /*!< Pending bit 11 */ 2059 #define EXTI_PR_PIF12_Pos (12U) 2060 #define EXTI_PR_PIF12_Msk (0x1U << EXTI_PR_PIF12_Pos) /*!< 0x00001000 */ 2061 #define EXTI_PR_PIF12 EXTI_PR_PIF12_Msk /*!< Pending bit 12 */ 2062 #define EXTI_PR_PIF13_Pos (13U) 2063 #define EXTI_PR_PIF13_Msk (0x1U << EXTI_PR_PIF13_Pos) /*!< 0x00002000 */ 2064 #define EXTI_PR_PIF13 EXTI_PR_PIF13_Msk /*!< Pending bit 13 */ 2065 #define EXTI_PR_PIF14_Pos (14U) 2066 #define EXTI_PR_PIF14_Msk (0x1U << EXTI_PR_PIF14_Pos) /*!< 0x00004000 */ 2067 #define EXTI_PR_PIF14 EXTI_PR_PIF14_Msk /*!< Pending bit 14 */ 2068 #define EXTI_PR_PIF15_Pos (15U) 2069 #define EXTI_PR_PIF15_Msk (0x1U << EXTI_PR_PIF15_Pos) /*!< 0x00008000 */ 2070 #define EXTI_PR_PIF15 EXTI_PR_PIF15_Msk /*!< Pending bit 15 */ 2071 #define EXTI_PR_PIF16_Pos (16U) 2072 #define EXTI_PR_PIF16_Msk (0x1U << EXTI_PR_PIF16_Pos) /*!< 0x00010000 */ 2073 #define EXTI_PR_PIF16 EXTI_PR_PIF16_Msk /*!< Pending bit 16 */ 2074 #define EXTI_PR_PIF17_Pos (17U) 2075 #define EXTI_PR_PIF17_Msk (0x1U << EXTI_PR_PIF17_Pos) /*!< 0x00020000 */ 2076 #define EXTI_PR_PIF17 EXTI_PR_PIF17_Msk /*!< Pending bit 17 */ 2077 #define EXTI_PR_PIF19_Pos (19U) 2078 #define EXTI_PR_PIF19_Msk (0x1U << EXTI_PR_PIF19_Pos) /*!< 0x00080000 */ 2079 #define EXTI_PR_PIF19 EXTI_PR_PIF19_Msk /*!< Pending bit 19 */ 2080 #define EXTI_PR_PIF20_Pos (20U) 2081 #define EXTI_PR_PIF20_Msk (0x1U << EXTI_PR_PIF20_Pos) /*!< 0x00100000 */ 2082 #define EXTI_PR_PIF20 EXTI_PR_PIF20_Msk /*!< Pending bit 20 */ 2083 #define EXTI_PR_PIF21_Pos (21U) 2084 #define EXTI_PR_PIF21_Msk (0x1U << EXTI_PR_PIF21_Pos) /*!< 0x00200000 */ 2085 #define EXTI_PR_PIF21 EXTI_PR_PIF21_Msk /*!< Pending bit 21 */ 2086 #define EXTI_PR_PIF22_Pos (22U) 2087 #define EXTI_PR_PIF22_Msk (0x1U << EXTI_PR_PIF22_Pos) /*!< 0x00400000 */ 2088 #define EXTI_PR_PIF22 EXTI_PR_PIF22_Msk /*!< Pending bit 22 */ 2089 2090 /* Legacy defines */ 2091 #define EXTI_PR_PR0 EXTI_PR_PIF0 2092 #define EXTI_PR_PR1 EXTI_PR_PIF1 2093 #define EXTI_PR_PR2 EXTI_PR_PIF2 2094 #define EXTI_PR_PR3 EXTI_PR_PIF3 2095 #define EXTI_PR_PR4 EXTI_PR_PIF4 2096 #define EXTI_PR_PR5 EXTI_PR_PIF5 2097 #define EXTI_PR_PR6 EXTI_PR_PIF6 2098 #define EXTI_PR_PR7 EXTI_PR_PIF7 2099 #define EXTI_PR_PR8 EXTI_PR_PIF8 2100 #define EXTI_PR_PR9 EXTI_PR_PIF9 2101 #define EXTI_PR_PR10 EXTI_PR_PIF10 2102 #define EXTI_PR_PR11 EXTI_PR_PIF11 2103 #define EXTI_PR_PR12 EXTI_PR_PIF12 2104 #define EXTI_PR_PR13 EXTI_PR_PIF13 2105 #define EXTI_PR_PR14 EXTI_PR_PIF14 2106 #define EXTI_PR_PR15 EXTI_PR_PIF15 2107 #define EXTI_PR_PR16 EXTI_PR_PIF16 2108 #define EXTI_PR_PR17 EXTI_PR_PIF17 2109 #define EXTI_PR_PR19 EXTI_PR_PIF19 2110 #define EXTI_PR_PR20 EXTI_PR_PIF20 2111 #define EXTI_PR_PR21 EXTI_PR_PIF21 2112 #define EXTI_PR_PR22 EXTI_PR_PIF22 2113 2114 /******************************************************************************/ 2115 /* */ 2116 /* FLASH and Option Bytes Registers */ 2117 /* */ 2118 /******************************************************************************/ 2119 2120 /******************* Bit definition for FLASH_ACR register ******************/ 2121 #define FLASH_ACR_LATENCY_Pos (0U) 2122 #define FLASH_ACR_LATENCY_Msk (0x1U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000001 */ 2123 #define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< LATENCY bit (Latency) */ 2124 #define FLASH_ACR_PRFTEN_Pos (1U) 2125 #define FLASH_ACR_PRFTEN_Msk (0x1U << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000002 */ 2126 #define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk /*!< Prefetch Buffer Enable */ 2127 #define FLASH_ACR_SLEEP_PD_Pos (3U) 2128 #define FLASH_ACR_SLEEP_PD_Msk (0x1U << FLASH_ACR_SLEEP_PD_Pos) /*!< 0x00000008 */ 2129 #define FLASH_ACR_SLEEP_PD FLASH_ACR_SLEEP_PD_Msk /*!< Flash mode during sleep mode */ 2130 #define FLASH_ACR_RUN_PD_Pos (4U) 2131 #define FLASH_ACR_RUN_PD_Msk (0x1U << FLASH_ACR_RUN_PD_Pos) /*!< 0x00000010 */ 2132 #define FLASH_ACR_RUN_PD FLASH_ACR_RUN_PD_Msk /*!< Flash mode during RUN mode */ 2133 #define FLASH_ACR_DISAB_BUF_Pos (5U) 2134 #define FLASH_ACR_DISAB_BUF_Msk (0x1U << FLASH_ACR_DISAB_BUF_Pos) /*!< 0x00000020 */ 2135 #define FLASH_ACR_DISAB_BUF FLASH_ACR_DISAB_BUF_Msk /*!< Disable Buffer */ 2136 #define FLASH_ACR_PRE_READ_Pos (6U) 2137 #define FLASH_ACR_PRE_READ_Msk (0x1U << FLASH_ACR_PRE_READ_Pos) /*!< 0x00000040 */ 2138 #define FLASH_ACR_PRE_READ FLASH_ACR_PRE_READ_Msk /*!< Pre-read data address */ 2139 2140 /******************* Bit definition for FLASH_PECR register ******************/ 2141 #define FLASH_PECR_PELOCK_Pos (0U) 2142 #define FLASH_PECR_PELOCK_Msk (0x1U << FLASH_PECR_PELOCK_Pos) /*!< 0x00000001 */ 2143 #define FLASH_PECR_PELOCK FLASH_PECR_PELOCK_Msk /*!< FLASH_PECR and Flash data Lock */ 2144 #define FLASH_PECR_PRGLOCK_Pos (1U) 2145 #define FLASH_PECR_PRGLOCK_Msk (0x1U << FLASH_PECR_PRGLOCK_Pos) /*!< 0x00000002 */ 2146 #define FLASH_PECR_PRGLOCK FLASH_PECR_PRGLOCK_Msk /*!< Program matrix Lock */ 2147 #define FLASH_PECR_OPTLOCK_Pos (2U) 2148 #define FLASH_PECR_OPTLOCK_Msk (0x1U << FLASH_PECR_OPTLOCK_Pos) /*!< 0x00000004 */ 2149 #define FLASH_PECR_OPTLOCK FLASH_PECR_OPTLOCK_Msk /*!< Option byte matrix Lock */ 2150 #define FLASH_PECR_PROG_Pos (3U) 2151 #define FLASH_PECR_PROG_Msk (0x1U << FLASH_PECR_PROG_Pos) /*!< 0x00000008 */ 2152 #define FLASH_PECR_PROG FLASH_PECR_PROG_Msk /*!< Program matrix selection */ 2153 #define FLASH_PECR_DATA_Pos (4U) 2154 #define FLASH_PECR_DATA_Msk (0x1U << FLASH_PECR_DATA_Pos) /*!< 0x00000010 */ 2155 #define FLASH_PECR_DATA FLASH_PECR_DATA_Msk /*!< Data matrix selection */ 2156 #define FLASH_PECR_FIX_Pos (8U) 2157 #define FLASH_PECR_FIX_Msk (0x1U << FLASH_PECR_FIX_Pos) /*!< 0x00000100 */ 2158 #define FLASH_PECR_FIX FLASH_PECR_FIX_Msk /*!< Fixed Time Data write for Word/Half Word/Byte programming */ 2159 #define FLASH_PECR_ERASE_Pos (9U) 2160 #define FLASH_PECR_ERASE_Msk (0x1U << FLASH_PECR_ERASE_Pos) /*!< 0x00000200 */ 2161 #define FLASH_PECR_ERASE FLASH_PECR_ERASE_Msk /*!< Page erasing mode */ 2162 #define FLASH_PECR_FPRG_Pos (10U) 2163 #define FLASH_PECR_FPRG_Msk (0x1U << FLASH_PECR_FPRG_Pos) /*!< 0x00000400 */ 2164 #define FLASH_PECR_FPRG FLASH_PECR_FPRG_Msk /*!< Fast Page/Half Page programming mode */ 2165 #define FLASH_PECR_PARALLBANK_Pos (15U) 2166 #define FLASH_PECR_PARALLBANK_Msk (0x1U << FLASH_PECR_PARALLBANK_Pos) /*!< 0x00008000 */ 2167 #define FLASH_PECR_PARALLBANK FLASH_PECR_PARALLBANK_Msk /*!< Parallel Bank mode */ 2168 #define FLASH_PECR_EOPIE_Pos (16U) 2169 #define FLASH_PECR_EOPIE_Msk (0x1U << FLASH_PECR_EOPIE_Pos) /*!< 0x00010000 */ 2170 #define FLASH_PECR_EOPIE FLASH_PECR_EOPIE_Msk /*!< End of programming interrupt */ 2171 #define FLASH_PECR_ERRIE_Pos (17U) 2172 #define FLASH_PECR_ERRIE_Msk (0x1U << FLASH_PECR_ERRIE_Pos) /*!< 0x00020000 */ 2173 #define FLASH_PECR_ERRIE FLASH_PECR_ERRIE_Msk /*!< Error interrupt */ 2174 #define FLASH_PECR_OBL_LAUNCH_Pos (18U) 2175 #define FLASH_PECR_OBL_LAUNCH_Msk (0x1U << FLASH_PECR_OBL_LAUNCH_Pos) /*!< 0x00040000 */ 2176 #define FLASH_PECR_OBL_LAUNCH FLASH_PECR_OBL_LAUNCH_Msk /*!< Launch the option byte loading */ 2177 #define FLASH_PECR_HALF_ARRAY_Pos (19U) 2178 #define FLASH_PECR_HALF_ARRAY_Msk (0x1U << FLASH_PECR_HALF_ARRAY_Pos) /*!< 0x00080000 */ 2179 #define FLASH_PECR_HALF_ARRAY FLASH_PECR_HALF_ARRAY_Msk /*!< Half array mode */ 2180 #define FLASH_PECR_NZDISABLE_Pos (22U) 2181 #define FLASH_PECR_NZDISABLE_Msk (0x1U << FLASH_PECR_NZDISABLE_Pos) /*!< 0x00400000 */ 2182 #define FLASH_PECR_NZDISABLE FLASH_PECR_NZDISABLE_Msk /*!< Non-Zero check disable */ 2183 2184 /****************** Bit definition for FLASH_PDKEYR register ******************/ 2185 #define FLASH_PDKEYR_PDKEYR_Pos (0U) 2186 #define FLASH_PDKEYR_PDKEYR_Msk (0xFFFFFFFFU << FLASH_PDKEYR_PDKEYR_Pos) /*!< 0xFFFFFFFF */ 2187 #define FLASH_PDKEYR_PDKEYR FLASH_PDKEYR_PDKEYR_Msk /*!< FLASH_PEC and data matrix Key */ 2188 2189 /****************** Bit definition for FLASH_PEKEYR register ******************/ 2190 #define FLASH_PEKEYR_PEKEYR_Pos (0U) 2191 #define FLASH_PEKEYR_PEKEYR_Msk (0xFFFFFFFFU << FLASH_PEKEYR_PEKEYR_Pos) /*!< 0xFFFFFFFF */ 2192 #define FLASH_PEKEYR_PEKEYR FLASH_PEKEYR_PEKEYR_Msk /*!< FLASH_PEC and data matrix Key */ 2193 2194 /****************** Bit definition for FLASH_PRGKEYR register ******************/ 2195 #define FLASH_PRGKEYR_PRGKEYR_Pos (0U) 2196 #define FLASH_PRGKEYR_PRGKEYR_Msk (0xFFFFFFFFU << FLASH_PRGKEYR_PRGKEYR_Pos) /*!< 0xFFFFFFFF */ 2197 #define FLASH_PRGKEYR_PRGKEYR FLASH_PRGKEYR_PRGKEYR_Msk /*!< Program matrix Key */ 2198 2199 /****************** Bit definition for FLASH_OPTKEYR register ******************/ 2200 #define FLASH_OPTKEYR_OPTKEYR_Pos (0U) 2201 #define FLASH_OPTKEYR_OPTKEYR_Msk (0xFFFFFFFFU << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */ 2202 #define FLASH_OPTKEYR_OPTKEYR FLASH_OPTKEYR_OPTKEYR_Msk /*!< Option bytes matrix Key */ 2203 2204 /****************** Bit definition for FLASH_SR register *******************/ 2205 #define FLASH_SR_BSY_Pos (0U) 2206 #define FLASH_SR_BSY_Msk (0x1U << FLASH_SR_BSY_Pos) /*!< 0x00000001 */ 2207 #define FLASH_SR_BSY FLASH_SR_BSY_Msk /*!< Busy */ 2208 #define FLASH_SR_EOP_Pos (1U) 2209 #define FLASH_SR_EOP_Msk (0x1U << FLASH_SR_EOP_Pos) /*!< 0x00000002 */ 2210 #define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< End Of Programming*/ 2211 #define FLASH_SR_HVOFF_Pos (2U) 2212 #define FLASH_SR_HVOFF_Msk (0x1U << FLASH_SR_HVOFF_Pos) /*!< 0x00000004 */ 2213 #define FLASH_SR_HVOFF FLASH_SR_HVOFF_Msk /*!< End of high voltage */ 2214 #define FLASH_SR_READY_Pos (3U) 2215 #define FLASH_SR_READY_Msk (0x1U << FLASH_SR_READY_Pos) /*!< 0x00000008 */ 2216 #define FLASH_SR_READY FLASH_SR_READY_Msk /*!< Flash ready after low power mode */ 2217 2218 #define FLASH_SR_WRPERR_Pos (8U) 2219 #define FLASH_SR_WRPERR_Msk (0x1U << FLASH_SR_WRPERR_Pos) /*!< 0x00000100 */ 2220 #define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk /*!< Write protection error */ 2221 #define FLASH_SR_PGAERR_Pos (9U) 2222 #define FLASH_SR_PGAERR_Msk (0x1U << FLASH_SR_PGAERR_Pos) /*!< 0x00000200 */ 2223 #define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk /*!< Programming Alignment Error */ 2224 #define FLASH_SR_SIZERR_Pos (10U) 2225 #define FLASH_SR_SIZERR_Msk (0x1U << FLASH_SR_SIZERR_Pos) /*!< 0x00000400 */ 2226 #define FLASH_SR_SIZERR FLASH_SR_SIZERR_Msk /*!< Size error */ 2227 #define FLASH_SR_OPTVERR_Pos (11U) 2228 #define FLASH_SR_OPTVERR_Msk (0x1U << FLASH_SR_OPTVERR_Pos) /*!< 0x00000800 */ 2229 #define FLASH_SR_OPTVERR FLASH_SR_OPTVERR_Msk /*!< Option Valid error */ 2230 #define FLASH_SR_RDERR_Pos (13U) 2231 #define FLASH_SR_RDERR_Msk (0x1U << FLASH_SR_RDERR_Pos) /*!< 0x00002000 */ 2232 #define FLASH_SR_RDERR FLASH_SR_RDERR_Msk /*!< Read protected error */ 2233 #define FLASH_SR_NOTZEROERR_Pos (16U) 2234 #define FLASH_SR_NOTZEROERR_Msk (0x1U << FLASH_SR_NOTZEROERR_Pos) /*!< 0x00010000 */ 2235 #define FLASH_SR_NOTZEROERR FLASH_SR_NOTZEROERR_Msk /*!< Not Zero error */ 2236 #define FLASH_SR_FWWERR_Pos (17U) 2237 #define FLASH_SR_FWWERR_Msk (0x1U << FLASH_SR_FWWERR_Pos) /*!< 0x00020000 */ 2238 #define FLASH_SR_FWWERR FLASH_SR_FWWERR_Msk /*!< Write/Errase operation aborted */ 2239 2240 /* Legacy defines */ 2241 #define FLASH_SR_FWWER FLASH_SR_FWWERR 2242 #define FLASH_SR_ENHV FLASH_SR_HVOFF 2243 #define FLASH_SR_ENDHV FLASH_SR_HVOFF 2244 2245 /****************** Bit definition for FLASH_OPTR register *******************/ 2246 #define FLASH_OPTR_RDPROT_Pos (0U) 2247 #define FLASH_OPTR_RDPROT_Msk (0xFFU << FLASH_OPTR_RDPROT_Pos) /*!< 0x000000FF */ 2248 #define FLASH_OPTR_RDPROT FLASH_OPTR_RDPROT_Msk /*!< Read Protection */ 2249 #define FLASH_OPTR_WPRMOD_Pos (8U) 2250 #define FLASH_OPTR_WPRMOD_Msk (0x1U << FLASH_OPTR_WPRMOD_Pos) /*!< 0x00000100 */ 2251 #define FLASH_OPTR_WPRMOD FLASH_OPTR_WPRMOD_Msk /*!< Selection of protection mode of WPR bits */ 2252 #define FLASH_OPTR_BOR_LEV_Pos (16U) 2253 #define FLASH_OPTR_BOR_LEV_Msk (0xFU << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x000F0000 */ 2254 #define FLASH_OPTR_BOR_LEV FLASH_OPTR_BOR_LEV_Msk /*!< BOR_LEV[3:0] Brown Out Reset Threshold Level*/ 2255 #define FLASH_OPTR_IWDG_SW_Pos (20U) 2256 #define FLASH_OPTR_IWDG_SW_Msk (0x1U << FLASH_OPTR_IWDG_SW_Pos) /*!< 0x00100000 */ 2257 #define FLASH_OPTR_IWDG_SW FLASH_OPTR_IWDG_SW_Msk /*!< IWDG_SW */ 2258 #define FLASH_OPTR_nRST_STOP_Pos (21U) 2259 #define FLASH_OPTR_nRST_STOP_Msk (0x1U << FLASH_OPTR_nRST_STOP_Pos) /*!< 0x00200000 */ 2260 #define FLASH_OPTR_nRST_STOP FLASH_OPTR_nRST_STOP_Msk /*!< nRST_STOP */ 2261 #define FLASH_OPTR_nRST_STDBY_Pos (22U) 2262 #define FLASH_OPTR_nRST_STDBY_Msk (0x1U << FLASH_OPTR_nRST_STDBY_Pos) /*!< 0x00400000 */ 2263 #define FLASH_OPTR_nRST_STDBY FLASH_OPTR_nRST_STDBY_Msk /*!< nRST_STDBY */ 2264 #define FLASH_OPTR_BFB2_Pos (23U) 2265 #define FLASH_OPTR_BFB2_Msk (0x1U << FLASH_OPTR_BFB2_Pos) /*!< 0x00800000 */ 2266 #define FLASH_OPTR_BFB2 FLASH_OPTR_BFB2_Msk /*!< BFB2 */ 2267 #define FLASH_OPTR_USER_Pos (20U) 2268 #define FLASH_OPTR_USER_Msk (0x7U << FLASH_OPTR_USER_Pos) /*!< 0x00700000 */ 2269 #define FLASH_OPTR_USER FLASH_OPTR_USER_Msk /*!< User Option Bytes */ 2270 #define FLASH_OPTR_BOOT1_Pos (31U) 2271 #define FLASH_OPTR_BOOT1_Msk (0x1U << FLASH_OPTR_BOOT1_Pos) /*!< 0x80000000 */ 2272 #define FLASH_OPTR_BOOT1 FLASH_OPTR_BOOT1_Msk /*!< BOOT1 */ 2273 2274 /****************** Bit definition for FLASH_WRPR register ******************/ 2275 #define FLASH_WRPR_WRP_Pos (0U) 2276 #define FLASH_WRPR_WRP_Msk (0xFFFFU << FLASH_WRPR_WRP_Pos) /*!< 0x0000FFFF */ 2277 #define FLASH_WRPR_WRP FLASH_WRPR_WRP_Msk /*!< Write Protection bits */ 2278 2279 /******************************************************************************/ 2280 /* */ 2281 /* General Purpose IOs (GPIO) */ 2282 /* */ 2283 /******************************************************************************/ 2284 /******************* Bit definition for GPIO_MODER register *****************/ 2285 #define GPIO_MODER_MODE0_Pos (0U) 2286 #define GPIO_MODER_MODE0_Msk (0x3U << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */ 2287 #define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk 2288 #define GPIO_MODER_MODE0_0 (0x1U << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */ 2289 #define GPIO_MODER_MODE0_1 (0x2U << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */ 2290 #define GPIO_MODER_MODE1_Pos (2U) 2291 #define GPIO_MODER_MODE1_Msk (0x3U << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */ 2292 #define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk 2293 #define GPIO_MODER_MODE1_0 (0x1U << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */ 2294 #define GPIO_MODER_MODE1_1 (0x2U << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */ 2295 #define GPIO_MODER_MODE2_Pos (4U) 2296 #define GPIO_MODER_MODE2_Msk (0x3U << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */ 2297 #define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk 2298 #define GPIO_MODER_MODE2_0 (0x1U << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */ 2299 #define GPIO_MODER_MODE2_1 (0x2U << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */ 2300 #define GPIO_MODER_MODE3_Pos (6U) 2301 #define GPIO_MODER_MODE3_Msk (0x3U << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */ 2302 #define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk 2303 #define GPIO_MODER_MODE3_0 (0x1U << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */ 2304 #define GPIO_MODER_MODE3_1 (0x2U << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */ 2305 #define GPIO_MODER_MODE4_Pos (8U) 2306 #define GPIO_MODER_MODE4_Msk (0x3U << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */ 2307 #define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk 2308 #define GPIO_MODER_MODE4_0 (0x1U << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */ 2309 #define GPIO_MODER_MODE4_1 (0x2U << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */ 2310 #define GPIO_MODER_MODE5_Pos (10U) 2311 #define GPIO_MODER_MODE5_Msk (0x3U << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */ 2312 #define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk 2313 #define GPIO_MODER_MODE5_0 (0x1U << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */ 2314 #define GPIO_MODER_MODE5_1 (0x2U << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */ 2315 #define GPIO_MODER_MODE6_Pos (12U) 2316 #define GPIO_MODER_MODE6_Msk (0x3U << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */ 2317 #define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk 2318 #define GPIO_MODER_MODE6_0 (0x1U << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */ 2319 #define GPIO_MODER_MODE6_1 (0x2U << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */ 2320 #define GPIO_MODER_MODE7_Pos (14U) 2321 #define GPIO_MODER_MODE7_Msk (0x3U << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */ 2322 #define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk 2323 #define GPIO_MODER_MODE7_0 (0x1U << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */ 2324 #define GPIO_MODER_MODE7_1 (0x2U << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */ 2325 #define GPIO_MODER_MODE8_Pos (16U) 2326 #define GPIO_MODER_MODE8_Msk (0x3U << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */ 2327 #define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk 2328 #define GPIO_MODER_MODE8_0 (0x1U << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */ 2329 #define GPIO_MODER_MODE8_1 (0x2U << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */ 2330 #define GPIO_MODER_MODE9_Pos (18U) 2331 #define GPIO_MODER_MODE9_Msk (0x3U << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */ 2332 #define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk 2333 #define GPIO_MODER_MODE9_0 (0x1U << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */ 2334 #define GPIO_MODER_MODE9_1 (0x2U << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */ 2335 #define GPIO_MODER_MODE10_Pos (20U) 2336 #define GPIO_MODER_MODE10_Msk (0x3U << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */ 2337 #define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk 2338 #define GPIO_MODER_MODE10_0 (0x1U << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */ 2339 #define GPIO_MODER_MODE10_1 (0x2U << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */ 2340 #define GPIO_MODER_MODE11_Pos (22U) 2341 #define GPIO_MODER_MODE11_Msk (0x3U << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */ 2342 #define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk 2343 #define GPIO_MODER_MODE11_0 (0x1U << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */ 2344 #define GPIO_MODER_MODE11_1 (0x2U << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */ 2345 #define GPIO_MODER_MODE12_Pos (24U) 2346 #define GPIO_MODER_MODE12_Msk (0x3U << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */ 2347 #define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk 2348 #define GPIO_MODER_MODE12_0 (0x1U << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */ 2349 #define GPIO_MODER_MODE12_1 (0x2U << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */ 2350 #define GPIO_MODER_MODE13_Pos (26U) 2351 #define GPIO_MODER_MODE13_Msk (0x3U << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */ 2352 #define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk 2353 #define GPIO_MODER_MODE13_0 (0x1U << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */ 2354 #define GPIO_MODER_MODE13_1 (0x2U << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */ 2355 #define GPIO_MODER_MODE14_Pos (28U) 2356 #define GPIO_MODER_MODE14_Msk (0x3U << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */ 2357 #define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk 2358 #define GPIO_MODER_MODE14_0 (0x1U << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */ 2359 #define GPIO_MODER_MODE14_1 (0x2U << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */ 2360 #define GPIO_MODER_MODE15_Pos (30U) 2361 #define GPIO_MODER_MODE15_Msk (0x3U << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */ 2362 #define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk 2363 #define GPIO_MODER_MODE15_0 (0x1U << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */ 2364 #define GPIO_MODER_MODE15_1 (0x2U << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */ 2365 2366 /****************** Bit definition for GPIO_OTYPER register *****************/ 2367 #define GPIO_OTYPER_OT_0 (0x00000001U) 2368 #define GPIO_OTYPER_OT_1 (0x00000002U) 2369 #define GPIO_OTYPER_OT_2 (0x00000004U) 2370 #define GPIO_OTYPER_OT_3 (0x00000008U) 2371 #define GPIO_OTYPER_OT_4 (0x00000010U) 2372 #define GPIO_OTYPER_OT_5 (0x00000020U) 2373 #define GPIO_OTYPER_OT_6 (0x00000040U) 2374 #define GPIO_OTYPER_OT_7 (0x00000080U) 2375 #define GPIO_OTYPER_OT_8 (0x00000100U) 2376 #define GPIO_OTYPER_OT_9 (0x00000200U) 2377 #define GPIO_OTYPER_OT_10 (0x00000400U) 2378 #define GPIO_OTYPER_OT_11 (0x00000800U) 2379 #define GPIO_OTYPER_OT_12 (0x00001000U) 2380 #define GPIO_OTYPER_OT_13 (0x00002000U) 2381 #define GPIO_OTYPER_OT_14 (0x00004000U) 2382 #define GPIO_OTYPER_OT_15 (0x00008000U) 2383 2384 /**************** Bit definition for GPIO_OSPEEDR register ******************/ 2385 #define GPIO_OSPEEDER_OSPEED0_Pos (0U) 2386 #define GPIO_OSPEEDER_OSPEED0_Msk (0x3U << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000003 */ 2387 #define GPIO_OSPEEDER_OSPEED0 GPIO_OSPEEDER_OSPEED0_Msk 2388 #define GPIO_OSPEEDER_OSPEED0_0 (0x1U << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000001 */ 2389 #define GPIO_OSPEEDER_OSPEED0_1 (0x2U << GPIO_OSPEEDER_OSPEED0_Pos) /*!< 0x00000002 */ 2390 #define GPIO_OSPEEDER_OSPEED1_Pos (2U) 2391 #define GPIO_OSPEEDER_OSPEED1_Msk (0x3U << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x0000000C */ 2392 #define GPIO_OSPEEDER_OSPEED1 GPIO_OSPEEDER_OSPEED1_Msk 2393 #define GPIO_OSPEEDER_OSPEED1_0 (0x1U << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x00000004 */ 2394 #define GPIO_OSPEEDER_OSPEED1_1 (0x2U << GPIO_OSPEEDER_OSPEED1_Pos) /*!< 0x00000008 */ 2395 #define GPIO_OSPEEDER_OSPEED2_Pos (4U) 2396 #define GPIO_OSPEEDER_OSPEED2_Msk (0x3U << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000030 */ 2397 #define GPIO_OSPEEDER_OSPEED2 GPIO_OSPEEDER_OSPEED2_Msk 2398 #define GPIO_OSPEEDER_OSPEED2_0 (0x1U << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000010 */ 2399 #define GPIO_OSPEEDER_OSPEED2_1 (0x2U << GPIO_OSPEEDER_OSPEED2_Pos) /*!< 0x00000020 */ 2400 #define GPIO_OSPEEDER_OSPEED3_Pos (6U) 2401 #define GPIO_OSPEEDER_OSPEED3_Msk (0x3U << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x000000C0 */ 2402 #define GPIO_OSPEEDER_OSPEED3 GPIO_OSPEEDER_OSPEED3_Msk 2403 #define GPIO_OSPEEDER_OSPEED3_0 (0x1U << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x00000040 */ 2404 #define GPIO_OSPEEDER_OSPEED3_1 (0x2U << GPIO_OSPEEDER_OSPEED3_Pos) /*!< 0x00000080 */ 2405 #define GPIO_OSPEEDER_OSPEED4_Pos (8U) 2406 #define GPIO_OSPEEDER_OSPEED4_Msk (0x3U << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000300 */ 2407 #define GPIO_OSPEEDER_OSPEED4 GPIO_OSPEEDER_OSPEED4_Msk 2408 #define GPIO_OSPEEDER_OSPEED4_0 (0x1U << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000100 */ 2409 #define GPIO_OSPEEDER_OSPEED4_1 (0x2U << GPIO_OSPEEDER_OSPEED4_Pos) /*!< 0x00000200 */ 2410 #define GPIO_OSPEEDER_OSPEED5_Pos (10U) 2411 #define GPIO_OSPEEDER_OSPEED5_Msk (0x3U << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000C00 */ 2412 #define GPIO_OSPEEDER_OSPEED5 GPIO_OSPEEDER_OSPEED5_Msk 2413 #define GPIO_OSPEEDER_OSPEED5_0 (0x1U << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000400 */ 2414 #define GPIO_OSPEEDER_OSPEED5_1 (0x2U << GPIO_OSPEEDER_OSPEED5_Pos) /*!< 0x00000800 */ 2415 #define GPIO_OSPEEDER_OSPEED6_Pos (12U) 2416 #define GPIO_OSPEEDER_OSPEED6_Msk (0x3U << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00003000 */ 2417 #define GPIO_OSPEEDER_OSPEED6 GPIO_OSPEEDER_OSPEED6_Msk 2418 #define GPIO_OSPEEDER_OSPEED6_0 (0x1U << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00001000 */ 2419 #define GPIO_OSPEEDER_OSPEED6_1 (0x2U << GPIO_OSPEEDER_OSPEED6_Pos) /*!< 0x00002000 */ 2420 #define GPIO_OSPEEDER_OSPEED7_Pos (14U) 2421 #define GPIO_OSPEEDER_OSPEED7_Msk (0x3U << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x0000C000 */ 2422 #define GPIO_OSPEEDER_OSPEED7 GPIO_OSPEEDER_OSPEED7_Msk 2423 #define GPIO_OSPEEDER_OSPEED7_0 (0x1U << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x00004000 */ 2424 #define GPIO_OSPEEDER_OSPEED7_1 (0x2U << GPIO_OSPEEDER_OSPEED7_Pos) /*!< 0x00008000 */ 2425 #define GPIO_OSPEEDER_OSPEED8_Pos (16U) 2426 #define GPIO_OSPEEDER_OSPEED8_Msk (0x3U << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00030000 */ 2427 #define GPIO_OSPEEDER_OSPEED8 GPIO_OSPEEDER_OSPEED8_Msk 2428 #define GPIO_OSPEEDER_OSPEED8_0 (0x1U << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00010000 */ 2429 #define GPIO_OSPEEDER_OSPEED8_1 (0x2U << GPIO_OSPEEDER_OSPEED8_Pos) /*!< 0x00020000 */ 2430 #define GPIO_OSPEEDER_OSPEED9_Pos (18U) 2431 #define GPIO_OSPEEDER_OSPEED9_Msk (0x3U << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x000C0000 */ 2432 #define GPIO_OSPEEDER_OSPEED9 GPIO_OSPEEDER_OSPEED9_Msk 2433 #define GPIO_OSPEEDER_OSPEED9_0 (0x1U << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x00040000 */ 2434 #define GPIO_OSPEEDER_OSPEED9_1 (0x2U << GPIO_OSPEEDER_OSPEED9_Pos) /*!< 0x00080000 */ 2435 #define GPIO_OSPEEDER_OSPEED10_Pos (20U) 2436 #define GPIO_OSPEEDER_OSPEED10_Msk (0x3U << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00300000 */ 2437 #define GPIO_OSPEEDER_OSPEED10 GPIO_OSPEEDER_OSPEED10_Msk 2438 #define GPIO_OSPEEDER_OSPEED10_0 (0x1U << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00100000 */ 2439 #define GPIO_OSPEEDER_OSPEED10_1 (0x2U << GPIO_OSPEEDER_OSPEED10_Pos) /*!< 0x00200000 */ 2440 #define GPIO_OSPEEDER_OSPEED11_Pos (22U) 2441 #define GPIO_OSPEEDER_OSPEED11_Msk (0x3U << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00C00000 */ 2442 #define GPIO_OSPEEDER_OSPEED11 GPIO_OSPEEDER_OSPEED11_Msk 2443 #define GPIO_OSPEEDER_OSPEED11_0 (0x1U << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00400000 */ 2444 #define GPIO_OSPEEDER_OSPEED11_1 (0x2U << GPIO_OSPEEDER_OSPEED11_Pos) /*!< 0x00800000 */ 2445 #define GPIO_OSPEEDER_OSPEED12_Pos (24U) 2446 #define GPIO_OSPEEDER_OSPEED12_Msk (0x3U << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x03000000 */ 2447 #define GPIO_OSPEEDER_OSPEED12 GPIO_OSPEEDER_OSPEED12_Msk 2448 #define GPIO_OSPEEDER_OSPEED12_0 (0x1U << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x01000000 */ 2449 #define GPIO_OSPEEDER_OSPEED12_1 (0x2U << GPIO_OSPEEDER_OSPEED12_Pos) /*!< 0x02000000 */ 2450 #define GPIO_OSPEEDER_OSPEED13_Pos (26U) 2451 #define GPIO_OSPEEDER_OSPEED13_Msk (0x3U << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x0C000000 */ 2452 #define GPIO_OSPEEDER_OSPEED13 GPIO_OSPEEDER_OSPEED13_Msk 2453 #define GPIO_OSPEEDER_OSPEED13_0 (0x1U << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x04000000 */ 2454 #define GPIO_OSPEEDER_OSPEED13_1 (0x2U << GPIO_OSPEEDER_OSPEED13_Pos) /*!< 0x08000000 */ 2455 #define GPIO_OSPEEDER_OSPEED14_Pos (28U) 2456 #define GPIO_OSPEEDER_OSPEED14_Msk (0x3U << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x30000000 */ 2457 #define GPIO_OSPEEDER_OSPEED14 GPIO_OSPEEDER_OSPEED14_Msk 2458 #define GPIO_OSPEEDER_OSPEED14_0 (0x1U << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x10000000 */ 2459 #define GPIO_OSPEEDER_OSPEED14_1 (0x2U << GPIO_OSPEEDER_OSPEED14_Pos) /*!< 0x20000000 */ 2460 #define GPIO_OSPEEDER_OSPEED15_Pos (30U) 2461 #define GPIO_OSPEEDER_OSPEED15_Msk (0x3U << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0xC0000000 */ 2462 #define GPIO_OSPEEDER_OSPEED15 GPIO_OSPEEDER_OSPEED15_Msk 2463 #define GPIO_OSPEEDER_OSPEED15_0 (0x1U << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0x40000000 */ 2464 #define GPIO_OSPEEDER_OSPEED15_1 (0x2U << GPIO_OSPEEDER_OSPEED15_Pos) /*!< 0x80000000 */ 2465 2466 /******************* Bit definition for GPIO_PUPDR register ******************/ 2467 #define GPIO_PUPDR_PUPD0_Pos (0U) 2468 #define GPIO_PUPDR_PUPD0_Msk (0x3U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */ 2469 #define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk 2470 #define GPIO_PUPDR_PUPD0_0 (0x1U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */ 2471 #define GPIO_PUPDR_PUPD0_1 (0x2U << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */ 2472 #define GPIO_PUPDR_PUPD1_Pos (2U) 2473 #define GPIO_PUPDR_PUPD1_Msk (0x3U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */ 2474 #define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk 2475 #define GPIO_PUPDR_PUPD1_0 (0x1U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */ 2476 #define GPIO_PUPDR_PUPD1_1 (0x2U << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */ 2477 #define GPIO_PUPDR_PUPD2_Pos (4U) 2478 #define GPIO_PUPDR_PUPD2_Msk (0x3U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */ 2479 #define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk 2480 #define GPIO_PUPDR_PUPD2_0 (0x1U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */ 2481 #define GPIO_PUPDR_PUPD2_1 (0x2U << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */ 2482 #define GPIO_PUPDR_PUPD3_Pos (6U) 2483 #define GPIO_PUPDR_PUPD3_Msk (0x3U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */ 2484 #define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk 2485 #define GPIO_PUPDR_PUPD3_0 (0x1U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */ 2486 #define GPIO_PUPDR_PUPD3_1 (0x2U << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */ 2487 #define GPIO_PUPDR_PUPD4_Pos (8U) 2488 #define GPIO_PUPDR_PUPD4_Msk (0x3U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */ 2489 #define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk 2490 #define GPIO_PUPDR_PUPD4_0 (0x1U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */ 2491 #define GPIO_PUPDR_PUPD4_1 (0x2U << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */ 2492 #define GPIO_PUPDR_PUPD5_Pos (10U) 2493 #define GPIO_PUPDR_PUPD5_Msk (0x3U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */ 2494 #define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk 2495 #define GPIO_PUPDR_PUPD5_0 (0x1U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */ 2496 #define GPIO_PUPDR_PUPD5_1 (0x2U << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */ 2497 #define GPIO_PUPDR_PUPD6_Pos (12U) 2498 #define GPIO_PUPDR_PUPD6_Msk (0x3U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */ 2499 #define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk 2500 #define GPIO_PUPDR_PUPD6_0 (0x1U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */ 2501 #define GPIO_PUPDR_PUPD6_1 (0x2U << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */ 2502 #define GPIO_PUPDR_PUPD7_Pos (14U) 2503 #define GPIO_PUPDR_PUPD7_Msk (0x3U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */ 2504 #define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk 2505 #define GPIO_PUPDR_PUPD7_0 (0x1U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */ 2506 #define GPIO_PUPDR_PUPD7_1 (0x2U << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */ 2507 #define GPIO_PUPDR_PUPD8_Pos (16U) 2508 #define GPIO_PUPDR_PUPD8_Msk (0x3U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */ 2509 #define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk 2510 #define GPIO_PUPDR_PUPD8_0 (0x1U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */ 2511 #define GPIO_PUPDR_PUPD8_1 (0x2U << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */ 2512 #define GPIO_PUPDR_PUPD9_Pos (18U) 2513 #define GPIO_PUPDR_PUPD9_Msk (0x3U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */ 2514 #define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk 2515 #define GPIO_PUPDR_PUPD9_0 (0x1U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */ 2516 #define GPIO_PUPDR_PUPD9_1 (0x2U << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */ 2517 #define GPIO_PUPDR_PUPD10_Pos (20U) 2518 #define GPIO_PUPDR_PUPD10_Msk (0x3U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */ 2519 #define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk 2520 #define GPIO_PUPDR_PUPD10_0 (0x1U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */ 2521 #define GPIO_PUPDR_PUPD10_1 (0x2U << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */ 2522 #define GPIO_PUPDR_PUPD11_Pos (22U) 2523 #define GPIO_PUPDR_PUPD11_Msk (0x3U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */ 2524 #define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk 2525 #define GPIO_PUPDR_PUPD11_0 (0x1U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */ 2526 #define GPIO_PUPDR_PUPD11_1 (0x2U << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */ 2527 #define GPIO_PUPDR_PUPD12_Pos (24U) 2528 #define GPIO_PUPDR_PUPD12_Msk (0x3U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */ 2529 #define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk 2530 #define GPIO_PUPDR_PUPD12_0 (0x1U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */ 2531 #define GPIO_PUPDR_PUPD12_1 (0x2U << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */ 2532 #define GPIO_PUPDR_PUPD13_Pos (26U) 2533 #define GPIO_PUPDR_PUPD13_Msk (0x3U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */ 2534 #define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk 2535 #define GPIO_PUPDR_PUPD13_0 (0x1U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */ 2536 #define GPIO_PUPDR_PUPD13_1 (0x2U << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */ 2537 #define GPIO_PUPDR_PUPD14_Pos (28U) 2538 #define GPIO_PUPDR_PUPD14_Msk (0x3U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */ 2539 #define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk 2540 #define GPIO_PUPDR_PUPD14_0 (0x1U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */ 2541 #define GPIO_PUPDR_PUPD14_1 (0x2U << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */ 2542 #define GPIO_PUPDR_PUPD15_Pos (30U) 2543 #define GPIO_PUPDR_PUPD15_Msk (0x3U << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */ 2544 #define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk 2545 #define GPIO_PUPDR_PUPD15_0 (0x1U << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */ 2546 #define GPIO_PUPDR_PUPD15_1 (0x2U << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */ 2547 2548 /******************* Bit definition for GPIO_IDR register *******************/ 2549 #define GPIO_IDR_ID0_Pos (0U) 2550 #define GPIO_IDR_ID0_Msk (0x1U << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */ 2551 #define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk 2552 #define GPIO_IDR_ID1_Pos (1U) 2553 #define GPIO_IDR_ID1_Msk (0x1U << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */ 2554 #define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk 2555 #define GPIO_IDR_ID2_Pos (2U) 2556 #define GPIO_IDR_ID2_Msk (0x1U << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */ 2557 #define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk 2558 #define GPIO_IDR_ID3_Pos (3U) 2559 #define GPIO_IDR_ID3_Msk (0x1U << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */ 2560 #define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk 2561 #define GPIO_IDR_ID4_Pos (4U) 2562 #define GPIO_IDR_ID4_Msk (0x1U << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */ 2563 #define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk 2564 #define GPIO_IDR_ID5_Pos (5U) 2565 #define GPIO_IDR_ID5_Msk (0x1U << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */ 2566 #define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk 2567 #define GPIO_IDR_ID6_Pos (6U) 2568 #define GPIO_IDR_ID6_Msk (0x1U << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */ 2569 #define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk 2570 #define GPIO_IDR_ID7_Pos (7U) 2571 #define GPIO_IDR_ID7_Msk (0x1U << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */ 2572 #define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk 2573 #define GPIO_IDR_ID8_Pos (8U) 2574 #define GPIO_IDR_ID8_Msk (0x1U << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */ 2575 #define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk 2576 #define GPIO_IDR_ID9_Pos (9U) 2577 #define GPIO_IDR_ID9_Msk (0x1U << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */ 2578 #define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk 2579 #define GPIO_IDR_ID10_Pos (10U) 2580 #define GPIO_IDR_ID10_Msk (0x1U << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */ 2581 #define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk 2582 #define GPIO_IDR_ID11_Pos (11U) 2583 #define GPIO_IDR_ID11_Msk (0x1U << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */ 2584 #define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk 2585 #define GPIO_IDR_ID12_Pos (12U) 2586 #define GPIO_IDR_ID12_Msk (0x1U << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */ 2587 #define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk 2588 #define GPIO_IDR_ID13_Pos (13U) 2589 #define GPIO_IDR_ID13_Msk (0x1U << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */ 2590 #define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk 2591 #define GPIO_IDR_ID14_Pos (14U) 2592 #define GPIO_IDR_ID14_Msk (0x1U << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */ 2593 #define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk 2594 #define GPIO_IDR_ID15_Pos (15U) 2595 #define GPIO_IDR_ID15_Msk (0x1U << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */ 2596 #define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk 2597 2598 /****************** Bit definition for GPIO_ODR register ********************/ 2599 #define GPIO_ODR_OD0_Pos (0U) 2600 #define GPIO_ODR_OD0_Msk (0x1U << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */ 2601 #define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk 2602 #define GPIO_ODR_OD1_Pos (1U) 2603 #define GPIO_ODR_OD1_Msk (0x1U << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */ 2604 #define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk 2605 #define GPIO_ODR_OD2_Pos (2U) 2606 #define GPIO_ODR_OD2_Msk (0x1U << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */ 2607 #define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk 2608 #define GPIO_ODR_OD3_Pos (3U) 2609 #define GPIO_ODR_OD3_Msk (0x1U << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */ 2610 #define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk 2611 #define GPIO_ODR_OD4_Pos (4U) 2612 #define GPIO_ODR_OD4_Msk (0x1U << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */ 2613 #define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk 2614 #define GPIO_ODR_OD5_Pos (5U) 2615 #define GPIO_ODR_OD5_Msk (0x1U << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */ 2616 #define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk 2617 #define GPIO_ODR_OD6_Pos (6U) 2618 #define GPIO_ODR_OD6_Msk (0x1U << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */ 2619 #define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk 2620 #define GPIO_ODR_OD7_Pos (7U) 2621 #define GPIO_ODR_OD7_Msk (0x1U << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */ 2622 #define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk 2623 #define GPIO_ODR_OD8_Pos (8U) 2624 #define GPIO_ODR_OD8_Msk (0x1U << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */ 2625 #define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk 2626 #define GPIO_ODR_OD9_Pos (9U) 2627 #define GPIO_ODR_OD9_Msk (0x1U << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */ 2628 #define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk 2629 #define GPIO_ODR_OD10_Pos (10U) 2630 #define GPIO_ODR_OD10_Msk (0x1U << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */ 2631 #define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk 2632 #define GPIO_ODR_OD11_Pos (11U) 2633 #define GPIO_ODR_OD11_Msk (0x1U << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */ 2634 #define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk 2635 #define GPIO_ODR_OD12_Pos (12U) 2636 #define GPIO_ODR_OD12_Msk (0x1U << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */ 2637 #define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk 2638 #define GPIO_ODR_OD13_Pos (13U) 2639 #define GPIO_ODR_OD13_Msk (0x1U << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */ 2640 #define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk 2641 #define GPIO_ODR_OD14_Pos (14U) 2642 #define GPIO_ODR_OD14_Msk (0x1U << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */ 2643 #define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk 2644 #define GPIO_ODR_OD15_Pos (15U) 2645 #define GPIO_ODR_OD15_Msk (0x1U << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */ 2646 #define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk 2647 2648 /****************** Bit definition for GPIO_BSRR register ********************/ 2649 #define GPIO_BSRR_BS_0 (0x00000001U) 2650 #define GPIO_BSRR_BS_1 (0x00000002U) 2651 #define GPIO_BSRR_BS_2 (0x00000004U) 2652 #define GPIO_BSRR_BS_3 (0x00000008U) 2653 #define GPIO_BSRR_BS_4 (0x00000010U) 2654 #define GPIO_BSRR_BS_5 (0x00000020U) 2655 #define GPIO_BSRR_BS_6 (0x00000040U) 2656 #define GPIO_BSRR_BS_7 (0x00000080U) 2657 #define GPIO_BSRR_BS_8 (0x00000100U) 2658 #define GPIO_BSRR_BS_9 (0x00000200U) 2659 #define GPIO_BSRR_BS_10 (0x00000400U) 2660 #define GPIO_BSRR_BS_11 (0x00000800U) 2661 #define GPIO_BSRR_BS_12 (0x00001000U) 2662 #define GPIO_BSRR_BS_13 (0x00002000U) 2663 #define GPIO_BSRR_BS_14 (0x00004000U) 2664 #define GPIO_BSRR_BS_15 (0x00008000U) 2665 #define GPIO_BSRR_BR_0 (0x00010000U) 2666 #define GPIO_BSRR_BR_1 (0x00020000U) 2667 #define GPIO_BSRR_BR_2 (0x00040000U) 2668 #define GPIO_BSRR_BR_3 (0x00080000U) 2669 #define GPIO_BSRR_BR_4 (0x00100000U) 2670 #define GPIO_BSRR_BR_5 (0x00200000U) 2671 #define GPIO_BSRR_BR_6 (0x00400000U) 2672 #define GPIO_BSRR_BR_7 (0x00800000U) 2673 #define GPIO_BSRR_BR_8 (0x01000000U) 2674 #define GPIO_BSRR_BR_9 (0x02000000U) 2675 #define GPIO_BSRR_BR_10 (0x04000000U) 2676 #define GPIO_BSRR_BR_11 (0x08000000U) 2677 #define GPIO_BSRR_BR_12 (0x10000000U) 2678 #define GPIO_BSRR_BR_13 (0x20000000U) 2679 #define GPIO_BSRR_BR_14 (0x40000000U) 2680 #define GPIO_BSRR_BR_15 (0x80000000U) 2681 2682 /****************** Bit definition for GPIO_LCKR register ********************/ 2683 #define GPIO_LCKR_LCK0_Pos (0U) 2684 #define GPIO_LCKR_LCK0_Msk (0x1U << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */ 2685 #define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk 2686 #define GPIO_LCKR_LCK1_Pos (1U) 2687 #define GPIO_LCKR_LCK1_Msk (0x1U << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */ 2688 #define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk 2689 #define GPIO_LCKR_LCK2_Pos (2U) 2690 #define GPIO_LCKR_LCK2_Msk (0x1U << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */ 2691 #define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk 2692 #define GPIO_LCKR_LCK3_Pos (3U) 2693 #define GPIO_LCKR_LCK3_Msk (0x1U << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */ 2694 #define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk 2695 #define GPIO_LCKR_LCK4_Pos (4U) 2696 #define GPIO_LCKR_LCK4_Msk (0x1U << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */ 2697 #define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk 2698 #define GPIO_LCKR_LCK5_Pos (5U) 2699 #define GPIO_LCKR_LCK5_Msk (0x1U << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */ 2700 #define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk 2701 #define GPIO_LCKR_LCK6_Pos (6U) 2702 #define GPIO_LCKR_LCK6_Msk (0x1U << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */ 2703 #define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk 2704 #define GPIO_LCKR_LCK7_Pos (7U) 2705 #define GPIO_LCKR_LCK7_Msk (0x1U << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */ 2706 #define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk 2707 #define GPIO_LCKR_LCK8_Pos (8U) 2708 #define GPIO_LCKR_LCK8_Msk (0x1U << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */ 2709 #define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk 2710 #define GPIO_LCKR_LCK9_Pos (9U) 2711 #define GPIO_LCKR_LCK9_Msk (0x1U << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */ 2712 #define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk 2713 #define GPIO_LCKR_LCK10_Pos (10U) 2714 #define GPIO_LCKR_LCK10_Msk (0x1U << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */ 2715 #define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk 2716 #define GPIO_LCKR_LCK11_Pos (11U) 2717 #define GPIO_LCKR_LCK11_Msk (0x1U << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */ 2718 #define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk 2719 #define GPIO_LCKR_LCK12_Pos (12U) 2720 #define GPIO_LCKR_LCK12_Msk (0x1U << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */ 2721 #define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk 2722 #define GPIO_LCKR_LCK13_Pos (13U) 2723 #define GPIO_LCKR_LCK13_Msk (0x1U << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */ 2724 #define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk 2725 #define GPIO_LCKR_LCK14_Pos (14U) 2726 #define GPIO_LCKR_LCK14_Msk (0x1U << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */ 2727 #define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk 2728 #define GPIO_LCKR_LCK15_Pos (15U) 2729 #define GPIO_LCKR_LCK15_Msk (0x1U << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */ 2730 #define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk 2731 #define GPIO_LCKR_LCKK_Pos (16U) 2732 #define GPIO_LCKR_LCKK_Msk (0x1U << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */ 2733 #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk 2734 2735 /****************** Bit definition for GPIO_AFRL register ********************/ 2736 #define GPIO_AFRL_AFRL0_Pos (0U) 2737 #define GPIO_AFRL_AFRL0_Msk (0xFU << GPIO_AFRL_AFRL0_Pos) /*!< 0x0000000F */ 2738 #define GPIO_AFRL_AFRL0 GPIO_AFRL_AFRL0_Msk 2739 #define GPIO_AFRL_AFRL1_Pos (4U) 2740 #define GPIO_AFRL_AFRL1_Msk (0xFU << GPIO_AFRL_AFRL1_Pos) /*!< 0x000000F0 */ 2741 #define GPIO_AFRL_AFRL1 GPIO_AFRL_AFRL1_Msk 2742 #define GPIO_AFRL_AFRL2_Pos (8U) 2743 #define GPIO_AFRL_AFRL2_Msk (0xFU << GPIO_AFRL_AFRL2_Pos) /*!< 0x00000F00 */ 2744 #define GPIO_AFRL_AFRL2 GPIO_AFRL_AFRL2_Msk 2745 #define GPIO_AFRL_AFRL3_Pos (12U) 2746 #define GPIO_AFRL_AFRL3_Msk (0xFU << GPIO_AFRL_AFRL3_Pos) /*!< 0x0000F000 */ 2747 #define GPIO_AFRL_AFRL3 GPIO_AFRL_AFRL3_Msk 2748 #define GPIO_AFRL_AFRL4_Pos (16U) 2749 #define GPIO_AFRL_AFRL4_Msk (0xFU << GPIO_AFRL_AFRL4_Pos) /*!< 0x000F0000 */ 2750 #define GPIO_AFRL_AFRL4 GPIO_AFRL_AFRL4_Msk 2751 #define GPIO_AFRL_AFRL5_Pos (20U) 2752 #define GPIO_AFRL_AFRL5_Msk (0xFU << GPIO_AFRL_AFRL5_Pos) /*!< 0x00F00000 */ 2753 #define GPIO_AFRL_AFRL5 GPIO_AFRL_AFRL5_Msk 2754 #define GPIO_AFRL_AFRL6_Pos (24U) 2755 #define GPIO_AFRL_AFRL6_Msk (0xFU << GPIO_AFRL_AFRL6_Pos) /*!< 0x0F000000 */ 2756 #define GPIO_AFRL_AFRL6 GPIO_AFRL_AFRL6_Msk 2757 #define GPIO_AFRL_AFRL7_Pos (28U) 2758 #define GPIO_AFRL_AFRL7_Msk (0xFU << GPIO_AFRL_AFRL7_Pos) /*!< 0xF0000000 */ 2759 #define GPIO_AFRL_AFRL7 GPIO_AFRL_AFRL7_Msk 2760 2761 /****************** Bit definition for GPIO_AFRH register ********************/ 2762 #define GPIO_AFRH_AFRH0_Pos (0U) 2763 #define GPIO_AFRH_AFRH0_Msk (0xFU << GPIO_AFRH_AFRH0_Pos) /*!< 0x0000000F */ 2764 #define GPIO_AFRH_AFRH0 GPIO_AFRH_AFRH0_Msk 2765 #define GPIO_AFRH_AFRH1_Pos (4U) 2766 #define GPIO_AFRH_AFRH1_Msk (0xFU << GPIO_AFRH_AFRH1_Pos) /*!< 0x000000F0 */ 2767 #define GPIO_AFRH_AFRH1 GPIO_AFRH_AFRH1_Msk 2768 #define GPIO_AFRH_AFRH2_Pos (8U) 2769 #define GPIO_AFRH_AFRH2_Msk (0xFU << GPIO_AFRH_AFRH2_Pos) /*!< 0x00000F00 */ 2770 #define GPIO_AFRH_AFRH2 GPIO_AFRH_AFRH2_Msk 2771 #define GPIO_AFRH_AFRH3_Pos (12U) 2772 #define GPIO_AFRH_AFRH3_Msk (0xFU << GPIO_AFRH_AFRH3_Pos) /*!< 0x0000F000 */ 2773 #define GPIO_AFRH_AFRH3 GPIO_AFRH_AFRH3_Msk 2774 #define GPIO_AFRH_AFRH4_Pos (16U) 2775 #define GPIO_AFRH_AFRH4_Msk (0xFU << GPIO_AFRH_AFRH4_Pos) /*!< 0x000F0000 */ 2776 #define GPIO_AFRH_AFRH4 GPIO_AFRH_AFRH4_Msk 2777 #define GPIO_AFRH_AFRH5_Pos (20U) 2778 #define GPIO_AFRH_AFRH5_Msk (0xFU << GPIO_AFRH_AFRH5_Pos) /*!< 0x00F00000 */ 2779 #define GPIO_AFRH_AFRH5 GPIO_AFRH_AFRH5_Msk 2780 #define GPIO_AFRH_AFRH6_Pos (24U) 2781 #define GPIO_AFRH_AFRH6_Msk (0xFU << GPIO_AFRH_AFRH6_Pos) /*!< 0x0F000000 */ 2782 #define GPIO_AFRH_AFRH6 GPIO_AFRH_AFRH6_Msk 2783 #define GPIO_AFRH_AFRH7_Pos (28U) 2784 #define GPIO_AFRH_AFRH7_Msk (0xFU << GPIO_AFRH_AFRH7_Pos) /*!< 0xF0000000 */ 2785 #define GPIO_AFRH_AFRH7 GPIO_AFRH_AFRH7_Msk 2786 2787 /****************** Bit definition for GPIO_BRR register *********************/ 2788 #define GPIO_BRR_BR_0 (0x00000001U) 2789 #define GPIO_BRR_BR_1 (0x00000002U) 2790 #define GPIO_BRR_BR_2 (0x00000004U) 2791 #define GPIO_BRR_BR_3 (0x00000008U) 2792 #define GPIO_BRR_BR_4 (0x00000010U) 2793 #define GPIO_BRR_BR_5 (0x00000020U) 2794 #define GPIO_BRR_BR_6 (0x00000040U) 2795 #define GPIO_BRR_BR_7 (0x00000080U) 2796 #define GPIO_BRR_BR_8 (0x00000100U) 2797 #define GPIO_BRR_BR_9 (0x00000200U) 2798 #define GPIO_BRR_BR_10 (0x00000400U) 2799 #define GPIO_BRR_BR_11 (0x00000800U) 2800 #define GPIO_BRR_BR_12 (0x00001000U) 2801 #define GPIO_BRR_BR_13 (0x00002000U) 2802 #define GPIO_BRR_BR_14 (0x00004000U) 2803 #define GPIO_BRR_BR_15 (0x00008000U) 2804 2805 /******************************************************************************/ 2806 /* */ 2807 /* Inter-integrated Circuit Interface (I2C) */ 2808 /* */ 2809 /******************************************************************************/ 2810 2811 /******************* Bit definition for I2C_CR1 register *******************/ 2812 #define I2C_CR1_PE_Pos (0U) 2813 #define I2C_CR1_PE_Msk (0x1U << I2C_CR1_PE_Pos) /*!< 0x00000001 */ 2814 #define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral enable */ 2815 #define I2C_CR1_TXIE_Pos (1U) 2816 #define I2C_CR1_TXIE_Msk (0x1U << I2C_CR1_TXIE_Pos) /*!< 0x00000002 */ 2817 #define I2C_CR1_TXIE I2C_CR1_TXIE_Msk /*!< TX interrupt enable */ 2818 #define I2C_CR1_RXIE_Pos (2U) 2819 #define I2C_CR1_RXIE_Msk (0x1U << I2C_CR1_RXIE_Pos) /*!< 0x00000004 */ 2820 #define I2C_CR1_RXIE I2C_CR1_RXIE_Msk /*!< RX interrupt enable */ 2821 #define I2C_CR1_ADDRIE_Pos (3U) 2822 #define I2C_CR1_ADDRIE_Msk (0x1U << I2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */ 2823 #define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */ 2824 #define I2C_CR1_NACKIE_Pos (4U) 2825 #define I2C_CR1_NACKIE_Msk (0x1U << I2C_CR1_NACKIE_Pos) /*!< 0x00000010 */ 2826 #define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */ 2827 #define I2C_CR1_STOPIE_Pos (5U) 2828 #define I2C_CR1_STOPIE_Msk (0x1U << I2C_CR1_STOPIE_Pos) /*!< 0x00000020 */ 2829 #define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */ 2830 #define I2C_CR1_TCIE_Pos (6U) 2831 #define I2C_CR1_TCIE_Msk (0x1U << I2C_CR1_TCIE_Pos) /*!< 0x00000040 */ 2832 #define I2C_CR1_TCIE I2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */ 2833 #define I2C_CR1_ERRIE_Pos (7U) 2834 #define I2C_CR1_ERRIE_Msk (0x1U << I2C_CR1_ERRIE_Pos) /*!< 0x00000080 */ 2835 #define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */ 2836 #define I2C_CR1_DNF_Pos (8U) 2837 #define I2C_CR1_DNF_Msk (0xFU << I2C_CR1_DNF_Pos) /*!< 0x00000F00 */ 2838 #define I2C_CR1_DNF I2C_CR1_DNF_Msk /*!< Digital noise filter */ 2839 #define I2C_CR1_ANFOFF_Pos (12U) 2840 #define I2C_CR1_ANFOFF_Msk (0x1U << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */ 2841 #define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */ 2842 #define I2C_CR1_TXDMAEN_Pos (14U) 2843 #define I2C_CR1_TXDMAEN_Msk (0x1U << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */ 2844 #define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */ 2845 #define I2C_CR1_RXDMAEN_Pos (15U) 2846 #define I2C_CR1_RXDMAEN_Msk (0x1U << I2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */ 2847 #define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */ 2848 #define I2C_CR1_SBC_Pos (16U) 2849 #define I2C_CR1_SBC_Msk (0x1U << I2C_CR1_SBC_Pos) /*!< 0x00010000 */ 2850 #define I2C_CR1_SBC I2C_CR1_SBC_Msk /*!< Slave byte control */ 2851 #define I2C_CR1_NOSTRETCH_Pos (17U) 2852 #define I2C_CR1_NOSTRETCH_Msk (0x1U << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */ 2853 #define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */ 2854 #define I2C_CR1_WUPEN_Pos (18U) 2855 #define I2C_CR1_WUPEN_Msk (0x1U << I2C_CR1_WUPEN_Pos) /*!< 0x00040000 */ 2856 #define I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk /*!< Wakeup from STOP enable */ 2857 #define I2C_CR1_GCEN_Pos (19U) 2858 #define I2C_CR1_GCEN_Msk (0x1U << I2C_CR1_GCEN_Pos) /*!< 0x00080000 */ 2859 #define I2C_CR1_GCEN I2C_CR1_GCEN_Msk /*!< General call enable */ 2860 #define I2C_CR1_SMBHEN_Pos (20U) 2861 #define I2C_CR1_SMBHEN_Msk (0x1U << I2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */ 2862 #define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */ 2863 #define I2C_CR1_SMBDEN_Pos (21U) 2864 #define I2C_CR1_SMBDEN_Msk (0x1U << I2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */ 2865 #define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */ 2866 #define I2C_CR1_ALERTEN_Pos (22U) 2867 #define I2C_CR1_ALERTEN_Msk (0x1U << I2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */ 2868 #define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */ 2869 #define I2C_CR1_PECEN_Pos (23U) 2870 #define I2C_CR1_PECEN_Msk (0x1U << I2C_CR1_PECEN_Pos) /*!< 0x00800000 */ 2871 #define I2C_CR1_PECEN I2C_CR1_PECEN_Msk /*!< PEC enable */ 2872 2873 /****************** Bit definition for I2C_CR2 register ********************/ 2874 #define I2C_CR2_SADD_Pos (0U) 2875 #define I2C_CR2_SADD_Msk (0x3FFU << I2C_CR2_SADD_Pos) /*!< 0x000003FF */ 2876 #define I2C_CR2_SADD I2C_CR2_SADD_Msk /*!< Slave address (master mode) */ 2877 #define I2C_CR2_RD_WRN_Pos (10U) 2878 #define I2C_CR2_RD_WRN_Msk (0x1U << I2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */ 2879 #define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */ 2880 #define I2C_CR2_ADD10_Pos (11U) 2881 #define I2C_CR2_ADD10_Msk (0x1U << I2C_CR2_ADD10_Pos) /*!< 0x00000800 */ 2882 #define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */ 2883 #define I2C_CR2_HEAD10R_Pos (12U) 2884 #define I2C_CR2_HEAD10R_Msk (0x1U << I2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */ 2885 #define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */ 2886 #define I2C_CR2_START_Pos (13U) 2887 #define I2C_CR2_START_Msk (0x1U << I2C_CR2_START_Pos) /*!< 0x00002000 */ 2888 #define I2C_CR2_START I2C_CR2_START_Msk /*!< START generation */ 2889 #define I2C_CR2_STOP_Pos (14U) 2890 #define I2C_CR2_STOP_Msk (0x1U << I2C_CR2_STOP_Pos) /*!< 0x00004000 */ 2891 #define I2C_CR2_STOP I2C_CR2_STOP_Msk /*!< STOP generation (master mode) */ 2892 #define I2C_CR2_NACK_Pos (15U) 2893 #define I2C_CR2_NACK_Msk (0x1U << I2C_CR2_NACK_Pos) /*!< 0x00008000 */ 2894 #define I2C_CR2_NACK I2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */ 2895 #define I2C_CR2_NBYTES_Pos (16U) 2896 #define I2C_CR2_NBYTES_Msk (0xFFU << I2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */ 2897 #define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk /*!< Number of bytes */ 2898 #define I2C_CR2_RELOAD_Pos (24U) 2899 #define I2C_CR2_RELOAD_Msk (0x1U << I2C_CR2_RELOAD_Pos) /*!< 0x01000000 */ 2900 #define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */ 2901 #define I2C_CR2_AUTOEND_Pos (25U) 2902 #define I2C_CR2_AUTOEND_Msk (0x1U << I2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */ 2903 #define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */ 2904 #define I2C_CR2_PECBYTE_Pos (26U) 2905 #define I2C_CR2_PECBYTE_Msk (0x1U << I2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */ 2906 #define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */ 2907 2908 /******************* Bit definition for I2C_OAR1 register ******************/ 2909 #define I2C_OAR1_OA1_Pos (0U) 2910 #define I2C_OAR1_OA1_Msk (0x3FFU << I2C_OAR1_OA1_Pos) /*!< 0x000003FF */ 2911 #define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk /*!< Interface own address 1 */ 2912 #define I2C_OAR1_OA1MODE_Pos (10U) 2913 #define I2C_OAR1_OA1MODE_Msk (0x1U << I2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */ 2914 #define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */ 2915 #define I2C_OAR1_OA1EN_Pos (15U) 2916 #define I2C_OAR1_OA1EN_Msk (0x1U << I2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */ 2917 #define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */ 2918 2919 /******************* Bit definition for I2C_OAR2 register ******************/ 2920 #define I2C_OAR2_OA2_Pos (1U) 2921 #define I2C_OAR2_OA2_Msk (0x7FU << I2C_OAR2_OA2_Pos) /*!< 0x000000FE */ 2922 #define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk /*!< Interface own address 2 */ 2923 #define I2C_OAR2_OA2MSK_Pos (8U) 2924 #define I2C_OAR2_OA2MSK_Msk (0x7U << I2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */ 2925 #define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */ 2926 #define I2C_OAR2_OA2NOMASK (0x00000000U) /*!< No mask */ 2927 #define I2C_OAR2_OA2MASK01_Pos (8U) 2928 #define I2C_OAR2_OA2MASK01_Msk (0x1U << I2C_OAR2_OA2MASK01_Pos) /*!< 0x00000100 */ 2929 #define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk /*!< OA2[1] is masked, Only OA2[7:2] are compared */ 2930 #define I2C_OAR2_OA2MASK02_Pos (9U) 2931 #define I2C_OAR2_OA2MASK02_Msk (0x1U << I2C_OAR2_OA2MASK02_Pos) /*!< 0x00000200 */ 2932 #define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */ 2933 #define I2C_OAR2_OA2MASK03_Pos (8U) 2934 #define I2C_OAR2_OA2MASK03_Msk (0x3U << I2C_OAR2_OA2MASK03_Pos) /*!< 0x00000300 */ 2935 #define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */ 2936 #define I2C_OAR2_OA2MASK04_Pos (10U) 2937 #define I2C_OAR2_OA2MASK04_Msk (0x1U << I2C_OAR2_OA2MASK04_Pos) /*!< 0x00000400 */ 2938 #define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */ 2939 #define I2C_OAR2_OA2MASK05_Pos (8U) 2940 #define I2C_OAR2_OA2MASK05_Msk (0x5U << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */ 2941 #define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */ 2942 #define I2C_OAR2_OA2MASK06_Pos (9U) 2943 #define I2C_OAR2_OA2MASK06_Msk (0x3U << I2C_OAR2_OA2MASK06_Pos) /*!< 0x00000600 */ 2944 #define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk /*!< OA2[6:1] is masked, Only OA2[7] are compared */ 2945 #define I2C_OAR2_OA2MASK07_Pos (8U) 2946 #define I2C_OAR2_OA2MASK07_Msk (0x7U << I2C_OAR2_OA2MASK07_Pos) /*!< 0x00000700 */ 2947 #define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk /*!< OA2[7:1] is masked, No comparison is done */ 2948 #define I2C_OAR2_OA2EN_Pos (15U) 2949 #define I2C_OAR2_OA2EN_Msk (0x1U << I2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */ 2950 #define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */ 2951 2952 /******************* Bit definition for I2C_TIMINGR register *******************/ 2953 #define I2C_TIMINGR_SCLL_Pos (0U) 2954 #define I2C_TIMINGR_SCLL_Msk (0xFFU << I2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */ 2955 #define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */ 2956 #define I2C_TIMINGR_SCLH_Pos (8U) 2957 #define I2C_TIMINGR_SCLH_Msk (0xFFU << I2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */ 2958 #define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */ 2959 #define I2C_TIMINGR_SDADEL_Pos (16U) 2960 #define I2C_TIMINGR_SDADEL_Msk (0xFU << I2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */ 2961 #define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk /*!< Data hold time */ 2962 #define I2C_TIMINGR_SCLDEL_Pos (20U) 2963 #define I2C_TIMINGR_SCLDEL_Msk (0xFU << I2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */ 2964 #define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */ 2965 #define I2C_TIMINGR_PRESC_Pos (28U) 2966 #define I2C_TIMINGR_PRESC_Msk (0xFU << I2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */ 2967 #define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */ 2968 2969 /******************* Bit definition for I2C_TIMEOUTR register *******************/ 2970 #define I2C_TIMEOUTR_TIMEOUTA_Pos (0U) 2971 #define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFU << I2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */ 2972 #define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */ 2973 #define I2C_TIMEOUTR_TIDLE_Pos (12U) 2974 #define I2C_TIMEOUTR_TIDLE_Msk (0x1U << I2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */ 2975 #define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */ 2976 #define I2C_TIMEOUTR_TIMOUTEN_Pos (15U) 2977 #define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1U << I2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */ 2978 #define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */ 2979 #define I2C_TIMEOUTR_TIMEOUTB_Pos (16U) 2980 #define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFU << I2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */ 2981 #define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B*/ 2982 #define I2C_TIMEOUTR_TEXTEN_Pos (31U) 2983 #define I2C_TIMEOUTR_TEXTEN_Msk (0x1U << I2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */ 2984 #define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */ 2985 2986 /****************** Bit definition for I2C_ISR register *********************/ 2987 #define I2C_ISR_TXE_Pos (0U) 2988 #define I2C_ISR_TXE_Msk (0x1U << I2C_ISR_TXE_Pos) /*!< 0x00000001 */ 2989 #define I2C_ISR_TXE I2C_ISR_TXE_Msk /*!< Transmit data register empty */ 2990 #define I2C_ISR_TXIS_Pos (1U) 2991 #define I2C_ISR_TXIS_Msk (0x1U << I2C_ISR_TXIS_Pos) /*!< 0x00000002 */ 2992 #define I2C_ISR_TXIS I2C_ISR_TXIS_Msk /*!< Transmit interrupt status */ 2993 #define I2C_ISR_RXNE_Pos (2U) 2994 #define I2C_ISR_RXNE_Msk (0x1U << I2C_ISR_RXNE_Pos) /*!< 0x00000004 */ 2995 #define I2C_ISR_RXNE I2C_ISR_RXNE_Msk /*!< Receive data register not empty */ 2996 #define I2C_ISR_ADDR_Pos (3U) 2997 #define I2C_ISR_ADDR_Msk (0x1U << I2C_ISR_ADDR_Pos) /*!< 0x00000008 */ 2998 #define I2C_ISR_ADDR I2C_ISR_ADDR_Msk /*!< Address matched (slave mode)*/ 2999 #define I2C_ISR_NACKF_Pos (4U) 3000 #define I2C_ISR_NACKF_Msk (0x1U << I2C_ISR_NACKF_Pos) /*!< 0x00000010 */ 3001 #define I2C_ISR_NACKF I2C_ISR_NACKF_Msk /*!< NACK received flag */ 3002 #define I2C_ISR_STOPF_Pos (5U) 3003 #define I2C_ISR_STOPF_Msk (0x1U << I2C_ISR_STOPF_Pos) /*!< 0x00000020 */ 3004 #define I2C_ISR_STOPF I2C_ISR_STOPF_Msk /*!< STOP detection flag */ 3005 #define I2C_ISR_TC_Pos (6U) 3006 #define I2C_ISR_TC_Msk (0x1U << I2C_ISR_TC_Pos) /*!< 0x00000040 */ 3007 #define I2C_ISR_TC I2C_ISR_TC_Msk /*!< Transfer complete (master mode) */ 3008 #define I2C_ISR_TCR_Pos (7U) 3009 #define I2C_ISR_TCR_Msk (0x1U << I2C_ISR_TCR_Pos) /*!< 0x00000080 */ 3010 #define I2C_ISR_TCR I2C_ISR_TCR_Msk /*!< Transfer complete reload */ 3011 #define I2C_ISR_BERR_Pos (8U) 3012 #define I2C_ISR_BERR_Msk (0x1U << I2C_ISR_BERR_Pos) /*!< 0x00000100 */ 3013 #define I2C_ISR_BERR I2C_ISR_BERR_Msk /*!< Bus error */ 3014 #define I2C_ISR_ARLO_Pos (9U) 3015 #define I2C_ISR_ARLO_Msk (0x1U << I2C_ISR_ARLO_Pos) /*!< 0x00000200 */ 3016 #define I2C_ISR_ARLO I2C_ISR_ARLO_Msk /*!< Arbitration lost */ 3017 #define I2C_ISR_OVR_Pos (10U) 3018 #define I2C_ISR_OVR_Msk (0x1U << I2C_ISR_OVR_Pos) /*!< 0x00000400 */ 3019 #define I2C_ISR_OVR I2C_ISR_OVR_Msk /*!< Overrun/Underrun */ 3020 #define I2C_ISR_PECERR_Pos (11U) 3021 #define I2C_ISR_PECERR_Msk (0x1U << I2C_ISR_PECERR_Pos) /*!< 0x00000800 */ 3022 #define I2C_ISR_PECERR I2C_ISR_PECERR_Msk /*!< PEC error in reception */ 3023 #define I2C_ISR_TIMEOUT_Pos (12U) 3024 #define I2C_ISR_TIMEOUT_Msk (0x1U << I2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */ 3025 #define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */ 3026 #define I2C_ISR_ALERT_Pos (13U) 3027 #define I2C_ISR_ALERT_Msk (0x1U << I2C_ISR_ALERT_Pos) /*!< 0x00002000 */ 3028 #define I2C_ISR_ALERT I2C_ISR_ALERT_Msk /*!< SMBus alert */ 3029 #define I2C_ISR_BUSY_Pos (15U) 3030 #define I2C_ISR_BUSY_Msk (0x1U << I2C_ISR_BUSY_Pos) /*!< 0x00008000 */ 3031 #define I2C_ISR_BUSY I2C_ISR_BUSY_Msk /*!< Bus busy */ 3032 #define I2C_ISR_DIR_Pos (16U) 3033 #define I2C_ISR_DIR_Msk (0x1U << I2C_ISR_DIR_Pos) /*!< 0x00010000 */ 3034 #define I2C_ISR_DIR I2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */ 3035 #define I2C_ISR_ADDCODE_Pos (17U) 3036 #define I2C_ISR_ADDCODE_Msk (0x7FU << I2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */ 3037 #define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */ 3038 3039 /****************** Bit definition for I2C_ICR register *********************/ 3040 #define I2C_ICR_ADDRCF_Pos (3U) 3041 #define I2C_ICR_ADDRCF_Msk (0x1U << I2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */ 3042 #define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */ 3043 #define I2C_ICR_NACKCF_Pos (4U) 3044 #define I2C_ICR_NACKCF_Msk (0x1U << I2C_ICR_NACKCF_Pos) /*!< 0x00000010 */ 3045 #define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk /*!< NACK clear flag */ 3046 #define I2C_ICR_STOPCF_Pos (5U) 3047 #define I2C_ICR_STOPCF_Msk (0x1U << I2C_ICR_STOPCF_Pos) /*!< 0x00000020 */ 3048 #define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */ 3049 #define I2C_ICR_BERRCF_Pos (8U) 3050 #define I2C_ICR_BERRCF_Msk (0x1U << I2C_ICR_BERRCF_Pos) /*!< 0x00000100 */ 3051 #define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk /*!< Bus error clear flag */ 3052 #define I2C_ICR_ARLOCF_Pos (9U) 3053 #define I2C_ICR_ARLOCF_Msk (0x1U << I2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */ 3054 #define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */ 3055 #define I2C_ICR_OVRCF_Pos (10U) 3056 #define I2C_ICR_OVRCF_Msk (0x1U << I2C_ICR_OVRCF_Pos) /*!< 0x00000400 */ 3057 #define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */ 3058 #define I2C_ICR_PECCF_Pos (11U) 3059 #define I2C_ICR_PECCF_Msk (0x1U << I2C_ICR_PECCF_Pos) /*!< 0x00000800 */ 3060 #define I2C_ICR_PECCF I2C_ICR_PECCF_Msk /*!< PAC error clear flag */ 3061 #define I2C_ICR_TIMOUTCF_Pos (12U) 3062 #define I2C_ICR_TIMOUTCF_Msk (0x1U << I2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */ 3063 #define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */ 3064 #define I2C_ICR_ALERTCF_Pos (13U) 3065 #define I2C_ICR_ALERTCF_Msk (0x1U << I2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */ 3066 #define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk /*!< Alert clear flag */ 3067 3068 /****************** Bit definition for I2C_PECR register *********************/ 3069 #define I2C_PECR_PEC_Pos (0U) 3070 #define I2C_PECR_PEC_Msk (0xFFU << I2C_PECR_PEC_Pos) /*!< 0x000000FF */ 3071 #define I2C_PECR_PEC I2C_PECR_PEC_Msk /*!< PEC register */ 3072 3073 /****************** Bit definition for I2C_RXDR register *********************/ 3074 #define I2C_RXDR_RXDATA_Pos (0U) 3075 #define I2C_RXDR_RXDATA_Msk (0xFFU << I2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */ 3076 #define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */ 3077 3078 /****************** Bit definition for I2C_TXDR register *********************/ 3079 #define I2C_TXDR_TXDATA_Pos (0U) 3080 #define I2C_TXDR_TXDATA_Msk (0xFFU << I2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */ 3081 #define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */ 3082 3083 /******************************************************************************/ 3084 /* */ 3085 /* Independent WATCHDOG (IWDG) */ 3086 /* */ 3087 /******************************************************************************/ 3088 /******************* Bit definition for IWDG_KR register ********************/ 3089 #define IWDG_KR_KEY_Pos (0U) 3090 #define IWDG_KR_KEY_Msk (0xFFFFU << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */ 3091 #define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!< Key value (write only, read 0000h) */ 3092 3093 /******************* Bit definition for IWDG_PR register ********************/ 3094 #define IWDG_PR_PR_Pos (0U) 3095 #define IWDG_PR_PR_Msk (0x7U << IWDG_PR_PR_Pos) /*!< 0x00000007 */ 3096 #define IWDG_PR_PR IWDG_PR_PR_Msk /*!< PR[2:0] (Prescaler divider) */ 3097 #define IWDG_PR_PR_0 (0x1U << IWDG_PR_PR_Pos) /*!< 0x00000001 */ 3098 #define IWDG_PR_PR_1 (0x2U << IWDG_PR_PR_Pos) /*!< 0x00000002 */ 3099 #define IWDG_PR_PR_2 (0x4U << IWDG_PR_PR_Pos) /*!< 0x00000004 */ 3100 3101 /******************* Bit definition for IWDG_RLR register *******************/ 3102 #define IWDG_RLR_RL_Pos (0U) 3103 #define IWDG_RLR_RL_Msk (0xFFFU << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */ 3104 #define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!< Watchdog counter reload value */ 3105 3106 /******************* Bit definition for IWDG_SR register ********************/ 3107 #define IWDG_SR_PVU_Pos (0U) 3108 #define IWDG_SR_PVU_Msk (0x1U << IWDG_SR_PVU_Pos) /*!< 0x00000001 */ 3109 #define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */ 3110 #define IWDG_SR_RVU_Pos (1U) 3111 #define IWDG_SR_RVU_Msk (0x1U << IWDG_SR_RVU_Pos) /*!< 0x00000002 */ 3112 #define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */ 3113 #define IWDG_SR_WVU_Pos (2U) 3114 #define IWDG_SR_WVU_Msk (0x1U << IWDG_SR_WVU_Pos) /*!< 0x00000004 */ 3115 #define IWDG_SR_WVU IWDG_SR_WVU_Msk /*!< Watchdog counter window value update */ 3116 3117 /******************* Bit definition for IWDG_KR register ********************/ 3118 #define IWDG_WINR_WIN_Pos (0U) 3119 #define IWDG_WINR_WIN_Msk (0xFFFU << IWDG_WINR_WIN_Pos) /*!< 0x00000FFF */ 3120 #define IWDG_WINR_WIN IWDG_WINR_WIN_Msk /*!< Watchdog counter window value */ 3121 3122 /******************************************************************************/ 3123 /* */ 3124 /* Low Power Timer (LPTTIM) */ 3125 /* */ 3126 /******************************************************************************/ 3127 /****************** Bit definition for LPTIM_ISR register *******************/ 3128 #define LPTIM_ISR_CMPM_Pos (0U) 3129 #define LPTIM_ISR_CMPM_Msk (0x1U << LPTIM_ISR_CMPM_Pos) /*!< 0x00000001 */ 3130 #define LPTIM_ISR_CMPM LPTIM_ISR_CMPM_Msk /*!< Compare match */ 3131 #define LPTIM_ISR_ARRM_Pos (1U) 3132 #define LPTIM_ISR_ARRM_Msk (0x1U << LPTIM_ISR_ARRM_Pos) /*!< 0x00000002 */ 3133 #define LPTIM_ISR_ARRM LPTIM_ISR_ARRM_Msk /*!< Autoreload match */ 3134 #define LPTIM_ISR_EXTTRIG_Pos (2U) 3135 #define LPTIM_ISR_EXTTRIG_Msk (0x1U << LPTIM_ISR_EXTTRIG_Pos) /*!< 0x00000004 */ 3136 #define LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG_Msk /*!< External trigger edge event */ 3137 #define LPTIM_ISR_CMPOK_Pos (3U) 3138 #define LPTIM_ISR_CMPOK_Msk (0x1U << LPTIM_ISR_CMPOK_Pos) /*!< 0x00000008 */ 3139 #define LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK_Msk /*!< Compare register update OK */ 3140 #define LPTIM_ISR_ARROK_Pos (4U) 3141 #define LPTIM_ISR_ARROK_Msk (0x1U << LPTIM_ISR_ARROK_Pos) /*!< 0x00000010 */ 3142 #define LPTIM_ISR_ARROK LPTIM_ISR_ARROK_Msk /*!< Autoreload register update OK */ 3143 #define LPTIM_ISR_UP_Pos (5U) 3144 #define LPTIM_ISR_UP_Msk (0x1U << LPTIM_ISR_UP_Pos) /*!< 0x00000020 */ 3145 #define LPTIM_ISR_UP LPTIM_ISR_UP_Msk /*!< Counter direction change down to up */ 3146 #define LPTIM_ISR_DOWN_Pos (6U) 3147 #define LPTIM_ISR_DOWN_Msk (0x1U << LPTIM_ISR_DOWN_Pos) /*!< 0x00000040 */ 3148 #define LPTIM_ISR_DOWN LPTIM_ISR_DOWN_Msk /*!< Counter direction change up to down */ 3149 3150 /****************** Bit definition for LPTIM_ICR register *******************/ 3151 #define LPTIM_ICR_CMPMCF_Pos (0U) 3152 #define LPTIM_ICR_CMPMCF_Msk (0x1U << LPTIM_ICR_CMPMCF_Pos) /*!< 0x00000001 */ 3153 #define LPTIM_ICR_CMPMCF LPTIM_ICR_CMPMCF_Msk /*!< Compare match Clear Flag */ 3154 #define LPTIM_ICR_ARRMCF_Pos (1U) 3155 #define LPTIM_ICR_ARRMCF_Msk (0x1U << LPTIM_ICR_ARRMCF_Pos) /*!< 0x00000002 */ 3156 #define LPTIM_ICR_ARRMCF LPTIM_ICR_ARRMCF_Msk /*!< Autoreload match Clear Flag */ 3157 #define LPTIM_ICR_EXTTRIGCF_Pos (2U) 3158 #define LPTIM_ICR_EXTTRIGCF_Msk (0x1U << LPTIM_ICR_EXTTRIGCF_Pos) /*!< 0x00000004 */ 3159 #define LPTIM_ICR_EXTTRIGCF LPTIM_ICR_EXTTRIGCF_Msk /*!< External trigger edge event Clear Flag */ 3160 #define LPTIM_ICR_CMPOKCF_Pos (3U) 3161 #define LPTIM_ICR_CMPOKCF_Msk (0x1U << LPTIM_ICR_CMPOKCF_Pos) /*!< 0x00000008 */ 3162 #define LPTIM_ICR_CMPOKCF LPTIM_ICR_CMPOKCF_Msk /*!< Compare register update OK Clear Flag */ 3163 #define LPTIM_ICR_ARROKCF_Pos (4U) 3164 #define LPTIM_ICR_ARROKCF_Msk (0x1U << LPTIM_ICR_ARROKCF_Pos) /*!< 0x00000010 */ 3165 #define LPTIM_ICR_ARROKCF LPTIM_ICR_ARROKCF_Msk /*!< Autoreload register update OK Clear Flag */ 3166 #define LPTIM_ICR_UPCF_Pos (5U) 3167 #define LPTIM_ICR_UPCF_Msk (0x1U << LPTIM_ICR_UPCF_Pos) /*!< 0x00000020 */ 3168 #define LPTIM_ICR_UPCF LPTIM_ICR_UPCF_Msk /*!< Counter direction change down to up Clear Flag */ 3169 #define LPTIM_ICR_DOWNCF_Pos (6U) 3170 #define LPTIM_ICR_DOWNCF_Msk (0x1U << LPTIM_ICR_DOWNCF_Pos) /*!< 0x00000040 */ 3171 #define LPTIM_ICR_DOWNCF LPTIM_ICR_DOWNCF_Msk /*!< Counter direction change up to down Clear Flag */ 3172 3173 /****************** Bit definition for LPTIM_IER register ********************/ 3174 #define LPTIM_IER_CMPMIE_Pos (0U) 3175 #define LPTIM_IER_CMPMIE_Msk (0x1U << LPTIM_IER_CMPMIE_Pos) /*!< 0x00000001 */ 3176 #define LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE_Msk /*!< Compare match Interrupt Enable */ 3177 #define LPTIM_IER_ARRMIE_Pos (1U) 3178 #define LPTIM_IER_ARRMIE_Msk (0x1U << LPTIM_IER_ARRMIE_Pos) /*!< 0x00000002 */ 3179 #define LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE_Msk /*!< Autoreload match Interrupt Enable */ 3180 #define LPTIM_IER_EXTTRIGIE_Pos (2U) 3181 #define LPTIM_IER_EXTTRIGIE_Msk (0x1U << LPTIM_IER_EXTTRIGIE_Pos) /*!< 0x00000004 */ 3182 #define LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE_Msk /*!< External trigger edge event Interrupt Enable */ 3183 #define LPTIM_IER_CMPOKIE_Pos (3U) 3184 #define LPTIM_IER_CMPOKIE_Msk (0x1U << LPTIM_IER_CMPOKIE_Pos) /*!< 0x00000008 */ 3185 #define LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE_Msk /*!< Compare register update OK Interrupt Enable */ 3186 #define LPTIM_IER_ARROKIE_Pos (4U) 3187 #define LPTIM_IER_ARROKIE_Msk (0x1U << LPTIM_IER_ARROKIE_Pos) /*!< 0x00000010 */ 3188 #define LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE_Msk /*!< Autoreload register update OK Interrupt Enable */ 3189 #define LPTIM_IER_UPIE_Pos (5U) 3190 #define LPTIM_IER_UPIE_Msk (0x1U << LPTIM_IER_UPIE_Pos) /*!< 0x00000020 */ 3191 #define LPTIM_IER_UPIE LPTIM_IER_UPIE_Msk /*!< Counter direction change down to up Interrupt Enable */ 3192 #define LPTIM_IER_DOWNIE_Pos (6U) 3193 #define LPTIM_IER_DOWNIE_Msk (0x1U << LPTIM_IER_DOWNIE_Pos) /*!< 0x00000040 */ 3194 #define LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE_Msk /*!< Counter direction change up to down Interrupt Enable */ 3195 3196 /****************** Bit definition for LPTIM_CFGR register *******************/ 3197 #define LPTIM_CFGR_CKSEL_Pos (0U) 3198 #define LPTIM_CFGR_CKSEL_Msk (0x1U << LPTIM_CFGR_CKSEL_Pos) /*!< 0x00000001 */ 3199 #define LPTIM_CFGR_CKSEL LPTIM_CFGR_CKSEL_Msk /*!< Clock selector */ 3200 3201 #define LPTIM_CFGR_CKPOL_Pos (1U) 3202 #define LPTIM_CFGR_CKPOL_Msk (0x3U << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000006 */ 3203 #define LPTIM_CFGR_CKPOL LPTIM_CFGR_CKPOL_Msk /*!< CKPOL[1:0] bits (Clock polarity) */ 3204 #define LPTIM_CFGR_CKPOL_0 (0x1U << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000002 */ 3205 #define LPTIM_CFGR_CKPOL_1 (0x2U << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000004 */ 3206 3207 #define LPTIM_CFGR_CKFLT_Pos (3U) 3208 #define LPTIM_CFGR_CKFLT_Msk (0x3U << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000018 */ 3209 #define LPTIM_CFGR_CKFLT LPTIM_CFGR_CKFLT_Msk /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */ 3210 #define LPTIM_CFGR_CKFLT_0 (0x1U << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000008 */ 3211 #define LPTIM_CFGR_CKFLT_1 (0x2U << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000010 */ 3212 3213 #define LPTIM_CFGR_TRGFLT_Pos (6U) 3214 #define LPTIM_CFGR_TRGFLT_Msk (0x3U << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x000000C0 */ 3215 #define LPTIM_CFGR_TRGFLT LPTIM_CFGR_TRGFLT_Msk /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */ 3216 #define LPTIM_CFGR_TRGFLT_0 (0x1U << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000040 */ 3217 #define LPTIM_CFGR_TRGFLT_1 (0x2U << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000080 */ 3218 3219 #define LPTIM_CFGR_PRESC_Pos (9U) 3220 #define LPTIM_CFGR_PRESC_Msk (0x7U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000E00 */ 3221 #define LPTIM_CFGR_PRESC LPTIM_CFGR_PRESC_Msk /*!< PRESC[2:0] bits (Clock prescaler) */ 3222 #define LPTIM_CFGR_PRESC_0 (0x1U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000200 */ 3223 #define LPTIM_CFGR_PRESC_1 (0x2U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000400 */ 3224 #define LPTIM_CFGR_PRESC_2 (0x4U << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000800 */ 3225 3226 #define LPTIM_CFGR_TRIGSEL_Pos (13U) 3227 #define LPTIM_CFGR_TRIGSEL_Msk (0x7U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x0000E000 */ 3228 #define LPTIM_CFGR_TRIGSEL LPTIM_CFGR_TRIGSEL_Msk /*!< TRIGSEL[2:0]] bits (Trigger selector) */ 3229 #define LPTIM_CFGR_TRIGSEL_0 (0x1U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00002000 */ 3230 #define LPTIM_CFGR_TRIGSEL_1 (0x2U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00004000 */ 3231 #define LPTIM_CFGR_TRIGSEL_2 (0x4U << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00008000 */ 3232 3233 #define LPTIM_CFGR_TRIGEN_Pos (17U) 3234 #define LPTIM_CFGR_TRIGEN_Msk (0x3U << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00060000 */ 3235 #define LPTIM_CFGR_TRIGEN LPTIM_CFGR_TRIGEN_Msk /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */ 3236 #define LPTIM_CFGR_TRIGEN_0 (0x1U << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00020000 */ 3237 #define LPTIM_CFGR_TRIGEN_1 (0x2U << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00040000 */ 3238 3239 #define LPTIM_CFGR_TIMOUT_Pos (19U) 3240 #define LPTIM_CFGR_TIMOUT_Msk (0x1U << LPTIM_CFGR_TIMOUT_Pos) /*!< 0x00080000 */ 3241 #define LPTIM_CFGR_TIMOUT LPTIM_CFGR_TIMOUT_Msk /*!< Timout enable */ 3242 #define LPTIM_CFGR_WAVE_Pos (20U) 3243 #define LPTIM_CFGR_WAVE_Msk (0x1U << LPTIM_CFGR_WAVE_Pos) /*!< 0x00100000 */ 3244 #define LPTIM_CFGR_WAVE LPTIM_CFGR_WAVE_Msk /*!< Waveform shape */ 3245 #define LPTIM_CFGR_WAVPOL_Pos (21U) 3246 #define LPTIM_CFGR_WAVPOL_Msk (0x1U << LPTIM_CFGR_WAVPOL_Pos) /*!< 0x00200000 */ 3247 #define LPTIM_CFGR_WAVPOL LPTIM_CFGR_WAVPOL_Msk /*!< Waveform shape polarity */ 3248 #define LPTIM_CFGR_PRELOAD_Pos (22U) 3249 #define LPTIM_CFGR_PRELOAD_Msk (0x1U << LPTIM_CFGR_PRELOAD_Pos) /*!< 0x00400000 */ 3250 #define LPTIM_CFGR_PRELOAD LPTIM_CFGR_PRELOAD_Msk /*!< Reg update mode */ 3251 #define LPTIM_CFGR_COUNTMODE_Pos (23U) 3252 #define LPTIM_CFGR_COUNTMODE_Msk (0x1U << LPTIM_CFGR_COUNTMODE_Pos) /*!< 0x00800000 */ 3253 #define LPTIM_CFGR_COUNTMODE LPTIM_CFGR_COUNTMODE_Msk /*!< Counter mode enable */ 3254 #define LPTIM_CFGR_ENC_Pos (24U) 3255 #define LPTIM_CFGR_ENC_Msk (0x1U << LPTIM_CFGR_ENC_Pos) /*!< 0x01000000 */ 3256 #define LPTIM_CFGR_ENC LPTIM_CFGR_ENC_Msk /*!< Encoder mode enable */ 3257 3258 /****************** Bit definition for LPTIM_CR register ********************/ 3259 #define LPTIM_CR_ENABLE_Pos (0U) 3260 #define LPTIM_CR_ENABLE_Msk (0x1U << LPTIM_CR_ENABLE_Pos) /*!< 0x00000001 */ 3261 #define LPTIM_CR_ENABLE LPTIM_CR_ENABLE_Msk /*!< LPTIMer enable */ 3262 #define LPTIM_CR_SNGSTRT_Pos (1U) 3263 #define LPTIM_CR_SNGSTRT_Msk (0x1U << LPTIM_CR_SNGSTRT_Pos) /*!< 0x00000002 */ 3264 #define LPTIM_CR_SNGSTRT LPTIM_CR_SNGSTRT_Msk /*!< Timer start in single mode */ 3265 #define LPTIM_CR_CNTSTRT_Pos (2U) 3266 #define LPTIM_CR_CNTSTRT_Msk (0x1U << LPTIM_CR_CNTSTRT_Pos) /*!< 0x00000004 */ 3267 #define LPTIM_CR_CNTSTRT LPTIM_CR_CNTSTRT_Msk /*!< Timer start in continuous mode */ 3268 3269 /****************** Bit definition for LPTIM_CMP register *******************/ 3270 #define LPTIM_CMP_CMP_Pos (0U) 3271 #define LPTIM_CMP_CMP_Msk (0xFFFFU << LPTIM_CMP_CMP_Pos) /*!< 0x0000FFFF */ 3272 #define LPTIM_CMP_CMP LPTIM_CMP_CMP_Msk /*!< Compare register */ 3273 3274 /****************** Bit definition for LPTIM_ARR register *******************/ 3275 #define LPTIM_ARR_ARR_Pos (0U) 3276 #define LPTIM_ARR_ARR_Msk (0xFFFFU << LPTIM_ARR_ARR_Pos) /*!< 0x0000FFFF */ 3277 #define LPTIM_ARR_ARR LPTIM_ARR_ARR_Msk /*!< Auto reload register */ 3278 3279 /****************** Bit definition for LPTIM_CNT register *******************/ 3280 #define LPTIM_CNT_CNT_Pos (0U) 3281 #define LPTIM_CNT_CNT_Msk (0xFFFFU << LPTIM_CNT_CNT_Pos) /*!< 0x0000FFFF */ 3282 #define LPTIM_CNT_CNT LPTIM_CNT_CNT_Msk /*!< Counter register */ 3283 3284 /******************************************************************************/ 3285 /* */ 3286 /* MIFARE Firewall */ 3287 /* */ 3288 /******************************************************************************/ 3289 3290 /*******Bit definition for CSSA;CSL;NVDSSA;NVDSL;VDSSA;VDSL register */ 3291 #define FW_CSSA_ADD_Pos (8U) 3292 #define FW_CSSA_ADD_Msk (0xFFFFU << FW_CSSA_ADD_Pos) /*!< 0x00FFFF00 */ 3293 #define FW_CSSA_ADD FW_CSSA_ADD_Msk /*!< Code Segment Start Address */ 3294 #define FW_CSL_LENG_Pos (8U) 3295 #define FW_CSL_LENG_Msk (0x3FFFU << FW_CSL_LENG_Pos) /*!< 0x003FFF00 */ 3296 #define FW_CSL_LENG FW_CSL_LENG_Msk /*!< Code Segment Length */ 3297 #define FW_NVDSSA_ADD_Pos (8U) 3298 #define FW_NVDSSA_ADD_Msk (0xFFFFU << FW_NVDSSA_ADD_Pos) /*!< 0x00FFFF00 */ 3299 #define FW_NVDSSA_ADD FW_NVDSSA_ADD_Msk /*!< Non Volatile Dat Segment Start Address */ 3300 #define FW_NVDSL_LENG_Pos (8U) 3301 #define FW_NVDSL_LENG_Msk (0x3FFFU << FW_NVDSL_LENG_Pos) /*!< 0x003FFF00 */ 3302 #define FW_NVDSL_LENG FW_NVDSL_LENG_Msk /*!< Non Volatile Data Segment Length */ 3303 #define FW_VDSSA_ADD_Pos (6U) 3304 #define FW_VDSSA_ADD_Msk (0x3FFU << FW_VDSSA_ADD_Pos) /*!< 0x0000FFC0 */ 3305 #define FW_VDSSA_ADD FW_VDSSA_ADD_Msk /*!< Volatile Data Segment Start Address */ 3306 #define FW_VDSL_LENG_Pos (6U) 3307 #define FW_VDSL_LENG_Msk (0x3FFU << FW_VDSL_LENG_Pos) /*!< 0x0000FFC0 */ 3308 #define FW_VDSL_LENG FW_VDSL_LENG_Msk /*!< Volatile Data Segment Length */ 3309 3310 /**************************Bit definition for CR register *********************/ 3311 #define FW_CR_FPA_Pos (0U) 3312 #define FW_CR_FPA_Msk (0x1U << FW_CR_FPA_Pos) /*!< 0x00000001 */ 3313 #define FW_CR_FPA FW_CR_FPA_Msk /*!< Firewall Pre Arm*/ 3314 #define FW_CR_VDS_Pos (1U) 3315 #define FW_CR_VDS_Msk (0x1U << FW_CR_VDS_Pos) /*!< 0x00000002 */ 3316 #define FW_CR_VDS FW_CR_VDS_Msk /*!< Volatile Data Sharing*/ 3317 #define FW_CR_VDE_Pos (2U) 3318 #define FW_CR_VDE_Msk (0x1U << FW_CR_VDE_Pos) /*!< 0x00000004 */ 3319 #define FW_CR_VDE FW_CR_VDE_Msk /*!< Volatile Data Execution*/ 3320 3321 /******************************************************************************/ 3322 /* */ 3323 /* Power Control (PWR) */ 3324 /* */ 3325 /******************************************************************************/ 3326 3327 #define PWR_PVD_SUPPORT /*!< PVD feature available on all devices: Power Voltage Detection feature */ 3328 3329 /******************** Bit definition for PWR_CR register ********************/ 3330 #define PWR_CR_LPSDSR_Pos (0U) 3331 #define PWR_CR_LPSDSR_Msk (0x1U << PWR_CR_LPSDSR_Pos) /*!< 0x00000001 */ 3332 #define PWR_CR_LPSDSR PWR_CR_LPSDSR_Msk /*!< Low-power deepsleep/sleep/low power run */ 3333 #define PWR_CR_PDDS_Pos (1U) 3334 #define PWR_CR_PDDS_Msk (0x1U << PWR_CR_PDDS_Pos) /*!< 0x00000002 */ 3335 #define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */ 3336 #define PWR_CR_CWUF_Pos (2U) 3337 #define PWR_CR_CWUF_Msk (0x1U << PWR_CR_CWUF_Pos) /*!< 0x00000004 */ 3338 #define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */ 3339 #define PWR_CR_CSBF_Pos (3U) 3340 #define PWR_CR_CSBF_Msk (0x1U << PWR_CR_CSBF_Pos) /*!< 0x00000008 */ 3341 #define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */ 3342 #define PWR_CR_PVDE_Pos (4U) 3343 #define PWR_CR_PVDE_Msk (0x1U << PWR_CR_PVDE_Pos) /*!< 0x00000010 */ 3344 #define PWR_CR_PVDE PWR_CR_PVDE_Msk /*!< Power Voltage Detector Enable */ 3345 3346 #define PWR_CR_PLS_Pos (5U) 3347 #define PWR_CR_PLS_Msk (0x7U << PWR_CR_PLS_Pos) /*!< 0x000000E0 */ 3348 #define PWR_CR_PLS PWR_CR_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */ 3349 #define PWR_CR_PLS_0 (0x1U << PWR_CR_PLS_Pos) /*!< 0x00000020 */ 3350 #define PWR_CR_PLS_1 (0x2U << PWR_CR_PLS_Pos) /*!< 0x00000040 */ 3351 #define PWR_CR_PLS_2 (0x4U << PWR_CR_PLS_Pos) /*!< 0x00000080 */ 3352 3353 /*!< PVD level configuration */ 3354 #define PWR_CR_PLS_LEV0 (0x00000000U) /*!< PVD level 0 */ 3355 #define PWR_CR_PLS_LEV1 (0x00000020U) /*!< PVD level 1 */ 3356 #define PWR_CR_PLS_LEV2 (0x00000040U) /*!< PVD level 2 */ 3357 #define PWR_CR_PLS_LEV3 (0x00000060U) /*!< PVD level 3 */ 3358 #define PWR_CR_PLS_LEV4 (0x00000080U) /*!< PVD level 4 */ 3359 #define PWR_CR_PLS_LEV5 (0x000000A0U) /*!< PVD level 5 */ 3360 #define PWR_CR_PLS_LEV6 (0x000000C0U) /*!< PVD level 6 */ 3361 #define PWR_CR_PLS_LEV7 (0x000000E0U) /*!< PVD level 7 */ 3362 3363 #define PWR_CR_DBP_Pos (8U) 3364 #define PWR_CR_DBP_Msk (0x1U << PWR_CR_DBP_Pos) /*!< 0x00000100 */ 3365 #define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */ 3366 #define PWR_CR_ULP_Pos (9U) 3367 #define PWR_CR_ULP_Msk (0x1U << PWR_CR_ULP_Pos) /*!< 0x00000200 */ 3368 #define PWR_CR_ULP PWR_CR_ULP_Msk /*!< Ultra Low Power mode */ 3369 #define PWR_CR_FWU_Pos (10U) 3370 #define PWR_CR_FWU_Msk (0x1U << PWR_CR_FWU_Pos) /*!< 0x00000400 */ 3371 #define PWR_CR_FWU PWR_CR_FWU_Msk /*!< Fast wakeup */ 3372 3373 #define PWR_CR_VOS_Pos (11U) 3374 #define PWR_CR_VOS_Msk (0x3U << PWR_CR_VOS_Pos) /*!< 0x00001800 */ 3375 #define PWR_CR_VOS PWR_CR_VOS_Msk /*!< VOS[1:0] bits (Voltage scaling range selection) */ 3376 #define PWR_CR_VOS_0 (0x1U << PWR_CR_VOS_Pos) /*!< 0x00000800 */ 3377 #define PWR_CR_VOS_1 (0x2U << PWR_CR_VOS_Pos) /*!< 0x00001000 */ 3378 #define PWR_CR_DSEEKOFF_Pos (13U) 3379 #define PWR_CR_DSEEKOFF_Msk (0x1U << PWR_CR_DSEEKOFF_Pos) /*!< 0x00002000 */ 3380 #define PWR_CR_DSEEKOFF PWR_CR_DSEEKOFF_Msk /*!< Deep Sleep mode with EEPROM kept Off */ 3381 #define PWR_CR_LPRUN_Pos (14U) 3382 #define PWR_CR_LPRUN_Msk (0x1U << PWR_CR_LPRUN_Pos) /*!< 0x00004000 */ 3383 #define PWR_CR_LPRUN PWR_CR_LPRUN_Msk /*!< Low power run mode */ 3384 3385 /******************* Bit definition for PWR_CSR register ********************/ 3386 #define PWR_CSR_WUF_Pos (0U) 3387 #define PWR_CSR_WUF_Msk (0x1U << PWR_CSR_WUF_Pos) /*!< 0x00000001 */ 3388 #define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */ 3389 #define PWR_CSR_SBF_Pos (1U) 3390 #define PWR_CSR_SBF_Msk (0x1U << PWR_CSR_SBF_Pos) /*!< 0x00000002 */ 3391 #define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */ 3392 #define PWR_CSR_PVDO_Pos (2U) 3393 #define PWR_CSR_PVDO_Msk (0x1U << PWR_CSR_PVDO_Pos) /*!< 0x00000004 */ 3394 #define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /*!< PVD Output */ 3395 #define PWR_CSR_VREFINTRDYF_Pos (3U) 3396 #define PWR_CSR_VREFINTRDYF_Msk (0x1U << PWR_CSR_VREFINTRDYF_Pos) /*!< 0x00000008 */ 3397 #define PWR_CSR_VREFINTRDYF PWR_CSR_VREFINTRDYF_Msk /*!< Internal voltage reference (VREFINT) ready flag */ 3398 #define PWR_CSR_VOSF_Pos (4U) 3399 #define PWR_CSR_VOSF_Msk (0x1U << PWR_CSR_VOSF_Pos) /*!< 0x00000010 */ 3400 #define PWR_CSR_VOSF PWR_CSR_VOSF_Msk /*!< Voltage Scaling select flag */ 3401 #define PWR_CSR_REGLPF_Pos (5U) 3402 #define PWR_CSR_REGLPF_Msk (0x1U << PWR_CSR_REGLPF_Pos) /*!< 0x00000020 */ 3403 #define PWR_CSR_REGLPF PWR_CSR_REGLPF_Msk /*!< Regulator LP flag */ 3404 3405 #define PWR_CSR_EWUP1_Pos (8U) 3406 #define PWR_CSR_EWUP1_Msk (0x1U << PWR_CSR_EWUP1_Pos) /*!< 0x00000100 */ 3407 #define PWR_CSR_EWUP1 PWR_CSR_EWUP1_Msk /*!< Enable WKUP pin 1 */ 3408 #define PWR_CSR_EWUP2_Pos (9U) 3409 #define PWR_CSR_EWUP2_Msk (0x1U << PWR_CSR_EWUP2_Pos) /*!< 0x00000200 */ 3410 #define PWR_CSR_EWUP2 PWR_CSR_EWUP2_Msk /*!< Enable WKUP pin 2 */ 3411 #define PWR_CSR_EWUP3_Pos (10U) 3412 #define PWR_CSR_EWUP3_Msk (0x1U << PWR_CSR_EWUP3_Pos) /*!< 0x00000400 */ 3413 #define PWR_CSR_EWUP3 PWR_CSR_EWUP3_Msk /*!< Enable WKUP pin 3 */ 3414 3415 /******************************************************************************/ 3416 /* */ 3417 /* Reset and Clock Control */ 3418 /* */ 3419 /******************************************************************************/ 3420 3421 #define RCC_HSECSS_SUPPORT /*!< HSE CSS feature activation support */ 3422 3423 /******************** Bit definition for RCC_CR register ********************/ 3424 #define RCC_CR_HSION_Pos (0U) 3425 #define RCC_CR_HSION_Msk (0x1U << RCC_CR_HSION_Pos) /*!< 0x00000001 */ 3426 #define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed clock enable */ 3427 #define RCC_CR_HSIKERON_Pos (1U) 3428 #define RCC_CR_HSIKERON_Msk (0x1U << RCC_CR_HSIKERON_Pos) /*!< 0x00000002 */ 3429 #define RCC_CR_HSIKERON RCC_CR_HSIKERON_Msk /*!< Internal High Speed clock enable for some IPs Kernel */ 3430 #define RCC_CR_HSIRDY_Pos (2U) 3431 #define RCC_CR_HSIRDY_Msk (0x1U << RCC_CR_HSIRDY_Pos) /*!< 0x00000004 */ 3432 #define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed clock ready flag */ 3433 #define RCC_CR_HSIDIVEN_Pos (3U) 3434 #define RCC_CR_HSIDIVEN_Msk (0x1U << RCC_CR_HSIDIVEN_Pos) /*!< 0x00000008 */ 3435 #define RCC_CR_HSIDIVEN RCC_CR_HSIDIVEN_Msk /*!< Internal High Speed clock divider enable */ 3436 #define RCC_CR_HSIDIVF_Pos (4U) 3437 #define RCC_CR_HSIDIVF_Msk (0x1U << RCC_CR_HSIDIVF_Pos) /*!< 0x00000010 */ 3438 #define RCC_CR_HSIDIVF RCC_CR_HSIDIVF_Msk /*!< Internal High Speed clock divider flag */ 3439 #define RCC_CR_HSIOUTEN_Pos (5U) 3440 #define RCC_CR_HSIOUTEN_Msk (0x1U << RCC_CR_HSIOUTEN_Pos) /*!< 0x00000020 */ 3441 #define RCC_CR_HSIOUTEN RCC_CR_HSIOUTEN_Msk /*!< Internal High Speed clock out enable */ 3442 #define RCC_CR_MSION_Pos (8U) 3443 #define RCC_CR_MSION_Msk (0x1U << RCC_CR_MSION_Pos) /*!< 0x00000100 */ 3444 #define RCC_CR_MSION RCC_CR_MSION_Msk /*!< Internal Multi Speed clock enable */ 3445 #define RCC_CR_MSIRDY_Pos (9U) 3446 #define RCC_CR_MSIRDY_Msk (0x1U << RCC_CR_MSIRDY_Pos) /*!< 0x00000200 */ 3447 #define RCC_CR_MSIRDY RCC_CR_MSIRDY_Msk /*!< Internal Multi Speed clock ready flag */ 3448 #define RCC_CR_HSEON_Pos (16U) 3449 #define RCC_CR_HSEON_Msk (0x1U << RCC_CR_HSEON_Pos) /*!< 0x00010000 */ 3450 #define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed clock enable */ 3451 #define RCC_CR_HSERDY_Pos (17U) 3452 #define RCC_CR_HSERDY_Msk (0x1U << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */ 3453 #define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed clock ready flag */ 3454 #define RCC_CR_HSEBYP_Pos (18U) 3455 #define RCC_CR_HSEBYP_Msk (0x1U << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */ 3456 #define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed clock Bypass */ 3457 #define RCC_CR_CSSHSEON_Pos (19U) 3458 #define RCC_CR_CSSHSEON_Msk (0x1U << RCC_CR_CSSHSEON_Pos) /*!< 0x00080000 */ 3459 #define RCC_CR_CSSHSEON RCC_CR_CSSHSEON_Msk /*!< HSE Clock Security System enable */ 3460 #define RCC_CR_RTCPRE_Pos (20U) 3461 #define RCC_CR_RTCPRE_Msk (0x3U << RCC_CR_RTCPRE_Pos) /*!< 0x00300000 */ 3462 #define RCC_CR_RTCPRE RCC_CR_RTCPRE_Msk /*!< RTC prescaler [1:0] bits */ 3463 #define RCC_CR_RTCPRE_0 (0x1U << RCC_CR_RTCPRE_Pos) /*!< 0x00100000 */ 3464 #define RCC_CR_RTCPRE_1 (0x2U << RCC_CR_RTCPRE_Pos) /*!< 0x00200000 */ 3465 #define RCC_CR_PLLON_Pos (24U) 3466 #define RCC_CR_PLLON_Msk (0x1U << RCC_CR_PLLON_Pos) /*!< 0x01000000 */ 3467 #define RCC_CR_PLLON RCC_CR_PLLON_Msk /*!< PLL enable */ 3468 #define RCC_CR_PLLRDY_Pos (25U) 3469 #define RCC_CR_PLLRDY_Msk (0x1U << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */ 3470 #define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< PLL clock ready flag */ 3471 3472 /* Reference defines */ 3473 #define RCC_CR_CSSON RCC_CR_CSSHSEON 3474 3475 /******************** Bit definition for RCC_ICSCR register *****************/ 3476 #define RCC_ICSCR_HSICAL_Pos (0U) 3477 #define RCC_ICSCR_HSICAL_Msk (0xFFU << RCC_ICSCR_HSICAL_Pos) /*!< 0x000000FF */ 3478 #define RCC_ICSCR_HSICAL RCC_ICSCR_HSICAL_Msk /*!< Internal High Speed clock Calibration */ 3479 #define RCC_ICSCR_HSITRIM_Pos (8U) 3480 #define RCC_ICSCR_HSITRIM_Msk (0x1FU << RCC_ICSCR_HSITRIM_Pos) /*!< 0x00001F00 */ 3481 #define RCC_ICSCR_HSITRIM RCC_ICSCR_HSITRIM_Msk /*!< Internal High Speed clock trimming */ 3482 3483 #define RCC_ICSCR_MSIRANGE_Pos (13U) 3484 #define RCC_ICSCR_MSIRANGE_Msk (0x7U << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x0000E000 */ 3485 #define RCC_ICSCR_MSIRANGE RCC_ICSCR_MSIRANGE_Msk /*!< Internal Multi Speed clock Range */ 3486 #define RCC_ICSCR_MSIRANGE_0 (0x0U << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00000000 */ 3487 #define RCC_ICSCR_MSIRANGE_1 (0x1U << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00002000 */ 3488 #define RCC_ICSCR_MSIRANGE_2 (0x2U << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00004000 */ 3489 #define RCC_ICSCR_MSIRANGE_3 (0x3U << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00006000 */ 3490 #define RCC_ICSCR_MSIRANGE_4 (0x4U << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x00008000 */ 3491 #define RCC_ICSCR_MSIRANGE_5 (0x5U << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x0000A000 */ 3492 #define RCC_ICSCR_MSIRANGE_6 (0x6U << RCC_ICSCR_MSIRANGE_Pos) /*!< 0x0000C000 */ 3493 #define RCC_ICSCR_MSICAL_Pos (16U) 3494 #define RCC_ICSCR_MSICAL_Msk (0xFFU << RCC_ICSCR_MSICAL_Pos) /*!< 0x00FF0000 */ 3495 #define RCC_ICSCR_MSICAL RCC_ICSCR_MSICAL_Msk /*!< Internal Multi Speed clock Calibration */ 3496 #define RCC_ICSCR_MSITRIM_Pos (24U) 3497 #define RCC_ICSCR_MSITRIM_Msk (0xFFU << RCC_ICSCR_MSITRIM_Pos) /*!< 0xFF000000 */ 3498 #define RCC_ICSCR_MSITRIM RCC_ICSCR_MSITRIM_Msk /*!< Internal Multi Speed clock trimming */ 3499 3500 3501 /******************* Bit definition for RCC_CFGR register *******************/ 3502 /*!< SW configuration */ 3503 #define RCC_CFGR_SW_Pos (0U) 3504 #define RCC_CFGR_SW_Msk (0x3U << RCC_CFGR_SW_Pos) /*!< 0x00000003 */ 3505 #define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */ 3506 #define RCC_CFGR_SW_0 (0x1U << RCC_CFGR_SW_Pos) /*!< 0x00000001 */ 3507 #define RCC_CFGR_SW_1 (0x2U << RCC_CFGR_SW_Pos) /*!< 0x00000002 */ 3508 3509 #define RCC_CFGR_SW_MSI (0x00000000U) /*!< MSI selected as system clock */ 3510 #define RCC_CFGR_SW_HSI (0x00000001U) /*!< HSI selected as system clock */ 3511 #define RCC_CFGR_SW_HSE (0x00000002U) /*!< HSE selected as system clock */ 3512 #define RCC_CFGR_SW_PLL (0x00000003U) /*!< PLL selected as system clock */ 3513 3514 /*!< SWS configuration */ 3515 #define RCC_CFGR_SWS_Pos (2U) 3516 #define RCC_CFGR_SWS_Msk (0x3U << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */ 3517 #define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */ 3518 #define RCC_CFGR_SWS_0 (0x1U << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */ 3519 #define RCC_CFGR_SWS_1 (0x2U << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */ 3520 3521 #define RCC_CFGR_SWS_MSI (0x00000000U) /*!< MSI oscillator used as system clock */ 3522 #define RCC_CFGR_SWS_HSI (0x00000004U) /*!< HSI oscillator used as system clock */ 3523 #define RCC_CFGR_SWS_HSE (0x00000008U) /*!< HSE oscillator used as system clock */ 3524 #define RCC_CFGR_SWS_PLL (0x0000000CU) /*!< PLL used as system clock */ 3525 3526 /*!< HPRE configuration */ 3527 #define RCC_CFGR_HPRE_Pos (4U) 3528 #define RCC_CFGR_HPRE_Msk (0xFU << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */ 3529 #define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */ 3530 #define RCC_CFGR_HPRE_0 (0x1U << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */ 3531 #define RCC_CFGR_HPRE_1 (0x2U << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */ 3532 #define RCC_CFGR_HPRE_2 (0x4U << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */ 3533 #define RCC_CFGR_HPRE_3 (0x8U << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */ 3534 3535 #define RCC_CFGR_HPRE_DIV1 (0x00000000U) /*!< SYSCLK not divided */ 3536 #define RCC_CFGR_HPRE_DIV2 (0x00000080U) /*!< SYSCLK divided by 2 */ 3537 #define RCC_CFGR_HPRE_DIV4 (0x00000090U) /*!< SYSCLK divided by 4 */ 3538 #define RCC_CFGR_HPRE_DIV8 (0x000000A0U) /*!< SYSCLK divided by 8 */ 3539 #define RCC_CFGR_HPRE_DIV16 (0x000000B0U) /*!< SYSCLK divided by 16 */ 3540 #define RCC_CFGR_HPRE_DIV64 (0x000000C0U) /*!< SYSCLK divided by 64 */ 3541 #define RCC_CFGR_HPRE_DIV128 (0x000000D0U) /*!< SYSCLK divided by 128 */ 3542 #define RCC_CFGR_HPRE_DIV256 (0x000000E0U) /*!< SYSCLK divided by 256 */ 3543 #define RCC_CFGR_HPRE_DIV512 (0x000000F0U) /*!< SYSCLK divided by 512 */ 3544 3545 /*!< PPRE1 configuration */ 3546 #define RCC_CFGR_PPRE1_Pos (8U) 3547 #define RCC_CFGR_PPRE1_Msk (0x7U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000700 */ 3548 #define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */ 3549 #define RCC_CFGR_PPRE1_0 (0x1U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000100 */ 3550 #define RCC_CFGR_PPRE1_1 (0x2U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000200 */ 3551 #define RCC_CFGR_PPRE1_2 (0x4U << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */ 3552 3553 #define RCC_CFGR_PPRE1_DIV1 (0x00000000U) /*!< HCLK not divided */ 3554 #define RCC_CFGR_PPRE1_DIV2 (0x00000400U) /*!< HCLK divided by 2 */ 3555 #define RCC_CFGR_PPRE1_DIV4 (0x00000500U) /*!< HCLK divided by 4 */ 3556 #define RCC_CFGR_PPRE1_DIV8 (0x00000600U) /*!< HCLK divided by 8 */ 3557 #define RCC_CFGR_PPRE1_DIV16 (0x00000700U) /*!< HCLK divided by 16 */ 3558 3559 /*!< PPRE2 configuration */ 3560 #define RCC_CFGR_PPRE2_Pos (11U) 3561 #define RCC_CFGR_PPRE2_Msk (0x7U << RCC_CFGR_PPRE2_Pos) /*!< 0x00003800 */ 3562 #define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */ 3563 #define RCC_CFGR_PPRE2_0 (0x1U << RCC_CFGR_PPRE2_Pos) /*!< 0x00000800 */ 3564 #define RCC_CFGR_PPRE2_1 (0x2U << RCC_CFGR_PPRE2_Pos) /*!< 0x00001000 */ 3565 #define RCC_CFGR_PPRE2_2 (0x4U << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */ 3566 3567 #define RCC_CFGR_PPRE2_DIV1 (0x00000000U) /*!< HCLK not divided */ 3568 #define RCC_CFGR_PPRE2_DIV2 (0x00002000U) /*!< HCLK divided by 2 */ 3569 #define RCC_CFGR_PPRE2_DIV4 (0x00002800U) /*!< HCLK divided by 4 */ 3570 #define RCC_CFGR_PPRE2_DIV8 (0x00003000U) /*!< HCLK divided by 8 */ 3571 #define RCC_CFGR_PPRE2_DIV16 (0x00003800U) /*!< HCLK divided by 16 */ 3572 3573 #define RCC_CFGR_STOPWUCK_Pos (15U) 3574 #define RCC_CFGR_STOPWUCK_Msk (0x1U << RCC_CFGR_STOPWUCK_Pos) /*!< 0x00008000 */ 3575 #define RCC_CFGR_STOPWUCK RCC_CFGR_STOPWUCK_Msk /*!< Wake Up from Stop Clock selection */ 3576 3577 /*!< PLL entry clock source*/ 3578 #define RCC_CFGR_PLLSRC_Pos (16U) 3579 #define RCC_CFGR_PLLSRC_Msk (0x1U << RCC_CFGR_PLLSRC_Pos) /*!< 0x00010000 */ 3580 #define RCC_CFGR_PLLSRC RCC_CFGR_PLLSRC_Msk /*!< PLL entry clock source */ 3581 3582 #define RCC_CFGR_PLLSRC_HSI (0x00000000U) /*!< HSI as PLL entry clock source */ 3583 #define RCC_CFGR_PLLSRC_HSE (0x00010000U) /*!< HSE as PLL entry clock source */ 3584 3585 3586 /*!< PLLMUL configuration */ 3587 #define RCC_CFGR_PLLMUL_Pos (18U) 3588 #define RCC_CFGR_PLLMUL_Msk (0xFU << RCC_CFGR_PLLMUL_Pos) /*!< 0x003C0000 */ 3589 #define RCC_CFGR_PLLMUL RCC_CFGR_PLLMUL_Msk /*!< PLLMUL[3:0] bits (PLL multiplication factor) */ 3590 #define RCC_CFGR_PLLMUL_0 (0x1U << RCC_CFGR_PLLMUL_Pos) /*!< 0x00040000 */ 3591 #define RCC_CFGR_PLLMUL_1 (0x2U << RCC_CFGR_PLLMUL_Pos) /*!< 0x00080000 */ 3592 #define RCC_CFGR_PLLMUL_2 (0x4U << RCC_CFGR_PLLMUL_Pos) /*!< 0x00100000 */ 3593 #define RCC_CFGR_PLLMUL_3 (0x8U << RCC_CFGR_PLLMUL_Pos) /*!< 0x00200000 */ 3594 3595 #define RCC_CFGR_PLLMUL3 (0x00000000U) /*!< PLL input clock * 3 */ 3596 #define RCC_CFGR_PLLMUL4 (0x00040000U) /*!< PLL input clock * 4 */ 3597 #define RCC_CFGR_PLLMUL6 (0x00080000U) /*!< PLL input clock * 6 */ 3598 #define RCC_CFGR_PLLMUL8 (0x000C0000U) /*!< PLL input clock * 8 */ 3599 #define RCC_CFGR_PLLMUL12 (0x00100000U) /*!< PLL input clock * 12 */ 3600 #define RCC_CFGR_PLLMUL16 (0x00140000U) /*!< PLL input clock * 16 */ 3601 #define RCC_CFGR_PLLMUL24 (0x00180000U) /*!< PLL input clock * 24 */ 3602 #define RCC_CFGR_PLLMUL32 (0x001C0000U) /*!< PLL input clock * 32 */ 3603 #define RCC_CFGR_PLLMUL48 (0x00200000U) /*!< PLL input clock * 48 */ 3604 3605 /*!< PLLDIV configuration */ 3606 #define RCC_CFGR_PLLDIV_Pos (22U) 3607 #define RCC_CFGR_PLLDIV_Msk (0x3U << RCC_CFGR_PLLDIV_Pos) /*!< 0x00C00000 */ 3608 #define RCC_CFGR_PLLDIV RCC_CFGR_PLLDIV_Msk /*!< PLLDIV[1:0] bits (PLL Output Division) */ 3609 #define RCC_CFGR_PLLDIV_0 (0x1U << RCC_CFGR_PLLDIV_Pos) /*!< 0x00400000 */ 3610 #define RCC_CFGR_PLLDIV_1 (0x2U << RCC_CFGR_PLLDIV_Pos) /*!< 0x00800000 */ 3611 3612 #define RCC_CFGR_PLLDIV2_Pos (22U) 3613 #define RCC_CFGR_PLLDIV2_Msk (0x1U << RCC_CFGR_PLLDIV2_Pos) /*!< 0x00400000 */ 3614 #define RCC_CFGR_PLLDIV2 RCC_CFGR_PLLDIV2_Msk /*!< PLL clock output = CKVCO / 2 */ 3615 #define RCC_CFGR_PLLDIV3_Pos (23U) 3616 #define RCC_CFGR_PLLDIV3_Msk (0x1U << RCC_CFGR_PLLDIV3_Pos) /*!< 0x00800000 */ 3617 #define RCC_CFGR_PLLDIV3 RCC_CFGR_PLLDIV3_Msk /*!< PLL clock output = CKVCO / 3 */ 3618 #define RCC_CFGR_PLLDIV4_Pos (22U) 3619 #define RCC_CFGR_PLLDIV4_Msk (0x3U << RCC_CFGR_PLLDIV4_Pos) /*!< 0x00C00000 */ 3620 #define RCC_CFGR_PLLDIV4 RCC_CFGR_PLLDIV4_Msk /*!< PLL clock output = CKVCO / 4 */ 3621 3622 /*!< MCO configuration */ 3623 #define RCC_CFGR_MCOSEL_Pos (24U) 3624 #define RCC_CFGR_MCOSEL_Msk (0xFU << RCC_CFGR_MCOSEL_Pos) /*!< 0x0F000000 */ 3625 #define RCC_CFGR_MCOSEL RCC_CFGR_MCOSEL_Msk /*!< MCO[3:0] bits (Microcontroller Clock Output) */ 3626 #define RCC_CFGR_MCOSEL_0 (0x1U << RCC_CFGR_MCOSEL_Pos) /*!< 0x01000000 */ 3627 #define RCC_CFGR_MCOSEL_1 (0x2U << RCC_CFGR_MCOSEL_Pos) /*!< 0x02000000 */ 3628 #define RCC_CFGR_MCOSEL_2 (0x4U << RCC_CFGR_MCOSEL_Pos) /*!< 0x04000000 */ 3629 #define RCC_CFGR_MCOSEL_3 (0x8U << RCC_CFGR_MCOSEL_Pos) /*!< 0x08000000 */ 3630 3631 #define RCC_CFGR_MCOSEL_NOCLOCK (0x00000000U) /*!< No clock */ 3632 #define RCC_CFGR_MCOSEL_SYSCLK_Pos (24U) 3633 #define RCC_CFGR_MCOSEL_SYSCLK_Msk (0x1U << RCC_CFGR_MCOSEL_SYSCLK_Pos) /*!< 0x01000000 */ 3634 #define RCC_CFGR_MCOSEL_SYSCLK RCC_CFGR_MCOSEL_SYSCLK_Msk /*!< System clock selected as MCO source */ 3635 #define RCC_CFGR_MCOSEL_HSI_Pos (25U) 3636 #define RCC_CFGR_MCOSEL_HSI_Msk (0x1U << RCC_CFGR_MCOSEL_HSI_Pos) /*!< 0x02000000 */ 3637 #define RCC_CFGR_MCOSEL_HSI RCC_CFGR_MCOSEL_HSI_Msk /*!< Internal 16 MHz RC oscillator clock selected */ 3638 #define RCC_CFGR_MCOSEL_MSI_Pos (24U) 3639 #define RCC_CFGR_MCOSEL_MSI_Msk (0x3U << RCC_CFGR_MCOSEL_MSI_Pos) /*!< 0x03000000 */ 3640 #define RCC_CFGR_MCOSEL_MSI RCC_CFGR_MCOSEL_MSI_Msk /*!< Internal Medium Speed RC oscillator clock selected */ 3641 #define RCC_CFGR_MCOSEL_HSE_Pos (26U) 3642 #define RCC_CFGR_MCOSEL_HSE_Msk (0x1U << RCC_CFGR_MCOSEL_HSE_Pos) /*!< 0x04000000 */ 3643 #define RCC_CFGR_MCOSEL_HSE RCC_CFGR_MCOSEL_HSE_Msk /*!< External 1-25 MHz oscillator clock selected */ 3644 #define RCC_CFGR_MCOSEL_PLL_Pos (24U) 3645 #define RCC_CFGR_MCOSEL_PLL_Msk (0x5U << RCC_CFGR_MCOSEL_PLL_Pos) /*!< 0x05000000 */ 3646 #define RCC_CFGR_MCOSEL_PLL RCC_CFGR_MCOSEL_PLL_Msk /*!< PLL clock divided */ 3647 #define RCC_CFGR_MCOSEL_LSI_Pos (25U) 3648 #define RCC_CFGR_MCOSEL_LSI_Msk (0x3U << RCC_CFGR_MCOSEL_LSI_Pos) /*!< 0x06000000 */ 3649 #define RCC_CFGR_MCOSEL_LSI RCC_CFGR_MCOSEL_LSI_Msk /*!< LSI selected */ 3650 #define RCC_CFGR_MCOSEL_LSE_Pos (24U) 3651 #define RCC_CFGR_MCOSEL_LSE_Msk (0x7U << RCC_CFGR_MCOSEL_LSE_Pos) /*!< 0x07000000 */ 3652 #define RCC_CFGR_MCOSEL_LSE RCC_CFGR_MCOSEL_LSE_Msk /*!< LSE selected */ 3653 3654 #define RCC_CFGR_MCOPRE_Pos (28U) 3655 #define RCC_CFGR_MCOPRE_Msk (0x7U << RCC_CFGR_MCOPRE_Pos) /*!< 0x70000000 */ 3656 #define RCC_CFGR_MCOPRE RCC_CFGR_MCOPRE_Msk /*!< MCO prescaler */ 3657 #define RCC_CFGR_MCOPRE_0 (0x1U << RCC_CFGR_MCOPRE_Pos) /*!< 0x10000000 */ 3658 #define RCC_CFGR_MCOPRE_1 (0x2U << RCC_CFGR_MCOPRE_Pos) /*!< 0x20000000 */ 3659 #define RCC_CFGR_MCOPRE_2 (0x4U << RCC_CFGR_MCOPRE_Pos) /*!< 0x40000000 */ 3660 3661 #define RCC_CFGR_MCOPRE_DIV1 (0x00000000U) /*!< MCO is divided by 1 */ 3662 #define RCC_CFGR_MCOPRE_DIV2 (0x10000000U) /*!< MCO is divided by 2 */ 3663 #define RCC_CFGR_MCOPRE_DIV4 (0x20000000U) /*!< MCO is divided by 4 */ 3664 #define RCC_CFGR_MCOPRE_DIV8 (0x30000000U) /*!< MCO is divided by 8 */ 3665 #define RCC_CFGR_MCOPRE_DIV16 (0x40000000U) /*!< MCO is divided by 16 */ 3666 3667 /* Legacy defines */ 3668 #define RCC_CFGR_MCO_NOCLOCK RCC_CFGR_MCOSEL_NOCLOCK 3669 #define RCC_CFGR_MCO_SYSCLK RCC_CFGR_MCOSEL_SYSCLK 3670 #define RCC_CFGR_MCO_HSI RCC_CFGR_MCOSEL_HSI 3671 #define RCC_CFGR_MCO_MSI RCC_CFGR_MCOSEL_MSI 3672 #define RCC_CFGR_MCO_HSE RCC_CFGR_MCOSEL_HSE 3673 #define RCC_CFGR_MCO_PLL RCC_CFGR_MCOSEL_PLL 3674 #define RCC_CFGR_MCO_LSI RCC_CFGR_MCOSEL_LSI 3675 #define RCC_CFGR_MCO_LSE RCC_CFGR_MCOSEL_LSE 3676 #ifdef RCC_CFGR_MCOSEL_HSI48 3677 #define RCC_CFGR_MCO_HSI48 RCC_CFGR_MCOSEL_HSI48 3678 #endif 3679 3680 #define RCC_CFGR_MCO_PRE RCC_CFGR_MCOPRE /*!< MCO prescaler */ 3681 #define RCC_CFGR_MCO_PRE_1 RCC_CFGR_MCOPRE_DIV1 /*!< MCO is divided by 1 */ 3682 #define RCC_CFGR_MCO_PRE_2 RCC_CFGR_MCOPRE_DIV2 /*!< MCO is divided by 1 */ 3683 #define RCC_CFGR_MCO_PRE_4 RCC_CFGR_MCOPRE_DIV4 /*!< MCO is divided by 1 */ 3684 #define RCC_CFGR_MCO_PRE_8 RCC_CFGR_MCOPRE_DIV8 /*!< MCO is divided by 1 */ 3685 #define RCC_CFGR_MCO_PRE_16 RCC_CFGR_MCOPRE_DIV16 /*!< MCO is divided by 1 */ 3686 3687 /*!<****************** Bit definition for RCC_CIER register ********************/ 3688 #define RCC_CIER_LSIRDYIE_Pos (0U) 3689 #define RCC_CIER_LSIRDYIE_Msk (0x1U << RCC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */ 3690 #define RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE_Msk /*!< LSI Ready Interrupt Enable */ 3691 #define RCC_CIER_LSERDYIE_Pos (1U) 3692 #define RCC_CIER_LSERDYIE_Msk (0x1U << RCC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */ 3693 #define RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE_Msk /*!< LSE Ready Interrupt Enable */ 3694 #define RCC_CIER_HSIRDYIE_Pos (2U) 3695 #define RCC_CIER_HSIRDYIE_Msk (0x1U << RCC_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */ 3696 #define RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE_Msk /*!< HSI Ready Interrupt Enable */ 3697 #define RCC_CIER_HSERDYIE_Pos (3U) 3698 #define RCC_CIER_HSERDYIE_Msk (0x1U << RCC_CIER_HSERDYIE_Pos) /*!< 0x00000008 */ 3699 #define RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE_Msk /*!< HSE Ready Interrupt Enable */ 3700 #define RCC_CIER_PLLRDYIE_Pos (4U) 3701 #define RCC_CIER_PLLRDYIE_Msk (0x1U << RCC_CIER_PLLRDYIE_Pos) /*!< 0x00000010 */ 3702 #define RCC_CIER_PLLRDYIE RCC_CIER_PLLRDYIE_Msk /*!< PLL Ready Interrupt Enable */ 3703 #define RCC_CIER_MSIRDYIE_Pos (5U) 3704 #define RCC_CIER_MSIRDYIE_Msk (0x1U << RCC_CIER_MSIRDYIE_Pos) /*!< 0x00000020 */ 3705 #define RCC_CIER_MSIRDYIE RCC_CIER_MSIRDYIE_Msk /*!< MSI Ready Interrupt Enable */ 3706 #define RCC_CIER_CSSLSE_Pos (7U) 3707 #define RCC_CIER_CSSLSE_Msk (0x1U << RCC_CIER_CSSLSE_Pos) /*!< 0x00000080 */ 3708 #define RCC_CIER_CSSLSE RCC_CIER_CSSLSE_Msk /*!< LSE CSS Interrupt Enable */ 3709 3710 /* Reference defines */ 3711 #define RCC_CIER_LSECSSIE RCC_CIER_CSSLSE 3712 3713 /*!<****************** Bit definition for RCC_CIFR register ********************/ 3714 #define RCC_CIFR_LSIRDYF_Pos (0U) 3715 #define RCC_CIFR_LSIRDYF_Msk (0x1U << RCC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */ 3716 #define RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF_Msk /*!< LSI Ready Interrupt flag */ 3717 #define RCC_CIFR_LSERDYF_Pos (1U) 3718 #define RCC_CIFR_LSERDYF_Msk (0x1U << RCC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */ 3719 #define RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF_Msk /*!< LSE Ready Interrupt flag */ 3720 #define RCC_CIFR_HSIRDYF_Pos (2U) 3721 #define RCC_CIFR_HSIRDYF_Msk (0x1U << RCC_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */ 3722 #define RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF_Msk /*!< HSI Ready Interrupt flag */ 3723 #define RCC_CIFR_HSERDYF_Pos (3U) 3724 #define RCC_CIFR_HSERDYF_Msk (0x1U << RCC_CIFR_HSERDYF_Pos) /*!< 0x00000008 */ 3725 #define RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF_Msk /*!< HSE Ready Interrupt flag */ 3726 #define RCC_CIFR_PLLRDYF_Pos (4U) 3727 #define RCC_CIFR_PLLRDYF_Msk (0x1U << RCC_CIFR_PLLRDYF_Pos) /*!< 0x00000010 */ 3728 #define RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF_Msk /*!< PLL Ready Interrupt flag */ 3729 #define RCC_CIFR_MSIRDYF_Pos (5U) 3730 #define RCC_CIFR_MSIRDYF_Msk (0x1U << RCC_CIFR_MSIRDYF_Pos) /*!< 0x00000020 */ 3731 #define RCC_CIFR_MSIRDYF RCC_CIFR_MSIRDYF_Msk /*!< MSI Ready Interrupt flag */ 3732 #define RCC_CIFR_CSSLSEF_Pos (7U) 3733 #define RCC_CIFR_CSSLSEF_Msk (0x1U << RCC_CIFR_CSSLSEF_Pos) /*!< 0x00000080 */ 3734 #define RCC_CIFR_CSSLSEF RCC_CIFR_CSSLSEF_Msk /*!< LSE Clock Security System Interrupt flag */ 3735 #define RCC_CIFR_CSSHSEF_Pos (8U) 3736 #define RCC_CIFR_CSSHSEF_Msk (0x1U << RCC_CIFR_CSSHSEF_Pos) /*!< 0x00000100 */ 3737 #define RCC_CIFR_CSSHSEF RCC_CIFR_CSSHSEF_Msk /*!< HSE Clock Security System Interrupt flag */ 3738 3739 /* Reference defines */ 3740 #define RCC_CIFR_LSECSSF RCC_CIFR_CSSLSEF 3741 #define RCC_CIFR_CSSF RCC_CIFR_CSSHSEF 3742 3743 /*!<****************** Bit definition for RCC_CICR register ********************/ 3744 #define RCC_CICR_LSIRDYC_Pos (0U) 3745 #define RCC_CICR_LSIRDYC_Msk (0x1U << RCC_CICR_LSIRDYC_Pos) /*!< 0x00000001 */ 3746 #define RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC_Msk /*!< LSI Ready Interrupt Clear */ 3747 #define RCC_CICR_LSERDYC_Pos (1U) 3748 #define RCC_CICR_LSERDYC_Msk (0x1U << RCC_CICR_LSERDYC_Pos) /*!< 0x00000002 */ 3749 #define RCC_CICR_LSERDYC RCC_CICR_LSERDYC_Msk /*!< LSE Ready Interrupt Clear */ 3750 #define RCC_CICR_HSIRDYC_Pos (2U) 3751 #define RCC_CICR_HSIRDYC_Msk (0x1U << RCC_CICR_HSIRDYC_Pos) /*!< 0x00000004 */ 3752 #define RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC_Msk /*!< HSI Ready Interrupt Clear */ 3753 #define RCC_CICR_HSERDYC_Pos (3U) 3754 #define RCC_CICR_HSERDYC_Msk (0x1U << RCC_CICR_HSERDYC_Pos) /*!< 0x00000008 */ 3755 #define RCC_CICR_HSERDYC RCC_CICR_HSERDYC_Msk /*!< HSE Ready Interrupt Clear */ 3756 #define RCC_CICR_PLLRDYC_Pos (4U) 3757 #define RCC_CICR_PLLRDYC_Msk (0x1U << RCC_CICR_PLLRDYC_Pos) /*!< 0x00000010 */ 3758 #define RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC_Msk /*!< PLL Ready Interrupt Clear */ 3759 #define RCC_CICR_MSIRDYC_Pos (5U) 3760 #define RCC_CICR_MSIRDYC_Msk (0x1U << RCC_CICR_MSIRDYC_Pos) /*!< 0x00000020 */ 3761 #define RCC_CICR_MSIRDYC RCC_CICR_MSIRDYC_Msk /*!< MSI Ready Interrupt Clear */ 3762 #define RCC_CICR_CSSLSEC_Pos (7U) 3763 #define RCC_CICR_CSSLSEC_Msk (0x1U << RCC_CICR_CSSLSEC_Pos) /*!< 0x00000080 */ 3764 #define RCC_CICR_CSSLSEC RCC_CICR_CSSLSEC_Msk /*!< LSE Clock Security System Interrupt Clear */ 3765 #define RCC_CICR_CSSHSEC_Pos (8U) 3766 #define RCC_CICR_CSSHSEC_Msk (0x1U << RCC_CICR_CSSHSEC_Pos) /*!< 0x00000100 */ 3767 #define RCC_CICR_CSSHSEC RCC_CICR_CSSHSEC_Msk /*!< HSE Clock Security System Interrupt Clear */ 3768 3769 /* Reference defines */ 3770 #define RCC_CICR_LSECSSC RCC_CICR_CSSLSEC 3771 #define RCC_CICR_CSSC RCC_CICR_CSSHSEC 3772 /***************** Bit definition for RCC_IOPRSTR register ******************/ 3773 #define RCC_IOPRSTR_IOPARST_Pos (0U) 3774 #define RCC_IOPRSTR_IOPARST_Msk (0x1U << RCC_IOPRSTR_IOPARST_Pos) /*!< 0x00000001 */ 3775 #define RCC_IOPRSTR_IOPARST RCC_IOPRSTR_IOPARST_Msk /*!< GPIO port A reset */ 3776 #define RCC_IOPRSTR_IOPBRST_Pos (1U) 3777 #define RCC_IOPRSTR_IOPBRST_Msk (0x1U << RCC_IOPRSTR_IOPBRST_Pos) /*!< 0x00000002 */ 3778 #define RCC_IOPRSTR_IOPBRST RCC_IOPRSTR_IOPBRST_Msk /*!< GPIO port B reset */ 3779 #define RCC_IOPRSTR_IOPCRST_Pos (2U) 3780 #define RCC_IOPRSTR_IOPCRST_Msk (0x1U << RCC_IOPRSTR_IOPCRST_Pos) /*!< 0x00000004 */ 3781 #define RCC_IOPRSTR_IOPCRST RCC_IOPRSTR_IOPCRST_Msk /*!< GPIO port C reset */ 3782 #define RCC_IOPRSTR_IOPDRST_Pos (3U) 3783 #define RCC_IOPRSTR_IOPDRST_Msk (0x1U << RCC_IOPRSTR_IOPDRST_Pos) /*!< 0x00000008 */ 3784 #define RCC_IOPRSTR_IOPDRST RCC_IOPRSTR_IOPDRST_Msk /*!< GPIO port D reset */ 3785 #define RCC_IOPRSTR_IOPERST_Pos (4U) 3786 #define RCC_IOPRSTR_IOPERST_Msk (0x1U << RCC_IOPRSTR_IOPERST_Pos) /*!< 0x00000010 */ 3787 #define RCC_IOPRSTR_IOPERST RCC_IOPRSTR_IOPERST_Msk /*!< GPIO port E reset */ 3788 #define RCC_IOPRSTR_IOPHRST_Pos (7U) 3789 #define RCC_IOPRSTR_IOPHRST_Msk (0x1U << RCC_IOPRSTR_IOPHRST_Pos) /*!< 0x00000080 */ 3790 #define RCC_IOPRSTR_IOPHRST RCC_IOPRSTR_IOPHRST_Msk /*!< GPIO port H reset */ 3791 3792 /* Reference defines */ 3793 #define RCC_IOPRSTR_GPIOARST RCC_IOPRSTR_IOPARST /*!< GPIO port A reset */ 3794 #define RCC_IOPRSTR_GPIOBRST RCC_IOPRSTR_IOPBRST /*!< GPIO port B reset */ 3795 #define RCC_IOPRSTR_GPIOCRST RCC_IOPRSTR_IOPCRST /*!< GPIO port C reset */ 3796 #define RCC_IOPRSTR_GPIODRST RCC_IOPRSTR_IOPDRST /*!< GPIO port D reset */ 3797 #define RCC_IOPRSTR_GPIOERST RCC_IOPRSTR_IOPERST /*!< GPIO port E reset */ 3798 #define RCC_IOPRSTR_GPIOHRST RCC_IOPRSTR_IOPHRST /*!< GPIO port H reset */ 3799 3800 3801 /****************** Bit definition for RCC_AHBRST register ******************/ 3802 #define RCC_AHBRSTR_DMARST_Pos (0U) 3803 #define RCC_AHBRSTR_DMARST_Msk (0x1U << RCC_AHBRSTR_DMARST_Pos) /*!< 0x00000001 */ 3804 #define RCC_AHBRSTR_DMARST RCC_AHBRSTR_DMARST_Msk /*!< DMA1 reset */ 3805 #define RCC_AHBRSTR_MIFRST_Pos (8U) 3806 #define RCC_AHBRSTR_MIFRST_Msk (0x1U << RCC_AHBRSTR_MIFRST_Pos) /*!< 0x00000100 */ 3807 #define RCC_AHBRSTR_MIFRST RCC_AHBRSTR_MIFRST_Msk /*!< Memory interface reset reset */ 3808 #define RCC_AHBRSTR_CRCRST_Pos (12U) 3809 #define RCC_AHBRSTR_CRCRST_Msk (0x1U << RCC_AHBRSTR_CRCRST_Pos) /*!< 0x00001000 */ 3810 #define RCC_AHBRSTR_CRCRST RCC_AHBRSTR_CRCRST_Msk /*!< CRC reset */ 3811 #define RCC_AHBRSTR_CRYPRST_Pos (24U) 3812 #define RCC_AHBRSTR_CRYPRST_Msk (0x1U << RCC_AHBRSTR_CRYPRST_Pos) /*!< 0x01000000 */ 3813 #define RCC_AHBRSTR_CRYPRST RCC_AHBRSTR_CRYPRST_Msk /*!< Crypto reset */ 3814 3815 /* Reference defines */ 3816 #define RCC_AHBRSTR_DMA1RST RCC_AHBRSTR_DMARST /*!< DMA1 reset */ 3817 3818 /***************** Bit definition for RCC_APB2RSTR register *****************/ 3819 #define RCC_APB2RSTR_SYSCFGRST_Pos (0U) 3820 #define RCC_APB2RSTR_SYSCFGRST_Msk (0x1U << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */ 3821 #define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk /*!< SYSCFG clock reset */ 3822 #define RCC_APB2RSTR_TIM21RST_Pos (2U) 3823 #define RCC_APB2RSTR_TIM21RST_Msk (0x1U << RCC_APB2RSTR_TIM21RST_Pos) /*!< 0x00000004 */ 3824 #define RCC_APB2RSTR_TIM21RST RCC_APB2RSTR_TIM21RST_Msk /*!< TIM21 clock reset */ 3825 #define RCC_APB2RSTR_TIM22RST_Pos (5U) 3826 #define RCC_APB2RSTR_TIM22RST_Msk (0x1U << RCC_APB2RSTR_TIM22RST_Pos) /*!< 0x00000020 */ 3827 #define RCC_APB2RSTR_TIM22RST RCC_APB2RSTR_TIM22RST_Msk /*!< TIM22 clock reset */ 3828 #define RCC_APB2RSTR_ADCRST_Pos (9U) 3829 #define RCC_APB2RSTR_ADCRST_Msk (0x1U << RCC_APB2RSTR_ADCRST_Pos) /*!< 0x00000200 */ 3830 #define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk /*!< ADC1 clock reset */ 3831 #define RCC_APB2RSTR_SPI1RST_Pos (12U) 3832 #define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */ 3833 #define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI1 clock reset */ 3834 #define RCC_APB2RSTR_USART1RST_Pos (14U) 3835 #define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */ 3836 #define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 clock reset */ 3837 #define RCC_APB2RSTR_DBGRST_Pos (22U) 3838 #define RCC_APB2RSTR_DBGRST_Msk (0x1U << RCC_APB2RSTR_DBGRST_Pos) /*!< 0x00400000 */ 3839 #define RCC_APB2RSTR_DBGRST RCC_APB2RSTR_DBGRST_Msk /*!< DBGMCU clock reset */ 3840 3841 /* Reference defines */ 3842 #define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADCRST /*!< ADC1 clock reset */ 3843 #define RCC_APB2RSTR_DBGMCURST RCC_APB2RSTR_DBGRST /*!< DBGMCU clock reset */ 3844 3845 /***************** Bit definition for RCC_APB1RSTR register *****************/ 3846 #define RCC_APB1RSTR_TIM2RST_Pos (0U) 3847 #define RCC_APB1RSTR_TIM2RST_Msk (0x1U << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */ 3848 #define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk /*!< Timer 2 clock reset */ 3849 #define RCC_APB1RSTR_TIM3RST_Pos (1U) 3850 #define RCC_APB1RSTR_TIM3RST_Msk (0x1U << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */ 3851 #define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk /*!< Timer 3 clock reset */ 3852 #define RCC_APB1RSTR_TIM6RST_Pos (4U) 3853 #define RCC_APB1RSTR_TIM6RST_Msk (0x1U << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */ 3854 #define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk /*!< Timer 6 clock reset */ 3855 #define RCC_APB1RSTR_TIM7RST_Pos (5U) 3856 #define RCC_APB1RSTR_TIM7RST_Msk (0x1U << RCC_APB1RSTR_TIM7RST_Pos) /*!< 0x00000020 */ 3857 #define RCC_APB1RSTR_TIM7RST RCC_APB1RSTR_TIM7RST_Msk /*!< Timer 7 clock reset */ 3858 #define RCC_APB1RSTR_WWDGRST_Pos (11U) 3859 #define RCC_APB1RSTR_WWDGRST_Msk (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */ 3860 #define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog clock reset */ 3861 #define RCC_APB1RSTR_SPI2RST_Pos (14U) 3862 #define RCC_APB1RSTR_SPI2RST_Msk (0x1U << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */ 3863 #define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk /*!< SPI2 clock reset */ 3864 #define RCC_APB1RSTR_USART2RST_Pos (17U) 3865 #define RCC_APB1RSTR_USART2RST_Msk (0x1U << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */ 3866 #define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /*!< USART 2 clock reset */ 3867 #define RCC_APB1RSTR_LPUART1RST_Pos (18U) 3868 #define RCC_APB1RSTR_LPUART1RST_Msk (0x1U << RCC_APB1RSTR_LPUART1RST_Pos) /*!< 0x00040000 */ 3869 #define RCC_APB1RSTR_LPUART1RST RCC_APB1RSTR_LPUART1RST_Msk /*!< LPUART1 clock reset */ 3870 #define RCC_APB1RSTR_USART4RST_Pos (19U) 3871 #define RCC_APB1RSTR_USART4RST_Msk (0x1U << RCC_APB1RSTR_USART4RST_Pos) /*!< 0x00080000 */ 3872 #define RCC_APB1RSTR_USART4RST RCC_APB1RSTR_USART4RST_Msk /*!< USART4 clock reset */ 3873 #define RCC_APB1RSTR_USART5RST_Pos (20U) 3874 #define RCC_APB1RSTR_USART5RST_Msk (0x1U << RCC_APB1RSTR_USART5RST_Pos) /*!< 0x00100000 */ 3875 #define RCC_APB1RSTR_USART5RST RCC_APB1RSTR_USART5RST_Msk /*!< USART5 clock reset */ 3876 #define RCC_APB1RSTR_I2C1RST_Pos (21U) 3877 #define RCC_APB1RSTR_I2C1RST_Msk (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */ 3878 #define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 1 clock reset */ 3879 #define RCC_APB1RSTR_I2C2RST_Pos (22U) 3880 #define RCC_APB1RSTR_I2C2RST_Msk (0x1U << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */ 3881 #define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk /*!< I2C 2 clock reset */ 3882 #define RCC_APB1RSTR_PWRRST_Pos (28U) 3883 #define RCC_APB1RSTR_PWRRST_Msk (0x1U << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */ 3884 #define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /*!< PWR clock reset */ 3885 #define RCC_APB1RSTR_I2C3RST_Pos (30U) 3886 #define RCC_APB1RSTR_I2C3RST_Msk (0x1U << RCC_APB1RSTR_I2C3RST_Pos) /*!< 0x40000000 */ 3887 #define RCC_APB1RSTR_I2C3RST RCC_APB1RSTR_I2C3RST_Msk /*!< I2C 3 clock reset */ 3888 #define RCC_APB1RSTR_LPTIM1RST_Pos (31U) 3889 #define RCC_APB1RSTR_LPTIM1RST_Msk (0x1U << RCC_APB1RSTR_LPTIM1RST_Pos) /*!< 0x80000000 */ 3890 #define RCC_APB1RSTR_LPTIM1RST RCC_APB1RSTR_LPTIM1RST_Msk /*!< LPTIM1 clock reset */ 3891 3892 /***************** Bit definition for RCC_IOPENR register ******************/ 3893 #define RCC_IOPENR_IOPAEN_Pos (0U) 3894 #define RCC_IOPENR_IOPAEN_Msk (0x1U << RCC_IOPENR_IOPAEN_Pos) /*!< 0x00000001 */ 3895 #define RCC_IOPENR_IOPAEN RCC_IOPENR_IOPAEN_Msk /*!< GPIO port A clock enable */ 3896 #define RCC_IOPENR_IOPBEN_Pos (1U) 3897 #define RCC_IOPENR_IOPBEN_Msk (0x1U << RCC_IOPENR_IOPBEN_Pos) /*!< 0x00000002 */ 3898 #define RCC_IOPENR_IOPBEN RCC_IOPENR_IOPBEN_Msk /*!< GPIO port B clock enable */ 3899 #define RCC_IOPENR_IOPCEN_Pos (2U) 3900 #define RCC_IOPENR_IOPCEN_Msk (0x1U << RCC_IOPENR_IOPCEN_Pos) /*!< 0x00000004 */ 3901 #define RCC_IOPENR_IOPCEN RCC_IOPENR_IOPCEN_Msk /*!< GPIO port C clock enable */ 3902 #define RCC_IOPENR_IOPDEN_Pos (3U) 3903 #define RCC_IOPENR_IOPDEN_Msk (0x1U << RCC_IOPENR_IOPDEN_Pos) /*!< 0x00000008 */ 3904 #define RCC_IOPENR_IOPDEN RCC_IOPENR_IOPDEN_Msk /*!< GPIO port D clock enable */ 3905 #define RCC_IOPENR_IOPEEN_Pos (4U) 3906 #define RCC_IOPENR_IOPEEN_Msk (0x1U << RCC_IOPENR_IOPEEN_Pos) /*!< 0x00000010 */ 3907 #define RCC_IOPENR_IOPEEN RCC_IOPENR_IOPEEN_Msk /*!< GPIO port E clock enable */ 3908 #define RCC_IOPENR_IOPHEN_Pos (7U) 3909 #define RCC_IOPENR_IOPHEN_Msk (0x1U << RCC_IOPENR_IOPHEN_Pos) /*!< 0x00000080 */ 3910 #define RCC_IOPENR_IOPHEN RCC_IOPENR_IOPHEN_Msk /*!< GPIO port H clock enable */ 3911 3912 /* Reference defines */ 3913 #define RCC_IOPENR_GPIOAEN RCC_IOPENR_IOPAEN /*!< GPIO port A clock enable */ 3914 #define RCC_IOPENR_GPIOBEN RCC_IOPENR_IOPBEN /*!< GPIO port B clock enable */ 3915 #define RCC_IOPENR_GPIOCEN RCC_IOPENR_IOPCEN /*!< GPIO port C clock enable */ 3916 #define RCC_IOPENR_GPIODEN RCC_IOPENR_IOPDEN /*!< GPIO port D clock enable */ 3917 #define RCC_IOPENR_GPIOEEN RCC_IOPENR_IOPEEN /*!< GPIO port E clock enable */ 3918 #define RCC_IOPENR_GPIOHEN RCC_IOPENR_IOPHEN /*!< GPIO port H clock enable */ 3919 3920 /***************** Bit definition for RCC_AHBENR register ******************/ 3921 #define RCC_AHBENR_DMAEN_Pos (0U) 3922 #define RCC_AHBENR_DMAEN_Msk (0x1U << RCC_AHBENR_DMAEN_Pos) /*!< 0x00000001 */ 3923 #define RCC_AHBENR_DMAEN RCC_AHBENR_DMAEN_Msk /*!< DMA1 clock enable */ 3924 #define RCC_AHBENR_MIFEN_Pos (8U) 3925 #define RCC_AHBENR_MIFEN_Msk (0x1U << RCC_AHBENR_MIFEN_Pos) /*!< 0x00000100 */ 3926 #define RCC_AHBENR_MIFEN RCC_AHBENR_MIFEN_Msk /*!< NVM interface clock enable bit */ 3927 #define RCC_AHBENR_CRCEN_Pos (12U) 3928 #define RCC_AHBENR_CRCEN_Msk (0x1U << RCC_AHBENR_CRCEN_Pos) /*!< 0x00001000 */ 3929 #define RCC_AHBENR_CRCEN RCC_AHBENR_CRCEN_Msk /*!< CRC clock enable */ 3930 #define RCC_AHBENR_CRYPEN_Pos (24U) 3931 #define RCC_AHBENR_CRYPEN_Msk (0x1U << RCC_AHBENR_CRYPEN_Pos) /*!< 0x01000000 */ 3932 #define RCC_AHBENR_CRYPEN RCC_AHBENR_CRYPEN_Msk /*!< Crypto clock enable*/ 3933 3934 /* Reference defines */ 3935 #define RCC_AHBENR_DMA1EN RCC_AHBENR_DMAEN /*!< DMA1 clock enable */ 3936 3937 /***************** Bit definition for RCC_APB2ENR register ******************/ 3938 #define RCC_APB2ENR_SYSCFGEN_Pos (0U) 3939 #define RCC_APB2ENR_SYSCFGEN_Msk (0x1U << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00000001 */ 3940 #define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk /*!< SYSCFG clock enable */ 3941 #define RCC_APB2ENR_TIM21EN_Pos (2U) 3942 #define RCC_APB2ENR_TIM21EN_Msk (0x1U << RCC_APB2ENR_TIM21EN_Pos) /*!< 0x00000004 */ 3943 #define RCC_APB2ENR_TIM21EN RCC_APB2ENR_TIM21EN_Msk /*!< TIM21 clock enable */ 3944 #define RCC_APB2ENR_TIM22EN_Pos (5U) 3945 #define RCC_APB2ENR_TIM22EN_Msk (0x1U << RCC_APB2ENR_TIM22EN_Pos) /*!< 0x00000020 */ 3946 #define RCC_APB2ENR_TIM22EN RCC_APB2ENR_TIM22EN_Msk /*!< TIM22 clock enable */ 3947 #define RCC_APB2ENR_FWEN_Pos (7U) 3948 #define RCC_APB2ENR_FWEN_Msk (0x1U << RCC_APB2ENR_FWEN_Pos) /*!< 0x00000080 */ 3949 #define RCC_APB2ENR_FWEN RCC_APB2ENR_FWEN_Msk /*!< MiFare Firewall clock enable */ 3950 #define RCC_APB2ENR_ADCEN_Pos (9U) 3951 #define RCC_APB2ENR_ADCEN_Msk (0x1U << RCC_APB2ENR_ADCEN_Pos) /*!< 0x00000200 */ 3952 #define RCC_APB2ENR_ADCEN RCC_APB2ENR_ADCEN_Msk /*!< ADC1 clock enable */ 3953 #define RCC_APB2ENR_SPI1EN_Pos (12U) 3954 #define RCC_APB2ENR_SPI1EN_Msk (0x1U << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */ 3955 #define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk /*!< SPI1 clock enable */ 3956 #define RCC_APB2ENR_USART1EN_Pos (14U) 3957 #define RCC_APB2ENR_USART1EN_Msk (0x1U << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */ 3958 #define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk /*!< USART1 clock enable */ 3959 #define RCC_APB2ENR_DBGEN_Pos (22U) 3960 #define RCC_APB2ENR_DBGEN_Msk (0x1U << RCC_APB2ENR_DBGEN_Pos) /*!< 0x00400000 */ 3961 #define RCC_APB2ENR_DBGEN RCC_APB2ENR_DBGEN_Msk /*!< DBGMCU clock enable */ 3962 3963 /* Reference defines */ 3964 3965 #define RCC_APB2ENR_MIFIEN RCC_APB2ENR_FWEN /*!< MiFare Firewall clock enable */ 3966 #define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADCEN /*!< ADC1 clock enable */ 3967 #define RCC_APB2ENR_DBGMCUEN RCC_APB2ENR_DBGEN /*!< DBGMCU clock enable */ 3968 3969 /***************** Bit definition for RCC_APB1ENR register ******************/ 3970 #define RCC_APB1ENR_TIM2EN_Pos (0U) 3971 #define RCC_APB1ENR_TIM2EN_Msk (0x1U << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */ 3972 #define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk /*!< Timer 2 clock enable */ 3973 #define RCC_APB1ENR_TIM3EN_Pos (1U) 3974 #define RCC_APB1ENR_TIM3EN_Msk (0x1U << RCC_APB1ENR_TIM3EN_Pos) /*!< 0x00000002 */ 3975 #define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk /*!< Timer 3 clock enable */ 3976 #define RCC_APB1ENR_TIM6EN_Pos (4U) 3977 #define RCC_APB1ENR_TIM6EN_Msk (0x1U << RCC_APB1ENR_TIM6EN_Pos) /*!< 0x00000010 */ 3978 #define RCC_APB1ENR_TIM6EN RCC_APB1ENR_TIM6EN_Msk /*!< Timer 6 clock enable */ 3979 #define RCC_APB1ENR_TIM7EN_Pos (5U) 3980 #define RCC_APB1ENR_TIM7EN_Msk (0x1U << RCC_APB1ENR_TIM7EN_Pos) /*!< 0x00000020 */ 3981 #define RCC_APB1ENR_TIM7EN RCC_APB1ENR_TIM7EN_Msk /*!< Timer 7 clock enable */ 3982 #define RCC_APB1ENR_WWDGEN_Pos (11U) 3983 #define RCC_APB1ENR_WWDGEN_Msk (0x1U << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */ 3984 #define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk /*!< Window Watchdog clock enable */ 3985 #define RCC_APB1ENR_SPI2EN_Pos (14U) 3986 #define RCC_APB1ENR_SPI2EN_Msk (0x1U << RCC_APB1ENR_SPI2EN_Pos) /*!< 0x00004000 */ 3987 #define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk /*!< SPI2 clock enable */ 3988 #define RCC_APB1ENR_USART2EN_Pos (17U) 3989 #define RCC_APB1ENR_USART2EN_Msk (0x1U << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */ 3990 #define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk /*!< USART2 clock enable */ 3991 #define RCC_APB1ENR_LPUART1EN_Pos (18U) 3992 #define RCC_APB1ENR_LPUART1EN_Msk (0x1U << RCC_APB1ENR_LPUART1EN_Pos) /*!< 0x00040000 */ 3993 #define RCC_APB1ENR_LPUART1EN RCC_APB1ENR_LPUART1EN_Msk /*!< LPUART1 clock enable */ 3994 #define RCC_APB1ENR_USART4EN_Pos (19U) 3995 #define RCC_APB1ENR_USART4EN_Msk (0x1U << RCC_APB1ENR_USART4EN_Pos) /*!< 0x00080000 */ 3996 #define RCC_APB1ENR_USART4EN RCC_APB1ENR_USART4EN_Msk /*!< USART4 clock enable */ 3997 #define RCC_APB1ENR_USART5EN_Pos (20U) 3998 #define RCC_APB1ENR_USART5EN_Msk (0x1U << RCC_APB1ENR_USART5EN_Pos) /*!< 0x00100000 */ 3999 #define RCC_APB1ENR_USART5EN RCC_APB1ENR_USART5EN_Msk /*!< USART5 clock enable */ 4000 #define RCC_APB1ENR_I2C1EN_Pos (21U) 4001 #define RCC_APB1ENR_I2C1EN_Msk (0x1U << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */ 4002 #define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk /*!< I2C1 clock enable */ 4003 #define RCC_APB1ENR_I2C2EN_Pos (22U) 4004 #define RCC_APB1ENR_I2C2EN_Msk (0x1U << RCC_APB1ENR_I2C2EN_Pos) /*!< 0x00400000 */ 4005 #define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk /*!< I2C2 clock enable */ 4006 #define RCC_APB1ENR_PWREN_Pos (28U) 4007 #define RCC_APB1ENR_PWREN_Msk (0x1U << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */ 4008 #define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk /*!< PWR clock enable */ 4009 #define RCC_APB1ENR_I2C3EN_Pos (30U) 4010 #define RCC_APB1ENR_I2C3EN_Msk (0x1U << RCC_APB1ENR_I2C3EN_Pos) /*!< 0x40000000 */ 4011 #define RCC_APB1ENR_I2C3EN RCC_APB1ENR_I2C3EN_Msk /*!< I2C3 clock enable */ 4012 #define RCC_APB1ENR_LPTIM1EN_Pos (31U) 4013 #define RCC_APB1ENR_LPTIM1EN_Msk (0x1U << RCC_APB1ENR_LPTIM1EN_Pos) /*!< 0x80000000 */ 4014 #define RCC_APB1ENR_LPTIM1EN RCC_APB1ENR_LPTIM1EN_Msk /*!< LPTIM1 clock enable */ 4015 4016 /****************** Bit definition for RCC_IOPSMENR register ****************/ 4017 #define RCC_IOPSMENR_IOPASMEN_Pos (0U) 4018 #define RCC_IOPSMENR_IOPASMEN_Msk (0x1U << RCC_IOPSMENR_IOPASMEN_Pos) /*!< 0x00000001 */ 4019 #define RCC_IOPSMENR_IOPASMEN RCC_IOPSMENR_IOPASMEN_Msk /*!< GPIO port A clock enabled in sleep mode */ 4020 #define RCC_IOPSMENR_IOPBSMEN_Pos (1U) 4021 #define RCC_IOPSMENR_IOPBSMEN_Msk (0x1U << RCC_IOPSMENR_IOPBSMEN_Pos) /*!< 0x00000002 */ 4022 #define RCC_IOPSMENR_IOPBSMEN RCC_IOPSMENR_IOPBSMEN_Msk /*!< GPIO port B clock enabled in sleep mode */ 4023 #define RCC_IOPSMENR_IOPCSMEN_Pos (2U) 4024 #define RCC_IOPSMENR_IOPCSMEN_Msk (0x1U << RCC_IOPSMENR_IOPCSMEN_Pos) /*!< 0x00000004 */ 4025 #define RCC_IOPSMENR_IOPCSMEN RCC_IOPSMENR_IOPCSMEN_Msk /*!< GPIO port C clock enabled in sleep mode */ 4026 #define RCC_IOPSMENR_IOPDSMEN_Pos (3U) 4027 #define RCC_IOPSMENR_IOPDSMEN_Msk (0x1U << RCC_IOPSMENR_IOPDSMEN_Pos) /*!< 0x00000008 */ 4028 #define RCC_IOPSMENR_IOPDSMEN RCC_IOPSMENR_IOPDSMEN_Msk /*!< GPIO port D clock enabled in sleep mode */ 4029 #define RCC_IOPSMENR_IOPESMEN_Pos (4U) 4030 #define RCC_IOPSMENR_IOPESMEN_Msk (0x1U << RCC_IOPSMENR_IOPESMEN_Pos) /*!< 0x00000010 */ 4031 #define RCC_IOPSMENR_IOPESMEN RCC_IOPSMENR_IOPESMEN_Msk /*!< GPIO port E clock enabled in sleep mode */ 4032 #define RCC_IOPSMENR_IOPHSMEN_Pos (7U) 4033 #define RCC_IOPSMENR_IOPHSMEN_Msk (0x1U << RCC_IOPSMENR_IOPHSMEN_Pos) /*!< 0x00000080 */ 4034 #define RCC_IOPSMENR_IOPHSMEN RCC_IOPSMENR_IOPHSMEN_Msk /*!< GPIO port H clock enabled in sleep mode */ 4035 4036 /* Reference defines */ 4037 #define RCC_IOPSMENR_GPIOASMEN RCC_IOPSMENR_IOPASMEN /*!< GPIO port A clock enabled in sleep mode */ 4038 #define RCC_IOPSMENR_GPIOBSMEN RCC_IOPSMENR_IOPBSMEN /*!< GPIO port B clock enabled in sleep mode */ 4039 #define RCC_IOPSMENR_GPIOCSMEN RCC_IOPSMENR_IOPCSMEN /*!< GPIO port C clock enabled in sleep mode */ 4040 #define RCC_IOPSMENR_GPIODSMEN RCC_IOPSMENR_IOPDSMEN /*!< GPIO port D clock enabled in sleep mode */ 4041 #define RCC_IOPSMENR_GPIOESMEN RCC_IOPSMENR_IOPESMEN /*!< GPIO port E clock enabled in sleep mode */ 4042 #define RCC_IOPSMENR_GPIOHSMEN RCC_IOPSMENR_IOPHSMEN /*!< GPIO port H clock enabled in sleep mode */ 4043 4044 /***************** Bit definition for RCC_AHBSMENR register ******************/ 4045 #define RCC_AHBSMENR_DMASMEN_Pos (0U) 4046 #define RCC_AHBSMENR_DMASMEN_Msk (0x1U << RCC_AHBSMENR_DMASMEN_Pos) /*!< 0x00000001 */ 4047 #define RCC_AHBSMENR_DMASMEN RCC_AHBSMENR_DMASMEN_Msk /*!< DMA1 clock enabled in sleep mode */ 4048 #define RCC_AHBSMENR_MIFSMEN_Pos (8U) 4049 #define RCC_AHBSMENR_MIFSMEN_Msk (0x1U << RCC_AHBSMENR_MIFSMEN_Pos) /*!< 0x00000100 */ 4050 #define RCC_AHBSMENR_MIFSMEN RCC_AHBSMENR_MIFSMEN_Msk /*!< NVM interface clock enable during sleep mode */ 4051 #define RCC_AHBSMENR_SRAMSMEN_Pos (9U) 4052 #define RCC_AHBSMENR_SRAMSMEN_Msk (0x1U << RCC_AHBSMENR_SRAMSMEN_Pos) /*!< 0x00000200 */ 4053 #define RCC_AHBSMENR_SRAMSMEN RCC_AHBSMENR_SRAMSMEN_Msk /*!< SRAM clock enabled in sleep mode */ 4054 #define RCC_AHBSMENR_CRCSMEN_Pos (12U) 4055 #define RCC_AHBSMENR_CRCSMEN_Msk (0x1U << RCC_AHBSMENR_CRCSMEN_Pos) /*!< 0x00001000 */ 4056 #define RCC_AHBSMENR_CRCSMEN RCC_AHBSMENR_CRCSMEN_Msk /*!< CRC clock enabled in sleep mode */ 4057 #define RCC_AHBSMENR_CRYPSMEN_Pos (24U) 4058 #define RCC_AHBSMENR_CRYPSMEN_Msk (0x1U << RCC_AHBSMENR_CRYPSMEN_Pos) /*!< 0x01000000 */ 4059 #define RCC_AHBSMENR_CRYPSMEN RCC_AHBSMENR_CRYPSMEN_Msk /*!< Crypto clock enabled in sleep mode */ 4060 4061 /* Reference defines */ 4062 #define RCC_AHBSMENR_DMA1SMEN RCC_AHBSMENR_DMASMEN /*!< DMA1 clock enabled in sleep mode */ 4063 4064 /***************** Bit definition for RCC_APB2SMENR register ******************/ 4065 #define RCC_APB2SMENR_SYSCFGSMEN_Pos (0U) 4066 #define RCC_APB2SMENR_SYSCFGSMEN_Msk (0x1U << RCC_APB2SMENR_SYSCFGSMEN_Pos) /*!< 0x00000001 */ 4067 #define RCC_APB2SMENR_SYSCFGSMEN RCC_APB2SMENR_SYSCFGSMEN_Msk /*!< SYSCFG clock enabled in sleep mode */ 4068 #define RCC_APB2SMENR_TIM21SMEN_Pos (2U) 4069 #define RCC_APB2SMENR_TIM21SMEN_Msk (0x1U << RCC_APB2SMENR_TIM21SMEN_Pos) /*!< 0x00000004 */ 4070 #define RCC_APB2SMENR_TIM21SMEN RCC_APB2SMENR_TIM21SMEN_Msk /*!< TIM21 clock enabled in sleep mode */ 4071 #define RCC_APB2SMENR_TIM22SMEN_Pos (5U) 4072 #define RCC_APB2SMENR_TIM22SMEN_Msk (0x1U << RCC_APB2SMENR_TIM22SMEN_Pos) /*!< 0x00000020 */ 4073 #define RCC_APB2SMENR_TIM22SMEN RCC_APB2SMENR_TIM22SMEN_Msk /*!< TIM22 clock enabled in sleep mode */ 4074 #define RCC_APB2SMENR_ADCSMEN_Pos (9U) 4075 #define RCC_APB2SMENR_ADCSMEN_Msk (0x1U << RCC_APB2SMENR_ADCSMEN_Pos) /*!< 0x00000200 */ 4076 #define RCC_APB2SMENR_ADCSMEN RCC_APB2SMENR_ADCSMEN_Msk /*!< ADC1 clock enabled in sleep mode */ 4077 #define RCC_APB2SMENR_SPI1SMEN_Pos (12U) 4078 #define RCC_APB2SMENR_SPI1SMEN_Msk (0x1U << RCC_APB2SMENR_SPI1SMEN_Pos) /*!< 0x00001000 */ 4079 #define RCC_APB2SMENR_SPI1SMEN RCC_APB2SMENR_SPI1SMEN_Msk /*!< SPI1 clock enabled in sleep mode */ 4080 #define RCC_APB2SMENR_USART1SMEN_Pos (14U) 4081 #define RCC_APB2SMENR_USART1SMEN_Msk (0x1U << RCC_APB2SMENR_USART1SMEN_Pos) /*!< 0x00004000 */ 4082 #define RCC_APB2SMENR_USART1SMEN RCC_APB2SMENR_USART1SMEN_Msk /*!< USART1 clock enabled in sleep mode */ 4083 #define RCC_APB2SMENR_DBGSMEN_Pos (22U) 4084 #define RCC_APB2SMENR_DBGSMEN_Msk (0x1U << RCC_APB2SMENR_DBGSMEN_Pos) /*!< 0x00400000 */ 4085 #define RCC_APB2SMENR_DBGSMEN RCC_APB2SMENR_DBGSMEN_Msk /*!< DBGMCU clock enabled in sleep mode */ 4086 4087 /* Reference defines */ 4088 #define RCC_APB2SMENR_ADC1SMEN RCC_APB2SMENR_ADCSMEN /*!< ADC1 clock enabled in sleep mode */ 4089 #define RCC_APB2SMENR_DBGMCUSMEN RCC_APB2SMENR_DBGSMEN /*!< DBGMCU clock enabled in sleep mode */ 4090 4091 /***************** Bit definition for RCC_APB1SMENR register ******************/ 4092 #define RCC_APB1SMENR_TIM2SMEN_Pos (0U) 4093 #define RCC_APB1SMENR_TIM2SMEN_Msk (0x1U << RCC_APB1SMENR_TIM2SMEN_Pos) /*!< 0x00000001 */ 4094 #define RCC_APB1SMENR_TIM2SMEN RCC_APB1SMENR_TIM2SMEN_Msk /*!< Timer 2 clock enabled in sleep mode */ 4095 #define RCC_APB1SMENR_TIM3SMEN_Pos (1U) 4096 #define RCC_APB1SMENR_TIM3SMEN_Msk (0x1U << RCC_APB1SMENR_TIM3SMEN_Pos) /*!< 0x00000002 */ 4097 #define RCC_APB1SMENR_TIM3SMEN RCC_APB1SMENR_TIM3SMEN_Msk /*!< Timer 3 clock enabled in sleep mode */ 4098 #define RCC_APB1SMENR_TIM6SMEN_Pos (4U) 4099 #define RCC_APB1SMENR_TIM6SMEN_Msk (0x1U << RCC_APB1SMENR_TIM6SMEN_Pos) /*!< 0x00000010 */ 4100 #define RCC_APB1SMENR_TIM6SMEN RCC_APB1SMENR_TIM6SMEN_Msk /*!< Timer 6 clock enabled in sleep mode */ 4101 #define RCC_APB1SMENR_TIM7SMEN_Pos (5U) 4102 #define RCC_APB1SMENR_TIM7SMEN_Msk (0x1U << RCC_APB1SMENR_TIM7SMEN_Pos) /*!< 0x00000020 */ 4103 #define RCC_APB1SMENR_TIM7SMEN RCC_APB1SMENR_TIM7SMEN_Msk /*!< Timer 7 clock enabled in sleep mode */ 4104 #define RCC_APB1SMENR_WWDGSMEN_Pos (11U) 4105 #define RCC_APB1SMENR_WWDGSMEN_Msk (0x1U << RCC_APB1SMENR_WWDGSMEN_Pos) /*!< 0x00000800 */ 4106 #define RCC_APB1SMENR_WWDGSMEN RCC_APB1SMENR_WWDGSMEN_Msk /*!< Window Watchdog clock enabled in sleep mode */ 4107 #define RCC_APB1SMENR_SPI2SMEN_Pos (14U) 4108 #define RCC_APB1SMENR_SPI2SMEN_Msk (0x1U << RCC_APB1SMENR_SPI2SMEN_Pos) /*!< 0x00004000 */ 4109 #define RCC_APB1SMENR_SPI2SMEN RCC_APB1SMENR_SPI2SMEN_Msk /*!< SPI2 clock enabled in sleep mode */ 4110 #define RCC_APB1SMENR_USART2SMEN_Pos (17U) 4111 #define RCC_APB1SMENR_USART2SMEN_Msk (0x1U << RCC_APB1SMENR_USART2SMEN_Pos) /*!< 0x00020000 */ 4112 #define RCC_APB1SMENR_USART2SMEN RCC_APB1SMENR_USART2SMEN_Msk /*!< USART2 clock enabled in sleep mode */ 4113 #define RCC_APB1SMENR_LPUART1SMEN_Pos (18U) 4114 #define RCC_APB1SMENR_LPUART1SMEN_Msk (0x1U << RCC_APB1SMENR_LPUART1SMEN_Pos) /*!< 0x00040000 */ 4115 #define RCC_APB1SMENR_LPUART1SMEN RCC_APB1SMENR_LPUART1SMEN_Msk /*!< LPUART1 clock enabled in sleep mode */ 4116 #define RCC_APB1SMENR_USART4SMEN_Pos (19U) 4117 #define RCC_APB1SMENR_USART4SMEN_Msk (0x1U << RCC_APB1SMENR_USART4SMEN_Pos) /*!< 0x00080000 */ 4118 #define RCC_APB1SMENR_USART4SMEN RCC_APB1SMENR_USART4SMEN_Msk /*!< USART4 clock enabled in sleep mode */ 4119 #define RCC_APB1SMENR_USART5SMEN_Pos (20U) 4120 #define RCC_APB1SMENR_USART5SMEN_Msk (0x1U << RCC_APB1SMENR_USART5SMEN_Pos) /*!< 0x00100000 */ 4121 #define RCC_APB1SMENR_USART5SMEN RCC_APB1SMENR_USART5SMEN_Msk /*!< USART5 clock enabled in sleep mode */ 4122 #define RCC_APB1SMENR_I2C1SMEN_Pos (21U) 4123 #define RCC_APB1SMENR_I2C1SMEN_Msk (0x1U << RCC_APB1SMENR_I2C1SMEN_Pos) /*!< 0x00200000 */ 4124 #define RCC_APB1SMENR_I2C1SMEN RCC_APB1SMENR_I2C1SMEN_Msk /*!< I2C1 clock enabled in sleep mode */ 4125 #define RCC_APB1SMENR_I2C2SMEN_Pos (22U) 4126 #define RCC_APB1SMENR_I2C2SMEN_Msk (0x1U << RCC_APB1SMENR_I2C2SMEN_Pos) /*!< 0x00400000 */ 4127 #define RCC_APB1SMENR_I2C2SMEN RCC_APB1SMENR_I2C2SMEN_Msk /*!< I2C2 clock enabled in sleep mode */ 4128 #define RCC_APB1SMENR_PWRSMEN_Pos (28U) 4129 #define RCC_APB1SMENR_PWRSMEN_Msk (0x1U << RCC_APB1SMENR_PWRSMEN_Pos) /*!< 0x10000000 */ 4130 #define RCC_APB1SMENR_PWRSMEN RCC_APB1SMENR_PWRSMEN_Msk /*!< PWR clock enabled in sleep mode */ 4131 #define RCC_APB1SMENR_I2C3SMEN_Pos (30U) 4132 #define RCC_APB1SMENR_I2C3SMEN_Msk (0x1U << RCC_APB1SMENR_I2C3SMEN_Pos) /*!< 0x40000000 */ 4133 #define RCC_APB1SMENR_I2C3SMEN RCC_APB1SMENR_I2C3SMEN_Msk /*!< I2C3 clock enabled in sleep mode */ 4134 #define RCC_APB1SMENR_LPTIM1SMEN_Pos (31U) 4135 #define RCC_APB1SMENR_LPTIM1SMEN_Msk (0x1U << RCC_APB1SMENR_LPTIM1SMEN_Pos) /*!< 0x80000000 */ 4136 #define RCC_APB1SMENR_LPTIM1SMEN RCC_APB1SMENR_LPTIM1SMEN_Msk /*!< LPTIM1 clock enabled in sleep mode */ 4137 4138 /******************* Bit definition for RCC_CCIPR register *******************/ 4139 /*!< USART1 Clock source selection */ 4140 #define RCC_CCIPR_USART1SEL_Pos (0U) 4141 #define RCC_CCIPR_USART1SEL_Msk (0x3U << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000003 */ 4142 #define RCC_CCIPR_USART1SEL RCC_CCIPR_USART1SEL_Msk /*!< USART1SEL[1:0] bits */ 4143 #define RCC_CCIPR_USART1SEL_0 (0x1U << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000001 */ 4144 #define RCC_CCIPR_USART1SEL_1 (0x2U << RCC_CCIPR_USART1SEL_Pos) /*!< 0x00000002 */ 4145 4146 /*!< USART2 Clock source selection */ 4147 #define RCC_CCIPR_USART2SEL_Pos (2U) 4148 #define RCC_CCIPR_USART2SEL_Msk (0x3U << RCC_CCIPR_USART2SEL_Pos) /*!< 0x0000000C */ 4149 #define RCC_CCIPR_USART2SEL RCC_CCIPR_USART2SEL_Msk /*!< USART2SEL[1:0] bits */ 4150 #define RCC_CCIPR_USART2SEL_0 (0x1U << RCC_CCIPR_USART2SEL_Pos) /*!< 0x00000004 */ 4151 #define RCC_CCIPR_USART2SEL_1 (0x2U << RCC_CCIPR_USART2SEL_Pos) /*!< 0x00000008 */ 4152 4153 /*!< LPUART1 Clock source selection */ 4154 #define RCC_CCIPR_LPUART1SEL_Pos (10U) 4155 #define RCC_CCIPR_LPUART1SEL_Msk (0x3U << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x00000C00 */ 4156 #define RCC_CCIPR_LPUART1SEL RCC_CCIPR_LPUART1SEL_Msk /*!< LPUART1SEL[1:0] bits */ 4157 #define RCC_CCIPR_LPUART1SEL_0 (0x1U << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x0000400 */ 4158 #define RCC_CCIPR_LPUART1SEL_1 (0x2U << RCC_CCIPR_LPUART1SEL_Pos) /*!< 0x0000800 */ 4159 4160 /*!< I2C1 Clock source selection */ 4161 #define RCC_CCIPR_I2C1SEL_Pos (12U) 4162 #define RCC_CCIPR_I2C1SEL_Msk (0x3U << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00003000 */ 4163 #define RCC_CCIPR_I2C1SEL RCC_CCIPR_I2C1SEL_Msk /*!< I2C1SEL [1:0] bits */ 4164 #define RCC_CCIPR_I2C1SEL_0 (0x1U << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00001000 */ 4165 #define RCC_CCIPR_I2C1SEL_1 (0x2U << RCC_CCIPR_I2C1SEL_Pos) /*!< 0x00002000 */ 4166 4167 /*!< I2C3 Clock source selection */ 4168 #define RCC_CCIPR_I2C3SEL_Pos (16U) 4169 #define RCC_CCIPR_I2C3SEL_Msk (0x3U << RCC_CCIPR_I2C3SEL_Pos) /*!< 0x00030000 */ 4170 #define RCC_CCIPR_I2C3SEL RCC_CCIPR_I2C3SEL_Msk /*!< I2C3SEL [1:0] bits */ 4171 #define RCC_CCIPR_I2C3SEL_0 (0x1U << RCC_CCIPR_I2C3SEL_Pos) /*!< 0x00010000 */ 4172 #define RCC_CCIPR_I2C3SEL_1 (0x2U << RCC_CCIPR_I2C3SEL_Pos) /*!< 0x00020000 */ 4173 4174 /*!< LPTIM1 Clock source selection */ 4175 #define RCC_CCIPR_LPTIM1SEL_Pos (18U) 4176 #define RCC_CCIPR_LPTIM1SEL_Msk (0x3U << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x000C0000 */ 4177 #define RCC_CCIPR_LPTIM1SEL RCC_CCIPR_LPTIM1SEL_Msk /*!< LPTIM1SEL [1:0] bits */ 4178 #define RCC_CCIPR_LPTIM1SEL_0 (0x1U << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x00040000 */ 4179 #define RCC_CCIPR_LPTIM1SEL_1 (0x2U << RCC_CCIPR_LPTIM1SEL_Pos) /*!< 0x00080000 */ 4180 4181 /******************* Bit definition for RCC_CSR register *******************/ 4182 #define RCC_CSR_LSION_Pos (0U) 4183 #define RCC_CSR_LSION_Msk (0x1U << RCC_CSR_LSION_Pos) /*!< 0x00000001 */ 4184 #define RCC_CSR_LSION RCC_CSR_LSION_Msk /*!< Internal Low Speed oscillator enable */ 4185 #define RCC_CSR_LSIRDY_Pos (1U) 4186 #define RCC_CSR_LSIRDY_Msk (0x1U << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */ 4187 #define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk /*!< Internal Low Speed oscillator Ready */ 4188 4189 #define RCC_CSR_LSEON_Pos (8U) 4190 #define RCC_CSR_LSEON_Msk (0x1U << RCC_CSR_LSEON_Pos) /*!< 0x00000100 */ 4191 #define RCC_CSR_LSEON RCC_CSR_LSEON_Msk /*!< External Low Speed oscillator enable */ 4192 #define RCC_CSR_LSERDY_Pos (9U) 4193 #define RCC_CSR_LSERDY_Msk (0x1U << RCC_CSR_LSERDY_Pos) /*!< 0x00000200 */ 4194 #define RCC_CSR_LSERDY RCC_CSR_LSERDY_Msk /*!< External Low Speed oscillator Ready */ 4195 #define RCC_CSR_LSEBYP_Pos (10U) 4196 #define RCC_CSR_LSEBYP_Msk (0x1U << RCC_CSR_LSEBYP_Pos) /*!< 0x00000400 */ 4197 #define RCC_CSR_LSEBYP RCC_CSR_LSEBYP_Msk /*!< External Low Speed oscillator Bypass */ 4198 4199 #define RCC_CSR_LSEDRV_Pos (11U) 4200 #define RCC_CSR_LSEDRV_Msk (0x3U << RCC_CSR_LSEDRV_Pos) /*!< 0x00001800 */ 4201 #define RCC_CSR_LSEDRV RCC_CSR_LSEDRV_Msk /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */ 4202 #define RCC_CSR_LSEDRV_0 (0x1U << RCC_CSR_LSEDRV_Pos) /*!< 0x00000800 */ 4203 #define RCC_CSR_LSEDRV_1 (0x2U << RCC_CSR_LSEDRV_Pos) /*!< 0x00001000 */ 4204 4205 #define RCC_CSR_LSECSSON_Pos (13U) 4206 #define RCC_CSR_LSECSSON_Msk (0x1U << RCC_CSR_LSECSSON_Pos) /*!< 0x00002000 */ 4207 #define RCC_CSR_LSECSSON RCC_CSR_LSECSSON_Msk /*!< External Low Speed oscillator CSS Enable */ 4208 #define RCC_CSR_LSECSSD_Pos (14U) 4209 #define RCC_CSR_LSECSSD_Msk (0x1U << RCC_CSR_LSECSSD_Pos) /*!< 0x00004000 */ 4210 #define RCC_CSR_LSECSSD RCC_CSR_LSECSSD_Msk /*!< External Low Speed oscillator CSS Detected */ 4211 4212 /*!< RTC congiguration */ 4213 #define RCC_CSR_RTCSEL_Pos (16U) 4214 #define RCC_CSR_RTCSEL_Msk (0x3U << RCC_CSR_RTCSEL_Pos) /*!< 0x00030000 */ 4215 #define RCC_CSR_RTCSEL RCC_CSR_RTCSEL_Msk /*!< RTCSEL[1:0] bits (RTC clock source selection) */ 4216 #define RCC_CSR_RTCSEL_0 (0x1U << RCC_CSR_RTCSEL_Pos) /*!< 0x00010000 */ 4217 #define RCC_CSR_RTCSEL_1 (0x2U << RCC_CSR_RTCSEL_Pos) /*!< 0x00020000 */ 4218 4219 #define RCC_CSR_RTCSEL_NOCLOCK (0x00000000U) /*!< No clock */ 4220 #define RCC_CSR_RTCSEL_LSE_Pos (16U) 4221 #define RCC_CSR_RTCSEL_LSE_Msk (0x1U << RCC_CSR_RTCSEL_LSE_Pos) /*!< 0x00010000 */ 4222 #define RCC_CSR_RTCSEL_LSE RCC_CSR_RTCSEL_LSE_Msk /*!< LSE oscillator clock used as RTC clock */ 4223 #define RCC_CSR_RTCSEL_LSI_Pos (17U) 4224 #define RCC_CSR_RTCSEL_LSI_Msk (0x1U << RCC_CSR_RTCSEL_LSI_Pos) /*!< 0x00020000 */ 4225 #define RCC_CSR_RTCSEL_LSI RCC_CSR_RTCSEL_LSI_Msk /*!< LSI oscillator clock used as RTC clock */ 4226 #define RCC_CSR_RTCSEL_HSE_Pos (16U) 4227 #define RCC_CSR_RTCSEL_HSE_Msk (0x3U << RCC_CSR_RTCSEL_HSE_Pos) /*!< 0x00030000 */ 4228 #define RCC_CSR_RTCSEL_HSE RCC_CSR_RTCSEL_HSE_Msk /*!< HSE oscillator clock used as RTC clock */ 4229 4230 #define RCC_CSR_RTCEN_Pos (18U) 4231 #define RCC_CSR_RTCEN_Msk (0x1U << RCC_CSR_RTCEN_Pos) /*!< 0x00040000 */ 4232 #define RCC_CSR_RTCEN RCC_CSR_RTCEN_Msk /*!< RTC clock enable */ 4233 #define RCC_CSR_RTCRST_Pos (19U) 4234 #define RCC_CSR_RTCRST_Msk (0x1U << RCC_CSR_RTCRST_Pos) /*!< 0x00080000 */ 4235 #define RCC_CSR_RTCRST RCC_CSR_RTCRST_Msk /*!< RTC software reset */ 4236 4237 #define RCC_CSR_RMVF_Pos (23U) 4238 #define RCC_CSR_RMVF_Msk (0x1U << RCC_CSR_RMVF_Pos) /*!< 0x00800000 */ 4239 #define RCC_CSR_RMVF RCC_CSR_RMVF_Msk /*!< Remove reset flag */ 4240 #define RCC_CSR_FWRSTF_Pos (24U) 4241 #define RCC_CSR_FWRSTF_Msk (0x1U << RCC_CSR_FWRSTF_Pos) /*!< 0x01000000 */ 4242 #define RCC_CSR_FWRSTF RCC_CSR_FWRSTF_Msk /*!< Mifare Firewall reset flag */ 4243 #define RCC_CSR_OBLRSTF_Pos (25U) 4244 #define RCC_CSR_OBLRSTF_Msk (0x1U << RCC_CSR_OBLRSTF_Pos) /*!< 0x02000000 */ 4245 #define RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF_Msk /*!< OBL reset flag */ 4246 #define RCC_CSR_PINRSTF_Pos (26U) 4247 #define RCC_CSR_PINRSTF_Msk (0x1U << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */ 4248 #define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk /*!< PIN reset flag */ 4249 #define RCC_CSR_PORRSTF_Pos (27U) 4250 #define RCC_CSR_PORRSTF_Msk (0x1U << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */ 4251 #define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk /*!< POR/PDR reset flag */ 4252 #define RCC_CSR_SFTRSTF_Pos (28U) 4253 #define RCC_CSR_SFTRSTF_Msk (0x1U << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */ 4254 #define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk /*!< Software Reset flag */ 4255 #define RCC_CSR_IWDGRSTF_Pos (29U) 4256 #define RCC_CSR_IWDGRSTF_Msk (0x1U << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */ 4257 #define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk /*!< Independent Watchdog reset flag */ 4258 #define RCC_CSR_WWDGRSTF_Pos (30U) 4259 #define RCC_CSR_WWDGRSTF_Msk (0x1U << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */ 4260 #define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk /*!< Window watchdog reset flag */ 4261 #define RCC_CSR_LPWRRSTF_Pos (31U) 4262 #define RCC_CSR_LPWRRSTF_Msk (0x1U << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */ 4263 #define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk /*!< Low-Power reset flag */ 4264 4265 /* Reference defines */ 4266 #define RCC_CSR_OBL RCC_CSR_OBLRSTF /*!< OBL reset flag */ 4267 4268 4269 /******************************************************************************/ 4270 /* */ 4271 /* Real-Time Clock (RTC) */ 4272 /* */ 4273 /******************************************************************************/ 4274 /* 4275 * @brief Specific device feature definitions 4276 */ 4277 #define RTC_TAMPER1_SUPPORT 4278 #define RTC_TAMPER2_SUPPORT 4279 #define RTC_TAMPER3_SUPPORT 4280 #define RTC_WAKEUP_SUPPORT 4281 #define RTC_BACKUP_SUPPORT 4282 4283 /******************** Bits definition for RTC_TR register *******************/ 4284 #define RTC_TR_PM_Pos (22U) 4285 #define RTC_TR_PM_Msk (0x1U << RTC_TR_PM_Pos) /*!< 0x00400000 */ 4286 #define RTC_TR_PM RTC_TR_PM_Msk /*!< */ 4287 #define RTC_TR_HT_Pos (20U) 4288 #define RTC_TR_HT_Msk (0x3U << RTC_TR_HT_Pos) /*!< 0x00300000 */ 4289 #define RTC_TR_HT RTC_TR_HT_Msk /*!< */ 4290 #define RTC_TR_HT_0 (0x1U << RTC_TR_HT_Pos) /*!< 0x00100000 */ 4291 #define RTC_TR_HT_1 (0x2U << RTC_TR_HT_Pos) /*!< 0x00200000 */ 4292 #define RTC_TR_HU_Pos (16U) 4293 #define RTC_TR_HU_Msk (0xFU << RTC_TR_HU_Pos) /*!< 0x000F0000 */ 4294 #define RTC_TR_HU RTC_TR_HU_Msk /*!< */ 4295 #define RTC_TR_HU_0 (0x1U << RTC_TR_HU_Pos) /*!< 0x00010000 */ 4296 #define RTC_TR_HU_1 (0x2U << RTC_TR_HU_Pos) /*!< 0x00020000 */ 4297 #define RTC_TR_HU_2 (0x4U << RTC_TR_HU_Pos) /*!< 0x00040000 */ 4298 #define RTC_TR_HU_3 (0x8U << RTC_TR_HU_Pos) /*!< 0x00080000 */ 4299 #define RTC_TR_MNT_Pos (12U) 4300 #define RTC_TR_MNT_Msk (0x7U << RTC_TR_MNT_Pos) /*!< 0x00007000 */ 4301 #define RTC_TR_MNT RTC_TR_MNT_Msk /*!< */ 4302 #define RTC_TR_MNT_0 (0x1U << RTC_TR_MNT_Pos) /*!< 0x00001000 */ 4303 #define RTC_TR_MNT_1 (0x2U << RTC_TR_MNT_Pos) /*!< 0x00002000 */ 4304 #define RTC_TR_MNT_2 (0x4U << RTC_TR_MNT_Pos) /*!< 0x00004000 */ 4305 #define RTC_TR_MNU_Pos (8U) 4306 #define RTC_TR_MNU_Msk (0xFU << RTC_TR_MNU_Pos) /*!< 0x00000F00 */ 4307 #define RTC_TR_MNU RTC_TR_MNU_Msk /*!< */ 4308 #define RTC_TR_MNU_0 (0x1U << RTC_TR_MNU_Pos) /*!< 0x00000100 */ 4309 #define RTC_TR_MNU_1 (0x2U << RTC_TR_MNU_Pos) /*!< 0x00000200 */ 4310 #define RTC_TR_MNU_2 (0x4U << RTC_TR_MNU_Pos) /*!< 0x00000400 */ 4311 #define RTC_TR_MNU_3 (0x8U << RTC_TR_MNU_Pos) /*!< 0x00000800 */ 4312 #define RTC_TR_ST_Pos (4U) 4313 #define RTC_TR_ST_Msk (0x7U << RTC_TR_ST_Pos) /*!< 0x00000070 */ 4314 #define RTC_TR_ST RTC_TR_ST_Msk /*!< */ 4315 #define RTC_TR_ST_0 (0x1U << RTC_TR_ST_Pos) /*!< 0x00000010 */ 4316 #define RTC_TR_ST_1 (0x2U << RTC_TR_ST_Pos) /*!< 0x00000020 */ 4317 #define RTC_TR_ST_2 (0x4U << RTC_TR_ST_Pos) /*!< 0x00000040 */ 4318 #define RTC_TR_SU_Pos (0U) 4319 #define RTC_TR_SU_Msk (0xFU << RTC_TR_SU_Pos) /*!< 0x0000000F */ 4320 #define RTC_TR_SU RTC_TR_SU_Msk /*!< */ 4321 #define RTC_TR_SU_0 (0x1U << RTC_TR_SU_Pos) /*!< 0x00000001 */ 4322 #define RTC_TR_SU_1 (0x2U << RTC_TR_SU_Pos) /*!< 0x00000002 */ 4323 #define RTC_TR_SU_2 (0x4U << RTC_TR_SU_Pos) /*!< 0x00000004 */ 4324 #define RTC_TR_SU_3 (0x8U << RTC_TR_SU_Pos) /*!< 0x00000008 */ 4325 4326 /******************** Bits definition for RTC_DR register *******************/ 4327 #define RTC_DR_YT_Pos (20U) 4328 #define RTC_DR_YT_Msk (0xFU << RTC_DR_YT_Pos) /*!< 0x00F00000 */ 4329 #define RTC_DR_YT RTC_DR_YT_Msk /*!< */ 4330 #define RTC_DR_YT_0 (0x1U << RTC_DR_YT_Pos) /*!< 0x00100000 */ 4331 #define RTC_DR_YT_1 (0x2U << RTC_DR_YT_Pos) /*!< 0x00200000 */ 4332 #define RTC_DR_YT_2 (0x4U << RTC_DR_YT_Pos) /*!< 0x00400000 */ 4333 #define RTC_DR_YT_3 (0x8U << RTC_DR_YT_Pos) /*!< 0x00800000 */ 4334 #define RTC_DR_YU_Pos (16U) 4335 #define RTC_DR_YU_Msk (0xFU << RTC_DR_YU_Pos) /*!< 0x000F0000 */ 4336 #define RTC_DR_YU RTC_DR_YU_Msk /*!< */ 4337 #define RTC_DR_YU_0 (0x1U << RTC_DR_YU_Pos) /*!< 0x00010000 */ 4338 #define RTC_DR_YU_1 (0x2U << RTC_DR_YU_Pos) /*!< 0x00020000 */ 4339 #define RTC_DR_YU_2 (0x4U << RTC_DR_YU_Pos) /*!< 0x00040000 */ 4340 #define RTC_DR_YU_3 (0x8U << RTC_DR_YU_Pos) /*!< 0x00080000 */ 4341 #define RTC_DR_WDU_Pos (13U) 4342 #define RTC_DR_WDU_Msk (0x7U << RTC_DR_WDU_Pos) /*!< 0x0000E000 */ 4343 #define RTC_DR_WDU RTC_DR_WDU_Msk /*!< */ 4344 #define RTC_DR_WDU_0 (0x1U << RTC_DR_WDU_Pos) /*!< 0x00002000 */ 4345 #define RTC_DR_WDU_1 (0x2U << RTC_DR_WDU_Pos) /*!< 0x00004000 */ 4346 #define RTC_DR_WDU_2 (0x4U << RTC_DR_WDU_Pos) /*!< 0x00008000 */ 4347 #define RTC_DR_MT_Pos (12U) 4348 #define RTC_DR_MT_Msk (0x1U << RTC_DR_MT_Pos) /*!< 0x00001000 */ 4349 #define RTC_DR_MT RTC_DR_MT_Msk /*!< */ 4350 #define RTC_DR_MU_Pos (8U) 4351 #define RTC_DR_MU_Msk (0xFU << RTC_DR_MU_Pos) /*!< 0x00000F00 */ 4352 #define RTC_DR_MU RTC_DR_MU_Msk /*!< */ 4353 #define RTC_DR_MU_0 (0x1U << RTC_DR_MU_Pos) /*!< 0x00000100 */ 4354 #define RTC_DR_MU_1 (0x2U << RTC_DR_MU_Pos) /*!< 0x00000200 */ 4355 #define RTC_DR_MU_2 (0x4U << RTC_DR_MU_Pos) /*!< 0x00000400 */ 4356 #define RTC_DR_MU_3 (0x8U << RTC_DR_MU_Pos) /*!< 0x00000800 */ 4357 #define RTC_DR_DT_Pos (4U) 4358 #define RTC_DR_DT_Msk (0x3U << RTC_DR_DT_Pos) /*!< 0x00000030 */ 4359 #define RTC_DR_DT RTC_DR_DT_Msk /*!< */ 4360 #define RTC_DR_DT_0 (0x1U << RTC_DR_DT_Pos) /*!< 0x00000010 */ 4361 #define RTC_DR_DT_1 (0x2U << RTC_DR_DT_Pos) /*!< 0x00000020 */ 4362 #define RTC_DR_DU_Pos (0U) 4363 #define RTC_DR_DU_Msk (0xFU << RTC_DR_DU_Pos) /*!< 0x0000000F */ 4364 #define RTC_DR_DU RTC_DR_DU_Msk /*!< */ 4365 #define RTC_DR_DU_0 (0x1U << RTC_DR_DU_Pos) /*!< 0x00000001 */ 4366 #define RTC_DR_DU_1 (0x2U << RTC_DR_DU_Pos) /*!< 0x00000002 */ 4367 #define RTC_DR_DU_2 (0x4U << RTC_DR_DU_Pos) /*!< 0x00000004 */ 4368 #define RTC_DR_DU_3 (0x8U << RTC_DR_DU_Pos) /*!< 0x00000008 */ 4369 4370 /******************** Bits definition for RTC_CR register *******************/ 4371 #define RTC_CR_COE_Pos (23U) 4372 #define RTC_CR_COE_Msk (0x1U << RTC_CR_COE_Pos) /*!< 0x00800000 */ 4373 #define RTC_CR_COE RTC_CR_COE_Msk /*!< */ 4374 #define RTC_CR_OSEL_Pos (21U) 4375 #define RTC_CR_OSEL_Msk (0x3U << RTC_CR_OSEL_Pos) /*!< 0x00600000 */ 4376 #define RTC_CR_OSEL RTC_CR_OSEL_Msk /*!< */ 4377 #define RTC_CR_OSEL_0 (0x1U << RTC_CR_OSEL_Pos) /*!< 0x00200000 */ 4378 #define RTC_CR_OSEL_1 (0x2U << RTC_CR_OSEL_Pos) /*!< 0x00400000 */ 4379 #define RTC_CR_POL_Pos (20U) 4380 #define RTC_CR_POL_Msk (0x1U << RTC_CR_POL_Pos) /*!< 0x00100000 */ 4381 #define RTC_CR_POL RTC_CR_POL_Msk /*!< */ 4382 #define RTC_CR_COSEL_Pos (19U) 4383 #define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */ 4384 #define RTC_CR_COSEL RTC_CR_COSEL_Msk /*!< */ 4385 #define RTC_CR_BCK_Pos (18U) 4386 #define RTC_CR_BCK_Msk (0x1U << RTC_CR_BCK_Pos) /*!< 0x00040000 */ 4387 #define RTC_CR_BCK RTC_CR_BCK_Msk /*!< */ 4388 #define RTC_CR_SUB1H_Pos (17U) 4389 #define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */ 4390 #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk /*!< */ 4391 #define RTC_CR_ADD1H_Pos (16U) 4392 #define RTC_CR_ADD1H_Msk (0x1U << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */ 4393 #define RTC_CR_ADD1H RTC_CR_ADD1H_Msk /*!< */ 4394 #define RTC_CR_TSIE_Pos (15U) 4395 #define RTC_CR_TSIE_Msk (0x1U << RTC_CR_TSIE_Pos) /*!< 0x00008000 */ 4396 #define RTC_CR_TSIE RTC_CR_TSIE_Msk /*!< */ 4397 #define RTC_CR_WUTIE_Pos (14U) 4398 #define RTC_CR_WUTIE_Msk (0x1U << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */ 4399 #define RTC_CR_WUTIE RTC_CR_WUTIE_Msk /*!< */ 4400 #define RTC_CR_ALRBIE_Pos (13U) 4401 #define RTC_CR_ALRBIE_Msk (0x1U << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */ 4402 #define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk /*!< */ 4403 #define RTC_CR_ALRAIE_Pos (12U) 4404 #define RTC_CR_ALRAIE_Msk (0x1U << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */ 4405 #define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk /*!< */ 4406 #define RTC_CR_TSE_Pos (11U) 4407 #define RTC_CR_TSE_Msk (0x1U << RTC_CR_TSE_Pos) /*!< 0x00000800 */ 4408 #define RTC_CR_TSE RTC_CR_TSE_Msk /*!< */ 4409 #define RTC_CR_WUTE_Pos (10U) 4410 #define RTC_CR_WUTE_Msk (0x1U << RTC_CR_WUTE_Pos) /*!< 0x00000400 */ 4411 #define RTC_CR_WUTE RTC_CR_WUTE_Msk /*!< */ 4412 #define RTC_CR_ALRBE_Pos (9U) 4413 #define RTC_CR_ALRBE_Msk (0x1U << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */ 4414 #define RTC_CR_ALRBE RTC_CR_ALRBE_Msk /*!< */ 4415 #define RTC_CR_ALRAE_Pos (8U) 4416 #define RTC_CR_ALRAE_Msk (0x1U << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */ 4417 #define RTC_CR_ALRAE RTC_CR_ALRAE_Msk /*!< */ 4418 #define RTC_CR_FMT_Pos (6U) 4419 #define RTC_CR_FMT_Msk (0x1U << RTC_CR_FMT_Pos) /*!< 0x00000040 */ 4420 #define RTC_CR_FMT RTC_CR_FMT_Msk /*!< */ 4421 #define RTC_CR_BYPSHAD_Pos (5U) 4422 #define RTC_CR_BYPSHAD_Msk (0x1U << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */ 4423 #define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk /*!< */ 4424 #define RTC_CR_REFCKON_Pos (4U) 4425 #define RTC_CR_REFCKON_Msk (0x1U << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */ 4426 #define RTC_CR_REFCKON RTC_CR_REFCKON_Msk /*!< */ 4427 #define RTC_CR_TSEDGE_Pos (3U) 4428 #define RTC_CR_TSEDGE_Msk (0x1U << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */ 4429 #define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk /*!< */ 4430 #define RTC_CR_WUCKSEL_Pos (0U) 4431 #define RTC_CR_WUCKSEL_Msk (0x7U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */ 4432 #define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk /*!< */ 4433 #define RTC_CR_WUCKSEL_0 (0x1U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */ 4434 #define RTC_CR_WUCKSEL_1 (0x2U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */ 4435 #define RTC_CR_WUCKSEL_2 (0x4U << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */ 4436 4437 /******************** Bits definition for RTC_ISR register ******************/ 4438 #define RTC_ISR_RECALPF_Pos (16U) 4439 #define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */ 4440 #define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk /*!< */ 4441 #define RTC_ISR_TAMP3F_Pos (15U) 4442 #define RTC_ISR_TAMP3F_Msk (0x1U << RTC_ISR_TAMP3F_Pos) /*!< 0x00008000 */ 4443 #define RTC_ISR_TAMP3F RTC_ISR_TAMP3F_Msk /*!< */ 4444 #define RTC_ISR_TAMP2F_Pos (14U) 4445 #define RTC_ISR_TAMP2F_Msk (0x1U << RTC_ISR_TAMP2F_Pos) /*!< 0x00004000 */ 4446 #define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk /*!< */ 4447 #define RTC_ISR_TAMP1F_Pos (13U) 4448 #define RTC_ISR_TAMP1F_Msk (0x1U << RTC_ISR_TAMP1F_Pos) /*!< 0x00002000 */ 4449 #define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk /*!< */ 4450 #define RTC_ISR_TSOVF_Pos (12U) 4451 #define RTC_ISR_TSOVF_Msk (0x1U << RTC_ISR_TSOVF_Pos) /*!< 0x00001000 */ 4452 #define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk /*!< */ 4453 #define RTC_ISR_TSF_Pos (11U) 4454 #define RTC_ISR_TSF_Msk (0x1U << RTC_ISR_TSF_Pos) /*!< 0x00000800 */ 4455 #define RTC_ISR_TSF RTC_ISR_TSF_Msk /*!< */ 4456 #define RTC_ISR_WUTF_Pos (10U) 4457 #define RTC_ISR_WUTF_Msk (0x1U << RTC_ISR_WUTF_Pos) /*!< 0x00000400 */ 4458 #define RTC_ISR_WUTF RTC_ISR_WUTF_Msk /*!< */ 4459 #define RTC_ISR_ALRBF_Pos (9U) 4460 #define RTC_ISR_ALRBF_Msk (0x1U << RTC_ISR_ALRBF_Pos) /*!< 0x00000200 */ 4461 #define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk /*!< */ 4462 #define RTC_ISR_ALRAF_Pos (8U) 4463 #define RTC_ISR_ALRAF_Msk (0x1U << RTC_ISR_ALRAF_Pos) /*!< 0x00000100 */ 4464 #define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk /*!< */ 4465 #define RTC_ISR_INIT_Pos (7U) 4466 #define RTC_ISR_INIT_Msk (0x1U << RTC_ISR_INIT_Pos) /*!< 0x00000080 */ 4467 #define RTC_ISR_INIT RTC_ISR_INIT_Msk /*!< */ 4468 #define RTC_ISR_INITF_Pos (6U) 4469 #define RTC_ISR_INITF_Msk (0x1U << RTC_ISR_INITF_Pos) /*!< 0x00000040 */ 4470 #define RTC_ISR_INITF RTC_ISR_INITF_Msk /*!< */ 4471 #define RTC_ISR_RSF_Pos (5U) 4472 #define RTC_ISR_RSF_Msk (0x1U << RTC_ISR_RSF_Pos) /*!< 0x00000020 */ 4473 #define RTC_ISR_RSF RTC_ISR_RSF_Msk /*!< */ 4474 #define RTC_ISR_INITS_Pos (4U) 4475 #define RTC_ISR_INITS_Msk (0x1U << RTC_ISR_INITS_Pos) /*!< 0x00000010 */ 4476 #define RTC_ISR_INITS RTC_ISR_INITS_Msk /*!< */ 4477 #define RTC_ISR_SHPF_Pos (3U) 4478 #define RTC_ISR_SHPF_Msk (0x1U << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */ 4479 #define RTC_ISR_SHPF RTC_ISR_SHPF_Msk /*!< */ 4480 #define RTC_ISR_WUTWF_Pos (2U) 4481 #define RTC_ISR_WUTWF_Msk (0x1U << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */ 4482 #define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk /*!< */ 4483 #define RTC_ISR_ALRBWF_Pos (1U) 4484 #define RTC_ISR_ALRBWF_Msk (0x1U << RTC_ISR_ALRBWF_Pos) /*!< 0x00000002 */ 4485 #define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk /*!< */ 4486 #define RTC_ISR_ALRAWF_Pos (0U) 4487 #define RTC_ISR_ALRAWF_Msk (0x1U << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */ 4488 #define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk /*!< */ 4489 4490 /******************** Bits definition for RTC_PRER register *****************/ 4491 #define RTC_PRER_PREDIV_A_Pos (16U) 4492 #define RTC_PRER_PREDIV_A_Msk (0x7FU << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */ 4493 #define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk /*!< */ 4494 #define RTC_PRER_PREDIV_S_Pos (0U) 4495 #define RTC_PRER_PREDIV_S_Msk (0x7FFFU << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */ 4496 #define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk /*!< */ 4497 4498 /******************** Bits definition for RTC_WUTR register *****************/ 4499 #define RTC_WUTR_WUT_Pos (0U) 4500 #define RTC_WUTR_WUT_Msk (0xFFFFU << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */ 4501 #define RTC_WUTR_WUT RTC_WUTR_WUT_Msk 4502 4503 /******************** Bits definition for RTC_ALRMAR register ***************/ 4504 #define RTC_ALRMAR_MSK4_Pos (31U) 4505 #define RTC_ALRMAR_MSK4_Msk (0x1U << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */ 4506 #define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk /*!< */ 4507 #define RTC_ALRMAR_WDSEL_Pos (30U) 4508 #define RTC_ALRMAR_WDSEL_Msk (0x1U << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */ 4509 #define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk /*!< */ 4510 #define RTC_ALRMAR_DT_Pos (28U) 4511 #define RTC_ALRMAR_DT_Msk (0x3U << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */ 4512 #define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk /*!< */ 4513 #define RTC_ALRMAR_DT_0 (0x1U << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */ 4514 #define RTC_ALRMAR_DT_1 (0x2U << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */ 4515 #define RTC_ALRMAR_DU_Pos (24U) 4516 #define RTC_ALRMAR_DU_Msk (0xFU << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */ 4517 #define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk /*!< */ 4518 #define RTC_ALRMAR_DU_0 (0x1U << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */ 4519 #define RTC_ALRMAR_DU_1 (0x2U << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */ 4520 #define RTC_ALRMAR_DU_2 (0x4U << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */ 4521 #define RTC_ALRMAR_DU_3 (0x8U << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */ 4522 #define RTC_ALRMAR_MSK3_Pos (23U) 4523 #define RTC_ALRMAR_MSK3_Msk (0x1U << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */ 4524 #define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk /*!< */ 4525 #define RTC_ALRMAR_PM_Pos (22U) 4526 #define RTC_ALRMAR_PM_Msk (0x1U << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */ 4527 #define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk /*!< */ 4528 #define RTC_ALRMAR_HT_Pos (20U) 4529 #define RTC_ALRMAR_HT_Msk (0x3U << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */ 4530 #define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk /*!< */ 4531 #define RTC_ALRMAR_HT_0 (0x1U << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */ 4532 #define RTC_ALRMAR_HT_1 (0x2U << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */ 4533 #define RTC_ALRMAR_HU_Pos (16U) 4534 #define RTC_ALRMAR_HU_Msk (0xFU << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */ 4535 #define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk /*!< */ 4536 #define RTC_ALRMAR_HU_0 (0x1U << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */ 4537 #define RTC_ALRMAR_HU_1 (0x2U << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */ 4538 #define RTC_ALRMAR_HU_2 (0x4U << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */ 4539 #define RTC_ALRMAR_HU_3 (0x8U << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */ 4540 #define RTC_ALRMAR_MSK2_Pos (15U) 4541 #define RTC_ALRMAR_MSK2_Msk (0x1U << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */ 4542 #define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk /*!< */ 4543 #define RTC_ALRMAR_MNT_Pos (12U) 4544 #define RTC_ALRMAR_MNT_Msk (0x7U << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */ 4545 #define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk /*!< */ 4546 #define RTC_ALRMAR_MNT_0 (0x1U << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */ 4547 #define RTC_ALRMAR_MNT_1 (0x2U << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */ 4548 #define RTC_ALRMAR_MNT_2 (0x4U << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */ 4549 #define RTC_ALRMAR_MNU_Pos (8U) 4550 #define RTC_ALRMAR_MNU_Msk (0xFU << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */ 4551 #define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk /*!< */ 4552 #define RTC_ALRMAR_MNU_0 (0x1U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */ 4553 #define RTC_ALRMAR_MNU_1 (0x2U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */ 4554 #define RTC_ALRMAR_MNU_2 (0x4U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */ 4555 #define RTC_ALRMAR_MNU_3 (0x8U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */ 4556 #define RTC_ALRMAR_MSK1_Pos (7U) 4557 #define RTC_ALRMAR_MSK1_Msk (0x1U << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */ 4558 #define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk /*!< */ 4559 #define RTC_ALRMAR_ST_Pos (4U) 4560 #define RTC_ALRMAR_ST_Msk (0x7U << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */ 4561 #define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk /*!< */ 4562 #define RTC_ALRMAR_ST_0 (0x1U << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */ 4563 #define RTC_ALRMAR_ST_1 (0x2U << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */ 4564 #define RTC_ALRMAR_ST_2 (0x4U << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */ 4565 #define RTC_ALRMAR_SU_Pos (0U) 4566 #define RTC_ALRMAR_SU_Msk (0xFU << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */ 4567 #define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk /*!< */ 4568 #define RTC_ALRMAR_SU_0 (0x1U << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */ 4569 #define RTC_ALRMAR_SU_1 (0x2U << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */ 4570 #define RTC_ALRMAR_SU_2 (0x4U << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */ 4571 #define RTC_ALRMAR_SU_3 (0x8U << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */ 4572 4573 /******************** Bits definition for RTC_ALRMBR register ***************/ 4574 #define RTC_ALRMBR_MSK4_Pos (31U) 4575 #define RTC_ALRMBR_MSK4_Msk (0x1U << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */ 4576 #define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk /*!< */ 4577 #define RTC_ALRMBR_WDSEL_Pos (30U) 4578 #define RTC_ALRMBR_WDSEL_Msk (0x1U << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */ 4579 #define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk /*!< */ 4580 #define RTC_ALRMBR_DT_Pos (28U) 4581 #define RTC_ALRMBR_DT_Msk (0x3U << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */ 4582 #define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk /*!< */ 4583 #define RTC_ALRMBR_DT_0 (0x1U << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */ 4584 #define RTC_ALRMBR_DT_1 (0x2U << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */ 4585 #define RTC_ALRMBR_DU_Pos (24U) 4586 #define RTC_ALRMBR_DU_Msk (0xFU << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */ 4587 #define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk /*!< */ 4588 #define RTC_ALRMBR_DU_0 (0x1U << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */ 4589 #define RTC_ALRMBR_DU_1 (0x2U << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */ 4590 #define RTC_ALRMBR_DU_2 (0x4U << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */ 4591 #define RTC_ALRMBR_DU_3 (0x8U << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */ 4592 #define RTC_ALRMBR_MSK3_Pos (23U) 4593 #define RTC_ALRMBR_MSK3_Msk (0x1U << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */ 4594 #define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk /*!< */ 4595 #define RTC_ALRMBR_PM_Pos (22U) 4596 #define RTC_ALRMBR_PM_Msk (0x1U << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */ 4597 #define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk /*!< */ 4598 #define RTC_ALRMBR_HT_Pos (20U) 4599 #define RTC_ALRMBR_HT_Msk (0x3U << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */ 4600 #define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk /*!< */ 4601 #define RTC_ALRMBR_HT_0 (0x1U << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */ 4602 #define RTC_ALRMBR_HT_1 (0x2U << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */ 4603 #define RTC_ALRMBR_HU_Pos (16U) 4604 #define RTC_ALRMBR_HU_Msk (0xFU << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */ 4605 #define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk /*!< */ 4606 #define RTC_ALRMBR_HU_0 (0x1U << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */ 4607 #define RTC_ALRMBR_HU_1 (0x2U << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */ 4608 #define RTC_ALRMBR_HU_2 (0x4U << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */ 4609 #define RTC_ALRMBR_HU_3 (0x8U << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */ 4610 #define RTC_ALRMBR_MSK2_Pos (15U) 4611 #define RTC_ALRMBR_MSK2_Msk (0x1U << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */ 4612 #define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk /*!< */ 4613 #define RTC_ALRMBR_MNT_Pos (12U) 4614 #define RTC_ALRMBR_MNT_Msk (0x7U << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */ 4615 #define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk /*!< */ 4616 #define RTC_ALRMBR_MNT_0 (0x1U << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */ 4617 #define RTC_ALRMBR_MNT_1 (0x2U << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */ 4618 #define RTC_ALRMBR_MNT_2 (0x4U << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */ 4619 #define RTC_ALRMBR_MNU_Pos (8U) 4620 #define RTC_ALRMBR_MNU_Msk (0xFU << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */ 4621 #define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk /*!< */ 4622 #define RTC_ALRMBR_MNU_0 (0x1U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */ 4623 #define RTC_ALRMBR_MNU_1 (0x2U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */ 4624 #define RTC_ALRMBR_MNU_2 (0x4U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */ 4625 #define RTC_ALRMBR_MNU_3 (0x8U << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */ 4626 #define RTC_ALRMBR_MSK1_Pos (7U) 4627 #define RTC_ALRMBR_MSK1_Msk (0x1U << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */ 4628 #define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk /*!< */ 4629 #define RTC_ALRMBR_ST_Pos (4U) 4630 #define RTC_ALRMBR_ST_Msk (0x7U << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */ 4631 #define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk /*!< */ 4632 #define RTC_ALRMBR_ST_0 (0x1U << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */ 4633 #define RTC_ALRMBR_ST_1 (0x2U << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */ 4634 #define RTC_ALRMBR_ST_2 (0x4U << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */ 4635 #define RTC_ALRMBR_SU_Pos (0U) 4636 #define RTC_ALRMBR_SU_Msk (0xFU << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */ 4637 #define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk /*!< */ 4638 #define RTC_ALRMBR_SU_0 (0x1U << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */ 4639 #define RTC_ALRMBR_SU_1 (0x2U << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */ 4640 #define RTC_ALRMBR_SU_2 (0x4U << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */ 4641 #define RTC_ALRMBR_SU_3 (0x8U << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */ 4642 4643 /******************** Bits definition for RTC_WPR register ******************/ 4644 #define RTC_WPR_KEY_Pos (0U) 4645 #define RTC_WPR_KEY_Msk (0xFFU << RTC_WPR_KEY_Pos) /*!< 0x000000FF */ 4646 #define RTC_WPR_KEY RTC_WPR_KEY_Msk /*!< */ 4647 4648 /******************** Bits definition for RTC_SSR register ******************/ 4649 #define RTC_SSR_SS_Pos (0U) 4650 #define RTC_SSR_SS_Msk (0xFFFFU << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */ 4651 #define RTC_SSR_SS RTC_SSR_SS_Msk /*!< */ 4652 4653 /******************** Bits definition for RTC_SHIFTR register ***************/ 4654 #define RTC_SHIFTR_SUBFS_Pos (0U) 4655 #define RTC_SHIFTR_SUBFS_Msk (0x7FFFU << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */ 4656 #define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk /*!< */ 4657 #define RTC_SHIFTR_ADD1S_Pos (31U) 4658 #define RTC_SHIFTR_ADD1S_Msk (0x1U << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */ 4659 #define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk /*!< */ 4660 4661 /******************** Bits definition for RTC_TSTR register *****************/ 4662 #define RTC_TSTR_PM_Pos (22U) 4663 #define RTC_TSTR_PM_Msk (0x1U << RTC_TSTR_PM_Pos) /*!< 0x00400000 */ 4664 #define RTC_TSTR_PM RTC_TSTR_PM_Msk /*!< */ 4665 #define RTC_TSTR_HT_Pos (20U) 4666 #define RTC_TSTR_HT_Msk (0x3U << RTC_TSTR_HT_Pos) /*!< 0x00300000 */ 4667 #define RTC_TSTR_HT RTC_TSTR_HT_Msk /*!< */ 4668 #define RTC_TSTR_HT_0 (0x1U << RTC_TSTR_HT_Pos) /*!< 0x00100000 */ 4669 #define RTC_TSTR_HT_1 (0x2U << RTC_TSTR_HT_Pos) /*!< 0x00200000 */ 4670 #define RTC_TSTR_HU_Pos (16U) 4671 #define RTC_TSTR_HU_Msk (0xFU << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */ 4672 #define RTC_TSTR_HU RTC_TSTR_HU_Msk /*!< */ 4673 #define RTC_TSTR_HU_0 (0x1U << RTC_TSTR_HU_Pos) /*!< 0x00010000 */ 4674 #define RTC_TSTR_HU_1 (0x2U << RTC_TSTR_HU_Pos) /*!< 0x00020000 */ 4675 #define RTC_TSTR_HU_2 (0x4U << RTC_TSTR_HU_Pos) /*!< 0x00040000 */ 4676 #define RTC_TSTR_HU_3 (0x8U << RTC_TSTR_HU_Pos) /*!< 0x00080000 */ 4677 #define RTC_TSTR_MNT_Pos (12U) 4678 #define RTC_TSTR_MNT_Msk (0x7U << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */ 4679 #define RTC_TSTR_MNT RTC_TSTR_MNT_Msk /*!< */ 4680 #define RTC_TSTR_MNT_0 (0x1U << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */ 4681 #define RTC_TSTR_MNT_1 (0x2U << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */ 4682 #define RTC_TSTR_MNT_2 (0x4U << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */ 4683 #define RTC_TSTR_MNU_Pos (8U) 4684 #define RTC_TSTR_MNU_Msk (0xFU << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */ 4685 #define RTC_TSTR_MNU RTC_TSTR_MNU_Msk /*!< */ 4686 #define RTC_TSTR_MNU_0 (0x1U << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */ 4687 #define RTC_TSTR_MNU_1 (0x2U << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */ 4688 #define RTC_TSTR_MNU_2 (0x4U << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */ 4689 #define RTC_TSTR_MNU_3 (0x8U << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */ 4690 #define RTC_TSTR_ST_Pos (4U) 4691 #define RTC_TSTR_ST_Msk (0x7U << RTC_TSTR_ST_Pos) /*!< 0x00000070 */ 4692 #define RTC_TSTR_ST RTC_TSTR_ST_Msk /*!< */ 4693 #define RTC_TSTR_ST_0 (0x1U << RTC_TSTR_ST_Pos) /*!< 0x00000010 */ 4694 #define RTC_TSTR_ST_1 (0x2U << RTC_TSTR_ST_Pos) /*!< 0x00000020 */ 4695 #define RTC_TSTR_ST_2 (0x4U << RTC_TSTR_ST_Pos) /*!< 0x00000040 */ 4696 #define RTC_TSTR_SU_Pos (0U) 4697 #define RTC_TSTR_SU_Msk (0xFU << RTC_TSTR_SU_Pos) /*!< 0x0000000F */ 4698 #define RTC_TSTR_SU RTC_TSTR_SU_Msk /*!< */ 4699 #define RTC_TSTR_SU_0 (0x1U << RTC_TSTR_SU_Pos) /*!< 0x00000001 */ 4700 #define RTC_TSTR_SU_1 (0x2U << RTC_TSTR_SU_Pos) /*!< 0x00000002 */ 4701 #define RTC_TSTR_SU_2 (0x4U << RTC_TSTR_SU_Pos) /*!< 0x00000004 */ 4702 #define RTC_TSTR_SU_3 (0x8U << RTC_TSTR_SU_Pos) /*!< 0x00000008 */ 4703 4704 /******************** Bits definition for RTC_TSDR register *****************/ 4705 #define RTC_TSDR_WDU_Pos (13U) 4706 #define RTC_TSDR_WDU_Msk (0x7U << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */ 4707 #define RTC_TSDR_WDU RTC_TSDR_WDU_Msk /*!< */ 4708 #define RTC_TSDR_WDU_0 (0x1U << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */ 4709 #define RTC_TSDR_WDU_1 (0x2U << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */ 4710 #define RTC_TSDR_WDU_2 (0x4U << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */ 4711 #define RTC_TSDR_MT_Pos (12U) 4712 #define RTC_TSDR_MT_Msk (0x1U << RTC_TSDR_MT_Pos) /*!< 0x00001000 */ 4713 #define RTC_TSDR_MT RTC_TSDR_MT_Msk /*!< */ 4714 #define RTC_TSDR_MU_Pos (8U) 4715 #define RTC_TSDR_MU_Msk (0xFU << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */ 4716 #define RTC_TSDR_MU RTC_TSDR_MU_Msk /*!< */ 4717 #define RTC_TSDR_MU_0 (0x1U << RTC_TSDR_MU_Pos) /*!< 0x00000100 */ 4718 #define RTC_TSDR_MU_1 (0x2U << RTC_TSDR_MU_Pos) /*!< 0x00000200 */ 4719 #define RTC_TSDR_MU_2 (0x4U << RTC_TSDR_MU_Pos) /*!< 0x00000400 */ 4720 #define RTC_TSDR_MU_3 (0x8U << RTC_TSDR_MU_Pos) /*!< 0x00000800 */ 4721 #define RTC_TSDR_DT_Pos (4U) 4722 #define RTC_TSDR_DT_Msk (0x3U << RTC_TSDR_DT_Pos) /*!< 0x00000030 */ 4723 #define RTC_TSDR_DT RTC_TSDR_DT_Msk /*!< */ 4724 #define RTC_TSDR_DT_0 (0x1U << RTC_TSDR_DT_Pos) /*!< 0x00000010 */ 4725 #define RTC_TSDR_DT_1 (0x2U << RTC_TSDR_DT_Pos) /*!< 0x00000020 */ 4726 #define RTC_TSDR_DU_Pos (0U) 4727 #define RTC_TSDR_DU_Msk (0xFU << RTC_TSDR_DU_Pos) /*!< 0x0000000F */ 4728 #define RTC_TSDR_DU RTC_TSDR_DU_Msk /*!< */ 4729 #define RTC_TSDR_DU_0 (0x1U << RTC_TSDR_DU_Pos) /*!< 0x00000001 */ 4730 #define RTC_TSDR_DU_1 (0x2U << RTC_TSDR_DU_Pos) /*!< 0x00000002 */ 4731 #define RTC_TSDR_DU_2 (0x4U << RTC_TSDR_DU_Pos) /*!< 0x00000004 */ 4732 #define RTC_TSDR_DU_3 (0x8U << RTC_TSDR_DU_Pos) /*!< 0x00000008 */ 4733 4734 /******************** Bits definition for RTC_TSSSR register ****************/ 4735 #define RTC_TSSSR_SS_Pos (0U) 4736 #define RTC_TSSSR_SS_Msk (0xFFFFU << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */ 4737 #define RTC_TSSSR_SS RTC_TSSSR_SS_Msk 4738 4739 /******************** Bits definition for RTC_CALR register *****************/ 4740 #define RTC_CALR_CALP_Pos (15U) 4741 #define RTC_CALR_CALP_Msk (0x1U << RTC_CALR_CALP_Pos) /*!< 0x00008000 */ 4742 #define RTC_CALR_CALP RTC_CALR_CALP_Msk /*!< */ 4743 #define RTC_CALR_CALW8_Pos (14U) 4744 #define RTC_CALR_CALW8_Msk (0x1U << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */ 4745 #define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk /*!< */ 4746 #define RTC_CALR_CALW16_Pos (13U) 4747 #define RTC_CALR_CALW16_Msk (0x1U << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */ 4748 #define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk /*!< */ 4749 #define RTC_CALR_CALM_Pos (0U) 4750 #define RTC_CALR_CALM_Msk (0x1FFU << RTC_CALR_CALM_Pos) /*!< 0x000001FF */ 4751 #define RTC_CALR_CALM RTC_CALR_CALM_Msk /*!< */ 4752 #define RTC_CALR_CALM_0 (0x001U << RTC_CALR_CALM_Pos) /*!< 0x00000001 */ 4753 #define RTC_CALR_CALM_1 (0x002U << RTC_CALR_CALM_Pos) /*!< 0x00000002 */ 4754 #define RTC_CALR_CALM_2 (0x004U << RTC_CALR_CALM_Pos) /*!< 0x00000004 */ 4755 #define RTC_CALR_CALM_3 (0x008U << RTC_CALR_CALM_Pos) /*!< 0x00000008 */ 4756 #define RTC_CALR_CALM_4 (0x010U << RTC_CALR_CALM_Pos) /*!< 0x00000010 */ 4757 #define RTC_CALR_CALM_5 (0x020U << RTC_CALR_CALM_Pos) /*!< 0x00000020 */ 4758 #define RTC_CALR_CALM_6 (0x040U << RTC_CALR_CALM_Pos) /*!< 0x00000040 */ 4759 #define RTC_CALR_CALM_7 (0x080U << RTC_CALR_CALM_Pos) /*!< 0x00000080 */ 4760 #define RTC_CALR_CALM_8 (0x100U << RTC_CALR_CALM_Pos) /*!< 0x00000100 */ 4761 4762 /* Legacy defines */ 4763 #define RTC_CAL_CALP RTC_CALR_CALP 4764 #define RTC_CAL_CALW8 RTC_CALR_CALW8 4765 #define RTC_CAL_CALW16 RTC_CALR_CALW16 4766 #define RTC_CAL_CALM RTC_CALR_CALM 4767 #define RTC_CAL_CALM_0 RTC_CALR_CALM_0 4768 #define RTC_CAL_CALM_1 RTC_CALR_CALM_1 4769 #define RTC_CAL_CALM_2 RTC_CALR_CALM_2 4770 #define RTC_CAL_CALM_3 RTC_CALR_CALM_3 4771 #define RTC_CAL_CALM_4 RTC_CALR_CALM_4 4772 #define RTC_CAL_CALM_5 RTC_CALR_CALM_5 4773 #define RTC_CAL_CALM_6 RTC_CALR_CALM_6 4774 #define RTC_CAL_CALM_7 RTC_CALR_CALM_7 4775 #define RTC_CAL_CALM_8 RTC_CALR_CALM_8 4776 4777 /******************** Bits definition for RTC_TAMPCR register ****************/ 4778 #define RTC_TAMPCR_TAMP3MF_Pos (24U) 4779 #define RTC_TAMPCR_TAMP3MF_Msk (0x1U << RTC_TAMPCR_TAMP3MF_Pos) /*!< 0x01000000 */ 4780 #define RTC_TAMPCR_TAMP3MF RTC_TAMPCR_TAMP3MF_Msk /*!< */ 4781 #define RTC_TAMPCR_TAMP3NOERASE_Pos (23U) 4782 #define RTC_TAMPCR_TAMP3NOERASE_Msk (0x1U << RTC_TAMPCR_TAMP3NOERASE_Pos) /*!< 0x00800000 */ 4783 #define RTC_TAMPCR_TAMP3NOERASE RTC_TAMPCR_TAMP3NOERASE_Msk /*!< */ 4784 #define RTC_TAMPCR_TAMP3IE_Pos (22U) 4785 #define RTC_TAMPCR_TAMP3IE_Msk (0x1U << RTC_TAMPCR_TAMP3IE_Pos) /*!< 0x00400000 */ 4786 #define RTC_TAMPCR_TAMP3IE RTC_TAMPCR_TAMP3IE_Msk /*!< */ 4787 #define RTC_TAMPCR_TAMP2MF_Pos (21U) 4788 #define RTC_TAMPCR_TAMP2MF_Msk (0x1U << RTC_TAMPCR_TAMP2MF_Pos) /*!< 0x00200000 */ 4789 #define RTC_TAMPCR_TAMP2MF RTC_TAMPCR_TAMP2MF_Msk /*!< */ 4790 #define RTC_TAMPCR_TAMP2NOERASE_Pos (20U) 4791 #define RTC_TAMPCR_TAMP2NOERASE_Msk (0x1U << RTC_TAMPCR_TAMP2NOERASE_Pos) /*!< 0x00100000 */ 4792 #define RTC_TAMPCR_TAMP2NOERASE RTC_TAMPCR_TAMP2NOERASE_Msk /*!< */ 4793 #define RTC_TAMPCR_TAMP2IE_Pos (19U) 4794 #define RTC_TAMPCR_TAMP2IE_Msk (0x1U << RTC_TAMPCR_TAMP2IE_Pos) /*!< 0x00080000 */ 4795 #define RTC_TAMPCR_TAMP2IE RTC_TAMPCR_TAMP2IE_Msk /*!< */ 4796 #define RTC_TAMPCR_TAMP1MF_Pos (18U) 4797 #define RTC_TAMPCR_TAMP1MF_Msk (0x1U << RTC_TAMPCR_TAMP1MF_Pos) /*!< 0x00040000 */ 4798 #define RTC_TAMPCR_TAMP1MF RTC_TAMPCR_TAMP1MF_Msk /*!< */ 4799 #define RTC_TAMPCR_TAMP1NOERASE_Pos (17U) 4800 #define RTC_TAMPCR_TAMP1NOERASE_Msk (0x1U << RTC_TAMPCR_TAMP1NOERASE_Pos) /*!< 0x00020000 */ 4801 #define RTC_TAMPCR_TAMP1NOERASE RTC_TAMPCR_TAMP1NOERASE_Msk /*!< */ 4802 #define RTC_TAMPCR_TAMP1IE_Pos (16U) 4803 #define RTC_TAMPCR_TAMP1IE_Msk (0x1U << RTC_TAMPCR_TAMP1IE_Pos) /*!< 0x00010000 */ 4804 #define RTC_TAMPCR_TAMP1IE RTC_TAMPCR_TAMP1IE_Msk /*!< */ 4805 #define RTC_TAMPCR_TAMPPUDIS_Pos (15U) 4806 #define RTC_TAMPCR_TAMPPUDIS_Msk (0x1U << RTC_TAMPCR_TAMPPUDIS_Pos) /*!< 0x00008000 */ 4807 #define RTC_TAMPCR_TAMPPUDIS RTC_TAMPCR_TAMPPUDIS_Msk /*!< */ 4808 #define RTC_TAMPCR_TAMPPRCH_Pos (13U) 4809 #define RTC_TAMPCR_TAMPPRCH_Msk (0x3U << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00006000 */ 4810 #define RTC_TAMPCR_TAMPPRCH RTC_TAMPCR_TAMPPRCH_Msk /*!< */ 4811 #define RTC_TAMPCR_TAMPPRCH_0 (0x1U << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00002000 */ 4812 #define RTC_TAMPCR_TAMPPRCH_1 (0x2U << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00004000 */ 4813 #define RTC_TAMPCR_TAMPFLT_Pos (11U) 4814 #define RTC_TAMPCR_TAMPFLT_Msk (0x3U << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00001800 */ 4815 #define RTC_TAMPCR_TAMPFLT RTC_TAMPCR_TAMPFLT_Msk /*!< */ 4816 #define RTC_TAMPCR_TAMPFLT_0 (0x1U << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00000800 */ 4817 #define RTC_TAMPCR_TAMPFLT_1 (0x2U << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00001000 */ 4818 #define RTC_TAMPCR_TAMPFREQ_Pos (8U) 4819 #define RTC_TAMPCR_TAMPFREQ_Msk (0x7U << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000700 */ 4820 #define RTC_TAMPCR_TAMPFREQ RTC_TAMPCR_TAMPFREQ_Msk /*!< */ 4821 #define RTC_TAMPCR_TAMPFREQ_0 (0x1U << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000100 */ 4822 #define RTC_TAMPCR_TAMPFREQ_1 (0x2U << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000200 */ 4823 #define RTC_TAMPCR_TAMPFREQ_2 (0x4U << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000400 */ 4824 #define RTC_TAMPCR_TAMPTS_Pos (7U) 4825 #define RTC_TAMPCR_TAMPTS_Msk (0x1U << RTC_TAMPCR_TAMPTS_Pos) /*!< 0x00000080 */ 4826 #define RTC_TAMPCR_TAMPTS RTC_TAMPCR_TAMPTS_Msk /*!< */ 4827 #define RTC_TAMPCR_TAMP3TRG_Pos (6U) 4828 #define RTC_TAMPCR_TAMP3TRG_Msk (0x1U << RTC_TAMPCR_TAMP3TRG_Pos) /*!< 0x00000040 */ 4829 #define RTC_TAMPCR_TAMP3TRG RTC_TAMPCR_TAMP3TRG_Msk /*!< */ 4830 #define RTC_TAMPCR_TAMP3E_Pos (5U) 4831 #define RTC_TAMPCR_TAMP3E_Msk (0x1U << RTC_TAMPCR_TAMP3E_Pos) /*!< 0x00000020 */ 4832 #define RTC_TAMPCR_TAMP3E RTC_TAMPCR_TAMP3E_Msk /*!< */ 4833 #define RTC_TAMPCR_TAMP2TRG_Pos (4U) 4834 #define RTC_TAMPCR_TAMP2TRG_Msk (0x1U << RTC_TAMPCR_TAMP2TRG_Pos) /*!< 0x00000010 */ 4835 #define RTC_TAMPCR_TAMP2TRG RTC_TAMPCR_TAMP2TRG_Msk /*!< */ 4836 #define RTC_TAMPCR_TAMP2E_Pos (3U) 4837 #define RTC_TAMPCR_TAMP2E_Msk (0x1U << RTC_TAMPCR_TAMP2E_Pos) /*!< 0x00000008 */ 4838 #define RTC_TAMPCR_TAMP2E RTC_TAMPCR_TAMP2E_Msk /*!< */ 4839 #define RTC_TAMPCR_TAMPIE_Pos (2U) 4840 #define RTC_TAMPCR_TAMPIE_Msk (0x1U << RTC_TAMPCR_TAMPIE_Pos) /*!< 0x00000004 */ 4841 #define RTC_TAMPCR_TAMPIE RTC_TAMPCR_TAMPIE_Msk /*!< */ 4842 #define RTC_TAMPCR_TAMP1TRG_Pos (1U) 4843 #define RTC_TAMPCR_TAMP1TRG_Msk (0x1U << RTC_TAMPCR_TAMP1TRG_Pos) /*!< 0x00000002 */ 4844 #define RTC_TAMPCR_TAMP1TRG RTC_TAMPCR_TAMP1TRG_Msk /*!< */ 4845 #define RTC_TAMPCR_TAMP1E_Pos (0U) 4846 #define RTC_TAMPCR_TAMP1E_Msk (0x1U << RTC_TAMPCR_TAMP1E_Pos) /*!< 0x00000001 */ 4847 #define RTC_TAMPCR_TAMP1E RTC_TAMPCR_TAMP1E_Msk /*!< */ 4848 4849 /******************** Bits definition for RTC_ALRMASSR register *************/ 4850 #define RTC_ALRMASSR_MASKSS_Pos (24U) 4851 #define RTC_ALRMASSR_MASKSS_Msk (0xFU << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */ 4852 #define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk 4853 #define RTC_ALRMASSR_MASKSS_0 (0x1U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */ 4854 #define RTC_ALRMASSR_MASKSS_1 (0x2U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */ 4855 #define RTC_ALRMASSR_MASKSS_2 (0x4U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */ 4856 #define RTC_ALRMASSR_MASKSS_3 (0x8U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */ 4857 #define RTC_ALRMASSR_SS_Pos (0U) 4858 #define RTC_ALRMASSR_SS_Msk (0x7FFFU << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */ 4859 #define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk 4860 4861 /******************** Bits definition for RTC_ALRMBSSR register *************/ 4862 #define RTC_ALRMBSSR_MASKSS_Pos (24U) 4863 #define RTC_ALRMBSSR_MASKSS_Msk (0xFU << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */ 4864 #define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk 4865 #define RTC_ALRMBSSR_MASKSS_0 (0x1U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */ 4866 #define RTC_ALRMBSSR_MASKSS_1 (0x2U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */ 4867 #define RTC_ALRMBSSR_MASKSS_2 (0x4U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */ 4868 #define RTC_ALRMBSSR_MASKSS_3 (0x8U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */ 4869 #define RTC_ALRMBSSR_SS_Pos (0U) 4870 #define RTC_ALRMBSSR_SS_Msk (0x7FFFU << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */ 4871 #define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk 4872 4873 /******************** Bits definition for RTC_OR register ****************/ 4874 #define RTC_OR_OUT_RMP_Pos (1U) 4875 #define RTC_OR_OUT_RMP_Msk (0x1U << RTC_OR_OUT_RMP_Pos) /*!< 0x00000002 */ 4876 #define RTC_OR_OUT_RMP RTC_OR_OUT_RMP_Msk /*!< */ 4877 #define RTC_OR_ALARMOUTTYPE_Pos (0U) 4878 #define RTC_OR_ALARMOUTTYPE_Msk (0x1U << RTC_OR_ALARMOUTTYPE_Pos) /*!< 0x00000001 */ 4879 #define RTC_OR_ALARMOUTTYPE RTC_OR_ALARMOUTTYPE_Msk /*!< */ 4880 4881 /* Legacy defines */ 4882 #define RTC_OR_RTC_OUT_RMP RTC_OR_OUT_RMP 4883 4884 /******************** Bits definition for RTC_BKP0R register ****************/ 4885 #define RTC_BKP0R_Pos (0U) 4886 #define RTC_BKP0R_Msk (0xFFFFFFFFU << RTC_BKP0R_Pos) /*!< 0xFFFFFFFF */ 4887 #define RTC_BKP0R RTC_BKP0R_Msk /*!< */ 4888 4889 /******************** Bits definition for RTC_BKP1R register ****************/ 4890 #define RTC_BKP1R_Pos (0U) 4891 #define RTC_BKP1R_Msk (0xFFFFFFFFU << RTC_BKP1R_Pos) /*!< 0xFFFFFFFF */ 4892 #define RTC_BKP1R RTC_BKP1R_Msk /*!< */ 4893 4894 /******************** Bits definition for RTC_BKP2R register ****************/ 4895 #define RTC_BKP2R_Pos (0U) 4896 #define RTC_BKP2R_Msk (0xFFFFFFFFU << RTC_BKP2R_Pos) /*!< 0xFFFFFFFF */ 4897 #define RTC_BKP2R RTC_BKP2R_Msk /*!< */ 4898 4899 /******************** Bits definition for RTC_BKP3R register ****************/ 4900 #define RTC_BKP3R_Pos (0U) 4901 #define RTC_BKP3R_Msk (0xFFFFFFFFU << RTC_BKP3R_Pos) /*!< 0xFFFFFFFF */ 4902 #define RTC_BKP3R RTC_BKP3R_Msk /*!< */ 4903 4904 /******************** Bits definition for RTC_BKP4R register ****************/ 4905 #define RTC_BKP4R_Pos (0U) 4906 #define RTC_BKP4R_Msk (0xFFFFFFFFU << RTC_BKP4R_Pos) /*!< 0xFFFFFFFF */ 4907 #define RTC_BKP4R RTC_BKP4R_Msk /*!< */ 4908 4909 /******************** Number of backup registers ******************************/ 4910 #define RTC_BKP_NUMBER (0x00000005U) /*!< */ 4911 4912 /******************************************************************************/ 4913 /* */ 4914 /* Serial Peripheral Interface (SPI) */ 4915 /* */ 4916 /******************************************************************************/ 4917 4918 /* 4919 * @brief Specific device feature definitions (not present on all devices in the STM32L0 family) 4920 */ 4921 #define SPI_I2S_SUPPORT /*!< I2S support */ 4922 4923 /******************* Bit definition for SPI_CR1 register ********************/ 4924 #define SPI_CR1_CPHA_Pos (0U) 4925 #define SPI_CR1_CPHA_Msk (0x1U << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */ 4926 #define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!< Clock Phase */ 4927 #define SPI_CR1_CPOL_Pos (1U) 4928 #define SPI_CR1_CPOL_Msk (0x1U << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */ 4929 #define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!< Clock Polarity */ 4930 #define SPI_CR1_MSTR_Pos (2U) 4931 #define SPI_CR1_MSTR_Msk (0x1U << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */ 4932 #define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!< Master Selection */ 4933 #define SPI_CR1_BR_Pos (3U) 4934 #define SPI_CR1_BR_Msk (0x7U << SPI_CR1_BR_Pos) /*!< 0x00000038 */ 4935 #define SPI_CR1_BR SPI_CR1_BR_Msk /*!< BR[2:0] bits (Baud Rate Control) */ 4936 #define SPI_CR1_BR_0 (0x1U << SPI_CR1_BR_Pos) /*!< 0x00000008 */ 4937 #define SPI_CR1_BR_1 (0x2U << SPI_CR1_BR_Pos) /*!< 0x00000010 */ 4938 #define SPI_CR1_BR_2 (0x4U << SPI_CR1_BR_Pos) /*!< 0x00000020 */ 4939 #define SPI_CR1_SPE_Pos (6U) 4940 #define SPI_CR1_SPE_Msk (0x1U << SPI_CR1_SPE_Pos) /*!< 0x00000040 */ 4941 #define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!< SPI Enable */ 4942 #define SPI_CR1_LSBFIRST_Pos (7U) 4943 #define SPI_CR1_LSBFIRST_Msk (0x1U << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */ 4944 #define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!< Frame Format */ 4945 #define SPI_CR1_SSI_Pos (8U) 4946 #define SPI_CR1_SSI_Msk (0x1U << SPI_CR1_SSI_Pos) /*!< 0x00000100 */ 4947 #define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!< Internal slave select */ 4948 #define SPI_CR1_SSM_Pos (9U) 4949 #define SPI_CR1_SSM_Msk (0x1U << SPI_CR1_SSM_Pos) /*!< 0x00000200 */ 4950 #define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!< Software slave management */ 4951 #define SPI_CR1_RXONLY_Pos (10U) 4952 #define SPI_CR1_RXONLY_Msk (0x1U << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */ 4953 #define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!< Receive only */ 4954 #define SPI_CR1_DFF_Pos (11U) 4955 #define SPI_CR1_DFF_Msk (0x1U << SPI_CR1_DFF_Pos) /*!< 0x00000800 */ 4956 #define SPI_CR1_DFF SPI_CR1_DFF_Msk /*!< Data Frame Format */ 4957 #define SPI_CR1_CRCNEXT_Pos (12U) 4958 #define SPI_CR1_CRCNEXT_Msk (0x1U << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */ 4959 #define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!< Transmit CRC next */ 4960 #define SPI_CR1_CRCEN_Pos (13U) 4961 #define SPI_CR1_CRCEN_Msk (0x1U << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */ 4962 #define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!< Hardware CRC calculation enable */ 4963 #define SPI_CR1_BIDIOE_Pos (14U) 4964 #define SPI_CR1_BIDIOE_Msk (0x1U << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */ 4965 #define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!< Output enable in bidirectional mode */ 4966 #define SPI_CR1_BIDIMODE_Pos (15U) 4967 #define SPI_CR1_BIDIMODE_Msk (0x1U << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */ 4968 #define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!< Bidirectional data mode enable */ 4969 4970 /******************* Bit definition for SPI_CR2 register ********************/ 4971 #define SPI_CR2_RXDMAEN_Pos (0U) 4972 #define SPI_CR2_RXDMAEN_Msk (0x1U << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */ 4973 #define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!< Rx Buffer DMA Enable */ 4974 #define SPI_CR2_TXDMAEN_Pos (1U) 4975 #define SPI_CR2_TXDMAEN_Msk (0x1U << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */ 4976 #define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!< Tx Buffer DMA Enable */ 4977 #define SPI_CR2_SSOE_Pos (2U) 4978 #define SPI_CR2_SSOE_Msk (0x1U << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */ 4979 #define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!< SS Output Enable */ 4980 #define SPI_CR2_FRF_Pos (4U) 4981 #define SPI_CR2_FRF_Msk (0x1U << SPI_CR2_FRF_Pos) /*!< 0x00000010 */ 4982 #define SPI_CR2_FRF SPI_CR2_FRF_Msk /*!< Frame Format Enable */ 4983 #define SPI_CR2_ERRIE_Pos (5U) 4984 #define SPI_CR2_ERRIE_Msk (0x1U << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */ 4985 #define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!< Error Interrupt Enable */ 4986 #define SPI_CR2_RXNEIE_Pos (6U) 4987 #define SPI_CR2_RXNEIE_Msk (0x1U << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */ 4988 #define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!< RX buffer Not Empty Interrupt Enable */ 4989 #define SPI_CR2_TXEIE_Pos (7U) 4990 #define SPI_CR2_TXEIE_Msk (0x1U << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */ 4991 #define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!< Tx buffer Empty Interrupt Enable */ 4992 4993 /******************** Bit definition for SPI_SR register ********************/ 4994 #define SPI_SR_RXNE_Pos (0U) 4995 #define SPI_SR_RXNE_Msk (0x1U << SPI_SR_RXNE_Pos) /*!< 0x00000001 */ 4996 #define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!< Receive buffer Not Empty */ 4997 #define SPI_SR_TXE_Pos (1U) 4998 #define SPI_SR_TXE_Msk (0x1U << SPI_SR_TXE_Pos) /*!< 0x00000002 */ 4999 #define SPI_SR_TXE SPI_SR_TXE_Msk /*!< Transmit buffer Empty */ 5000 #define SPI_SR_CHSIDE_Pos (2U) 5001 #define SPI_SR_CHSIDE_Msk (0x1U << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */ 5002 #define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!< Channel side */ 5003 #define SPI_SR_UDR_Pos (3U) 5004 #define SPI_SR_UDR_Msk (0x1U << SPI_SR_UDR_Pos) /*!< 0x00000008 */ 5005 #define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */ 5006 #define SPI_SR_CRCERR_Pos (4U) 5007 #define SPI_SR_CRCERR_Msk (0x1U << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */ 5008 #define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!< CRC Error flag */ 5009 #define SPI_SR_MODF_Pos (5U) 5010 #define SPI_SR_MODF_Msk (0x1U << SPI_SR_MODF_Pos) /*!< 0x00000020 */ 5011 #define SPI_SR_MODF SPI_SR_MODF_Msk /*!< Mode fault */ 5012 #define SPI_SR_OVR_Pos (6U) 5013 #define SPI_SR_OVR_Msk (0x1U << SPI_SR_OVR_Pos) /*!< 0x00000040 */ 5014 #define SPI_SR_OVR SPI_SR_OVR_Msk /*!< Overrun flag */ 5015 #define SPI_SR_BSY_Pos (7U) 5016 #define SPI_SR_BSY_Msk (0x1U << SPI_SR_BSY_Pos) /*!< 0x00000080 */ 5017 #define SPI_SR_BSY SPI_SR_BSY_Msk /*!< Busy flag */ 5018 #define SPI_SR_FRE_Pos (8U) 5019 #define SPI_SR_FRE_Msk (0x1U << SPI_SR_FRE_Pos) /*!< 0x00000100 */ 5020 #define SPI_SR_FRE SPI_SR_FRE_Msk /*!< TI frame format error */ 5021 5022 /******************** Bit definition for SPI_DR register ********************/ 5023 #define SPI_DR_DR_Pos (0U) 5024 #define SPI_DR_DR_Msk (0xFFFFU << SPI_DR_DR_Pos) /*!< 0x0000FFFF */ 5025 #define SPI_DR_DR SPI_DR_DR_Msk /*!< Data Register */ 5026 5027 /******************* Bit definition for SPI_CRCPR register ******************/ 5028 #define SPI_CRCPR_CRCPOLY_Pos (0U) 5029 #define SPI_CRCPR_CRCPOLY_Msk (0xFFFFU << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */ 5030 #define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!< CRC polynomial register */ 5031 5032 /****************** Bit definition for SPI_RXCRCR register ******************/ 5033 #define SPI_RXCRCR_RXCRC_Pos (0U) 5034 #define SPI_RXCRCR_RXCRC_Msk (0xFFFFU << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */ 5035 #define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!< Rx CRC Register */ 5036 5037 /****************** Bit definition for SPI_TXCRCR register ******************/ 5038 #define SPI_TXCRCR_TXCRC_Pos (0U) 5039 #define SPI_TXCRCR_TXCRC_Msk (0xFFFFU << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */ 5040 #define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!< Tx CRC Register */ 5041 5042 /****************** Bit definition for SPI_I2SCFGR register *****************/ 5043 #define SPI_I2SCFGR_CHLEN_Pos (0U) 5044 #define SPI_I2SCFGR_CHLEN_Msk (0x1U << SPI_I2SCFGR_CHLEN_Pos) /*!< 0x00000001 */ 5045 #define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk /*!<Channel length (number of bits per audio channel) */ 5046 #define SPI_I2SCFGR_DATLEN_Pos (1U) 5047 #define SPI_I2SCFGR_DATLEN_Msk (0x3U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000006 */ 5048 #define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk /*!<DATLEN[1:0] bits (Data length to be transferred) */ 5049 #define SPI_I2SCFGR_DATLEN_0 (0x1U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000002 */ 5050 #define SPI_I2SCFGR_DATLEN_1 (0x2U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000004 */ 5051 #define SPI_I2SCFGR_CKPOL_Pos (3U) 5052 #define SPI_I2SCFGR_CKPOL_Msk (0x1U << SPI_I2SCFGR_CKPOL_Pos) /*!< 0x00000008 */ 5053 #define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk /*!<steady state clock polarity */ 5054 #define SPI_I2SCFGR_I2SSTD_Pos (4U) 5055 #define SPI_I2SCFGR_I2SSTD_Msk (0x3U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000030 */ 5056 #define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk /*!<I2SSTD[1:0] bits (I2S standard selection) */ 5057 #define SPI_I2SCFGR_I2SSTD_0 (0x1U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000010 */ 5058 #define SPI_I2SCFGR_I2SSTD_1 (0x2U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000020 */ 5059 #define SPI_I2SCFGR_PCMSYNC_Pos (7U) 5060 #define SPI_I2SCFGR_PCMSYNC_Msk (0x1U << SPI_I2SCFGR_PCMSYNC_Pos) /*!< 0x00000080 */ 5061 #define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk /*!<PCM frame synchronization */ 5062 #define SPI_I2SCFGR_I2SCFG_Pos (8U) 5063 #define SPI_I2SCFGR_I2SCFG_Msk (0x3U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000300 */ 5064 #define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk /*!<I2SCFG[1:0] bits (I2S configuration mode) */ 5065 #define SPI_I2SCFGR_I2SCFG_0 (0x1U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000100 */ 5066 #define SPI_I2SCFGR_I2SCFG_1 (0x2U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000200 */ 5067 #define SPI_I2SCFGR_I2SE_Pos (10U) 5068 #define SPI_I2SCFGR_I2SE_Msk (0x1U << SPI_I2SCFGR_I2SE_Pos) /*!< 0x00000400 */ 5069 #define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk /*!<I2S Enable */ 5070 #define SPI_I2SCFGR_I2SMOD_Pos (11U) 5071 #define SPI_I2SCFGR_I2SMOD_Msk (0x1U << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */ 5072 #define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!<I2S mode selection */ 5073 #define SPI_I2SCFGR_ASTRTEN_Pos (12U) 5074 #define SPI_I2SCFGR_ASTRTEN_Msk (0x1U << SPI_I2SCFGR_ASTRTEN_Pos) /*!< 0x00001000 */ 5075 #define SPI_I2SCFGR_ASTRTEN SPI_I2SCFGR_ASTRTEN_Msk /*!<Asynchronous start enable */ 5076 /****************** Bit definition for SPI_I2SPR register *******************/ 5077 #define SPI_I2SPR_I2SDIV_Pos (0U) 5078 #define SPI_I2SPR_I2SDIV_Msk (0xFFU << SPI_I2SPR_I2SDIV_Pos) /*!< 0x000000FF */ 5079 #define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk /*!<I2S Linear prescaler */ 5080 #define SPI_I2SPR_ODD_Pos (8U) 5081 #define SPI_I2SPR_ODD_Msk (0x1U << SPI_I2SPR_ODD_Pos) /*!< 0x00000100 */ 5082 #define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk /*!<Odd factor for the prescaler */ 5083 #define SPI_I2SPR_MCKOE_Pos (9U) 5084 #define SPI_I2SPR_MCKOE_Msk (0x1U << SPI_I2SPR_MCKOE_Pos) /*!< 0x00000200 */ 5085 #define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk /*!<Master Clock Output Enable */ 5086 5087 /******************************************************************************/ 5088 /* */ 5089 /* System Configuration (SYSCFG) */ 5090 /* */ 5091 /******************************************************************************/ 5092 /***************** Bit definition for SYSCFG_CFGR1 register ****************/ 5093 #define SYSCFG_CFGR1_MEM_MODE_Pos (0U) 5094 #define SYSCFG_CFGR1_MEM_MODE_Msk (0x3U << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000003 */ 5095 #define SYSCFG_CFGR1_MEM_MODE SYSCFG_CFGR1_MEM_MODE_Msk /*!< SYSCFG_Memory Remap Config */ 5096 #define SYSCFG_CFGR1_MEM_MODE_0 (0x1U << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000001 */ 5097 #define SYSCFG_CFGR1_MEM_MODE_1 (0x2U << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000002 */ 5098 #define SYSCFG_CFGR1_UFB_Pos (3U) 5099 #define SYSCFG_CFGR1_UFB_Msk (0x1U << SYSCFG_CFGR1_UFB_Pos) /*!< 0x00000008 */ 5100 #define SYSCFG_CFGR1_UFB SYSCFG_CFGR1_UFB_Msk /*!< User bank swapping */ 5101 #define SYSCFG_CFGR1_BOOT_MODE_Pos (8U) 5102 #define SYSCFG_CFGR1_BOOT_MODE_Msk (0x3U << SYSCFG_CFGR1_BOOT_MODE_Pos) /*!< 0x00000300 */ 5103 #define SYSCFG_CFGR1_BOOT_MODE SYSCFG_CFGR1_BOOT_MODE_Msk /*!< SYSCFG_Boot mode Config */ 5104 #define SYSCFG_CFGR1_BOOT_MODE_0 (0x1U << SYSCFG_CFGR1_BOOT_MODE_Pos) /*!< 0x00000100 */ 5105 #define SYSCFG_CFGR1_BOOT_MODE_1 (0x2U << SYSCFG_CFGR1_BOOT_MODE_Pos) /*!< 0x00000200 */ 5106 5107 /***************** Bit definition for SYSCFG_CFGR2 register ****************/ 5108 #define SYSCFG_CFGR2_FWDISEN_Pos (0U) 5109 #define SYSCFG_CFGR2_FWDISEN_Msk (0x1U << SYSCFG_CFGR2_FWDISEN_Pos) /*!< 0x00000001 */ 5110 #define SYSCFG_CFGR2_FWDISEN SYSCFG_CFGR2_FWDISEN_Msk /*!< Firewall disable bit */ 5111 #define SYSCFG_CFGR2_I2C_PB6_FMP_Pos (8U) 5112 #define SYSCFG_CFGR2_I2C_PB6_FMP_Msk (0x1U << SYSCFG_CFGR2_I2C_PB6_FMP_Pos) /*!< 0x00000100 */ 5113 #define SYSCFG_CFGR2_I2C_PB6_FMP SYSCFG_CFGR2_I2C_PB6_FMP_Msk /*!< I2C PB6 Fast mode plus */ 5114 #define SYSCFG_CFGR2_I2C_PB7_FMP_Pos (9U) 5115 #define SYSCFG_CFGR2_I2C_PB7_FMP_Msk (0x1U << SYSCFG_CFGR2_I2C_PB7_FMP_Pos) /*!< 0x00000200 */ 5116 #define SYSCFG_CFGR2_I2C_PB7_FMP SYSCFG_CFGR2_I2C_PB7_FMP_Msk /*!< I2C PB7 Fast mode plus */ 5117 #define SYSCFG_CFGR2_I2C_PB8_FMP_Pos (10U) 5118 #define SYSCFG_CFGR2_I2C_PB8_FMP_Msk (0x1U << SYSCFG_CFGR2_I2C_PB8_FMP_Pos) /*!< 0x00000400 */ 5119 #define SYSCFG_CFGR2_I2C_PB8_FMP SYSCFG_CFGR2_I2C_PB8_FMP_Msk /*!< I2C PB8 Fast mode plus */ 5120 #define SYSCFG_CFGR2_I2C_PB9_FMP_Pos (11U) 5121 #define SYSCFG_CFGR2_I2C_PB9_FMP_Msk (0x1U << SYSCFG_CFGR2_I2C_PB9_FMP_Pos) /*!< 0x00000800 */ 5122 #define SYSCFG_CFGR2_I2C_PB9_FMP SYSCFG_CFGR2_I2C_PB9_FMP_Msk /*!< I2C PB9 Fast mode plus */ 5123 #define SYSCFG_CFGR2_I2C1_FMP_Pos (12U) 5124 #define SYSCFG_CFGR2_I2C1_FMP_Msk (0x1U << SYSCFG_CFGR2_I2C1_FMP_Pos) /*!< 0x00001000 */ 5125 #define SYSCFG_CFGR2_I2C1_FMP SYSCFG_CFGR2_I2C1_FMP_Msk /*!< I2C1 Fast mode plus */ 5126 #define SYSCFG_CFGR2_I2C2_FMP_Pos (13U) 5127 #define SYSCFG_CFGR2_I2C2_FMP_Msk (0x1U << SYSCFG_CFGR2_I2C2_FMP_Pos) /*!< 0x00002000 */ 5128 #define SYSCFG_CFGR2_I2C2_FMP SYSCFG_CFGR2_I2C2_FMP_Msk /*!< I2C2 Fast mode plus */ 5129 #define SYSCFG_CFGR2_I2C3_FMP_Pos (14U) 5130 #define SYSCFG_CFGR2_I2C3_FMP_Msk (0x1U << SYSCFG_CFGR2_I2C3_FMP_Pos) /*!< 0x00004000 */ 5131 #define SYSCFG_CFGR2_I2C3_FMP SYSCFG_CFGR2_I2C3_FMP_Msk /*!< I2C3 Fast mode plus */ 5132 5133 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/ 5134 #define SYSCFG_EXTICR1_EXTI0_Pos (0U) 5135 #define SYSCFG_EXTICR1_EXTI0_Msk (0xFU << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */ 5136 #define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk /*!< EXTI 0 configuration */ 5137 #define SYSCFG_EXTICR1_EXTI1_Pos (4U) 5138 #define SYSCFG_EXTICR1_EXTI1_Msk (0xFU << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */ 5139 #define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk /*!< EXTI 1 configuration */ 5140 #define SYSCFG_EXTICR1_EXTI2_Pos (8U) 5141 #define SYSCFG_EXTICR1_EXTI2_Msk (0xFU << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */ 5142 #define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk /*!< EXTI 2 configuration */ 5143 #define SYSCFG_EXTICR1_EXTI3_Pos (12U) 5144 #define SYSCFG_EXTICR1_EXTI3_Msk (0xFU << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */ 5145 #define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk /*!< EXTI 3 configuration */ 5146 5147 /** 5148 * @brief EXTI0 configuration 5149 */ 5150 #define SYSCFG_EXTICR1_EXTI0_PA (0x00000000U) /*!< PA[0] pin */ 5151 #define SYSCFG_EXTICR1_EXTI0_PB (0x00000001U) /*!< PB[0] pin */ 5152 #define SYSCFG_EXTICR1_EXTI0_PC (0x00000002U) /*!< PC[0] pin */ 5153 #define SYSCFG_EXTICR1_EXTI0_PD (0x00000003U) /*!< PD[0] pin */ 5154 #define SYSCFG_EXTICR1_EXTI0_PE (0x00000004U) /*!< PE[0] pin */ 5155 #define SYSCFG_EXTICR1_EXTI0_PH (0x00000005U) /*!< PH[0] pin */ 5156 5157 /** 5158 * @brief EXTI1 configuration 5159 */ 5160 #define SYSCFG_EXTICR1_EXTI1_PA (0x00000000U) /*!< PA[1] pin */ 5161 #define SYSCFG_EXTICR1_EXTI1_PB (0x00000010U) /*!< PB[1] pin */ 5162 #define SYSCFG_EXTICR1_EXTI1_PC (0x00000020U) /*!< PC[1] pin */ 5163 #define SYSCFG_EXTICR1_EXTI1_PD (0x00000030U) /*!< PD[1] pin */ 5164 #define SYSCFG_EXTICR1_EXTI1_PE (0x00000040U) /*!< PE[1] pin */ 5165 #define SYSCFG_EXTICR1_EXTI1_PH (0x00000050U) /*!< PH[1] pin */ 5166 5167 /** 5168 * @brief EXTI2 configuration 5169 */ 5170 #define SYSCFG_EXTICR1_EXTI2_PA (0x00000000U) /*!< PA[2] pin */ 5171 #define SYSCFG_EXTICR1_EXTI2_PB (0x00000100U) /*!< PB[2] pin */ 5172 #define SYSCFG_EXTICR1_EXTI2_PC (0x00000200U) /*!< PC[2] pin */ 5173 #define SYSCFG_EXTICR1_EXTI2_PD (0x00000300U) /*!< PD[2] pin */ 5174 #define SYSCFG_EXTICR1_EXTI2_PE (0x00000400U) /*!< PE[2] pin */ 5175 5176 /** 5177 * @brief EXTI3 configuration 5178 */ 5179 #define SYSCFG_EXTICR1_EXTI3_PA (0x00000000U) /*!< PA[3] pin */ 5180 #define SYSCFG_EXTICR1_EXTI3_PB (0x00001000U) /*!< PB[3] pin */ 5181 #define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!< PC[3] pin */ 5182 #define SYSCFG_EXTICR1_EXTI3_PD (0x00003000U) /*!< PD[3] pin */ 5183 #define SYSCFG_EXTICR1_EXTI3_PE (0x00004000U) /*!< PE[3] pin */ 5184 5185 /***************** Bit definition for SYSCFG_EXTICR2 register *****************/ 5186 #define SYSCFG_EXTICR2_EXTI4_Pos (0U) 5187 #define SYSCFG_EXTICR2_EXTI4_Msk (0xFU << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */ 5188 #define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!< EXTI 4 configuration */ 5189 #define SYSCFG_EXTICR2_EXTI5_Pos (4U) 5190 #define SYSCFG_EXTICR2_EXTI5_Msk (0xFU << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */ 5191 #define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk /*!< EXTI 5 configuration */ 5192 #define SYSCFG_EXTICR2_EXTI6_Pos (8U) 5193 #define SYSCFG_EXTICR2_EXTI6_Msk (0xFU << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */ 5194 #define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk /*!< EXTI 6 configuration */ 5195 #define SYSCFG_EXTICR2_EXTI7_Pos (12U) 5196 #define SYSCFG_EXTICR2_EXTI7_Msk (0xFU << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */ 5197 #define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk /*!< EXTI 7 configuration */ 5198 5199 /** 5200 * @brief EXTI4 configuration 5201 */ 5202 #define SYSCFG_EXTICR2_EXTI4_PA (0x00000000U) /*!< PA[4] pin */ 5203 #define SYSCFG_EXTICR2_EXTI4_PB (0x00000001U) /*!< PB[4] pin */ 5204 #define SYSCFG_EXTICR2_EXTI4_PC (0x00000002U) /*!< PC[4] pin */ 5205 #define SYSCFG_EXTICR2_EXTI4_PD (0x00000003U) /*!< PD[4] pin */ 5206 #define SYSCFG_EXTICR2_EXTI4_PE (0x00000004U) /*!< PE[4] pin */ 5207 5208 /** 5209 * @brief EXTI5 configuration 5210 */ 5211 #define SYSCFG_EXTICR2_EXTI5_PA (0x00000000U) /*!< PA[5] pin */ 5212 #define SYSCFG_EXTICR2_EXTI5_PB (0x00000010U) /*!< PB[5] pin */ 5213 #define SYSCFG_EXTICR2_EXTI5_PC (0x00000020U) /*!< PC[5] pin */ 5214 #define SYSCFG_EXTICR2_EXTI5_PD (0x00000030U) /*!< PD[5] pin */ 5215 #define SYSCFG_EXTICR2_EXTI5_PE (0x00000040U) /*!< PE[5] pin */ 5216 5217 /** 5218 * @brief EXTI6 configuration 5219 */ 5220 #define SYSCFG_EXTICR2_EXTI6_PA (0x00000000U) /*!< PA[6] pin */ 5221 #define SYSCFG_EXTICR2_EXTI6_PB (0x00000100U) /*!< PB[6] pin */ 5222 #define SYSCFG_EXTICR2_EXTI6_PC (0x00000200U) /*!< PC[6] pin */ 5223 #define SYSCFG_EXTICR2_EXTI6_PD (0x00000300U) /*!< PD[6] pin */ 5224 #define SYSCFG_EXTICR2_EXTI6_PE (0x00000400U) /*!< PE[6] pin */ 5225 5226 /** 5227 * @brief EXTI7 configuration 5228 */ 5229 #define SYSCFG_EXTICR2_EXTI7_PA (0x00000000U) /*!< PA[7] pin */ 5230 #define SYSCFG_EXTICR2_EXTI7_PB (0x00001000U) /*!< PB[7] pin */ 5231 #define SYSCFG_EXTICR2_EXTI7_PC (0x00002000U) /*!< PC[7] pin */ 5232 #define SYSCFG_EXTICR2_EXTI7_PD (0x00003000U) /*!< PD[7] pin */ 5233 #define SYSCFG_EXTICR2_EXTI7_PE (0x00004000U) /*!< PE[7] pin */ 5234 5235 /***************** Bit definition for SYSCFG_EXTICR3 register *****************/ 5236 #define SYSCFG_EXTICR3_EXTI8_Pos (0U) 5237 #define SYSCFG_EXTICR3_EXTI8_Msk (0xFU << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */ 5238 #define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk /*!< EXTI 8 configuration */ 5239 #define SYSCFG_EXTICR3_EXTI9_Pos (4U) 5240 #define SYSCFG_EXTICR3_EXTI9_Msk (0xFU << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */ 5241 #define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk /*!< EXTI 9 configuration */ 5242 #define SYSCFG_EXTICR3_EXTI10_Pos (8U) 5243 #define SYSCFG_EXTICR3_EXTI10_Msk (0xFU << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */ 5244 #define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk /*!< EXTI 10 configuration */ 5245 #define SYSCFG_EXTICR3_EXTI11_Pos (12U) 5246 #define SYSCFG_EXTICR3_EXTI11_Msk (0xFU << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */ 5247 #define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk /*!< EXTI 11 configuration */ 5248 5249 /** 5250 * @brief EXTI8 configuration 5251 */ 5252 #define SYSCFG_EXTICR3_EXTI8_PA (0x00000000U) /*!< PA[8] pin */ 5253 #define SYSCFG_EXTICR3_EXTI8_PB (0x00000001U) /*!< PB[8] pin */ 5254 #define SYSCFG_EXTICR3_EXTI8_PC (0x00000002U) /*!< PC[8] pin */ 5255 #define SYSCFG_EXTICR3_EXTI8_PD (0x00000003U) /*!< PD[8] pin */ 5256 #define SYSCFG_EXTICR3_EXTI8_PE (0x00000004U) /*!< PE[8] pin */ 5257 5258 /** 5259 * @brief EXTI9 configuration 5260 */ 5261 #define SYSCFG_EXTICR3_EXTI9_PA (0x00000000U) /*!< PA[9] pin */ 5262 #define SYSCFG_EXTICR3_EXTI9_PB (0x00000010U) /*!< PB[9] pin */ 5263 #define SYSCFG_EXTICR3_EXTI9_PC (0x00000020U) /*!< PC[9] pin */ 5264 #define SYSCFG_EXTICR3_EXTI9_PD (0x00000030U) /*!< PD[9] pin */ 5265 #define SYSCFG_EXTICR3_EXTI9_PE (0x00000040U) /*!< PE[9] pin */ 5266 #define SYSCFG_EXTICR3_EXTI9_PH (0x00000050U) /*!< PH[9] pin */ 5267 5268 /** 5269 * @brief EXTI10 configuration 5270 */ 5271 #define SYSCFG_EXTICR3_EXTI10_PA (0x00000000U) /*!< PA[10] pin */ 5272 #define SYSCFG_EXTICR3_EXTI10_PB (0x00000100U) /*!< PB[10] pin */ 5273 #define SYSCFG_EXTICR3_EXTI10_PC (0x00000200U) /*!< PC[10] pin */ 5274 #define SYSCFG_EXTICR3_EXTI10_PD (0x00000300U) /*!< PD[10] pin */ 5275 #define SYSCFG_EXTICR3_EXTI10_PE (0x00000400U) /*!< PE[10] pin */ 5276 #define SYSCFG_EXTICR3_EXTI10_PH (0x00000500U) /*!< PH[10] pin */ 5277 5278 /** 5279 * @brief EXTI11 configuration 5280 */ 5281 #define SYSCFG_EXTICR3_EXTI11_PA (0x00000000U) /*!< PA[11] pin */ 5282 #define SYSCFG_EXTICR3_EXTI11_PB (0x00001000U) /*!< PB[11] pin */ 5283 #define SYSCFG_EXTICR3_EXTI11_PC (0x00002000U) /*!< PC[11] pin */ 5284 #define SYSCFG_EXTICR3_EXTI11_PD (0x00003000U) /*!< PD[11] pin */ 5285 #define SYSCFG_EXTICR3_EXTI11_PE (0x00004000U) /*!< PE[11] pin */ 5286 5287 /***************** Bit definition for SYSCFG_EXTICR4 register *****************/ 5288 #define SYSCFG_EXTICR4_EXTI12_Pos (0U) 5289 #define SYSCFG_EXTICR4_EXTI12_Msk (0xFU << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */ 5290 #define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk /*!< EXTI 12 configuration */ 5291 #define SYSCFG_EXTICR4_EXTI13_Pos (4U) 5292 #define SYSCFG_EXTICR4_EXTI13_Msk (0xFU << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */ 5293 #define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk /*!< EXTI 13 configuration */ 5294 #define SYSCFG_EXTICR4_EXTI14_Pos (8U) 5295 #define SYSCFG_EXTICR4_EXTI14_Msk (0xFU << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */ 5296 #define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk /*!< EXTI 14 configuration */ 5297 #define SYSCFG_EXTICR4_EXTI15_Pos (12U) 5298 #define SYSCFG_EXTICR4_EXTI15_Msk (0xFU << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */ 5299 #define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk /*!< EXTI 15 configuration */ 5300 5301 /** 5302 * @brief EXTI12 configuration 5303 */ 5304 #define SYSCFG_EXTICR4_EXTI12_PA (0x00000000U) /*!< PA[12] pin */ 5305 #define SYSCFG_EXTICR4_EXTI12_PB (0x00000001U) /*!< PB[12] pin */ 5306 #define SYSCFG_EXTICR4_EXTI12_PC (0x00000002U) /*!< PC[12] pin */ 5307 #define SYSCFG_EXTICR4_EXTI12_PD (0x00000003U) /*!< PD[12] pin */ 5308 #define SYSCFG_EXTICR4_EXTI12_PE (0x00000004U) /*!< PE[12] pin */ 5309 5310 /** 5311 * @brief EXTI13 configuration 5312 */ 5313 #define SYSCFG_EXTICR4_EXTI13_PA (0x00000000U) /*!< PA[13] pin */ 5314 #define SYSCFG_EXTICR4_EXTI13_PB (0x00000010U) /*!< PB[13] pin */ 5315 #define SYSCFG_EXTICR4_EXTI13_PC (0x00000020U) /*!< PC[13] pin */ 5316 #define SYSCFG_EXTICR4_EXTI13_PD (0x00000030U) /*!< PD[13] pin */ 5317 #define SYSCFG_EXTICR4_EXTI13_PE (0x00000040U) /*!< PE[13] pin */ 5318 5319 /** 5320 * @brief EXTI14 configuration 5321 */ 5322 #define SYSCFG_EXTICR4_EXTI14_PA (0x00000000U) /*!< PA[14] pin */ 5323 #define SYSCFG_EXTICR4_EXTI14_PB (0x00000100U) /*!< PB[14] pin */ 5324 #define SYSCFG_EXTICR4_EXTI14_PC (0x00000200U) /*!< PC[14] pin */ 5325 #define SYSCFG_EXTICR4_EXTI14_PD (0x00000300U) /*!< PD[14] pin */ 5326 #define SYSCFG_EXTICR4_EXTI14_PE (0x00000400U) /*!< PE[14] pin */ 5327 5328 /** 5329 * @brief EXTI15 configuration 5330 */ 5331 #define SYSCFG_EXTICR4_EXTI15_PA (0x00000000U) /*!< PA[15] pin */ 5332 #define SYSCFG_EXTICR4_EXTI15_PB (0x00001000U) /*!< PB[15] pin */ 5333 #define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U) /*!< PC[15] pin */ 5334 #define SYSCFG_EXTICR4_EXTI15_PD (0x00003000U) /*!< PD[15] pin */ 5335 #define SYSCFG_EXTICR4_EXTI15_PE (0x00004000U) /*!< PE[15] pin */ 5336 5337 5338 /***************** Bit definition for SYSCFG_CFGR3 register ****************/ 5339 #define SYSCFG_CFGR3_VREF_OUT_Pos (4U) 5340 #define SYSCFG_CFGR3_VREF_OUT_Msk (0x3U << SYSCFG_CFGR3_VREF_OUT_Pos) /*!< 0x00000030 */ 5341 #define SYSCFG_CFGR3_VREF_OUT SYSCFG_CFGR3_VREF_OUT_Msk /*!< Verf_ADC connection bit */ 5342 #define SYSCFG_CFGR3_VREF_OUT_0 (0x1U << SYSCFG_CFGR3_VREF_OUT_Pos) /*!< 0x00000010 */ 5343 #define SYSCFG_CFGR3_VREF_OUT_1 (0x2U << SYSCFG_CFGR3_VREF_OUT_Pos) /*!< 0x00000020 */ 5344 #define SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Pos (8U) 5345 #define SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Msk (0x1U << SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Pos) /*!< 0x00000100 */ 5346 #define SYSCFG_CFGR3_ENBUF_VREFINT_ADC SYSCFG_CFGR3_ENBUF_VREFINT_ADC_Msk /*!< VREFINT reference for ADC enable bit */ 5347 #define SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Pos (9U) 5348 #define SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Msk (0x1U << SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Pos) /*!< 0x00000200 */ 5349 #define SYSCFG_CFGR3_ENBUF_SENSOR_ADC SYSCFG_CFGR3_ENBUF_SENSOR_ADC_Msk /*!< Sensor reference for ADC enable bit */ 5350 #define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Pos (12U) 5351 #define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Msk (0x1U << SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Pos) /*!< 0x00001000 */ 5352 #define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP_Msk /*!< VREFINT reference for comparator 2 enable bit */ 5353 #define SYSCFG_CFGR3_VREFINT_RDYF_Pos (30U) 5354 #define SYSCFG_CFGR3_VREFINT_RDYF_Msk (0x1U << SYSCFG_CFGR3_VREFINT_RDYF_Pos) /*!< 0x40000000 */ 5355 #define SYSCFG_CFGR3_VREFINT_RDYF SYSCFG_CFGR3_VREFINT_RDYF_Msk /*!< VREFINT ready flag */ 5356 #define SYSCFG_CFGR3_REF_LOCK_Pos (31U) 5357 #define SYSCFG_CFGR3_REF_LOCK_Msk (0x1U << SYSCFG_CFGR3_REF_LOCK_Pos) /*!< 0x80000000 */ 5358 #define SYSCFG_CFGR3_REF_LOCK SYSCFG_CFGR3_REF_LOCK_Msk /*!< CFGR3 lock bit */ 5359 5360 /* Legacy defines */ 5361 5362 #define SYSCFG_CFGR3_ENBUF_BGAP_ADC SYSCFG_CFGR3_ENBUF_VREFINT_ADC 5363 #define SYSCFG_CFGR3_ENBUFLP_BGAP_COMP SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP 5364 #define SYSCFG_VREFINT_ADC_RDYF SYSCFG_CFGR3_VREFINT_RDYF 5365 #define SYSCFG_CFGR3_SENSOR_ADC_RDYF SYSCFG_CFGR3_VREFINT_RDYF 5366 #define SYSCFG_CFGR3_VREFINT_ADC_RDYF SYSCFG_CFGR3_VREFINT_RDYF 5367 #define SYSCFG_CFGR3_VREFINT_COMP_RDYF SYSCFG_CFGR3_VREFINT_RDYF 5368 5369 /******************************************************************************/ 5370 /* */ 5371 /* Timers (TIM) */ 5372 /* */ 5373 /******************************************************************************/ 5374 /* 5375 * @brief Specific device feature definitions (not present on all devices in the STM32L0 family) 5376 */ 5377 #if defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) \ 5378 || defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx) 5379 #define TIM_TIM2_REMAP_HSI_SUPPORT /*!<Support remap HSI on TIM2 */ 5380 #define TIM_TIM2_REMAP_HSI48_SUPPORT /*!<Support remap HSI48 on TIM2 */ 5381 #else 5382 #define TIM_TIM2_REMAP_HSI48_SUPPORT /*!<Support remap HSI48 on TIM2 */ 5383 #endif 5384 5385 /******************* Bit definition for TIM_CR1 register ********************/ 5386 #define TIM_CR1_CEN_Pos (0U) 5387 #define TIM_CR1_CEN_Msk (0x1U << TIM_CR1_CEN_Pos) /*!< 0x00000001 */ 5388 #define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */ 5389 #define TIM_CR1_UDIS_Pos (1U) 5390 #define TIM_CR1_UDIS_Msk (0x1U << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */ 5391 #define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */ 5392 #define TIM_CR1_URS_Pos (2U) 5393 #define TIM_CR1_URS_Msk (0x1U << TIM_CR1_URS_Pos) /*!< 0x00000004 */ 5394 #define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */ 5395 #define TIM_CR1_OPM_Pos (3U) 5396 #define TIM_CR1_OPM_Msk (0x1U << TIM_CR1_OPM_Pos) /*!< 0x00000008 */ 5397 #define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */ 5398 #define TIM_CR1_DIR_Pos (4U) 5399 #define TIM_CR1_DIR_Msk (0x1U << TIM_CR1_DIR_Pos) /*!< 0x00000010 */ 5400 #define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */ 5401 5402 #define TIM_CR1_CMS_Pos (5U) 5403 #define TIM_CR1_CMS_Msk (0x3U << TIM_CR1_CMS_Pos) /*!< 0x00000060 */ 5404 #define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */ 5405 #define TIM_CR1_CMS_0 (0x1U << TIM_CR1_CMS_Pos) /*!< 0x00000020 */ 5406 #define TIM_CR1_CMS_1 (0x2U << TIM_CR1_CMS_Pos) /*!< 0x00000040 */ 5407 5408 #define TIM_CR1_ARPE_Pos (7U) 5409 #define TIM_CR1_ARPE_Msk (0x1U << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */ 5410 #define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */ 5411 5412 #define TIM_CR1_CKD_Pos (8U) 5413 #define TIM_CR1_CKD_Msk (0x3U << TIM_CR1_CKD_Pos) /*!< 0x00000300 */ 5414 #define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */ 5415 #define TIM_CR1_CKD_0 (0x1U << TIM_CR1_CKD_Pos) /*!< 0x00000100 */ 5416 #define TIM_CR1_CKD_1 (0x2U << TIM_CR1_CKD_Pos) /*!< 0x00000200 */ 5417 5418 /******************* Bit definition for TIM_CR2 register ********************/ 5419 #define TIM_CR2_CCDS_Pos (3U) 5420 #define TIM_CR2_CCDS_Msk (0x1U << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */ 5421 #define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */ 5422 5423 #define TIM_CR2_MMS_Pos (4U) 5424 #define TIM_CR2_MMS_Msk (0x7U << TIM_CR2_MMS_Pos) /*!< 0x00000070 */ 5425 #define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */ 5426 #define TIM_CR2_MMS_0 (0x1U << TIM_CR2_MMS_Pos) /*!< 0x00000010 */ 5427 #define TIM_CR2_MMS_1 (0x2U << TIM_CR2_MMS_Pos) /*!< 0x00000020 */ 5428 #define TIM_CR2_MMS_2 (0x4U << TIM_CR2_MMS_Pos) /*!< 0x00000040 */ 5429 5430 #define TIM_CR2_TI1S_Pos (7U) 5431 #define TIM_CR2_TI1S_Msk (0x1U << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */ 5432 #define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */ 5433 5434 /******************* Bit definition for TIM_SMCR register *******************/ 5435 #define TIM_SMCR_SMS_Pos (0U) 5436 #define TIM_SMCR_SMS_Msk (0x7U << TIM_SMCR_SMS_Pos) /*!< 0x00000007 */ 5437 #define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */ 5438 #define TIM_SMCR_SMS_0 (0x1U << TIM_SMCR_SMS_Pos) /*!< 0x00000001 */ 5439 #define TIM_SMCR_SMS_1 (0x2U << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */ 5440 #define TIM_SMCR_SMS_2 (0x4U << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */ 5441 5442 #define TIM_SMCR_OCCS_Pos (3U) 5443 #define TIM_SMCR_OCCS_Msk (0x1U << TIM_SMCR_OCCS_Pos) /*!< 0x00000008 */ 5444 #define TIM_SMCR_OCCS TIM_SMCR_OCCS_Msk /*!< OCREF clear selection */ 5445 5446 #define TIM_SMCR_TS_Pos (4U) 5447 #define TIM_SMCR_TS_Msk (0x7U << TIM_SMCR_TS_Pos) /*!< 0x00000070 */ 5448 #define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */ 5449 #define TIM_SMCR_TS_0 (0x1U << TIM_SMCR_TS_Pos) /*!< 0x00000010 */ 5450 #define TIM_SMCR_TS_1 (0x2U << TIM_SMCR_TS_Pos) /*!< 0x00000020 */ 5451 #define TIM_SMCR_TS_2 (0x4U << TIM_SMCR_TS_Pos) /*!< 0x00000040 */ 5452 5453 #define TIM_SMCR_MSM_Pos (7U) 5454 #define TIM_SMCR_MSM_Msk (0x1U << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */ 5455 #define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */ 5456 5457 #define TIM_SMCR_ETF_Pos (8U) 5458 #define TIM_SMCR_ETF_Msk (0xFU << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */ 5459 #define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */ 5460 #define TIM_SMCR_ETF_0 (0x1U << TIM_SMCR_ETF_Pos) /*!< 0x00000100 */ 5461 #define TIM_SMCR_ETF_1 (0x2U << TIM_SMCR_ETF_Pos) /*!< 0x00000200 */ 5462 #define TIM_SMCR_ETF_2 (0x4U << TIM_SMCR_ETF_Pos) /*!< 0x00000400 */ 5463 #define TIM_SMCR_ETF_3 (0x8U << TIM_SMCR_ETF_Pos) /*!< 0x00000800 */ 5464 5465 #define TIM_SMCR_ETPS_Pos (12U) 5466 #define TIM_SMCR_ETPS_Msk (0x3U << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */ 5467 #define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */ 5468 #define TIM_SMCR_ETPS_0 (0x1U << TIM_SMCR_ETPS_Pos) /*!< 0x00001000 */ 5469 #define TIM_SMCR_ETPS_1 (0x2U << TIM_SMCR_ETPS_Pos) /*!< 0x00002000 */ 5470 5471 #define TIM_SMCR_ECE_Pos (14U) 5472 #define TIM_SMCR_ECE_Msk (0x1U << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */ 5473 #define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */ 5474 #define TIM_SMCR_ETP_Pos (15U) 5475 #define TIM_SMCR_ETP_Msk (0x1U << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */ 5476 #define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */ 5477 5478 /******************* Bit definition for TIM_DIER register *******************/ 5479 #define TIM_DIER_UIE_Pos (0U) 5480 #define TIM_DIER_UIE_Msk (0x1U << TIM_DIER_UIE_Pos) /*!< 0x00000001 */ 5481 #define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */ 5482 #define TIM_DIER_CC1IE_Pos (1U) 5483 #define TIM_DIER_CC1IE_Msk (0x1U << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */ 5484 #define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */ 5485 #define TIM_DIER_CC2IE_Pos (2U) 5486 #define TIM_DIER_CC2IE_Msk (0x1U << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */ 5487 #define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */ 5488 #define TIM_DIER_CC3IE_Pos (3U) 5489 #define TIM_DIER_CC3IE_Msk (0x1U << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */ 5490 #define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */ 5491 #define TIM_DIER_CC4IE_Pos (4U) 5492 #define TIM_DIER_CC4IE_Msk (0x1U << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */ 5493 #define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */ 5494 #define TIM_DIER_TIE_Pos (6U) 5495 #define TIM_DIER_TIE_Msk (0x1U << TIM_DIER_TIE_Pos) /*!< 0x00000040 */ 5496 #define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */ 5497 #define TIM_DIER_UDE_Pos (8U) 5498 #define TIM_DIER_UDE_Msk (0x1U << TIM_DIER_UDE_Pos) /*!< 0x00000100 */ 5499 #define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */ 5500 #define TIM_DIER_CC1DE_Pos (9U) 5501 #define TIM_DIER_CC1DE_Msk (0x1U << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */ 5502 #define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */ 5503 #define TIM_DIER_CC2DE_Pos (10U) 5504 #define TIM_DIER_CC2DE_Msk (0x1U << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */ 5505 #define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */ 5506 #define TIM_DIER_CC3DE_Pos (11U) 5507 #define TIM_DIER_CC3DE_Msk (0x1U << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */ 5508 #define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */ 5509 #define TIM_DIER_CC4DE_Pos (12U) 5510 #define TIM_DIER_CC4DE_Msk (0x1U << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */ 5511 #define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */ 5512 #define TIM_DIER_TDE_Pos (14U) 5513 #define TIM_DIER_TDE_Msk (0x1U << TIM_DIER_TDE_Pos) /*!< 0x00004000 */ 5514 #define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */ 5515 5516 /******************** Bit definition for TIM_SR register ********************/ 5517 #define TIM_SR_UIF_Pos (0U) 5518 #define TIM_SR_UIF_Msk (0x1U << TIM_SR_UIF_Pos) /*!< 0x00000001 */ 5519 #define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */ 5520 #define TIM_SR_CC1IF_Pos (1U) 5521 #define TIM_SR_CC1IF_Msk (0x1U << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */ 5522 #define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */ 5523 #define TIM_SR_CC2IF_Pos (2U) 5524 #define TIM_SR_CC2IF_Msk (0x1U << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */ 5525 #define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */ 5526 #define TIM_SR_CC3IF_Pos (3U) 5527 #define TIM_SR_CC3IF_Msk (0x1U << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */ 5528 #define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */ 5529 #define TIM_SR_CC4IF_Pos (4U) 5530 #define TIM_SR_CC4IF_Msk (0x1U << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */ 5531 #define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */ 5532 #define TIM_SR_TIF_Pos (6U) 5533 #define TIM_SR_TIF_Msk (0x1U << TIM_SR_TIF_Pos) /*!< 0x00000040 */ 5534 #define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */ 5535 #define TIM_SR_CC1OF_Pos (9U) 5536 #define TIM_SR_CC1OF_Msk (0x1U << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */ 5537 #define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */ 5538 #define TIM_SR_CC2OF_Pos (10U) 5539 #define TIM_SR_CC2OF_Msk (0x1U << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */ 5540 #define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */ 5541 #define TIM_SR_CC3OF_Pos (11U) 5542 #define TIM_SR_CC3OF_Msk (0x1U << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */ 5543 #define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */ 5544 #define TIM_SR_CC4OF_Pos (12U) 5545 #define TIM_SR_CC4OF_Msk (0x1U << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */ 5546 #define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */ 5547 5548 /******************* Bit definition for TIM_EGR register ********************/ 5549 #define TIM_EGR_UG_Pos (0U) 5550 #define TIM_EGR_UG_Msk (0x1U << TIM_EGR_UG_Pos) /*!< 0x00000001 */ 5551 #define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */ 5552 #define TIM_EGR_CC1G_Pos (1U) 5553 #define TIM_EGR_CC1G_Msk (0x1U << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */ 5554 #define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */ 5555 #define TIM_EGR_CC2G_Pos (2U) 5556 #define TIM_EGR_CC2G_Msk (0x1U << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */ 5557 #define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */ 5558 #define TIM_EGR_CC3G_Pos (3U) 5559 #define TIM_EGR_CC3G_Msk (0x1U << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */ 5560 #define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */ 5561 #define TIM_EGR_CC4G_Pos (4U) 5562 #define TIM_EGR_CC4G_Msk (0x1U << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */ 5563 #define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */ 5564 #define TIM_EGR_TG_Pos (6U) 5565 #define TIM_EGR_TG_Msk (0x1U << TIM_EGR_TG_Pos) /*!< 0x00000040 */ 5566 #define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */ 5567 5568 /****************** Bit definition for TIM_CCMR1 register *******************/ 5569 #define TIM_CCMR1_CC1S_Pos (0U) 5570 #define TIM_CCMR1_CC1S_Msk (0x3U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */ 5571 #define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */ 5572 #define TIM_CCMR1_CC1S_0 (0x1U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000001 */ 5573 #define TIM_CCMR1_CC1S_1 (0x2U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000002 */ 5574 5575 #define TIM_CCMR1_OC1FE_Pos (2U) 5576 #define TIM_CCMR1_OC1FE_Msk (0x1U << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */ 5577 #define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */ 5578 #define TIM_CCMR1_OC1PE_Pos (3U) 5579 #define TIM_CCMR1_OC1PE_Msk (0x1U << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */ 5580 #define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */ 5581 5582 #define TIM_CCMR1_OC1M_Pos (4U) 5583 #define TIM_CCMR1_OC1M_Msk (0x7U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000070 */ 5584 #define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */ 5585 #define TIM_CCMR1_OC1M_0 (0x1U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000010 */ 5586 #define TIM_CCMR1_OC1M_1 (0x2U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000020 */ 5587 #define TIM_CCMR1_OC1M_2 (0x4U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000040 */ 5588 5589 #define TIM_CCMR1_OC1CE_Pos (7U) 5590 #define TIM_CCMR1_OC1CE_Msk (0x1U << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */ 5591 #define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */ 5592 5593 #define TIM_CCMR1_CC2S_Pos (8U) 5594 #define TIM_CCMR1_CC2S_Msk (0x3U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */ 5595 #define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */ 5596 #define TIM_CCMR1_CC2S_0 (0x1U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000100 */ 5597 #define TIM_CCMR1_CC2S_1 (0x2U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000200 */ 5598 5599 #define TIM_CCMR1_OC2FE_Pos (10U) 5600 #define TIM_CCMR1_OC2FE_Msk (0x1U << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */ 5601 #define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */ 5602 #define TIM_CCMR1_OC2PE_Pos (11U) 5603 #define TIM_CCMR1_OC2PE_Msk (0x1U << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */ 5604 #define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */ 5605 5606 #define TIM_CCMR1_OC2M_Pos (12U) 5607 #define TIM_CCMR1_OC2M_Msk (0x7U << TIM_CCMR1_OC2M_Pos) /*!< 0x00007000 */ 5608 #define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */ 5609 #define TIM_CCMR1_OC2M_0 (0x1U << TIM_CCMR1_OC2M_Pos) /*!< 0x00001000 */ 5610 #define TIM_CCMR1_OC2M_1 (0x2U << TIM_CCMR1_OC2M_Pos) /*!< 0x00002000 */ 5611 #define TIM_CCMR1_OC2M_2 (0x4U << TIM_CCMR1_OC2M_Pos) /*!< 0x00004000 */ 5612 5613 #define TIM_CCMR1_OC2CE_Pos (15U) 5614 #define TIM_CCMR1_OC2CE_Msk (0x1U << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */ 5615 #define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */ 5616 5617 /*----------------------------------------------------------------------------*/ 5618 5619 #define TIM_CCMR1_IC1PSC_Pos (2U) 5620 #define TIM_CCMR1_IC1PSC_Msk (0x3U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */ 5621 #define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */ 5622 #define TIM_CCMR1_IC1PSC_0 (0x1U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000004 */ 5623 #define TIM_CCMR1_IC1PSC_1 (0x2U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000008 */ 5624 5625 #define TIM_CCMR1_IC1F_Pos (4U) 5626 #define TIM_CCMR1_IC1F_Msk (0xFU << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */ 5627 #define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */ 5628 #define TIM_CCMR1_IC1F_0 (0x1U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000010 */ 5629 #define TIM_CCMR1_IC1F_1 (0x2U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000020 */ 5630 #define TIM_CCMR1_IC1F_2 (0x4U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000040 */ 5631 #define TIM_CCMR1_IC1F_3 (0x8U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000080 */ 5632 5633 #define TIM_CCMR1_IC2PSC_Pos (10U) 5634 #define TIM_CCMR1_IC2PSC_Msk (0x3U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */ 5635 #define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */ 5636 #define TIM_CCMR1_IC2PSC_0 (0x1U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000400 */ 5637 #define TIM_CCMR1_IC2PSC_1 (0x2U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000800 */ 5638 5639 #define TIM_CCMR1_IC2F_Pos (12U) 5640 #define TIM_CCMR1_IC2F_Msk (0xFU << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */ 5641 #define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */ 5642 #define TIM_CCMR1_IC2F_0 (0x1U << TIM_CCMR1_IC2F_Pos) /*!< 0x00001000 */ 5643 #define TIM_CCMR1_IC2F_1 (0x2U << TIM_CCMR1_IC2F_Pos) /*!< 0x00002000 */ 5644 #define TIM_CCMR1_IC2F_2 (0x4U << TIM_CCMR1_IC2F_Pos) /*!< 0x00004000 */ 5645 #define TIM_CCMR1_IC2F_3 (0x8U << TIM_CCMR1_IC2F_Pos) /*!< 0x00008000 */ 5646 5647 /****************** Bit definition for TIM_CCMR2 register *******************/ 5648 #define TIM_CCMR2_CC3S_Pos (0U) 5649 #define TIM_CCMR2_CC3S_Msk (0x3U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */ 5650 #define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */ 5651 #define TIM_CCMR2_CC3S_0 (0x1U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000001 */ 5652 #define TIM_CCMR2_CC3S_1 (0x2U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000002 */ 5653 5654 #define TIM_CCMR2_OC3FE_Pos (2U) 5655 #define TIM_CCMR2_OC3FE_Msk (0x1U << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */ 5656 #define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */ 5657 #define TIM_CCMR2_OC3PE_Pos (3U) 5658 #define TIM_CCMR2_OC3PE_Msk (0x1U << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */ 5659 #define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */ 5660 5661 #define TIM_CCMR2_OC3M_Pos (4U) 5662 #define TIM_CCMR2_OC3M_Msk (0x7U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */ 5663 #define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */ 5664 #define TIM_CCMR2_OC3M_0 (0x1U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */ 5665 #define TIM_CCMR2_OC3M_1 (0x2U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */ 5666 #define TIM_CCMR2_OC3M_2 (0x4U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */ 5667 5668 #define TIM_CCMR2_OC3CE_Pos (7U) 5669 #define TIM_CCMR2_OC3CE_Msk (0x1U << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */ 5670 #define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */ 5671 5672 #define TIM_CCMR2_CC4S_Pos (8U) 5673 #define TIM_CCMR2_CC4S_Msk (0x3U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */ 5674 #define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */ 5675 #define TIM_CCMR2_CC4S_0 (0x1U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000100 */ 5676 #define TIM_CCMR2_CC4S_1 (0x2U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000200 */ 5677 5678 #define TIM_CCMR2_OC4FE_Pos (10U) 5679 #define TIM_CCMR2_OC4FE_Msk (0x1U << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */ 5680 #define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */ 5681 #define TIM_CCMR2_OC4PE_Pos (11U) 5682 #define TIM_CCMR2_OC4PE_Msk (0x1U << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */ 5683 #define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */ 5684 5685 #define TIM_CCMR2_OC4M_Pos (12U) 5686 #define TIM_CCMR2_OC4M_Msk (0x7U << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */ 5687 #define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */ 5688 #define TIM_CCMR2_OC4M_0 (0x1U << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */ 5689 #define TIM_CCMR2_OC4M_1 (0x2U << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */ 5690 #define TIM_CCMR2_OC4M_2 (0x4U << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */ 5691 5692 #define TIM_CCMR2_OC4CE_Pos (15U) 5693 #define TIM_CCMR2_OC4CE_Msk (0x1U << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */ 5694 #define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */ 5695 5696 /*----------------------------------------------------------------------------*/ 5697 5698 #define TIM_CCMR2_IC3PSC_Pos (2U) 5699 #define TIM_CCMR2_IC3PSC_Msk (0x3U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */ 5700 #define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */ 5701 #define TIM_CCMR2_IC3PSC_0 (0x1U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000004 */ 5702 #define TIM_CCMR2_IC3PSC_1 (0x2U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000008 */ 5703 5704 #define TIM_CCMR2_IC3F_Pos (4U) 5705 #define TIM_CCMR2_IC3F_Msk (0xFU << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */ 5706 #define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */ 5707 #define TIM_CCMR2_IC3F_0 (0x1U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000010 */ 5708 #define TIM_CCMR2_IC3F_1 (0x2U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000020 */ 5709 #define TIM_CCMR2_IC3F_2 (0x4U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000040 */ 5710 #define TIM_CCMR2_IC3F_3 (0x8U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000080 */ 5711 5712 #define TIM_CCMR2_IC4PSC_Pos (10U) 5713 #define TIM_CCMR2_IC4PSC_Msk (0x3U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */ 5714 #define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */ 5715 #define TIM_CCMR2_IC4PSC_0 (0x1U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000400 */ 5716 #define TIM_CCMR2_IC4PSC_1 (0x2U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000800 */ 5717 5718 #define TIM_CCMR2_IC4F_Pos (12U) 5719 #define TIM_CCMR2_IC4F_Msk (0xFU << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */ 5720 #define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */ 5721 #define TIM_CCMR2_IC4F_0 (0x1U << TIM_CCMR2_IC4F_Pos) /*!< 0x00001000 */ 5722 #define TIM_CCMR2_IC4F_1 (0x2U << TIM_CCMR2_IC4F_Pos) /*!< 0x00002000 */ 5723 #define TIM_CCMR2_IC4F_2 (0x4U << TIM_CCMR2_IC4F_Pos) /*!< 0x00004000 */ 5724 #define TIM_CCMR2_IC4F_3 (0x8U << TIM_CCMR2_IC4F_Pos) /*!< 0x00008000 */ 5725 5726 /******************* Bit definition for TIM_CCER register *******************/ 5727 #define TIM_CCER_CC1E_Pos (0U) 5728 #define TIM_CCER_CC1E_Msk (0x1U << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */ 5729 #define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */ 5730 #define TIM_CCER_CC1P_Pos (1U) 5731 #define TIM_CCER_CC1P_Msk (0x1U << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */ 5732 #define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */ 5733 #define TIM_CCER_CC1NP_Pos (3U) 5734 #define TIM_CCER_CC1NP_Msk (0x1U << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */ 5735 #define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */ 5736 #define TIM_CCER_CC2E_Pos (4U) 5737 #define TIM_CCER_CC2E_Msk (0x1U << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */ 5738 #define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */ 5739 #define TIM_CCER_CC2P_Pos (5U) 5740 #define TIM_CCER_CC2P_Msk (0x1U << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */ 5741 #define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */ 5742 #define TIM_CCER_CC2NP_Pos (7U) 5743 #define TIM_CCER_CC2NP_Msk (0x1U << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */ 5744 #define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */ 5745 #define TIM_CCER_CC3E_Pos (8U) 5746 #define TIM_CCER_CC3E_Msk (0x1U << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */ 5747 #define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */ 5748 #define TIM_CCER_CC3P_Pos (9U) 5749 #define TIM_CCER_CC3P_Msk (0x1U << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */ 5750 #define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */ 5751 #define TIM_CCER_CC3NP_Pos (11U) 5752 #define TIM_CCER_CC3NP_Msk (0x1U << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */ 5753 #define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */ 5754 #define TIM_CCER_CC4E_Pos (12U) 5755 #define TIM_CCER_CC4E_Msk (0x1U << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */ 5756 #define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */ 5757 #define TIM_CCER_CC4P_Pos (13U) 5758 #define TIM_CCER_CC4P_Msk (0x1U << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */ 5759 #define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */ 5760 #define TIM_CCER_CC4NP_Pos (15U) 5761 #define TIM_CCER_CC4NP_Msk (0x1U << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */ 5762 #define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */ 5763 5764 /******************* Bit definition for TIM_CNT register ********************/ 5765 #define TIM_CNT_CNT_Pos (0U) 5766 #define TIM_CNT_CNT_Msk (0xFFFFU << TIM_CNT_CNT_Pos) /*!< 0x0000FFFF */ 5767 #define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */ 5768 5769 /******************* Bit definition for TIM_PSC register ********************/ 5770 #define TIM_PSC_PSC_Pos (0U) 5771 #define TIM_PSC_PSC_Msk (0xFFFFU << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */ 5772 #define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */ 5773 5774 /******************* Bit definition for TIM_ARR register ********************/ 5775 #define TIM_ARR_ARR_Pos (0U) 5776 #define TIM_ARR_ARR_Msk (0xFFFFU << TIM_ARR_ARR_Pos) /*!< 0x0000FFFF */ 5777 #define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */ 5778 5779 /******************* Bit definition for TIM_CCR1 register *******************/ 5780 #define TIM_CCR1_CCR1_Pos (0U) 5781 #define TIM_CCR1_CCR1_Msk (0xFFFFU << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */ 5782 #define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */ 5783 5784 /******************* Bit definition for TIM_CCR2 register *******************/ 5785 #define TIM_CCR2_CCR2_Pos (0U) 5786 #define TIM_CCR2_CCR2_Msk (0xFFFFU << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */ 5787 #define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */ 5788 5789 /******************* Bit definition for TIM_CCR3 register *******************/ 5790 #define TIM_CCR3_CCR3_Pos (0U) 5791 #define TIM_CCR3_CCR3_Msk (0xFFFFU << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */ 5792 #define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */ 5793 5794 /******************* Bit definition for TIM_CCR4 register *******************/ 5795 #define TIM_CCR4_CCR4_Pos (0U) 5796 #define TIM_CCR4_CCR4_Msk (0xFFFFU << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */ 5797 #define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */ 5798 5799 /******************* Bit definition for TIM_DCR register ********************/ 5800 #define TIM_DCR_DBA_Pos (0U) 5801 #define TIM_DCR_DBA_Msk (0x1FU << TIM_DCR_DBA_Pos) /*!< 0x0000001F */ 5802 #define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */ 5803 #define TIM_DCR_DBA_0 (0x01U << TIM_DCR_DBA_Pos) /*!< 0x00000001 */ 5804 #define TIM_DCR_DBA_1 (0x02U << TIM_DCR_DBA_Pos) /*!< 0x00000002 */ 5805 #define TIM_DCR_DBA_2 (0x04U << TIM_DCR_DBA_Pos) /*!< 0x00000004 */ 5806 #define TIM_DCR_DBA_3 (0x08U << TIM_DCR_DBA_Pos) /*!< 0x00000008 */ 5807 #define TIM_DCR_DBA_4 (0x10U << TIM_DCR_DBA_Pos) /*!< 0x00000010 */ 5808 5809 #define TIM_DCR_DBL_Pos (8U) 5810 #define TIM_DCR_DBL_Msk (0x1FU << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */ 5811 #define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */ 5812 #define TIM_DCR_DBL_0 (0x01U << TIM_DCR_DBL_Pos) /*!< 0x00000100 */ 5813 #define TIM_DCR_DBL_1 (0x02U << TIM_DCR_DBL_Pos) /*!< 0x00000200 */ 5814 #define TIM_DCR_DBL_2 (0x04U << TIM_DCR_DBL_Pos) /*!< 0x00000400 */ 5815 #define TIM_DCR_DBL_3 (0x08U << TIM_DCR_DBL_Pos) /*!< 0x00000800 */ 5816 #define TIM_DCR_DBL_4 (0x10U << TIM_DCR_DBL_Pos) /*!< 0x00001000 */ 5817 5818 /******************* Bit definition for TIM_DMAR register *******************/ 5819 #define TIM_DMAR_DMAB_Pos (0U) 5820 #define TIM_DMAR_DMAB_Msk (0xFFFFU << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */ 5821 #define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */ 5822 5823 /******************* Bit definition for TIM_OR register *********************/ 5824 #define TIM2_OR_ETR_RMP_Pos (0U) 5825 #define TIM2_OR_ETR_RMP_Msk (0x7U << TIM2_OR_ETR_RMP_Pos) /*!< 0x00000007 */ 5826 #define TIM2_OR_ETR_RMP TIM2_OR_ETR_RMP_Msk /*!<ETR_RMP[1:0] bits (TIM2 ETR remap) */ 5827 #define TIM2_OR_ETR_RMP_0 (0x1U << TIM2_OR_ETR_RMP_Pos) /*!< 0x00000001 */ 5828 #define TIM2_OR_ETR_RMP_1 (0x2U << TIM2_OR_ETR_RMP_Pos) /*!< 0x00000002 */ 5829 #define TIM2_OR_ETR_RMP_2 (0x4U << TIM2_OR_ETR_RMP_Pos) /*!< 0x00000004 */ 5830 #define TIM2_OR_TI4_RMP_Pos (3U) 5831 #define TIM2_OR_TI4_RMP_Msk (0x3U << TIM2_OR_TI4_RMP_Pos) /*!< 0x00000018 */ 5832 #define TIM2_OR_TI4_RMP TIM2_OR_TI4_RMP_Msk /*!<TI4_RMP[1:0] bits (TIM2 Input 4 remap) */ 5833 #define TIM2_OR_TI4_RMP_0 (0x1U << TIM2_OR_TI4_RMP_Pos) /*!< 0x00000008 */ 5834 #define TIM2_OR_TI4_RMP_1 (0x2U << TIM2_OR_TI4_RMP_Pos) /*!< 0x00000010 */ 5835 5836 #define TIM21_OR_ETR_RMP_Pos (0U) 5837 #define TIM21_OR_ETR_RMP_Msk (0x3U << TIM21_OR_ETR_RMP_Pos) /*!< 0x00000003 */ 5838 #define TIM21_OR_ETR_RMP TIM21_OR_ETR_RMP_Msk /*!<ETR_RMP[1:0] bits (TIM21 ETR remap) */ 5839 #define TIM21_OR_ETR_RMP_0 (0x1U << TIM21_OR_ETR_RMP_Pos) /*!< 0x00000001 */ 5840 #define TIM21_OR_ETR_RMP_1 (0x2U << TIM21_OR_ETR_RMP_Pos) /*!< 0x00000002 */ 5841 #define TIM21_OR_TI1_RMP_Pos (2U) 5842 #define TIM21_OR_TI1_RMP_Msk (0x7U << TIM21_OR_TI1_RMP_Pos) /*!< 0x0000001C */ 5843 #define TIM21_OR_TI1_RMP TIM21_OR_TI1_RMP_Msk /*!<TI1_RMP[2:0] bits (TIM21 Input 1 remap) */ 5844 #define TIM21_OR_TI1_RMP_0 (0x1U << TIM21_OR_TI1_RMP_Pos) /*!< 0x00000004 */ 5845 #define TIM21_OR_TI1_RMP_1 (0x2U << TIM21_OR_TI1_RMP_Pos) /*!< 0x00000008 */ 5846 #define TIM21_OR_TI1_RMP_2 (0x4U << TIM21_OR_TI1_RMP_Pos) /*!< 0x00000010 */ 5847 #define TIM21_OR_TI2_RMP_Pos (5U) 5848 #define TIM21_OR_TI2_RMP_Msk (0x1U << TIM21_OR_TI2_RMP_Pos) /*!< 0x00000020 */ 5849 #define TIM21_OR_TI2_RMP TIM21_OR_TI2_RMP_Msk /*!<TI2_RMP bit (TIM21 Input 2 remap) */ 5850 5851 #define TIM22_OR_ETR_RMP_Pos (0U) 5852 #define TIM22_OR_ETR_RMP_Msk (0x3U << TIM22_OR_ETR_RMP_Pos) /*!< 0x00000003 */ 5853 #define TIM22_OR_ETR_RMP TIM22_OR_ETR_RMP_Msk /*!<ETR_RMP[1:0] bits (TIM22 ETR remap) */ 5854 #define TIM22_OR_ETR_RMP_0 (0x1U << TIM22_OR_ETR_RMP_Pos) /*!< 0x00000001 */ 5855 #define TIM22_OR_ETR_RMP_1 (0x2U << TIM22_OR_ETR_RMP_Pos) /*!< 0x00000002 */ 5856 #define TIM22_OR_TI1_RMP_Pos (2U) 5857 #define TIM22_OR_TI1_RMP_Msk (0x3U << TIM22_OR_TI1_RMP_Pos) /*!< 0x0000000C */ 5858 #define TIM22_OR_TI1_RMP TIM22_OR_TI1_RMP_Msk /*!<TI1_RMP[2:0] bits (TIM22 Input 1 remap) */ 5859 #define TIM22_OR_TI1_RMP_0 (0x1U << TIM22_OR_TI1_RMP_Pos) /*!< 0x00000004 */ 5860 #define TIM22_OR_TI1_RMP_1 (0x2U << TIM22_OR_TI1_RMP_Pos) /*!< 0x00000008 */ 5861 5862 #define TIM3_OR_ETR_RMP_Pos (0U) 5863 #define TIM3_OR_ETR_RMP_Msk (0x3U << TIM3_OR_ETR_RMP_Pos) /*!< 0x00000003 */ 5864 #define TIM3_OR_ETR_RMP TIM3_OR_ETR_RMP_Msk /*!<ETR_RMP[1:0] bits (TIM3 ETR remap) */ 5865 #define TIM3_OR_ETR_RMP_0 (0x1U << TIM3_OR_ETR_RMP_Pos) /*!< 0x00000001 */ 5866 #define TIM3_OR_ETR_RMP_1 (0x2U << TIM3_OR_ETR_RMP_Pos) /*!< 0x00000002 */ 5867 #define TIM3_OR_TI1_RMP_Pos (2U) 5868 #define TIM3_OR_TI1_RMP_Msk (0x1U << TIM3_OR_TI1_RMP_Pos) /*!< 0x00000004 */ 5869 #define TIM3_OR_TI1_RMP TIM3_OR_TI1_RMP_Msk /*!<TI1_RMP[2] bit */ 5870 #define TIM3_OR_TI2_RMP_Pos (3U) 5871 #define TIM3_OR_TI2_RMP_Msk (0x1U << TIM3_OR_TI2_RMP_Pos) /*!< 0x00000008 */ 5872 #define TIM3_OR_TI2_RMP TIM3_OR_TI2_RMP_Msk /*!<TI2_RMP[3] bit */ 5873 #define TIM3_OR_TI4_RMP_Pos (4U) 5874 #define TIM3_OR_TI4_RMP_Msk (0x1U << TIM3_OR_TI4_RMP_Pos) /*!< 0x00000010 */ 5875 #define TIM3_OR_TI4_RMP TIM3_OR_TI4_RMP_Msk /*!<TI4_RMP[4] bit */ 5876 5877 5878 /******************************************************************************/ 5879 /* */ 5880 /* Universal Synchronous Asynchronous Receiver Transmitter (USART) */ 5881 /* */ 5882 /******************************************************************************/ 5883 5884 /* 5885 * @brief Specific device feature definitions (not present on all devices in the STM32L0 family) 5886 */ 5887 /* Note: No specific macro feature on this device */ 5888 5889 /****************** Bit definition for USART_CR1 register *******************/ 5890 #define USART_CR1_UE_Pos (0U) 5891 #define USART_CR1_UE_Msk (0x1U << USART_CR1_UE_Pos) /*!< 0x00000001 */ 5892 #define USART_CR1_UE USART_CR1_UE_Msk /*!< USART Enable */ 5893 #define USART_CR1_UESM_Pos (1U) 5894 #define USART_CR1_UESM_Msk (0x1U << USART_CR1_UESM_Pos) /*!< 0x00000002 */ 5895 #define USART_CR1_UESM USART_CR1_UESM_Msk /*!< USART Enable in STOP Mode */ 5896 #define USART_CR1_RE_Pos (2U) 5897 #define USART_CR1_RE_Msk (0x1U << USART_CR1_RE_Pos) /*!< 0x00000004 */ 5898 #define USART_CR1_RE USART_CR1_RE_Msk /*!< Receiver Enable */ 5899 #define USART_CR1_TE_Pos (3U) 5900 #define USART_CR1_TE_Msk (0x1U << USART_CR1_TE_Pos) /*!< 0x00000008 */ 5901 #define USART_CR1_TE USART_CR1_TE_Msk /*!< Transmitter Enable */ 5902 #define USART_CR1_IDLEIE_Pos (4U) 5903 #define USART_CR1_IDLEIE_Msk (0x1U << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */ 5904 #define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!< IDLE Interrupt Enable */ 5905 #define USART_CR1_RXNEIE_Pos (5U) 5906 #define USART_CR1_RXNEIE_Msk (0x1U << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */ 5907 #define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!< RXNE Interrupt Enable */ 5908 #define USART_CR1_TCIE_Pos (6U) 5909 #define USART_CR1_TCIE_Msk (0x1U << USART_CR1_TCIE_Pos) /*!< 0x00000040 */ 5910 #define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!< Transmission Complete Interrupt Enable */ 5911 #define USART_CR1_TXEIE_Pos (7U) 5912 #define USART_CR1_TXEIE_Msk (0x1U << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */ 5913 #define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!< TXE Interrupt Enable */ 5914 #define USART_CR1_PEIE_Pos (8U) 5915 #define USART_CR1_PEIE_Msk (0x1U << USART_CR1_PEIE_Pos) /*!< 0x00000100 */ 5916 #define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!< PE Interrupt Enable */ 5917 #define USART_CR1_PS_Pos (9U) 5918 #define USART_CR1_PS_Msk (0x1U << USART_CR1_PS_Pos) /*!< 0x00000200 */ 5919 #define USART_CR1_PS USART_CR1_PS_Msk /*!< Parity Selection */ 5920 #define USART_CR1_PCE_Pos (10U) 5921 #define USART_CR1_PCE_Msk (0x1U << USART_CR1_PCE_Pos) /*!< 0x00000400 */ 5922 #define USART_CR1_PCE USART_CR1_PCE_Msk /*!< Parity Control Enable */ 5923 #define USART_CR1_WAKE_Pos (11U) 5924 #define USART_CR1_WAKE_Msk (0x1U << USART_CR1_WAKE_Pos) /*!< 0x00000800 */ 5925 #define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!< Receiver Wakeup method */ 5926 #define USART_CR1_M_Pos (12U) 5927 #define USART_CR1_M_Msk (0x10001U << USART_CR1_M_Pos) /*!< 0x10001000 */ 5928 #define USART_CR1_M USART_CR1_M_Msk /*!< Word length */ 5929 #define USART_CR1_M0_Pos (12U) 5930 #define USART_CR1_M0_Msk (0x1U << USART_CR1_M0_Pos) /*!< 0x00001000 */ 5931 #define USART_CR1_M0 USART_CR1_M0_Msk /*!< Word length - Bit 0 */ 5932 #define USART_CR1_MME_Pos (13U) 5933 #define USART_CR1_MME_Msk (0x1U << USART_CR1_MME_Pos) /*!< 0x00002000 */ 5934 #define USART_CR1_MME USART_CR1_MME_Msk /*!< Mute Mode Enable */ 5935 #define USART_CR1_CMIE_Pos (14U) 5936 #define USART_CR1_CMIE_Msk (0x1U << USART_CR1_CMIE_Pos) /*!< 0x00004000 */ 5937 #define USART_CR1_CMIE USART_CR1_CMIE_Msk /*!< Character match interrupt enable */ 5938 #define USART_CR1_OVER8_Pos (15U) 5939 #define USART_CR1_OVER8_Msk (0x1U << USART_CR1_OVER8_Pos) /*!< 0x00008000 */ 5940 #define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!< Oversampling by 8-bit or 16-bit mode */ 5941 #define USART_CR1_DEDT_Pos (16U) 5942 #define USART_CR1_DEDT_Msk (0x1FU << USART_CR1_DEDT_Pos) /*!< 0x001F0000 */ 5943 #define USART_CR1_DEDT USART_CR1_DEDT_Msk /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */ 5944 #define USART_CR1_DEDT_0 (0x01U << USART_CR1_DEDT_Pos) /*!< 0x00010000 */ 5945 #define USART_CR1_DEDT_1 (0x02U << USART_CR1_DEDT_Pos) /*!< 0x00020000 */ 5946 #define USART_CR1_DEDT_2 (0x04U << USART_CR1_DEDT_Pos) /*!< 0x00040000 */ 5947 #define USART_CR1_DEDT_3 (0x08U << USART_CR1_DEDT_Pos) /*!< 0x00080000 */ 5948 #define USART_CR1_DEDT_4 (0x10U << USART_CR1_DEDT_Pos) /*!< 0x00100000 */ 5949 #define USART_CR1_DEAT_Pos (21U) 5950 #define USART_CR1_DEAT_Msk (0x1FU << USART_CR1_DEAT_Pos) /*!< 0x03E00000 */ 5951 #define USART_CR1_DEAT USART_CR1_DEAT_Msk /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */ 5952 #define USART_CR1_DEAT_0 (0x01U << USART_CR1_DEAT_Pos) /*!< 0x00200000 */ 5953 #define USART_CR1_DEAT_1 (0x02U << USART_CR1_DEAT_Pos) /*!< 0x00400000 */ 5954 #define USART_CR1_DEAT_2 (0x04U << USART_CR1_DEAT_Pos) /*!< 0x00800000 */ 5955 #define USART_CR1_DEAT_3 (0x08U << USART_CR1_DEAT_Pos) /*!< 0x01000000 */ 5956 #define USART_CR1_DEAT_4 (0x10U << USART_CR1_DEAT_Pos) /*!< 0x02000000 */ 5957 #define USART_CR1_RTOIE_Pos (26U) 5958 #define USART_CR1_RTOIE_Msk (0x1U << USART_CR1_RTOIE_Pos) /*!< 0x04000000 */ 5959 #define USART_CR1_RTOIE USART_CR1_RTOIE_Msk /*!< Receive Time Out interrupt enable */ 5960 #define USART_CR1_EOBIE_Pos (27U) 5961 #define USART_CR1_EOBIE_Msk (0x1U << USART_CR1_EOBIE_Pos) /*!< 0x08000000 */ 5962 #define USART_CR1_EOBIE USART_CR1_EOBIE_Msk /*!< End of Block interrupt enable */ 5963 #define USART_CR1_M1_Pos (28U) 5964 #define USART_CR1_M1_Msk (0x1U << USART_CR1_M1_Pos) /*!< 0x10000000 */ 5965 #define USART_CR1_M1 USART_CR1_M1_Msk /*!< Word length - Bit 1 */ 5966 /****************** Bit definition for USART_CR2 register *******************/ 5967 #define USART_CR2_ADDM7_Pos (4U) 5968 #define USART_CR2_ADDM7_Msk (0x1U << USART_CR2_ADDM7_Pos) /*!< 0x00000010 */ 5969 #define USART_CR2_ADDM7 USART_CR2_ADDM7_Msk /*!< 7-bit or 4-bit Address Detection */ 5970 #define USART_CR2_LBDL_Pos (5U) 5971 #define USART_CR2_LBDL_Msk (0x1U << USART_CR2_LBDL_Pos) /*!< 0x00000020 */ 5972 #define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!< LIN Break Detection Length */ 5973 #define USART_CR2_LBDIE_Pos (6U) 5974 #define USART_CR2_LBDIE_Msk (0x1U << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */ 5975 #define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!< LIN Break Detection Interrupt Enable */ 5976 #define USART_CR2_LBCL_Pos (8U) 5977 #define USART_CR2_LBCL_Msk (0x1U << USART_CR2_LBCL_Pos) /*!< 0x00000100 */ 5978 #define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!< Last Bit Clock pulse */ 5979 #define USART_CR2_CPHA_Pos (9U) 5980 #define USART_CR2_CPHA_Msk (0x1U << USART_CR2_CPHA_Pos) /*!< 0x00000200 */ 5981 #define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!< Clock Phase */ 5982 #define USART_CR2_CPOL_Pos (10U) 5983 #define USART_CR2_CPOL_Msk (0x1U << USART_CR2_CPOL_Pos) /*!< 0x00000400 */ 5984 #define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!< Clock Polarity */ 5985 #define USART_CR2_CLKEN_Pos (11U) 5986 #define USART_CR2_CLKEN_Msk (0x1U << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */ 5987 #define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!< Clock Enable */ 5988 #define USART_CR2_STOP_Pos (12U) 5989 #define USART_CR2_STOP_Msk (0x3U << USART_CR2_STOP_Pos) /*!< 0x00003000 */ 5990 #define USART_CR2_STOP USART_CR2_STOP_Msk /*!< STOP[1:0] bits (STOP bits) */ 5991 #define USART_CR2_STOP_0 (0x1U << USART_CR2_STOP_Pos) /*!< 0x00001000 */ 5992 #define USART_CR2_STOP_1 (0x2U << USART_CR2_STOP_Pos) /*!< 0x00002000 */ 5993 #define USART_CR2_LINEN_Pos (14U) 5994 #define USART_CR2_LINEN_Msk (0x1U << USART_CR2_LINEN_Pos) /*!< 0x00004000 */ 5995 #define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!< LIN mode enable */ 5996 #define USART_CR2_SWAP_Pos (15U) 5997 #define USART_CR2_SWAP_Msk (0x1U << USART_CR2_SWAP_Pos) /*!< 0x00008000 */ 5998 #define USART_CR2_SWAP USART_CR2_SWAP_Msk /*!< SWAP TX/RX pins */ 5999 #define USART_CR2_RXINV_Pos (16U) 6000 #define USART_CR2_RXINV_Msk (0x1U << USART_CR2_RXINV_Pos) /*!< 0x00010000 */ 6001 #define USART_CR2_RXINV USART_CR2_RXINV_Msk /*!< RX pin active level inversion */ 6002 #define USART_CR2_TXINV_Pos (17U) 6003 #define USART_CR2_TXINV_Msk (0x1U << USART_CR2_TXINV_Pos) /*!< 0x00020000 */ 6004 #define USART_CR2_TXINV USART_CR2_TXINV_Msk /*!< TX pin active level inversion */ 6005 #define USART_CR2_DATAINV_Pos (18U) 6006 #define USART_CR2_DATAINV_Msk (0x1U << USART_CR2_DATAINV_Pos) /*!< 0x00040000 */ 6007 #define USART_CR2_DATAINV USART_CR2_DATAINV_Msk /*!< Binary data inversion */ 6008 #define USART_CR2_MSBFIRST_Pos (19U) 6009 #define USART_CR2_MSBFIRST_Msk (0x1U << USART_CR2_MSBFIRST_Pos) /*!< 0x00080000 */ 6010 #define USART_CR2_MSBFIRST USART_CR2_MSBFIRST_Msk /*!< Most Significant Bit First */ 6011 #define USART_CR2_ABREN_Pos (20U) 6012 #define USART_CR2_ABREN_Msk (0x1U << USART_CR2_ABREN_Pos) /*!< 0x00100000 */ 6013 #define USART_CR2_ABREN USART_CR2_ABREN_Msk /*!< Auto Baud-Rate Enable*/ 6014 #define USART_CR2_ABRMODE_Pos (21U) 6015 #define USART_CR2_ABRMODE_Msk (0x3U << USART_CR2_ABRMODE_Pos) /*!< 0x00600000 */ 6016 #define USART_CR2_ABRMODE USART_CR2_ABRMODE_Msk /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */ 6017 #define USART_CR2_ABRMODE_0 (0x1U << USART_CR2_ABRMODE_Pos) /*!< 0x00200000 */ 6018 #define USART_CR2_ABRMODE_1 (0x2U << USART_CR2_ABRMODE_Pos) /*!< 0x00400000 */ 6019 #define USART_CR2_RTOEN_Pos (23U) 6020 #define USART_CR2_RTOEN_Msk (0x1U << USART_CR2_RTOEN_Pos) /*!< 0x00800000 */ 6021 #define USART_CR2_RTOEN USART_CR2_RTOEN_Msk /*!< Receiver Time-Out enable */ 6022 #define USART_CR2_ADD_Pos (24U) 6023 #define USART_CR2_ADD_Msk (0xFFU << USART_CR2_ADD_Pos) /*!< 0xFF000000 */ 6024 #define USART_CR2_ADD USART_CR2_ADD_Msk /*!< Address of the USART node */ 6025 6026 /****************** Bit definition for USART_CR3 register *******************/ 6027 #define USART_CR3_EIE_Pos (0U) 6028 #define USART_CR3_EIE_Msk (0x1U << USART_CR3_EIE_Pos) /*!< 0x00000001 */ 6029 #define USART_CR3_EIE USART_CR3_EIE_Msk /*!< Error Interrupt Enable */ 6030 #define USART_CR3_IREN_Pos (1U) 6031 #define USART_CR3_IREN_Msk (0x1U << USART_CR3_IREN_Pos) /*!< 0x00000002 */ 6032 #define USART_CR3_IREN USART_CR3_IREN_Msk /*!< IrDA mode Enable */ 6033 #define USART_CR3_IRLP_Pos (2U) 6034 #define USART_CR3_IRLP_Msk (0x1U << USART_CR3_IRLP_Pos) /*!< 0x00000004 */ 6035 #define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-Power */ 6036 #define USART_CR3_HDSEL_Pos (3U) 6037 #define USART_CR3_HDSEL_Msk (0x1U << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */ 6038 #define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Selection */ 6039 #define USART_CR3_NACK_Pos (4U) 6040 #define USART_CR3_NACK_Msk (0x1U << USART_CR3_NACK_Pos) /*!< 0x00000010 */ 6041 #define USART_CR3_NACK USART_CR3_NACK_Msk /*!< SmartCard NACK enable */ 6042 #define USART_CR3_SCEN_Pos (5U) 6043 #define USART_CR3_SCEN_Msk (0x1U << USART_CR3_SCEN_Pos) /*!< 0x00000020 */ 6044 #define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!< SmartCard mode enable */ 6045 #define USART_CR3_DMAR_Pos (6U) 6046 #define USART_CR3_DMAR_Msk (0x1U << USART_CR3_DMAR_Pos) /*!< 0x00000040 */ 6047 #define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!< DMA Enable Receiver */ 6048 #define USART_CR3_DMAT_Pos (7U) 6049 #define USART_CR3_DMAT_Msk (0x1U << USART_CR3_DMAT_Pos) /*!< 0x00000080 */ 6050 #define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!< DMA Enable Transmitter */ 6051 #define USART_CR3_RTSE_Pos (8U) 6052 #define USART_CR3_RTSE_Msk (0x1U << USART_CR3_RTSE_Pos) /*!< 0x00000100 */ 6053 #define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!< RTS Enable */ 6054 #define USART_CR3_CTSE_Pos (9U) 6055 #define USART_CR3_CTSE_Msk (0x1U << USART_CR3_CTSE_Pos) /*!< 0x00000200 */ 6056 #define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!< CTS Enable */ 6057 #define USART_CR3_CTSIE_Pos (10U) 6058 #define USART_CR3_CTSIE_Msk (0x1U << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */ 6059 #define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!< CTS Interrupt Enable */ 6060 #define USART_CR3_ONEBIT_Pos (11U) 6061 #define USART_CR3_ONEBIT_Msk (0x1U << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */ 6062 #define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!< One sample bit method enable */ 6063 #define USART_CR3_OVRDIS_Pos (12U) 6064 #define USART_CR3_OVRDIS_Msk (0x1U << USART_CR3_OVRDIS_Pos) /*!< 0x00001000 */ 6065 #define USART_CR3_OVRDIS USART_CR3_OVRDIS_Msk /*!< Overrun Disable */ 6066 #define USART_CR3_DDRE_Pos (13U) 6067 #define USART_CR3_DDRE_Msk (0x1U << USART_CR3_DDRE_Pos) /*!< 0x00002000 */ 6068 #define USART_CR3_DDRE USART_CR3_DDRE_Msk /*!< DMA Disable on Reception Error */ 6069 #define USART_CR3_DEM_Pos (14U) 6070 #define USART_CR3_DEM_Msk (0x1U << USART_CR3_DEM_Pos) /*!< 0x00004000 */ 6071 #define USART_CR3_DEM USART_CR3_DEM_Msk /*!< Driver Enable Mode */ 6072 #define USART_CR3_DEP_Pos (15U) 6073 #define USART_CR3_DEP_Msk (0x1U << USART_CR3_DEP_Pos) /*!< 0x00008000 */ 6074 #define USART_CR3_DEP USART_CR3_DEP_Msk /*!< Driver Enable Polarity Selection */ 6075 #define USART_CR3_SCARCNT_Pos (17U) 6076 #define USART_CR3_SCARCNT_Msk (0x7U << USART_CR3_SCARCNT_Pos) /*!< 0x000E0000 */ 6077 #define USART_CR3_SCARCNT USART_CR3_SCARCNT_Msk /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */ 6078 #define USART_CR3_SCARCNT_0 (0x1U << USART_CR3_SCARCNT_Pos) /*!< 0x00020000 */ 6079 #define USART_CR3_SCARCNT_1 (0x2U << USART_CR3_SCARCNT_Pos) /*!< 0x00040000 */ 6080 #define USART_CR3_SCARCNT_2 (0x4U << USART_CR3_SCARCNT_Pos) /*!< 0x00080000 */ 6081 #define USART_CR3_WUS_Pos (20U) 6082 #define USART_CR3_WUS_Msk (0x3U << USART_CR3_WUS_Pos) /*!< 0x00300000 */ 6083 #define USART_CR3_WUS USART_CR3_WUS_Msk /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */ 6084 #define USART_CR3_WUS_0 (0x1U << USART_CR3_WUS_Pos) /*!< 0x00100000 */ 6085 #define USART_CR3_WUS_1 (0x2U << USART_CR3_WUS_Pos) /*!< 0x00200000 */ 6086 #define USART_CR3_WUFIE_Pos (22U) 6087 #define USART_CR3_WUFIE_Msk (0x1U << USART_CR3_WUFIE_Pos) /*!< 0x00400000 */ 6088 #define USART_CR3_WUFIE USART_CR3_WUFIE_Msk /*!< Wake Up Interrupt Enable */ 6089 #define USART_CR3_UCESM_Pos (23U) 6090 #define USART_CR3_UCESM_Msk (0x1U << USART_CR3_UCESM_Pos) /*!< 0x00800000 */ 6091 #define USART_CR3_UCESM USART_CR3_UCESM_Msk /*!< Clock Enable in Stop mode */ 6092 6093 /****************** Bit definition for USART_BRR register *******************/ 6094 #define USART_BRR_DIV_FRACTION_Pos (0U) 6095 #define USART_BRR_DIV_FRACTION_Msk (0xFU << USART_BRR_DIV_FRACTION_Pos) /*!< 0x0000000F */ 6096 #define USART_BRR_DIV_FRACTION USART_BRR_DIV_FRACTION_Msk /*!< Fraction of USARTDIV */ 6097 #define USART_BRR_DIV_MANTISSA_Pos (4U) 6098 #define USART_BRR_DIV_MANTISSA_Msk (0xFFFU << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */ 6099 #define USART_BRR_DIV_MANTISSA USART_BRR_DIV_MANTISSA_Msk /*!< Mantissa of USARTDIV */ 6100 6101 /****************** Bit definition for USART_GTPR register ******************/ 6102 #define USART_GTPR_PSC_Pos (0U) 6103 #define USART_GTPR_PSC_Msk (0xFFU << USART_GTPR_PSC_Pos) /*!< 0x000000FF */ 6104 #define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!< PSC[7:0] bits (Prescaler value) */ 6105 #define USART_GTPR_GT_Pos (8U) 6106 #define USART_GTPR_GT_Msk (0xFFU << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */ 6107 #define USART_GTPR_GT USART_GTPR_GT_Msk /*!< GT[7:0] bits (Guard time value) */ 6108 6109 6110 /******************* Bit definition for USART_RTOR register *****************/ 6111 #define USART_RTOR_RTO_Pos (0U) 6112 #define USART_RTOR_RTO_Msk (0xFFFFFFU << USART_RTOR_RTO_Pos) /*!< 0x00FFFFFF */ 6113 #define USART_RTOR_RTO USART_RTOR_RTO_Msk /*!< Receiver Time Out Value */ 6114 #define USART_RTOR_BLEN_Pos (24U) 6115 #define USART_RTOR_BLEN_Msk (0xFFU << USART_RTOR_BLEN_Pos) /*!< 0xFF000000 */ 6116 #define USART_RTOR_BLEN USART_RTOR_BLEN_Msk /*!< Block Length */ 6117 6118 /******************* Bit definition for USART_RQR register ******************/ 6119 #define USART_RQR_ABRRQ_Pos (0U) 6120 #define USART_RQR_ABRRQ_Msk (0x1U << USART_RQR_ABRRQ_Pos) /*!< 0x00000001 */ 6121 #define USART_RQR_ABRRQ USART_RQR_ABRRQ_Msk /*!< Auto-Baud Rate Request */ 6122 #define USART_RQR_SBKRQ_Pos (1U) 6123 #define USART_RQR_SBKRQ_Msk (0x1U << USART_RQR_SBKRQ_Pos) /*!< 0x00000002 */ 6124 #define USART_RQR_SBKRQ USART_RQR_SBKRQ_Msk /*!< Send Break Request */ 6125 #define USART_RQR_MMRQ_Pos (2U) 6126 #define USART_RQR_MMRQ_Msk (0x1U << USART_RQR_MMRQ_Pos) /*!< 0x00000004 */ 6127 #define USART_RQR_MMRQ USART_RQR_MMRQ_Msk /*!< Mute Mode Request */ 6128 #define USART_RQR_RXFRQ_Pos (3U) 6129 #define USART_RQR_RXFRQ_Msk (0x1U << USART_RQR_RXFRQ_Pos) /*!< 0x00000008 */ 6130 #define USART_RQR_RXFRQ USART_RQR_RXFRQ_Msk /*!< Receive Data flush Request */ 6131 #define USART_RQR_TXFRQ_Pos (4U) 6132 #define USART_RQR_TXFRQ_Msk (0x1U << USART_RQR_TXFRQ_Pos) /*!< 0x00000010 */ 6133 #define USART_RQR_TXFRQ USART_RQR_TXFRQ_Msk /*!< Transmit data flush Request */ 6134 6135 /******************* Bit definition for USART_ISR register ******************/ 6136 #define USART_ISR_PE_Pos (0U) 6137 #define USART_ISR_PE_Msk (0x1U << USART_ISR_PE_Pos) /*!< 0x00000001 */ 6138 #define USART_ISR_PE USART_ISR_PE_Msk /*!< Parity Error */ 6139 #define USART_ISR_FE_Pos (1U) 6140 #define USART_ISR_FE_Msk (0x1U << USART_ISR_FE_Pos) /*!< 0x00000002 */ 6141 #define USART_ISR_FE USART_ISR_FE_Msk /*!< Framing Error */ 6142 #define USART_ISR_NE_Pos (2U) 6143 #define USART_ISR_NE_Msk (0x1U << USART_ISR_NE_Pos) /*!< 0x00000004 */ 6144 #define USART_ISR_NE USART_ISR_NE_Msk /*!< Noise detected Flag */ 6145 #define USART_ISR_ORE_Pos (3U) 6146 #define USART_ISR_ORE_Msk (0x1U << USART_ISR_ORE_Pos) /*!< 0x00000008 */ 6147 #define USART_ISR_ORE USART_ISR_ORE_Msk /*!< OverRun Error */ 6148 #define USART_ISR_IDLE_Pos (4U) 6149 #define USART_ISR_IDLE_Msk (0x1U << USART_ISR_IDLE_Pos) /*!< 0x00000010 */ 6150 #define USART_ISR_IDLE USART_ISR_IDLE_Msk /*!< IDLE line detected */ 6151 #define USART_ISR_RXNE_Pos (5U) 6152 #define USART_ISR_RXNE_Msk (0x1U << USART_ISR_RXNE_Pos) /*!< 0x00000020 */ 6153 #define USART_ISR_RXNE USART_ISR_RXNE_Msk /*!< Read Data Register Not Empty */ 6154 #define USART_ISR_TC_Pos (6U) 6155 #define USART_ISR_TC_Msk (0x1U << USART_ISR_TC_Pos) /*!< 0x00000040 */ 6156 #define USART_ISR_TC USART_ISR_TC_Msk /*!< Transmission Complete */ 6157 #define USART_ISR_TXE_Pos (7U) 6158 #define USART_ISR_TXE_Msk (0x1U << USART_ISR_TXE_Pos) /*!< 0x00000080 */ 6159 #define USART_ISR_TXE USART_ISR_TXE_Msk /*!< Transmit Data Register Empty */ 6160 #define USART_ISR_LBDF_Pos (8U) 6161 #define USART_ISR_LBDF_Msk (0x1U << USART_ISR_LBDF_Pos) /*!< 0x00000100 */ 6162 #define USART_ISR_LBDF USART_ISR_LBDF_Msk /*!< LIN Break Detection Flag */ 6163 #define USART_ISR_CTSIF_Pos (9U) 6164 #define USART_ISR_CTSIF_Msk (0x1U << USART_ISR_CTSIF_Pos) /*!< 0x00000200 */ 6165 #define USART_ISR_CTSIF USART_ISR_CTSIF_Msk /*!< CTS interrupt flag */ 6166 #define USART_ISR_CTS_Pos (10U) 6167 #define USART_ISR_CTS_Msk (0x1U << USART_ISR_CTS_Pos) /*!< 0x00000400 */ 6168 #define USART_ISR_CTS USART_ISR_CTS_Msk /*!< CTS flag */ 6169 #define USART_ISR_RTOF_Pos (11U) 6170 #define USART_ISR_RTOF_Msk (0x1U << USART_ISR_RTOF_Pos) /*!< 0x00000800 */ 6171 #define USART_ISR_RTOF USART_ISR_RTOF_Msk /*!< Receiver Time Out */ 6172 #define USART_ISR_EOBF_Pos (12U) 6173 #define USART_ISR_EOBF_Msk (0x1U << USART_ISR_EOBF_Pos) /*!< 0x00001000 */ 6174 #define USART_ISR_EOBF USART_ISR_EOBF_Msk /*!< End Of Block Flag */ 6175 #define USART_ISR_ABRE_Pos (14U) 6176 #define USART_ISR_ABRE_Msk (0x1U << USART_ISR_ABRE_Pos) /*!< 0x00004000 */ 6177 #define USART_ISR_ABRE USART_ISR_ABRE_Msk /*!< Auto-Baud Rate Error */ 6178 #define USART_ISR_ABRF_Pos (15U) 6179 #define USART_ISR_ABRF_Msk (0x1U << USART_ISR_ABRF_Pos) /*!< 0x00008000 */ 6180 #define USART_ISR_ABRF USART_ISR_ABRF_Msk /*!< Auto-Baud Rate Flag */ 6181 #define USART_ISR_BUSY_Pos (16U) 6182 #define USART_ISR_BUSY_Msk (0x1U << USART_ISR_BUSY_Pos) /*!< 0x00010000 */ 6183 #define USART_ISR_BUSY USART_ISR_BUSY_Msk /*!< Busy Flag */ 6184 #define USART_ISR_CMF_Pos (17U) 6185 #define USART_ISR_CMF_Msk (0x1U << USART_ISR_CMF_Pos) /*!< 0x00020000 */ 6186 #define USART_ISR_CMF USART_ISR_CMF_Msk /*!< Character Match Flag */ 6187 #define USART_ISR_SBKF_Pos (18U) 6188 #define USART_ISR_SBKF_Msk (0x1U << USART_ISR_SBKF_Pos) /*!< 0x00040000 */ 6189 #define USART_ISR_SBKF USART_ISR_SBKF_Msk /*!< Send Break Flag */ 6190 #define USART_ISR_RWU_Pos (19U) 6191 #define USART_ISR_RWU_Msk (0x1U << USART_ISR_RWU_Pos) /*!< 0x00080000 */ 6192 #define USART_ISR_RWU USART_ISR_RWU_Msk /*!< Receive Wake Up from mute mode Flag */ 6193 #define USART_ISR_WUF_Pos (20U) 6194 #define USART_ISR_WUF_Msk (0x1U << USART_ISR_WUF_Pos) /*!< 0x00100000 */ 6195 #define USART_ISR_WUF USART_ISR_WUF_Msk /*!< Wake Up from stop mode Flag */ 6196 #define USART_ISR_TEACK_Pos (21U) 6197 #define USART_ISR_TEACK_Msk (0x1U << USART_ISR_TEACK_Pos) /*!< 0x00200000 */ 6198 #define USART_ISR_TEACK USART_ISR_TEACK_Msk /*!< Transmit Enable Acknowledge Flag */ 6199 #define USART_ISR_REACK_Pos (22U) 6200 #define USART_ISR_REACK_Msk (0x1U << USART_ISR_REACK_Pos) /*!< 0x00400000 */ 6201 #define USART_ISR_REACK USART_ISR_REACK_Msk /*!< Receive Enable Acknowledge Flag */ 6202 6203 /******************* Bit definition for USART_ICR register ******************/ 6204 #define USART_ICR_PECF_Pos (0U) 6205 #define USART_ICR_PECF_Msk (0x1U << USART_ICR_PECF_Pos) /*!< 0x00000001 */ 6206 #define USART_ICR_PECF USART_ICR_PECF_Msk /*!< Parity Error Clear Flag */ 6207 #define USART_ICR_FECF_Pos (1U) 6208 #define USART_ICR_FECF_Msk (0x1U << USART_ICR_FECF_Pos) /*!< 0x00000002 */ 6209 #define USART_ICR_FECF USART_ICR_FECF_Msk /*!< Framing Error Clear Flag */ 6210 #define USART_ICR_NCF_Pos (2U) 6211 #define USART_ICR_NCF_Msk (0x1U << USART_ICR_NCF_Pos) /*!< 0x00000004 */ 6212 #define USART_ICR_NCF USART_ICR_NCF_Msk /*!< Noise detected Clear Flag */ 6213 #define USART_ICR_ORECF_Pos (3U) 6214 #define USART_ICR_ORECF_Msk (0x1U << USART_ICR_ORECF_Pos) /*!< 0x00000008 */ 6215 #define USART_ICR_ORECF USART_ICR_ORECF_Msk /*!< OverRun Error Clear Flag */ 6216 #define USART_ICR_IDLECF_Pos (4U) 6217 #define USART_ICR_IDLECF_Msk (0x1U << USART_ICR_IDLECF_Pos) /*!< 0x00000010 */ 6218 #define USART_ICR_IDLECF USART_ICR_IDLECF_Msk /*!< IDLE line detected Clear Flag */ 6219 #define USART_ICR_TCCF_Pos (6U) 6220 #define USART_ICR_TCCF_Msk (0x1U << USART_ICR_TCCF_Pos) /*!< 0x00000040 */ 6221 #define USART_ICR_TCCF USART_ICR_TCCF_Msk /*!< Transmission Complete Clear Flag */ 6222 #define USART_ICR_LBDCF_Pos (8U) 6223 #define USART_ICR_LBDCF_Msk (0x1U << USART_ICR_LBDCF_Pos) /*!< 0x00000100 */ 6224 #define USART_ICR_LBDCF USART_ICR_LBDCF_Msk /*!< LIN Break Detection Clear Flag */ 6225 #define USART_ICR_CTSCF_Pos (9U) 6226 #define USART_ICR_CTSCF_Msk (0x1U << USART_ICR_CTSCF_Pos) /*!< 0x00000200 */ 6227 #define USART_ICR_CTSCF USART_ICR_CTSCF_Msk /*!< CTS Interrupt Clear Flag */ 6228 #define USART_ICR_RTOCF_Pos (11U) 6229 #define USART_ICR_RTOCF_Msk (0x1U << USART_ICR_RTOCF_Pos) /*!< 0x00000800 */ 6230 #define USART_ICR_RTOCF USART_ICR_RTOCF_Msk /*!< Receiver Time Out Clear Flag */ 6231 #define USART_ICR_EOBCF_Pos (12U) 6232 #define USART_ICR_EOBCF_Msk (0x1U << USART_ICR_EOBCF_Pos) /*!< 0x00001000 */ 6233 #define USART_ICR_EOBCF USART_ICR_EOBCF_Msk /*!< End Of Block Clear Flag */ 6234 #define USART_ICR_CMCF_Pos (17U) 6235 #define USART_ICR_CMCF_Msk (0x1U << USART_ICR_CMCF_Pos) /*!< 0x00020000 */ 6236 #define USART_ICR_CMCF USART_ICR_CMCF_Msk /*!< Character Match Clear Flag */ 6237 #define USART_ICR_WUCF_Pos (20U) 6238 #define USART_ICR_WUCF_Msk (0x1U << USART_ICR_WUCF_Pos) /*!< 0x00100000 */ 6239 #define USART_ICR_WUCF USART_ICR_WUCF_Msk /*!< Wake Up from stop mode Clear Flag */ 6240 6241 /******************* Bit definition for USART_RDR register ******************/ 6242 #define USART_RDR_RDR_Pos (0U) 6243 #define USART_RDR_RDR_Msk (0x1FFU << USART_RDR_RDR_Pos) /*!< 0x000001FF */ 6244 #define USART_RDR_RDR USART_RDR_RDR_Msk /*!< RDR[8:0] bits (Receive Data value) */ 6245 6246 /******************* Bit definition for USART_TDR register ******************/ 6247 #define USART_TDR_TDR_Pos (0U) 6248 #define USART_TDR_TDR_Msk (0x1FFU << USART_TDR_TDR_Pos) /*!< 0x000001FF */ 6249 #define USART_TDR_TDR USART_TDR_TDR_Msk /*!< TDR[8:0] bits (Transmit Data value) */ 6250 6251 /******************************************************************************/ 6252 /* */ 6253 /* Window WATCHDOG (WWDG) */ 6254 /* */ 6255 /******************************************************************************/ 6256 6257 /******************* Bit definition for WWDG_CR register ********************/ 6258 #define WWDG_CR_T_Pos (0U) 6259 #define WWDG_CR_T_Msk (0x7FU << WWDG_CR_T_Pos) /*!< 0x0000007F */ 6260 #define WWDG_CR_T WWDG_CR_T_Msk /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */ 6261 #define WWDG_CR_T_0 (0x01U << WWDG_CR_T_Pos) /*!< 0x00000001 */ 6262 #define WWDG_CR_T_1 (0x02U << WWDG_CR_T_Pos) /*!< 0x00000002 */ 6263 #define WWDG_CR_T_2 (0x04U << WWDG_CR_T_Pos) /*!< 0x00000004 */ 6264 #define WWDG_CR_T_3 (0x08U << WWDG_CR_T_Pos) /*!< 0x00000008 */ 6265 #define WWDG_CR_T_4 (0x10U << WWDG_CR_T_Pos) /*!< 0x00000010 */ 6266 #define WWDG_CR_T_5 (0x20U << WWDG_CR_T_Pos) /*!< 0x00000020 */ 6267 #define WWDG_CR_T_6 (0x40U << WWDG_CR_T_Pos) /*!< 0x00000040 */ 6268 6269 /* Legacy defines */ 6270 #define WWDG_CR_T0 WWDG_CR_T_0 6271 #define WWDG_CR_T1 WWDG_CR_T_1 6272 #define WWDG_CR_T2 WWDG_CR_T_2 6273 #define WWDG_CR_T3 WWDG_CR_T_3 6274 #define WWDG_CR_T4 WWDG_CR_T_4 6275 #define WWDG_CR_T5 WWDG_CR_T_5 6276 #define WWDG_CR_T6 WWDG_CR_T_6 6277 6278 #define WWDG_CR_WDGA_Pos (7U) 6279 #define WWDG_CR_WDGA_Msk (0x1U << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */ 6280 #define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!< Activation bit */ 6281 6282 /******************* Bit definition for WWDG_CFR register *******************/ 6283 #define WWDG_CFR_W_Pos (0U) 6284 #define WWDG_CFR_W_Msk (0x7FU << WWDG_CFR_W_Pos) /*!< 0x0000007F */ 6285 #define WWDG_CFR_W WWDG_CFR_W_Msk /*!< W[6:0] bits (7-bit window value) */ 6286 #define WWDG_CFR_W_0 (0x01U << WWDG_CFR_W_Pos) /*!< 0x00000001 */ 6287 #define WWDG_CFR_W_1 (0x02U << WWDG_CFR_W_Pos) /*!< 0x00000002 */ 6288 #define WWDG_CFR_W_2 (0x04U << WWDG_CFR_W_Pos) /*!< 0x00000004 */ 6289 #define WWDG_CFR_W_3 (0x08U << WWDG_CFR_W_Pos) /*!< 0x00000008 */ 6290 #define WWDG_CFR_W_4 (0x10U << WWDG_CFR_W_Pos) /*!< 0x00000010 */ 6291 #define WWDG_CFR_W_5 (0x20U << WWDG_CFR_W_Pos) /*!< 0x00000020 */ 6292 #define WWDG_CFR_W_6 (0x40U << WWDG_CFR_W_Pos) /*!< 0x00000040 */ 6293 6294 /* Legacy defines */ 6295 #define WWDG_CFR_W0 WWDG_CFR_W_0 6296 #define WWDG_CFR_W1 WWDG_CFR_W_1 6297 #define WWDG_CFR_W2 WWDG_CFR_W_2 6298 #define WWDG_CFR_W3 WWDG_CFR_W_3 6299 #define WWDG_CFR_W4 WWDG_CFR_W_4 6300 #define WWDG_CFR_W5 WWDG_CFR_W_5 6301 #define WWDG_CFR_W6 WWDG_CFR_W_6 6302 6303 #define WWDG_CFR_WDGTB_Pos (7U) 6304 #define WWDG_CFR_WDGTB_Msk (0x3U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */ 6305 #define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!< WDGTB[1:0] bits (Timer Base) */ 6306 #define WWDG_CFR_WDGTB_0 (0x1U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000080 */ 6307 #define WWDG_CFR_WDGTB_1 (0x2U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000100 */ 6308 6309 /* Legacy defines */ 6310 #define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0 6311 #define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1 6312 6313 #define WWDG_CFR_EWI_Pos (9U) 6314 #define WWDG_CFR_EWI_Msk (0x1U << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */ 6315 #define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!< Early Wakeup Interrupt */ 6316 6317 /******************* Bit definition for WWDG_SR register ********************/ 6318 #define WWDG_SR_EWIF_Pos (0U) 6319 #define WWDG_SR_EWIF_Msk (0x1U << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */ 6320 #define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!< Early Wakeup Interrupt Flag */ 6321 6322 /** 6323 * @} 6324 */ 6325 6326 /** 6327 * @} 6328 */ 6329 6330 /** @addtogroup Exported_macros 6331 * @{ 6332 */ 6333 6334 /******************************* ADC Instances ********************************/ 6335 #define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1) 6336 #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON) 6337 6338 /******************************* AES Instances ********************************/ 6339 #define IS_AES_ALL_INSTANCE(INSTANCE) ((INSTANCE) == AES) 6340 6341 /******************************* COMP Instances *******************************/ 6342 #define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \ 6343 ((INSTANCE) == COMP2)) 6344 6345 #define IS_COMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == COMP12_COMMON) 6346 6347 /******************************* CRC Instances ********************************/ 6348 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC) 6349 6350 /******************************* DMA Instances *********************************/ 6351 #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \ 6352 ((INSTANCE) == DMA1_Channel2) || \ 6353 ((INSTANCE) == DMA1_Channel3) || \ 6354 ((INSTANCE) == DMA1_Channel4) || \ 6355 ((INSTANCE) == DMA1_Channel5) || \ 6356 ((INSTANCE) == DMA1_Channel6) || \ 6357 ((INSTANCE) == DMA1_Channel7)) 6358 6359 /******************************* GPIO Instances *******************************/ 6360 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \ 6361 ((INSTANCE) == GPIOB) || \ 6362 ((INSTANCE) == GPIOC) || \ 6363 ((INSTANCE) == GPIOD) || \ 6364 ((INSTANCE) == GPIOE) || \ 6365 ((INSTANCE) == GPIOH)) 6366 6367 #define IS_GPIO_AF_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \ 6368 ((INSTANCE) == GPIOB) || \ 6369 ((INSTANCE) == GPIOC) || \ 6370 ((INSTANCE) == GPIOD) || \ 6371 ((INSTANCE) == GPIOE)) 6372 6373 /******************************** I2C Instances *******************************/ 6374 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \ 6375 ((INSTANCE) == I2C2) || \ 6376 ((INSTANCE) == I2C3)) 6377 6378 /****************** I2C Instances : wakeup capability from stop modes *********/ 6379 #define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \ 6380 ((INSTANCE) == I2C3)) 6381 6382 6383 /******************************** I2S Instances *******************************/ 6384 #define IS_I2S_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPI2) 6385 6386 6387 /****************************** RTC Instances *********************************/ 6388 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC) 6389 6390 /******************************** SMBUS Instances *****************************/ 6391 #define IS_SMBUS_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \ 6392 ((INSTANCE) == I2C3)) 6393 6394 /******************************** SPI Instances *******************************/ 6395 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \ 6396 ((INSTANCE) == SPI2)) 6397 6398 /****************** LPTIM Instances : All supported instances *****************/ 6399 #define IS_LPTIM_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1) 6400 6401 /****************** TIM Instances : All supported instances *******************/ 6402 #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ 6403 ((INSTANCE) == TIM3) || \ 6404 ((INSTANCE) == TIM6) || \ 6405 ((INSTANCE) == TIM7) || \ 6406 ((INSTANCE) == TIM21) || \ 6407 ((INSTANCE) == TIM22)) 6408 6409 /****************** TIM Instances : supporting counting mode selection ********/ 6410 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ 6411 ((INSTANCE) == TIM3) || \ 6412 ((INSTANCE) == TIM21) || \ 6413 ((INSTANCE) == TIM22)) 6414 6415 /****************** TIM Instances : supporting clock division *****************/ 6416 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ 6417 ((INSTANCE) == TIM3) || \ 6418 ((INSTANCE) == TIM21) || \ 6419 ((INSTANCE) == TIM22)) 6420 6421 /****** TIM Instances : supporting external clock mode 1 for ETRF input *******/ 6422 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ 6423 ((INSTANCE) == TIM3) || \ 6424 ((INSTANCE) == TIM21)) 6425 6426 /****** TIM Instances : supporting external clock mode 2 for ETRF input *******/ 6427 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ 6428 ((INSTANCE) == TIM3) || \ 6429 ((INSTANCE) == TIM21) || \ 6430 ((INSTANCE) == TIM22)) 6431 6432 /****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/ 6433 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ 6434 ((INSTANCE) == TIM3) || \ 6435 ((INSTANCE) == TIM21)) 6436 6437 /****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/ 6438 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ 6439 ((INSTANCE) == TIM3) || \ 6440 ((INSTANCE) == TIM21) || \ 6441 ((INSTANCE) == TIM22)) 6442 6443 /************* TIM Instances : at least 1 capture/compare channel *************/ 6444 #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ 6445 ((INSTANCE) == TIM3) || \ 6446 ((INSTANCE) == TIM21) || \ 6447 ((INSTANCE) == TIM22)) 6448 6449 /************ TIM Instances : at least 2 capture/compare channels *************/ 6450 #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ 6451 ((INSTANCE) == TIM3) || \ 6452 ((INSTANCE) == TIM21) || \ 6453 ((INSTANCE) == TIM22)) 6454 6455 /************ TIM Instances : at least 3 capture/compare channels *************/ 6456 #define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ 6457 ((INSTANCE) == TIM3)) 6458 6459 /************ TIM Instances : at least 4 capture/compare channels *************/ 6460 #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ 6461 ((INSTANCE) == TIM3)) 6462 6463 /******************** TIM Instances : Advanced-control timers *****************/ 6464 6465 /******************* TIM Instances : Timer input XOR function *****************/ 6466 #define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ 6467 ((INSTANCE) == TIM3)) 6468 6469 /****************** TIM Instances : DMA requests generation (UDE) *************/ 6470 #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ 6471 ((INSTANCE) == TIM3) || \ 6472 ((INSTANCE) == TIM6) || \ 6473 ((INSTANCE) == TIM7)) 6474 6475 /************ TIM Instances : DMA requests generation (CCxDE) *****************/ 6476 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ 6477 ((INSTANCE) == TIM3)) 6478 6479 /************ TIM Instances : DMA requests generation (COMDE) *****************/ 6480 #define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ 6481 (INSTANCE) == TIM3)) 6482 6483 /******************** TIM Instances : DMA burst feature ***********************/ 6484 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ 6485 ((INSTANCE) == TIM3)) 6486 6487 /****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/ 6488 #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ 6489 ((INSTANCE) == TIM3) || \ 6490 ((INSTANCE) == TIM6) || \ 6491 ((INSTANCE) == TIM7) || \ 6492 ((INSTANCE) == TIM21) || \ 6493 ((INSTANCE) == TIM22)) 6494 6495 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/ 6496 #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ 6497 ((INSTANCE) == TIM3) || \ 6498 ((INSTANCE) == TIM21) || \ 6499 ((INSTANCE) == TIM22)) 6500 6501 /********************** TIM Instances : 32 bit Counter ************************/ 6502 6503 /***************** TIM Instances : external trigger input availabe ************/ 6504 #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ 6505 ((INSTANCE) == TIM3) || \ 6506 ((INSTANCE) == TIM21) || \ 6507 ((INSTANCE) == TIM22)) 6508 6509 /****************** TIM Instances : remapping capability **********************/ 6510 #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ 6511 ((INSTANCE) == TIM3) || \ 6512 ((INSTANCE) == TIM21) || \ 6513 ((INSTANCE) == TIM22)) 6514 6515 /****************** TIM Instances : supporting encoder interface **************/ 6516 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ 6517 ((INSTANCE) == TIM3) || \ 6518 ((INSTANCE) == TIM21) || \ 6519 ((INSTANCE) == TIM22)) 6520 6521 /******************* TIM Instances : output(s) OCXEC register *****************/ 6522 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \ 6523 ((INSTANCE) == TIM3)) 6524 6525 /******************* TIM Instances : output(s) available **********************/ 6526 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \ 6527 (((((INSTANCE) == TIM2) || \ 6528 ((INSTANCE) == TIM3)) \ 6529 && \ 6530 (((CHANNEL) == TIM_CHANNEL_1) || \ 6531 ((CHANNEL) == TIM_CHANNEL_2) || \ 6532 ((CHANNEL) == TIM_CHANNEL_3) || \ 6533 ((CHANNEL) == TIM_CHANNEL_4))) \ 6534 || \ 6535 (((INSTANCE) == TIM21) && \ 6536 (((CHANNEL) == TIM_CHANNEL_1) || \ 6537 ((CHANNEL) == TIM_CHANNEL_2))) \ 6538 || \ 6539 (((INSTANCE) == TIM22) && \ 6540 (((CHANNEL) == TIM_CHANNEL_1) || \ 6541 ((CHANNEL) == TIM_CHANNEL_2)))) 6542 6543 /******************** UART Instances : Asynchronous mode **********************/ 6544 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 6545 ((INSTANCE) == USART2) || \ 6546 ((INSTANCE) == USART4) || \ 6547 ((INSTANCE) == USART5) || \ 6548 ((INSTANCE) == LPUART1)) 6549 6550 /******************** USART Instances : Synchronous mode **********************/ 6551 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 6552 ((INSTANCE) == USART2) || \ 6553 ((INSTANCE) == USART4) || \ 6554 ((INSTANCE) == USART5)) 6555 6556 /****************** USART Instances : Auto Baud Rate detection ****************/ 6557 6558 #define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 6559 ((INSTANCE) == USART2)) 6560 6561 /******************** UART Instances : Half-Duplex mode **********************/ 6562 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 6563 ((INSTANCE) == USART2) || \ 6564 ((INSTANCE) == USART4) || \ 6565 ((INSTANCE) == USART5) || \ 6566 ((INSTANCE) == LPUART1)) 6567 6568 /******************** UART Instances : LIN mode **********************/ 6569 #define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 6570 ((INSTANCE) == USART2)) 6571 6572 /******************** UART Instances : Wake-up from Stop mode **********************/ 6573 #define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 6574 ((INSTANCE) == USART2) || \ 6575 ((INSTANCE) == LPUART1)) 6576 /****************** UART Instances : Hardware Flow control ********************/ 6577 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 6578 ((INSTANCE) == USART2) || \ 6579 ((INSTANCE) == USART4) || \ 6580 ((INSTANCE) == USART5) || \ 6581 ((INSTANCE) == LPUART1)) 6582 6583 /********************* UART Instances : Smard card mode ***********************/ 6584 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 6585 ((INSTANCE) == USART2)) 6586 6587 /*********************** UART Instances : IRDA mode ***************************/ 6588 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ 6589 ((INSTANCE) == USART2)) 6590 6591 /******************** LPUART Instance *****************************************/ 6592 #define IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1) 6593 6594 /****************************** IWDG Instances ********************************/ 6595 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG) 6596 6597 /****************************** WWDG Instances ********************************/ 6598 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG) 6599 6600 /** 6601 * @} 6602 */ 6603 6604 /******************************************************************************/ 6605 /* For a painless codes migration between the STM32L0xx device product */ 6606 /* lines, the aliases defined below are put in place to overcome the */ 6607 /* differences in the interrupt handlers and IRQn definitions. */ 6608 /* No need to update developed interrupt code when moving across */ 6609 /* product lines within the same STM32L0 Family */ 6610 /******************************************************************************/ 6611 6612 /* Aliases for __IRQn */ 6613 6614 #define RNG_LPUART1_IRQn AES_LPUART1_IRQn 6615 #define LPUART1_IRQn AES_LPUART1_IRQn 6616 #define AES_RNG_LPUART1_IRQn AES_LPUART1_IRQn 6617 #define TIM6_DAC_IRQn TIM6_IRQn 6618 #define RCC_CRS_IRQn RCC_IRQn 6619 6620 /* Aliases for __IRQHandler */ 6621 #define LPUART1_IRQHandler AES_LPUART1_IRQHandler 6622 #define RNG_LPUART1_IRQHandler AES_LPUART1_IRQHandler 6623 #define AES_RNG_LPUART1_IRQHandler AES_LPUART1_IRQHandler 6624 #define TIM6_DAC_IRQHandler TIM6_IRQHandler 6625 #define RCC_CRS_IRQHandler RCC_IRQHandler 6626 6627 /** 6628 * @} 6629 */ 6630 6631 /** 6632 * @} 6633 */ 6634 6635 #ifdef __cplusplus 6636 } 6637 #endif /* __cplusplus */ 6638 6639 #endif /* __STM32L081xx_H */ 6640 6641 6642 6643 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 6644
