1 /****************************************************************************** 2 * Filename: hw_bpu_h 3 ****************************************************************************** 4 * Copyright (c) 2021 Texas Instruments Incorporated. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are met: 8 * 9 * 1) Redistributions of source code must retain the above copyright notice, 10 * this list of conditions and the following disclaimer. 11 * 12 * 2) Redistributions in binary form must reproduce the above copyright notice, 13 * this list of conditions and the following disclaimer in the documentation 14 * and/or other materials provided with the distribution. 15 * 16 * 3) Neither the name of the copyright holder nor the names of its contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 24 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 ******************************************************************************/ 32 33 #ifndef __HW_BPU_H__ 34 #define __HW_BPU_H__ 35 36 //***************************************************************************** 37 // 38 // This section defines the register offsets of 39 // BPU component 40 // 41 //***************************************************************************** 42 // Breakpoint Control Register 43 #define BPU_O_BP_CTRL 0x00000000U 44 45 // Breakpoint Comparator Register 0 46 #define BPU_O_BP_COMP0 0x00000008U 47 48 // Breakpoint Comparator Register 1 49 #define BPU_O_BP_COMP1 0x0000000CU 50 51 // Breakpoint Comparator Register 2 52 #define BPU_O_BP_COMP2 0x00000010U 53 54 // Breakpoint Comparator Register 3 55 #define BPU_O_BP_COMP3 0x00000014U 56 57 // Peripheral ID Register 4 58 #define BPU_O_PIDR4 0x00000FD0U 59 60 // Peripheral ID Register 5 61 #define BPU_O_PIDR5 0x00000FD4U 62 63 // Peripheral ID Register 6 64 #define BPU_O_PIDR6 0x00000FD8U 65 66 // Peripheral ID Register 7 67 #define BPU_O_PIDR7 0x00000FDCU 68 69 // Peripheral ID Register 0 70 #define BPU_O_PIDR0 0x00000FE0U 71 72 // Peripheral ID Register 1 73 #define BPU_O_PIDR1 0x00000FE4U 74 75 // Peripheral ID Register 2 76 #define BPU_O_PIDR2 0x00000FE8U 77 78 // Peripheral ID Register 3 79 #define BPU_O_PIDR3 0x00000FECU 80 81 // Component ID Register 0 82 #define BPU_O_CIDR0 0x00000FF0U 83 84 // Component ID Register 1 85 #define BPU_O_CIDR1 0x00000FF4U 86 87 // Component ID Register 2 88 #define BPU_O_CIDR2 0x00000FF8U 89 90 // Component ID Register 3 91 #define BPU_O_CIDR3 0x00000FFCU 92 93 //***************************************************************************** 94 // 95 // Register: BPU_O_BP_CTRL 96 // 97 //***************************************************************************** 98 // Field: [7:4] NUM_CODE 99 // 100 // Number of comparators. 101 #define BPU_BP_CTRL_NUM_CODE_W 4U 102 #define BPU_BP_CTRL_NUM_CODE_M 0x000000F0U 103 #define BPU_BP_CTRL_NUM_CODE_S 4U 104 105 // Field: [1] KEY 106 // 107 // Key field. To write to the Breakpoint Control Register, you must write a 1 108 // to this write-only bit. This bit reads as zero. 109 #define BPU_BP_CTRL_KEY 0x00000002U 110 #define BPU_BP_CTRL_KEY_M 0x00000002U 111 #define BPU_BP_CTRL_KEY_S 1U 112 113 // Field: [0] ENABLE 114 // 115 // Breakpoint unit enable bit. DBGRESETn clears the ENABLE bit. 116 // ENUMs: 117 // BKPT_EN Breakpoint unit enabled 118 // BKPT_DIS Breakpoint unit disabled 119 #define BPU_BP_CTRL_ENABLE 0x00000001U 120 #define BPU_BP_CTRL_ENABLE_M 0x00000001U 121 #define BPU_BP_CTRL_ENABLE_S 0U 122 #define BPU_BP_CTRL_ENABLE_BKPT_EN 0x00000001U 123 #define BPU_BP_CTRL_ENABLE_BKPT_DIS 0x00000000U 124 125 //***************************************************************************** 126 // 127 // Register: BPU_O_BP_COMP0 128 // 129 //***************************************************************************** 130 // Field: [31:30] BP_MATCH 131 // 132 // This selects what happens when the COMP address is matched 133 // ENUMs: 134 // BKPT_COMP_BOTH set breakpoint on both lower and upper halfwords 135 // BKPT_COMP_HI set breakpoint on upper halfword, lower is 136 // unaffected 137 // BKPT_COMP_LOW set breakpoint on lower halfword, upper is 138 // unaffected 139 // BKPT_COMP_NONE no breakpoint generated 140 #define BPU_BP_COMP0_BP_MATCH_W 2U 141 #define BPU_BP_COMP0_BP_MATCH_M 0xC0000000U 142 #define BPU_BP_COMP0_BP_MATCH_S 30U 143 #define BPU_BP_COMP0_BP_MATCH_BKPT_COMP_BOTH 0xC0000000U 144 #define BPU_BP_COMP0_BP_MATCH_BKPT_COMP_HI 0x80000000U 145 #define BPU_BP_COMP0_BP_MATCH_BKPT_COMP_LOW 0x40000000U 146 #define BPU_BP_COMP0_BP_MATCH_BKPT_COMP_NONE 0x00000000U 147 148 // Field: [28:2] COMP 149 // 150 // Comparison address, UNKNOWN on reset. 151 #define BPU_BP_COMP0_COMP_W 27U 152 #define BPU_BP_COMP0_COMP_M 0x1FFFFFFCU 153 #define BPU_BP_COMP0_COMP_S 2U 154 155 // Field: [0] ENABLE 156 // 157 // Compare enable for Breakpoint Comparator Register 0. The ENABLE bit of 158 // BP_CTRL must also be set to enable comparisons. DBGRESETn clears the ENABLE 159 // bit. 160 // ENUMs: 161 // BKPT_COMP_DIS Breakpoint Comparator Register 0 compare enabled 162 // BKPT_COMP_EN Breakpoint Comparator Register 0 compare disabled 163 #define BPU_BP_COMP0_ENABLE 0x00000001U 164 #define BPU_BP_COMP0_ENABLE_M 0x00000001U 165 #define BPU_BP_COMP0_ENABLE_S 0U 166 #define BPU_BP_COMP0_ENABLE_BKPT_COMP_DIS 0x00000001U 167 #define BPU_BP_COMP0_ENABLE_BKPT_COMP_EN 0x00000000U 168 169 //***************************************************************************** 170 // 171 // Register: BPU_O_BP_COMP1 172 // 173 //***************************************************************************** 174 // Field: [31:30] BP_MATCH 175 // 176 // This selects what happens when the COMP address is matched 177 // ENUMs: 178 // BKPT_COMP_BOTH Set breakpoint on both lower and upper halfwords 179 // BKPT_COMP_HI Set breakpoint on upper halfword, lower is 180 // unaffected 181 // BKPT_COMP_LOW Set breakpoint on lower halfword, upper is 182 // unaffected 183 // BKPT_COMP_NONE No breakpoint generated 184 #define BPU_BP_COMP1_BP_MATCH_W 2U 185 #define BPU_BP_COMP1_BP_MATCH_M 0xC0000000U 186 #define BPU_BP_COMP1_BP_MATCH_S 30U 187 #define BPU_BP_COMP1_BP_MATCH_BKPT_COMP_BOTH 0xC0000000U 188 #define BPU_BP_COMP1_BP_MATCH_BKPT_COMP_HI 0x80000000U 189 #define BPU_BP_COMP1_BP_MATCH_BKPT_COMP_LOW 0x40000000U 190 #define BPU_BP_COMP1_BP_MATCH_BKPT_COMP_NONE 0x00000000U 191 192 // Field: [28:2] COMP 193 // 194 // Comparison address. Although it is architecturally Unpredictable whether 195 // breakpoint matches on the address of the second halfword of a 32-bit 196 // instruction to generates a debug event, in this processor it is predictable 197 // and a debug event is generated. 198 #define BPU_BP_COMP1_COMP_W 27U 199 #define BPU_BP_COMP1_COMP_M 0x1FFFFFFCU 200 #define BPU_BP_COMP1_COMP_S 2U 201 202 // Field: [0] ENABLE 203 // 204 // Comparison address, UNKNOWN on reset. 205 // ENUMs: 206 // BKPT_COMP_DIS Breakpoint Comparator Register 1 compare enabled 207 // BKPT_COMP_EN Breakpoint Comparator Register 1 compare disabled 208 #define BPU_BP_COMP1_ENABLE 0x00000001U 209 #define BPU_BP_COMP1_ENABLE_M 0x00000001U 210 #define BPU_BP_COMP1_ENABLE_S 0U 211 #define BPU_BP_COMP1_ENABLE_BKPT_COMP_DIS 0x00000001U 212 #define BPU_BP_COMP1_ENABLE_BKPT_COMP_EN 0x00000000U 213 214 //***************************************************************************** 215 // 216 // Register: BPU_O_BP_COMP2 217 // 218 //***************************************************************************** 219 // Field: [31:30] BP_MATCH 220 // 221 // This selects what happens when the COMP address is matched 222 // ENUMs: 223 // BKPT_COMP_BOTH Set breakpoint on both lower and upper halfwords 224 // BKPT_COMP_HI Set breakpoint on upper halfword, lower is 225 // unaffected 226 // BKPT_COMP_LOW Set breakpoint on lower halfword, upper is 227 // unaffected 228 // BKPT_COMP_NONE No breakpoint matching 229 #define BPU_BP_COMP2_BP_MATCH_W 2U 230 #define BPU_BP_COMP2_BP_MATCH_M 0xC0000000U 231 #define BPU_BP_COMP2_BP_MATCH_S 30U 232 #define BPU_BP_COMP2_BP_MATCH_BKPT_COMP_BOTH 0xC0000000U 233 #define BPU_BP_COMP2_BP_MATCH_BKPT_COMP_HI 0x80000000U 234 #define BPU_BP_COMP2_BP_MATCH_BKPT_COMP_LOW 0x40000000U 235 #define BPU_BP_COMP2_BP_MATCH_BKPT_COMP_NONE 0x00000000U 236 237 // Field: [28:2] COMP 238 // 239 // Comparison address, UNKNOWN on reset. 240 #define BPU_BP_COMP2_COMP_W 27U 241 #define BPU_BP_COMP2_COMP_M 0x1FFFFFFCU 242 #define BPU_BP_COMP2_COMP_S 2U 243 244 // Field: [0] ENABLE 245 // 246 // Compare enable for Breakpoint Comparator Register 2. The ENABLE bit of 247 // BP_CTRL must also be set to enable comparisons. DBGRESETn clears the ENABLE 248 // bit. 249 // ENUMs: 250 // BKPT_COMP_DIS Breakpoint Comparator Register 2 compare enabled 251 // BKPT_COMP_EN Breakpoint Comparator Register 2 compare disabled 252 #define BPU_BP_COMP2_ENABLE 0x00000001U 253 #define BPU_BP_COMP2_ENABLE_M 0x00000001U 254 #define BPU_BP_COMP2_ENABLE_S 0U 255 #define BPU_BP_COMP2_ENABLE_BKPT_COMP_DIS 0x00000001U 256 #define BPU_BP_COMP2_ENABLE_BKPT_COMP_EN 0x00000000U 257 258 //***************************************************************************** 259 // 260 // Register: BPU_O_BP_COMP3 261 // 262 //***************************************************************************** 263 // Field: [31:30] BP_MATCH 264 // 265 // This selects what happens when the COMP address is matched 266 // ENUMs: 267 // BKPT_COMP_BOTH Set breakpoint on both lower and upper halfwords 268 // BKPT_COMP_HI Set breakpoint on upper halfword, lower is 269 // unaffected 270 // BKPT_COMP_LOW Set breakpoint on lower halfword, upper is 271 // unaffected 272 // BKPT_COMP_NONE No breakpoint generated 273 #define BPU_BP_COMP3_BP_MATCH_W 2U 274 #define BPU_BP_COMP3_BP_MATCH_M 0xC0000000U 275 #define BPU_BP_COMP3_BP_MATCH_S 30U 276 #define BPU_BP_COMP3_BP_MATCH_BKPT_COMP_BOTH 0xC0000000U 277 #define BPU_BP_COMP3_BP_MATCH_BKPT_COMP_HI 0x80000000U 278 #define BPU_BP_COMP3_BP_MATCH_BKPT_COMP_LOW 0x40000000U 279 #define BPU_BP_COMP3_BP_MATCH_BKPT_COMP_NONE 0x00000000U 280 281 // Field: [28:2] COMP 282 // 283 // Comparison address, UNKNOWN on reset. 284 #define BPU_BP_COMP3_COMP_W 27U 285 #define BPU_BP_COMP3_COMP_M 0x1FFFFFFCU 286 #define BPU_BP_COMP3_COMP_S 2U 287 288 // Field: [0] ENABLE 289 // 290 // Compare enable for Breakpoint Comparator Register 3. The ENABLE bit of 291 // BP_CTRL must also be set to enable comparisons. DBGRESETn clears the ENABLE 292 // bit. 293 // ENUMs: 294 // BKPT_COMP_DIS Breakpoint Comparator Register 3 compare enabled 295 // BKPT_COMP_EN Breakpoint Comparator Register 3 compare disabled 296 #define BPU_BP_COMP3_ENABLE 0x00000001U 297 #define BPU_BP_COMP3_ENABLE_M 0x00000001U 298 #define BPU_BP_COMP3_ENABLE_S 0U 299 #define BPU_BP_COMP3_ENABLE_BKPT_COMP_DIS 0x00000001U 300 #define BPU_BP_COMP3_ENABLE_BKPT_COMP_EN 0x00000000U 301 302 //***************************************************************************** 303 // 304 // Register: BPU_O_PIDR4 305 // 306 //***************************************************************************** 307 // Field: [7:4] SIZE 308 // 309 // This is a 4-bit value that indicates the total contiguous size of the memory 310 // window used by this component in powers of 2 from the standard 4KB. If a 311 // component only requires the standard 4KB then this should read as 0x0, 4KB 312 // only, for 8KB set to 0x1, 16KB == 0x2, 32KB == 0x3, and so on. 313 #define BPU_PIDR4_SIZE_W 4U 314 #define BPU_PIDR4_SIZE_M 0x000000F0U 315 #define BPU_PIDR4_SIZE_S 4U 316 317 // Field: [3:0] DES_2 318 // 319 // Number of JEDEC continuation codes. Indicates the designer of the component 320 // (along with the identity code) 321 #define BPU_PIDR4_DES_2_W 4U 322 #define BPU_PIDR4_DES_2_M 0x0000000FU 323 #define BPU_PIDR4_DES_2_S 0U 324 325 //***************************************************************************** 326 // 327 // Register: BPU_O_PIDR5 328 // 329 //***************************************************************************** 330 //***************************************************************************** 331 // 332 // Register: BPU_O_PIDR6 333 // 334 //***************************************************************************** 335 //***************************************************************************** 336 // 337 // Register: BPU_O_PIDR7 338 // 339 //***************************************************************************** 340 //***************************************************************************** 341 // 342 // Register: BPU_O_PIDR0 343 // 344 //***************************************************************************** 345 // Field: [7:0] PART_0 346 // 347 // Bits [7:0] of the component's part number. This is selected by the designer 348 // of the component. 349 #define BPU_PIDR0_PART_0_W 8U 350 #define BPU_PIDR0_PART_0_M 0x000000FFU 351 #define BPU_PIDR0_PART_0_S 0U 352 353 //***************************************************************************** 354 // 355 // Register: BPU_O_PIDR1 356 // 357 //***************************************************************************** 358 // Field: [7:4] DES_0 359 // 360 // Bits [3:0] of the JEDEC identity code indicating the designer of the 361 // component (along with the continuation code) 362 #define BPU_PIDR1_DES_0_W 4U 363 #define BPU_PIDR1_DES_0_M 0x000000F0U 364 #define BPU_PIDR1_DES_0_S 4U 365 366 // Field: [3:0] PART_1 367 // 368 // Bits [11:8] of the component's part number. This is selected by the designer 369 // of the component. 370 #define BPU_PIDR1_PART_1_W 4U 371 #define BPU_PIDR1_PART_1_M 0x0000000FU 372 #define BPU_PIDR1_PART_1_S 0U 373 374 //***************************************************************************** 375 // 376 // Register: BPU_O_PIDR2 377 // 378 //***************************************************************************** 379 // Field: [7:4] REVISION 380 // 381 // The Revision field is an incremental value starting at 0x0 for the first 382 // design of this component. This only increases by 1 for both major and minor 383 // revisions and is simply used as a look-up to establish the exact major/minor 384 // revision. 385 #define BPU_PIDR2_REVISION_W 4U 386 #define BPU_PIDR2_REVISION_M 0x000000F0U 387 #define BPU_PIDR2_REVISION_S 4U 388 389 // Field: [3] JEDEC 390 // 391 // Always set. Indicates that a JEDEC assigned value is used 392 #define BPU_PIDR2_JEDEC 0x00000008U 393 #define BPU_PIDR2_JEDEC_M 0x00000008U 394 #define BPU_PIDR2_JEDEC_S 3U 395 396 // Field: [2:0] DES_1 397 // 398 // Bits [6:4] of the JEDEC identity code indicating the designer of the 399 // component (along with the continuation code) 400 #define BPU_PIDR2_DES_1_W 3U 401 #define BPU_PIDR2_DES_1_M 0x00000007U 402 #define BPU_PIDR2_DES_1_S 0U 403 404 //***************************************************************************** 405 // 406 // Register: BPU_O_PIDR3 407 // 408 //***************************************************************************** 409 // Field: [7:4] REVAND 410 // 411 // This field indicates minor errata fixes specific to this design, for example 412 // metal fixes after implementation. In most cases this field is zero. It is 413 // recommended that component designers ensure this field can be changed by a 414 // metal fix if required, for example by driving it from registers that reset 415 // to zero. 416 #define BPU_PIDR3_REVAND_W 4U 417 #define BPU_PIDR3_REVAND_M 0x000000F0U 418 #define BPU_PIDR3_REVAND_S 4U 419 420 // Field: [3:0] CMOD 421 // 422 // Where the component is reusable IP, this value indicates if the customer has 423 // modified the behavior of the component. In most cases this field is zero. 424 #define BPU_PIDR3_CMOD_W 4U 425 #define BPU_PIDR3_CMOD_M 0x0000000FU 426 #define BPU_PIDR3_CMOD_S 0U 427 428 //***************************************************************************** 429 // 430 // Register: BPU_O_CIDR0 431 // 432 //***************************************************************************** 433 // Field: [7:0] PRMBL_0 434 // 435 // Contains bits [7:0] of the component identification 436 #define BPU_CIDR0_PRMBL_0_W 8U 437 #define BPU_CIDR0_PRMBL_0_M 0x000000FFU 438 #define BPU_CIDR0_PRMBL_0_S 0U 439 440 //***************************************************************************** 441 // 442 // Register: BPU_O_CIDR1 443 // 444 //***************************************************************************** 445 // Field: [7:4] CLASS 446 // 447 // Class of the component. E.g. ROM table, CoreSight component etc. Constitutes 448 // bits [15:12] of the component identification. 449 #define BPU_CIDR1_CLASS_W 4U 450 #define BPU_CIDR1_CLASS_M 0x000000F0U 451 #define BPU_CIDR1_CLASS_S 4U 452 453 // Field: [3:0] PRMBL_1 454 // 455 // Contains bits [11:8] of the component identification 456 #define BPU_CIDR1_PRMBL_1_W 4U 457 #define BPU_CIDR1_PRMBL_1_M 0x0000000FU 458 #define BPU_CIDR1_PRMBL_1_S 0U 459 460 //***************************************************************************** 461 // 462 // Register: BPU_O_CIDR2 463 // 464 //***************************************************************************** 465 // Field: [7:0] PRMBL_2 466 // 467 // Contains bits [23:16] of the component identification 468 #define BPU_CIDR2_PRMBL_2_W 8U 469 #define BPU_CIDR2_PRMBL_2_M 0x000000FFU 470 #define BPU_CIDR2_PRMBL_2_S 0U 471 472 //***************************************************************************** 473 // 474 // Register: BPU_O_CIDR3 475 // 476 //***************************************************************************** 477 // Field: [7:0] PRMBL_3 478 // 479 // Contains bits [31:24] of the component identification 480 #define BPU_CIDR3_PRMBL_3_W 8U 481 #define BPU_CIDR3_PRMBL_3_M 0x000000FFU 482 #define BPU_CIDR3_PRMBL_3_S 0U 483 484 485 #endif // __BPU__ 486
