1 /****************************************************************************** 2 * Filename: hw_ioc_h 3 * Revised: $Date$ 4 * Revision: $Revision$ 5 * 6 * Copyright (c) 2015 - 2017, Texas Instruments Incorporated 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions are met: 11 * 12 * 1) Redistributions of source code must retain the above copyright notice, 13 * this list of conditions and the following disclaimer. 14 * 15 * 2) Redistributions in binary form must reproduce the above copyright notice, 16 * this list of conditions and the following disclaimer in the documentation 17 * and/or other materials provided with the distribution. 18 * 19 * 3) Neither the name of the ORGANIZATION nor the names of its contributors may 20 * be used to endorse or promote products derived from this software without 21 * specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 27 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 * 35 ******************************************************************************/ 36 37 #ifndef __HW_IOC_H__ 38 #define __HW_IOC_H__ 39 40 //***************************************************************************** 41 // 42 // This section defines the register offsets of 43 // IOC component 44 // 45 //***************************************************************************** 46 // Configuration of DIO0 47 #define IOC_O_IOCFG0 0x00000000 48 49 // Configuration of DIO1 50 #define IOC_O_IOCFG1 0x00000004 51 52 // Configuration of DIO2 53 #define IOC_O_IOCFG2 0x00000008 54 55 // Configuration of DIO3 56 #define IOC_O_IOCFG3 0x0000000C 57 58 // Configuration of DIO4 59 #define IOC_O_IOCFG4 0x00000010 60 61 // Configuration of DIO5 62 #define IOC_O_IOCFG5 0x00000014 63 64 // Configuration of DIO6 65 #define IOC_O_IOCFG6 0x00000018 66 67 // Configuration of DIO7 68 #define IOC_O_IOCFG7 0x0000001C 69 70 // Configuration of DIO8 71 #define IOC_O_IOCFG8 0x00000020 72 73 // Configuration of DIO9 74 #define IOC_O_IOCFG9 0x00000024 75 76 // Configuration of DIO10 77 #define IOC_O_IOCFG10 0x00000028 78 79 // Configuration of DIO11 80 #define IOC_O_IOCFG11 0x0000002C 81 82 // Configuration of DIO12 83 #define IOC_O_IOCFG12 0x00000030 84 85 // Configuration of DIO13 86 #define IOC_O_IOCFG13 0x00000034 87 88 // Configuration of DIO14 89 #define IOC_O_IOCFG14 0x00000038 90 91 // Configuration of DIO15 92 #define IOC_O_IOCFG15 0x0000003C 93 94 // Configuration of DIO16 95 #define IOC_O_IOCFG16 0x00000040 96 97 // Configuration of DIO17 98 #define IOC_O_IOCFG17 0x00000044 99 100 // Configuration of DIO18 101 #define IOC_O_IOCFG18 0x00000048 102 103 // Configuration of DIO19 104 #define IOC_O_IOCFG19 0x0000004C 105 106 // Configuration of DIO20 107 #define IOC_O_IOCFG20 0x00000050 108 109 // Configuration of DIO21 110 #define IOC_O_IOCFG21 0x00000054 111 112 // Configuration of DIO22 113 #define IOC_O_IOCFG22 0x00000058 114 115 // Configuration of DIO23 116 #define IOC_O_IOCFG23 0x0000005C 117 118 // Configuration of DIO24 119 #define IOC_O_IOCFG24 0x00000060 120 121 // Configuration of DIO25 122 #define IOC_O_IOCFG25 0x00000064 123 124 // Configuration of DIO26 125 #define IOC_O_IOCFG26 0x00000068 126 127 // Configuration of DIO27 128 #define IOC_O_IOCFG27 0x0000006C 129 130 // Configuration of DIO28 131 #define IOC_O_IOCFG28 0x00000070 132 133 // Configuration of DIO29 134 #define IOC_O_IOCFG29 0x00000074 135 136 // Configuration of DIO30 137 #define IOC_O_IOCFG30 0x00000078 138 139 // Configuration of DIO31 140 #define IOC_O_IOCFG31 0x0000007C 141 142 //***************************************************************************** 143 // 144 // Register: IOC_O_IOCFG0 145 // 146 //***************************************************************************** 147 // Field: [30] HYST_EN 148 // 149 // 0: Input hysteresis disable 150 // 1: Input hysteresis enable 151 #define IOC_IOCFG0_HYST_EN 0x40000000 152 #define IOC_IOCFG0_HYST_EN_BITN 30 153 #define IOC_IOCFG0_HYST_EN_M 0x40000000 154 #define IOC_IOCFG0_HYST_EN_S 30 155 156 // Field: [29] IE 157 // 158 // 0: Input disabled 159 // 1: Input enabled 160 // 161 // Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be 162 // ignored. 163 #define IOC_IOCFG0_IE 0x20000000 164 #define IOC_IOCFG0_IE_BITN 29 165 #define IOC_IOCFG0_IE_M 0x20000000 166 #define IOC_IOCFG0_IE_S 29 167 168 // Field: [28:27] WU_CFG 169 // 170 // If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or 171 // >0x08: 172 // 173 // 00: No wake-up 174 // 01: No wake-up 175 // 10: Wakes up from shutdown if this pad is going low. 176 // 11: Wakes up from shutdown if this pad is going high. 177 // 178 // If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, 179 // this register only sets wakeup enable or not. 180 // 181 // 00, 01: Wakeup disabled 182 // 10, 11: Wakeup enabled 183 // 184 // Polarity is controlled from AON registers. 185 // 186 // Note:When the MSB is set, the IOC will deactivate the output enable for the 187 // DIO. 188 #define IOC_IOCFG0_WU_CFG_W 2 189 #define IOC_IOCFG0_WU_CFG_M 0x18000000 190 #define IOC_IOCFG0_WU_CFG_S 27 191 192 // Field: [26:24] IOMODE 193 // 194 // IO Mode 195 // Not applicable for IO configured for AON periph. signals and AUX PORT_ID 196 // 0x01-0x08 197 // AUX has its own open_source/drain configuration. 198 // 199 // 0x2: Reserved. Undefined behavior. 200 // 0x3: Reserved. Undefined behavior. 201 // ENUMs: 202 // OPENSRC_INV Open Source 203 // Inverted input/output 204 // OPENSRC Open Source 205 // Normal input / outut 206 // OPENDR_INV Open Drain 207 // Inverted input / output 208 // OPENDR Open Drain, 209 // Normal input / output 210 // INV Inverted input / ouput 211 // NORMAL Normal input / output 212 #define IOC_IOCFG0_IOMODE_W 3 213 #define IOC_IOCFG0_IOMODE_M 0x07000000 214 #define IOC_IOCFG0_IOMODE_S 24 215 #define IOC_IOCFG0_IOMODE_OPENSRC_INV 0x07000000 216 #define IOC_IOCFG0_IOMODE_OPENSRC 0x06000000 217 #define IOC_IOCFG0_IOMODE_OPENDR_INV 0x05000000 218 #define IOC_IOCFG0_IOMODE_OPENDR 0x04000000 219 #define IOC_IOCFG0_IOMODE_INV 0x01000000 220 #define IOC_IOCFG0_IOMODE_NORMAL 0x00000000 221 222 // Field: [23] IOEV_AON_PROG2_EN 223 // 224 // Event asserted by this IO when edge detection is enabled 225 // 226 // 0: Input edge detection does not assert AON_PROG2 event 227 // 1: Input edge detection asserts AON_PROG2 event 228 #define IOC_IOCFG0_IOEV_AON_PROG2_EN 0x00800000 229 #define IOC_IOCFG0_IOEV_AON_PROG2_EN_BITN 23 230 #define IOC_IOCFG0_IOEV_AON_PROG2_EN_M 0x00800000 231 #define IOC_IOCFG0_IOEV_AON_PROG2_EN_S 23 232 233 // Field: [22] IOEV_AON_PROG1_EN 234 // 235 // Event asserted by this IO when edge detection is enabled 236 // 237 // 0: Input edge detection does not assert AON_PROG1 event 238 // 1: Input edge detection asserts AON_PROG1 event 239 #define IOC_IOCFG0_IOEV_AON_PROG1_EN 0x00400000 240 #define IOC_IOCFG0_IOEV_AON_PROG1_EN_BITN 22 241 #define IOC_IOCFG0_IOEV_AON_PROG1_EN_M 0x00400000 242 #define IOC_IOCFG0_IOEV_AON_PROG1_EN_S 22 243 244 // Field: [21] IOEV_AON_PROG0_EN 245 // 246 // Event asserted by this IO when edge detection is enabled 247 // 248 // 0: Input edge detection does not assert AON_PROG0 event 249 // 1: Input edge detection asserts AON_PROG0 event 250 #define IOC_IOCFG0_IOEV_AON_PROG0_EN 0x00200000 251 #define IOC_IOCFG0_IOEV_AON_PROG0_EN_BITN 21 252 #define IOC_IOCFG0_IOEV_AON_PROG0_EN_M 0x00200000 253 #define IOC_IOCFG0_IOEV_AON_PROG0_EN_S 21 254 255 // Field: [18] EDGE_IRQ_EN 256 // 257 // 0: No interrupt generation 258 // 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is 259 // enabled) 260 #define IOC_IOCFG0_EDGE_IRQ_EN 0x00040000 261 #define IOC_IOCFG0_EDGE_IRQ_EN_BITN 18 262 #define IOC_IOCFG0_EDGE_IRQ_EN_M 0x00040000 263 #define IOC_IOCFG0_EDGE_IRQ_EN_S 18 264 265 // Field: [17:16] EDGE_DET 266 // 267 // Enable generation of edge detection events on this IO 268 // ENUMs: 269 // BOTH Positive and negative edge detection 270 // POS Positive edge detection 271 // NEG Negative edge detection 272 // NONE No edge detection 273 #define IOC_IOCFG0_EDGE_DET_W 2 274 #define IOC_IOCFG0_EDGE_DET_M 0x00030000 275 #define IOC_IOCFG0_EDGE_DET_S 16 276 #define IOC_IOCFG0_EDGE_DET_BOTH 0x00030000 277 #define IOC_IOCFG0_EDGE_DET_POS 0x00020000 278 #define IOC_IOCFG0_EDGE_DET_NEG 0x00010000 279 #define IOC_IOCFG0_EDGE_DET_NONE 0x00000000 280 281 // Field: [14:13] PULL_CTL 282 // 283 // Pull control 284 // ENUMs: 285 // DIS No pull 286 // UP Pull up 287 // DWN Pull down 288 #define IOC_IOCFG0_PULL_CTL_W 2 289 #define IOC_IOCFG0_PULL_CTL_M 0x00006000 290 #define IOC_IOCFG0_PULL_CTL_S 13 291 #define IOC_IOCFG0_PULL_CTL_DIS 0x00006000 292 #define IOC_IOCFG0_PULL_CTL_UP 0x00004000 293 #define IOC_IOCFG0_PULL_CTL_DWN 0x00002000 294 295 // Field: [12] SLEW_RED 296 // 297 // 0: Normal slew rate 298 // 1: Enables reduced slew rate in output driver. 299 #define IOC_IOCFG0_SLEW_RED 0x00001000 300 #define IOC_IOCFG0_SLEW_RED_BITN 12 301 #define IOC_IOCFG0_SLEW_RED_M 0x00001000 302 #define IOC_IOCFG0_SLEW_RED_S 12 303 304 // Field: [11:10] IOCURR 305 // 306 // Selects IO current mode of this IO. 307 // ENUMs: 308 // 4_8MA Extended-Current (EC) mode: Min 8 mA for double 309 // drive strength IOs (min 4 mA for normal IOs) 310 // when IOSTR is set to AUTO 311 // 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set 312 // to AUTO 313 // 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set 314 // to AUTO 315 #define IOC_IOCFG0_IOCURR_W 2 316 #define IOC_IOCFG0_IOCURR_M 0x00000C00 317 #define IOC_IOCFG0_IOCURR_S 10 318 #define IOC_IOCFG0_IOCURR_4_8MA 0x00000800 319 #define IOC_IOCFG0_IOCURR_4MA 0x00000400 320 #define IOC_IOCFG0_IOCURR_2MA 0x00000000 321 322 // Field: [9:8] IOSTR 323 // 324 // Select source for drive strength control of this IO. 325 // This setting controls the drive strength of the Low-Current (LC) mode. 326 // Higher drive strength can be selected in IOCURR 327 // ENUMs: 328 // MAX Maximum drive strength, controlled by 329 // AON_IOC:IOSTRMAX (min 2 mA @1.8V with default 330 // values) 331 // MED Medium drive strength, controlled by 332 // AON_IOC:IOSTRMED (min 2 mA @2.5V with default 333 // values) 334 // MIN Minimum drive strength, controlled by 335 // AON_IOC:IOSTRMIN (min 2 mA @3.3V with default 336 // values) 337 // AUTO Automatic drive strength, controlled by AON BATMON 338 // based on battery voltage. (min 2 mA @VDDS) 339 #define IOC_IOCFG0_IOSTR_W 2 340 #define IOC_IOCFG0_IOSTR_M 0x00000300 341 #define IOC_IOCFG0_IOSTR_S 8 342 #define IOC_IOCFG0_IOSTR_MAX 0x00000300 343 #define IOC_IOCFG0_IOSTR_MED 0x00000200 344 #define IOC_IOCFG0_IOSTR_MIN 0x00000100 345 #define IOC_IOCFG0_IOSTR_AUTO 0x00000000 346 347 // Field: [7] IOEV_RTC_EN 348 // 349 // Event asserted by this IO when edge detection is enabled 350 // 351 // 0: Input edge detection does not assert RTC event 352 // 1: Input edge detection asserts RTC event 353 #define IOC_IOCFG0_IOEV_RTC_EN 0x00000080 354 #define IOC_IOCFG0_IOEV_RTC_EN_BITN 7 355 #define IOC_IOCFG0_IOEV_RTC_EN_M 0x00000080 356 #define IOC_IOCFG0_IOEV_RTC_EN_S 7 357 358 // Field: [6] IOEV_MCU_WU_EN 359 // 360 // Event asserted by this IO when edge detection is enabled 361 // 362 // 0: Input edge detection does not assert MCU_WU event 363 // 1: Input edge detection asserts MCU_WU event 364 #define IOC_IOCFG0_IOEV_MCU_WU_EN 0x00000040 365 #define IOC_IOCFG0_IOEV_MCU_WU_EN_BITN 6 366 #define IOC_IOCFG0_IOEV_MCU_WU_EN_M 0x00000040 367 #define IOC_IOCFG0_IOEV_MCU_WU_EN_S 6 368 369 // Field: [5:0] PORT_ID 370 // 371 // Selects usage for DIO0 372 // Note: This field should not be written other than the times when PORT_ID 373 // value is specifically required to change. 374 // ENUMs: 375 // RFC_SMI_CL_IN RF Core SMI Command Link In 376 // RFC_SMI_CL_OUT RF Core SMI Command Link Out 377 // RFC_SMI_DL_IN RF Core SMI Data Link In 378 // RFC_SMI_DL_OUT RF Core SMI Data Link Out 379 // RFC_GPI1 RF Core Data In 1 380 // RFC_GPI0 RF Core Data In 0 381 // RFC_GPO3 RF Core Data Out 3 382 // RFC_GPO2 RF Core Data Out 2 383 // RFC_GPO1 RF Core Data Out 1 384 // RFC_GPO0 RF Core Data Out 0 385 // RFC_TRC RF Core Trace 386 // I2S_MCLK I2S MCLK 387 // I2S_BCLK I2S BCLK 388 // I2S_WCLK I2S WCLK 389 // I2S_AD1 I2S Data 1 390 // I2S_AD0 I2S Data 0 391 // SSI1_CLK SSI1 CLK 392 // SSI1_FSS SSI1 FSS 393 // SSI1_TX SSI1 TX 394 // SSI1_RX SSI1 RX 395 // CPU_SWV CPU SWV 396 // PORT_EVENT7 PORT EVENT 7 397 // Can be used as a general 398 // purpose IO event by selecting it through 399 // registers in the EVENT module, for example 400 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 401 // and so on 402 // PORT_EVENT6 PORT EVENT 6 403 // Can be used as a general 404 // purpose IO event by selecting it through 405 // registers in the EVENT module, for example 406 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 407 // and so on 408 // PORT_EVENT5 PORT EVENT 5 409 // Can be used as a general 410 // purpose IO event by selecting it through 411 // registers in the EVENT module, for example 412 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 413 // and so on 414 // PORT_EVENT4 PORT EVENT 4 415 // Can be used as a general 416 // purpose IO event by selecting it through 417 // registers in the EVENT module, for example 418 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 419 // and so on 420 // PORT_EVENT3 PORT EVENT 3 421 // Can be used as a general 422 // purpose IO event by selecting it through 423 // registers in the EVENT module, for example 424 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 425 // and so on 426 // PORT_EVENT2 PORT EVENT 2 427 // Can be used as a general 428 // purpose IO event by selecting it through 429 // registers in the EVENT module, for example 430 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 431 // and so on 432 // PORT_EVENT1 PORT EVENT 1 433 // Can be used as a general 434 // purpose IO event by selecting it through 435 // registers in the EVENT module, for example 436 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 437 // and so on 438 // PORT_EVENT0 PORT EVENT 0 439 // Can be used as a general 440 // purpose IO event by selecting it through 441 // registers in the EVENT module, for example 442 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 443 // and so on 444 // UART1_RTS UART1 RTS 445 // UART1_CTS UART1 CTS 446 // UART1_TX UART1 TX 447 // UART1_RX UART1 RX 448 // UART0_RTS UART0 RTS 449 // UART0_CTS UART0 CTS 450 // UART0_TX UART0 TX 451 // UART0_RX UART0 RX 452 // I2C_MSSCL I2C Clock 453 // I2C_MSSDA I2C Data 454 // SSI0_CLK SSI0 CLK 455 // SSI0_FSS SSI0 FSS 456 // SSI0_TX SSI0 TX 457 // SSI0_RX SSI0 RX 458 // AUX_IO AUX IO 459 // AON_CLK32K AON 32 KHz clock (SCLK_LF) 460 // GPIO General Purpose IO 461 #define IOC_IOCFG0_PORT_ID_W 6 462 #define IOC_IOCFG0_PORT_ID_M 0x0000003F 463 #define IOC_IOCFG0_PORT_ID_S 0 464 #define IOC_IOCFG0_PORT_ID_RFC_SMI_CL_IN 0x00000038 465 #define IOC_IOCFG0_PORT_ID_RFC_SMI_CL_OUT 0x00000037 466 #define IOC_IOCFG0_PORT_ID_RFC_SMI_DL_IN 0x00000036 467 #define IOC_IOCFG0_PORT_ID_RFC_SMI_DL_OUT 0x00000035 468 #define IOC_IOCFG0_PORT_ID_RFC_GPI1 0x00000034 469 #define IOC_IOCFG0_PORT_ID_RFC_GPI0 0x00000033 470 #define IOC_IOCFG0_PORT_ID_RFC_GPO3 0x00000032 471 #define IOC_IOCFG0_PORT_ID_RFC_GPO2 0x00000031 472 #define IOC_IOCFG0_PORT_ID_RFC_GPO1 0x00000030 473 #define IOC_IOCFG0_PORT_ID_RFC_GPO0 0x0000002F 474 #define IOC_IOCFG0_PORT_ID_RFC_TRC 0x0000002E 475 #define IOC_IOCFG0_PORT_ID_I2S_MCLK 0x00000029 476 #define IOC_IOCFG0_PORT_ID_I2S_BCLK 0x00000028 477 #define IOC_IOCFG0_PORT_ID_I2S_WCLK 0x00000027 478 #define IOC_IOCFG0_PORT_ID_I2S_AD1 0x00000026 479 #define IOC_IOCFG0_PORT_ID_I2S_AD0 0x00000025 480 #define IOC_IOCFG0_PORT_ID_SSI1_CLK 0x00000024 481 #define IOC_IOCFG0_PORT_ID_SSI1_FSS 0x00000023 482 #define IOC_IOCFG0_PORT_ID_SSI1_TX 0x00000022 483 #define IOC_IOCFG0_PORT_ID_SSI1_RX 0x00000021 484 #define IOC_IOCFG0_PORT_ID_CPU_SWV 0x00000020 485 #define IOC_IOCFG0_PORT_ID_PORT_EVENT7 0x0000001E 486 #define IOC_IOCFG0_PORT_ID_PORT_EVENT6 0x0000001D 487 #define IOC_IOCFG0_PORT_ID_PORT_EVENT5 0x0000001C 488 #define IOC_IOCFG0_PORT_ID_PORT_EVENT4 0x0000001B 489 #define IOC_IOCFG0_PORT_ID_PORT_EVENT3 0x0000001A 490 #define IOC_IOCFG0_PORT_ID_PORT_EVENT2 0x00000019 491 #define IOC_IOCFG0_PORT_ID_PORT_EVENT1 0x00000018 492 #define IOC_IOCFG0_PORT_ID_PORT_EVENT0 0x00000017 493 #define IOC_IOCFG0_PORT_ID_UART1_RTS 0x00000016 494 #define IOC_IOCFG0_PORT_ID_UART1_CTS 0x00000015 495 #define IOC_IOCFG0_PORT_ID_UART1_TX 0x00000014 496 #define IOC_IOCFG0_PORT_ID_UART1_RX 0x00000013 497 #define IOC_IOCFG0_PORT_ID_UART0_RTS 0x00000012 498 #define IOC_IOCFG0_PORT_ID_UART0_CTS 0x00000011 499 #define IOC_IOCFG0_PORT_ID_UART0_TX 0x00000010 500 #define IOC_IOCFG0_PORT_ID_UART0_RX 0x0000000F 501 #define IOC_IOCFG0_PORT_ID_I2C_MSSCL 0x0000000E 502 #define IOC_IOCFG0_PORT_ID_I2C_MSSDA 0x0000000D 503 #define IOC_IOCFG0_PORT_ID_SSI0_CLK 0x0000000C 504 #define IOC_IOCFG0_PORT_ID_SSI0_FSS 0x0000000B 505 #define IOC_IOCFG0_PORT_ID_SSI0_TX 0x0000000A 506 #define IOC_IOCFG0_PORT_ID_SSI0_RX 0x00000009 507 #define IOC_IOCFG0_PORT_ID_AUX_IO 0x00000008 508 #define IOC_IOCFG0_PORT_ID_AON_CLK32K 0x00000007 509 #define IOC_IOCFG0_PORT_ID_GPIO 0x00000000 510 511 //***************************************************************************** 512 // 513 // Register: IOC_O_IOCFG1 514 // 515 //***************************************************************************** 516 // Field: [30] HYST_EN 517 // 518 // 0: Input hysteresis disable 519 // 1: Input hysteresis enable 520 #define IOC_IOCFG1_HYST_EN 0x40000000 521 #define IOC_IOCFG1_HYST_EN_BITN 30 522 #define IOC_IOCFG1_HYST_EN_M 0x40000000 523 #define IOC_IOCFG1_HYST_EN_S 30 524 525 // Field: [29] IE 526 // 527 // 0: Input disabled 528 // 1: Input enabled 529 // 530 // Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be 531 // ignored. 532 #define IOC_IOCFG1_IE 0x20000000 533 #define IOC_IOCFG1_IE_BITN 29 534 #define IOC_IOCFG1_IE_M 0x20000000 535 #define IOC_IOCFG1_IE_S 29 536 537 // Field: [28:27] WU_CFG 538 // 539 // If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or 540 // >0x08: 541 // 542 // 00: No wake-up 543 // 01: No wake-up 544 // 10: Wakes up from shutdown if this pad is going low. 545 // 11: Wakes up from shutdown if this pad is going high. 546 // 547 // If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, 548 // this register only sets wakeup enable or not. 549 // 550 // 00, 01: Wakeup disabled 551 // 10, 11: Wakeup enabled 552 // 553 // Polarity is controlled from AON registers. 554 // 555 // Note:When the MSB is set, the IOC will deactivate the output enable for the 556 // DIO. 557 #define IOC_IOCFG1_WU_CFG_W 2 558 #define IOC_IOCFG1_WU_CFG_M 0x18000000 559 #define IOC_IOCFG1_WU_CFG_S 27 560 561 // Field: [26:24] IOMODE 562 // 563 // IO Mode 564 // Not applicable for IO configured for AON periph. signals and AUX PORT_ID 565 // 0x01-0x08 566 // AUX has its own open_source/drain configuration. 567 // 568 // 0x2: Reserved. Undefined behavior. 569 // 0x3: Reserved. Undefined behavior. 570 // ENUMs: 571 // OPENSRC_INV Open Source 572 // Inverted input / output 573 // OPENSRC Open Source 574 // Normal input / output 575 // OPENDR_INV Open Drain 576 // Inverted input / output 577 // OPENDR Open Drain, 578 // Normal input / output 579 // INV Inverted input / ouput 580 // NORMAL Normal input / output 581 #define IOC_IOCFG1_IOMODE_W 3 582 #define IOC_IOCFG1_IOMODE_M 0x07000000 583 #define IOC_IOCFG1_IOMODE_S 24 584 #define IOC_IOCFG1_IOMODE_OPENSRC_INV 0x07000000 585 #define IOC_IOCFG1_IOMODE_OPENSRC 0x06000000 586 #define IOC_IOCFG1_IOMODE_OPENDR_INV 0x05000000 587 #define IOC_IOCFG1_IOMODE_OPENDR 0x04000000 588 #define IOC_IOCFG1_IOMODE_INV 0x01000000 589 #define IOC_IOCFG1_IOMODE_NORMAL 0x00000000 590 591 // Field: [23] IOEV_AON_PROG2_EN 592 // 593 // Event asserted by this IO when edge detection is enabled 594 // 595 // 0: Input edge detection does not assert AON_PROG2 event 596 // 1: Input edge detection asserts AON_PROG2 event 597 #define IOC_IOCFG1_IOEV_AON_PROG2_EN 0x00800000 598 #define IOC_IOCFG1_IOEV_AON_PROG2_EN_BITN 23 599 #define IOC_IOCFG1_IOEV_AON_PROG2_EN_M 0x00800000 600 #define IOC_IOCFG1_IOEV_AON_PROG2_EN_S 23 601 602 // Field: [22] IOEV_AON_PROG1_EN 603 // 604 // Event asserted by this IO when edge detection is enabled 605 // 606 // 0: Input edge detection does not assert AON_PROG1 event 607 // 1: Input edge detection asserts AON_PROG1 event 608 #define IOC_IOCFG1_IOEV_AON_PROG1_EN 0x00400000 609 #define IOC_IOCFG1_IOEV_AON_PROG1_EN_BITN 22 610 #define IOC_IOCFG1_IOEV_AON_PROG1_EN_M 0x00400000 611 #define IOC_IOCFG1_IOEV_AON_PROG1_EN_S 22 612 613 // Field: [21] IOEV_AON_PROG0_EN 614 // 615 // Event asserted by this IO when edge detection is enabled 616 // 617 // 0: Input edge detection does not assert AON_PROG0 event 618 // 1: Input edge detection asserts AON_PROG0 event 619 #define IOC_IOCFG1_IOEV_AON_PROG0_EN 0x00200000 620 #define IOC_IOCFG1_IOEV_AON_PROG0_EN_BITN 21 621 #define IOC_IOCFG1_IOEV_AON_PROG0_EN_M 0x00200000 622 #define IOC_IOCFG1_IOEV_AON_PROG0_EN_S 21 623 624 // Field: [18] EDGE_IRQ_EN 625 // 626 // 0: No interrupt generation 627 // 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is 628 // enabled) 629 #define IOC_IOCFG1_EDGE_IRQ_EN 0x00040000 630 #define IOC_IOCFG1_EDGE_IRQ_EN_BITN 18 631 #define IOC_IOCFG1_EDGE_IRQ_EN_M 0x00040000 632 #define IOC_IOCFG1_EDGE_IRQ_EN_S 18 633 634 // Field: [17:16] EDGE_DET 635 // 636 // Enable generation of edge detection events on this IO 637 // ENUMs: 638 // BOTH Positive and negative edge detection 639 // POS Positive edge detection 640 // NEG Negative edge detection 641 // NONE No edge detection 642 #define IOC_IOCFG1_EDGE_DET_W 2 643 #define IOC_IOCFG1_EDGE_DET_M 0x00030000 644 #define IOC_IOCFG1_EDGE_DET_S 16 645 #define IOC_IOCFG1_EDGE_DET_BOTH 0x00030000 646 #define IOC_IOCFG1_EDGE_DET_POS 0x00020000 647 #define IOC_IOCFG1_EDGE_DET_NEG 0x00010000 648 #define IOC_IOCFG1_EDGE_DET_NONE 0x00000000 649 650 // Field: [14:13] PULL_CTL 651 // 652 // Pull control 653 // ENUMs: 654 // DIS No pull 655 // UP Pull up 656 // DWN Pull down 657 #define IOC_IOCFG1_PULL_CTL_W 2 658 #define IOC_IOCFG1_PULL_CTL_M 0x00006000 659 #define IOC_IOCFG1_PULL_CTL_S 13 660 #define IOC_IOCFG1_PULL_CTL_DIS 0x00006000 661 #define IOC_IOCFG1_PULL_CTL_UP 0x00004000 662 #define IOC_IOCFG1_PULL_CTL_DWN 0x00002000 663 664 // Field: [12] SLEW_RED 665 // 666 // 0: Normal slew rate 667 // 1: Enables reduced slew rate in output driver. 668 #define IOC_IOCFG1_SLEW_RED 0x00001000 669 #define IOC_IOCFG1_SLEW_RED_BITN 12 670 #define IOC_IOCFG1_SLEW_RED_M 0x00001000 671 #define IOC_IOCFG1_SLEW_RED_S 12 672 673 // Field: [11:10] IOCURR 674 // 675 // Selects IO current mode of this IO. 676 // ENUMs: 677 // 4_8MA Extended-Current (EC) mode: Min 8 mA for double 678 // drive strength IOs (min 4 mA for normal IOs) 679 // when IOSTR is set to AUTO 680 // 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set 681 // to AUTO 682 // 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set 683 // to AUTO 684 #define IOC_IOCFG1_IOCURR_W 2 685 #define IOC_IOCFG1_IOCURR_M 0x00000C00 686 #define IOC_IOCFG1_IOCURR_S 10 687 #define IOC_IOCFG1_IOCURR_4_8MA 0x00000800 688 #define IOC_IOCFG1_IOCURR_4MA 0x00000400 689 #define IOC_IOCFG1_IOCURR_2MA 0x00000000 690 691 // Field: [9:8] IOSTR 692 // 693 // Select source for drive strength control of this IO. 694 // This setting controls the drive strength of the Low-Current (LC) mode. 695 // Higher drive strength can be selected in IOCURR 696 // ENUMs: 697 // MAX Maximum drive strength, controlled by 698 // AON_IOC:IOSTRMAX (min 2 mA @1.8V with default 699 // values) 700 // MED Medium drive strength, controlled by 701 // AON_IOC:IOSTRMED (min 2 mA @2.5V with default 702 // values) 703 // MIN Minimum drive strength, controlled by 704 // AON_IOC:IOSTRMIN (min 2 mA @3.3V with default 705 // values) 706 // AUTO Automatic drive strength, controlled by AON BATMON 707 // based on battery voltage. (min 2 mA @VDDS) 708 #define IOC_IOCFG1_IOSTR_W 2 709 #define IOC_IOCFG1_IOSTR_M 0x00000300 710 #define IOC_IOCFG1_IOSTR_S 8 711 #define IOC_IOCFG1_IOSTR_MAX 0x00000300 712 #define IOC_IOCFG1_IOSTR_MED 0x00000200 713 #define IOC_IOCFG1_IOSTR_MIN 0x00000100 714 #define IOC_IOCFG1_IOSTR_AUTO 0x00000000 715 716 // Field: [7] IOEV_RTC_EN 717 // 718 // Event asserted by this IO when edge detection is enabled 719 // 720 // 0: Input edge detection does not assert RTC event 721 // 1: Input edge detection asserts RTC event 722 #define IOC_IOCFG1_IOEV_RTC_EN 0x00000080 723 #define IOC_IOCFG1_IOEV_RTC_EN_BITN 7 724 #define IOC_IOCFG1_IOEV_RTC_EN_M 0x00000080 725 #define IOC_IOCFG1_IOEV_RTC_EN_S 7 726 727 // Field: [6] IOEV_MCU_WU_EN 728 // 729 // Event asserted by this IO when edge detection is enabled 730 // 731 // 0: Input edge detection does not assert MCU_WU event 732 // 1: Input edge detection asserts MCU_WU event 733 #define IOC_IOCFG1_IOEV_MCU_WU_EN 0x00000040 734 #define IOC_IOCFG1_IOEV_MCU_WU_EN_BITN 6 735 #define IOC_IOCFG1_IOEV_MCU_WU_EN_M 0x00000040 736 #define IOC_IOCFG1_IOEV_MCU_WU_EN_S 6 737 738 // Field: [5:0] PORT_ID 739 // 740 // Selects usage for DIO1 741 // Note: This field should not be written other than the times when PORT_ID 742 // value is specifically required to change. 743 // ENUMs: 744 // RFC_SMI_CL_IN RF Core SMI Command Link In 745 // RFC_SMI_CL_OUT RF Core SMI Command Link Out 746 // RFC_SMI_DL_IN RF Core SMI Data Link In 747 // RFC_SMI_DL_OUT RF Core SMI Data Link Out 748 // RFC_GPI1 RF Core Data In 1 749 // RFC_GPI0 RF Core Data In 0 750 // RFC_GPO3 RF Core Data Out 3 751 // RFC_GPO2 RF Core Data Out 2 752 // RFC_GPO1 RF Core Data Out 1 753 // RFC_GPO0 RF Core Data Out 0 754 // RFC_TRC RF Core Trace 755 // I2S_MCLK I2S MCLK 756 // I2S_BCLK I2S BCLK 757 // I2S_WCLK I2S WCLK 758 // I2S_AD1 I2S Data 1 759 // I2S_AD0 I2S Data 0 760 // SSI1_CLK SSI1 CLK 761 // SSI1_FSS SSI1 FSS 762 // SSI1_TX SSI1 TX 763 // SSI1_RX SSI1 RX 764 // CPU_SWV CPU SWV 765 // PORT_EVENT7 PORT EVENT 7 766 // Can be used as a general 767 // purpose IO event by selecting it through 768 // registers in the EVENT module, for example 769 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 770 // and so on 771 // PORT_EVENT6 PORT EVENT 6 772 // Can be used as a general 773 // purpose IO event by selecting it through 774 // registers in the EVENT module, for example 775 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 776 // and so on 777 // PORT_EVENT5 PORT EVENT 5 778 // Can be used as a general 779 // purpose IO event by selecting it through 780 // registers in the EVENT module, for example 781 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 782 // and so on 783 // PORT_EVENT4 PORT EVENT 4 784 // Can be used as a general 785 // purpose IO event by selecting it through 786 // registers in the EVENT module, for example 787 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 788 // and so on 789 // PORT_EVENT3 PORT EVENT 3 790 // Can be used as a general 791 // purpose IO event by selecting it through 792 // registers in the EVENT module, for example 793 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 794 // and so on 795 // PORT_EVENT2 PORT EVENT 2 796 // Can be used as a general 797 // purpose IO event by selecting it through 798 // registers in the EVENT module, for example 799 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 800 // and so on 801 // PORT_EVENT1 PORT EVENT 1 802 // Can be used as a general 803 // purpose IO event by selecting it through 804 // registers in the EVENT module, for example 805 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 806 // and so on 807 // PORT_EVENT0 PORT EVENT 0 808 // Can be used as a general 809 // purpose IO event by selecting it through 810 // registers in the EVENT module, for example 811 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 812 // and so on 813 // UART1_RTS UART1 RTS 814 // UART1_CTS UART1 CTS 815 // UART1_TX UART1 TX 816 // UART1_RX UART1 RX 817 // UART0_RTS UART0 RTS 818 // UART0_CTS UART0 CTS 819 // UART0_TX UART0 TX 820 // UART0_RX UART0 RX 821 // I2C_MSSCL I2C Clock 822 // I2C_MSSDA I2C Data 823 // SSI0_CLK SSI0 CLK 824 // SSI0_FSS SSI0 FSS 825 // SSI0_TX SSI0 TX 826 // SSI0_RX SSI0 RX 827 // AUX_IO AUX IO 828 // AON_CLK32K AON 32 KHz clock (SCLK_LF) 829 // GPIO General Purpose IO 830 #define IOC_IOCFG1_PORT_ID_W 6 831 #define IOC_IOCFG1_PORT_ID_M 0x0000003F 832 #define IOC_IOCFG1_PORT_ID_S 0 833 #define IOC_IOCFG1_PORT_ID_RFC_SMI_CL_IN 0x00000038 834 #define IOC_IOCFG1_PORT_ID_RFC_SMI_CL_OUT 0x00000037 835 #define IOC_IOCFG1_PORT_ID_RFC_SMI_DL_IN 0x00000036 836 #define IOC_IOCFG1_PORT_ID_RFC_SMI_DL_OUT 0x00000035 837 #define IOC_IOCFG1_PORT_ID_RFC_GPI1 0x00000034 838 #define IOC_IOCFG1_PORT_ID_RFC_GPI0 0x00000033 839 #define IOC_IOCFG1_PORT_ID_RFC_GPO3 0x00000032 840 #define IOC_IOCFG1_PORT_ID_RFC_GPO2 0x00000031 841 #define IOC_IOCFG1_PORT_ID_RFC_GPO1 0x00000030 842 #define IOC_IOCFG1_PORT_ID_RFC_GPO0 0x0000002F 843 #define IOC_IOCFG1_PORT_ID_RFC_TRC 0x0000002E 844 #define IOC_IOCFG1_PORT_ID_I2S_MCLK 0x00000029 845 #define IOC_IOCFG1_PORT_ID_I2S_BCLK 0x00000028 846 #define IOC_IOCFG1_PORT_ID_I2S_WCLK 0x00000027 847 #define IOC_IOCFG1_PORT_ID_I2S_AD1 0x00000026 848 #define IOC_IOCFG1_PORT_ID_I2S_AD0 0x00000025 849 #define IOC_IOCFG1_PORT_ID_SSI1_CLK 0x00000024 850 #define IOC_IOCFG1_PORT_ID_SSI1_FSS 0x00000023 851 #define IOC_IOCFG1_PORT_ID_SSI1_TX 0x00000022 852 #define IOC_IOCFG1_PORT_ID_SSI1_RX 0x00000021 853 #define IOC_IOCFG1_PORT_ID_CPU_SWV 0x00000020 854 #define IOC_IOCFG1_PORT_ID_PORT_EVENT7 0x0000001E 855 #define IOC_IOCFG1_PORT_ID_PORT_EVENT6 0x0000001D 856 #define IOC_IOCFG1_PORT_ID_PORT_EVENT5 0x0000001C 857 #define IOC_IOCFG1_PORT_ID_PORT_EVENT4 0x0000001B 858 #define IOC_IOCFG1_PORT_ID_PORT_EVENT3 0x0000001A 859 #define IOC_IOCFG1_PORT_ID_PORT_EVENT2 0x00000019 860 #define IOC_IOCFG1_PORT_ID_PORT_EVENT1 0x00000018 861 #define IOC_IOCFG1_PORT_ID_PORT_EVENT0 0x00000017 862 #define IOC_IOCFG1_PORT_ID_UART1_RTS 0x00000016 863 #define IOC_IOCFG1_PORT_ID_UART1_CTS 0x00000015 864 #define IOC_IOCFG1_PORT_ID_UART1_TX 0x00000014 865 #define IOC_IOCFG1_PORT_ID_UART1_RX 0x00000013 866 #define IOC_IOCFG1_PORT_ID_UART0_RTS 0x00000012 867 #define IOC_IOCFG1_PORT_ID_UART0_CTS 0x00000011 868 #define IOC_IOCFG1_PORT_ID_UART0_TX 0x00000010 869 #define IOC_IOCFG1_PORT_ID_UART0_RX 0x0000000F 870 #define IOC_IOCFG1_PORT_ID_I2C_MSSCL 0x0000000E 871 #define IOC_IOCFG1_PORT_ID_I2C_MSSDA 0x0000000D 872 #define IOC_IOCFG1_PORT_ID_SSI0_CLK 0x0000000C 873 #define IOC_IOCFG1_PORT_ID_SSI0_FSS 0x0000000B 874 #define IOC_IOCFG1_PORT_ID_SSI0_TX 0x0000000A 875 #define IOC_IOCFG1_PORT_ID_SSI0_RX 0x00000009 876 #define IOC_IOCFG1_PORT_ID_AUX_IO 0x00000008 877 #define IOC_IOCFG1_PORT_ID_AON_CLK32K 0x00000007 878 #define IOC_IOCFG1_PORT_ID_GPIO 0x00000000 879 880 //***************************************************************************** 881 // 882 // Register: IOC_O_IOCFG2 883 // 884 //***************************************************************************** 885 // Field: [30] HYST_EN 886 // 887 // 0: Input hysteresis disable 888 // 1: Input hysteresis enable 889 #define IOC_IOCFG2_HYST_EN 0x40000000 890 #define IOC_IOCFG2_HYST_EN_BITN 30 891 #define IOC_IOCFG2_HYST_EN_M 0x40000000 892 #define IOC_IOCFG2_HYST_EN_S 30 893 894 // Field: [29] IE 895 // 896 // 0: Input disabled 897 // 1: Input enabled 898 // 899 // Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be 900 // ignored. 901 #define IOC_IOCFG2_IE 0x20000000 902 #define IOC_IOCFG2_IE_BITN 29 903 #define IOC_IOCFG2_IE_M 0x20000000 904 #define IOC_IOCFG2_IE_S 29 905 906 // Field: [28:27] WU_CFG 907 // 908 // If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or 909 // >0x08: 910 // 911 // 00: No wake-up 912 // 01: No wake-up 913 // 10: Wakes up from shutdown if this pad is going low. 914 // 11: Wakes up from shutdown if this pad is going high. 915 // 916 // If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, 917 // this register only sets wakeup enable or not. 918 // 919 // 00, 01: Wakeup disabled 920 // 10, 11: Wakeup enabled 921 // 922 // Polarity is controlled from AON registers. 923 // 924 // Note:When the MSB is set, the IOC will deactivate the output enable for the 925 // DIO. 926 #define IOC_IOCFG2_WU_CFG_W 2 927 #define IOC_IOCFG2_WU_CFG_M 0x18000000 928 #define IOC_IOCFG2_WU_CFG_S 27 929 930 // Field: [26:24] IOMODE 931 // 932 // IO Mode 933 // Not applicable for IO configured for AON periph. signals and AUX PORT_ID 934 // 0x01-0x08 935 // AUX has its own open_source/drain configuration. 936 // 937 // 0x2: Reserved. Undefined behavior. 938 // 0x3: Reserved. Undefined behavior. 939 // ENUMs: 940 // OPENSRC_INV Open Source 941 // Inverted input / output 942 // OPENSRC Open Source 943 // Normal input / output 944 // OPENDR_INV Open Drain 945 // Inverted input / output 946 // OPENDR Open Drain, 947 // Normal input / output 948 // INV Inverted input / ouput 949 // NORMAL Normal input / output 950 #define IOC_IOCFG2_IOMODE_W 3 951 #define IOC_IOCFG2_IOMODE_M 0x07000000 952 #define IOC_IOCFG2_IOMODE_S 24 953 #define IOC_IOCFG2_IOMODE_OPENSRC_INV 0x07000000 954 #define IOC_IOCFG2_IOMODE_OPENSRC 0x06000000 955 #define IOC_IOCFG2_IOMODE_OPENDR_INV 0x05000000 956 #define IOC_IOCFG2_IOMODE_OPENDR 0x04000000 957 #define IOC_IOCFG2_IOMODE_INV 0x01000000 958 #define IOC_IOCFG2_IOMODE_NORMAL 0x00000000 959 960 // Field: [23] IOEV_AON_PROG2_EN 961 // 962 // Event asserted by this IO when edge detection is enabled 963 // 964 // 0: Input edge detection does not assert AON_PROG2 event 965 // 1: Input edge detection asserts AON_PROG2 event 966 #define IOC_IOCFG2_IOEV_AON_PROG2_EN 0x00800000 967 #define IOC_IOCFG2_IOEV_AON_PROG2_EN_BITN 23 968 #define IOC_IOCFG2_IOEV_AON_PROG2_EN_M 0x00800000 969 #define IOC_IOCFG2_IOEV_AON_PROG2_EN_S 23 970 971 // Field: [22] IOEV_AON_PROG1_EN 972 // 973 // Event asserted by this IO when edge detection is enabled 974 // 975 // 0: Input edge detection does not assert AON_PROG1 event 976 // 1: Input edge detection asserts AON_PROG1 event 977 #define IOC_IOCFG2_IOEV_AON_PROG1_EN 0x00400000 978 #define IOC_IOCFG2_IOEV_AON_PROG1_EN_BITN 22 979 #define IOC_IOCFG2_IOEV_AON_PROG1_EN_M 0x00400000 980 #define IOC_IOCFG2_IOEV_AON_PROG1_EN_S 22 981 982 // Field: [21] IOEV_AON_PROG0_EN 983 // 984 // Event asserted by this IO when edge detection is enabled 985 // 986 // 0: Input edge detection does not assert AON_PROG0 event 987 // 1: Input edge detection asserts AON_PROG0 event 988 #define IOC_IOCFG2_IOEV_AON_PROG0_EN 0x00200000 989 #define IOC_IOCFG2_IOEV_AON_PROG0_EN_BITN 21 990 #define IOC_IOCFG2_IOEV_AON_PROG0_EN_M 0x00200000 991 #define IOC_IOCFG2_IOEV_AON_PROG0_EN_S 21 992 993 // Field: [18] EDGE_IRQ_EN 994 // 995 // 0: No interrupt generation 996 // 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is 997 // enabled) 998 #define IOC_IOCFG2_EDGE_IRQ_EN 0x00040000 999 #define IOC_IOCFG2_EDGE_IRQ_EN_BITN 18 1000 #define IOC_IOCFG2_EDGE_IRQ_EN_M 0x00040000 1001 #define IOC_IOCFG2_EDGE_IRQ_EN_S 18 1002 1003 // Field: [17:16] EDGE_DET 1004 // 1005 // Enable generation of edge detection events on this IO 1006 // ENUMs: 1007 // BOTH Positive and negative edge detection 1008 // POS Positive edge detection 1009 // NEG Negative edge detection 1010 // NONE No edge detection 1011 #define IOC_IOCFG2_EDGE_DET_W 2 1012 #define IOC_IOCFG2_EDGE_DET_M 0x00030000 1013 #define IOC_IOCFG2_EDGE_DET_S 16 1014 #define IOC_IOCFG2_EDGE_DET_BOTH 0x00030000 1015 #define IOC_IOCFG2_EDGE_DET_POS 0x00020000 1016 #define IOC_IOCFG2_EDGE_DET_NEG 0x00010000 1017 #define IOC_IOCFG2_EDGE_DET_NONE 0x00000000 1018 1019 // Field: [14:13] PULL_CTL 1020 // 1021 // Pull control 1022 // ENUMs: 1023 // DIS No pull 1024 // UP Pull up 1025 // DWN Pull down 1026 #define IOC_IOCFG2_PULL_CTL_W 2 1027 #define IOC_IOCFG2_PULL_CTL_M 0x00006000 1028 #define IOC_IOCFG2_PULL_CTL_S 13 1029 #define IOC_IOCFG2_PULL_CTL_DIS 0x00006000 1030 #define IOC_IOCFG2_PULL_CTL_UP 0x00004000 1031 #define IOC_IOCFG2_PULL_CTL_DWN 0x00002000 1032 1033 // Field: [12] SLEW_RED 1034 // 1035 // 0: Normal slew rate 1036 // 1: Enables reduced slew rate in output driver. 1037 #define IOC_IOCFG2_SLEW_RED 0x00001000 1038 #define IOC_IOCFG2_SLEW_RED_BITN 12 1039 #define IOC_IOCFG2_SLEW_RED_M 0x00001000 1040 #define IOC_IOCFG2_SLEW_RED_S 12 1041 1042 // Field: [11:10] IOCURR 1043 // 1044 // Selects IO current mode of this IO. 1045 // ENUMs: 1046 // 4_8MA Extended-Current (EC) mode: Min 8 mA for double 1047 // drive strength IOs (min 4 mA for normal IOs) 1048 // when IOSTR is set to AUTO 1049 // 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set 1050 // to AUTO 1051 // 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set 1052 // to AUTO 1053 #define IOC_IOCFG2_IOCURR_W 2 1054 #define IOC_IOCFG2_IOCURR_M 0x00000C00 1055 #define IOC_IOCFG2_IOCURR_S 10 1056 #define IOC_IOCFG2_IOCURR_4_8MA 0x00000800 1057 #define IOC_IOCFG2_IOCURR_4MA 0x00000400 1058 #define IOC_IOCFG2_IOCURR_2MA 0x00000000 1059 1060 // Field: [9:8] IOSTR 1061 // 1062 // Select source for drive strength control of this IO. 1063 // This setting controls the drive strength of the Low-Current (LC) mode. 1064 // Higher drive strength can be selected in IOCURR 1065 // ENUMs: 1066 // MAX Maximum drive strength, controlled by 1067 // AON_IOC:IOSTRMAX (min 2 mA @1.8V with default 1068 // values) 1069 // MED Medium drive strength, controlled by 1070 // AON_IOC:IOSTRMED (min 2 mA @2.5V with default 1071 // values) 1072 // MIN Minimum drive strength, controlled by 1073 // AON_IOC:IOSTRMIN (min 2 mA @3.3V with default 1074 // values) 1075 // AUTO Automatic drive strength, controlled by AON BATMON 1076 // based on battery voltage. (min 2 mA @VDDS) 1077 #define IOC_IOCFG2_IOSTR_W 2 1078 #define IOC_IOCFG2_IOSTR_M 0x00000300 1079 #define IOC_IOCFG2_IOSTR_S 8 1080 #define IOC_IOCFG2_IOSTR_MAX 0x00000300 1081 #define IOC_IOCFG2_IOSTR_MED 0x00000200 1082 #define IOC_IOCFG2_IOSTR_MIN 0x00000100 1083 #define IOC_IOCFG2_IOSTR_AUTO 0x00000000 1084 1085 // Field: [7] IOEV_RTC_EN 1086 // 1087 // Event asserted by this IO when edge detection is enabled 1088 // 1089 // 0: Input edge detection does not assert RTC event 1090 // 1: Input edge detection asserts RTC event 1091 #define IOC_IOCFG2_IOEV_RTC_EN 0x00000080 1092 #define IOC_IOCFG2_IOEV_RTC_EN_BITN 7 1093 #define IOC_IOCFG2_IOEV_RTC_EN_M 0x00000080 1094 #define IOC_IOCFG2_IOEV_RTC_EN_S 7 1095 1096 // Field: [6] IOEV_MCU_WU_EN 1097 // 1098 // Event asserted by this IO when edge detection is enabled 1099 // 1100 // 0: Input edge detection does not assert MCU_WU event 1101 // 1: Input edge detection asserts MCU_WU event 1102 #define IOC_IOCFG2_IOEV_MCU_WU_EN 0x00000040 1103 #define IOC_IOCFG2_IOEV_MCU_WU_EN_BITN 6 1104 #define IOC_IOCFG2_IOEV_MCU_WU_EN_M 0x00000040 1105 #define IOC_IOCFG2_IOEV_MCU_WU_EN_S 6 1106 1107 // Field: [5:0] PORT_ID 1108 // 1109 // Selects usage for DIO2 1110 // Note: This field should not be written other than the times when PORT_ID 1111 // value is specifically required to change. 1112 // ENUMs: 1113 // RFC_SMI_CL_IN RF Core SMI Command Link In 1114 // RFC_SMI_CL_OUT RF Core SMI Command Link Out 1115 // RFC_SMI_DL_IN RF Core SMI Data Link In 1116 // RFC_SMI_DL_OUT RF Core SMI Data Link Out 1117 // RFC_GPI1 RF Core Data In 1 1118 // RFC_GPI0 RF Core Data In 0 1119 // RFC_GPO3 RF Core Data Out 3 1120 // RFC_GPO2 RF Core Data Out 2 1121 // RFC_GPO1 RF Core Data Out 1 1122 // RFC_GPO0 RF Core Data Out 0 1123 // RFC_TRC RF Core Trace 1124 // I2S_MCLK I2S MCLK 1125 // I2S_BCLK I2S BCLK 1126 // I2S_WCLK I2S WCLK 1127 // I2S_AD1 I2S Data 1 1128 // I2S_AD0 I2S Data 0 1129 // SSI1_CLK SSI1 CLK 1130 // SSI1_FSS SSI1 FSS 1131 // SSI1_TX SSI1 TX 1132 // SSI1_RX SSI1 RX 1133 // CPU_SWV CPU SWV 1134 // PORT_EVENT7 PORT EVENT 7 1135 // Can be used as a general 1136 // purpose IO event by selecting it through 1137 // registers in the EVENT module, for example 1138 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 1139 // and so on 1140 // PORT_EVENT6 PORT EVENT 6 1141 // Can be used as a general 1142 // purpose IO event by selecting it through 1143 // registers in the EVENT module, for example 1144 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 1145 // and so on 1146 // PORT_EVENT5 PORT EVENT 5 1147 // Can be used as a general 1148 // purpose IO event by selecting it through 1149 // registers in the EVENT module, for example 1150 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 1151 // and so on 1152 // PORT_EVENT4 PORT EVENT 4 1153 // Can be used as a general 1154 // purpose IO event by selecting it through 1155 // registers in the EVENT module, for example 1156 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 1157 // and so on 1158 // PORT_EVENT3 PORT EVENT 3 1159 // Can be used as a general 1160 // purpose IO event by selecting it through 1161 // registers in the EVENT module, for example 1162 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 1163 // and so on 1164 // PORT_EVENT2 PORT EVENT 2 1165 // Can be used as a general 1166 // purpose IO event by selecting it through 1167 // registers in the EVENT module, for example 1168 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 1169 // and so on 1170 // PORT_EVENT1 PORT EVENT 1 1171 // Can be used as a general 1172 // purpose IO event by selecting it through 1173 // registers in the EVENT module, for example 1174 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 1175 // and so on 1176 // PORT_EVENT0 PORT EVENT 0 1177 // Can be used as a general 1178 // purpose IO event by selecting it through 1179 // registers in the EVENT module, for example 1180 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 1181 // and so on 1182 // UART1_RTS UART1 RTS 1183 // UART1_CTS UART1 CTS 1184 // UART1_TX UART1 TX 1185 // UART1_RX UART1 RX 1186 // UART0_RTS UART0 RTS 1187 // UART0_CTS UART0 CTS 1188 // UART0_TX UART0 TX 1189 // UART0_RX UART0 RX 1190 // I2C_MSSCL I2C Clock 1191 // I2C_MSSDA I2C Data 1192 // SSI0_CLK SSI0 CLK 1193 // SSI0_FSS SSI0 FSS 1194 // SSI0_TX SSI0 TX 1195 // SSI0_RX SSI0 RX 1196 // AUX_IO AUX IO 1197 // AON_CLK32K AON 32 KHz clock (SCLK_LF) 1198 // GPIO General Purpose IO 1199 #define IOC_IOCFG2_PORT_ID_W 6 1200 #define IOC_IOCFG2_PORT_ID_M 0x0000003F 1201 #define IOC_IOCFG2_PORT_ID_S 0 1202 #define IOC_IOCFG2_PORT_ID_RFC_SMI_CL_IN 0x00000038 1203 #define IOC_IOCFG2_PORT_ID_RFC_SMI_CL_OUT 0x00000037 1204 #define IOC_IOCFG2_PORT_ID_RFC_SMI_DL_IN 0x00000036 1205 #define IOC_IOCFG2_PORT_ID_RFC_SMI_DL_OUT 0x00000035 1206 #define IOC_IOCFG2_PORT_ID_RFC_GPI1 0x00000034 1207 #define IOC_IOCFG2_PORT_ID_RFC_GPI0 0x00000033 1208 #define IOC_IOCFG2_PORT_ID_RFC_GPO3 0x00000032 1209 #define IOC_IOCFG2_PORT_ID_RFC_GPO2 0x00000031 1210 #define IOC_IOCFG2_PORT_ID_RFC_GPO1 0x00000030 1211 #define IOC_IOCFG2_PORT_ID_RFC_GPO0 0x0000002F 1212 #define IOC_IOCFG2_PORT_ID_RFC_TRC 0x0000002E 1213 #define IOC_IOCFG2_PORT_ID_I2S_MCLK 0x00000029 1214 #define IOC_IOCFG2_PORT_ID_I2S_BCLK 0x00000028 1215 #define IOC_IOCFG2_PORT_ID_I2S_WCLK 0x00000027 1216 #define IOC_IOCFG2_PORT_ID_I2S_AD1 0x00000026 1217 #define IOC_IOCFG2_PORT_ID_I2S_AD0 0x00000025 1218 #define IOC_IOCFG2_PORT_ID_SSI1_CLK 0x00000024 1219 #define IOC_IOCFG2_PORT_ID_SSI1_FSS 0x00000023 1220 #define IOC_IOCFG2_PORT_ID_SSI1_TX 0x00000022 1221 #define IOC_IOCFG2_PORT_ID_SSI1_RX 0x00000021 1222 #define IOC_IOCFG2_PORT_ID_CPU_SWV 0x00000020 1223 #define IOC_IOCFG2_PORT_ID_PORT_EVENT7 0x0000001E 1224 #define IOC_IOCFG2_PORT_ID_PORT_EVENT6 0x0000001D 1225 #define IOC_IOCFG2_PORT_ID_PORT_EVENT5 0x0000001C 1226 #define IOC_IOCFG2_PORT_ID_PORT_EVENT4 0x0000001B 1227 #define IOC_IOCFG2_PORT_ID_PORT_EVENT3 0x0000001A 1228 #define IOC_IOCFG2_PORT_ID_PORT_EVENT2 0x00000019 1229 #define IOC_IOCFG2_PORT_ID_PORT_EVENT1 0x00000018 1230 #define IOC_IOCFG2_PORT_ID_PORT_EVENT0 0x00000017 1231 #define IOC_IOCFG2_PORT_ID_UART1_RTS 0x00000016 1232 #define IOC_IOCFG2_PORT_ID_UART1_CTS 0x00000015 1233 #define IOC_IOCFG2_PORT_ID_UART1_TX 0x00000014 1234 #define IOC_IOCFG2_PORT_ID_UART1_RX 0x00000013 1235 #define IOC_IOCFG2_PORT_ID_UART0_RTS 0x00000012 1236 #define IOC_IOCFG2_PORT_ID_UART0_CTS 0x00000011 1237 #define IOC_IOCFG2_PORT_ID_UART0_TX 0x00000010 1238 #define IOC_IOCFG2_PORT_ID_UART0_RX 0x0000000F 1239 #define IOC_IOCFG2_PORT_ID_I2C_MSSCL 0x0000000E 1240 #define IOC_IOCFG2_PORT_ID_I2C_MSSDA 0x0000000D 1241 #define IOC_IOCFG2_PORT_ID_SSI0_CLK 0x0000000C 1242 #define IOC_IOCFG2_PORT_ID_SSI0_FSS 0x0000000B 1243 #define IOC_IOCFG2_PORT_ID_SSI0_TX 0x0000000A 1244 #define IOC_IOCFG2_PORT_ID_SSI0_RX 0x00000009 1245 #define IOC_IOCFG2_PORT_ID_AUX_IO 0x00000008 1246 #define IOC_IOCFG2_PORT_ID_AON_CLK32K 0x00000007 1247 #define IOC_IOCFG2_PORT_ID_GPIO 0x00000000 1248 1249 //***************************************************************************** 1250 // 1251 // Register: IOC_O_IOCFG3 1252 // 1253 //***************************************************************************** 1254 // Field: [30] HYST_EN 1255 // 1256 // 0: Input hysteresis disable 1257 // 1: Input hysteresis enable 1258 #define IOC_IOCFG3_HYST_EN 0x40000000 1259 #define IOC_IOCFG3_HYST_EN_BITN 30 1260 #define IOC_IOCFG3_HYST_EN_M 0x40000000 1261 #define IOC_IOCFG3_HYST_EN_S 30 1262 1263 // Field: [29] IE 1264 // 1265 // 0: Input disabled 1266 // 1: Input enabled 1267 // 1268 // Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be 1269 // ignored. 1270 #define IOC_IOCFG3_IE 0x20000000 1271 #define IOC_IOCFG3_IE_BITN 29 1272 #define IOC_IOCFG3_IE_M 0x20000000 1273 #define IOC_IOCFG3_IE_S 29 1274 1275 // Field: [28:27] WU_CFG 1276 // 1277 // If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or 1278 // >0x08: 1279 // 1280 // 00: No wake-up 1281 // 01: No wake-up 1282 // 10: Wakes up from shutdown if this pad is going low. 1283 // 11: Wakes up from shutdown if this pad is going high. 1284 // 1285 // If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, 1286 // this register only sets wakeup enable or not. 1287 // 1288 // 00, 01: Wakeup disabled 1289 // 10, 11: Wakeup enabled 1290 // 1291 // Polarity is controlled from AON registers. 1292 // 1293 // Note:When the MSB is set, the IOC will deactivate the output enable for the 1294 // DIO. 1295 #define IOC_IOCFG3_WU_CFG_W 2 1296 #define IOC_IOCFG3_WU_CFG_M 0x18000000 1297 #define IOC_IOCFG3_WU_CFG_S 27 1298 1299 // Field: [26:24] IOMODE 1300 // 1301 // IO Mode 1302 // Not applicable for IO configured for AON periph. signals and AUX PORT_ID 1303 // 0x01-0x08 1304 // AUX has its own open_source/drain configuration. 1305 // 1306 // 0x2: Reserved. Undefined behavior. 1307 // 0x3: Reserved. Undefined behavior. 1308 // ENUMs: 1309 // OPENSRC_INV Open Source 1310 // Inverted input / output 1311 // OPENSRC Open Source 1312 // Normal input / output 1313 // OPENDR_INV Open Drain 1314 // Inverted input / output 1315 // OPENDR Open Drain, 1316 // Normal input / output 1317 // INV Inverted input / ouput 1318 // NORMAL Normal input / output 1319 #define IOC_IOCFG3_IOMODE_W 3 1320 #define IOC_IOCFG3_IOMODE_M 0x07000000 1321 #define IOC_IOCFG3_IOMODE_S 24 1322 #define IOC_IOCFG3_IOMODE_OPENSRC_INV 0x07000000 1323 #define IOC_IOCFG3_IOMODE_OPENSRC 0x06000000 1324 #define IOC_IOCFG3_IOMODE_OPENDR_INV 0x05000000 1325 #define IOC_IOCFG3_IOMODE_OPENDR 0x04000000 1326 #define IOC_IOCFG3_IOMODE_INV 0x01000000 1327 #define IOC_IOCFG3_IOMODE_NORMAL 0x00000000 1328 1329 // Field: [23] IOEV_AON_PROG2_EN 1330 // 1331 // Event asserted by this IO when edge detection is enabled 1332 // 1333 // 0: Input edge detection does not assert AON_PROG2 event 1334 // 1: Input edge detection asserts AON_PROG2 event 1335 #define IOC_IOCFG3_IOEV_AON_PROG2_EN 0x00800000 1336 #define IOC_IOCFG3_IOEV_AON_PROG2_EN_BITN 23 1337 #define IOC_IOCFG3_IOEV_AON_PROG2_EN_M 0x00800000 1338 #define IOC_IOCFG3_IOEV_AON_PROG2_EN_S 23 1339 1340 // Field: [22] IOEV_AON_PROG1_EN 1341 // 1342 // Event asserted by this IO when edge detection is enabled 1343 // 1344 // 0: Input edge detection does not assert AON_PROG1 event 1345 // 1: Input edge detection asserts AON_PROG1 event 1346 #define IOC_IOCFG3_IOEV_AON_PROG1_EN 0x00400000 1347 #define IOC_IOCFG3_IOEV_AON_PROG1_EN_BITN 22 1348 #define IOC_IOCFG3_IOEV_AON_PROG1_EN_M 0x00400000 1349 #define IOC_IOCFG3_IOEV_AON_PROG1_EN_S 22 1350 1351 // Field: [21] IOEV_AON_PROG0_EN 1352 // 1353 // Event asserted by this IO when edge detection is enabled 1354 // 1355 // 0: Input edge detection does not assert AON_PROG0 event 1356 // 1: Input edge detection asserts AON_PROG0 event 1357 #define IOC_IOCFG3_IOEV_AON_PROG0_EN 0x00200000 1358 #define IOC_IOCFG3_IOEV_AON_PROG0_EN_BITN 21 1359 #define IOC_IOCFG3_IOEV_AON_PROG0_EN_M 0x00200000 1360 #define IOC_IOCFG3_IOEV_AON_PROG0_EN_S 21 1361 1362 // Field: [18] EDGE_IRQ_EN 1363 // 1364 // 0: No interrupt generation 1365 // 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is 1366 // enabled) 1367 #define IOC_IOCFG3_EDGE_IRQ_EN 0x00040000 1368 #define IOC_IOCFG3_EDGE_IRQ_EN_BITN 18 1369 #define IOC_IOCFG3_EDGE_IRQ_EN_M 0x00040000 1370 #define IOC_IOCFG3_EDGE_IRQ_EN_S 18 1371 1372 // Field: [17:16] EDGE_DET 1373 // 1374 // Enable generation of edge detection events on this IO 1375 // ENUMs: 1376 // BOTH Positive and negative edge detection 1377 // POS Positive edge detection 1378 // NEG Negative edge detection 1379 // NONE No edge detection 1380 #define IOC_IOCFG3_EDGE_DET_W 2 1381 #define IOC_IOCFG3_EDGE_DET_M 0x00030000 1382 #define IOC_IOCFG3_EDGE_DET_S 16 1383 #define IOC_IOCFG3_EDGE_DET_BOTH 0x00030000 1384 #define IOC_IOCFG3_EDGE_DET_POS 0x00020000 1385 #define IOC_IOCFG3_EDGE_DET_NEG 0x00010000 1386 #define IOC_IOCFG3_EDGE_DET_NONE 0x00000000 1387 1388 // Field: [14:13] PULL_CTL 1389 // 1390 // Pull control 1391 // ENUMs: 1392 // DIS No pull 1393 // UP Pull up 1394 // DWN Pull down 1395 #define IOC_IOCFG3_PULL_CTL_W 2 1396 #define IOC_IOCFG3_PULL_CTL_M 0x00006000 1397 #define IOC_IOCFG3_PULL_CTL_S 13 1398 #define IOC_IOCFG3_PULL_CTL_DIS 0x00006000 1399 #define IOC_IOCFG3_PULL_CTL_UP 0x00004000 1400 #define IOC_IOCFG3_PULL_CTL_DWN 0x00002000 1401 1402 // Field: [12] SLEW_RED 1403 // 1404 // 0: Normal slew rate 1405 // 1: Enables reduced slew rate in output driver. 1406 #define IOC_IOCFG3_SLEW_RED 0x00001000 1407 #define IOC_IOCFG3_SLEW_RED_BITN 12 1408 #define IOC_IOCFG3_SLEW_RED_M 0x00001000 1409 #define IOC_IOCFG3_SLEW_RED_S 12 1410 1411 // Field: [11:10] IOCURR 1412 // 1413 // Selects IO current mode of this IO. 1414 // ENUMs: 1415 // 4_8MA Extended-Current (EC) mode: Min 8 mA for double 1416 // drive strength IOs (min 4 mA for normal IOs) 1417 // when IOSTR is set to AUTO 1418 // 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set 1419 // to AUTO 1420 // 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set 1421 // to AUTO 1422 #define IOC_IOCFG3_IOCURR_W 2 1423 #define IOC_IOCFG3_IOCURR_M 0x00000C00 1424 #define IOC_IOCFG3_IOCURR_S 10 1425 #define IOC_IOCFG3_IOCURR_4_8MA 0x00000800 1426 #define IOC_IOCFG3_IOCURR_4MA 0x00000400 1427 #define IOC_IOCFG3_IOCURR_2MA 0x00000000 1428 1429 // Field: [9:8] IOSTR 1430 // 1431 // Select source for drive strength control of this IO. 1432 // This setting controls the drive strength of the Low-Current (LC) mode. 1433 // Higher drive strength can be selected in IOCURR 1434 // ENUMs: 1435 // MAX Maximum drive strength, controlled by 1436 // AON_IOC:IOSTRMAX (min 2 mA @1.8V with default 1437 // values) 1438 // MED Medium drive strength, controlled by 1439 // AON_IOC:IOSTRMED (min 2 mA @2.5V with default 1440 // values) 1441 // MIN Minimum drive strength, controlled by 1442 // AON_IOC:IOSTRMIN (min 2 mA @3.3V with default 1443 // values) 1444 // AUTO Automatic drive strength, controlled by AON BATMON 1445 // based on battery voltage. (min 2 mA @VDDS) 1446 #define IOC_IOCFG3_IOSTR_W 2 1447 #define IOC_IOCFG3_IOSTR_M 0x00000300 1448 #define IOC_IOCFG3_IOSTR_S 8 1449 #define IOC_IOCFG3_IOSTR_MAX 0x00000300 1450 #define IOC_IOCFG3_IOSTR_MED 0x00000200 1451 #define IOC_IOCFG3_IOSTR_MIN 0x00000100 1452 #define IOC_IOCFG3_IOSTR_AUTO 0x00000000 1453 1454 // Field: [7] IOEV_RTC_EN 1455 // 1456 // Event asserted by this IO when edge detection is enabled 1457 // 1458 // 0: Input edge detection does not assert RTC event 1459 // 1: Input edge detection asserts RTC event 1460 #define IOC_IOCFG3_IOEV_RTC_EN 0x00000080 1461 #define IOC_IOCFG3_IOEV_RTC_EN_BITN 7 1462 #define IOC_IOCFG3_IOEV_RTC_EN_M 0x00000080 1463 #define IOC_IOCFG3_IOEV_RTC_EN_S 7 1464 1465 // Field: [6] IOEV_MCU_WU_EN 1466 // 1467 // Event asserted by this IO when edge detection is enabled 1468 // 1469 // 0: Input edge detection does not assert MCU_WU event 1470 // 1: Input edge detection asserts MCU_WU event 1471 #define IOC_IOCFG3_IOEV_MCU_WU_EN 0x00000040 1472 #define IOC_IOCFG3_IOEV_MCU_WU_EN_BITN 6 1473 #define IOC_IOCFG3_IOEV_MCU_WU_EN_M 0x00000040 1474 #define IOC_IOCFG3_IOEV_MCU_WU_EN_S 6 1475 1476 // Field: [5:0] PORT_ID 1477 // 1478 // Selects usage for DIO3 1479 // Note: This field should not be written other than the times when PORT_ID 1480 // value is specifically required to change. 1481 // ENUMs: 1482 // RFC_SMI_CL_IN RF Core SMI Command Link In 1483 // RFC_SMI_CL_OUT RF Core SMI Command Link Out 1484 // RFC_SMI_DL_IN RF Core SMI Data Link In 1485 // RFC_SMI_DL_OUT RF Core SMI Data Link Out 1486 // RFC_GPI1 RF Core Data In 1 1487 // RFC_GPI0 RF Core Data In 0 1488 // RFC_GPO3 RF Core Data Out 3 1489 // RFC_GPO2 RF Core Data Out 2 1490 // RFC_GPO1 RF Core Data Out 1 1491 // RFC_GPO0 RF Core Data Out 0 1492 // RFC_TRC RF Core Trace 1493 // I2S_MCLK I2S MCLK 1494 // I2S_BCLK I2S BCLK 1495 // I2S_WCLK I2S WCLK 1496 // I2S_AD1 I2S Data 1 1497 // I2S_AD0 I2S Data 0 1498 // SSI1_CLK SSI1 CLK 1499 // SSI1_FSS SSI1 FSS 1500 // SSI1_TX SSI1 TX 1501 // SSI1_RX SSI1 RX 1502 // CPU_SWV CPU SWV 1503 // PORT_EVENT7 PORT EVENT 7 1504 // Can be used as a general 1505 // purpose IO event by selecting it through 1506 // registers in the EVENT module, for example 1507 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 1508 // and so on 1509 // PORT_EVENT6 PORT EVENT 6 1510 // Can be used as a general 1511 // purpose IO event by selecting it through 1512 // registers in the EVENT module, for example 1513 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 1514 // and so on 1515 // PORT_EVENT5 PORT EVENT 5 1516 // Can be used as a general 1517 // purpose IO event by selecting it through 1518 // registers in the EVENT module, for example 1519 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 1520 // and so on 1521 // PORT_EVENT4 PORT EVENT 4 1522 // Can be used as a general 1523 // purpose IO event by selecting it through 1524 // registers in the EVENT module, for example 1525 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 1526 // and so on 1527 // PORT_EVENT3 PORT EVENT 3 1528 // Can be used as a general 1529 // purpose IO event by selecting it through 1530 // registers in the EVENT module, for example 1531 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 1532 // and so on 1533 // PORT_EVENT2 PORT EVENT 2 1534 // Can be used as a general 1535 // purpose IO event by selecting it through 1536 // registers in the EVENT module, for example 1537 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 1538 // and so on 1539 // PORT_EVENT1 PORT EVENT 1 1540 // Can be used as a general 1541 // purpose IO event by selecting it through 1542 // registers in the EVENT module, for example 1543 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 1544 // and so on 1545 // PORT_EVENT0 PORT EVENT 0 1546 // Can be used as a general 1547 // purpose IO event by selecting it through 1548 // registers in the EVENT module, for example 1549 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 1550 // and so on 1551 // UART1_RTS UART1 RTS 1552 // UART1_CTS UART1 CTS 1553 // UART1_TX UART1 TX 1554 // UART1_RX UART1 RX 1555 // UART0_RTS UART0 RTS 1556 // UART0_CTS UART0 CTS 1557 // UART0_TX UART0 TX 1558 // UART0_RX UART0 RX 1559 // I2C_MSSCL I2C Clock 1560 // I2C_MSSDA I2C Data 1561 // SSI0_CLK SSI0 CLK 1562 // SSI0_FSS SSI0 FSS 1563 // SSI0_TX SSI0 TX 1564 // SSI0_RX SSI0 RX 1565 // AUX_IO AUX IO 1566 // AON_CLK32K AON 32 KHz clock (SCLK_LF) 1567 // GPIO General Purpose IO 1568 #define IOC_IOCFG3_PORT_ID_W 6 1569 #define IOC_IOCFG3_PORT_ID_M 0x0000003F 1570 #define IOC_IOCFG3_PORT_ID_S 0 1571 #define IOC_IOCFG3_PORT_ID_RFC_SMI_CL_IN 0x00000038 1572 #define IOC_IOCFG3_PORT_ID_RFC_SMI_CL_OUT 0x00000037 1573 #define IOC_IOCFG3_PORT_ID_RFC_SMI_DL_IN 0x00000036 1574 #define IOC_IOCFG3_PORT_ID_RFC_SMI_DL_OUT 0x00000035 1575 #define IOC_IOCFG3_PORT_ID_RFC_GPI1 0x00000034 1576 #define IOC_IOCFG3_PORT_ID_RFC_GPI0 0x00000033 1577 #define IOC_IOCFG3_PORT_ID_RFC_GPO3 0x00000032 1578 #define IOC_IOCFG3_PORT_ID_RFC_GPO2 0x00000031 1579 #define IOC_IOCFG3_PORT_ID_RFC_GPO1 0x00000030 1580 #define IOC_IOCFG3_PORT_ID_RFC_GPO0 0x0000002F 1581 #define IOC_IOCFG3_PORT_ID_RFC_TRC 0x0000002E 1582 #define IOC_IOCFG3_PORT_ID_I2S_MCLK 0x00000029 1583 #define IOC_IOCFG3_PORT_ID_I2S_BCLK 0x00000028 1584 #define IOC_IOCFG3_PORT_ID_I2S_WCLK 0x00000027 1585 #define IOC_IOCFG3_PORT_ID_I2S_AD1 0x00000026 1586 #define IOC_IOCFG3_PORT_ID_I2S_AD0 0x00000025 1587 #define IOC_IOCFG3_PORT_ID_SSI1_CLK 0x00000024 1588 #define IOC_IOCFG3_PORT_ID_SSI1_FSS 0x00000023 1589 #define IOC_IOCFG3_PORT_ID_SSI1_TX 0x00000022 1590 #define IOC_IOCFG3_PORT_ID_SSI1_RX 0x00000021 1591 #define IOC_IOCFG3_PORT_ID_CPU_SWV 0x00000020 1592 #define IOC_IOCFG3_PORT_ID_PORT_EVENT7 0x0000001E 1593 #define IOC_IOCFG3_PORT_ID_PORT_EVENT6 0x0000001D 1594 #define IOC_IOCFG3_PORT_ID_PORT_EVENT5 0x0000001C 1595 #define IOC_IOCFG3_PORT_ID_PORT_EVENT4 0x0000001B 1596 #define IOC_IOCFG3_PORT_ID_PORT_EVENT3 0x0000001A 1597 #define IOC_IOCFG3_PORT_ID_PORT_EVENT2 0x00000019 1598 #define IOC_IOCFG3_PORT_ID_PORT_EVENT1 0x00000018 1599 #define IOC_IOCFG3_PORT_ID_PORT_EVENT0 0x00000017 1600 #define IOC_IOCFG3_PORT_ID_UART1_RTS 0x00000016 1601 #define IOC_IOCFG3_PORT_ID_UART1_CTS 0x00000015 1602 #define IOC_IOCFG3_PORT_ID_UART1_TX 0x00000014 1603 #define IOC_IOCFG3_PORT_ID_UART1_RX 0x00000013 1604 #define IOC_IOCFG3_PORT_ID_UART0_RTS 0x00000012 1605 #define IOC_IOCFG3_PORT_ID_UART0_CTS 0x00000011 1606 #define IOC_IOCFG3_PORT_ID_UART0_TX 0x00000010 1607 #define IOC_IOCFG3_PORT_ID_UART0_RX 0x0000000F 1608 #define IOC_IOCFG3_PORT_ID_I2C_MSSCL 0x0000000E 1609 #define IOC_IOCFG3_PORT_ID_I2C_MSSDA 0x0000000D 1610 #define IOC_IOCFG3_PORT_ID_SSI0_CLK 0x0000000C 1611 #define IOC_IOCFG3_PORT_ID_SSI0_FSS 0x0000000B 1612 #define IOC_IOCFG3_PORT_ID_SSI0_TX 0x0000000A 1613 #define IOC_IOCFG3_PORT_ID_SSI0_RX 0x00000009 1614 #define IOC_IOCFG3_PORT_ID_AUX_IO 0x00000008 1615 #define IOC_IOCFG3_PORT_ID_AON_CLK32K 0x00000007 1616 #define IOC_IOCFG3_PORT_ID_GPIO 0x00000000 1617 1618 //***************************************************************************** 1619 // 1620 // Register: IOC_O_IOCFG4 1621 // 1622 //***************************************************************************** 1623 // Field: [30] HYST_EN 1624 // 1625 // 0: Input hysteresis disable 1626 // 1: Input hysteresis enable 1627 #define IOC_IOCFG4_HYST_EN 0x40000000 1628 #define IOC_IOCFG4_HYST_EN_BITN 30 1629 #define IOC_IOCFG4_HYST_EN_M 0x40000000 1630 #define IOC_IOCFG4_HYST_EN_S 30 1631 1632 // Field: [29] IE 1633 // 1634 // 0: Input disabled 1635 // 1: Input enabled 1636 // 1637 // Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be 1638 // ignored. 1639 #define IOC_IOCFG4_IE 0x20000000 1640 #define IOC_IOCFG4_IE_BITN 29 1641 #define IOC_IOCFG4_IE_M 0x20000000 1642 #define IOC_IOCFG4_IE_S 29 1643 1644 // Field: [28:27] WU_CFG 1645 // 1646 // If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or 1647 // >0x08: 1648 // 1649 // 00: No wake-up 1650 // 01: No wake-up 1651 // 10: Wakes up from shutdown if this pad is going low. 1652 // 11: Wakes up from shutdown if this pad is going high. 1653 // 1654 // If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, 1655 // this register only sets wakeup enable or not. 1656 // 1657 // 00, 01: Wakeup disabled 1658 // 10, 11: Wakeup enabled 1659 // 1660 // Polarity is controlled from AON registers. 1661 // 1662 // Note:When the MSB is set, the IOC will deactivate the output enable for the 1663 // DIO. 1664 #define IOC_IOCFG4_WU_CFG_W 2 1665 #define IOC_IOCFG4_WU_CFG_M 0x18000000 1666 #define IOC_IOCFG4_WU_CFG_S 27 1667 1668 // Field: [26:24] IOMODE 1669 // 1670 // IO Mode 1671 // Not applicable for IO configured for AON periph. signals and AUX PORT_ID 1672 // 0x01-0x08 1673 // AUX has its own open_source/drain configuration. 1674 // 1675 // 0x2: Reserved. Undefined behavior. 1676 // 0x3: Reserved. Undefined behavior. 1677 // ENUMs: 1678 // OPENSRC_INV Open Source 1679 // Inverted input / output 1680 // OPENSRC Open Source 1681 // Normal input / output 1682 // OPENDR_INV Open Drain 1683 // Inverted input / output 1684 // OPENDR Open Drain, 1685 // Normal input / output 1686 // INV Inverted input / ouput 1687 // NORMAL Normal input / output 1688 #define IOC_IOCFG4_IOMODE_W 3 1689 #define IOC_IOCFG4_IOMODE_M 0x07000000 1690 #define IOC_IOCFG4_IOMODE_S 24 1691 #define IOC_IOCFG4_IOMODE_OPENSRC_INV 0x07000000 1692 #define IOC_IOCFG4_IOMODE_OPENSRC 0x06000000 1693 #define IOC_IOCFG4_IOMODE_OPENDR_INV 0x05000000 1694 #define IOC_IOCFG4_IOMODE_OPENDR 0x04000000 1695 #define IOC_IOCFG4_IOMODE_INV 0x01000000 1696 #define IOC_IOCFG4_IOMODE_NORMAL 0x00000000 1697 1698 // Field: [23] IOEV_AON_PROG2_EN 1699 // 1700 // Event asserted by this IO when edge detection is enabled 1701 // 1702 // 0: Input edge detection does not assert AON_PROG2 event 1703 // 1: Input edge detection asserts AON_PROG2 event 1704 #define IOC_IOCFG4_IOEV_AON_PROG2_EN 0x00800000 1705 #define IOC_IOCFG4_IOEV_AON_PROG2_EN_BITN 23 1706 #define IOC_IOCFG4_IOEV_AON_PROG2_EN_M 0x00800000 1707 #define IOC_IOCFG4_IOEV_AON_PROG2_EN_S 23 1708 1709 // Field: [22] IOEV_AON_PROG1_EN 1710 // 1711 // Event asserted by this IO when edge detection is enabled 1712 // 1713 // 0: Input edge detection does not assert AON_PROG1 event 1714 // 1: Input edge detection asserts AON_PROG1 event 1715 #define IOC_IOCFG4_IOEV_AON_PROG1_EN 0x00400000 1716 #define IOC_IOCFG4_IOEV_AON_PROG1_EN_BITN 22 1717 #define IOC_IOCFG4_IOEV_AON_PROG1_EN_M 0x00400000 1718 #define IOC_IOCFG4_IOEV_AON_PROG1_EN_S 22 1719 1720 // Field: [21] IOEV_AON_PROG0_EN 1721 // 1722 // Event asserted by this IO when edge detection is enabled 1723 // 1724 // 0: Input edge detection does not assert AON_PROG0 event 1725 // 1: Input edge detection asserts AON_PROG0 event 1726 #define IOC_IOCFG4_IOEV_AON_PROG0_EN 0x00200000 1727 #define IOC_IOCFG4_IOEV_AON_PROG0_EN_BITN 21 1728 #define IOC_IOCFG4_IOEV_AON_PROG0_EN_M 0x00200000 1729 #define IOC_IOCFG4_IOEV_AON_PROG0_EN_S 21 1730 1731 // Field: [18] EDGE_IRQ_EN 1732 // 1733 // 0: No interrupt generation 1734 // 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is 1735 // enabled) 1736 #define IOC_IOCFG4_EDGE_IRQ_EN 0x00040000 1737 #define IOC_IOCFG4_EDGE_IRQ_EN_BITN 18 1738 #define IOC_IOCFG4_EDGE_IRQ_EN_M 0x00040000 1739 #define IOC_IOCFG4_EDGE_IRQ_EN_S 18 1740 1741 // Field: [17:16] EDGE_DET 1742 // 1743 // Enable generation of edge detection events on this IO 1744 // ENUMs: 1745 // BOTH Positive and negative edge detection 1746 // POS Positive edge detection 1747 // NEG Negative edge detection 1748 // NONE No edge detection 1749 #define IOC_IOCFG4_EDGE_DET_W 2 1750 #define IOC_IOCFG4_EDGE_DET_M 0x00030000 1751 #define IOC_IOCFG4_EDGE_DET_S 16 1752 #define IOC_IOCFG4_EDGE_DET_BOTH 0x00030000 1753 #define IOC_IOCFG4_EDGE_DET_POS 0x00020000 1754 #define IOC_IOCFG4_EDGE_DET_NEG 0x00010000 1755 #define IOC_IOCFG4_EDGE_DET_NONE 0x00000000 1756 1757 // Field: [14:13] PULL_CTL 1758 // 1759 // Pull control 1760 // ENUMs: 1761 // DIS No pull 1762 // UP Pull up 1763 // DWN Pull down 1764 #define IOC_IOCFG4_PULL_CTL_W 2 1765 #define IOC_IOCFG4_PULL_CTL_M 0x00006000 1766 #define IOC_IOCFG4_PULL_CTL_S 13 1767 #define IOC_IOCFG4_PULL_CTL_DIS 0x00006000 1768 #define IOC_IOCFG4_PULL_CTL_UP 0x00004000 1769 #define IOC_IOCFG4_PULL_CTL_DWN 0x00002000 1770 1771 // Field: [12] SLEW_RED 1772 // 1773 // 0: Normal slew rate 1774 // 1: Enables reduced slew rate in output driver. 1775 #define IOC_IOCFG4_SLEW_RED 0x00001000 1776 #define IOC_IOCFG4_SLEW_RED_BITN 12 1777 #define IOC_IOCFG4_SLEW_RED_M 0x00001000 1778 #define IOC_IOCFG4_SLEW_RED_S 12 1779 1780 // Field: [11:10] IOCURR 1781 // 1782 // Selects IO current mode of this IO. 1783 // ENUMs: 1784 // 4_8MA Extended-Current (EC) mode: Min 8 mA for double 1785 // drive strength IOs (min 4 mA for normal IOs) 1786 // when IOSTR is set to AUTO 1787 // 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set 1788 // to AUTO 1789 // 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set 1790 // to AUTO 1791 #define IOC_IOCFG4_IOCURR_W 2 1792 #define IOC_IOCFG4_IOCURR_M 0x00000C00 1793 #define IOC_IOCFG4_IOCURR_S 10 1794 #define IOC_IOCFG4_IOCURR_4_8MA 0x00000800 1795 #define IOC_IOCFG4_IOCURR_4MA 0x00000400 1796 #define IOC_IOCFG4_IOCURR_2MA 0x00000000 1797 1798 // Field: [9:8] IOSTR 1799 // 1800 // Select source for drive strength control of this IO. 1801 // This setting controls the drive strength of the Low-Current (LC) mode. 1802 // Higher drive strength can be selected in IOCURR 1803 // ENUMs: 1804 // MAX Maximum drive strength, controlled by 1805 // AON_IOC:IOSTRMAX (min 2 mA @1.8V with default 1806 // values) 1807 // MED Medium drive strength, controlled by 1808 // AON_IOC:IOSTRMED (min 2 mA @2.5V with default 1809 // values) 1810 // MIN Minimum drive strength, controlled by 1811 // AON_IOC:IOSTRMIN (min 2 mA @3.3V with default 1812 // values) 1813 // AUTO Automatic drive strength, controlled by AON BATMON 1814 // based on battery voltage. (min 2 mA @VDDS) 1815 #define IOC_IOCFG4_IOSTR_W 2 1816 #define IOC_IOCFG4_IOSTR_M 0x00000300 1817 #define IOC_IOCFG4_IOSTR_S 8 1818 #define IOC_IOCFG4_IOSTR_MAX 0x00000300 1819 #define IOC_IOCFG4_IOSTR_MED 0x00000200 1820 #define IOC_IOCFG4_IOSTR_MIN 0x00000100 1821 #define IOC_IOCFG4_IOSTR_AUTO 0x00000000 1822 1823 // Field: [7] IOEV_RTC_EN 1824 // 1825 // Event asserted by this IO when edge detection is enabled 1826 // 1827 // 0: Input edge detection does not assert RTC event 1828 // 1: Input edge detection asserts RTC event 1829 #define IOC_IOCFG4_IOEV_RTC_EN 0x00000080 1830 #define IOC_IOCFG4_IOEV_RTC_EN_BITN 7 1831 #define IOC_IOCFG4_IOEV_RTC_EN_M 0x00000080 1832 #define IOC_IOCFG4_IOEV_RTC_EN_S 7 1833 1834 // Field: [6] IOEV_MCU_WU_EN 1835 // 1836 // Event asserted by this IO when edge detection is enabled 1837 // 1838 // 0: Input edge detection does not assert MCU_WU event 1839 // 1: Input edge detection asserts MCU_WU event 1840 #define IOC_IOCFG4_IOEV_MCU_WU_EN 0x00000040 1841 #define IOC_IOCFG4_IOEV_MCU_WU_EN_BITN 6 1842 #define IOC_IOCFG4_IOEV_MCU_WU_EN_M 0x00000040 1843 #define IOC_IOCFG4_IOEV_MCU_WU_EN_S 6 1844 1845 // Field: [5:0] PORT_ID 1846 // 1847 // Selects usage for DIO4 1848 // Note: This field should not be written other than the times when PORT_ID 1849 // value is specifically required to change. 1850 // ENUMs: 1851 // RFC_SMI_CL_IN RF Core SMI Command Link In 1852 // RFC_SMI_CL_OUT RF Core SMI Command Link Out 1853 // RFC_SMI_DL_IN RF Core SMI Data Link In 1854 // RFC_SMI_DL_OUT RF Core SMI Data Link Out 1855 // RFC_GPI1 RF Core Data In 1 1856 // RFC_GPI0 RF Core Data In 0 1857 // RFC_GPO3 RF Core Data Out 3 1858 // RFC_GPO2 RF Core Data Out 2 1859 // RFC_GPO1 RF Core Data Out 1 1860 // RFC_GPO0 RF Core Data Out 0 1861 // RFC_TRC RF Core Trace 1862 // I2S_MCLK I2S MCLK 1863 // I2S_BCLK I2S BCLK 1864 // I2S_WCLK I2S WCLK 1865 // I2S_AD1 I2S Data 1 1866 // I2S_AD0 I2S Data 0 1867 // SSI1_CLK SSI1 CLK 1868 // SSI1_FSS SSI1 FSS 1869 // SSI1_TX SSI1 TX 1870 // SSI1_RX SSI1 RX 1871 // CPU_SWV CPU SWV 1872 // PORT_EVENT7 PORT EVENT 7 1873 // Can be used as a general 1874 // purpose IO event by selecting it through 1875 // registers in the EVENT module, for example 1876 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 1877 // and so on 1878 // PORT_EVENT6 PORT EVENT 6 1879 // Can be used as a general 1880 // purpose IO event by selecting it through 1881 // registers in the EVENT module, for example 1882 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 1883 // and so on 1884 // PORT_EVENT5 PORT EVENT 5 1885 // Can be used as a general 1886 // purpose IO event by selecting it through 1887 // registers in the EVENT module, for example 1888 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 1889 // and so on 1890 // PORT_EVENT4 PORT EVENT 4 1891 // Can be used as a general 1892 // purpose IO event by selecting it through 1893 // registers in the EVENT module, for example 1894 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 1895 // and so on 1896 // PORT_EVENT3 PORT EVENT 3 1897 // Can be used as a general 1898 // purpose IO event by selecting it through 1899 // registers in the EVENT module, for example 1900 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 1901 // and so on 1902 // PORT_EVENT2 PORT EVENT 2 1903 // Can be used as a general 1904 // purpose IO event by selecting it through 1905 // registers in the EVENT module, for example 1906 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 1907 // and so on 1908 // PORT_EVENT1 PORT EVENT 1 1909 // Can be used as a general 1910 // purpose IO event by selecting it through 1911 // registers in the EVENT module, for example 1912 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 1913 // and so on 1914 // PORT_EVENT0 PORT EVENT 0 1915 // Can be used as a general 1916 // purpose IO event by selecting it through 1917 // registers in the EVENT module, for example 1918 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 1919 // and so on 1920 // UART1_RTS UART1 RTS 1921 // UART1_CTS UART1 CTS 1922 // UART1_TX UART1 TX 1923 // UART1_RX UART1 RX 1924 // UART0_RTS UART0 RTS 1925 // UART0_CTS UART0 CTS 1926 // UART0_TX UART0 TX 1927 // UART0_RX UART0 RX 1928 // I2C_MSSCL I2C Clock 1929 // I2C_MSSDA I2C Data 1930 // SSI0_CLK SSI0 CLK 1931 // SSI0_FSS SSI0 FSS 1932 // SSI0_TX SSI0 TX 1933 // SSI0_RX SSI0 RX 1934 // AUX_IO AUX IO 1935 // AON_CLK32K AON 32 KHz clock (SCLK_LF) 1936 // GPIO General Purpose IO 1937 #define IOC_IOCFG4_PORT_ID_W 6 1938 #define IOC_IOCFG4_PORT_ID_M 0x0000003F 1939 #define IOC_IOCFG4_PORT_ID_S 0 1940 #define IOC_IOCFG4_PORT_ID_RFC_SMI_CL_IN 0x00000038 1941 #define IOC_IOCFG4_PORT_ID_RFC_SMI_CL_OUT 0x00000037 1942 #define IOC_IOCFG4_PORT_ID_RFC_SMI_DL_IN 0x00000036 1943 #define IOC_IOCFG4_PORT_ID_RFC_SMI_DL_OUT 0x00000035 1944 #define IOC_IOCFG4_PORT_ID_RFC_GPI1 0x00000034 1945 #define IOC_IOCFG4_PORT_ID_RFC_GPI0 0x00000033 1946 #define IOC_IOCFG4_PORT_ID_RFC_GPO3 0x00000032 1947 #define IOC_IOCFG4_PORT_ID_RFC_GPO2 0x00000031 1948 #define IOC_IOCFG4_PORT_ID_RFC_GPO1 0x00000030 1949 #define IOC_IOCFG4_PORT_ID_RFC_GPO0 0x0000002F 1950 #define IOC_IOCFG4_PORT_ID_RFC_TRC 0x0000002E 1951 #define IOC_IOCFG4_PORT_ID_I2S_MCLK 0x00000029 1952 #define IOC_IOCFG4_PORT_ID_I2S_BCLK 0x00000028 1953 #define IOC_IOCFG4_PORT_ID_I2S_WCLK 0x00000027 1954 #define IOC_IOCFG4_PORT_ID_I2S_AD1 0x00000026 1955 #define IOC_IOCFG4_PORT_ID_I2S_AD0 0x00000025 1956 #define IOC_IOCFG4_PORT_ID_SSI1_CLK 0x00000024 1957 #define IOC_IOCFG4_PORT_ID_SSI1_FSS 0x00000023 1958 #define IOC_IOCFG4_PORT_ID_SSI1_TX 0x00000022 1959 #define IOC_IOCFG4_PORT_ID_SSI1_RX 0x00000021 1960 #define IOC_IOCFG4_PORT_ID_CPU_SWV 0x00000020 1961 #define IOC_IOCFG4_PORT_ID_PORT_EVENT7 0x0000001E 1962 #define IOC_IOCFG4_PORT_ID_PORT_EVENT6 0x0000001D 1963 #define IOC_IOCFG4_PORT_ID_PORT_EVENT5 0x0000001C 1964 #define IOC_IOCFG4_PORT_ID_PORT_EVENT4 0x0000001B 1965 #define IOC_IOCFG4_PORT_ID_PORT_EVENT3 0x0000001A 1966 #define IOC_IOCFG4_PORT_ID_PORT_EVENT2 0x00000019 1967 #define IOC_IOCFG4_PORT_ID_PORT_EVENT1 0x00000018 1968 #define IOC_IOCFG4_PORT_ID_PORT_EVENT0 0x00000017 1969 #define IOC_IOCFG4_PORT_ID_UART1_RTS 0x00000016 1970 #define IOC_IOCFG4_PORT_ID_UART1_CTS 0x00000015 1971 #define IOC_IOCFG4_PORT_ID_UART1_TX 0x00000014 1972 #define IOC_IOCFG4_PORT_ID_UART1_RX 0x00000013 1973 #define IOC_IOCFG4_PORT_ID_UART0_RTS 0x00000012 1974 #define IOC_IOCFG4_PORT_ID_UART0_CTS 0x00000011 1975 #define IOC_IOCFG4_PORT_ID_UART0_TX 0x00000010 1976 #define IOC_IOCFG4_PORT_ID_UART0_RX 0x0000000F 1977 #define IOC_IOCFG4_PORT_ID_I2C_MSSCL 0x0000000E 1978 #define IOC_IOCFG4_PORT_ID_I2C_MSSDA 0x0000000D 1979 #define IOC_IOCFG4_PORT_ID_SSI0_CLK 0x0000000C 1980 #define IOC_IOCFG4_PORT_ID_SSI0_FSS 0x0000000B 1981 #define IOC_IOCFG4_PORT_ID_SSI0_TX 0x0000000A 1982 #define IOC_IOCFG4_PORT_ID_SSI0_RX 0x00000009 1983 #define IOC_IOCFG4_PORT_ID_AUX_IO 0x00000008 1984 #define IOC_IOCFG4_PORT_ID_AON_CLK32K 0x00000007 1985 #define IOC_IOCFG4_PORT_ID_GPIO 0x00000000 1986 1987 //***************************************************************************** 1988 // 1989 // Register: IOC_O_IOCFG5 1990 // 1991 //***************************************************************************** 1992 // Field: [30] HYST_EN 1993 // 1994 // 0: Input hysteresis disable 1995 // 1: Input hysteresis enable 1996 #define IOC_IOCFG5_HYST_EN 0x40000000 1997 #define IOC_IOCFG5_HYST_EN_BITN 30 1998 #define IOC_IOCFG5_HYST_EN_M 0x40000000 1999 #define IOC_IOCFG5_HYST_EN_S 30 2000 2001 // Field: [29] IE 2002 // 2003 // 0: Input disabled 2004 // 1: Input enabled 2005 // 2006 // Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be 2007 // ignored. 2008 #define IOC_IOCFG5_IE 0x20000000 2009 #define IOC_IOCFG5_IE_BITN 29 2010 #define IOC_IOCFG5_IE_M 0x20000000 2011 #define IOC_IOCFG5_IE_S 29 2012 2013 // Field: [28:27] WU_CFG 2014 // 2015 // If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or 2016 // >0x08: 2017 // 2018 // 00: No wake-up 2019 // 01: No wake-up 2020 // 10: Wakes up from shutdown if this pad is going low. 2021 // 11: Wakes up from shutdown if this pad is going high. 2022 // 2023 // If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, 2024 // this register only sets wakeup enable or not. 2025 // 2026 // 00, 01: Wakeup disabled 2027 // 10, 11: Wakeup enabled 2028 // 2029 // Polarity is controlled from AON registers. 2030 // 2031 // Note:When the MSB is set, the IOC will deactivate the output enable for the 2032 // DIO. 2033 #define IOC_IOCFG5_WU_CFG_W 2 2034 #define IOC_IOCFG5_WU_CFG_M 0x18000000 2035 #define IOC_IOCFG5_WU_CFG_S 27 2036 2037 // Field: [26:24] IOMODE 2038 // 2039 // IO Mode 2040 // Not applicable for IO configured for AON periph. signals and AUX PORT_ID 2041 // 0x01-0x08 2042 // AUX has its own open_source/drain configuration. 2043 // 2044 // 0x2: Reserved. Undefined behavior. 2045 // 0x3: Reserved. Undefined behavior. 2046 // ENUMs: 2047 // OPENSRC_INV Open Source 2048 // Inverted input / output 2049 // OPENSRC Open Source 2050 // Normal input / output 2051 // OPENDR_INV Open Drain 2052 // Inverted input / output 2053 // OPENDR Open Drain, 2054 // Normal input / output 2055 // INV Inverted input / ouput 2056 // NORMAL Normal input / output 2057 #define IOC_IOCFG5_IOMODE_W 3 2058 #define IOC_IOCFG5_IOMODE_M 0x07000000 2059 #define IOC_IOCFG5_IOMODE_S 24 2060 #define IOC_IOCFG5_IOMODE_OPENSRC_INV 0x07000000 2061 #define IOC_IOCFG5_IOMODE_OPENSRC 0x06000000 2062 #define IOC_IOCFG5_IOMODE_OPENDR_INV 0x05000000 2063 #define IOC_IOCFG5_IOMODE_OPENDR 0x04000000 2064 #define IOC_IOCFG5_IOMODE_INV 0x01000000 2065 #define IOC_IOCFG5_IOMODE_NORMAL 0x00000000 2066 2067 // Field: [23] IOEV_AON_PROG2_EN 2068 // 2069 // Event asserted by this IO when edge detection is enabled 2070 // 2071 // 0: Input edge detection does not assert AON_PROG2 event 2072 // 1: Input edge detection asserts AON_PROG2 event 2073 #define IOC_IOCFG5_IOEV_AON_PROG2_EN 0x00800000 2074 #define IOC_IOCFG5_IOEV_AON_PROG2_EN_BITN 23 2075 #define IOC_IOCFG5_IOEV_AON_PROG2_EN_M 0x00800000 2076 #define IOC_IOCFG5_IOEV_AON_PROG2_EN_S 23 2077 2078 // Field: [22] IOEV_AON_PROG1_EN 2079 // 2080 // Event asserted by this IO when edge detection is enabled 2081 // 2082 // 0: Input edge detection does not assert AON_PROG1 event 2083 // 1: Input edge detection asserts AON_PROG1 event 2084 #define IOC_IOCFG5_IOEV_AON_PROG1_EN 0x00400000 2085 #define IOC_IOCFG5_IOEV_AON_PROG1_EN_BITN 22 2086 #define IOC_IOCFG5_IOEV_AON_PROG1_EN_M 0x00400000 2087 #define IOC_IOCFG5_IOEV_AON_PROG1_EN_S 22 2088 2089 // Field: [21] IOEV_AON_PROG0_EN 2090 // 2091 // Event asserted by this IO when edge detection is enabled 2092 // 2093 // 0: Input edge detection does not assert AON_PROG0 event 2094 // 1: Input edge detection asserts AON_PROG0 event 2095 #define IOC_IOCFG5_IOEV_AON_PROG0_EN 0x00200000 2096 #define IOC_IOCFG5_IOEV_AON_PROG0_EN_BITN 21 2097 #define IOC_IOCFG5_IOEV_AON_PROG0_EN_M 0x00200000 2098 #define IOC_IOCFG5_IOEV_AON_PROG0_EN_S 21 2099 2100 // Field: [18] EDGE_IRQ_EN 2101 // 2102 // 0: No interrupt generation 2103 // 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is 2104 // enabled) 2105 #define IOC_IOCFG5_EDGE_IRQ_EN 0x00040000 2106 #define IOC_IOCFG5_EDGE_IRQ_EN_BITN 18 2107 #define IOC_IOCFG5_EDGE_IRQ_EN_M 0x00040000 2108 #define IOC_IOCFG5_EDGE_IRQ_EN_S 18 2109 2110 // Field: [17:16] EDGE_DET 2111 // 2112 // Enable generation of edge detection events on this IO 2113 // ENUMs: 2114 // BOTH Positive and negative edge detection 2115 // POS Positive edge detection 2116 // NEG Negative edge detection 2117 // NONE No edge detection 2118 #define IOC_IOCFG5_EDGE_DET_W 2 2119 #define IOC_IOCFG5_EDGE_DET_M 0x00030000 2120 #define IOC_IOCFG5_EDGE_DET_S 16 2121 #define IOC_IOCFG5_EDGE_DET_BOTH 0x00030000 2122 #define IOC_IOCFG5_EDGE_DET_POS 0x00020000 2123 #define IOC_IOCFG5_EDGE_DET_NEG 0x00010000 2124 #define IOC_IOCFG5_EDGE_DET_NONE 0x00000000 2125 2126 // Field: [14:13] PULL_CTL 2127 // 2128 // Pull control 2129 // ENUMs: 2130 // DIS No pull 2131 // UP Pull up 2132 // DWN Pull down 2133 #define IOC_IOCFG5_PULL_CTL_W 2 2134 #define IOC_IOCFG5_PULL_CTL_M 0x00006000 2135 #define IOC_IOCFG5_PULL_CTL_S 13 2136 #define IOC_IOCFG5_PULL_CTL_DIS 0x00006000 2137 #define IOC_IOCFG5_PULL_CTL_UP 0x00004000 2138 #define IOC_IOCFG5_PULL_CTL_DWN 0x00002000 2139 2140 // Field: [12] SLEW_RED 2141 // 2142 // 0: Normal slew rate 2143 // 1: Enables reduced slew rate in output driver. 2144 #define IOC_IOCFG5_SLEW_RED 0x00001000 2145 #define IOC_IOCFG5_SLEW_RED_BITN 12 2146 #define IOC_IOCFG5_SLEW_RED_M 0x00001000 2147 #define IOC_IOCFG5_SLEW_RED_S 12 2148 2149 // Field: [11:10] IOCURR 2150 // 2151 // Selects IO current mode of this IO. 2152 // ENUMs: 2153 // 4_8MA Extended-Current (EC) mode: Min 8 mA for double 2154 // drive strength IOs (min 4 mA for normal IOs) 2155 // when IOSTR is set to AUTO 2156 // 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set 2157 // to AUTO 2158 // 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set 2159 // to AUTO 2160 #define IOC_IOCFG5_IOCURR_W 2 2161 #define IOC_IOCFG5_IOCURR_M 0x00000C00 2162 #define IOC_IOCFG5_IOCURR_S 10 2163 #define IOC_IOCFG5_IOCURR_4_8MA 0x00000800 2164 #define IOC_IOCFG5_IOCURR_4MA 0x00000400 2165 #define IOC_IOCFG5_IOCURR_2MA 0x00000000 2166 2167 // Field: [9:8] IOSTR 2168 // 2169 // Select source for drive strength control of this IO. 2170 // This setting controls the drive strength of the Low-Current (LC) mode. 2171 // Higher drive strength can be selected in IOCURR 2172 // ENUMs: 2173 // MAX Maximum drive strength, controlled by 2174 // AON_IOC:IOSTRMAX (min 2 mA @1.8V with default 2175 // values) 2176 // MED Medium drive strength, controlled by 2177 // AON_IOC:IOSTRMED (min 2 mA @2.5V with default 2178 // values) 2179 // MIN Minimum drive strength, controlled by 2180 // AON_IOC:IOSTRMIN (min 2 mA @3.3V with default 2181 // values) 2182 // AUTO Automatic drive strength, controlled by AON BATMON 2183 // based on battery voltage. (min 2 mA @VDDS) 2184 #define IOC_IOCFG5_IOSTR_W 2 2185 #define IOC_IOCFG5_IOSTR_M 0x00000300 2186 #define IOC_IOCFG5_IOSTR_S 8 2187 #define IOC_IOCFG5_IOSTR_MAX 0x00000300 2188 #define IOC_IOCFG5_IOSTR_MED 0x00000200 2189 #define IOC_IOCFG5_IOSTR_MIN 0x00000100 2190 #define IOC_IOCFG5_IOSTR_AUTO 0x00000000 2191 2192 // Field: [7] IOEV_RTC_EN 2193 // 2194 // Event asserted by this IO when edge detection is enabled 2195 // 2196 // 0: Input edge detection does not assert RTC event 2197 // 1: Input edge detection asserts RTC event 2198 #define IOC_IOCFG5_IOEV_RTC_EN 0x00000080 2199 #define IOC_IOCFG5_IOEV_RTC_EN_BITN 7 2200 #define IOC_IOCFG5_IOEV_RTC_EN_M 0x00000080 2201 #define IOC_IOCFG5_IOEV_RTC_EN_S 7 2202 2203 // Field: [6] IOEV_MCU_WU_EN 2204 // 2205 // Event asserted by this IO when edge detection is enabled 2206 // 2207 // 0: Input edge detection does not assert MCU_WU event 2208 // 1: Input edge detection asserts MCU_WU event 2209 #define IOC_IOCFG5_IOEV_MCU_WU_EN 0x00000040 2210 #define IOC_IOCFG5_IOEV_MCU_WU_EN_BITN 6 2211 #define IOC_IOCFG5_IOEV_MCU_WU_EN_M 0x00000040 2212 #define IOC_IOCFG5_IOEV_MCU_WU_EN_S 6 2213 2214 // Field: [5:0] PORT_ID 2215 // 2216 // Selects usage for DIO5 2217 // Note: This field should not be written other than the times when PORT_ID 2218 // value is specifically required to change. 2219 // ENUMs: 2220 // RFC_SMI_CL_IN RF Core SMI Command Link In 2221 // RFC_SMI_CL_OUT RF Core SMI Command Link Out 2222 // RFC_SMI_DL_IN RF Core SMI Data Link In 2223 // RFC_SMI_DL_OUT RF Core SMI Data Link Out 2224 // RFC_GPI1 RF Core Data In 1 2225 // RFC_GPI0 RF Core Data In 0 2226 // RFC_GPO3 RF Core Data Out 3 2227 // RFC_GPO2 RF Core Data Out 2 2228 // RFC_GPO1 RF Core Data Out 1 2229 // RFC_GPO0 RF Core Data Out 0 2230 // RFC_TRC RF Core Trace 2231 // I2S_MCLK I2S MCLK 2232 // I2S_BCLK I2S BCLK 2233 // I2S_WCLK I2S WCLK 2234 // I2S_AD1 I2S Data 1 2235 // I2S_AD0 I2S Data 0 2236 // SSI1_CLK SSI1 CLK 2237 // SSI1_FSS SSI1 FSS 2238 // SSI1_TX SSI1 TX 2239 // SSI1_RX SSI1 RX 2240 // CPU_SWV CPU SWV 2241 // PORT_EVENT7 PORT EVENT 7 2242 // Can be used as a general 2243 // purpose IO event by selecting it through 2244 // registers in the EVENT module, for example 2245 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 2246 // and so on 2247 // PORT_EVENT6 PORT EVENT 6 2248 // Can be used as a general 2249 // purpose IO event by selecting it through 2250 // registers in the EVENT module, for example 2251 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 2252 // and so on 2253 // PORT_EVENT5 PORT EVENT 5 2254 // Can be used as a general 2255 // purpose IO event by selecting it through 2256 // registers in the EVENT module, for example 2257 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 2258 // and so on 2259 // PORT_EVENT4 PORT EVENT 4 2260 // Can be used as a general 2261 // purpose IO event by selecting it through 2262 // registers in the EVENT module, for example 2263 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 2264 // and so on 2265 // PORT_EVENT3 PORT EVENT 3 2266 // Can be used as a general 2267 // purpose IO event by selecting it through 2268 // registers in the EVENT module, for example 2269 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 2270 // and so on 2271 // PORT_EVENT2 PORT EVENT 2 2272 // Can be used as a general 2273 // purpose IO event by selecting it through 2274 // registers in the EVENT module, for example 2275 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 2276 // and so on 2277 // PORT_EVENT1 PORT EVENT 1 2278 // Can be used as a general 2279 // purpose IO event by selecting it through 2280 // registers in the EVENT module, for example 2281 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 2282 // and so on 2283 // PORT_EVENT0 PORT EVENT 0 2284 // Can be used as a general 2285 // purpose IO event by selecting it through 2286 // registers in the EVENT module, for example 2287 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 2288 // and so on 2289 // UART1_RTS UART1 RTS 2290 // UART1_CTS UART1 CTS 2291 // UART1_TX UART1 TX 2292 // UART1_RX UART1 RX 2293 // UART0_RTS UART0 RTS 2294 // UART0_CTS UART0 CTS 2295 // UART0_TX UART0 TX 2296 // UART0_RX UART0 RX 2297 // I2C_MSSCL I2C Clock 2298 // I2C_MSSDA I2C Data 2299 // SSI0_CLK SSI0 CLK 2300 // SSI0_FSS SSI0 FSS 2301 // SSI0_TX SSI0 TX 2302 // SSI0_RX SSI0 RX 2303 // AUX_IO AUX IO 2304 // AON_CLK32K AON 32 KHz clock (SCLK_LF) 2305 // GPIO General Purpose IO 2306 #define IOC_IOCFG5_PORT_ID_W 6 2307 #define IOC_IOCFG5_PORT_ID_M 0x0000003F 2308 #define IOC_IOCFG5_PORT_ID_S 0 2309 #define IOC_IOCFG5_PORT_ID_RFC_SMI_CL_IN 0x00000038 2310 #define IOC_IOCFG5_PORT_ID_RFC_SMI_CL_OUT 0x00000037 2311 #define IOC_IOCFG5_PORT_ID_RFC_SMI_DL_IN 0x00000036 2312 #define IOC_IOCFG5_PORT_ID_RFC_SMI_DL_OUT 0x00000035 2313 #define IOC_IOCFG5_PORT_ID_RFC_GPI1 0x00000034 2314 #define IOC_IOCFG5_PORT_ID_RFC_GPI0 0x00000033 2315 #define IOC_IOCFG5_PORT_ID_RFC_GPO3 0x00000032 2316 #define IOC_IOCFG5_PORT_ID_RFC_GPO2 0x00000031 2317 #define IOC_IOCFG5_PORT_ID_RFC_GPO1 0x00000030 2318 #define IOC_IOCFG5_PORT_ID_RFC_GPO0 0x0000002F 2319 #define IOC_IOCFG5_PORT_ID_RFC_TRC 0x0000002E 2320 #define IOC_IOCFG5_PORT_ID_I2S_MCLK 0x00000029 2321 #define IOC_IOCFG5_PORT_ID_I2S_BCLK 0x00000028 2322 #define IOC_IOCFG5_PORT_ID_I2S_WCLK 0x00000027 2323 #define IOC_IOCFG5_PORT_ID_I2S_AD1 0x00000026 2324 #define IOC_IOCFG5_PORT_ID_I2S_AD0 0x00000025 2325 #define IOC_IOCFG5_PORT_ID_SSI1_CLK 0x00000024 2326 #define IOC_IOCFG5_PORT_ID_SSI1_FSS 0x00000023 2327 #define IOC_IOCFG5_PORT_ID_SSI1_TX 0x00000022 2328 #define IOC_IOCFG5_PORT_ID_SSI1_RX 0x00000021 2329 #define IOC_IOCFG5_PORT_ID_CPU_SWV 0x00000020 2330 #define IOC_IOCFG5_PORT_ID_PORT_EVENT7 0x0000001E 2331 #define IOC_IOCFG5_PORT_ID_PORT_EVENT6 0x0000001D 2332 #define IOC_IOCFG5_PORT_ID_PORT_EVENT5 0x0000001C 2333 #define IOC_IOCFG5_PORT_ID_PORT_EVENT4 0x0000001B 2334 #define IOC_IOCFG5_PORT_ID_PORT_EVENT3 0x0000001A 2335 #define IOC_IOCFG5_PORT_ID_PORT_EVENT2 0x00000019 2336 #define IOC_IOCFG5_PORT_ID_PORT_EVENT1 0x00000018 2337 #define IOC_IOCFG5_PORT_ID_PORT_EVENT0 0x00000017 2338 #define IOC_IOCFG5_PORT_ID_UART1_RTS 0x00000016 2339 #define IOC_IOCFG5_PORT_ID_UART1_CTS 0x00000015 2340 #define IOC_IOCFG5_PORT_ID_UART1_TX 0x00000014 2341 #define IOC_IOCFG5_PORT_ID_UART1_RX 0x00000013 2342 #define IOC_IOCFG5_PORT_ID_UART0_RTS 0x00000012 2343 #define IOC_IOCFG5_PORT_ID_UART0_CTS 0x00000011 2344 #define IOC_IOCFG5_PORT_ID_UART0_TX 0x00000010 2345 #define IOC_IOCFG5_PORT_ID_UART0_RX 0x0000000F 2346 #define IOC_IOCFG5_PORT_ID_I2C_MSSCL 0x0000000E 2347 #define IOC_IOCFG5_PORT_ID_I2C_MSSDA 0x0000000D 2348 #define IOC_IOCFG5_PORT_ID_SSI0_CLK 0x0000000C 2349 #define IOC_IOCFG5_PORT_ID_SSI0_FSS 0x0000000B 2350 #define IOC_IOCFG5_PORT_ID_SSI0_TX 0x0000000A 2351 #define IOC_IOCFG5_PORT_ID_SSI0_RX 0x00000009 2352 #define IOC_IOCFG5_PORT_ID_AUX_IO 0x00000008 2353 #define IOC_IOCFG5_PORT_ID_AON_CLK32K 0x00000007 2354 #define IOC_IOCFG5_PORT_ID_GPIO 0x00000000 2355 2356 //***************************************************************************** 2357 // 2358 // Register: IOC_O_IOCFG6 2359 // 2360 //***************************************************************************** 2361 // Field: [30] HYST_EN 2362 // 2363 // 0: Input hysteresis disable 2364 // 1: Input hysteresis enable 2365 #define IOC_IOCFG6_HYST_EN 0x40000000 2366 #define IOC_IOCFG6_HYST_EN_BITN 30 2367 #define IOC_IOCFG6_HYST_EN_M 0x40000000 2368 #define IOC_IOCFG6_HYST_EN_S 30 2369 2370 // Field: [29] IE 2371 // 2372 // 0: Input disabled 2373 // 1: Input enabled 2374 // 2375 // Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be 2376 // ignored. 2377 #define IOC_IOCFG6_IE 0x20000000 2378 #define IOC_IOCFG6_IE_BITN 29 2379 #define IOC_IOCFG6_IE_M 0x20000000 2380 #define IOC_IOCFG6_IE_S 29 2381 2382 // Field: [28:27] WU_CFG 2383 // 2384 // If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or 2385 // >0x08: 2386 // 2387 // 00: No wake-up 2388 // 01: No wake-up 2389 // 10: Wakes up from shutdown if this pad is going low. 2390 // 11: Wakes up from shutdown if this pad is going high. 2391 // 2392 // If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, 2393 // this register only sets wakeup enable or not. 2394 // 2395 // 00, 01: Wakeup disabled 2396 // 10, 11: Wakeup enabled 2397 // 2398 // Polarity is controlled from AON registers. 2399 // 2400 // Note:When the MSB is set, the IOC will deactivate the output enable for the 2401 // DIO. 2402 #define IOC_IOCFG6_WU_CFG_W 2 2403 #define IOC_IOCFG6_WU_CFG_M 0x18000000 2404 #define IOC_IOCFG6_WU_CFG_S 27 2405 2406 // Field: [26:24] IOMODE 2407 // 2408 // IO Mode 2409 // Not applicable for IO configured for AON periph. signals and AUX PORT_ID 2410 // 0x01-0x08 2411 // AUX has its own open_source/drain configuration. 2412 // 2413 // 0x2: Reserved. Undefined behavior. 2414 // 0x3: Reserved. Undefined behavior. 2415 // ENUMs: 2416 // OPENSRC_INV Open Source 2417 // Inverted input / output 2418 // OPENSRC Open Source 2419 // Normal input / output 2420 // OPENDR_INV Open Drain 2421 // Inverted input / output 2422 // OPENDR Open Drain, 2423 // Normal input / output 2424 // INV Inverted input / ouput 2425 // NORMAL Normal input / output 2426 #define IOC_IOCFG6_IOMODE_W 3 2427 #define IOC_IOCFG6_IOMODE_M 0x07000000 2428 #define IOC_IOCFG6_IOMODE_S 24 2429 #define IOC_IOCFG6_IOMODE_OPENSRC_INV 0x07000000 2430 #define IOC_IOCFG6_IOMODE_OPENSRC 0x06000000 2431 #define IOC_IOCFG6_IOMODE_OPENDR_INV 0x05000000 2432 #define IOC_IOCFG6_IOMODE_OPENDR 0x04000000 2433 #define IOC_IOCFG6_IOMODE_INV 0x01000000 2434 #define IOC_IOCFG6_IOMODE_NORMAL 0x00000000 2435 2436 // Field: [23] IOEV_AON_PROG2_EN 2437 // 2438 // Event asserted by this IO when edge detection is enabled 2439 // 2440 // 0: Input edge detection does not assert AON_PROG2 event 2441 // 1: Input edge detection asserts AON_PROG2 event 2442 #define IOC_IOCFG6_IOEV_AON_PROG2_EN 0x00800000 2443 #define IOC_IOCFG6_IOEV_AON_PROG2_EN_BITN 23 2444 #define IOC_IOCFG6_IOEV_AON_PROG2_EN_M 0x00800000 2445 #define IOC_IOCFG6_IOEV_AON_PROG2_EN_S 23 2446 2447 // Field: [22] IOEV_AON_PROG1_EN 2448 // 2449 // Event asserted by this IO when edge detection is enabled 2450 // 2451 // 0: Input edge detection does not assert AON_PROG1 event 2452 // 1: Input edge detection asserts AON_PROG1 event 2453 #define IOC_IOCFG6_IOEV_AON_PROG1_EN 0x00400000 2454 #define IOC_IOCFG6_IOEV_AON_PROG1_EN_BITN 22 2455 #define IOC_IOCFG6_IOEV_AON_PROG1_EN_M 0x00400000 2456 #define IOC_IOCFG6_IOEV_AON_PROG1_EN_S 22 2457 2458 // Field: [21] IOEV_AON_PROG0_EN 2459 // 2460 // Event asserted by this IO when edge detection is enabled 2461 // 2462 // 0: Input edge detection does not assert AON_PROG0 event 2463 // 1: Input edge detection asserts AON_PROG0 event 2464 #define IOC_IOCFG6_IOEV_AON_PROG0_EN 0x00200000 2465 #define IOC_IOCFG6_IOEV_AON_PROG0_EN_BITN 21 2466 #define IOC_IOCFG6_IOEV_AON_PROG0_EN_M 0x00200000 2467 #define IOC_IOCFG6_IOEV_AON_PROG0_EN_S 21 2468 2469 // Field: [18] EDGE_IRQ_EN 2470 // 2471 // 0: No interrupt generation 2472 // 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is 2473 // enabled) 2474 #define IOC_IOCFG6_EDGE_IRQ_EN 0x00040000 2475 #define IOC_IOCFG6_EDGE_IRQ_EN_BITN 18 2476 #define IOC_IOCFG6_EDGE_IRQ_EN_M 0x00040000 2477 #define IOC_IOCFG6_EDGE_IRQ_EN_S 18 2478 2479 // Field: [17:16] EDGE_DET 2480 // 2481 // Enable generation of edge detection events on this IO 2482 // ENUMs: 2483 // BOTH Positive and negative edge detection 2484 // POS Positive edge detection 2485 // NEG Negative edge detection 2486 // NONE No edge detection 2487 #define IOC_IOCFG6_EDGE_DET_W 2 2488 #define IOC_IOCFG6_EDGE_DET_M 0x00030000 2489 #define IOC_IOCFG6_EDGE_DET_S 16 2490 #define IOC_IOCFG6_EDGE_DET_BOTH 0x00030000 2491 #define IOC_IOCFG6_EDGE_DET_POS 0x00020000 2492 #define IOC_IOCFG6_EDGE_DET_NEG 0x00010000 2493 #define IOC_IOCFG6_EDGE_DET_NONE 0x00000000 2494 2495 // Field: [14:13] PULL_CTL 2496 // 2497 // Pull control 2498 // ENUMs: 2499 // DIS No pull 2500 // UP Pull up 2501 // DWN Pull down 2502 #define IOC_IOCFG6_PULL_CTL_W 2 2503 #define IOC_IOCFG6_PULL_CTL_M 0x00006000 2504 #define IOC_IOCFG6_PULL_CTL_S 13 2505 #define IOC_IOCFG6_PULL_CTL_DIS 0x00006000 2506 #define IOC_IOCFG6_PULL_CTL_UP 0x00004000 2507 #define IOC_IOCFG6_PULL_CTL_DWN 0x00002000 2508 2509 // Field: [12] SLEW_RED 2510 // 2511 // 0: Normal slew rate 2512 // 1: Enables reduced slew rate in output driver. 2513 #define IOC_IOCFG6_SLEW_RED 0x00001000 2514 #define IOC_IOCFG6_SLEW_RED_BITN 12 2515 #define IOC_IOCFG6_SLEW_RED_M 0x00001000 2516 #define IOC_IOCFG6_SLEW_RED_S 12 2517 2518 // Field: [11:10] IOCURR 2519 // 2520 // Selects IO current mode of this IO. 2521 // ENUMs: 2522 // 4_8MA Extended-Current (EC) mode: Min 8 mA for double 2523 // drive strength IOs (min 4 mA for normal IOs) 2524 // when IOSTR is set to AUTO 2525 // 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set 2526 // to AUTO 2527 // 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set 2528 // to AUTO 2529 #define IOC_IOCFG6_IOCURR_W 2 2530 #define IOC_IOCFG6_IOCURR_M 0x00000C00 2531 #define IOC_IOCFG6_IOCURR_S 10 2532 #define IOC_IOCFG6_IOCURR_4_8MA 0x00000800 2533 #define IOC_IOCFG6_IOCURR_4MA 0x00000400 2534 #define IOC_IOCFG6_IOCURR_2MA 0x00000000 2535 2536 // Field: [9:8] IOSTR 2537 // 2538 // Select source for drive strength control of this IO. 2539 // This setting controls the drive strength of the Low-Current (LC) mode. 2540 // Higher drive strength can be selected in IOCURR 2541 // ENUMs: 2542 // MAX Maximum drive strength, controlled by 2543 // AON_IOC:IOSTRMAX (min 2 mA @1.8V with default 2544 // values) 2545 // MED Medium drive strength, controlled by 2546 // AON_IOC:IOSTRMED (min 2 mA @2.5V with default 2547 // values) 2548 // MIN Minimum drive strength, controlled by 2549 // AON_IOC:IOSTRMIN (min 2 mA @3.3V with default 2550 // values) 2551 // AUTO Automatic drive strength, controlled by AON BATMON 2552 // based on battery voltage. (min 2 mA @VDDS) 2553 #define IOC_IOCFG6_IOSTR_W 2 2554 #define IOC_IOCFG6_IOSTR_M 0x00000300 2555 #define IOC_IOCFG6_IOSTR_S 8 2556 #define IOC_IOCFG6_IOSTR_MAX 0x00000300 2557 #define IOC_IOCFG6_IOSTR_MED 0x00000200 2558 #define IOC_IOCFG6_IOSTR_MIN 0x00000100 2559 #define IOC_IOCFG6_IOSTR_AUTO 0x00000000 2560 2561 // Field: [7] IOEV_RTC_EN 2562 // 2563 // Event asserted by this IO when edge detection is enabled 2564 // 2565 // 0: Input edge detection does not assert RTC event 2566 // 1: Input edge detection asserts RTC event 2567 #define IOC_IOCFG6_IOEV_RTC_EN 0x00000080 2568 #define IOC_IOCFG6_IOEV_RTC_EN_BITN 7 2569 #define IOC_IOCFG6_IOEV_RTC_EN_M 0x00000080 2570 #define IOC_IOCFG6_IOEV_RTC_EN_S 7 2571 2572 // Field: [6] IOEV_MCU_WU_EN 2573 // 2574 // Event asserted by this IO when edge detection is enabled 2575 // 2576 // 0: Input edge detection does not assert MCU_WU event 2577 // 1: Input edge detection asserts MCU_WU event 2578 #define IOC_IOCFG6_IOEV_MCU_WU_EN 0x00000040 2579 #define IOC_IOCFG6_IOEV_MCU_WU_EN_BITN 6 2580 #define IOC_IOCFG6_IOEV_MCU_WU_EN_M 0x00000040 2581 #define IOC_IOCFG6_IOEV_MCU_WU_EN_S 6 2582 2583 // Field: [5:0] PORT_ID 2584 // 2585 // Selects usage for DIO6 2586 // Note: This field should not be written other than the times when PORT_ID 2587 // value is specifically required to change. 2588 // ENUMs: 2589 // RFC_SMI_CL_IN RF Core SMI Command Link In 2590 // RFC_SMI_CL_OUT RF Core SMI Command Link Out 2591 // RFC_SMI_DL_IN RF Core SMI Data Link In 2592 // RFC_SMI_DL_OUT RF Core SMI Data Link Out 2593 // RFC_GPI1 RF Core Data In 1 2594 // RFC_GPI0 RF Core Data In 0 2595 // RFC_GPO3 RF Core Data Out 3 2596 // RFC_GPO2 RF Core Data Out 2 2597 // RFC_GPO1 RF Core Data Out 1 2598 // RFC_GPO0 RF Core Data Out 0 2599 // RFC_TRC RF Core Trace 2600 // I2S_MCLK I2S MCLK 2601 // I2S_BCLK I2S BCLK 2602 // I2S_WCLK I2S WCLK 2603 // I2S_AD1 I2S Data 1 2604 // I2S_AD0 I2S Data 0 2605 // SSI1_CLK SSI1 CLK 2606 // SSI1_FSS SSI1 FSS 2607 // SSI1_TX SSI1 TX 2608 // SSI1_RX SSI1 RX 2609 // CPU_SWV CPU SWV 2610 // PORT_EVENT7 PORT EVENT 7 2611 // Can be used as a general 2612 // purpose IO event by selecting it through 2613 // registers in the EVENT module, for example 2614 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 2615 // and so on 2616 // PORT_EVENT6 PORT EVENT 6 2617 // Can be used as a general 2618 // purpose IO event by selecting it through 2619 // registers in the EVENT module, for example 2620 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 2621 // and so on 2622 // PORT_EVENT5 PORT EVENT 5 2623 // Can be used as a general 2624 // purpose IO event by selecting it through 2625 // registers in the EVENT module, for example 2626 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 2627 // and so on 2628 // PORT_EVENT4 PORT EVENT 4 2629 // Can be used as a general 2630 // purpose IO event by selecting it through 2631 // registers in the EVENT module, for example 2632 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 2633 // and so on 2634 // PORT_EVENT3 PORT EVENT 3 2635 // Can be used as a general 2636 // purpose IO event by selecting it through 2637 // registers in the EVENT module, for example 2638 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 2639 // and so on 2640 // PORT_EVENT2 PORT EVENT 2 2641 // Can be used as a general 2642 // purpose IO event by selecting it through 2643 // registers in the EVENT module, for example 2644 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 2645 // and so on 2646 // PORT_EVENT1 PORT EVENT 1 2647 // Can be used as a general 2648 // purpose IO event by selecting it through 2649 // registers in the EVENT module, for example 2650 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 2651 // and so on 2652 // PORT_EVENT0 PORT EVENT 0 2653 // Can be used as a general 2654 // purpose IO event by selecting it through 2655 // registers in the EVENT module, for example 2656 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 2657 // and so on 2658 // UART1_RTS UART1 RTS 2659 // UART1_CTS UART1 CTS 2660 // UART1_TX UART1 TX 2661 // UART1_RX UART1 RX 2662 // UART0_RTS UART0 RTS 2663 // UART0_CTS UART0 CTS 2664 // UART0_TX UART0 TX 2665 // UART0_RX UART0 RX 2666 // I2C_MSSCL I2C Clock 2667 // I2C_MSSDA I2C Data 2668 // SSI0_CLK SSI0 CLK 2669 // SSI0_FSS SSI0 FSS 2670 // SSI0_TX SSI0 TX 2671 // SSI0_RX SSI0 RX 2672 // AUX_IO AUX IO 2673 // AON_CLK32K AON 32 KHz clock (SCLK_LF) 2674 // GPIO General Purpose IO 2675 #define IOC_IOCFG6_PORT_ID_W 6 2676 #define IOC_IOCFG6_PORT_ID_M 0x0000003F 2677 #define IOC_IOCFG6_PORT_ID_S 0 2678 #define IOC_IOCFG6_PORT_ID_RFC_SMI_CL_IN 0x00000038 2679 #define IOC_IOCFG6_PORT_ID_RFC_SMI_CL_OUT 0x00000037 2680 #define IOC_IOCFG6_PORT_ID_RFC_SMI_DL_IN 0x00000036 2681 #define IOC_IOCFG6_PORT_ID_RFC_SMI_DL_OUT 0x00000035 2682 #define IOC_IOCFG6_PORT_ID_RFC_GPI1 0x00000034 2683 #define IOC_IOCFG6_PORT_ID_RFC_GPI0 0x00000033 2684 #define IOC_IOCFG6_PORT_ID_RFC_GPO3 0x00000032 2685 #define IOC_IOCFG6_PORT_ID_RFC_GPO2 0x00000031 2686 #define IOC_IOCFG6_PORT_ID_RFC_GPO1 0x00000030 2687 #define IOC_IOCFG6_PORT_ID_RFC_GPO0 0x0000002F 2688 #define IOC_IOCFG6_PORT_ID_RFC_TRC 0x0000002E 2689 #define IOC_IOCFG6_PORT_ID_I2S_MCLK 0x00000029 2690 #define IOC_IOCFG6_PORT_ID_I2S_BCLK 0x00000028 2691 #define IOC_IOCFG6_PORT_ID_I2S_WCLK 0x00000027 2692 #define IOC_IOCFG6_PORT_ID_I2S_AD1 0x00000026 2693 #define IOC_IOCFG6_PORT_ID_I2S_AD0 0x00000025 2694 #define IOC_IOCFG6_PORT_ID_SSI1_CLK 0x00000024 2695 #define IOC_IOCFG6_PORT_ID_SSI1_FSS 0x00000023 2696 #define IOC_IOCFG6_PORT_ID_SSI1_TX 0x00000022 2697 #define IOC_IOCFG6_PORT_ID_SSI1_RX 0x00000021 2698 #define IOC_IOCFG6_PORT_ID_CPU_SWV 0x00000020 2699 #define IOC_IOCFG6_PORT_ID_PORT_EVENT7 0x0000001E 2700 #define IOC_IOCFG6_PORT_ID_PORT_EVENT6 0x0000001D 2701 #define IOC_IOCFG6_PORT_ID_PORT_EVENT5 0x0000001C 2702 #define IOC_IOCFG6_PORT_ID_PORT_EVENT4 0x0000001B 2703 #define IOC_IOCFG6_PORT_ID_PORT_EVENT3 0x0000001A 2704 #define IOC_IOCFG6_PORT_ID_PORT_EVENT2 0x00000019 2705 #define IOC_IOCFG6_PORT_ID_PORT_EVENT1 0x00000018 2706 #define IOC_IOCFG6_PORT_ID_PORT_EVENT0 0x00000017 2707 #define IOC_IOCFG6_PORT_ID_UART1_RTS 0x00000016 2708 #define IOC_IOCFG6_PORT_ID_UART1_CTS 0x00000015 2709 #define IOC_IOCFG6_PORT_ID_UART1_TX 0x00000014 2710 #define IOC_IOCFG6_PORT_ID_UART1_RX 0x00000013 2711 #define IOC_IOCFG6_PORT_ID_UART0_RTS 0x00000012 2712 #define IOC_IOCFG6_PORT_ID_UART0_CTS 0x00000011 2713 #define IOC_IOCFG6_PORT_ID_UART0_TX 0x00000010 2714 #define IOC_IOCFG6_PORT_ID_UART0_RX 0x0000000F 2715 #define IOC_IOCFG6_PORT_ID_I2C_MSSCL 0x0000000E 2716 #define IOC_IOCFG6_PORT_ID_I2C_MSSDA 0x0000000D 2717 #define IOC_IOCFG6_PORT_ID_SSI0_CLK 0x0000000C 2718 #define IOC_IOCFG6_PORT_ID_SSI0_FSS 0x0000000B 2719 #define IOC_IOCFG6_PORT_ID_SSI0_TX 0x0000000A 2720 #define IOC_IOCFG6_PORT_ID_SSI0_RX 0x00000009 2721 #define IOC_IOCFG6_PORT_ID_AUX_IO 0x00000008 2722 #define IOC_IOCFG6_PORT_ID_AON_CLK32K 0x00000007 2723 #define IOC_IOCFG6_PORT_ID_GPIO 0x00000000 2724 2725 //***************************************************************************** 2726 // 2727 // Register: IOC_O_IOCFG7 2728 // 2729 //***************************************************************************** 2730 // Field: [30] HYST_EN 2731 // 2732 // 0: Input hysteresis disable 2733 // 1: Input hysteresis enable 2734 #define IOC_IOCFG7_HYST_EN 0x40000000 2735 #define IOC_IOCFG7_HYST_EN_BITN 30 2736 #define IOC_IOCFG7_HYST_EN_M 0x40000000 2737 #define IOC_IOCFG7_HYST_EN_S 30 2738 2739 // Field: [29] IE 2740 // 2741 // 0: Input disabled 2742 // 1: Input enabled 2743 // 2744 // Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be 2745 // ignored. 2746 #define IOC_IOCFG7_IE 0x20000000 2747 #define IOC_IOCFG7_IE_BITN 29 2748 #define IOC_IOCFG7_IE_M 0x20000000 2749 #define IOC_IOCFG7_IE_S 29 2750 2751 // Field: [28:27] WU_CFG 2752 // 2753 // If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or 2754 // >0x08: 2755 // 2756 // 00: No wake-up 2757 // 01: No wake-up 2758 // 10: Wakes up from shutdown if this pad is going low. 2759 // 11: Wakes up from shutdown if this pad is going high. 2760 // 2761 // If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, 2762 // this register only sets wakeup enable or not. 2763 // 2764 // 00, 01: Wakeup disabled 2765 // 10, 11: Wakeup enabled 2766 // 2767 // Polarity is controlled from AON registers. 2768 // 2769 // Note:When the MSB is set, the IOC will deactivate the output enable for the 2770 // DIO. 2771 #define IOC_IOCFG7_WU_CFG_W 2 2772 #define IOC_IOCFG7_WU_CFG_M 0x18000000 2773 #define IOC_IOCFG7_WU_CFG_S 27 2774 2775 // Field: [26:24] IOMODE 2776 // 2777 // IO Mode 2778 // Not applicable for IO configured for AON periph. signals and AUX PORT_ID 2779 // 0x01-0x08 2780 // AUX has its own open_source/drain configuration. 2781 // 2782 // 0x2: Reserved. Undefined behavior. 2783 // 0x3: Reserved. Undefined behavior. 2784 // ENUMs: 2785 // OPENSRC_INV Open Source 2786 // Inverted input / output 2787 // OPENSRC Open Source 2788 // Normal input / output 2789 // OPENDR_INV Open Drain 2790 // Inverted input / output 2791 // OPENDR Open Drain, 2792 // Normal input / output 2793 // INV Inverted input / ouput 2794 // NORMAL Normal input / output 2795 #define IOC_IOCFG7_IOMODE_W 3 2796 #define IOC_IOCFG7_IOMODE_M 0x07000000 2797 #define IOC_IOCFG7_IOMODE_S 24 2798 #define IOC_IOCFG7_IOMODE_OPENSRC_INV 0x07000000 2799 #define IOC_IOCFG7_IOMODE_OPENSRC 0x06000000 2800 #define IOC_IOCFG7_IOMODE_OPENDR_INV 0x05000000 2801 #define IOC_IOCFG7_IOMODE_OPENDR 0x04000000 2802 #define IOC_IOCFG7_IOMODE_INV 0x01000000 2803 #define IOC_IOCFG7_IOMODE_NORMAL 0x00000000 2804 2805 // Field: [23] IOEV_AON_PROG2_EN 2806 // 2807 // Event asserted by this IO when edge detection is enabled 2808 // 2809 // 0: Input edge detection does not assert AON_PROG2 event 2810 // 1: Input edge detection asserts AON_PROG2 event 2811 #define IOC_IOCFG7_IOEV_AON_PROG2_EN 0x00800000 2812 #define IOC_IOCFG7_IOEV_AON_PROG2_EN_BITN 23 2813 #define IOC_IOCFG7_IOEV_AON_PROG2_EN_M 0x00800000 2814 #define IOC_IOCFG7_IOEV_AON_PROG2_EN_S 23 2815 2816 // Field: [22] IOEV_AON_PROG1_EN 2817 // 2818 // Event asserted by this IO when edge detection is enabled 2819 // 2820 // 0: Input edge detection does not assert AON_PROG1 event 2821 // 1: Input edge detection asserts AON_PROG1 event 2822 #define IOC_IOCFG7_IOEV_AON_PROG1_EN 0x00400000 2823 #define IOC_IOCFG7_IOEV_AON_PROG1_EN_BITN 22 2824 #define IOC_IOCFG7_IOEV_AON_PROG1_EN_M 0x00400000 2825 #define IOC_IOCFG7_IOEV_AON_PROG1_EN_S 22 2826 2827 // Field: [21] IOEV_AON_PROG0_EN 2828 // 2829 // Event asserted by this IO when edge detection is enabled 2830 // 2831 // 0: Input edge detection does not assert AON_PROG0 event 2832 // 1: Input edge detection asserts AON_PROG0 event 2833 #define IOC_IOCFG7_IOEV_AON_PROG0_EN 0x00200000 2834 #define IOC_IOCFG7_IOEV_AON_PROG0_EN_BITN 21 2835 #define IOC_IOCFG7_IOEV_AON_PROG0_EN_M 0x00200000 2836 #define IOC_IOCFG7_IOEV_AON_PROG0_EN_S 21 2837 2838 // Field: [18] EDGE_IRQ_EN 2839 // 2840 // 0: No interrupt generation 2841 // 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is 2842 // enabled) 2843 #define IOC_IOCFG7_EDGE_IRQ_EN 0x00040000 2844 #define IOC_IOCFG7_EDGE_IRQ_EN_BITN 18 2845 #define IOC_IOCFG7_EDGE_IRQ_EN_M 0x00040000 2846 #define IOC_IOCFG7_EDGE_IRQ_EN_S 18 2847 2848 // Field: [17:16] EDGE_DET 2849 // 2850 // Enable generation of edge detection events on this IO 2851 // ENUMs: 2852 // BOTH Positive and negative edge detection 2853 // POS Positive edge detection 2854 // NEG Negative edge detection 2855 // NONE No edge detection 2856 #define IOC_IOCFG7_EDGE_DET_W 2 2857 #define IOC_IOCFG7_EDGE_DET_M 0x00030000 2858 #define IOC_IOCFG7_EDGE_DET_S 16 2859 #define IOC_IOCFG7_EDGE_DET_BOTH 0x00030000 2860 #define IOC_IOCFG7_EDGE_DET_POS 0x00020000 2861 #define IOC_IOCFG7_EDGE_DET_NEG 0x00010000 2862 #define IOC_IOCFG7_EDGE_DET_NONE 0x00000000 2863 2864 // Field: [14:13] PULL_CTL 2865 // 2866 // Pull control 2867 // ENUMs: 2868 // DIS No pull 2869 // UP Pull up 2870 // DWN Pull down 2871 #define IOC_IOCFG7_PULL_CTL_W 2 2872 #define IOC_IOCFG7_PULL_CTL_M 0x00006000 2873 #define IOC_IOCFG7_PULL_CTL_S 13 2874 #define IOC_IOCFG7_PULL_CTL_DIS 0x00006000 2875 #define IOC_IOCFG7_PULL_CTL_UP 0x00004000 2876 #define IOC_IOCFG7_PULL_CTL_DWN 0x00002000 2877 2878 // Field: [12] SLEW_RED 2879 // 2880 // 0: Normal slew rate 2881 // 1: Enables reduced slew rate in output driver. 2882 #define IOC_IOCFG7_SLEW_RED 0x00001000 2883 #define IOC_IOCFG7_SLEW_RED_BITN 12 2884 #define IOC_IOCFG7_SLEW_RED_M 0x00001000 2885 #define IOC_IOCFG7_SLEW_RED_S 12 2886 2887 // Field: [11:10] IOCURR 2888 // 2889 // Selects IO current mode of this IO. 2890 // ENUMs: 2891 // 4_8MA Extended-Current (EC) mode: Min 8 mA for double 2892 // drive strength IOs (min 4 mA for normal IOs) 2893 // when IOSTR is set to AUTO 2894 // 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set 2895 // to AUTO 2896 // 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set 2897 // to AUTO 2898 #define IOC_IOCFG7_IOCURR_W 2 2899 #define IOC_IOCFG7_IOCURR_M 0x00000C00 2900 #define IOC_IOCFG7_IOCURR_S 10 2901 #define IOC_IOCFG7_IOCURR_4_8MA 0x00000800 2902 #define IOC_IOCFG7_IOCURR_4MA 0x00000400 2903 #define IOC_IOCFG7_IOCURR_2MA 0x00000000 2904 2905 // Field: [9:8] IOSTR 2906 // 2907 // Select source for drive strength control of this IO. 2908 // This setting controls the drive strength of the Low-Current (LC) mode. 2909 // Higher drive strength can be selected in IOCURR 2910 // ENUMs: 2911 // MAX Maximum drive strength, controlled by 2912 // AON_IOC:IOSTRMAX (min 2 mA @1.8V with default 2913 // values) 2914 // MED Medium drive strength, controlled by 2915 // AON_IOC:IOSTRMED (min 2 mA @2.5V with default 2916 // values) 2917 // MIN Minimum drive strength, controlled by 2918 // AON_IOC:IOSTRMIN (min 2 mA @3.3V with default 2919 // values) 2920 // AUTO Automatic drive strength, controlled by AON BATMON 2921 // based on battery voltage. (min 2 mA @VDDS) 2922 #define IOC_IOCFG7_IOSTR_W 2 2923 #define IOC_IOCFG7_IOSTR_M 0x00000300 2924 #define IOC_IOCFG7_IOSTR_S 8 2925 #define IOC_IOCFG7_IOSTR_MAX 0x00000300 2926 #define IOC_IOCFG7_IOSTR_MED 0x00000200 2927 #define IOC_IOCFG7_IOSTR_MIN 0x00000100 2928 #define IOC_IOCFG7_IOSTR_AUTO 0x00000000 2929 2930 // Field: [7] IOEV_RTC_EN 2931 // 2932 // Event asserted by this IO when edge detection is enabled 2933 // 2934 // 0: Input edge detection does not assert RTC event 2935 // 1: Input edge detection asserts RTC event 2936 #define IOC_IOCFG7_IOEV_RTC_EN 0x00000080 2937 #define IOC_IOCFG7_IOEV_RTC_EN_BITN 7 2938 #define IOC_IOCFG7_IOEV_RTC_EN_M 0x00000080 2939 #define IOC_IOCFG7_IOEV_RTC_EN_S 7 2940 2941 // Field: [6] IOEV_MCU_WU_EN 2942 // 2943 // Event asserted by this IO when edge detection is enabled 2944 // 2945 // 0: Input edge detection does not assert MCU_WU event 2946 // 1: Input edge detection asserts MCU_WU event 2947 #define IOC_IOCFG7_IOEV_MCU_WU_EN 0x00000040 2948 #define IOC_IOCFG7_IOEV_MCU_WU_EN_BITN 6 2949 #define IOC_IOCFG7_IOEV_MCU_WU_EN_M 0x00000040 2950 #define IOC_IOCFG7_IOEV_MCU_WU_EN_S 6 2951 2952 // Field: [5:0] PORT_ID 2953 // 2954 // Selects usage for DIO7 2955 // Note: This field should not be written other than the times when PORT_ID 2956 // value is specifically required to change. 2957 // ENUMs: 2958 // RFC_SMI_CL_IN RF Core SMI Command Link In 2959 // RFC_SMI_CL_OUT RF Core SMI Command Link Out 2960 // RFC_SMI_DL_IN RF Core SMI Data Link In 2961 // RFC_SMI_DL_OUT RF Core SMI Data Link Out 2962 // RFC_GPI1 RF Core Data In 1 2963 // RFC_GPI0 RF Core Data In 0 2964 // RFC_GPO3 RF Core Data Out 3 2965 // RFC_GPO2 RF Core Data Out 2 2966 // RFC_GPO1 RF Core Data Out 1 2967 // RFC_GPO0 RF Core Data Out 0 2968 // RFC_TRC RF Core Trace 2969 // I2S_MCLK I2S MCLK 2970 // I2S_BCLK I2S BCLK 2971 // I2S_WCLK I2S WCLK 2972 // I2S_AD1 I2S Data 1 2973 // I2S_AD0 I2S Data 0 2974 // SSI1_CLK SSI1 CLK 2975 // SSI1_FSS SSI1 FSS 2976 // SSI1_TX SSI1 TX 2977 // SSI1_RX SSI1 RX 2978 // CPU_SWV CPU SWV 2979 // PORT_EVENT7 PORT EVENT 7 2980 // Can be used as a general 2981 // purpose IO event by selecting it through 2982 // registers in the EVENT module, for example 2983 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 2984 // and so on 2985 // PORT_EVENT6 PORT EVENT 6 2986 // Can be used as a general 2987 // purpose IO event by selecting it through 2988 // registers in the EVENT module, for example 2989 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 2990 // and so on 2991 // PORT_EVENT5 PORT EVENT 5 2992 // Can be used as a general 2993 // purpose IO event by selecting it through 2994 // registers in the EVENT module, for example 2995 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 2996 // and so on 2997 // PORT_EVENT4 PORT EVENT 4 2998 // Can be used as a general 2999 // purpose IO event by selecting it through 3000 // registers in the EVENT module, for example 3001 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 3002 // and so on 3003 // PORT_EVENT3 PORT EVENT 3 3004 // Can be used as a general 3005 // purpose IO event by selecting it through 3006 // registers in the EVENT module, for example 3007 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 3008 // and so on 3009 // PORT_EVENT2 PORT EVENT 2 3010 // Can be used as a general 3011 // purpose IO event by selecting it through 3012 // registers in the EVENT module, for example 3013 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 3014 // and so on 3015 // PORT_EVENT1 PORT EVENT 1 3016 // Can be used as a general 3017 // purpose IO event by selecting it through 3018 // registers in the EVENT module, for example 3019 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 3020 // and so on 3021 // PORT_EVENT0 PORT EVENT 0 3022 // Can be used as a general 3023 // purpose IO event by selecting it through 3024 // registers in the EVENT module, for example 3025 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 3026 // and so on 3027 // UART1_RTS UART1 RTS 3028 // UART1_CTS UART1 CTS 3029 // UART1_TX UART1 TX 3030 // UART1_RX UART1 RX 3031 // UART0_RTS UART0 RTS 3032 // UART0_CTS UART0 CTS 3033 // UART0_TX UART0 TX 3034 // UART0_RX UART0 RX 3035 // I2C_MSSCL I2C Clock 3036 // I2C_MSSDA I2C Data 3037 // SSI0_CLK SSI0 CLK 3038 // SSI0_FSS SSI0 FSS 3039 // SSI0_TX SSI0 TX 3040 // SSI0_RX SSI0 RX 3041 // AUX_IO AUX IO 3042 // AON_CLK32K AON 32 KHz clock (SCLK_LF) 3043 // GPIO General Purpose IO 3044 #define IOC_IOCFG7_PORT_ID_W 6 3045 #define IOC_IOCFG7_PORT_ID_M 0x0000003F 3046 #define IOC_IOCFG7_PORT_ID_S 0 3047 #define IOC_IOCFG7_PORT_ID_RFC_SMI_CL_IN 0x00000038 3048 #define IOC_IOCFG7_PORT_ID_RFC_SMI_CL_OUT 0x00000037 3049 #define IOC_IOCFG7_PORT_ID_RFC_SMI_DL_IN 0x00000036 3050 #define IOC_IOCFG7_PORT_ID_RFC_SMI_DL_OUT 0x00000035 3051 #define IOC_IOCFG7_PORT_ID_RFC_GPI1 0x00000034 3052 #define IOC_IOCFG7_PORT_ID_RFC_GPI0 0x00000033 3053 #define IOC_IOCFG7_PORT_ID_RFC_GPO3 0x00000032 3054 #define IOC_IOCFG7_PORT_ID_RFC_GPO2 0x00000031 3055 #define IOC_IOCFG7_PORT_ID_RFC_GPO1 0x00000030 3056 #define IOC_IOCFG7_PORT_ID_RFC_GPO0 0x0000002F 3057 #define IOC_IOCFG7_PORT_ID_RFC_TRC 0x0000002E 3058 #define IOC_IOCFG7_PORT_ID_I2S_MCLK 0x00000029 3059 #define IOC_IOCFG7_PORT_ID_I2S_BCLK 0x00000028 3060 #define IOC_IOCFG7_PORT_ID_I2S_WCLK 0x00000027 3061 #define IOC_IOCFG7_PORT_ID_I2S_AD1 0x00000026 3062 #define IOC_IOCFG7_PORT_ID_I2S_AD0 0x00000025 3063 #define IOC_IOCFG7_PORT_ID_SSI1_CLK 0x00000024 3064 #define IOC_IOCFG7_PORT_ID_SSI1_FSS 0x00000023 3065 #define IOC_IOCFG7_PORT_ID_SSI1_TX 0x00000022 3066 #define IOC_IOCFG7_PORT_ID_SSI1_RX 0x00000021 3067 #define IOC_IOCFG7_PORT_ID_CPU_SWV 0x00000020 3068 #define IOC_IOCFG7_PORT_ID_PORT_EVENT7 0x0000001E 3069 #define IOC_IOCFG7_PORT_ID_PORT_EVENT6 0x0000001D 3070 #define IOC_IOCFG7_PORT_ID_PORT_EVENT5 0x0000001C 3071 #define IOC_IOCFG7_PORT_ID_PORT_EVENT4 0x0000001B 3072 #define IOC_IOCFG7_PORT_ID_PORT_EVENT3 0x0000001A 3073 #define IOC_IOCFG7_PORT_ID_PORT_EVENT2 0x00000019 3074 #define IOC_IOCFG7_PORT_ID_PORT_EVENT1 0x00000018 3075 #define IOC_IOCFG7_PORT_ID_PORT_EVENT0 0x00000017 3076 #define IOC_IOCFG7_PORT_ID_UART1_RTS 0x00000016 3077 #define IOC_IOCFG7_PORT_ID_UART1_CTS 0x00000015 3078 #define IOC_IOCFG7_PORT_ID_UART1_TX 0x00000014 3079 #define IOC_IOCFG7_PORT_ID_UART1_RX 0x00000013 3080 #define IOC_IOCFG7_PORT_ID_UART0_RTS 0x00000012 3081 #define IOC_IOCFG7_PORT_ID_UART0_CTS 0x00000011 3082 #define IOC_IOCFG7_PORT_ID_UART0_TX 0x00000010 3083 #define IOC_IOCFG7_PORT_ID_UART0_RX 0x0000000F 3084 #define IOC_IOCFG7_PORT_ID_I2C_MSSCL 0x0000000E 3085 #define IOC_IOCFG7_PORT_ID_I2C_MSSDA 0x0000000D 3086 #define IOC_IOCFG7_PORT_ID_SSI0_CLK 0x0000000C 3087 #define IOC_IOCFG7_PORT_ID_SSI0_FSS 0x0000000B 3088 #define IOC_IOCFG7_PORT_ID_SSI0_TX 0x0000000A 3089 #define IOC_IOCFG7_PORT_ID_SSI0_RX 0x00000009 3090 #define IOC_IOCFG7_PORT_ID_AUX_IO 0x00000008 3091 #define IOC_IOCFG7_PORT_ID_AON_CLK32K 0x00000007 3092 #define IOC_IOCFG7_PORT_ID_GPIO 0x00000000 3093 3094 //***************************************************************************** 3095 // 3096 // Register: IOC_O_IOCFG8 3097 // 3098 //***************************************************************************** 3099 // Field: [30] HYST_EN 3100 // 3101 // 0: Input hysteresis disable 3102 // 1: Input hysteresis enable 3103 #define IOC_IOCFG8_HYST_EN 0x40000000 3104 #define IOC_IOCFG8_HYST_EN_BITN 30 3105 #define IOC_IOCFG8_HYST_EN_M 0x40000000 3106 #define IOC_IOCFG8_HYST_EN_S 30 3107 3108 // Field: [29] IE 3109 // 3110 // 0: Input disabled 3111 // 1: Input enabled 3112 // 3113 // Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be 3114 // ignored. 3115 #define IOC_IOCFG8_IE 0x20000000 3116 #define IOC_IOCFG8_IE_BITN 29 3117 #define IOC_IOCFG8_IE_M 0x20000000 3118 #define IOC_IOCFG8_IE_S 29 3119 3120 // Field: [28:27] WU_CFG 3121 // 3122 // If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or 3123 // >0x08: 3124 // 3125 // 00: No wake-up 3126 // 01: No wake-up 3127 // 10: Wakes up from shutdown if this pad is going low. 3128 // 11: Wakes up from shutdown if this pad is going high. 3129 // 3130 // If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, 3131 // this register only sets wakeup enable or not. 3132 // 3133 // 00, 01: Wakeup disabled 3134 // 10, 11: Wakeup enabled 3135 // 3136 // Polarity is controlled from AON registers. 3137 // 3138 // Note:When the MSB is set, the IOC will deactivate the output enable for the 3139 // DIO. 3140 #define IOC_IOCFG8_WU_CFG_W 2 3141 #define IOC_IOCFG8_WU_CFG_M 0x18000000 3142 #define IOC_IOCFG8_WU_CFG_S 27 3143 3144 // Field: [26:24] IOMODE 3145 // 3146 // IO Mode 3147 // Not applicable for IO configured for AON periph. signals and AUX PORT_ID 3148 // 0x01-0x08 3149 // AUX has its own open_source/drain configuration. 3150 // 3151 // 0x2: Reserved. Undefined behavior. 3152 // 0x3: Reserved. Undefined behavior. 3153 // ENUMs: 3154 // OPENSRC_INV Open Source 3155 // Inverted input / output 3156 // OPENSRC Open Source 3157 // Normal input / output 3158 // OPENDR_INV Open Drain 3159 // Inverted input / output 3160 // OPENDR Open Drain, 3161 // Normal input / output 3162 // INV Inverted input / ouput 3163 // NORMAL Normal input / output 3164 #define IOC_IOCFG8_IOMODE_W 3 3165 #define IOC_IOCFG8_IOMODE_M 0x07000000 3166 #define IOC_IOCFG8_IOMODE_S 24 3167 #define IOC_IOCFG8_IOMODE_OPENSRC_INV 0x07000000 3168 #define IOC_IOCFG8_IOMODE_OPENSRC 0x06000000 3169 #define IOC_IOCFG8_IOMODE_OPENDR_INV 0x05000000 3170 #define IOC_IOCFG8_IOMODE_OPENDR 0x04000000 3171 #define IOC_IOCFG8_IOMODE_INV 0x01000000 3172 #define IOC_IOCFG8_IOMODE_NORMAL 0x00000000 3173 3174 // Field: [23] IOEV_AON_PROG2_EN 3175 // 3176 // Event asserted by this IO when edge detection is enabled 3177 // 3178 // 0: Input edge detection does not assert AON_PROG2 event 3179 // 1: Input edge detection asserts AON_PROG2 event 3180 #define IOC_IOCFG8_IOEV_AON_PROG2_EN 0x00800000 3181 #define IOC_IOCFG8_IOEV_AON_PROG2_EN_BITN 23 3182 #define IOC_IOCFG8_IOEV_AON_PROG2_EN_M 0x00800000 3183 #define IOC_IOCFG8_IOEV_AON_PROG2_EN_S 23 3184 3185 // Field: [22] IOEV_AON_PROG1_EN 3186 // 3187 // Event asserted by this IO when edge detection is enabled 3188 // 3189 // 0: Input edge detection does not assert AON_PROG1 event 3190 // 1: Input edge detection asserts AON_PROG1 event 3191 #define IOC_IOCFG8_IOEV_AON_PROG1_EN 0x00400000 3192 #define IOC_IOCFG8_IOEV_AON_PROG1_EN_BITN 22 3193 #define IOC_IOCFG8_IOEV_AON_PROG1_EN_M 0x00400000 3194 #define IOC_IOCFG8_IOEV_AON_PROG1_EN_S 22 3195 3196 // Field: [21] IOEV_AON_PROG0_EN 3197 // 3198 // Event asserted by this IO when edge detection is enabled 3199 // 3200 // 0: Input edge detection does not assert AON_PROG0 event 3201 // 1: Input edge detection asserts AON_PROG0 event 3202 #define IOC_IOCFG8_IOEV_AON_PROG0_EN 0x00200000 3203 #define IOC_IOCFG8_IOEV_AON_PROG0_EN_BITN 21 3204 #define IOC_IOCFG8_IOEV_AON_PROG0_EN_M 0x00200000 3205 #define IOC_IOCFG8_IOEV_AON_PROG0_EN_S 21 3206 3207 // Field: [18] EDGE_IRQ_EN 3208 // 3209 // 0: No interrupt generation 3210 // 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is 3211 // enabled) 3212 #define IOC_IOCFG8_EDGE_IRQ_EN 0x00040000 3213 #define IOC_IOCFG8_EDGE_IRQ_EN_BITN 18 3214 #define IOC_IOCFG8_EDGE_IRQ_EN_M 0x00040000 3215 #define IOC_IOCFG8_EDGE_IRQ_EN_S 18 3216 3217 // Field: [17:16] EDGE_DET 3218 // 3219 // Enable generation of edge detection events on this IO 3220 // ENUMs: 3221 // BOTH Positive and negative edge detection 3222 // POS Positive edge detection 3223 // NEG Negative edge detection 3224 // NONE No edge detection 3225 #define IOC_IOCFG8_EDGE_DET_W 2 3226 #define IOC_IOCFG8_EDGE_DET_M 0x00030000 3227 #define IOC_IOCFG8_EDGE_DET_S 16 3228 #define IOC_IOCFG8_EDGE_DET_BOTH 0x00030000 3229 #define IOC_IOCFG8_EDGE_DET_POS 0x00020000 3230 #define IOC_IOCFG8_EDGE_DET_NEG 0x00010000 3231 #define IOC_IOCFG8_EDGE_DET_NONE 0x00000000 3232 3233 // Field: [14:13] PULL_CTL 3234 // 3235 // Pull control 3236 // ENUMs: 3237 // DIS No pull 3238 // UP Pull up 3239 // DWN Pull down 3240 #define IOC_IOCFG8_PULL_CTL_W 2 3241 #define IOC_IOCFG8_PULL_CTL_M 0x00006000 3242 #define IOC_IOCFG8_PULL_CTL_S 13 3243 #define IOC_IOCFG8_PULL_CTL_DIS 0x00006000 3244 #define IOC_IOCFG8_PULL_CTL_UP 0x00004000 3245 #define IOC_IOCFG8_PULL_CTL_DWN 0x00002000 3246 3247 // Field: [12] SLEW_RED 3248 // 3249 // 0: Normal slew rate 3250 // 1: Enables reduced slew rate in output driver. 3251 #define IOC_IOCFG8_SLEW_RED 0x00001000 3252 #define IOC_IOCFG8_SLEW_RED_BITN 12 3253 #define IOC_IOCFG8_SLEW_RED_M 0x00001000 3254 #define IOC_IOCFG8_SLEW_RED_S 12 3255 3256 // Field: [11:10] IOCURR 3257 // 3258 // Selects IO current mode of this IO. 3259 // ENUMs: 3260 // 4_8MA Extended-Current (EC) mode: Min 8 mA for double 3261 // drive strength IOs (min 4 mA for normal IOs) 3262 // when IOSTR is set to AUTO 3263 // 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set 3264 // to AUTO 3265 // 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set 3266 // to AUTO 3267 #define IOC_IOCFG8_IOCURR_W 2 3268 #define IOC_IOCFG8_IOCURR_M 0x00000C00 3269 #define IOC_IOCFG8_IOCURR_S 10 3270 #define IOC_IOCFG8_IOCURR_4_8MA 0x00000800 3271 #define IOC_IOCFG8_IOCURR_4MA 0x00000400 3272 #define IOC_IOCFG8_IOCURR_2MA 0x00000000 3273 3274 // Field: [9:8] IOSTR 3275 // 3276 // Select source for drive strength control of this IO. 3277 // This setting controls the drive strength of the Low-Current (LC) mode. 3278 // Higher drive strength can be selected in IOCURR 3279 // ENUMs: 3280 // MAX Maximum drive strength, controlled by 3281 // AON_IOC:IOSTRMAX (min 2 mA @1.8V with default 3282 // values) 3283 // MED Medium drive strength, controlled by 3284 // AON_IOC:IOSTRMED (min 2 mA @2.5V with default 3285 // values) 3286 // MIN Minimum drive strength, controlled by 3287 // AON_IOC:IOSTRMIN (min 2 mA @3.3V with default 3288 // values) 3289 // AUTO Automatic drive strength, controlled by AON BATMON 3290 // based on battery voltage. (min 2 mA @VDDS) 3291 #define IOC_IOCFG8_IOSTR_W 2 3292 #define IOC_IOCFG8_IOSTR_M 0x00000300 3293 #define IOC_IOCFG8_IOSTR_S 8 3294 #define IOC_IOCFG8_IOSTR_MAX 0x00000300 3295 #define IOC_IOCFG8_IOSTR_MED 0x00000200 3296 #define IOC_IOCFG8_IOSTR_MIN 0x00000100 3297 #define IOC_IOCFG8_IOSTR_AUTO 0x00000000 3298 3299 // Field: [7] IOEV_RTC_EN 3300 // 3301 // Event asserted by this IO when edge detection is enabled 3302 // 3303 // 0: Input edge detection does not assert RTC event 3304 // 1: Input edge detection asserts RTC event 3305 #define IOC_IOCFG8_IOEV_RTC_EN 0x00000080 3306 #define IOC_IOCFG8_IOEV_RTC_EN_BITN 7 3307 #define IOC_IOCFG8_IOEV_RTC_EN_M 0x00000080 3308 #define IOC_IOCFG8_IOEV_RTC_EN_S 7 3309 3310 // Field: [6] IOEV_MCU_WU_EN 3311 // 3312 // Event asserted by this IO when edge detection is enabled 3313 // 3314 // 0: Input edge detection does not assert MCU_WU event 3315 // 1: Input edge detection asserts MCU_WU event 3316 #define IOC_IOCFG8_IOEV_MCU_WU_EN 0x00000040 3317 #define IOC_IOCFG8_IOEV_MCU_WU_EN_BITN 6 3318 #define IOC_IOCFG8_IOEV_MCU_WU_EN_M 0x00000040 3319 #define IOC_IOCFG8_IOEV_MCU_WU_EN_S 6 3320 3321 // Field: [5:0] PORT_ID 3322 // 3323 // Selects usage for DIO8 3324 // Note: This field should not be written other than the times when PORT_ID 3325 // value is specifically required to change. 3326 // ENUMs: 3327 // RFC_SMI_CL_IN RF Core SMI Command Link In 3328 // RFC_SMI_CL_OUT RF Core SMI Command Link Out 3329 // RFC_SMI_DL_IN RF Core SMI Data Link In 3330 // RFC_SMI_DL_OUT RF Core SMI Data Link Out 3331 // RFC_GPI1 RF Core Data In 1 3332 // RFC_GPI0 RF Core Data In 0 3333 // RFC_GPO3 RF Core Data Out 3 3334 // RFC_GPO2 RF Core Data Out 2 3335 // RFC_GPO1 RF Core Data Out 1 3336 // RFC_GPO0 RF Core Data Out 0 3337 // RFC_TRC RF Core Trace 3338 // I2S_MCLK I2S MCLK 3339 // I2S_BCLK I2S BCLK 3340 // I2S_WCLK I2S WCLK 3341 // I2S_AD1 I2S Data 1 3342 // I2S_AD0 I2S Data 0 3343 // SSI1_CLK SSI1 CLK 3344 // SSI1_FSS SSI1 FSS 3345 // SSI1_TX SSI1 TX 3346 // SSI1_RX SSI1 RX 3347 // CPU_SWV CPU SWV 3348 // PORT_EVENT7 PORT EVENT 7 3349 // Can be used as a general 3350 // purpose IO event by selecting it through 3351 // registers in the EVENT module, for example 3352 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 3353 // and so on 3354 // PORT_EVENT6 PORT EVENT 6 3355 // Can be used as a general 3356 // purpose IO event by selecting it through 3357 // registers in the EVENT module, for example 3358 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 3359 // and so on 3360 // PORT_EVENT5 PORT EVENT 5 3361 // Can be used as a general 3362 // purpose IO event by selecting it through 3363 // registers in the EVENT module, for example 3364 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 3365 // and so on 3366 // PORT_EVENT4 PORT EVENT 4 3367 // Can be used as a general 3368 // purpose IO event by selecting it through 3369 // registers in the EVENT module, for example 3370 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 3371 // and so on 3372 // PORT_EVENT3 PORT EVENT 3 3373 // Can be used as a general 3374 // purpose IO event by selecting it through 3375 // registers in the EVENT module, for example 3376 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 3377 // and so on 3378 // PORT_EVENT2 PORT EVENT 2 3379 // Can be used as a general 3380 // purpose IO event by selecting it through 3381 // registers in the EVENT module, for example 3382 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 3383 // and so on 3384 // PORT_EVENT1 PORT EVENT 1 3385 // Can be used as a general 3386 // purpose IO event by selecting it through 3387 // registers in the EVENT module, for example 3388 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 3389 // and so on 3390 // PORT_EVENT0 PORT EVENT 0 3391 // Can be used as a general 3392 // purpose IO event by selecting it through 3393 // registers in the EVENT module, for example 3394 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 3395 // and so on 3396 // UART1_RTS UART1 RTS 3397 // UART1_CTS UART1 CTS 3398 // UART1_TX UART1 TX 3399 // UART1_RX UART1 RX 3400 // UART0_RTS UART0 RTS 3401 // UART0_CTS UART0 CTS 3402 // UART0_TX UART0 TX 3403 // UART0_RX UART0 RX 3404 // I2C_MSSCL I2C Clock 3405 // I2C_MSSDA I2C Data 3406 // SSI0_CLK SSI0 CLK 3407 // SSI0_FSS SSI0 FSS 3408 // SSI0_TX SSI0 TX 3409 // SSI0_RX SSI0 RX 3410 // AUX_IO AUX IO 3411 // AON_CLK32K AON 32 KHz clock (SCLK_LF) 3412 // GPIO General Purpose IO 3413 #define IOC_IOCFG8_PORT_ID_W 6 3414 #define IOC_IOCFG8_PORT_ID_M 0x0000003F 3415 #define IOC_IOCFG8_PORT_ID_S 0 3416 #define IOC_IOCFG8_PORT_ID_RFC_SMI_CL_IN 0x00000038 3417 #define IOC_IOCFG8_PORT_ID_RFC_SMI_CL_OUT 0x00000037 3418 #define IOC_IOCFG8_PORT_ID_RFC_SMI_DL_IN 0x00000036 3419 #define IOC_IOCFG8_PORT_ID_RFC_SMI_DL_OUT 0x00000035 3420 #define IOC_IOCFG8_PORT_ID_RFC_GPI1 0x00000034 3421 #define IOC_IOCFG8_PORT_ID_RFC_GPI0 0x00000033 3422 #define IOC_IOCFG8_PORT_ID_RFC_GPO3 0x00000032 3423 #define IOC_IOCFG8_PORT_ID_RFC_GPO2 0x00000031 3424 #define IOC_IOCFG8_PORT_ID_RFC_GPO1 0x00000030 3425 #define IOC_IOCFG8_PORT_ID_RFC_GPO0 0x0000002F 3426 #define IOC_IOCFG8_PORT_ID_RFC_TRC 0x0000002E 3427 #define IOC_IOCFG8_PORT_ID_I2S_MCLK 0x00000029 3428 #define IOC_IOCFG8_PORT_ID_I2S_BCLK 0x00000028 3429 #define IOC_IOCFG8_PORT_ID_I2S_WCLK 0x00000027 3430 #define IOC_IOCFG8_PORT_ID_I2S_AD1 0x00000026 3431 #define IOC_IOCFG8_PORT_ID_I2S_AD0 0x00000025 3432 #define IOC_IOCFG8_PORT_ID_SSI1_CLK 0x00000024 3433 #define IOC_IOCFG8_PORT_ID_SSI1_FSS 0x00000023 3434 #define IOC_IOCFG8_PORT_ID_SSI1_TX 0x00000022 3435 #define IOC_IOCFG8_PORT_ID_SSI1_RX 0x00000021 3436 #define IOC_IOCFG8_PORT_ID_CPU_SWV 0x00000020 3437 #define IOC_IOCFG8_PORT_ID_PORT_EVENT7 0x0000001E 3438 #define IOC_IOCFG8_PORT_ID_PORT_EVENT6 0x0000001D 3439 #define IOC_IOCFG8_PORT_ID_PORT_EVENT5 0x0000001C 3440 #define IOC_IOCFG8_PORT_ID_PORT_EVENT4 0x0000001B 3441 #define IOC_IOCFG8_PORT_ID_PORT_EVENT3 0x0000001A 3442 #define IOC_IOCFG8_PORT_ID_PORT_EVENT2 0x00000019 3443 #define IOC_IOCFG8_PORT_ID_PORT_EVENT1 0x00000018 3444 #define IOC_IOCFG8_PORT_ID_PORT_EVENT0 0x00000017 3445 #define IOC_IOCFG8_PORT_ID_UART1_RTS 0x00000016 3446 #define IOC_IOCFG8_PORT_ID_UART1_CTS 0x00000015 3447 #define IOC_IOCFG8_PORT_ID_UART1_TX 0x00000014 3448 #define IOC_IOCFG8_PORT_ID_UART1_RX 0x00000013 3449 #define IOC_IOCFG8_PORT_ID_UART0_RTS 0x00000012 3450 #define IOC_IOCFG8_PORT_ID_UART0_CTS 0x00000011 3451 #define IOC_IOCFG8_PORT_ID_UART0_TX 0x00000010 3452 #define IOC_IOCFG8_PORT_ID_UART0_RX 0x0000000F 3453 #define IOC_IOCFG8_PORT_ID_I2C_MSSCL 0x0000000E 3454 #define IOC_IOCFG8_PORT_ID_I2C_MSSDA 0x0000000D 3455 #define IOC_IOCFG8_PORT_ID_SSI0_CLK 0x0000000C 3456 #define IOC_IOCFG8_PORT_ID_SSI0_FSS 0x0000000B 3457 #define IOC_IOCFG8_PORT_ID_SSI0_TX 0x0000000A 3458 #define IOC_IOCFG8_PORT_ID_SSI0_RX 0x00000009 3459 #define IOC_IOCFG8_PORT_ID_AUX_IO 0x00000008 3460 #define IOC_IOCFG8_PORT_ID_AON_CLK32K 0x00000007 3461 #define IOC_IOCFG8_PORT_ID_GPIO 0x00000000 3462 3463 //***************************************************************************** 3464 // 3465 // Register: IOC_O_IOCFG9 3466 // 3467 //***************************************************************************** 3468 // Field: [30] HYST_EN 3469 // 3470 // 0: Input hysteresis disable 3471 // 1: Input hysteresis enable 3472 #define IOC_IOCFG9_HYST_EN 0x40000000 3473 #define IOC_IOCFG9_HYST_EN_BITN 30 3474 #define IOC_IOCFG9_HYST_EN_M 0x40000000 3475 #define IOC_IOCFG9_HYST_EN_S 30 3476 3477 // Field: [29] IE 3478 // 3479 // 0: Input disabled 3480 // 1: Input enabled 3481 // 3482 // Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be 3483 // ignored. 3484 #define IOC_IOCFG9_IE 0x20000000 3485 #define IOC_IOCFG9_IE_BITN 29 3486 #define IOC_IOCFG9_IE_M 0x20000000 3487 #define IOC_IOCFG9_IE_S 29 3488 3489 // Field: [28:27] WU_CFG 3490 // 3491 // If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or 3492 // >0x08: 3493 // 3494 // 00: No wake-up 3495 // 01: No wake-up 3496 // 10: Wakes up from shutdown if this pad is going low. 3497 // 11: Wakes up from shutdown if this pad is going high. 3498 // 3499 // If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, 3500 // this register only sets wakeup enable or not. 3501 // 3502 // 00, 01: Wakeup disabled 3503 // 10, 11: Wakeup enabled 3504 // 3505 // Polarity is controlled from AON registers. 3506 // 3507 // Note:When the MSB is set, the IOC will deactivate the output enable for the 3508 // DIO. 3509 #define IOC_IOCFG9_WU_CFG_W 2 3510 #define IOC_IOCFG9_WU_CFG_M 0x18000000 3511 #define IOC_IOCFG9_WU_CFG_S 27 3512 3513 // Field: [26:24] IOMODE 3514 // 3515 // IO Mode 3516 // Not applicable for IO configured for AON periph. signals and AUX PORT_ID 3517 // 0x01-0x08 3518 // AUX has its own open_source/drain configuration. 3519 // 3520 // 0x2: Reserved. Undefined behavior. 3521 // 0x3: Reserved. Undefined behavior. 3522 // ENUMs: 3523 // OPENSRC_INV Open Source 3524 // Inverted input / output 3525 // OPENSRC Open Source 3526 // Normal input / output 3527 // OPENDR_INV Open Drain 3528 // Inverted input / output 3529 // OPENDR Open Drain, 3530 // Normal input / output 3531 // INV Inverted input / ouput 3532 // NORMAL Normal input / output 3533 #define IOC_IOCFG9_IOMODE_W 3 3534 #define IOC_IOCFG9_IOMODE_M 0x07000000 3535 #define IOC_IOCFG9_IOMODE_S 24 3536 #define IOC_IOCFG9_IOMODE_OPENSRC_INV 0x07000000 3537 #define IOC_IOCFG9_IOMODE_OPENSRC 0x06000000 3538 #define IOC_IOCFG9_IOMODE_OPENDR_INV 0x05000000 3539 #define IOC_IOCFG9_IOMODE_OPENDR 0x04000000 3540 #define IOC_IOCFG9_IOMODE_INV 0x01000000 3541 #define IOC_IOCFG9_IOMODE_NORMAL 0x00000000 3542 3543 // Field: [23] IOEV_AON_PROG2_EN 3544 // 3545 // Event asserted by this IO when edge detection is enabled 3546 // 3547 // 0: Input edge detection does not assert AON_PROG2 event 3548 // 1: Input edge detection asserts AON_PROG2 event 3549 #define IOC_IOCFG9_IOEV_AON_PROG2_EN 0x00800000 3550 #define IOC_IOCFG9_IOEV_AON_PROG2_EN_BITN 23 3551 #define IOC_IOCFG9_IOEV_AON_PROG2_EN_M 0x00800000 3552 #define IOC_IOCFG9_IOEV_AON_PROG2_EN_S 23 3553 3554 // Field: [22] IOEV_AON_PROG1_EN 3555 // 3556 // Event asserted by this IO when edge detection is enabled 3557 // 3558 // 0: Input edge detection does not assert AON_PROG1 event 3559 // 1: Input edge detection asserts AON_PROG1 event 3560 #define IOC_IOCFG9_IOEV_AON_PROG1_EN 0x00400000 3561 #define IOC_IOCFG9_IOEV_AON_PROG1_EN_BITN 22 3562 #define IOC_IOCFG9_IOEV_AON_PROG1_EN_M 0x00400000 3563 #define IOC_IOCFG9_IOEV_AON_PROG1_EN_S 22 3564 3565 // Field: [21] IOEV_AON_PROG0_EN 3566 // 3567 // Event asserted by this IO when edge detection is enabled 3568 // 3569 // 0: Input edge detection does not assert AON_PROG0 event 3570 // 1: Input edge detection asserts AON_PROG0 event 3571 #define IOC_IOCFG9_IOEV_AON_PROG0_EN 0x00200000 3572 #define IOC_IOCFG9_IOEV_AON_PROG0_EN_BITN 21 3573 #define IOC_IOCFG9_IOEV_AON_PROG0_EN_M 0x00200000 3574 #define IOC_IOCFG9_IOEV_AON_PROG0_EN_S 21 3575 3576 // Field: [18] EDGE_IRQ_EN 3577 // 3578 // 0: No interrupt generation 3579 // 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is 3580 // enabled) 3581 #define IOC_IOCFG9_EDGE_IRQ_EN 0x00040000 3582 #define IOC_IOCFG9_EDGE_IRQ_EN_BITN 18 3583 #define IOC_IOCFG9_EDGE_IRQ_EN_M 0x00040000 3584 #define IOC_IOCFG9_EDGE_IRQ_EN_S 18 3585 3586 // Field: [17:16] EDGE_DET 3587 // 3588 // Enable generation of edge detection events on this IO 3589 // ENUMs: 3590 // BOTH Positive and negative edge detection 3591 // POS Positive edge detection 3592 // NEG Negative edge detection 3593 // NONE No edge detection 3594 #define IOC_IOCFG9_EDGE_DET_W 2 3595 #define IOC_IOCFG9_EDGE_DET_M 0x00030000 3596 #define IOC_IOCFG9_EDGE_DET_S 16 3597 #define IOC_IOCFG9_EDGE_DET_BOTH 0x00030000 3598 #define IOC_IOCFG9_EDGE_DET_POS 0x00020000 3599 #define IOC_IOCFG9_EDGE_DET_NEG 0x00010000 3600 #define IOC_IOCFG9_EDGE_DET_NONE 0x00000000 3601 3602 // Field: [14:13] PULL_CTL 3603 // 3604 // Pull control 3605 // ENUMs: 3606 // DIS No pull 3607 // UP Pull up 3608 // DWN Pull down 3609 #define IOC_IOCFG9_PULL_CTL_W 2 3610 #define IOC_IOCFG9_PULL_CTL_M 0x00006000 3611 #define IOC_IOCFG9_PULL_CTL_S 13 3612 #define IOC_IOCFG9_PULL_CTL_DIS 0x00006000 3613 #define IOC_IOCFG9_PULL_CTL_UP 0x00004000 3614 #define IOC_IOCFG9_PULL_CTL_DWN 0x00002000 3615 3616 // Field: [12] SLEW_RED 3617 // 3618 // 0: Normal slew rate 3619 // 1: Enables reduced slew rate in output driver. 3620 #define IOC_IOCFG9_SLEW_RED 0x00001000 3621 #define IOC_IOCFG9_SLEW_RED_BITN 12 3622 #define IOC_IOCFG9_SLEW_RED_M 0x00001000 3623 #define IOC_IOCFG9_SLEW_RED_S 12 3624 3625 // Field: [11:10] IOCURR 3626 // 3627 // Selects IO current mode of this IO. 3628 // ENUMs: 3629 // 4_8MA Extended-Current (EC) mode: Min 8 mA for double 3630 // drive strength IOs (min 4 mA for normal IOs) 3631 // when IOSTR is set to AUTO 3632 // 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set 3633 // to AUTO 3634 // 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set 3635 // to AUTO 3636 #define IOC_IOCFG9_IOCURR_W 2 3637 #define IOC_IOCFG9_IOCURR_M 0x00000C00 3638 #define IOC_IOCFG9_IOCURR_S 10 3639 #define IOC_IOCFG9_IOCURR_4_8MA 0x00000800 3640 #define IOC_IOCFG9_IOCURR_4MA 0x00000400 3641 #define IOC_IOCFG9_IOCURR_2MA 0x00000000 3642 3643 // Field: [9:8] IOSTR 3644 // 3645 // Select source for drive strength control of this IO. 3646 // This setting controls the drive strength of the Low-Current (LC) mode. 3647 // Higher drive strength can be selected in IOCURR 3648 // ENUMs: 3649 // MAX Maximum drive strength, controlled by 3650 // AON_IOC:IOSTRMAX (min 2 mA @1.8V with default 3651 // values) 3652 // MED Medium drive strength, controlled by 3653 // AON_IOC:IOSTRMED (min 2 mA @2.5V with default 3654 // values) 3655 // MIN Minimum drive strength, controlled by 3656 // AON_IOC:IOSTRMIN (min 2 mA @3.3V with default 3657 // values) 3658 // AUTO Automatic drive strength, controlled by AON BATMON 3659 // based on battery voltage. (min 2 mA @VDDS) 3660 #define IOC_IOCFG9_IOSTR_W 2 3661 #define IOC_IOCFG9_IOSTR_M 0x00000300 3662 #define IOC_IOCFG9_IOSTR_S 8 3663 #define IOC_IOCFG9_IOSTR_MAX 0x00000300 3664 #define IOC_IOCFG9_IOSTR_MED 0x00000200 3665 #define IOC_IOCFG9_IOSTR_MIN 0x00000100 3666 #define IOC_IOCFG9_IOSTR_AUTO 0x00000000 3667 3668 // Field: [7] IOEV_RTC_EN 3669 // 3670 // Event asserted by this IO when edge detection is enabled 3671 // 3672 // 0: Input edge detection does not assert RTC event 3673 // 1: Input edge detection asserts RTC event 3674 #define IOC_IOCFG9_IOEV_RTC_EN 0x00000080 3675 #define IOC_IOCFG9_IOEV_RTC_EN_BITN 7 3676 #define IOC_IOCFG9_IOEV_RTC_EN_M 0x00000080 3677 #define IOC_IOCFG9_IOEV_RTC_EN_S 7 3678 3679 // Field: [6] IOEV_MCU_WU_EN 3680 // 3681 // Event asserted by this IO when edge detection is enabled 3682 // 3683 // 0: Input edge detection does not assert MCU_WU event 3684 // 1: Input edge detection asserts MCU_WU event 3685 #define IOC_IOCFG9_IOEV_MCU_WU_EN 0x00000040 3686 #define IOC_IOCFG9_IOEV_MCU_WU_EN_BITN 6 3687 #define IOC_IOCFG9_IOEV_MCU_WU_EN_M 0x00000040 3688 #define IOC_IOCFG9_IOEV_MCU_WU_EN_S 6 3689 3690 // Field: [5:0] PORT_ID 3691 // 3692 // Selects usage for DIO9 3693 // Note: This field should not be written other than the times when PORT_ID 3694 // value is specifically required to change. 3695 // ENUMs: 3696 // RFC_SMI_CL_IN RF Core SMI Command Link In 3697 // RFC_SMI_CL_OUT RF Core SMI Command Link Out 3698 // RFC_SMI_DL_IN RF Core SMI Data Link In 3699 // RFC_SMI_DL_OUT RF Core SMI Data Link Out 3700 // RFC_GPI1 RF Core Data In 1 3701 // RFC_GPI0 RF Core Data In 0 3702 // RFC_GPO3 RF Core Data Out 3 3703 // RFC_GPO2 RF Core Data Out 2 3704 // RFC_GPO1 RF Core Data Out 1 3705 // RFC_GPO0 RF Core Data Out 0 3706 // RFC_TRC RF Core Trace 3707 // I2S_MCLK I2S MCLK 3708 // I2S_BCLK I2S BCLK 3709 // I2S_WCLK I2S WCLK 3710 // I2S_AD1 I2S Data 1 3711 // I2S_AD0 I2S Data 0 3712 // SSI1_CLK SSI1 CLK 3713 // SSI1_FSS SSI1 FSS 3714 // SSI1_TX SSI1 TX 3715 // SSI1_RX SSI1 RX 3716 // CPU_SWV CPU SWV 3717 // PORT_EVENT7 PORT EVENT 7 3718 // Can be used as a general 3719 // purpose IO event by selecting it through 3720 // registers in the EVENT module, for example 3721 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 3722 // and so on 3723 // PORT_EVENT6 PORT EVENT 6 3724 // Can be used as a general 3725 // purpose IO event by selecting it through 3726 // registers in the EVENT module, for example 3727 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 3728 // and so on 3729 // PORT_EVENT5 PORT EVENT 5 3730 // Can be used as a general 3731 // purpose IO event by selecting it through 3732 // registers in the EVENT module, for example 3733 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 3734 // and so on 3735 // PORT_EVENT4 PORT EVENT 4 3736 // Can be used as a general 3737 // purpose IO event by selecting it through 3738 // registers in the EVENT module, for example 3739 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 3740 // and so on 3741 // PORT_EVENT3 PORT EVENT 3 3742 // Can be used as a general 3743 // purpose IO event by selecting it through 3744 // registers in the EVENT module, for example 3745 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 3746 // and so on 3747 // PORT_EVENT2 PORT EVENT 2 3748 // Can be used as a general 3749 // purpose IO event by selecting it through 3750 // registers in the EVENT module, for example 3751 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 3752 // and so on 3753 // PORT_EVENT1 PORT EVENT 1 3754 // Can be used as a general 3755 // purpose IO event by selecting it through 3756 // registers in the EVENT module, for example 3757 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 3758 // and so on 3759 // PORT_EVENT0 PORT EVENT 0 3760 // Can be used as a general 3761 // purpose IO event by selecting it through 3762 // registers in the EVENT module, for example 3763 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 3764 // and so on 3765 // UART1_RTS UART1 RTS 3766 // UART1_CTS UART1 CTS 3767 // UART1_TX UART1 TX 3768 // UART1_RX UART1 RX 3769 // UART0_RTS UART0 RTS 3770 // UART0_CTS UART0 CTS 3771 // UART0_TX UART0 TX 3772 // UART0_RX UART0 RX 3773 // I2C_MSSCL I2C Clock 3774 // I2C_MSSDA I2C Data 3775 // SSI0_CLK SSI0 CLK 3776 // SSI0_FSS SSI0 FSS 3777 // SSI0_TX SSI0 TX 3778 // SSI0_RX SSI0 RX 3779 // AUX_IO AUX IO 3780 // AON_CLK32K AON 32 KHz clock (SCLK_LF) 3781 // GPIO General Purpose IO 3782 #define IOC_IOCFG9_PORT_ID_W 6 3783 #define IOC_IOCFG9_PORT_ID_M 0x0000003F 3784 #define IOC_IOCFG9_PORT_ID_S 0 3785 #define IOC_IOCFG9_PORT_ID_RFC_SMI_CL_IN 0x00000038 3786 #define IOC_IOCFG9_PORT_ID_RFC_SMI_CL_OUT 0x00000037 3787 #define IOC_IOCFG9_PORT_ID_RFC_SMI_DL_IN 0x00000036 3788 #define IOC_IOCFG9_PORT_ID_RFC_SMI_DL_OUT 0x00000035 3789 #define IOC_IOCFG9_PORT_ID_RFC_GPI1 0x00000034 3790 #define IOC_IOCFG9_PORT_ID_RFC_GPI0 0x00000033 3791 #define IOC_IOCFG9_PORT_ID_RFC_GPO3 0x00000032 3792 #define IOC_IOCFG9_PORT_ID_RFC_GPO2 0x00000031 3793 #define IOC_IOCFG9_PORT_ID_RFC_GPO1 0x00000030 3794 #define IOC_IOCFG9_PORT_ID_RFC_GPO0 0x0000002F 3795 #define IOC_IOCFG9_PORT_ID_RFC_TRC 0x0000002E 3796 #define IOC_IOCFG9_PORT_ID_I2S_MCLK 0x00000029 3797 #define IOC_IOCFG9_PORT_ID_I2S_BCLK 0x00000028 3798 #define IOC_IOCFG9_PORT_ID_I2S_WCLK 0x00000027 3799 #define IOC_IOCFG9_PORT_ID_I2S_AD1 0x00000026 3800 #define IOC_IOCFG9_PORT_ID_I2S_AD0 0x00000025 3801 #define IOC_IOCFG9_PORT_ID_SSI1_CLK 0x00000024 3802 #define IOC_IOCFG9_PORT_ID_SSI1_FSS 0x00000023 3803 #define IOC_IOCFG9_PORT_ID_SSI1_TX 0x00000022 3804 #define IOC_IOCFG9_PORT_ID_SSI1_RX 0x00000021 3805 #define IOC_IOCFG9_PORT_ID_CPU_SWV 0x00000020 3806 #define IOC_IOCFG9_PORT_ID_PORT_EVENT7 0x0000001E 3807 #define IOC_IOCFG9_PORT_ID_PORT_EVENT6 0x0000001D 3808 #define IOC_IOCFG9_PORT_ID_PORT_EVENT5 0x0000001C 3809 #define IOC_IOCFG9_PORT_ID_PORT_EVENT4 0x0000001B 3810 #define IOC_IOCFG9_PORT_ID_PORT_EVENT3 0x0000001A 3811 #define IOC_IOCFG9_PORT_ID_PORT_EVENT2 0x00000019 3812 #define IOC_IOCFG9_PORT_ID_PORT_EVENT1 0x00000018 3813 #define IOC_IOCFG9_PORT_ID_PORT_EVENT0 0x00000017 3814 #define IOC_IOCFG9_PORT_ID_UART1_RTS 0x00000016 3815 #define IOC_IOCFG9_PORT_ID_UART1_CTS 0x00000015 3816 #define IOC_IOCFG9_PORT_ID_UART1_TX 0x00000014 3817 #define IOC_IOCFG9_PORT_ID_UART1_RX 0x00000013 3818 #define IOC_IOCFG9_PORT_ID_UART0_RTS 0x00000012 3819 #define IOC_IOCFG9_PORT_ID_UART0_CTS 0x00000011 3820 #define IOC_IOCFG9_PORT_ID_UART0_TX 0x00000010 3821 #define IOC_IOCFG9_PORT_ID_UART0_RX 0x0000000F 3822 #define IOC_IOCFG9_PORT_ID_I2C_MSSCL 0x0000000E 3823 #define IOC_IOCFG9_PORT_ID_I2C_MSSDA 0x0000000D 3824 #define IOC_IOCFG9_PORT_ID_SSI0_CLK 0x0000000C 3825 #define IOC_IOCFG9_PORT_ID_SSI0_FSS 0x0000000B 3826 #define IOC_IOCFG9_PORT_ID_SSI0_TX 0x0000000A 3827 #define IOC_IOCFG9_PORT_ID_SSI0_RX 0x00000009 3828 #define IOC_IOCFG9_PORT_ID_AUX_IO 0x00000008 3829 #define IOC_IOCFG9_PORT_ID_AON_CLK32K 0x00000007 3830 #define IOC_IOCFG9_PORT_ID_GPIO 0x00000000 3831 3832 //***************************************************************************** 3833 // 3834 // Register: IOC_O_IOCFG10 3835 // 3836 //***************************************************************************** 3837 // Field: [30] HYST_EN 3838 // 3839 // 0: Input hysteresis disable 3840 // 1: Input hysteresis enable 3841 #define IOC_IOCFG10_HYST_EN 0x40000000 3842 #define IOC_IOCFG10_HYST_EN_BITN 30 3843 #define IOC_IOCFG10_HYST_EN_M 0x40000000 3844 #define IOC_IOCFG10_HYST_EN_S 30 3845 3846 // Field: [29] IE 3847 // 3848 // 0: Input disabled 3849 // 1: Input enabled 3850 // 3851 // Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be 3852 // ignored. 3853 #define IOC_IOCFG10_IE 0x20000000 3854 #define IOC_IOCFG10_IE_BITN 29 3855 #define IOC_IOCFG10_IE_M 0x20000000 3856 #define IOC_IOCFG10_IE_S 29 3857 3858 // Field: [28:27] WU_CFG 3859 // 3860 // If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or 3861 // >0x08: 3862 // 3863 // 00: No wake-up 3864 // 01: No wake-up 3865 // 10: Wakes up from shutdown if this pad is going low. 3866 // 11: Wakes up from shutdown if this pad is going high. 3867 // 3868 // If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, 3869 // this register only sets wakeup enable or not. 3870 // 3871 // 00, 01: Wakeup disabled 3872 // 10, 11: Wakeup enabled 3873 // 3874 // Polarity is controlled from AON registers. 3875 // 3876 // Note:When the MSB is set, the IOC will deactivate the output enable for the 3877 // DIO. 3878 #define IOC_IOCFG10_WU_CFG_W 2 3879 #define IOC_IOCFG10_WU_CFG_M 0x18000000 3880 #define IOC_IOCFG10_WU_CFG_S 27 3881 3882 // Field: [26:24] IOMODE 3883 // 3884 // IO Mode 3885 // Not applicable for IO configured for AON periph. signals and AUX PORT_ID 3886 // 0x01-0x08 3887 // AUX has its own open_source/drain configuration. 3888 // 3889 // 0x2: Reserved. Undefined behavior. 3890 // 0x3: Reserved. Undefined behavior. 3891 // ENUMs: 3892 // OPENSRC_INV Open Source 3893 // Inverted input / output 3894 // OPENSRC Open Source 3895 // Normal input / output 3896 // OPENDR_INV Open Drain 3897 // Inverted input / output 3898 // OPENDR Open Drain, 3899 // Normal input / output 3900 // INV Inverted input / ouput 3901 // NORMAL Normal input / output 3902 #define IOC_IOCFG10_IOMODE_W 3 3903 #define IOC_IOCFG10_IOMODE_M 0x07000000 3904 #define IOC_IOCFG10_IOMODE_S 24 3905 #define IOC_IOCFG10_IOMODE_OPENSRC_INV 0x07000000 3906 #define IOC_IOCFG10_IOMODE_OPENSRC 0x06000000 3907 #define IOC_IOCFG10_IOMODE_OPENDR_INV 0x05000000 3908 #define IOC_IOCFG10_IOMODE_OPENDR 0x04000000 3909 #define IOC_IOCFG10_IOMODE_INV 0x01000000 3910 #define IOC_IOCFG10_IOMODE_NORMAL 0x00000000 3911 3912 // Field: [23] IOEV_AON_PROG2_EN 3913 // 3914 // Event asserted by this IO when edge detection is enabled 3915 // 3916 // 0: Input edge detection does not assert AON_PROG2 event 3917 // 1: Input edge detection asserts AON_PROG2 event 3918 #define IOC_IOCFG10_IOEV_AON_PROG2_EN 0x00800000 3919 #define IOC_IOCFG10_IOEV_AON_PROG2_EN_BITN 23 3920 #define IOC_IOCFG10_IOEV_AON_PROG2_EN_M 0x00800000 3921 #define IOC_IOCFG10_IOEV_AON_PROG2_EN_S 23 3922 3923 // Field: [22] IOEV_AON_PROG1_EN 3924 // 3925 // Event asserted by this IO when edge detection is enabled 3926 // 3927 // 0: Input edge detection does not assert AON_PROG1 event 3928 // 1: Input edge detection asserts AON_PROG1 event 3929 #define IOC_IOCFG10_IOEV_AON_PROG1_EN 0x00400000 3930 #define IOC_IOCFG10_IOEV_AON_PROG1_EN_BITN 22 3931 #define IOC_IOCFG10_IOEV_AON_PROG1_EN_M 0x00400000 3932 #define IOC_IOCFG10_IOEV_AON_PROG1_EN_S 22 3933 3934 // Field: [21] IOEV_AON_PROG0_EN 3935 // 3936 // Event asserted by this IO when edge detection is enabled 3937 // 3938 // 0: Input edge detection does not assert AON_PROG0 event 3939 // 1: Input edge detection asserts AON_PROG0 event 3940 #define IOC_IOCFG10_IOEV_AON_PROG0_EN 0x00200000 3941 #define IOC_IOCFG10_IOEV_AON_PROG0_EN_BITN 21 3942 #define IOC_IOCFG10_IOEV_AON_PROG0_EN_M 0x00200000 3943 #define IOC_IOCFG10_IOEV_AON_PROG0_EN_S 21 3944 3945 // Field: [18] EDGE_IRQ_EN 3946 // 3947 // 0: No interrupt generation 3948 // 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is 3949 // enabled) 3950 #define IOC_IOCFG10_EDGE_IRQ_EN 0x00040000 3951 #define IOC_IOCFG10_EDGE_IRQ_EN_BITN 18 3952 #define IOC_IOCFG10_EDGE_IRQ_EN_M 0x00040000 3953 #define IOC_IOCFG10_EDGE_IRQ_EN_S 18 3954 3955 // Field: [17:16] EDGE_DET 3956 // 3957 // Enable generation of edge detection events on this IO 3958 // ENUMs: 3959 // BOTH Positive and negative edge detection 3960 // POS Positive edge detection 3961 // NEG Negative edge detection 3962 // NONE No edge detection 3963 #define IOC_IOCFG10_EDGE_DET_W 2 3964 #define IOC_IOCFG10_EDGE_DET_M 0x00030000 3965 #define IOC_IOCFG10_EDGE_DET_S 16 3966 #define IOC_IOCFG10_EDGE_DET_BOTH 0x00030000 3967 #define IOC_IOCFG10_EDGE_DET_POS 0x00020000 3968 #define IOC_IOCFG10_EDGE_DET_NEG 0x00010000 3969 #define IOC_IOCFG10_EDGE_DET_NONE 0x00000000 3970 3971 // Field: [14:13] PULL_CTL 3972 // 3973 // Pull control 3974 // ENUMs: 3975 // DIS No pull 3976 // UP Pull up 3977 // DWN Pull down 3978 #define IOC_IOCFG10_PULL_CTL_W 2 3979 #define IOC_IOCFG10_PULL_CTL_M 0x00006000 3980 #define IOC_IOCFG10_PULL_CTL_S 13 3981 #define IOC_IOCFG10_PULL_CTL_DIS 0x00006000 3982 #define IOC_IOCFG10_PULL_CTL_UP 0x00004000 3983 #define IOC_IOCFG10_PULL_CTL_DWN 0x00002000 3984 3985 // Field: [12] SLEW_RED 3986 // 3987 // 0: Normal slew rate 3988 // 1: Enables reduced slew rate in output driver. 3989 #define IOC_IOCFG10_SLEW_RED 0x00001000 3990 #define IOC_IOCFG10_SLEW_RED_BITN 12 3991 #define IOC_IOCFG10_SLEW_RED_M 0x00001000 3992 #define IOC_IOCFG10_SLEW_RED_S 12 3993 3994 // Field: [11:10] IOCURR 3995 // 3996 // Selects IO current mode of this IO. 3997 // ENUMs: 3998 // 4_8MA Extended-Current (EC) mode: Min 8 mA for double 3999 // drive strength IOs (min 4 mA for normal IOs) 4000 // when IOSTR is set to AUTO 4001 // 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set 4002 // to AUTO 4003 // 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set 4004 // to AUTO 4005 #define IOC_IOCFG10_IOCURR_W 2 4006 #define IOC_IOCFG10_IOCURR_M 0x00000C00 4007 #define IOC_IOCFG10_IOCURR_S 10 4008 #define IOC_IOCFG10_IOCURR_4_8MA 0x00000800 4009 #define IOC_IOCFG10_IOCURR_4MA 0x00000400 4010 #define IOC_IOCFG10_IOCURR_2MA 0x00000000 4011 4012 // Field: [9:8] IOSTR 4013 // 4014 // Select source for drive strength control of this IO. 4015 // This setting controls the drive strength of the Low-Current (LC) mode. 4016 // Higher drive strength can be selected in IOCURR 4017 // ENUMs: 4018 // MAX Maximum drive strength, controlled by 4019 // AON_IOC:IOSTRMAX (min 2 mA @1.8V with default 4020 // values) 4021 // MED Medium drive strength, controlled by 4022 // AON_IOC:IOSTRMED (min 2 mA @2.5V with default 4023 // values) 4024 // MIN Minimum drive strength, controlled by 4025 // AON_IOC:IOSTRMIN (min 2 mA @3.3V with default 4026 // values) 4027 // AUTO Automatic drive strength, controlled by AON BATMON 4028 // based on battery voltage. (min 2 mA @VDDS) 4029 #define IOC_IOCFG10_IOSTR_W 2 4030 #define IOC_IOCFG10_IOSTR_M 0x00000300 4031 #define IOC_IOCFG10_IOSTR_S 8 4032 #define IOC_IOCFG10_IOSTR_MAX 0x00000300 4033 #define IOC_IOCFG10_IOSTR_MED 0x00000200 4034 #define IOC_IOCFG10_IOSTR_MIN 0x00000100 4035 #define IOC_IOCFG10_IOSTR_AUTO 0x00000000 4036 4037 // Field: [7] IOEV_RTC_EN 4038 // 4039 // Event asserted by this IO when edge detection is enabled 4040 // 4041 // 0: Input edge detection does not assert RTC event 4042 // 1: Input edge detection asserts RTC event 4043 #define IOC_IOCFG10_IOEV_RTC_EN 0x00000080 4044 #define IOC_IOCFG10_IOEV_RTC_EN_BITN 7 4045 #define IOC_IOCFG10_IOEV_RTC_EN_M 0x00000080 4046 #define IOC_IOCFG10_IOEV_RTC_EN_S 7 4047 4048 // Field: [6] IOEV_MCU_WU_EN 4049 // 4050 // Event asserted by this IO when edge detection is enabled 4051 // 4052 // 0: Input edge detection does not assert MCU_WU event 4053 // 1: Input edge detection asserts MCU_WU event 4054 #define IOC_IOCFG10_IOEV_MCU_WU_EN 0x00000040 4055 #define IOC_IOCFG10_IOEV_MCU_WU_EN_BITN 6 4056 #define IOC_IOCFG10_IOEV_MCU_WU_EN_M 0x00000040 4057 #define IOC_IOCFG10_IOEV_MCU_WU_EN_S 6 4058 4059 // Field: [5:0] PORT_ID 4060 // 4061 // Selects usage for DIO10 4062 // Note: This field should not be written other than the times when PORT_ID 4063 // value is specifically required to change. 4064 // ENUMs: 4065 // RFC_SMI_CL_IN RF Core SMI Command Link In 4066 // RFC_SMI_CL_OUT RF Core SMI Command Link Out 4067 // RFC_SMI_DL_IN RF Core SMI Data Link In 4068 // RFC_SMI_DL_OUT RF Core SMI Data Link Out 4069 // RFC_GPI1 RF Core Data In 1 4070 // RFC_GPI0 RF Core Data In 0 4071 // RFC_GPO3 RF Core Data Out 3 4072 // RFC_GPO2 RF Core Data Out 2 4073 // RFC_GPO1 RF Core Data Out 1 4074 // RFC_GPO0 RF Core Data Out 0 4075 // RFC_TRC RF Core Trace 4076 // I2S_MCLK I2S MCLK 4077 // I2S_BCLK I2S BCLK 4078 // I2S_WCLK I2S WCLK 4079 // I2S_AD1 I2S Data 1 4080 // I2S_AD0 I2S Data 0 4081 // SSI1_CLK SSI1 CLK 4082 // SSI1_FSS SSI1 FSS 4083 // SSI1_TX SSI1 TX 4084 // SSI1_RX SSI1 RX 4085 // CPU_SWV CPU SWV 4086 // PORT_EVENT7 PORT EVENT 7 4087 // Can be used as a general 4088 // purpose IO event by selecting it through 4089 // registers in the EVENT module, for example 4090 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 4091 // and so on 4092 // PORT_EVENT6 PORT EVENT 6 4093 // Can be used as a general 4094 // purpose IO event by selecting it through 4095 // registers in the EVENT module, for example 4096 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 4097 // and so on 4098 // PORT_EVENT5 PORT EVENT 5 4099 // Can be used as a general 4100 // purpose IO event by selecting it through 4101 // registers in the EVENT module, for example 4102 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 4103 // and so on 4104 // PORT_EVENT4 PORT EVENT 4 4105 // Can be used as a general 4106 // purpose IO event by selecting it through 4107 // registers in the EVENT module, for example 4108 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 4109 // and so on 4110 // PORT_EVENT3 PORT EVENT 3 4111 // Can be used as a general 4112 // purpose IO event by selecting it through 4113 // registers in the EVENT module, for example 4114 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 4115 // and so on 4116 // PORT_EVENT2 PORT EVENT 2 4117 // Can be used as a general 4118 // purpose IO event by selecting it through 4119 // registers in the EVENT module, for example 4120 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 4121 // and so on 4122 // PORT_EVENT1 PORT EVENT 1 4123 // Can be used as a general 4124 // purpose IO event by selecting it through 4125 // registers in the EVENT module, for example 4126 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 4127 // and so on 4128 // PORT_EVENT0 PORT EVENT 0 4129 // Can be used as a general 4130 // purpose IO event by selecting it through 4131 // registers in the EVENT module, for example 4132 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 4133 // and so on 4134 // UART1_RTS UART1 RTS 4135 // UART1_CTS UART1 CTS 4136 // UART1_TX UART1 TX 4137 // UART1_RX UART1 RX 4138 // UART0_RTS UART0 RTS 4139 // UART0_CTS UART0 CTS 4140 // UART0_TX UART0 TX 4141 // UART0_RX UART0 RX 4142 // I2C_MSSCL I2C Clock 4143 // I2C_MSSDA I2C Data 4144 // SSI0_CLK SSI0 CLK 4145 // SSI0_FSS SSI0 FSS 4146 // SSI0_TX SSI0 TX 4147 // SSI0_RX SSI0 RX 4148 // AUX_IO AUX IO 4149 // AON_CLK32K AON 32 KHz clock (SCLK_LF) 4150 // GPIO General Purpose IO 4151 #define IOC_IOCFG10_PORT_ID_W 6 4152 #define IOC_IOCFG10_PORT_ID_M 0x0000003F 4153 #define IOC_IOCFG10_PORT_ID_S 0 4154 #define IOC_IOCFG10_PORT_ID_RFC_SMI_CL_IN 0x00000038 4155 #define IOC_IOCFG10_PORT_ID_RFC_SMI_CL_OUT 0x00000037 4156 #define IOC_IOCFG10_PORT_ID_RFC_SMI_DL_IN 0x00000036 4157 #define IOC_IOCFG10_PORT_ID_RFC_SMI_DL_OUT 0x00000035 4158 #define IOC_IOCFG10_PORT_ID_RFC_GPI1 0x00000034 4159 #define IOC_IOCFG10_PORT_ID_RFC_GPI0 0x00000033 4160 #define IOC_IOCFG10_PORT_ID_RFC_GPO3 0x00000032 4161 #define IOC_IOCFG10_PORT_ID_RFC_GPO2 0x00000031 4162 #define IOC_IOCFG10_PORT_ID_RFC_GPO1 0x00000030 4163 #define IOC_IOCFG10_PORT_ID_RFC_GPO0 0x0000002F 4164 #define IOC_IOCFG10_PORT_ID_RFC_TRC 0x0000002E 4165 #define IOC_IOCFG10_PORT_ID_I2S_MCLK 0x00000029 4166 #define IOC_IOCFG10_PORT_ID_I2S_BCLK 0x00000028 4167 #define IOC_IOCFG10_PORT_ID_I2S_WCLK 0x00000027 4168 #define IOC_IOCFG10_PORT_ID_I2S_AD1 0x00000026 4169 #define IOC_IOCFG10_PORT_ID_I2S_AD0 0x00000025 4170 #define IOC_IOCFG10_PORT_ID_SSI1_CLK 0x00000024 4171 #define IOC_IOCFG10_PORT_ID_SSI1_FSS 0x00000023 4172 #define IOC_IOCFG10_PORT_ID_SSI1_TX 0x00000022 4173 #define IOC_IOCFG10_PORT_ID_SSI1_RX 0x00000021 4174 #define IOC_IOCFG10_PORT_ID_CPU_SWV 0x00000020 4175 #define IOC_IOCFG10_PORT_ID_PORT_EVENT7 0x0000001E 4176 #define IOC_IOCFG10_PORT_ID_PORT_EVENT6 0x0000001D 4177 #define IOC_IOCFG10_PORT_ID_PORT_EVENT5 0x0000001C 4178 #define IOC_IOCFG10_PORT_ID_PORT_EVENT4 0x0000001B 4179 #define IOC_IOCFG10_PORT_ID_PORT_EVENT3 0x0000001A 4180 #define IOC_IOCFG10_PORT_ID_PORT_EVENT2 0x00000019 4181 #define IOC_IOCFG10_PORT_ID_PORT_EVENT1 0x00000018 4182 #define IOC_IOCFG10_PORT_ID_PORT_EVENT0 0x00000017 4183 #define IOC_IOCFG10_PORT_ID_UART1_RTS 0x00000016 4184 #define IOC_IOCFG10_PORT_ID_UART1_CTS 0x00000015 4185 #define IOC_IOCFG10_PORT_ID_UART1_TX 0x00000014 4186 #define IOC_IOCFG10_PORT_ID_UART1_RX 0x00000013 4187 #define IOC_IOCFG10_PORT_ID_UART0_RTS 0x00000012 4188 #define IOC_IOCFG10_PORT_ID_UART0_CTS 0x00000011 4189 #define IOC_IOCFG10_PORT_ID_UART0_TX 0x00000010 4190 #define IOC_IOCFG10_PORT_ID_UART0_RX 0x0000000F 4191 #define IOC_IOCFG10_PORT_ID_I2C_MSSCL 0x0000000E 4192 #define IOC_IOCFG10_PORT_ID_I2C_MSSDA 0x0000000D 4193 #define IOC_IOCFG10_PORT_ID_SSI0_CLK 0x0000000C 4194 #define IOC_IOCFG10_PORT_ID_SSI0_FSS 0x0000000B 4195 #define IOC_IOCFG10_PORT_ID_SSI0_TX 0x0000000A 4196 #define IOC_IOCFG10_PORT_ID_SSI0_RX 0x00000009 4197 #define IOC_IOCFG10_PORT_ID_AUX_IO 0x00000008 4198 #define IOC_IOCFG10_PORT_ID_AON_CLK32K 0x00000007 4199 #define IOC_IOCFG10_PORT_ID_GPIO 0x00000000 4200 4201 //***************************************************************************** 4202 // 4203 // Register: IOC_O_IOCFG11 4204 // 4205 //***************************************************************************** 4206 // Field: [30] HYST_EN 4207 // 4208 // 0: Input hysteresis disable 4209 // 1: Input hysteresis enable 4210 #define IOC_IOCFG11_HYST_EN 0x40000000 4211 #define IOC_IOCFG11_HYST_EN_BITN 30 4212 #define IOC_IOCFG11_HYST_EN_M 0x40000000 4213 #define IOC_IOCFG11_HYST_EN_S 30 4214 4215 // Field: [29] IE 4216 // 4217 // 0: Input disabled 4218 // 1: Input enabled 4219 // 4220 // Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be 4221 // ignored. 4222 #define IOC_IOCFG11_IE 0x20000000 4223 #define IOC_IOCFG11_IE_BITN 29 4224 #define IOC_IOCFG11_IE_M 0x20000000 4225 #define IOC_IOCFG11_IE_S 29 4226 4227 // Field: [28:27] WU_CFG 4228 // 4229 // If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or 4230 // >0x08: 4231 // 4232 // 00: No wake-up 4233 // 01: No wake-up 4234 // 10: Wakes up from shutdown if this pad is going low. 4235 // 11: Wakes up from shutdown if this pad is going high. 4236 // 4237 // If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, 4238 // this register only sets wakeup enable or not. 4239 // 4240 // 00, 01: Wakeup disabled 4241 // 10, 11: Wakeup enabled 4242 // 4243 // Polarity is controlled from AON registers. 4244 // 4245 // Note:When the MSB is set, the IOC will deactivate the output enable for the 4246 // DIO. 4247 #define IOC_IOCFG11_WU_CFG_W 2 4248 #define IOC_IOCFG11_WU_CFG_M 0x18000000 4249 #define IOC_IOCFG11_WU_CFG_S 27 4250 4251 // Field: [26:24] IOMODE 4252 // 4253 // IO Mode 4254 // Not applicable for IO configured for AON periph. signals and AUX PORT_ID 4255 // 0x01-0x08 4256 // AUX has its own open_source/drain configuration. 4257 // 4258 // 0x2: Reserved. Undefined behavior. 4259 // 0x3: Reserved. Undefined behavior. 4260 // ENUMs: 4261 // OPENSRC_INV Open Source 4262 // Inverted input / output 4263 // OPENSRC Open Source 4264 // Normal input / output 4265 // OPENDR_INV Open Drain 4266 // Inverted input / output 4267 // OPENDR Open Drain, 4268 // Normal input / output 4269 // INV Inverted input / ouput 4270 // NORMAL Normal input / output 4271 #define IOC_IOCFG11_IOMODE_W 3 4272 #define IOC_IOCFG11_IOMODE_M 0x07000000 4273 #define IOC_IOCFG11_IOMODE_S 24 4274 #define IOC_IOCFG11_IOMODE_OPENSRC_INV 0x07000000 4275 #define IOC_IOCFG11_IOMODE_OPENSRC 0x06000000 4276 #define IOC_IOCFG11_IOMODE_OPENDR_INV 0x05000000 4277 #define IOC_IOCFG11_IOMODE_OPENDR 0x04000000 4278 #define IOC_IOCFG11_IOMODE_INV 0x01000000 4279 #define IOC_IOCFG11_IOMODE_NORMAL 0x00000000 4280 4281 // Field: [23] IOEV_AON_PROG2_EN 4282 // 4283 // Event asserted by this IO when edge detection is enabled 4284 // 4285 // 0: Input edge detection does not assert AON_PROG2 event 4286 // 1: Input edge detection asserts AON_PROG2 event 4287 #define IOC_IOCFG11_IOEV_AON_PROG2_EN 0x00800000 4288 #define IOC_IOCFG11_IOEV_AON_PROG2_EN_BITN 23 4289 #define IOC_IOCFG11_IOEV_AON_PROG2_EN_M 0x00800000 4290 #define IOC_IOCFG11_IOEV_AON_PROG2_EN_S 23 4291 4292 // Field: [22] IOEV_AON_PROG1_EN 4293 // 4294 // Event asserted by this IO when edge detection is enabled 4295 // 4296 // 0: Input edge detection does not assert AON_PROG1 event 4297 // 1: Input edge detection asserts AON_PROG1 event 4298 #define IOC_IOCFG11_IOEV_AON_PROG1_EN 0x00400000 4299 #define IOC_IOCFG11_IOEV_AON_PROG1_EN_BITN 22 4300 #define IOC_IOCFG11_IOEV_AON_PROG1_EN_M 0x00400000 4301 #define IOC_IOCFG11_IOEV_AON_PROG1_EN_S 22 4302 4303 // Field: [21] IOEV_AON_PROG0_EN 4304 // 4305 // Event asserted by this IO when edge detection is enabled 4306 // 4307 // 0: Input edge detection does not assert AON_PROG0 event 4308 // 1: Input edge detection asserts AON_PROG0 event 4309 #define IOC_IOCFG11_IOEV_AON_PROG0_EN 0x00200000 4310 #define IOC_IOCFG11_IOEV_AON_PROG0_EN_BITN 21 4311 #define IOC_IOCFG11_IOEV_AON_PROG0_EN_M 0x00200000 4312 #define IOC_IOCFG11_IOEV_AON_PROG0_EN_S 21 4313 4314 // Field: [18] EDGE_IRQ_EN 4315 // 4316 // 0: No interrupt generation 4317 // 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is 4318 // enabled) 4319 #define IOC_IOCFG11_EDGE_IRQ_EN 0x00040000 4320 #define IOC_IOCFG11_EDGE_IRQ_EN_BITN 18 4321 #define IOC_IOCFG11_EDGE_IRQ_EN_M 0x00040000 4322 #define IOC_IOCFG11_EDGE_IRQ_EN_S 18 4323 4324 // Field: [17:16] EDGE_DET 4325 // 4326 // Enable generation of edge detection events on this IO 4327 // ENUMs: 4328 // BOTH Positive and negative edge detection 4329 // POS Positive edge detection 4330 // NEG Negative edge detection 4331 // NONE No edge detection 4332 #define IOC_IOCFG11_EDGE_DET_W 2 4333 #define IOC_IOCFG11_EDGE_DET_M 0x00030000 4334 #define IOC_IOCFG11_EDGE_DET_S 16 4335 #define IOC_IOCFG11_EDGE_DET_BOTH 0x00030000 4336 #define IOC_IOCFG11_EDGE_DET_POS 0x00020000 4337 #define IOC_IOCFG11_EDGE_DET_NEG 0x00010000 4338 #define IOC_IOCFG11_EDGE_DET_NONE 0x00000000 4339 4340 // Field: [14:13] PULL_CTL 4341 // 4342 // Pull control 4343 // ENUMs: 4344 // DIS No pull 4345 // UP Pull up 4346 // DWN Pull down 4347 #define IOC_IOCFG11_PULL_CTL_W 2 4348 #define IOC_IOCFG11_PULL_CTL_M 0x00006000 4349 #define IOC_IOCFG11_PULL_CTL_S 13 4350 #define IOC_IOCFG11_PULL_CTL_DIS 0x00006000 4351 #define IOC_IOCFG11_PULL_CTL_UP 0x00004000 4352 #define IOC_IOCFG11_PULL_CTL_DWN 0x00002000 4353 4354 // Field: [12] SLEW_RED 4355 // 4356 // 0: Normal slew rate 4357 // 1: Enables reduced slew rate in output driver. 4358 #define IOC_IOCFG11_SLEW_RED 0x00001000 4359 #define IOC_IOCFG11_SLEW_RED_BITN 12 4360 #define IOC_IOCFG11_SLEW_RED_M 0x00001000 4361 #define IOC_IOCFG11_SLEW_RED_S 12 4362 4363 // Field: [11:10] IOCURR 4364 // 4365 // Selects IO current mode of this IO. 4366 // ENUMs: 4367 // 4_8MA Extended-Current (EC) mode: Min 8 mA for double 4368 // drive strength IOs (min 4 mA for normal IOs) 4369 // when IOSTR is set to AUTO 4370 // 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set 4371 // to AUTO 4372 // 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set 4373 // to AUTO 4374 #define IOC_IOCFG11_IOCURR_W 2 4375 #define IOC_IOCFG11_IOCURR_M 0x00000C00 4376 #define IOC_IOCFG11_IOCURR_S 10 4377 #define IOC_IOCFG11_IOCURR_4_8MA 0x00000800 4378 #define IOC_IOCFG11_IOCURR_4MA 0x00000400 4379 #define IOC_IOCFG11_IOCURR_2MA 0x00000000 4380 4381 // Field: [9:8] IOSTR 4382 // 4383 // Select source for drive strength control of this IO. 4384 // This setting controls the drive strength of the Low-Current (LC) mode. 4385 // Higher drive strength can be selected in IOCURR 4386 // ENUMs: 4387 // MAX Maximum drive strength, controlled by 4388 // AON_IOC:IOSTRMAX (min 2 mA @1.8V with default 4389 // values) 4390 // MED Medium drive strength, controlled by 4391 // AON_IOC:IOSTRMED (min 2 mA @2.5V with default 4392 // values) 4393 // MIN Minimum drive strength, controlled by 4394 // AON_IOC:IOSTRMIN (min 2 mA @3.3V with default 4395 // values) 4396 // AUTO Automatic drive strength, controlled by AON BATMON 4397 // based on battery voltage. (min 2 mA @VDDS) 4398 #define IOC_IOCFG11_IOSTR_W 2 4399 #define IOC_IOCFG11_IOSTR_M 0x00000300 4400 #define IOC_IOCFG11_IOSTR_S 8 4401 #define IOC_IOCFG11_IOSTR_MAX 0x00000300 4402 #define IOC_IOCFG11_IOSTR_MED 0x00000200 4403 #define IOC_IOCFG11_IOSTR_MIN 0x00000100 4404 #define IOC_IOCFG11_IOSTR_AUTO 0x00000000 4405 4406 // Field: [7] IOEV_RTC_EN 4407 // 4408 // Event asserted by this IO when edge detection is enabled 4409 // 4410 // 0: Input edge detection does not assert RTC event 4411 // 1: Input edge detection asserts RTC event 4412 #define IOC_IOCFG11_IOEV_RTC_EN 0x00000080 4413 #define IOC_IOCFG11_IOEV_RTC_EN_BITN 7 4414 #define IOC_IOCFG11_IOEV_RTC_EN_M 0x00000080 4415 #define IOC_IOCFG11_IOEV_RTC_EN_S 7 4416 4417 // Field: [6] IOEV_MCU_WU_EN 4418 // 4419 // Event asserted by this IO when edge detection is enabled 4420 // 4421 // 0: Input edge detection does not assert MCU_WU event 4422 // 1: Input edge detection asserts MCU_WU event 4423 #define IOC_IOCFG11_IOEV_MCU_WU_EN 0x00000040 4424 #define IOC_IOCFG11_IOEV_MCU_WU_EN_BITN 6 4425 #define IOC_IOCFG11_IOEV_MCU_WU_EN_M 0x00000040 4426 #define IOC_IOCFG11_IOEV_MCU_WU_EN_S 6 4427 4428 // Field: [5:0] PORT_ID 4429 // 4430 // Selects usage for DIO11 4431 // Note: This field should not be written other than the times when PORT_ID 4432 // value is specifically required to change. 4433 // ENUMs: 4434 // RFC_SMI_CL_IN RF Core SMI Command Link In 4435 // RFC_SMI_CL_OUT RF Core SMI Command Link Out 4436 // RFC_SMI_DL_IN RF Core SMI Data Link In 4437 // RFC_SMI_DL_OUT RF Core SMI Data Link Out 4438 // RFC_GPI1 RF Core Data In 1 4439 // RFC_GPI0 RF Core Data In 0 4440 // RFC_GPO3 RF Core Data Out 3 4441 // RFC_GPO2 RF Core Data Out 2 4442 // RFC_GPO1 RF Core Data Out 1 4443 // RFC_GPO0 RF Core Data Out 0 4444 // RFC_TRC RF Core Trace 4445 // I2S_MCLK I2S MCLK 4446 // I2S_BCLK I2S BCLK 4447 // I2S_WCLK I2S WCLK 4448 // I2S_AD1 I2S Data 1 4449 // I2S_AD0 I2S Data 0 4450 // SSI1_CLK SSI1 CLK 4451 // SSI1_FSS SSI1 FSS 4452 // SSI1_TX SSI1 TX 4453 // SSI1_RX SSI1 RX 4454 // CPU_SWV CPU SWV 4455 // PORT_EVENT7 PORT EVENT 7 4456 // Can be used as a general 4457 // purpose IO event by selecting it through 4458 // registers in the EVENT module, for example 4459 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 4460 // and so on 4461 // PORT_EVENT6 PORT EVENT 6 4462 // Can be used as a general 4463 // purpose IO event by selecting it through 4464 // registers in the EVENT module, for example 4465 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 4466 // and so on 4467 // PORT_EVENT5 PORT EVENT 5 4468 // Can be used as a general 4469 // purpose IO event by selecting it through 4470 // registers in the EVENT module, for example 4471 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 4472 // and so on 4473 // PORT_EVENT4 PORT EVENT 4 4474 // Can be used as a general 4475 // purpose IO event by selecting it through 4476 // registers in the EVENT module, for example 4477 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 4478 // and so on 4479 // PORT_EVENT3 PORT EVENT 3 4480 // Can be used as a general 4481 // purpose IO event by selecting it through 4482 // registers in the EVENT module, for example 4483 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 4484 // and so on 4485 // PORT_EVENT2 PORT EVENT 2 4486 // Can be used as a general 4487 // purpose IO event by selecting it through 4488 // registers in the EVENT module, for example 4489 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 4490 // and so on 4491 // PORT_EVENT1 PORT EVENT 1 4492 // Can be used as a general 4493 // purpose IO event by selecting it through 4494 // registers in the EVENT module, for example 4495 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 4496 // and so on 4497 // PORT_EVENT0 PORT EVENT 0 4498 // Can be used as a general 4499 // purpose IO event by selecting it through 4500 // registers in the EVENT module, for example 4501 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 4502 // and so on 4503 // UART1_RTS UART1 RTS 4504 // UART1_CTS UART1 CTS 4505 // UART1_TX UART1 TX 4506 // UART1_RX UART1 RX 4507 // UART0_RTS UART0 RTS 4508 // UART0_CTS UART0 CTS 4509 // UART0_TX UART0 TX 4510 // UART0_RX UART0 RX 4511 // I2C_MSSCL I2C Clock 4512 // I2C_MSSDA I2C Data 4513 // SSI0_CLK SSI0 CLK 4514 // SSI0_FSS SSI0 FSS 4515 // SSI0_TX SSI0 TX 4516 // SSI0_RX SSI0 RX 4517 // AUX_IO AUX IO 4518 // AON_CLK32K AON 32 KHz clock (SCLK_LF) 4519 // GPIO General Purpose IO 4520 #define IOC_IOCFG11_PORT_ID_W 6 4521 #define IOC_IOCFG11_PORT_ID_M 0x0000003F 4522 #define IOC_IOCFG11_PORT_ID_S 0 4523 #define IOC_IOCFG11_PORT_ID_RFC_SMI_CL_IN 0x00000038 4524 #define IOC_IOCFG11_PORT_ID_RFC_SMI_CL_OUT 0x00000037 4525 #define IOC_IOCFG11_PORT_ID_RFC_SMI_DL_IN 0x00000036 4526 #define IOC_IOCFG11_PORT_ID_RFC_SMI_DL_OUT 0x00000035 4527 #define IOC_IOCFG11_PORT_ID_RFC_GPI1 0x00000034 4528 #define IOC_IOCFG11_PORT_ID_RFC_GPI0 0x00000033 4529 #define IOC_IOCFG11_PORT_ID_RFC_GPO3 0x00000032 4530 #define IOC_IOCFG11_PORT_ID_RFC_GPO2 0x00000031 4531 #define IOC_IOCFG11_PORT_ID_RFC_GPO1 0x00000030 4532 #define IOC_IOCFG11_PORT_ID_RFC_GPO0 0x0000002F 4533 #define IOC_IOCFG11_PORT_ID_RFC_TRC 0x0000002E 4534 #define IOC_IOCFG11_PORT_ID_I2S_MCLK 0x00000029 4535 #define IOC_IOCFG11_PORT_ID_I2S_BCLK 0x00000028 4536 #define IOC_IOCFG11_PORT_ID_I2S_WCLK 0x00000027 4537 #define IOC_IOCFG11_PORT_ID_I2S_AD1 0x00000026 4538 #define IOC_IOCFG11_PORT_ID_I2S_AD0 0x00000025 4539 #define IOC_IOCFG11_PORT_ID_SSI1_CLK 0x00000024 4540 #define IOC_IOCFG11_PORT_ID_SSI1_FSS 0x00000023 4541 #define IOC_IOCFG11_PORT_ID_SSI1_TX 0x00000022 4542 #define IOC_IOCFG11_PORT_ID_SSI1_RX 0x00000021 4543 #define IOC_IOCFG11_PORT_ID_CPU_SWV 0x00000020 4544 #define IOC_IOCFG11_PORT_ID_PORT_EVENT7 0x0000001E 4545 #define IOC_IOCFG11_PORT_ID_PORT_EVENT6 0x0000001D 4546 #define IOC_IOCFG11_PORT_ID_PORT_EVENT5 0x0000001C 4547 #define IOC_IOCFG11_PORT_ID_PORT_EVENT4 0x0000001B 4548 #define IOC_IOCFG11_PORT_ID_PORT_EVENT3 0x0000001A 4549 #define IOC_IOCFG11_PORT_ID_PORT_EVENT2 0x00000019 4550 #define IOC_IOCFG11_PORT_ID_PORT_EVENT1 0x00000018 4551 #define IOC_IOCFG11_PORT_ID_PORT_EVENT0 0x00000017 4552 #define IOC_IOCFG11_PORT_ID_UART1_RTS 0x00000016 4553 #define IOC_IOCFG11_PORT_ID_UART1_CTS 0x00000015 4554 #define IOC_IOCFG11_PORT_ID_UART1_TX 0x00000014 4555 #define IOC_IOCFG11_PORT_ID_UART1_RX 0x00000013 4556 #define IOC_IOCFG11_PORT_ID_UART0_RTS 0x00000012 4557 #define IOC_IOCFG11_PORT_ID_UART0_CTS 0x00000011 4558 #define IOC_IOCFG11_PORT_ID_UART0_TX 0x00000010 4559 #define IOC_IOCFG11_PORT_ID_UART0_RX 0x0000000F 4560 #define IOC_IOCFG11_PORT_ID_I2C_MSSCL 0x0000000E 4561 #define IOC_IOCFG11_PORT_ID_I2C_MSSDA 0x0000000D 4562 #define IOC_IOCFG11_PORT_ID_SSI0_CLK 0x0000000C 4563 #define IOC_IOCFG11_PORT_ID_SSI0_FSS 0x0000000B 4564 #define IOC_IOCFG11_PORT_ID_SSI0_TX 0x0000000A 4565 #define IOC_IOCFG11_PORT_ID_SSI0_RX 0x00000009 4566 #define IOC_IOCFG11_PORT_ID_AUX_IO 0x00000008 4567 #define IOC_IOCFG11_PORT_ID_AON_CLK32K 0x00000007 4568 #define IOC_IOCFG11_PORT_ID_GPIO 0x00000000 4569 4570 //***************************************************************************** 4571 // 4572 // Register: IOC_O_IOCFG12 4573 // 4574 //***************************************************************************** 4575 // Field: [30] HYST_EN 4576 // 4577 // 0: Input hysteresis disable 4578 // 1: Input hysteresis enable 4579 #define IOC_IOCFG12_HYST_EN 0x40000000 4580 #define IOC_IOCFG12_HYST_EN_BITN 30 4581 #define IOC_IOCFG12_HYST_EN_M 0x40000000 4582 #define IOC_IOCFG12_HYST_EN_S 30 4583 4584 // Field: [29] IE 4585 // 4586 // 0: Input disabled 4587 // 1: Input enabled 4588 // 4589 // Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be 4590 // ignored. 4591 #define IOC_IOCFG12_IE 0x20000000 4592 #define IOC_IOCFG12_IE_BITN 29 4593 #define IOC_IOCFG12_IE_M 0x20000000 4594 #define IOC_IOCFG12_IE_S 29 4595 4596 // Field: [28:27] WU_CFG 4597 // 4598 // If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or 4599 // >0x08: 4600 // 4601 // 00: No wake-up 4602 // 01: No wake-up 4603 // 10: Wakes up from shutdown if this pad is going low. 4604 // 11: Wakes up from shutdown if this pad is going high. 4605 // 4606 // If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, 4607 // this register only sets wakeup enable or not. 4608 // 4609 // 00, 01: Wakeup disabled 4610 // 10, 11: Wakeup enabled 4611 // 4612 // Polarity is controlled from AON registers. 4613 // 4614 // Note:When the MSB is set, the IOC will deactivate the output enable for the 4615 // DIO. 4616 #define IOC_IOCFG12_WU_CFG_W 2 4617 #define IOC_IOCFG12_WU_CFG_M 0x18000000 4618 #define IOC_IOCFG12_WU_CFG_S 27 4619 4620 // Field: [26:24] IOMODE 4621 // 4622 // IO Mode 4623 // Not applicable for IO configured for AON periph. signals and AUX PORT_ID 4624 // 0x01-0x08 4625 // AUX has its own open_source/drain configuration. 4626 // 4627 // 0x2: Reserved. Undefined behavior. 4628 // 0x3: Reserved. Undefined behavior. 4629 // ENUMs: 4630 // OPENSRC_INV Open Source 4631 // Inverted input / output 4632 // OPENSRC Open Source 4633 // Normal input / output 4634 // OPENDR_INV Open Drain 4635 // Inverted input / output 4636 // OPENDR Open Drain, 4637 // Normal input / output 4638 // INV Inverted input / ouput 4639 // NORMAL Normal input / output 4640 #define IOC_IOCFG12_IOMODE_W 3 4641 #define IOC_IOCFG12_IOMODE_M 0x07000000 4642 #define IOC_IOCFG12_IOMODE_S 24 4643 #define IOC_IOCFG12_IOMODE_OPENSRC_INV 0x07000000 4644 #define IOC_IOCFG12_IOMODE_OPENSRC 0x06000000 4645 #define IOC_IOCFG12_IOMODE_OPENDR_INV 0x05000000 4646 #define IOC_IOCFG12_IOMODE_OPENDR 0x04000000 4647 #define IOC_IOCFG12_IOMODE_INV 0x01000000 4648 #define IOC_IOCFG12_IOMODE_NORMAL 0x00000000 4649 4650 // Field: [23] IOEV_AON_PROG2_EN 4651 // 4652 // Event asserted by this IO when edge detection is enabled 4653 // 4654 // 0: Input edge detection does not assert AON_PROG2 event 4655 // 1: Input edge detection asserts AON_PROG2 event 4656 #define IOC_IOCFG12_IOEV_AON_PROG2_EN 0x00800000 4657 #define IOC_IOCFG12_IOEV_AON_PROG2_EN_BITN 23 4658 #define IOC_IOCFG12_IOEV_AON_PROG2_EN_M 0x00800000 4659 #define IOC_IOCFG12_IOEV_AON_PROG2_EN_S 23 4660 4661 // Field: [22] IOEV_AON_PROG1_EN 4662 // 4663 // Event asserted by this IO when edge detection is enabled 4664 // 4665 // 0: Input edge detection does not assert AON_PROG1 event 4666 // 1: Input edge detection asserts AON_PROG1 event 4667 #define IOC_IOCFG12_IOEV_AON_PROG1_EN 0x00400000 4668 #define IOC_IOCFG12_IOEV_AON_PROG1_EN_BITN 22 4669 #define IOC_IOCFG12_IOEV_AON_PROG1_EN_M 0x00400000 4670 #define IOC_IOCFG12_IOEV_AON_PROG1_EN_S 22 4671 4672 // Field: [21] IOEV_AON_PROG0_EN 4673 // 4674 // Event asserted by this IO when edge detection is enabled 4675 // 4676 // 0: Input edge detection does not assert AON_PROG0 event 4677 // 1: Input edge detection asserts AON_PROG0 event 4678 #define IOC_IOCFG12_IOEV_AON_PROG0_EN 0x00200000 4679 #define IOC_IOCFG12_IOEV_AON_PROG0_EN_BITN 21 4680 #define IOC_IOCFG12_IOEV_AON_PROG0_EN_M 0x00200000 4681 #define IOC_IOCFG12_IOEV_AON_PROG0_EN_S 21 4682 4683 // Field: [18] EDGE_IRQ_EN 4684 // 4685 // 0: No interrupt generation 4686 // 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is 4687 // enabled) 4688 #define IOC_IOCFG12_EDGE_IRQ_EN 0x00040000 4689 #define IOC_IOCFG12_EDGE_IRQ_EN_BITN 18 4690 #define IOC_IOCFG12_EDGE_IRQ_EN_M 0x00040000 4691 #define IOC_IOCFG12_EDGE_IRQ_EN_S 18 4692 4693 // Field: [17:16] EDGE_DET 4694 // 4695 // Enable generation of edge detection events on this IO 4696 // ENUMs: 4697 // BOTH Positive and negative edge detection 4698 // POS Positive edge detection 4699 // NEG Negative edge detection 4700 // NONE No edge detection 4701 #define IOC_IOCFG12_EDGE_DET_W 2 4702 #define IOC_IOCFG12_EDGE_DET_M 0x00030000 4703 #define IOC_IOCFG12_EDGE_DET_S 16 4704 #define IOC_IOCFG12_EDGE_DET_BOTH 0x00030000 4705 #define IOC_IOCFG12_EDGE_DET_POS 0x00020000 4706 #define IOC_IOCFG12_EDGE_DET_NEG 0x00010000 4707 #define IOC_IOCFG12_EDGE_DET_NONE 0x00000000 4708 4709 // Field: [14:13] PULL_CTL 4710 // 4711 // Pull control 4712 // ENUMs: 4713 // DIS No pull 4714 // UP Pull up 4715 // DWN Pull down 4716 #define IOC_IOCFG12_PULL_CTL_W 2 4717 #define IOC_IOCFG12_PULL_CTL_M 0x00006000 4718 #define IOC_IOCFG12_PULL_CTL_S 13 4719 #define IOC_IOCFG12_PULL_CTL_DIS 0x00006000 4720 #define IOC_IOCFG12_PULL_CTL_UP 0x00004000 4721 #define IOC_IOCFG12_PULL_CTL_DWN 0x00002000 4722 4723 // Field: [12] SLEW_RED 4724 // 4725 // 0: Normal slew rate 4726 // 1: Enables reduced slew rate in output driver. 4727 #define IOC_IOCFG12_SLEW_RED 0x00001000 4728 #define IOC_IOCFG12_SLEW_RED_BITN 12 4729 #define IOC_IOCFG12_SLEW_RED_M 0x00001000 4730 #define IOC_IOCFG12_SLEW_RED_S 12 4731 4732 // Field: [11:10] IOCURR 4733 // 4734 // Selects IO current mode of this IO. 4735 // ENUMs: 4736 // 4_8MA Extended-Current (EC) mode: Min 8 mA for double 4737 // drive strength IOs (min 4 mA for normal IOs) 4738 // when IOSTR is set to AUTO 4739 // 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set 4740 // to AUTO 4741 // 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set 4742 // to AUTO 4743 #define IOC_IOCFG12_IOCURR_W 2 4744 #define IOC_IOCFG12_IOCURR_M 0x00000C00 4745 #define IOC_IOCFG12_IOCURR_S 10 4746 #define IOC_IOCFG12_IOCURR_4_8MA 0x00000800 4747 #define IOC_IOCFG12_IOCURR_4MA 0x00000400 4748 #define IOC_IOCFG12_IOCURR_2MA 0x00000000 4749 4750 // Field: [9:8] IOSTR 4751 // 4752 // Select source for drive strength control of this IO. 4753 // This setting controls the drive strength of the Low-Current (LC) mode. 4754 // Higher drive strength can be selected in IOCURR 4755 // ENUMs: 4756 // MAX Maximum drive strength, controlled by 4757 // AON_IOC:IOSTRMAX (min 2 mA @1.8V with default 4758 // values) 4759 // MED Medium drive strength, controlled by 4760 // AON_IOC:IOSTRMED (min 2 mA @2.5V with default 4761 // values) 4762 // MIN Minimum drive strength, controlled by 4763 // AON_IOC:IOSTRMIN (min 2 mA @3.3V with default 4764 // values) 4765 // AUTO Automatic drive strength, controlled by AON BATMON 4766 // based on battery voltage. (min 2 mA @VDDS) 4767 #define IOC_IOCFG12_IOSTR_W 2 4768 #define IOC_IOCFG12_IOSTR_M 0x00000300 4769 #define IOC_IOCFG12_IOSTR_S 8 4770 #define IOC_IOCFG12_IOSTR_MAX 0x00000300 4771 #define IOC_IOCFG12_IOSTR_MED 0x00000200 4772 #define IOC_IOCFG12_IOSTR_MIN 0x00000100 4773 #define IOC_IOCFG12_IOSTR_AUTO 0x00000000 4774 4775 // Field: [7] IOEV_RTC_EN 4776 // 4777 // Event asserted by this IO when edge detection is enabled 4778 // 4779 // 0: Input edge detection does not assert RTC event 4780 // 1: Input edge detection asserts RTC event 4781 #define IOC_IOCFG12_IOEV_RTC_EN 0x00000080 4782 #define IOC_IOCFG12_IOEV_RTC_EN_BITN 7 4783 #define IOC_IOCFG12_IOEV_RTC_EN_M 0x00000080 4784 #define IOC_IOCFG12_IOEV_RTC_EN_S 7 4785 4786 // Field: [6] IOEV_MCU_WU_EN 4787 // 4788 // Event asserted by this IO when edge detection is enabled 4789 // 4790 // 0: Input edge detection does not assert MCU_WU event 4791 // 1: Input edge detection asserts MCU_WU event 4792 #define IOC_IOCFG12_IOEV_MCU_WU_EN 0x00000040 4793 #define IOC_IOCFG12_IOEV_MCU_WU_EN_BITN 6 4794 #define IOC_IOCFG12_IOEV_MCU_WU_EN_M 0x00000040 4795 #define IOC_IOCFG12_IOEV_MCU_WU_EN_S 6 4796 4797 // Field: [5:0] PORT_ID 4798 // 4799 // Selects usage for DIO12 4800 // Note: This field should not be written other than the times when PORT_ID 4801 // value is specifically required to change. 4802 // ENUMs: 4803 // RFC_SMI_CL_IN RF Core SMI Command Link In 4804 // RFC_SMI_CL_OUT RF Core SMI Command Link Out 4805 // RFC_SMI_DL_IN RF Core SMI Data Link In 4806 // RFC_SMI_DL_OUT RF Core SMI Data Link Out 4807 // RFC_GPI1 RF Core Data In 1 4808 // RFC_GPI0 RF Core Data In 0 4809 // RFC_GPO3 RF Core Data Out 3 4810 // RFC_GPO2 RF Core Data Out 2 4811 // RFC_GPO1 RF Core Data Out 1 4812 // RFC_GPO0 RF Core Data Out 0 4813 // RFC_TRC RF Core Trace 4814 // I2S_MCLK I2S MCLK 4815 // I2S_BCLK I2S BCLK 4816 // I2S_WCLK I2S WCLK 4817 // I2S_AD1 I2S Data 1 4818 // I2S_AD0 I2S Data 0 4819 // SSI1_CLK SSI1 CLK 4820 // SSI1_FSS SSI1 FSS 4821 // SSI1_TX SSI1 TX 4822 // SSI1_RX SSI1 RX 4823 // CPU_SWV CPU SWV 4824 // PORT_EVENT7 PORT EVENT 7 4825 // Can be used as a general 4826 // purpose IO event by selecting it through 4827 // registers in the EVENT module, for example 4828 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 4829 // and so on 4830 // PORT_EVENT6 PORT EVENT 6 4831 // Can be used as a general 4832 // purpose IO event by selecting it through 4833 // registers in the EVENT module, for example 4834 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 4835 // and so on 4836 // PORT_EVENT5 PORT EVENT 5 4837 // Can be used as a general 4838 // purpose IO event by selecting it through 4839 // registers in the EVENT module, for example 4840 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 4841 // and so on 4842 // PORT_EVENT4 PORT EVENT 4 4843 // Can be used as a general 4844 // purpose IO event by selecting it through 4845 // registers in the EVENT module, for example 4846 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 4847 // and so on 4848 // PORT_EVENT3 PORT EVENT 3 4849 // Can be used as a general 4850 // purpose IO event by selecting it through 4851 // registers in the EVENT module, for example 4852 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 4853 // and so on 4854 // PORT_EVENT2 PORT EVENT 2 4855 // Can be used as a general 4856 // purpose IO event by selecting it through 4857 // registers in the EVENT module, for example 4858 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 4859 // and so on 4860 // PORT_EVENT1 PORT EVENT 1 4861 // Can be used as a general 4862 // purpose IO event by selecting it through 4863 // registers in the EVENT module, for example 4864 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 4865 // and so on 4866 // PORT_EVENT0 PORT EVENT 0 4867 // Can be used as a general 4868 // purpose IO event by selecting it through 4869 // registers in the EVENT module, for example 4870 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 4871 // and so on 4872 // UART1_RTS UART1 RTS 4873 // UART1_CTS UART1 CTS 4874 // UART1_TX UART1 TX 4875 // UART1_RX UART1 RX 4876 // UART0_RTS UART0 RTS 4877 // UART0_CTS UART0 CTS 4878 // UART0_TX UART0 TX 4879 // UART0_RX UART0 RX 4880 // I2C_MSSCL I2C Clock 4881 // I2C_MSSDA I2C Data 4882 // SSI0_CLK SSI0 CLK 4883 // SSI0_FSS SSI0 FSS 4884 // SSI0_TX SSI0 TX 4885 // SSI0_RX SSI0 RX 4886 // AUX_IO AUX IO 4887 // AON_CLK32K AON 32 KHz clock (SCLK_LF) 4888 // GPIO General Purpose IO 4889 #define IOC_IOCFG12_PORT_ID_W 6 4890 #define IOC_IOCFG12_PORT_ID_M 0x0000003F 4891 #define IOC_IOCFG12_PORT_ID_S 0 4892 #define IOC_IOCFG12_PORT_ID_RFC_SMI_CL_IN 0x00000038 4893 #define IOC_IOCFG12_PORT_ID_RFC_SMI_CL_OUT 0x00000037 4894 #define IOC_IOCFG12_PORT_ID_RFC_SMI_DL_IN 0x00000036 4895 #define IOC_IOCFG12_PORT_ID_RFC_SMI_DL_OUT 0x00000035 4896 #define IOC_IOCFG12_PORT_ID_RFC_GPI1 0x00000034 4897 #define IOC_IOCFG12_PORT_ID_RFC_GPI0 0x00000033 4898 #define IOC_IOCFG12_PORT_ID_RFC_GPO3 0x00000032 4899 #define IOC_IOCFG12_PORT_ID_RFC_GPO2 0x00000031 4900 #define IOC_IOCFG12_PORT_ID_RFC_GPO1 0x00000030 4901 #define IOC_IOCFG12_PORT_ID_RFC_GPO0 0x0000002F 4902 #define IOC_IOCFG12_PORT_ID_RFC_TRC 0x0000002E 4903 #define IOC_IOCFG12_PORT_ID_I2S_MCLK 0x00000029 4904 #define IOC_IOCFG12_PORT_ID_I2S_BCLK 0x00000028 4905 #define IOC_IOCFG12_PORT_ID_I2S_WCLK 0x00000027 4906 #define IOC_IOCFG12_PORT_ID_I2S_AD1 0x00000026 4907 #define IOC_IOCFG12_PORT_ID_I2S_AD0 0x00000025 4908 #define IOC_IOCFG12_PORT_ID_SSI1_CLK 0x00000024 4909 #define IOC_IOCFG12_PORT_ID_SSI1_FSS 0x00000023 4910 #define IOC_IOCFG12_PORT_ID_SSI1_TX 0x00000022 4911 #define IOC_IOCFG12_PORT_ID_SSI1_RX 0x00000021 4912 #define IOC_IOCFG12_PORT_ID_CPU_SWV 0x00000020 4913 #define IOC_IOCFG12_PORT_ID_PORT_EVENT7 0x0000001E 4914 #define IOC_IOCFG12_PORT_ID_PORT_EVENT6 0x0000001D 4915 #define IOC_IOCFG12_PORT_ID_PORT_EVENT5 0x0000001C 4916 #define IOC_IOCFG12_PORT_ID_PORT_EVENT4 0x0000001B 4917 #define IOC_IOCFG12_PORT_ID_PORT_EVENT3 0x0000001A 4918 #define IOC_IOCFG12_PORT_ID_PORT_EVENT2 0x00000019 4919 #define IOC_IOCFG12_PORT_ID_PORT_EVENT1 0x00000018 4920 #define IOC_IOCFG12_PORT_ID_PORT_EVENT0 0x00000017 4921 #define IOC_IOCFG12_PORT_ID_UART1_RTS 0x00000016 4922 #define IOC_IOCFG12_PORT_ID_UART1_CTS 0x00000015 4923 #define IOC_IOCFG12_PORT_ID_UART1_TX 0x00000014 4924 #define IOC_IOCFG12_PORT_ID_UART1_RX 0x00000013 4925 #define IOC_IOCFG12_PORT_ID_UART0_RTS 0x00000012 4926 #define IOC_IOCFG12_PORT_ID_UART0_CTS 0x00000011 4927 #define IOC_IOCFG12_PORT_ID_UART0_TX 0x00000010 4928 #define IOC_IOCFG12_PORT_ID_UART0_RX 0x0000000F 4929 #define IOC_IOCFG12_PORT_ID_I2C_MSSCL 0x0000000E 4930 #define IOC_IOCFG12_PORT_ID_I2C_MSSDA 0x0000000D 4931 #define IOC_IOCFG12_PORT_ID_SSI0_CLK 0x0000000C 4932 #define IOC_IOCFG12_PORT_ID_SSI0_FSS 0x0000000B 4933 #define IOC_IOCFG12_PORT_ID_SSI0_TX 0x0000000A 4934 #define IOC_IOCFG12_PORT_ID_SSI0_RX 0x00000009 4935 #define IOC_IOCFG12_PORT_ID_AUX_IO 0x00000008 4936 #define IOC_IOCFG12_PORT_ID_AON_CLK32K 0x00000007 4937 #define IOC_IOCFG12_PORT_ID_GPIO 0x00000000 4938 4939 //***************************************************************************** 4940 // 4941 // Register: IOC_O_IOCFG13 4942 // 4943 //***************************************************************************** 4944 // Field: [30] HYST_EN 4945 // 4946 // 0: Input hysteresis disable 4947 // 1: Input hysteresis enable 4948 #define IOC_IOCFG13_HYST_EN 0x40000000 4949 #define IOC_IOCFG13_HYST_EN_BITN 30 4950 #define IOC_IOCFG13_HYST_EN_M 0x40000000 4951 #define IOC_IOCFG13_HYST_EN_S 30 4952 4953 // Field: [29] IE 4954 // 4955 // 0: Input disabled 4956 // 1: Input enabled 4957 // 4958 // Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be 4959 // ignored. 4960 #define IOC_IOCFG13_IE 0x20000000 4961 #define IOC_IOCFG13_IE_BITN 29 4962 #define IOC_IOCFG13_IE_M 0x20000000 4963 #define IOC_IOCFG13_IE_S 29 4964 4965 // Field: [28:27] WU_CFG 4966 // 4967 // If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or 4968 // >0x08: 4969 // 4970 // 00: No wake-up 4971 // 01: No wake-up 4972 // 10: Wakes up from shutdown if this pad is going low. 4973 // 11: Wakes up from shutdown if this pad is going high. 4974 // 4975 // If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, 4976 // this register only sets wakeup enable or not. 4977 // 4978 // 00, 01: Wakeup disabled 4979 // 10, 11: Wakeup enabled 4980 // 4981 // Polarity is controlled from AON registers. 4982 // 4983 // Note:When the MSB is set, the IOC will deactivate the output enable for the 4984 // DIO. 4985 #define IOC_IOCFG13_WU_CFG_W 2 4986 #define IOC_IOCFG13_WU_CFG_M 0x18000000 4987 #define IOC_IOCFG13_WU_CFG_S 27 4988 4989 // Field: [26:24] IOMODE 4990 // 4991 // IO Mode 4992 // Not applicable for IO configured for AON periph. signals and AUX PORT_ID 4993 // 0x01-0x08 4994 // AUX has its own open_source/drain configuration. 4995 // 4996 // 0x2: Reserved. Undefined behavior. 4997 // 0x3: Reserved. Undefined behavior. 4998 // ENUMs: 4999 // OPENSRC_INV Open Source 5000 // Inverted input / output 5001 // OPENSRC Open Source 5002 // Normal input / output 5003 // OPENDR_INV Open Drain 5004 // Inverted input / output 5005 // OPENDR Open Drain, 5006 // Normal input / output 5007 // INV Inverted input / ouput 5008 // NORMAL Normal input / output 5009 #define IOC_IOCFG13_IOMODE_W 3 5010 #define IOC_IOCFG13_IOMODE_M 0x07000000 5011 #define IOC_IOCFG13_IOMODE_S 24 5012 #define IOC_IOCFG13_IOMODE_OPENSRC_INV 0x07000000 5013 #define IOC_IOCFG13_IOMODE_OPENSRC 0x06000000 5014 #define IOC_IOCFG13_IOMODE_OPENDR_INV 0x05000000 5015 #define IOC_IOCFG13_IOMODE_OPENDR 0x04000000 5016 #define IOC_IOCFG13_IOMODE_INV 0x01000000 5017 #define IOC_IOCFG13_IOMODE_NORMAL 0x00000000 5018 5019 // Field: [23] IOEV_AON_PROG2_EN 5020 // 5021 // Event asserted by this IO when edge detection is enabled 5022 // 5023 // 0: Input edge detection does not assert AON_PROG2 event 5024 // 1: Input edge detection asserts AON_PROG2 event 5025 #define IOC_IOCFG13_IOEV_AON_PROG2_EN 0x00800000 5026 #define IOC_IOCFG13_IOEV_AON_PROG2_EN_BITN 23 5027 #define IOC_IOCFG13_IOEV_AON_PROG2_EN_M 0x00800000 5028 #define IOC_IOCFG13_IOEV_AON_PROG2_EN_S 23 5029 5030 // Field: [22] IOEV_AON_PROG1_EN 5031 // 5032 // Event asserted by this IO when edge detection is enabled 5033 // 5034 // 0: Input edge detection does not assert AON_PROG1 event 5035 // 1: Input edge detection asserts AON_PROG1 event 5036 #define IOC_IOCFG13_IOEV_AON_PROG1_EN 0x00400000 5037 #define IOC_IOCFG13_IOEV_AON_PROG1_EN_BITN 22 5038 #define IOC_IOCFG13_IOEV_AON_PROG1_EN_M 0x00400000 5039 #define IOC_IOCFG13_IOEV_AON_PROG1_EN_S 22 5040 5041 // Field: [21] IOEV_AON_PROG0_EN 5042 // 5043 // Event asserted by this IO when edge detection is enabled 5044 // 5045 // 0: Input edge detection does not assert AON_PROG0 event 5046 // 1: Input edge detection asserts AON_PROG0 event 5047 #define IOC_IOCFG13_IOEV_AON_PROG0_EN 0x00200000 5048 #define IOC_IOCFG13_IOEV_AON_PROG0_EN_BITN 21 5049 #define IOC_IOCFG13_IOEV_AON_PROG0_EN_M 0x00200000 5050 #define IOC_IOCFG13_IOEV_AON_PROG0_EN_S 21 5051 5052 // Field: [18] EDGE_IRQ_EN 5053 // 5054 // 0: No interrupt generation 5055 // 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is 5056 // enabled) 5057 #define IOC_IOCFG13_EDGE_IRQ_EN 0x00040000 5058 #define IOC_IOCFG13_EDGE_IRQ_EN_BITN 18 5059 #define IOC_IOCFG13_EDGE_IRQ_EN_M 0x00040000 5060 #define IOC_IOCFG13_EDGE_IRQ_EN_S 18 5061 5062 // Field: [17:16] EDGE_DET 5063 // 5064 // Enable generation of edge detection events on this IO 5065 // ENUMs: 5066 // BOTH Positive and negative edge detection 5067 // POS Positive edge detection 5068 // NEG Negative edge detection 5069 // NONE No edge detection 5070 #define IOC_IOCFG13_EDGE_DET_W 2 5071 #define IOC_IOCFG13_EDGE_DET_M 0x00030000 5072 #define IOC_IOCFG13_EDGE_DET_S 16 5073 #define IOC_IOCFG13_EDGE_DET_BOTH 0x00030000 5074 #define IOC_IOCFG13_EDGE_DET_POS 0x00020000 5075 #define IOC_IOCFG13_EDGE_DET_NEG 0x00010000 5076 #define IOC_IOCFG13_EDGE_DET_NONE 0x00000000 5077 5078 // Field: [14:13] PULL_CTL 5079 // 5080 // Pull control 5081 // ENUMs: 5082 // DIS No pull 5083 // UP Pull up 5084 // DWN Pull down 5085 #define IOC_IOCFG13_PULL_CTL_W 2 5086 #define IOC_IOCFG13_PULL_CTL_M 0x00006000 5087 #define IOC_IOCFG13_PULL_CTL_S 13 5088 #define IOC_IOCFG13_PULL_CTL_DIS 0x00006000 5089 #define IOC_IOCFG13_PULL_CTL_UP 0x00004000 5090 #define IOC_IOCFG13_PULL_CTL_DWN 0x00002000 5091 5092 // Field: [12] SLEW_RED 5093 // 5094 // 0: Normal slew rate 5095 // 1: Enables reduced slew rate in output driver. 5096 #define IOC_IOCFG13_SLEW_RED 0x00001000 5097 #define IOC_IOCFG13_SLEW_RED_BITN 12 5098 #define IOC_IOCFG13_SLEW_RED_M 0x00001000 5099 #define IOC_IOCFG13_SLEW_RED_S 12 5100 5101 // Field: [11:10] IOCURR 5102 // 5103 // Selects IO current mode of this IO. 5104 // ENUMs: 5105 // 4_8MA Extended-Current (EC) mode: Min 8 mA for double 5106 // drive strength IOs (min 4 mA for normal IOs) 5107 // when IOSTR is set to AUTO 5108 // 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set 5109 // to AUTO 5110 // 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set 5111 // to AUTO 5112 #define IOC_IOCFG13_IOCURR_W 2 5113 #define IOC_IOCFG13_IOCURR_M 0x00000C00 5114 #define IOC_IOCFG13_IOCURR_S 10 5115 #define IOC_IOCFG13_IOCURR_4_8MA 0x00000800 5116 #define IOC_IOCFG13_IOCURR_4MA 0x00000400 5117 #define IOC_IOCFG13_IOCURR_2MA 0x00000000 5118 5119 // Field: [9:8] IOSTR 5120 // 5121 // Select source for drive strength control of this IO. 5122 // This setting controls the drive strength of the Low-Current (LC) mode. 5123 // Higher drive strength can be selected in IOCURR 5124 // ENUMs: 5125 // MAX Maximum drive strength, controlled by 5126 // AON_IOC:IOSTRMAX (min 2 mA @1.8V with default 5127 // values) 5128 // MED Medium drive strength, controlled by 5129 // AON_IOC:IOSTRMED (min 2 mA @2.5V with default 5130 // values) 5131 // MIN Minimum drive strength, controlled by 5132 // AON_IOC:IOSTRMIN (min 2 mA @3.3V with default 5133 // values) 5134 // AUTO Automatic drive strength, controlled by AON BATMON 5135 // based on battery voltage. (min 2 mA @VDDS) 5136 #define IOC_IOCFG13_IOSTR_W 2 5137 #define IOC_IOCFG13_IOSTR_M 0x00000300 5138 #define IOC_IOCFG13_IOSTR_S 8 5139 #define IOC_IOCFG13_IOSTR_MAX 0x00000300 5140 #define IOC_IOCFG13_IOSTR_MED 0x00000200 5141 #define IOC_IOCFG13_IOSTR_MIN 0x00000100 5142 #define IOC_IOCFG13_IOSTR_AUTO 0x00000000 5143 5144 // Field: [7] IOEV_RTC_EN 5145 // 5146 // Event asserted by this IO when edge detection is enabled 5147 // 5148 // 0: Input edge detection does not assert RTC event 5149 // 1: Input edge detection asserts RTC event 5150 #define IOC_IOCFG13_IOEV_RTC_EN 0x00000080 5151 #define IOC_IOCFG13_IOEV_RTC_EN_BITN 7 5152 #define IOC_IOCFG13_IOEV_RTC_EN_M 0x00000080 5153 #define IOC_IOCFG13_IOEV_RTC_EN_S 7 5154 5155 // Field: [6] IOEV_MCU_WU_EN 5156 // 5157 // Event asserted by this IO when edge detection is enabled 5158 // 5159 // 0: Input edge detection does not assert MCU_WU event 5160 // 1: Input edge detection asserts MCU_WU event 5161 #define IOC_IOCFG13_IOEV_MCU_WU_EN 0x00000040 5162 #define IOC_IOCFG13_IOEV_MCU_WU_EN_BITN 6 5163 #define IOC_IOCFG13_IOEV_MCU_WU_EN_M 0x00000040 5164 #define IOC_IOCFG13_IOEV_MCU_WU_EN_S 6 5165 5166 // Field: [5:0] PORT_ID 5167 // 5168 // Selects usage for DIO13 5169 // Note: This field should not be written other than the times when PORT_ID 5170 // value is specifically required to change. 5171 // ENUMs: 5172 // RFC_SMI_CL_IN RF Core SMI Command Link In 5173 // RFC_SMI_CL_OUT RF Core SMI Command Link Out 5174 // RFC_SMI_DL_IN RF Core SMI Data Link In 5175 // RFC_SMI_DL_OUT RF Core SMI Data Link Out 5176 // RFC_GPI1 RF Core Data In 1 5177 // RFC_GPI0 RF Core Data In 0 5178 // RFC_GPO3 RF Core Data Out 3 5179 // RFC_GPO2 RF Core Data Out 2 5180 // RFC_GPO1 RF Core Data Out 1 5181 // RFC_GPO0 RF Core Data Out 0 5182 // RFC_TRC RF Core Trace 5183 // I2S_MCLK I2S MCLK 5184 // I2S_BCLK I2S BCLK 5185 // I2S_WCLK I2S WCLK 5186 // I2S_AD1 I2S Data 1 5187 // I2S_AD0 I2S Data 0 5188 // SSI1_CLK SSI1 CLK 5189 // SSI1_FSS SSI1 FSS 5190 // SSI1_TX SSI1 TX 5191 // SSI1_RX SSI1 RX 5192 // CPU_SWV CPU SWV 5193 // PORT_EVENT7 PORT EVENT 7 5194 // Can be used as a general 5195 // purpose IO event by selecting it through 5196 // registers in the EVENT module, for example 5197 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 5198 // and so on 5199 // PORT_EVENT6 PORT EVENT 6 5200 // Can be used as a general 5201 // purpose IO event by selecting it through 5202 // registers in the EVENT module, for example 5203 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 5204 // and so on 5205 // PORT_EVENT5 PORT EVENT 5 5206 // Can be used as a general 5207 // purpose IO event by selecting it through 5208 // registers in the EVENT module, for example 5209 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 5210 // and so on 5211 // PORT_EVENT4 PORT EVENT 4 5212 // Can be used as a general 5213 // purpose IO event by selecting it through 5214 // registers in the EVENT module, for example 5215 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 5216 // and so on 5217 // PORT_EVENT3 PORT EVENT 3 5218 // Can be used as a general 5219 // purpose IO event by selecting it through 5220 // registers in the EVENT module, for example 5221 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 5222 // and so on 5223 // PORT_EVENT2 PORT EVENT 2 5224 // Can be used as a general 5225 // purpose IO event by selecting it through 5226 // registers in the EVENT module, for example 5227 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 5228 // and so on 5229 // PORT_EVENT1 PORT EVENT 1 5230 // Can be used as a general 5231 // purpose IO event by selecting it through 5232 // registers in the EVENT module, for example 5233 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 5234 // and so on 5235 // PORT_EVENT0 PORT EVENT 0 5236 // Can be used as a general 5237 // purpose IO event by selecting it through 5238 // registers in the EVENT module, for example 5239 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 5240 // and so on 5241 // UART1_RTS UART1 RTS 5242 // UART1_CTS UART1 CTS 5243 // UART1_TX UART1 TX 5244 // UART1_RX UART1 RX 5245 // UART0_RTS UART0 RTS 5246 // UART0_CTS UART0 CTS 5247 // UART0_TX UART0 TX 5248 // UART0_RX UART0 RX 5249 // I2C_MSSCL I2C Clock 5250 // I2C_MSSDA I2C Data 5251 // SSI0_CLK SSI0 CLK 5252 // SSI0_FSS SSI0 FSS 5253 // SSI0_TX SSI0 TX 5254 // SSI0_RX SSI0 RX 5255 // AUX_IO AUX IO 5256 // AON_CLK32K AON 32 KHz clock (SCLK_LF) 5257 // GPIO General Purpose IO 5258 #define IOC_IOCFG13_PORT_ID_W 6 5259 #define IOC_IOCFG13_PORT_ID_M 0x0000003F 5260 #define IOC_IOCFG13_PORT_ID_S 0 5261 #define IOC_IOCFG13_PORT_ID_RFC_SMI_CL_IN 0x00000038 5262 #define IOC_IOCFG13_PORT_ID_RFC_SMI_CL_OUT 0x00000037 5263 #define IOC_IOCFG13_PORT_ID_RFC_SMI_DL_IN 0x00000036 5264 #define IOC_IOCFG13_PORT_ID_RFC_SMI_DL_OUT 0x00000035 5265 #define IOC_IOCFG13_PORT_ID_RFC_GPI1 0x00000034 5266 #define IOC_IOCFG13_PORT_ID_RFC_GPI0 0x00000033 5267 #define IOC_IOCFG13_PORT_ID_RFC_GPO3 0x00000032 5268 #define IOC_IOCFG13_PORT_ID_RFC_GPO2 0x00000031 5269 #define IOC_IOCFG13_PORT_ID_RFC_GPO1 0x00000030 5270 #define IOC_IOCFG13_PORT_ID_RFC_GPO0 0x0000002F 5271 #define IOC_IOCFG13_PORT_ID_RFC_TRC 0x0000002E 5272 #define IOC_IOCFG13_PORT_ID_I2S_MCLK 0x00000029 5273 #define IOC_IOCFG13_PORT_ID_I2S_BCLK 0x00000028 5274 #define IOC_IOCFG13_PORT_ID_I2S_WCLK 0x00000027 5275 #define IOC_IOCFG13_PORT_ID_I2S_AD1 0x00000026 5276 #define IOC_IOCFG13_PORT_ID_I2S_AD0 0x00000025 5277 #define IOC_IOCFG13_PORT_ID_SSI1_CLK 0x00000024 5278 #define IOC_IOCFG13_PORT_ID_SSI1_FSS 0x00000023 5279 #define IOC_IOCFG13_PORT_ID_SSI1_TX 0x00000022 5280 #define IOC_IOCFG13_PORT_ID_SSI1_RX 0x00000021 5281 #define IOC_IOCFG13_PORT_ID_CPU_SWV 0x00000020 5282 #define IOC_IOCFG13_PORT_ID_PORT_EVENT7 0x0000001E 5283 #define IOC_IOCFG13_PORT_ID_PORT_EVENT6 0x0000001D 5284 #define IOC_IOCFG13_PORT_ID_PORT_EVENT5 0x0000001C 5285 #define IOC_IOCFG13_PORT_ID_PORT_EVENT4 0x0000001B 5286 #define IOC_IOCFG13_PORT_ID_PORT_EVENT3 0x0000001A 5287 #define IOC_IOCFG13_PORT_ID_PORT_EVENT2 0x00000019 5288 #define IOC_IOCFG13_PORT_ID_PORT_EVENT1 0x00000018 5289 #define IOC_IOCFG13_PORT_ID_PORT_EVENT0 0x00000017 5290 #define IOC_IOCFG13_PORT_ID_UART1_RTS 0x00000016 5291 #define IOC_IOCFG13_PORT_ID_UART1_CTS 0x00000015 5292 #define IOC_IOCFG13_PORT_ID_UART1_TX 0x00000014 5293 #define IOC_IOCFG13_PORT_ID_UART1_RX 0x00000013 5294 #define IOC_IOCFG13_PORT_ID_UART0_RTS 0x00000012 5295 #define IOC_IOCFG13_PORT_ID_UART0_CTS 0x00000011 5296 #define IOC_IOCFG13_PORT_ID_UART0_TX 0x00000010 5297 #define IOC_IOCFG13_PORT_ID_UART0_RX 0x0000000F 5298 #define IOC_IOCFG13_PORT_ID_I2C_MSSCL 0x0000000E 5299 #define IOC_IOCFG13_PORT_ID_I2C_MSSDA 0x0000000D 5300 #define IOC_IOCFG13_PORT_ID_SSI0_CLK 0x0000000C 5301 #define IOC_IOCFG13_PORT_ID_SSI0_FSS 0x0000000B 5302 #define IOC_IOCFG13_PORT_ID_SSI0_TX 0x0000000A 5303 #define IOC_IOCFG13_PORT_ID_SSI0_RX 0x00000009 5304 #define IOC_IOCFG13_PORT_ID_AUX_IO 0x00000008 5305 #define IOC_IOCFG13_PORT_ID_AON_CLK32K 0x00000007 5306 #define IOC_IOCFG13_PORT_ID_GPIO 0x00000000 5307 5308 //***************************************************************************** 5309 // 5310 // Register: IOC_O_IOCFG14 5311 // 5312 //***************************************************************************** 5313 // Field: [30] HYST_EN 5314 // 5315 // 0: Input hysteresis disable 5316 // 1: Input hysteresis enable 5317 #define IOC_IOCFG14_HYST_EN 0x40000000 5318 #define IOC_IOCFG14_HYST_EN_BITN 30 5319 #define IOC_IOCFG14_HYST_EN_M 0x40000000 5320 #define IOC_IOCFG14_HYST_EN_S 30 5321 5322 // Field: [29] IE 5323 // 5324 // 0: Input disabled 5325 // 1: Input enabled 5326 // 5327 // Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be 5328 // ignored. 5329 #define IOC_IOCFG14_IE 0x20000000 5330 #define IOC_IOCFG14_IE_BITN 29 5331 #define IOC_IOCFG14_IE_M 0x20000000 5332 #define IOC_IOCFG14_IE_S 29 5333 5334 // Field: [28:27] WU_CFG 5335 // 5336 // If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or 5337 // >0x08: 5338 // 5339 // 00: No wake-up 5340 // 01: No wake-up 5341 // 10: Wakes up from shutdown if this pad is going low. 5342 // 11: Wakes up from shutdown if this pad is going high. 5343 // 5344 // If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, 5345 // this register only sets wakeup enable or not. 5346 // 5347 // 00, 01: Wakeup disabled 5348 // 10, 11: Wakeup enabled 5349 // 5350 // Polarity is controlled from AON registers. 5351 // 5352 // Note:When the MSB is set, the IOC will deactivate the output enable for the 5353 // DIO. 5354 #define IOC_IOCFG14_WU_CFG_W 2 5355 #define IOC_IOCFG14_WU_CFG_M 0x18000000 5356 #define IOC_IOCFG14_WU_CFG_S 27 5357 5358 // Field: [26:24] IOMODE 5359 // 5360 // IO Mode 5361 // Not applicable for IO configured for AON periph. signals and AUX PORT_ID 5362 // 0x01-0x08 5363 // AUX has its own open_source/drain configuration. 5364 // 5365 // 0x2: Reserved. Undefined behavior. 5366 // 0x3: Reserved. Undefined behavior. 5367 // ENUMs: 5368 // OPENSRC_INV Open Source 5369 // Inverted input / output 5370 // OPENSRC Open Source 5371 // Normal input / output 5372 // OPENDR_INV Open Drain 5373 // Inverted input / output 5374 // OPENDR Open Drain, 5375 // Normal input / output 5376 // INV Inverted input / ouput 5377 // NORMAL Normal input / output 5378 #define IOC_IOCFG14_IOMODE_W 3 5379 #define IOC_IOCFG14_IOMODE_M 0x07000000 5380 #define IOC_IOCFG14_IOMODE_S 24 5381 #define IOC_IOCFG14_IOMODE_OPENSRC_INV 0x07000000 5382 #define IOC_IOCFG14_IOMODE_OPENSRC 0x06000000 5383 #define IOC_IOCFG14_IOMODE_OPENDR_INV 0x05000000 5384 #define IOC_IOCFG14_IOMODE_OPENDR 0x04000000 5385 #define IOC_IOCFG14_IOMODE_INV 0x01000000 5386 #define IOC_IOCFG14_IOMODE_NORMAL 0x00000000 5387 5388 // Field: [23] IOEV_AON_PROG2_EN 5389 // 5390 // Event asserted by this IO when edge detection is enabled 5391 // 5392 // 0: Input edge detection does not assert AON_PROG2 event 5393 // 1: Input edge detection asserts AON_PROG2 event 5394 #define IOC_IOCFG14_IOEV_AON_PROG2_EN 0x00800000 5395 #define IOC_IOCFG14_IOEV_AON_PROG2_EN_BITN 23 5396 #define IOC_IOCFG14_IOEV_AON_PROG2_EN_M 0x00800000 5397 #define IOC_IOCFG14_IOEV_AON_PROG2_EN_S 23 5398 5399 // Field: [22] IOEV_AON_PROG1_EN 5400 // 5401 // Event asserted by this IO when edge detection is enabled 5402 // 5403 // 0: Input edge detection does not assert AON_PROG1 event 5404 // 1: Input edge detection asserts AON_PROG1 event 5405 #define IOC_IOCFG14_IOEV_AON_PROG1_EN 0x00400000 5406 #define IOC_IOCFG14_IOEV_AON_PROG1_EN_BITN 22 5407 #define IOC_IOCFG14_IOEV_AON_PROG1_EN_M 0x00400000 5408 #define IOC_IOCFG14_IOEV_AON_PROG1_EN_S 22 5409 5410 // Field: [21] IOEV_AON_PROG0_EN 5411 // 5412 // Event asserted by this IO when edge detection is enabled 5413 // 5414 // 0: Input edge detection does not assert AON_PROG0 event 5415 // 1: Input edge detection asserts AON_PROG0 event 5416 #define IOC_IOCFG14_IOEV_AON_PROG0_EN 0x00200000 5417 #define IOC_IOCFG14_IOEV_AON_PROG0_EN_BITN 21 5418 #define IOC_IOCFG14_IOEV_AON_PROG0_EN_M 0x00200000 5419 #define IOC_IOCFG14_IOEV_AON_PROG0_EN_S 21 5420 5421 // Field: [18] EDGE_IRQ_EN 5422 // 5423 // 0: No interrupt generation 5424 // 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is 5425 // enabled) 5426 #define IOC_IOCFG14_EDGE_IRQ_EN 0x00040000 5427 #define IOC_IOCFG14_EDGE_IRQ_EN_BITN 18 5428 #define IOC_IOCFG14_EDGE_IRQ_EN_M 0x00040000 5429 #define IOC_IOCFG14_EDGE_IRQ_EN_S 18 5430 5431 // Field: [17:16] EDGE_DET 5432 // 5433 // Enable generation of edge detection events on this IO 5434 // ENUMs: 5435 // BOTH Positive and negative edge detection 5436 // POS Positive edge detection 5437 // NEG Negative edge detection 5438 // NONE No edge detection 5439 #define IOC_IOCFG14_EDGE_DET_W 2 5440 #define IOC_IOCFG14_EDGE_DET_M 0x00030000 5441 #define IOC_IOCFG14_EDGE_DET_S 16 5442 #define IOC_IOCFG14_EDGE_DET_BOTH 0x00030000 5443 #define IOC_IOCFG14_EDGE_DET_POS 0x00020000 5444 #define IOC_IOCFG14_EDGE_DET_NEG 0x00010000 5445 #define IOC_IOCFG14_EDGE_DET_NONE 0x00000000 5446 5447 // Field: [14:13] PULL_CTL 5448 // 5449 // Pull control 5450 // ENUMs: 5451 // DIS No pull 5452 // UP Pull up 5453 // DWN Pull down 5454 #define IOC_IOCFG14_PULL_CTL_W 2 5455 #define IOC_IOCFG14_PULL_CTL_M 0x00006000 5456 #define IOC_IOCFG14_PULL_CTL_S 13 5457 #define IOC_IOCFG14_PULL_CTL_DIS 0x00006000 5458 #define IOC_IOCFG14_PULL_CTL_UP 0x00004000 5459 #define IOC_IOCFG14_PULL_CTL_DWN 0x00002000 5460 5461 // Field: [12] SLEW_RED 5462 // 5463 // 0: Normal slew rate 5464 // 1: Enables reduced slew rate in output driver. 5465 #define IOC_IOCFG14_SLEW_RED 0x00001000 5466 #define IOC_IOCFG14_SLEW_RED_BITN 12 5467 #define IOC_IOCFG14_SLEW_RED_M 0x00001000 5468 #define IOC_IOCFG14_SLEW_RED_S 12 5469 5470 // Field: [11:10] IOCURR 5471 // 5472 // Selects IO current mode of this IO. 5473 // ENUMs: 5474 // 4_8MA Extended-Current (EC) mode: Min 8 mA for double 5475 // drive strength IOs (min 4 mA for normal IOs) 5476 // when IOSTR is set to AUTO 5477 // 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set 5478 // to AUTO 5479 // 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set 5480 // to AUTO 5481 #define IOC_IOCFG14_IOCURR_W 2 5482 #define IOC_IOCFG14_IOCURR_M 0x00000C00 5483 #define IOC_IOCFG14_IOCURR_S 10 5484 #define IOC_IOCFG14_IOCURR_4_8MA 0x00000800 5485 #define IOC_IOCFG14_IOCURR_4MA 0x00000400 5486 #define IOC_IOCFG14_IOCURR_2MA 0x00000000 5487 5488 // Field: [9:8] IOSTR 5489 // 5490 // Select source for drive strength control of this IO. 5491 // This setting controls the drive strength of the Low-Current (LC) mode. 5492 // Higher drive strength can be selected in IOCURR 5493 // ENUMs: 5494 // MAX Maximum drive strength, controlled by 5495 // AON_IOC:IOSTRMAX (min 2 mA @1.8V with default 5496 // values) 5497 // MED Medium drive strength, controlled by 5498 // AON_IOC:IOSTRMED (min 2 mA @2.5V with default 5499 // values) 5500 // MIN Minimum drive strength, controlled by 5501 // AON_IOC:IOSTRMIN (min 2 mA @3.3V with default 5502 // values) 5503 // AUTO Automatic drive strength, controlled by AON BATMON 5504 // based on battery voltage. (min 2 mA @VDDS) 5505 #define IOC_IOCFG14_IOSTR_W 2 5506 #define IOC_IOCFG14_IOSTR_M 0x00000300 5507 #define IOC_IOCFG14_IOSTR_S 8 5508 #define IOC_IOCFG14_IOSTR_MAX 0x00000300 5509 #define IOC_IOCFG14_IOSTR_MED 0x00000200 5510 #define IOC_IOCFG14_IOSTR_MIN 0x00000100 5511 #define IOC_IOCFG14_IOSTR_AUTO 0x00000000 5512 5513 // Field: [7] IOEV_RTC_EN 5514 // 5515 // Event asserted by this IO when edge detection is enabled 5516 // 5517 // 0: Input edge detection does not assert RTC event 5518 // 1: Input edge detection asserts RTC event 5519 #define IOC_IOCFG14_IOEV_RTC_EN 0x00000080 5520 #define IOC_IOCFG14_IOEV_RTC_EN_BITN 7 5521 #define IOC_IOCFG14_IOEV_RTC_EN_M 0x00000080 5522 #define IOC_IOCFG14_IOEV_RTC_EN_S 7 5523 5524 // Field: [6] IOEV_MCU_WU_EN 5525 // 5526 // Event asserted by this IO when edge detection is enabled 5527 // 5528 // 0: Input edge detection does not assert MCU_WU event 5529 // 1: Input edge detection asserts MCU_WU event 5530 #define IOC_IOCFG14_IOEV_MCU_WU_EN 0x00000040 5531 #define IOC_IOCFG14_IOEV_MCU_WU_EN_BITN 6 5532 #define IOC_IOCFG14_IOEV_MCU_WU_EN_M 0x00000040 5533 #define IOC_IOCFG14_IOEV_MCU_WU_EN_S 6 5534 5535 // Field: [5:0] PORT_ID 5536 // 5537 // Selects usage for DIO14 5538 // Note: This field should not be written other than the times when PORT_ID 5539 // value is specifically required to change. 5540 // ENUMs: 5541 // RFC_SMI_CL_IN RF Core SMI Command Link In 5542 // RFC_SMI_CL_OUT RF Core SMI Command Link Out 5543 // RFC_SMI_DL_IN RF Core SMI Data Link In 5544 // RFC_SMI_DL_OUT RF Core SMI Data Link Out 5545 // RFC_GPI1 RF Core Data In 1 5546 // RFC_GPI0 RF Core Data In 0 5547 // RFC_GPO3 RF Core Data Out 3 5548 // RFC_GPO2 RF Core Data Out 2 5549 // RFC_GPO1 RF Core Data Out 1 5550 // RFC_GPO0 RF Core Data Out 0 5551 // RFC_TRC RF Core Trace 5552 // I2S_MCLK I2S MCLK 5553 // I2S_BCLK I2S BCLK 5554 // I2S_WCLK I2S WCLK 5555 // I2S_AD1 I2S Data 1 5556 // I2S_AD0 I2S Data 0 5557 // SSI1_CLK SSI1 CLK 5558 // SSI1_FSS SSI1 FSS 5559 // SSI1_TX SSI1 TX 5560 // SSI1_RX SSI1 RX 5561 // CPU_SWV CPU SWV 5562 // PORT_EVENT7 PORT EVENT 7 5563 // Can be used as a general 5564 // purpose IO event by selecting it through 5565 // registers in the EVENT module, for example 5566 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 5567 // and so on 5568 // PORT_EVENT6 PORT EVENT 6 5569 // Can be used as a general 5570 // purpose IO event by selecting it through 5571 // registers in the EVENT module, for example 5572 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 5573 // and so on 5574 // PORT_EVENT5 PORT EVENT 5 5575 // Can be used as a general 5576 // purpose IO event by selecting it through 5577 // registers in the EVENT module, for example 5578 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 5579 // and so on 5580 // PORT_EVENT4 PORT EVENT 4 5581 // Can be used as a general 5582 // purpose IO event by selecting it through 5583 // registers in the EVENT module, for example 5584 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 5585 // and so on 5586 // PORT_EVENT3 PORT EVENT 3 5587 // Can be used as a general 5588 // purpose IO event by selecting it through 5589 // registers in the EVENT module, for example 5590 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 5591 // and so on 5592 // PORT_EVENT2 PORT EVENT 2 5593 // Can be used as a general 5594 // purpose IO event by selecting it through 5595 // registers in the EVENT module, for example 5596 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 5597 // and so on 5598 // PORT_EVENT1 PORT EVENT 1 5599 // Can be used as a general 5600 // purpose IO event by selecting it through 5601 // registers in the EVENT module, for example 5602 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 5603 // and so on 5604 // PORT_EVENT0 PORT EVENT 0 5605 // Can be used as a general 5606 // purpose IO event by selecting it through 5607 // registers in the EVENT module, for example 5608 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 5609 // and so on 5610 // UART1_RTS UART1 RTS 5611 // UART1_CTS UART1 CTS 5612 // UART1_TX UART1 TX 5613 // UART1_RX UART1 RX 5614 // UART0_RTS UART0 RTS 5615 // UART0_CTS UART0 CTS 5616 // UART0_TX UART0 TX 5617 // UART0_RX UART0 RX 5618 // I2C_MSSCL I2C Clock 5619 // I2C_MSSDA I2C Data 5620 // SSI0_CLK SSI0 CLK 5621 // SSI0_FSS SSI0 FSS 5622 // SSI0_TX SSI0 TX 5623 // SSI0_RX SSI0 RX 5624 // AUX_IO AUX IO 5625 // AON_CLK32K AON 32 KHz clock (SCLK_LF) 5626 // GPIO General Purpose IO 5627 #define IOC_IOCFG14_PORT_ID_W 6 5628 #define IOC_IOCFG14_PORT_ID_M 0x0000003F 5629 #define IOC_IOCFG14_PORT_ID_S 0 5630 #define IOC_IOCFG14_PORT_ID_RFC_SMI_CL_IN 0x00000038 5631 #define IOC_IOCFG14_PORT_ID_RFC_SMI_CL_OUT 0x00000037 5632 #define IOC_IOCFG14_PORT_ID_RFC_SMI_DL_IN 0x00000036 5633 #define IOC_IOCFG14_PORT_ID_RFC_SMI_DL_OUT 0x00000035 5634 #define IOC_IOCFG14_PORT_ID_RFC_GPI1 0x00000034 5635 #define IOC_IOCFG14_PORT_ID_RFC_GPI0 0x00000033 5636 #define IOC_IOCFG14_PORT_ID_RFC_GPO3 0x00000032 5637 #define IOC_IOCFG14_PORT_ID_RFC_GPO2 0x00000031 5638 #define IOC_IOCFG14_PORT_ID_RFC_GPO1 0x00000030 5639 #define IOC_IOCFG14_PORT_ID_RFC_GPO0 0x0000002F 5640 #define IOC_IOCFG14_PORT_ID_RFC_TRC 0x0000002E 5641 #define IOC_IOCFG14_PORT_ID_I2S_MCLK 0x00000029 5642 #define IOC_IOCFG14_PORT_ID_I2S_BCLK 0x00000028 5643 #define IOC_IOCFG14_PORT_ID_I2S_WCLK 0x00000027 5644 #define IOC_IOCFG14_PORT_ID_I2S_AD1 0x00000026 5645 #define IOC_IOCFG14_PORT_ID_I2S_AD0 0x00000025 5646 #define IOC_IOCFG14_PORT_ID_SSI1_CLK 0x00000024 5647 #define IOC_IOCFG14_PORT_ID_SSI1_FSS 0x00000023 5648 #define IOC_IOCFG14_PORT_ID_SSI1_TX 0x00000022 5649 #define IOC_IOCFG14_PORT_ID_SSI1_RX 0x00000021 5650 #define IOC_IOCFG14_PORT_ID_CPU_SWV 0x00000020 5651 #define IOC_IOCFG14_PORT_ID_PORT_EVENT7 0x0000001E 5652 #define IOC_IOCFG14_PORT_ID_PORT_EVENT6 0x0000001D 5653 #define IOC_IOCFG14_PORT_ID_PORT_EVENT5 0x0000001C 5654 #define IOC_IOCFG14_PORT_ID_PORT_EVENT4 0x0000001B 5655 #define IOC_IOCFG14_PORT_ID_PORT_EVENT3 0x0000001A 5656 #define IOC_IOCFG14_PORT_ID_PORT_EVENT2 0x00000019 5657 #define IOC_IOCFG14_PORT_ID_PORT_EVENT1 0x00000018 5658 #define IOC_IOCFG14_PORT_ID_PORT_EVENT0 0x00000017 5659 #define IOC_IOCFG14_PORT_ID_UART1_RTS 0x00000016 5660 #define IOC_IOCFG14_PORT_ID_UART1_CTS 0x00000015 5661 #define IOC_IOCFG14_PORT_ID_UART1_TX 0x00000014 5662 #define IOC_IOCFG14_PORT_ID_UART1_RX 0x00000013 5663 #define IOC_IOCFG14_PORT_ID_UART0_RTS 0x00000012 5664 #define IOC_IOCFG14_PORT_ID_UART0_CTS 0x00000011 5665 #define IOC_IOCFG14_PORT_ID_UART0_TX 0x00000010 5666 #define IOC_IOCFG14_PORT_ID_UART0_RX 0x0000000F 5667 #define IOC_IOCFG14_PORT_ID_I2C_MSSCL 0x0000000E 5668 #define IOC_IOCFG14_PORT_ID_I2C_MSSDA 0x0000000D 5669 #define IOC_IOCFG14_PORT_ID_SSI0_CLK 0x0000000C 5670 #define IOC_IOCFG14_PORT_ID_SSI0_FSS 0x0000000B 5671 #define IOC_IOCFG14_PORT_ID_SSI0_TX 0x0000000A 5672 #define IOC_IOCFG14_PORT_ID_SSI0_RX 0x00000009 5673 #define IOC_IOCFG14_PORT_ID_AUX_IO 0x00000008 5674 #define IOC_IOCFG14_PORT_ID_AON_CLK32K 0x00000007 5675 #define IOC_IOCFG14_PORT_ID_GPIO 0x00000000 5676 5677 //***************************************************************************** 5678 // 5679 // Register: IOC_O_IOCFG15 5680 // 5681 //***************************************************************************** 5682 // Field: [30] HYST_EN 5683 // 5684 // 0: Input hysteresis disable 5685 // 1: Input hysteresis enable 5686 #define IOC_IOCFG15_HYST_EN 0x40000000 5687 #define IOC_IOCFG15_HYST_EN_BITN 30 5688 #define IOC_IOCFG15_HYST_EN_M 0x40000000 5689 #define IOC_IOCFG15_HYST_EN_S 30 5690 5691 // Field: [29] IE 5692 // 5693 // 0: Input disabled 5694 // 1: Input enabled 5695 // 5696 // Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be 5697 // ignored. 5698 #define IOC_IOCFG15_IE 0x20000000 5699 #define IOC_IOCFG15_IE_BITN 29 5700 #define IOC_IOCFG15_IE_M 0x20000000 5701 #define IOC_IOCFG15_IE_S 29 5702 5703 // Field: [28:27] WU_CFG 5704 // 5705 // If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or 5706 // >0x08: 5707 // 5708 // 00: No wake-up 5709 // 01: No wake-up 5710 // 10: Wakes up from shutdown if this pad is going low. 5711 // 11: Wakes up from shutdown if this pad is going high. 5712 // 5713 // If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, 5714 // this register only sets wakeup enable or not. 5715 // 5716 // 00, 01: Wakeup disabled 5717 // 10, 11: Wakeup enabled 5718 // 5719 // Polarity is controlled from AON registers. 5720 // 5721 // Note:When the MSB is set, the IOC will deactivate the output enable for the 5722 // DIO. 5723 #define IOC_IOCFG15_WU_CFG_W 2 5724 #define IOC_IOCFG15_WU_CFG_M 0x18000000 5725 #define IOC_IOCFG15_WU_CFG_S 27 5726 5727 // Field: [26:24] IOMODE 5728 // 5729 // IO Mode 5730 // Not applicable for IO configured for AON periph. signals and AUX PORT_ID 5731 // 0x01-0x08 5732 // AUX has its own open_source/drain configuration. 5733 // 5734 // 0x2: Reserved. Undefined behavior. 5735 // 0x3: Reserved. Undefined behavior. 5736 // ENUMs: 5737 // OPENSRC_INV Open Source 5738 // Inverted input / output 5739 // OPENSRC Open Source 5740 // Normal input / output 5741 // OPENDR_INV Open Drain 5742 // Inverted input / output 5743 // OPENDR Open Drain, 5744 // Normal input / output 5745 // INV Inverted input / ouput 5746 // NORMAL Normal input / output 5747 #define IOC_IOCFG15_IOMODE_W 3 5748 #define IOC_IOCFG15_IOMODE_M 0x07000000 5749 #define IOC_IOCFG15_IOMODE_S 24 5750 #define IOC_IOCFG15_IOMODE_OPENSRC_INV 0x07000000 5751 #define IOC_IOCFG15_IOMODE_OPENSRC 0x06000000 5752 #define IOC_IOCFG15_IOMODE_OPENDR_INV 0x05000000 5753 #define IOC_IOCFG15_IOMODE_OPENDR 0x04000000 5754 #define IOC_IOCFG15_IOMODE_INV 0x01000000 5755 #define IOC_IOCFG15_IOMODE_NORMAL 0x00000000 5756 5757 // Field: [23] IOEV_AON_PROG2_EN 5758 // 5759 // Event asserted by this IO when edge detection is enabled 5760 // 5761 // 0: Input edge detection does not assert AON_PROG2 event 5762 // 1: Input edge detection asserts AON_PROG2 event 5763 #define IOC_IOCFG15_IOEV_AON_PROG2_EN 0x00800000 5764 #define IOC_IOCFG15_IOEV_AON_PROG2_EN_BITN 23 5765 #define IOC_IOCFG15_IOEV_AON_PROG2_EN_M 0x00800000 5766 #define IOC_IOCFG15_IOEV_AON_PROG2_EN_S 23 5767 5768 // Field: [22] IOEV_AON_PROG1_EN 5769 // 5770 // Event asserted by this IO when edge detection is enabled 5771 // 5772 // 0: Input edge detection does not assert AON_PROG1 event 5773 // 1: Input edge detection asserts AON_PROG1 event 5774 #define IOC_IOCFG15_IOEV_AON_PROG1_EN 0x00400000 5775 #define IOC_IOCFG15_IOEV_AON_PROG1_EN_BITN 22 5776 #define IOC_IOCFG15_IOEV_AON_PROG1_EN_M 0x00400000 5777 #define IOC_IOCFG15_IOEV_AON_PROG1_EN_S 22 5778 5779 // Field: [21] IOEV_AON_PROG0_EN 5780 // 5781 // Event asserted by this IO when edge detection is enabled 5782 // 5783 // 0: Input edge detection does not assert AON_PROG0 event 5784 // 1: Input edge detection asserts AON_PROG0 event 5785 #define IOC_IOCFG15_IOEV_AON_PROG0_EN 0x00200000 5786 #define IOC_IOCFG15_IOEV_AON_PROG0_EN_BITN 21 5787 #define IOC_IOCFG15_IOEV_AON_PROG0_EN_M 0x00200000 5788 #define IOC_IOCFG15_IOEV_AON_PROG0_EN_S 21 5789 5790 // Field: [18] EDGE_IRQ_EN 5791 // 5792 // 0: No interrupt generation 5793 // 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is 5794 // enabled) 5795 #define IOC_IOCFG15_EDGE_IRQ_EN 0x00040000 5796 #define IOC_IOCFG15_EDGE_IRQ_EN_BITN 18 5797 #define IOC_IOCFG15_EDGE_IRQ_EN_M 0x00040000 5798 #define IOC_IOCFG15_EDGE_IRQ_EN_S 18 5799 5800 // Field: [17:16] EDGE_DET 5801 // 5802 // Enable generation of edge detection events on this IO 5803 // ENUMs: 5804 // BOTH Positive and negative edge detection 5805 // POS Positive edge detection 5806 // NEG Negative edge detection 5807 // NONE No edge detection 5808 #define IOC_IOCFG15_EDGE_DET_W 2 5809 #define IOC_IOCFG15_EDGE_DET_M 0x00030000 5810 #define IOC_IOCFG15_EDGE_DET_S 16 5811 #define IOC_IOCFG15_EDGE_DET_BOTH 0x00030000 5812 #define IOC_IOCFG15_EDGE_DET_POS 0x00020000 5813 #define IOC_IOCFG15_EDGE_DET_NEG 0x00010000 5814 #define IOC_IOCFG15_EDGE_DET_NONE 0x00000000 5815 5816 // Field: [14:13] PULL_CTL 5817 // 5818 // Pull control 5819 // ENUMs: 5820 // DIS No pull 5821 // UP Pull up 5822 // DWN Pull down 5823 #define IOC_IOCFG15_PULL_CTL_W 2 5824 #define IOC_IOCFG15_PULL_CTL_M 0x00006000 5825 #define IOC_IOCFG15_PULL_CTL_S 13 5826 #define IOC_IOCFG15_PULL_CTL_DIS 0x00006000 5827 #define IOC_IOCFG15_PULL_CTL_UP 0x00004000 5828 #define IOC_IOCFG15_PULL_CTL_DWN 0x00002000 5829 5830 // Field: [12] SLEW_RED 5831 // 5832 // 0: Normal slew rate 5833 // 1: Enables reduced slew rate in output driver. 5834 #define IOC_IOCFG15_SLEW_RED 0x00001000 5835 #define IOC_IOCFG15_SLEW_RED_BITN 12 5836 #define IOC_IOCFG15_SLEW_RED_M 0x00001000 5837 #define IOC_IOCFG15_SLEW_RED_S 12 5838 5839 // Field: [11:10] IOCURR 5840 // 5841 // Selects IO current mode of this IO. 5842 // ENUMs: 5843 // 4_8MA Extended-Current (EC) mode: Min 8 mA for double 5844 // drive strength IOs (min 4 mA for normal IOs) 5845 // when IOSTR is set to AUTO 5846 // 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set 5847 // to AUTO 5848 // 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set 5849 // to AUTO 5850 #define IOC_IOCFG15_IOCURR_W 2 5851 #define IOC_IOCFG15_IOCURR_M 0x00000C00 5852 #define IOC_IOCFG15_IOCURR_S 10 5853 #define IOC_IOCFG15_IOCURR_4_8MA 0x00000800 5854 #define IOC_IOCFG15_IOCURR_4MA 0x00000400 5855 #define IOC_IOCFG15_IOCURR_2MA 0x00000000 5856 5857 // Field: [9:8] IOSTR 5858 // 5859 // Select source for drive strength control of this IO. 5860 // This setting controls the drive strength of the Low-Current (LC) mode. 5861 // Higher drive strength can be selected in IOCURR 5862 // ENUMs: 5863 // MAX Maximum drive strength, controlled by 5864 // AON_IOC:IOSTRMAX (min 2 mA @1.8V with default 5865 // values) 5866 // MED Medium drive strength, controlled by 5867 // AON_IOC:IOSTRMED (min 2 mA @2.5V with default 5868 // values) 5869 // MIN Minimum drive strength, controlled by 5870 // AON_IOC:IOSTRMIN (min 2 mA @3.3V with default 5871 // values) 5872 // AUTO Automatic drive strength, controlled by AON BATMON 5873 // based on battery voltage. (min 2 mA @VDDS) 5874 #define IOC_IOCFG15_IOSTR_W 2 5875 #define IOC_IOCFG15_IOSTR_M 0x00000300 5876 #define IOC_IOCFG15_IOSTR_S 8 5877 #define IOC_IOCFG15_IOSTR_MAX 0x00000300 5878 #define IOC_IOCFG15_IOSTR_MED 0x00000200 5879 #define IOC_IOCFG15_IOSTR_MIN 0x00000100 5880 #define IOC_IOCFG15_IOSTR_AUTO 0x00000000 5881 5882 // Field: [7] IOEV_RTC_EN 5883 // 5884 // Event asserted by this IO when edge detection is enabled 5885 // 5886 // 0: Input edge detection does not assert RTC event 5887 // 1: Input edge detection asserts RTC event 5888 #define IOC_IOCFG15_IOEV_RTC_EN 0x00000080 5889 #define IOC_IOCFG15_IOEV_RTC_EN_BITN 7 5890 #define IOC_IOCFG15_IOEV_RTC_EN_M 0x00000080 5891 #define IOC_IOCFG15_IOEV_RTC_EN_S 7 5892 5893 // Field: [6] IOEV_MCU_WU_EN 5894 // 5895 // Event asserted by this IO when edge detection is enabled 5896 // 5897 // 0: Input edge detection does not assert MCU_WU event 5898 // 1: Input edge detection asserts MCU_WU event 5899 #define IOC_IOCFG15_IOEV_MCU_WU_EN 0x00000040 5900 #define IOC_IOCFG15_IOEV_MCU_WU_EN_BITN 6 5901 #define IOC_IOCFG15_IOEV_MCU_WU_EN_M 0x00000040 5902 #define IOC_IOCFG15_IOEV_MCU_WU_EN_S 6 5903 5904 // Field: [5:0] PORT_ID 5905 // 5906 // Selects usage for DIO15 5907 // Note: This field should not be written other than the times when PORT_ID 5908 // value is specifically required to change. 5909 // ENUMs: 5910 // RFC_SMI_CL_IN RF Core SMI Command Link In 5911 // RFC_SMI_CL_OUT RF Core SMI Command Link Out 5912 // RFC_SMI_DL_IN RF Core SMI Data Link In 5913 // RFC_SMI_DL_OUT RF Core SMI Data Link Out 5914 // RFC_GPI1 RF Core Data In 1 5915 // RFC_GPI0 RF Core Data In 0 5916 // RFC_GPO3 RF Core Data Out 3 5917 // RFC_GPO2 RF Core Data Out 2 5918 // RFC_GPO1 RF Core Data Out 1 5919 // RFC_GPO0 RF Core Data Out 0 5920 // RFC_TRC RF Core Trace 5921 // I2S_MCLK I2S MCLK 5922 // I2S_BCLK I2S BCLK 5923 // I2S_WCLK I2S WCLK 5924 // I2S_AD1 I2S Data 1 5925 // I2S_AD0 I2S Data 0 5926 // SSI1_CLK SSI1 CLK 5927 // SSI1_FSS SSI1 FSS 5928 // SSI1_TX SSI1 TX 5929 // SSI1_RX SSI1 RX 5930 // CPU_SWV CPU SWV 5931 // PORT_EVENT7 PORT EVENT 7 5932 // Can be used as a general 5933 // purpose IO event by selecting it through 5934 // registers in the EVENT module, for example 5935 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 5936 // and so on 5937 // PORT_EVENT6 PORT EVENT 6 5938 // Can be used as a general 5939 // purpose IO event by selecting it through 5940 // registers in the EVENT module, for example 5941 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 5942 // and so on 5943 // PORT_EVENT5 PORT EVENT 5 5944 // Can be used as a general 5945 // purpose IO event by selecting it through 5946 // registers in the EVENT module, for example 5947 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 5948 // and so on 5949 // PORT_EVENT4 PORT EVENT 4 5950 // Can be used as a general 5951 // purpose IO event by selecting it through 5952 // registers in the EVENT module, for example 5953 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 5954 // and so on 5955 // PORT_EVENT3 PORT EVENT 3 5956 // Can be used as a general 5957 // purpose IO event by selecting it through 5958 // registers in the EVENT module, for example 5959 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 5960 // and so on 5961 // PORT_EVENT2 PORT EVENT 2 5962 // Can be used as a general 5963 // purpose IO event by selecting it through 5964 // registers in the EVENT module, for example 5965 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 5966 // and so on 5967 // PORT_EVENT1 PORT EVENT 1 5968 // Can be used as a general 5969 // purpose IO event by selecting it through 5970 // registers in the EVENT module, for example 5971 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 5972 // and so on 5973 // PORT_EVENT0 PORT EVENT 0 5974 // Can be used as a general 5975 // purpose IO event by selecting it through 5976 // registers in the EVENT module, for example 5977 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 5978 // and so on 5979 // UART1_RTS UART1 RTS 5980 // UART1_CTS UART1 CTS 5981 // UART1_TX UART1 TX 5982 // UART1_RX UART1 RX 5983 // UART0_RTS UART0 RTS 5984 // UART0_CTS UART0 CTS 5985 // UART0_TX UART0 TX 5986 // UART0_RX UART0 RX 5987 // I2C_MSSCL I2C Clock 5988 // I2C_MSSDA I2C Data 5989 // SSI0_CLK SSI0 CLK 5990 // SSI0_FSS SSI0 FSS 5991 // SSI0_TX SSI0 TX 5992 // SSI0_RX SSI0 RX 5993 // AUX_IO AUX IO 5994 // AON_CLK32K AON 32 KHz clock (SCLK_LF) 5995 // GPIO General Purpose IO 5996 #define IOC_IOCFG15_PORT_ID_W 6 5997 #define IOC_IOCFG15_PORT_ID_M 0x0000003F 5998 #define IOC_IOCFG15_PORT_ID_S 0 5999 #define IOC_IOCFG15_PORT_ID_RFC_SMI_CL_IN 0x00000038 6000 #define IOC_IOCFG15_PORT_ID_RFC_SMI_CL_OUT 0x00000037 6001 #define IOC_IOCFG15_PORT_ID_RFC_SMI_DL_IN 0x00000036 6002 #define IOC_IOCFG15_PORT_ID_RFC_SMI_DL_OUT 0x00000035 6003 #define IOC_IOCFG15_PORT_ID_RFC_GPI1 0x00000034 6004 #define IOC_IOCFG15_PORT_ID_RFC_GPI0 0x00000033 6005 #define IOC_IOCFG15_PORT_ID_RFC_GPO3 0x00000032 6006 #define IOC_IOCFG15_PORT_ID_RFC_GPO2 0x00000031 6007 #define IOC_IOCFG15_PORT_ID_RFC_GPO1 0x00000030 6008 #define IOC_IOCFG15_PORT_ID_RFC_GPO0 0x0000002F 6009 #define IOC_IOCFG15_PORT_ID_RFC_TRC 0x0000002E 6010 #define IOC_IOCFG15_PORT_ID_I2S_MCLK 0x00000029 6011 #define IOC_IOCFG15_PORT_ID_I2S_BCLK 0x00000028 6012 #define IOC_IOCFG15_PORT_ID_I2S_WCLK 0x00000027 6013 #define IOC_IOCFG15_PORT_ID_I2S_AD1 0x00000026 6014 #define IOC_IOCFG15_PORT_ID_I2S_AD0 0x00000025 6015 #define IOC_IOCFG15_PORT_ID_SSI1_CLK 0x00000024 6016 #define IOC_IOCFG15_PORT_ID_SSI1_FSS 0x00000023 6017 #define IOC_IOCFG15_PORT_ID_SSI1_TX 0x00000022 6018 #define IOC_IOCFG15_PORT_ID_SSI1_RX 0x00000021 6019 #define IOC_IOCFG15_PORT_ID_CPU_SWV 0x00000020 6020 #define IOC_IOCFG15_PORT_ID_PORT_EVENT7 0x0000001E 6021 #define IOC_IOCFG15_PORT_ID_PORT_EVENT6 0x0000001D 6022 #define IOC_IOCFG15_PORT_ID_PORT_EVENT5 0x0000001C 6023 #define IOC_IOCFG15_PORT_ID_PORT_EVENT4 0x0000001B 6024 #define IOC_IOCFG15_PORT_ID_PORT_EVENT3 0x0000001A 6025 #define IOC_IOCFG15_PORT_ID_PORT_EVENT2 0x00000019 6026 #define IOC_IOCFG15_PORT_ID_PORT_EVENT1 0x00000018 6027 #define IOC_IOCFG15_PORT_ID_PORT_EVENT0 0x00000017 6028 #define IOC_IOCFG15_PORT_ID_UART1_RTS 0x00000016 6029 #define IOC_IOCFG15_PORT_ID_UART1_CTS 0x00000015 6030 #define IOC_IOCFG15_PORT_ID_UART1_TX 0x00000014 6031 #define IOC_IOCFG15_PORT_ID_UART1_RX 0x00000013 6032 #define IOC_IOCFG15_PORT_ID_UART0_RTS 0x00000012 6033 #define IOC_IOCFG15_PORT_ID_UART0_CTS 0x00000011 6034 #define IOC_IOCFG15_PORT_ID_UART0_TX 0x00000010 6035 #define IOC_IOCFG15_PORT_ID_UART0_RX 0x0000000F 6036 #define IOC_IOCFG15_PORT_ID_I2C_MSSCL 0x0000000E 6037 #define IOC_IOCFG15_PORT_ID_I2C_MSSDA 0x0000000D 6038 #define IOC_IOCFG15_PORT_ID_SSI0_CLK 0x0000000C 6039 #define IOC_IOCFG15_PORT_ID_SSI0_FSS 0x0000000B 6040 #define IOC_IOCFG15_PORT_ID_SSI0_TX 0x0000000A 6041 #define IOC_IOCFG15_PORT_ID_SSI0_RX 0x00000009 6042 #define IOC_IOCFG15_PORT_ID_AUX_IO 0x00000008 6043 #define IOC_IOCFG15_PORT_ID_AON_CLK32K 0x00000007 6044 #define IOC_IOCFG15_PORT_ID_GPIO 0x00000000 6045 6046 //***************************************************************************** 6047 // 6048 // Register: IOC_O_IOCFG16 6049 // 6050 //***************************************************************************** 6051 // Field: [30] HYST_EN 6052 // 6053 // 0: Input hysteresis disable 6054 // 1: Input hysteresis enable 6055 #define IOC_IOCFG16_HYST_EN 0x40000000 6056 #define IOC_IOCFG16_HYST_EN_BITN 30 6057 #define IOC_IOCFG16_HYST_EN_M 0x40000000 6058 #define IOC_IOCFG16_HYST_EN_S 30 6059 6060 // Field: [29] IE 6061 // 6062 // 0: Input disabled 6063 // 1: Input enabled 6064 // 6065 // Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be 6066 // ignored. 6067 #define IOC_IOCFG16_IE 0x20000000 6068 #define IOC_IOCFG16_IE_BITN 29 6069 #define IOC_IOCFG16_IE_M 0x20000000 6070 #define IOC_IOCFG16_IE_S 29 6071 6072 // Field: [28:27] WU_CFG 6073 // 6074 // If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or 6075 // >0x08: 6076 // 6077 // 00: No wake-up 6078 // 01: No wake-up 6079 // 10: Wakes up from shutdown if this pad is going low. 6080 // 11: Wakes up from shutdown if this pad is going high. 6081 // 6082 // If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, 6083 // this register only sets wakeup enable or not. 6084 // 6085 // 00, 01: Wakeup disabled 6086 // 10, 11: Wakeup enabled 6087 // 6088 // Polarity is controlled from AON registers. 6089 // 6090 // Note:When the MSB is set, the IOC will deactivate the output enable for the 6091 // DIO. 6092 #define IOC_IOCFG16_WU_CFG_W 2 6093 #define IOC_IOCFG16_WU_CFG_M 0x18000000 6094 #define IOC_IOCFG16_WU_CFG_S 27 6095 6096 // Field: [26:24] IOMODE 6097 // 6098 // IO Mode 6099 // Not applicable for IO configured for AON periph. signals and AUX PORT_ID 6100 // 0x01-0x08 6101 // AUX has its own open_source/drain configuration. 6102 // 6103 // 0x2: Reserved. Undefined behavior. 6104 // 0x3: Reserved. Undefined behavior. 6105 // ENUMs: 6106 // OPENSRC_INV Open Source 6107 // Inverted input / output 6108 // OPENSRC Open Source 6109 // Normal input / output 6110 // OPENDR_INV Open Drain 6111 // Inverted input / output 6112 // OPENDR Open Drain, 6113 // Normal input / output 6114 // INV Inverted input / ouput 6115 // NORMAL Normal input / output 6116 #define IOC_IOCFG16_IOMODE_W 3 6117 #define IOC_IOCFG16_IOMODE_M 0x07000000 6118 #define IOC_IOCFG16_IOMODE_S 24 6119 #define IOC_IOCFG16_IOMODE_OPENSRC_INV 0x07000000 6120 #define IOC_IOCFG16_IOMODE_OPENSRC 0x06000000 6121 #define IOC_IOCFG16_IOMODE_OPENDR_INV 0x05000000 6122 #define IOC_IOCFG16_IOMODE_OPENDR 0x04000000 6123 #define IOC_IOCFG16_IOMODE_INV 0x01000000 6124 #define IOC_IOCFG16_IOMODE_NORMAL 0x00000000 6125 6126 // Field: [23] IOEV_AON_PROG2_EN 6127 // 6128 // Event asserted by this IO when edge detection is enabled 6129 // 6130 // 0: Input edge detection does not assert AON_PROG2 event 6131 // 1: Input edge detection asserts AON_PROG2 event 6132 #define IOC_IOCFG16_IOEV_AON_PROG2_EN 0x00800000 6133 #define IOC_IOCFG16_IOEV_AON_PROG2_EN_BITN 23 6134 #define IOC_IOCFG16_IOEV_AON_PROG2_EN_M 0x00800000 6135 #define IOC_IOCFG16_IOEV_AON_PROG2_EN_S 23 6136 6137 // Field: [22] IOEV_AON_PROG1_EN 6138 // 6139 // Event asserted by this IO when edge detection is enabled 6140 // 6141 // 0: Input edge detection does not assert AON_PROG1 event 6142 // 1: Input edge detection asserts AON_PROG1 event 6143 #define IOC_IOCFG16_IOEV_AON_PROG1_EN 0x00400000 6144 #define IOC_IOCFG16_IOEV_AON_PROG1_EN_BITN 22 6145 #define IOC_IOCFG16_IOEV_AON_PROG1_EN_M 0x00400000 6146 #define IOC_IOCFG16_IOEV_AON_PROG1_EN_S 22 6147 6148 // Field: [21] IOEV_AON_PROG0_EN 6149 // 6150 // Event asserted by this IO when edge detection is enabled 6151 // 6152 // 0: Input edge detection does not assert AON_PROG0 event 6153 // 1: Input edge detection asserts AON_PROG0 event 6154 #define IOC_IOCFG16_IOEV_AON_PROG0_EN 0x00200000 6155 #define IOC_IOCFG16_IOEV_AON_PROG0_EN_BITN 21 6156 #define IOC_IOCFG16_IOEV_AON_PROG0_EN_M 0x00200000 6157 #define IOC_IOCFG16_IOEV_AON_PROG0_EN_S 21 6158 6159 // Field: [18] EDGE_IRQ_EN 6160 // 6161 // 0: No interrupt generation 6162 // 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is 6163 // enabled) 6164 #define IOC_IOCFG16_EDGE_IRQ_EN 0x00040000 6165 #define IOC_IOCFG16_EDGE_IRQ_EN_BITN 18 6166 #define IOC_IOCFG16_EDGE_IRQ_EN_M 0x00040000 6167 #define IOC_IOCFG16_EDGE_IRQ_EN_S 18 6168 6169 // Field: [17:16] EDGE_DET 6170 // 6171 // Enable generation of edge detection events on this IO 6172 // ENUMs: 6173 // BOTH Positive and negative edge detection 6174 // POS Positive edge detection 6175 // NEG Negative edge detection 6176 // NONE No edge detection 6177 #define IOC_IOCFG16_EDGE_DET_W 2 6178 #define IOC_IOCFG16_EDGE_DET_M 0x00030000 6179 #define IOC_IOCFG16_EDGE_DET_S 16 6180 #define IOC_IOCFG16_EDGE_DET_BOTH 0x00030000 6181 #define IOC_IOCFG16_EDGE_DET_POS 0x00020000 6182 #define IOC_IOCFG16_EDGE_DET_NEG 0x00010000 6183 #define IOC_IOCFG16_EDGE_DET_NONE 0x00000000 6184 6185 // Field: [14:13] PULL_CTL 6186 // 6187 // Pull control 6188 // ENUMs: 6189 // DIS No pull 6190 // UP Pull up 6191 // DWN Pull down 6192 #define IOC_IOCFG16_PULL_CTL_W 2 6193 #define IOC_IOCFG16_PULL_CTL_M 0x00006000 6194 #define IOC_IOCFG16_PULL_CTL_S 13 6195 #define IOC_IOCFG16_PULL_CTL_DIS 0x00006000 6196 #define IOC_IOCFG16_PULL_CTL_UP 0x00004000 6197 #define IOC_IOCFG16_PULL_CTL_DWN 0x00002000 6198 6199 // Field: [12] SLEW_RED 6200 // 6201 // 0: Normal slew rate 6202 // 1: Enables reduced slew rate in output driver. 6203 #define IOC_IOCFG16_SLEW_RED 0x00001000 6204 #define IOC_IOCFG16_SLEW_RED_BITN 12 6205 #define IOC_IOCFG16_SLEW_RED_M 0x00001000 6206 #define IOC_IOCFG16_SLEW_RED_S 12 6207 6208 // Field: [11:10] IOCURR 6209 // 6210 // Selects IO current mode of this IO. 6211 // ENUMs: 6212 // 4_8MA Extended-Current (EC) mode: Min 8 mA for double 6213 // drive strength IOs (min 4 mA for normal IOs) 6214 // when IOSTR is set to AUTO 6215 // 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set 6216 // to AUTO 6217 // 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set 6218 // to AUTO 6219 #define IOC_IOCFG16_IOCURR_W 2 6220 #define IOC_IOCFG16_IOCURR_M 0x00000C00 6221 #define IOC_IOCFG16_IOCURR_S 10 6222 #define IOC_IOCFG16_IOCURR_4_8MA 0x00000800 6223 #define IOC_IOCFG16_IOCURR_4MA 0x00000400 6224 #define IOC_IOCFG16_IOCURR_2MA 0x00000000 6225 6226 // Field: [9:8] IOSTR 6227 // 6228 // Select source for drive strength control of this IO. 6229 // This setting controls the drive strength of the Low-Current (LC) mode. 6230 // Higher drive strength can be selected in IOCURR 6231 // ENUMs: 6232 // MAX Maximum drive strength, controlled by 6233 // AON_IOC:IOSTRMAX (min 2 mA @1.8V with default 6234 // values) 6235 // MED Medium drive strength, controlled by 6236 // AON_IOC:IOSTRMED (min 2 mA @2.5V with default 6237 // values) 6238 // MIN Minimum drive strength, controlled by 6239 // AON_IOC:IOSTRMIN (min 2 mA @3.3V with default 6240 // values) 6241 // AUTO Automatic drive strength, controlled by AON BATMON 6242 // based on battery voltage. (min 2 mA @VDDS) 6243 #define IOC_IOCFG16_IOSTR_W 2 6244 #define IOC_IOCFG16_IOSTR_M 0x00000300 6245 #define IOC_IOCFG16_IOSTR_S 8 6246 #define IOC_IOCFG16_IOSTR_MAX 0x00000300 6247 #define IOC_IOCFG16_IOSTR_MED 0x00000200 6248 #define IOC_IOCFG16_IOSTR_MIN 0x00000100 6249 #define IOC_IOCFG16_IOSTR_AUTO 0x00000000 6250 6251 // Field: [7] IOEV_RTC_EN 6252 // 6253 // Event asserted by this IO when edge detection is enabled 6254 // 6255 // 0: Input edge detection does not assert RTC event 6256 // 1: Input edge detection asserts RTC event 6257 #define IOC_IOCFG16_IOEV_RTC_EN 0x00000080 6258 #define IOC_IOCFG16_IOEV_RTC_EN_BITN 7 6259 #define IOC_IOCFG16_IOEV_RTC_EN_M 0x00000080 6260 #define IOC_IOCFG16_IOEV_RTC_EN_S 7 6261 6262 // Field: [6] IOEV_MCU_WU_EN 6263 // 6264 // Event asserted by this IO when edge detection is enabled 6265 // 6266 // 0: Input edge detection does not assert MCU_WU event 6267 // 1: Input edge detection asserts MCU_WU event 6268 #define IOC_IOCFG16_IOEV_MCU_WU_EN 0x00000040 6269 #define IOC_IOCFG16_IOEV_MCU_WU_EN_BITN 6 6270 #define IOC_IOCFG16_IOEV_MCU_WU_EN_M 0x00000040 6271 #define IOC_IOCFG16_IOEV_MCU_WU_EN_S 6 6272 6273 // Field: [5:0] PORT_ID 6274 // 6275 // Selects usage for DIO16 6276 // Note: This field should not be written other than the times when PORT_ID 6277 // value is specifically required to change. 6278 // ENUMs: 6279 // RFC_SMI_CL_IN RF Core SMI Command Link In 6280 // RFC_SMI_CL_OUT RF Core SMI Command Link Out 6281 // RFC_SMI_DL_IN RF Core SMI Data Link In 6282 // RFC_SMI_DL_OUT RF Core SMI Data Link Out 6283 // RFC_GPI1 RF Core Data In 1 6284 // RFC_GPI0 RF Core Data In 0 6285 // RFC_GPO3 RF Core Data Out 3 6286 // RFC_GPO2 RF Core Data Out 2 6287 // RFC_GPO1 RF Core Data Out 1 6288 // RFC_GPO0 RF Core Data Out 0 6289 // RFC_TRC RF Core Trace 6290 // I2S_MCLK I2S MCLK 6291 // I2S_BCLK I2S BCLK 6292 // I2S_WCLK I2S WCLK 6293 // I2S_AD1 I2S Data 1 6294 // I2S_AD0 I2S Data 0 6295 // SSI1_CLK SSI1 CLK 6296 // SSI1_FSS SSI1 FSS 6297 // SSI1_TX SSI1 TX 6298 // SSI1_RX SSI1 RX 6299 // CPU_SWV CPU SWV 6300 // PORT_EVENT7 PORT EVENT 7 6301 // Can be used as a general 6302 // purpose IO event by selecting it through 6303 // registers in the EVENT module, for example 6304 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 6305 // and so on 6306 // PORT_EVENT6 PORT EVENT 6 6307 // Can be used as a general 6308 // purpose IO event by selecting it through 6309 // registers in the EVENT module, for example 6310 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 6311 // and so on 6312 // PORT_EVENT5 PORT EVENT 5 6313 // Can be used as a general 6314 // purpose IO event by selecting it through 6315 // registers in the EVENT module, for example 6316 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 6317 // and so on 6318 // PORT_EVENT4 PORT EVENT 4 6319 // Can be used as a general 6320 // purpose IO event by selecting it through 6321 // registers in the EVENT module, for example 6322 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 6323 // and so on 6324 // PORT_EVENT3 PORT EVENT 3 6325 // Can be used as a general 6326 // purpose IO event by selecting it through 6327 // registers in the EVENT module, for example 6328 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 6329 // and so on 6330 // PORT_EVENT2 PORT EVENT 2 6331 // Can be used as a general 6332 // purpose IO event by selecting it through 6333 // registers in the EVENT module, for example 6334 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 6335 // and so on 6336 // PORT_EVENT1 PORT EVENT 1 6337 // Can be used as a general 6338 // purpose IO event by selecting it through 6339 // registers in the EVENT module, for example 6340 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 6341 // and so on 6342 // PORT_EVENT0 PORT EVENT 0 6343 // Can be used as a general 6344 // purpose IO event by selecting it through 6345 // registers in the EVENT module, for example 6346 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 6347 // and so on 6348 // UART1_RTS UART1 RTS 6349 // UART1_CTS UART1 CTS 6350 // UART1_TX UART1 TX 6351 // UART1_RX UART1 RX 6352 // UART0_RTS UART0 RTS 6353 // UART0_CTS UART0 CTS 6354 // UART0_TX UART0 TX 6355 // UART0_RX UART0 RX 6356 // I2C_MSSCL I2C Clock 6357 // I2C_MSSDA I2C Data 6358 // SSI0_CLK SSI0 CLK 6359 // SSI0_FSS SSI0 FSS 6360 // SSI0_TX SSI0 TX 6361 // SSI0_RX SSI0 RX 6362 // AUX_IO AUX IO 6363 // AON_CLK32K AON 32 KHz clock (SCLK_LF) 6364 // GPIO General Purpose IO 6365 #define IOC_IOCFG16_PORT_ID_W 6 6366 #define IOC_IOCFG16_PORT_ID_M 0x0000003F 6367 #define IOC_IOCFG16_PORT_ID_S 0 6368 #define IOC_IOCFG16_PORT_ID_RFC_SMI_CL_IN 0x00000038 6369 #define IOC_IOCFG16_PORT_ID_RFC_SMI_CL_OUT 0x00000037 6370 #define IOC_IOCFG16_PORT_ID_RFC_SMI_DL_IN 0x00000036 6371 #define IOC_IOCFG16_PORT_ID_RFC_SMI_DL_OUT 0x00000035 6372 #define IOC_IOCFG16_PORT_ID_RFC_GPI1 0x00000034 6373 #define IOC_IOCFG16_PORT_ID_RFC_GPI0 0x00000033 6374 #define IOC_IOCFG16_PORT_ID_RFC_GPO3 0x00000032 6375 #define IOC_IOCFG16_PORT_ID_RFC_GPO2 0x00000031 6376 #define IOC_IOCFG16_PORT_ID_RFC_GPO1 0x00000030 6377 #define IOC_IOCFG16_PORT_ID_RFC_GPO0 0x0000002F 6378 #define IOC_IOCFG16_PORT_ID_RFC_TRC 0x0000002E 6379 #define IOC_IOCFG16_PORT_ID_I2S_MCLK 0x00000029 6380 #define IOC_IOCFG16_PORT_ID_I2S_BCLK 0x00000028 6381 #define IOC_IOCFG16_PORT_ID_I2S_WCLK 0x00000027 6382 #define IOC_IOCFG16_PORT_ID_I2S_AD1 0x00000026 6383 #define IOC_IOCFG16_PORT_ID_I2S_AD0 0x00000025 6384 #define IOC_IOCFG16_PORT_ID_SSI1_CLK 0x00000024 6385 #define IOC_IOCFG16_PORT_ID_SSI1_FSS 0x00000023 6386 #define IOC_IOCFG16_PORT_ID_SSI1_TX 0x00000022 6387 #define IOC_IOCFG16_PORT_ID_SSI1_RX 0x00000021 6388 #define IOC_IOCFG16_PORT_ID_CPU_SWV 0x00000020 6389 #define IOC_IOCFG16_PORT_ID_PORT_EVENT7 0x0000001E 6390 #define IOC_IOCFG16_PORT_ID_PORT_EVENT6 0x0000001D 6391 #define IOC_IOCFG16_PORT_ID_PORT_EVENT5 0x0000001C 6392 #define IOC_IOCFG16_PORT_ID_PORT_EVENT4 0x0000001B 6393 #define IOC_IOCFG16_PORT_ID_PORT_EVENT3 0x0000001A 6394 #define IOC_IOCFG16_PORT_ID_PORT_EVENT2 0x00000019 6395 #define IOC_IOCFG16_PORT_ID_PORT_EVENT1 0x00000018 6396 #define IOC_IOCFG16_PORT_ID_PORT_EVENT0 0x00000017 6397 #define IOC_IOCFG16_PORT_ID_UART1_RTS 0x00000016 6398 #define IOC_IOCFG16_PORT_ID_UART1_CTS 0x00000015 6399 #define IOC_IOCFG16_PORT_ID_UART1_TX 0x00000014 6400 #define IOC_IOCFG16_PORT_ID_UART1_RX 0x00000013 6401 #define IOC_IOCFG16_PORT_ID_UART0_RTS 0x00000012 6402 #define IOC_IOCFG16_PORT_ID_UART0_CTS 0x00000011 6403 #define IOC_IOCFG16_PORT_ID_UART0_TX 0x00000010 6404 #define IOC_IOCFG16_PORT_ID_UART0_RX 0x0000000F 6405 #define IOC_IOCFG16_PORT_ID_I2C_MSSCL 0x0000000E 6406 #define IOC_IOCFG16_PORT_ID_I2C_MSSDA 0x0000000D 6407 #define IOC_IOCFG16_PORT_ID_SSI0_CLK 0x0000000C 6408 #define IOC_IOCFG16_PORT_ID_SSI0_FSS 0x0000000B 6409 #define IOC_IOCFG16_PORT_ID_SSI0_TX 0x0000000A 6410 #define IOC_IOCFG16_PORT_ID_SSI0_RX 0x00000009 6411 #define IOC_IOCFG16_PORT_ID_AUX_IO 0x00000008 6412 #define IOC_IOCFG16_PORT_ID_AON_CLK32K 0x00000007 6413 #define IOC_IOCFG16_PORT_ID_GPIO 0x00000000 6414 6415 //***************************************************************************** 6416 // 6417 // Register: IOC_O_IOCFG17 6418 // 6419 //***************************************************************************** 6420 // Field: [30] HYST_EN 6421 // 6422 // 0: Input hysteresis disable 6423 // 1: Input hysteresis enable 6424 #define IOC_IOCFG17_HYST_EN 0x40000000 6425 #define IOC_IOCFG17_HYST_EN_BITN 30 6426 #define IOC_IOCFG17_HYST_EN_M 0x40000000 6427 #define IOC_IOCFG17_HYST_EN_S 30 6428 6429 // Field: [29] IE 6430 // 6431 // 0: Input disabled 6432 // 1: Input enabled 6433 // 6434 // Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be 6435 // ignored. 6436 #define IOC_IOCFG17_IE 0x20000000 6437 #define IOC_IOCFG17_IE_BITN 29 6438 #define IOC_IOCFG17_IE_M 0x20000000 6439 #define IOC_IOCFG17_IE_S 29 6440 6441 // Field: [28:27] WU_CFG 6442 // 6443 // If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or 6444 // >0x08: 6445 // 6446 // 00: No wake-up 6447 // 01: No wake-up 6448 // 10: Wakes up from shutdown if this pad is going low. 6449 // 11: Wakes up from shutdown if this pad is going high. 6450 // 6451 // If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, 6452 // this register only sets wakeup enable or not. 6453 // 6454 // 00, 01: Wakeup disabled 6455 // 10, 11: Wakeup enabled 6456 // 6457 // Polarity is controlled from AON registers. 6458 // 6459 // Note:When the MSB is set, the IOC will deactivate the output enable for the 6460 // DIO. 6461 #define IOC_IOCFG17_WU_CFG_W 2 6462 #define IOC_IOCFG17_WU_CFG_M 0x18000000 6463 #define IOC_IOCFG17_WU_CFG_S 27 6464 6465 // Field: [26:24] IOMODE 6466 // 6467 // IO Mode 6468 // Not applicable for IO configured for AON periph. signals and AUX PORT_ID 6469 // 0x01-0x08 6470 // AUX has its own open_source/drain configuration. 6471 // 6472 // 0x2: Reserved. Undefined behavior. 6473 // 0x3: Reserved. Undefined behavior. 6474 // ENUMs: 6475 // OPENSRC_INV Open Source 6476 // Inverted input / output 6477 // OPENSRC Open Source 6478 // Normal input / output 6479 // OPENDR_INV Open Drain 6480 // Inverted input / output 6481 // OPENDR Open Drain, 6482 // Normal input / output 6483 // INV Inverted input / ouput 6484 // NORMAL Normal input / output 6485 #define IOC_IOCFG17_IOMODE_W 3 6486 #define IOC_IOCFG17_IOMODE_M 0x07000000 6487 #define IOC_IOCFG17_IOMODE_S 24 6488 #define IOC_IOCFG17_IOMODE_OPENSRC_INV 0x07000000 6489 #define IOC_IOCFG17_IOMODE_OPENSRC 0x06000000 6490 #define IOC_IOCFG17_IOMODE_OPENDR_INV 0x05000000 6491 #define IOC_IOCFG17_IOMODE_OPENDR 0x04000000 6492 #define IOC_IOCFG17_IOMODE_INV 0x01000000 6493 #define IOC_IOCFG17_IOMODE_NORMAL 0x00000000 6494 6495 // Field: [23] IOEV_AON_PROG2_EN 6496 // 6497 // Event asserted by this IO when edge detection is enabled 6498 // 6499 // 0: Input edge detection does not assert AON_PROG2 event 6500 // 1: Input edge detection asserts AON_PROG2 event 6501 #define IOC_IOCFG17_IOEV_AON_PROG2_EN 0x00800000 6502 #define IOC_IOCFG17_IOEV_AON_PROG2_EN_BITN 23 6503 #define IOC_IOCFG17_IOEV_AON_PROG2_EN_M 0x00800000 6504 #define IOC_IOCFG17_IOEV_AON_PROG2_EN_S 23 6505 6506 // Field: [22] IOEV_AON_PROG1_EN 6507 // 6508 // Event asserted by this IO when edge detection is enabled 6509 // 6510 // 0: Input edge detection does not assert AON_PROG1 event 6511 // 1: Input edge detection asserts AON_PROG1 event 6512 #define IOC_IOCFG17_IOEV_AON_PROG1_EN 0x00400000 6513 #define IOC_IOCFG17_IOEV_AON_PROG1_EN_BITN 22 6514 #define IOC_IOCFG17_IOEV_AON_PROG1_EN_M 0x00400000 6515 #define IOC_IOCFG17_IOEV_AON_PROG1_EN_S 22 6516 6517 // Field: [21] IOEV_AON_PROG0_EN 6518 // 6519 // Event asserted by this IO when edge detection is enabled 6520 // 6521 // 0: Input edge detection does not assert AON_PROG0 event 6522 // 1: Input edge detection asserts AON_PROG0 event 6523 #define IOC_IOCFG17_IOEV_AON_PROG0_EN 0x00200000 6524 #define IOC_IOCFG17_IOEV_AON_PROG0_EN_BITN 21 6525 #define IOC_IOCFG17_IOEV_AON_PROG0_EN_M 0x00200000 6526 #define IOC_IOCFG17_IOEV_AON_PROG0_EN_S 21 6527 6528 // Field: [18] EDGE_IRQ_EN 6529 // 6530 // 0: No interrupt generation 6531 // 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is 6532 // enabled) 6533 #define IOC_IOCFG17_EDGE_IRQ_EN 0x00040000 6534 #define IOC_IOCFG17_EDGE_IRQ_EN_BITN 18 6535 #define IOC_IOCFG17_EDGE_IRQ_EN_M 0x00040000 6536 #define IOC_IOCFG17_EDGE_IRQ_EN_S 18 6537 6538 // Field: [17:16] EDGE_DET 6539 // 6540 // Enable generation of edge detection events on this IO 6541 // ENUMs: 6542 // BOTH Positive and negative edge detection 6543 // POS Positive edge detection 6544 // NEG Negative edge detection 6545 // NONE No edge detection 6546 #define IOC_IOCFG17_EDGE_DET_W 2 6547 #define IOC_IOCFG17_EDGE_DET_M 0x00030000 6548 #define IOC_IOCFG17_EDGE_DET_S 16 6549 #define IOC_IOCFG17_EDGE_DET_BOTH 0x00030000 6550 #define IOC_IOCFG17_EDGE_DET_POS 0x00020000 6551 #define IOC_IOCFG17_EDGE_DET_NEG 0x00010000 6552 #define IOC_IOCFG17_EDGE_DET_NONE 0x00000000 6553 6554 // Field: [14:13] PULL_CTL 6555 // 6556 // Pull control 6557 // ENUMs: 6558 // DIS No pull 6559 // UP Pull up 6560 // DWN Pull down 6561 #define IOC_IOCFG17_PULL_CTL_W 2 6562 #define IOC_IOCFG17_PULL_CTL_M 0x00006000 6563 #define IOC_IOCFG17_PULL_CTL_S 13 6564 #define IOC_IOCFG17_PULL_CTL_DIS 0x00006000 6565 #define IOC_IOCFG17_PULL_CTL_UP 0x00004000 6566 #define IOC_IOCFG17_PULL_CTL_DWN 0x00002000 6567 6568 // Field: [12] SLEW_RED 6569 // 6570 // 0: Normal slew rate 6571 // 1: Enables reduced slew rate in output driver. 6572 #define IOC_IOCFG17_SLEW_RED 0x00001000 6573 #define IOC_IOCFG17_SLEW_RED_BITN 12 6574 #define IOC_IOCFG17_SLEW_RED_M 0x00001000 6575 #define IOC_IOCFG17_SLEW_RED_S 12 6576 6577 // Field: [11:10] IOCURR 6578 // 6579 // Selects IO current mode of this IO. 6580 // ENUMs: 6581 // 4_8MA Extended-Current (EC) mode: Min 8 mA for double 6582 // drive strength IOs (min 4 mA for normal IOs) 6583 // when IOSTR is set to AUTO 6584 // 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set 6585 // to AUTO 6586 // 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set 6587 // to AUTO 6588 #define IOC_IOCFG17_IOCURR_W 2 6589 #define IOC_IOCFG17_IOCURR_M 0x00000C00 6590 #define IOC_IOCFG17_IOCURR_S 10 6591 #define IOC_IOCFG17_IOCURR_4_8MA 0x00000800 6592 #define IOC_IOCFG17_IOCURR_4MA 0x00000400 6593 #define IOC_IOCFG17_IOCURR_2MA 0x00000000 6594 6595 // Field: [9:8] IOSTR 6596 // 6597 // Select source for drive strength control of this IO. 6598 // This setting controls the drive strength of the Low-Current (LC) mode. 6599 // Higher drive strength can be selected in IOCURR 6600 // ENUMs: 6601 // MAX Maximum drive strength, controlled by 6602 // AON_IOC:IOSTRMAX (min 2 mA @1.8V with default 6603 // values) 6604 // MED Medium drive strength, controlled by 6605 // AON_IOC:IOSTRMED (min 2 mA @2.5V with default 6606 // values) 6607 // MIN Minimum drive strength, controlled by 6608 // AON_IOC:IOSTRMIN (min 2 mA @3.3V with default 6609 // values) 6610 // AUTO Automatic drive strength, controlled by AON BATMON 6611 // based on battery voltage. (min 2 mA @VDDS) 6612 #define IOC_IOCFG17_IOSTR_W 2 6613 #define IOC_IOCFG17_IOSTR_M 0x00000300 6614 #define IOC_IOCFG17_IOSTR_S 8 6615 #define IOC_IOCFG17_IOSTR_MAX 0x00000300 6616 #define IOC_IOCFG17_IOSTR_MED 0x00000200 6617 #define IOC_IOCFG17_IOSTR_MIN 0x00000100 6618 #define IOC_IOCFG17_IOSTR_AUTO 0x00000000 6619 6620 // Field: [7] IOEV_RTC_EN 6621 // 6622 // Event asserted by this IO when edge detection is enabled 6623 // 6624 // 0: Input edge detection does not assert RTC event 6625 // 1: Input edge detection asserts RTC event 6626 #define IOC_IOCFG17_IOEV_RTC_EN 0x00000080 6627 #define IOC_IOCFG17_IOEV_RTC_EN_BITN 7 6628 #define IOC_IOCFG17_IOEV_RTC_EN_M 0x00000080 6629 #define IOC_IOCFG17_IOEV_RTC_EN_S 7 6630 6631 // Field: [6] IOEV_MCU_WU_EN 6632 // 6633 // Event asserted by this IO when edge detection is enabled 6634 // 6635 // 0: Input edge detection does not assert MCU_WU event 6636 // 1: Input edge detection asserts MCU_WU event 6637 #define IOC_IOCFG17_IOEV_MCU_WU_EN 0x00000040 6638 #define IOC_IOCFG17_IOEV_MCU_WU_EN_BITN 6 6639 #define IOC_IOCFG17_IOEV_MCU_WU_EN_M 0x00000040 6640 #define IOC_IOCFG17_IOEV_MCU_WU_EN_S 6 6641 6642 // Field: [5:0] PORT_ID 6643 // 6644 // Selects usage for DIO17 6645 // Note: This field should not be written other than the times when PORT_ID 6646 // value is specifically required to change. 6647 // ENUMs: 6648 // RFC_SMI_CL_IN RF Core SMI Command Link In 6649 // RFC_SMI_CL_OUT RF Core SMI Command Link Out 6650 // RFC_SMI_DL_IN RF Core SMI Data Link In 6651 // RFC_SMI_DL_OUT RF Core SMI Data Link Out 6652 // RFC_GPI1 RF Core Data In 1 6653 // RFC_GPI0 RF Core Data In 0 6654 // RFC_GPO3 RF Core Data Out 3 6655 // RFC_GPO2 RF Core Data Out 2 6656 // RFC_GPO1 RF Core Data Out 1 6657 // RFC_GPO0 RF Core Data Out 0 6658 // RFC_TRC RF Core Trace 6659 // I2S_MCLK I2S MCLK 6660 // I2S_BCLK I2S BCLK 6661 // I2S_WCLK I2S WCLK 6662 // I2S_AD1 I2S Data 1 6663 // I2S_AD0 I2S Data 0 6664 // SSI1_CLK SSI1 CLK 6665 // SSI1_FSS SSI1 FSS 6666 // SSI1_TX SSI1 TX 6667 // SSI1_RX SSI1 RX 6668 // CPU_SWV CPU SWV 6669 // PORT_EVENT7 PORT EVENT 7 6670 // Can be used as a general 6671 // purpose IO event by selecting it through 6672 // registers in the EVENT module, for example 6673 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 6674 // and so on 6675 // PORT_EVENT6 PORT EVENT 6 6676 // Can be used as a general 6677 // purpose IO event by selecting it through 6678 // registers in the EVENT module, for example 6679 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 6680 // and so on 6681 // PORT_EVENT5 PORT EVENT 5 6682 // Can be used as a general 6683 // purpose IO event by selecting it through 6684 // registers in the EVENT module, for example 6685 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 6686 // and so on 6687 // PORT_EVENT4 PORT EVENT 4 6688 // Can be used as a general 6689 // purpose IO event by selecting it through 6690 // registers in the EVENT module, for example 6691 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 6692 // and so on 6693 // PORT_EVENT3 PORT EVENT 3 6694 // Can be used as a general 6695 // purpose IO event by selecting it through 6696 // registers in the EVENT module, for example 6697 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 6698 // and so on 6699 // PORT_EVENT2 PORT EVENT 2 6700 // Can be used as a general 6701 // purpose IO event by selecting it through 6702 // registers in the EVENT module, for example 6703 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 6704 // and so on 6705 // PORT_EVENT1 PORT EVENT 1 6706 // Can be used as a general 6707 // purpose IO event by selecting it through 6708 // registers in the EVENT module, for example 6709 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 6710 // and so on 6711 // PORT_EVENT0 PORT EVENT 0 6712 // Can be used as a general 6713 // purpose IO event by selecting it through 6714 // registers in the EVENT module, for example 6715 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 6716 // and so on 6717 // UART1_RTS UART1 RTS 6718 // UART1_CTS UART1 CTS 6719 // UART1_TX UART1 TX 6720 // UART1_RX UART1 RX 6721 // UART0_RTS UART0 RTS 6722 // UART0_CTS UART0 CTS 6723 // UART0_TX UART0 TX 6724 // UART0_RX UART0 RX 6725 // I2C_MSSCL I2C Clock 6726 // I2C_MSSDA I2C Data 6727 // SSI0_CLK SSI0 CLK 6728 // SSI0_FSS SSI0 FSS 6729 // SSI0_TX SSI0 TX 6730 // SSI0_RX SSI0 RX 6731 // AUX_IO AUX IO 6732 // AON_CLK32K AON 32 KHz clock (SCLK_LF) 6733 // GPIO General Purpose IO 6734 #define IOC_IOCFG17_PORT_ID_W 6 6735 #define IOC_IOCFG17_PORT_ID_M 0x0000003F 6736 #define IOC_IOCFG17_PORT_ID_S 0 6737 #define IOC_IOCFG17_PORT_ID_RFC_SMI_CL_IN 0x00000038 6738 #define IOC_IOCFG17_PORT_ID_RFC_SMI_CL_OUT 0x00000037 6739 #define IOC_IOCFG17_PORT_ID_RFC_SMI_DL_IN 0x00000036 6740 #define IOC_IOCFG17_PORT_ID_RFC_SMI_DL_OUT 0x00000035 6741 #define IOC_IOCFG17_PORT_ID_RFC_GPI1 0x00000034 6742 #define IOC_IOCFG17_PORT_ID_RFC_GPI0 0x00000033 6743 #define IOC_IOCFG17_PORT_ID_RFC_GPO3 0x00000032 6744 #define IOC_IOCFG17_PORT_ID_RFC_GPO2 0x00000031 6745 #define IOC_IOCFG17_PORT_ID_RFC_GPO1 0x00000030 6746 #define IOC_IOCFG17_PORT_ID_RFC_GPO0 0x0000002F 6747 #define IOC_IOCFG17_PORT_ID_RFC_TRC 0x0000002E 6748 #define IOC_IOCFG17_PORT_ID_I2S_MCLK 0x00000029 6749 #define IOC_IOCFG17_PORT_ID_I2S_BCLK 0x00000028 6750 #define IOC_IOCFG17_PORT_ID_I2S_WCLK 0x00000027 6751 #define IOC_IOCFG17_PORT_ID_I2S_AD1 0x00000026 6752 #define IOC_IOCFG17_PORT_ID_I2S_AD0 0x00000025 6753 #define IOC_IOCFG17_PORT_ID_SSI1_CLK 0x00000024 6754 #define IOC_IOCFG17_PORT_ID_SSI1_FSS 0x00000023 6755 #define IOC_IOCFG17_PORT_ID_SSI1_TX 0x00000022 6756 #define IOC_IOCFG17_PORT_ID_SSI1_RX 0x00000021 6757 #define IOC_IOCFG17_PORT_ID_CPU_SWV 0x00000020 6758 #define IOC_IOCFG17_PORT_ID_PORT_EVENT7 0x0000001E 6759 #define IOC_IOCFG17_PORT_ID_PORT_EVENT6 0x0000001D 6760 #define IOC_IOCFG17_PORT_ID_PORT_EVENT5 0x0000001C 6761 #define IOC_IOCFG17_PORT_ID_PORT_EVENT4 0x0000001B 6762 #define IOC_IOCFG17_PORT_ID_PORT_EVENT3 0x0000001A 6763 #define IOC_IOCFG17_PORT_ID_PORT_EVENT2 0x00000019 6764 #define IOC_IOCFG17_PORT_ID_PORT_EVENT1 0x00000018 6765 #define IOC_IOCFG17_PORT_ID_PORT_EVENT0 0x00000017 6766 #define IOC_IOCFG17_PORT_ID_UART1_RTS 0x00000016 6767 #define IOC_IOCFG17_PORT_ID_UART1_CTS 0x00000015 6768 #define IOC_IOCFG17_PORT_ID_UART1_TX 0x00000014 6769 #define IOC_IOCFG17_PORT_ID_UART1_RX 0x00000013 6770 #define IOC_IOCFG17_PORT_ID_UART0_RTS 0x00000012 6771 #define IOC_IOCFG17_PORT_ID_UART0_CTS 0x00000011 6772 #define IOC_IOCFG17_PORT_ID_UART0_TX 0x00000010 6773 #define IOC_IOCFG17_PORT_ID_UART0_RX 0x0000000F 6774 #define IOC_IOCFG17_PORT_ID_I2C_MSSCL 0x0000000E 6775 #define IOC_IOCFG17_PORT_ID_I2C_MSSDA 0x0000000D 6776 #define IOC_IOCFG17_PORT_ID_SSI0_CLK 0x0000000C 6777 #define IOC_IOCFG17_PORT_ID_SSI0_FSS 0x0000000B 6778 #define IOC_IOCFG17_PORT_ID_SSI0_TX 0x0000000A 6779 #define IOC_IOCFG17_PORT_ID_SSI0_RX 0x00000009 6780 #define IOC_IOCFG17_PORT_ID_AUX_IO 0x00000008 6781 #define IOC_IOCFG17_PORT_ID_AON_CLK32K 0x00000007 6782 #define IOC_IOCFG17_PORT_ID_GPIO 0x00000000 6783 6784 //***************************************************************************** 6785 // 6786 // Register: IOC_O_IOCFG18 6787 // 6788 //***************************************************************************** 6789 // Field: [30] HYST_EN 6790 // 6791 // 0: Input hysteresis disable 6792 // 1: Input hysteresis enable 6793 #define IOC_IOCFG18_HYST_EN 0x40000000 6794 #define IOC_IOCFG18_HYST_EN_BITN 30 6795 #define IOC_IOCFG18_HYST_EN_M 0x40000000 6796 #define IOC_IOCFG18_HYST_EN_S 30 6797 6798 // Field: [29] IE 6799 // 6800 // 0: Input disabled 6801 // 1: Input enabled 6802 // 6803 // Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be 6804 // ignored. 6805 #define IOC_IOCFG18_IE 0x20000000 6806 #define IOC_IOCFG18_IE_BITN 29 6807 #define IOC_IOCFG18_IE_M 0x20000000 6808 #define IOC_IOCFG18_IE_S 29 6809 6810 // Field: [28:27] WU_CFG 6811 // 6812 // If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or 6813 // >0x08: 6814 // 6815 // 00: No wake-up 6816 // 01: No wake-up 6817 // 10: Wakes up from shutdown if this pad is going low. 6818 // 11: Wakes up from shutdown if this pad is going high. 6819 // 6820 // If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, 6821 // this register only sets wakeup enable or not. 6822 // 6823 // 00, 01: Wakeup disabled 6824 // 10, 11: Wakeup enabled 6825 // 6826 // Polarity is controlled from AON registers. 6827 // 6828 // Note:When the MSB is set, the IOC will deactivate the output enable for the 6829 // DIO. 6830 #define IOC_IOCFG18_WU_CFG_W 2 6831 #define IOC_IOCFG18_WU_CFG_M 0x18000000 6832 #define IOC_IOCFG18_WU_CFG_S 27 6833 6834 // Field: [26:24] IOMODE 6835 // 6836 // IO Mode 6837 // Not applicable for IO configured for AON periph. signals and AUX PORT_ID 6838 // 0x01-0x08 6839 // AUX has its own open_source/drain configuration. 6840 // 6841 // 0x2: Reserved. Undefined behavior. 6842 // 0x3: Reserved. Undefined behavior. 6843 // ENUMs: 6844 // OPENSRC_INV Open Source 6845 // Inverted input / output 6846 // OPENSRC Open Source 6847 // Normal input / output 6848 // OPENDR_INV Open Drain 6849 // Inverted input / output 6850 // OPENDR Open Drain, 6851 // Normal input / output 6852 // INV Inverted input / ouput 6853 // NORMAL Normal input / output 6854 #define IOC_IOCFG18_IOMODE_W 3 6855 #define IOC_IOCFG18_IOMODE_M 0x07000000 6856 #define IOC_IOCFG18_IOMODE_S 24 6857 #define IOC_IOCFG18_IOMODE_OPENSRC_INV 0x07000000 6858 #define IOC_IOCFG18_IOMODE_OPENSRC 0x06000000 6859 #define IOC_IOCFG18_IOMODE_OPENDR_INV 0x05000000 6860 #define IOC_IOCFG18_IOMODE_OPENDR 0x04000000 6861 #define IOC_IOCFG18_IOMODE_INV 0x01000000 6862 #define IOC_IOCFG18_IOMODE_NORMAL 0x00000000 6863 6864 // Field: [23] IOEV_AON_PROG2_EN 6865 // 6866 // Event asserted by this IO when edge detection is enabled 6867 // 6868 // 0: Input edge detection does not assert AON_PROG2 event 6869 // 1: Input edge detection asserts AON_PROG2 event 6870 #define IOC_IOCFG18_IOEV_AON_PROG2_EN 0x00800000 6871 #define IOC_IOCFG18_IOEV_AON_PROG2_EN_BITN 23 6872 #define IOC_IOCFG18_IOEV_AON_PROG2_EN_M 0x00800000 6873 #define IOC_IOCFG18_IOEV_AON_PROG2_EN_S 23 6874 6875 // Field: [22] IOEV_AON_PROG1_EN 6876 // 6877 // Event asserted by this IO when edge detection is enabled 6878 // 6879 // 0: Input edge detection does not assert AON_PROG1 event 6880 // 1: Input edge detection asserts AON_PROG1 event 6881 #define IOC_IOCFG18_IOEV_AON_PROG1_EN 0x00400000 6882 #define IOC_IOCFG18_IOEV_AON_PROG1_EN_BITN 22 6883 #define IOC_IOCFG18_IOEV_AON_PROG1_EN_M 0x00400000 6884 #define IOC_IOCFG18_IOEV_AON_PROG1_EN_S 22 6885 6886 // Field: [21] IOEV_AON_PROG0_EN 6887 // 6888 // Event asserted by this IO when edge detection is enabled 6889 // 6890 // 0: Input edge detection does not assert AON_PROG0 event 6891 // 1: Input edge detection asserts AON_PROG0 event 6892 #define IOC_IOCFG18_IOEV_AON_PROG0_EN 0x00200000 6893 #define IOC_IOCFG18_IOEV_AON_PROG0_EN_BITN 21 6894 #define IOC_IOCFG18_IOEV_AON_PROG0_EN_M 0x00200000 6895 #define IOC_IOCFG18_IOEV_AON_PROG0_EN_S 21 6896 6897 // Field: [18] EDGE_IRQ_EN 6898 // 6899 // 0: No interrupt generation 6900 // 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is 6901 // enabled) 6902 #define IOC_IOCFG18_EDGE_IRQ_EN 0x00040000 6903 #define IOC_IOCFG18_EDGE_IRQ_EN_BITN 18 6904 #define IOC_IOCFG18_EDGE_IRQ_EN_M 0x00040000 6905 #define IOC_IOCFG18_EDGE_IRQ_EN_S 18 6906 6907 // Field: [17:16] EDGE_DET 6908 // 6909 // Enable generation of edge detection events on this IO 6910 // ENUMs: 6911 // BOTH Positive and negative edge detection 6912 // POS Positive edge detection 6913 // NEG Negative edge detection 6914 // NONE No edge detection 6915 #define IOC_IOCFG18_EDGE_DET_W 2 6916 #define IOC_IOCFG18_EDGE_DET_M 0x00030000 6917 #define IOC_IOCFG18_EDGE_DET_S 16 6918 #define IOC_IOCFG18_EDGE_DET_BOTH 0x00030000 6919 #define IOC_IOCFG18_EDGE_DET_POS 0x00020000 6920 #define IOC_IOCFG18_EDGE_DET_NEG 0x00010000 6921 #define IOC_IOCFG18_EDGE_DET_NONE 0x00000000 6922 6923 // Field: [14:13] PULL_CTL 6924 // 6925 // Pull control 6926 // ENUMs: 6927 // DIS No pull 6928 // UP Pull up 6929 // DWN Pull down 6930 #define IOC_IOCFG18_PULL_CTL_W 2 6931 #define IOC_IOCFG18_PULL_CTL_M 0x00006000 6932 #define IOC_IOCFG18_PULL_CTL_S 13 6933 #define IOC_IOCFG18_PULL_CTL_DIS 0x00006000 6934 #define IOC_IOCFG18_PULL_CTL_UP 0x00004000 6935 #define IOC_IOCFG18_PULL_CTL_DWN 0x00002000 6936 6937 // Field: [12] SLEW_RED 6938 // 6939 // 0: Normal slew rate 6940 // 1: Enables reduced slew rate in output driver. 6941 #define IOC_IOCFG18_SLEW_RED 0x00001000 6942 #define IOC_IOCFG18_SLEW_RED_BITN 12 6943 #define IOC_IOCFG18_SLEW_RED_M 0x00001000 6944 #define IOC_IOCFG18_SLEW_RED_S 12 6945 6946 // Field: [11:10] IOCURR 6947 // 6948 // Selects IO current mode of this IO. 6949 // ENUMs: 6950 // 4_8MA Extended-Current (EC) mode: Min 8 mA for double 6951 // drive strength IOs (min 4 mA for normal IOs) 6952 // when IOSTR is set to AUTO 6953 // 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set 6954 // to AUTO 6955 // 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set 6956 // to AUTO 6957 #define IOC_IOCFG18_IOCURR_W 2 6958 #define IOC_IOCFG18_IOCURR_M 0x00000C00 6959 #define IOC_IOCFG18_IOCURR_S 10 6960 #define IOC_IOCFG18_IOCURR_4_8MA 0x00000800 6961 #define IOC_IOCFG18_IOCURR_4MA 0x00000400 6962 #define IOC_IOCFG18_IOCURR_2MA 0x00000000 6963 6964 // Field: [9:8] IOSTR 6965 // 6966 // Select source for drive strength control of this IO. 6967 // This setting controls the drive strength of the Low-Current (LC) mode. 6968 // Higher drive strength can be selected in IOCURR 6969 // ENUMs: 6970 // MAX Maximum drive strength, controlled by 6971 // AON_IOC:IOSTRMAX (min 2 mA @1.8V with default 6972 // values) 6973 // MED Medium drive strength, controlled by 6974 // AON_IOC:IOSTRMED (min 2 mA @2.5V with default 6975 // values) 6976 // MIN Minimum drive strength, controlled by 6977 // AON_IOC:IOSTRMIN (min 2 mA @3.3V with default 6978 // values) 6979 // AUTO Automatic drive strength, controlled by AON BATMON 6980 // based on battery voltage. (min 2 mA @VDDS) 6981 #define IOC_IOCFG18_IOSTR_W 2 6982 #define IOC_IOCFG18_IOSTR_M 0x00000300 6983 #define IOC_IOCFG18_IOSTR_S 8 6984 #define IOC_IOCFG18_IOSTR_MAX 0x00000300 6985 #define IOC_IOCFG18_IOSTR_MED 0x00000200 6986 #define IOC_IOCFG18_IOSTR_MIN 0x00000100 6987 #define IOC_IOCFG18_IOSTR_AUTO 0x00000000 6988 6989 // Field: [7] IOEV_RTC_EN 6990 // 6991 // Event asserted by this IO when edge detection is enabled 6992 // 6993 // 0: Input edge detection does not assert RTC event 6994 // 1: Input edge detection asserts RTC event 6995 #define IOC_IOCFG18_IOEV_RTC_EN 0x00000080 6996 #define IOC_IOCFG18_IOEV_RTC_EN_BITN 7 6997 #define IOC_IOCFG18_IOEV_RTC_EN_M 0x00000080 6998 #define IOC_IOCFG18_IOEV_RTC_EN_S 7 6999 7000 // Field: [6] IOEV_MCU_WU_EN 7001 // 7002 // Event asserted by this IO when edge detection is enabled 7003 // 7004 // 0: Input edge detection does not assert MCU_WU event 7005 // 1: Input edge detection asserts MCU_WU event 7006 #define IOC_IOCFG18_IOEV_MCU_WU_EN 0x00000040 7007 #define IOC_IOCFG18_IOEV_MCU_WU_EN_BITN 6 7008 #define IOC_IOCFG18_IOEV_MCU_WU_EN_M 0x00000040 7009 #define IOC_IOCFG18_IOEV_MCU_WU_EN_S 6 7010 7011 // Field: [5:0] PORT_ID 7012 // 7013 // Selects usage for DIO18 7014 // Note: This field should not be written other than the times when PORT_ID 7015 // value is specifically required to change. 7016 // ENUMs: 7017 // RFC_SMI_CL_IN RF Core SMI Command Link In 7018 // RFC_SMI_CL_OUT RF Core SMI Command Link Out 7019 // RFC_SMI_DL_IN RF Core SMI Data Link In 7020 // RFC_SMI_DL_OUT RF Core SMI Data Link Out 7021 // RFC_GPI1 RF Core Data In 1 7022 // RFC_GPI0 RF Core Data In 0 7023 // RFC_GPO3 RF Core Data Out 3 7024 // RFC_GPO2 RF Core Data Out 2 7025 // RFC_GPO1 RF Core Data Out 1 7026 // RFC_GPO0 RF Core Data Out 0 7027 // RFC_TRC RF Core Trace 7028 // I2S_MCLK I2S MCLK 7029 // I2S_BCLK I2S BCLK 7030 // I2S_WCLK I2S WCLK 7031 // I2S_AD1 I2S Data 1 7032 // I2S_AD0 I2S Data 0 7033 // SSI1_CLK SSI1 CLK 7034 // SSI1_FSS SSI1 FSS 7035 // SSI1_TX SSI1 TX 7036 // SSI1_RX SSI1 RX 7037 // CPU_SWV CPU SWV 7038 // PORT_EVENT7 PORT EVENT 7 7039 // Can be used as a general 7040 // purpose IO event by selecting it through 7041 // registers in the EVENT module, for example 7042 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 7043 // and so on 7044 // PORT_EVENT6 PORT EVENT 6 7045 // Can be used as a general 7046 // purpose IO event by selecting it through 7047 // registers in the EVENT module, for example 7048 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 7049 // and so on 7050 // PORT_EVENT5 PORT EVENT 5 7051 // Can be used as a general 7052 // purpose IO event by selecting it through 7053 // registers in the EVENT module, for example 7054 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 7055 // and so on 7056 // PORT_EVENT4 PORT EVENT 4 7057 // Can be used as a general 7058 // purpose IO event by selecting it through 7059 // registers in the EVENT module, for example 7060 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 7061 // and so on 7062 // PORT_EVENT3 PORT EVENT 3 7063 // Can be used as a general 7064 // purpose IO event by selecting it through 7065 // registers in the EVENT module, for example 7066 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 7067 // and so on 7068 // PORT_EVENT2 PORT EVENT 2 7069 // Can be used as a general 7070 // purpose IO event by selecting it through 7071 // registers in the EVENT module, for example 7072 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 7073 // and so on 7074 // PORT_EVENT1 PORT EVENT 1 7075 // Can be used as a general 7076 // purpose IO event by selecting it through 7077 // registers in the EVENT module, for example 7078 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 7079 // and so on 7080 // PORT_EVENT0 PORT EVENT 0 7081 // Can be used as a general 7082 // purpose IO event by selecting it through 7083 // registers in the EVENT module, for example 7084 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 7085 // and so on 7086 // UART1_RTS UART1 RTS 7087 // UART1_CTS UART1 CTS 7088 // UART1_TX UART1 TX 7089 // UART1_RX UART1 RX 7090 // UART0_RTS UART0 RTS 7091 // UART0_CTS UART0 CTS 7092 // UART0_TX UART0 TX 7093 // UART0_RX UART0 RX 7094 // I2C_MSSCL I2C Clock 7095 // I2C_MSSDA I2C Data 7096 // SSI0_CLK SSI0 CLK 7097 // SSI0_FSS SSI0 FSS 7098 // SSI0_TX SSI0 TX 7099 // SSI0_RX SSI0 RX 7100 // AUX_IO AUX IO 7101 // AON_CLK32K AON 32 KHz clock (SCLK_LF) 7102 // GPIO General Purpose IO 7103 #define IOC_IOCFG18_PORT_ID_W 6 7104 #define IOC_IOCFG18_PORT_ID_M 0x0000003F 7105 #define IOC_IOCFG18_PORT_ID_S 0 7106 #define IOC_IOCFG18_PORT_ID_RFC_SMI_CL_IN 0x00000038 7107 #define IOC_IOCFG18_PORT_ID_RFC_SMI_CL_OUT 0x00000037 7108 #define IOC_IOCFG18_PORT_ID_RFC_SMI_DL_IN 0x00000036 7109 #define IOC_IOCFG18_PORT_ID_RFC_SMI_DL_OUT 0x00000035 7110 #define IOC_IOCFG18_PORT_ID_RFC_GPI1 0x00000034 7111 #define IOC_IOCFG18_PORT_ID_RFC_GPI0 0x00000033 7112 #define IOC_IOCFG18_PORT_ID_RFC_GPO3 0x00000032 7113 #define IOC_IOCFG18_PORT_ID_RFC_GPO2 0x00000031 7114 #define IOC_IOCFG18_PORT_ID_RFC_GPO1 0x00000030 7115 #define IOC_IOCFG18_PORT_ID_RFC_GPO0 0x0000002F 7116 #define IOC_IOCFG18_PORT_ID_RFC_TRC 0x0000002E 7117 #define IOC_IOCFG18_PORT_ID_I2S_MCLK 0x00000029 7118 #define IOC_IOCFG18_PORT_ID_I2S_BCLK 0x00000028 7119 #define IOC_IOCFG18_PORT_ID_I2S_WCLK 0x00000027 7120 #define IOC_IOCFG18_PORT_ID_I2S_AD1 0x00000026 7121 #define IOC_IOCFG18_PORT_ID_I2S_AD0 0x00000025 7122 #define IOC_IOCFG18_PORT_ID_SSI1_CLK 0x00000024 7123 #define IOC_IOCFG18_PORT_ID_SSI1_FSS 0x00000023 7124 #define IOC_IOCFG18_PORT_ID_SSI1_TX 0x00000022 7125 #define IOC_IOCFG18_PORT_ID_SSI1_RX 0x00000021 7126 #define IOC_IOCFG18_PORT_ID_CPU_SWV 0x00000020 7127 #define IOC_IOCFG18_PORT_ID_PORT_EVENT7 0x0000001E 7128 #define IOC_IOCFG18_PORT_ID_PORT_EVENT6 0x0000001D 7129 #define IOC_IOCFG18_PORT_ID_PORT_EVENT5 0x0000001C 7130 #define IOC_IOCFG18_PORT_ID_PORT_EVENT4 0x0000001B 7131 #define IOC_IOCFG18_PORT_ID_PORT_EVENT3 0x0000001A 7132 #define IOC_IOCFG18_PORT_ID_PORT_EVENT2 0x00000019 7133 #define IOC_IOCFG18_PORT_ID_PORT_EVENT1 0x00000018 7134 #define IOC_IOCFG18_PORT_ID_PORT_EVENT0 0x00000017 7135 #define IOC_IOCFG18_PORT_ID_UART1_RTS 0x00000016 7136 #define IOC_IOCFG18_PORT_ID_UART1_CTS 0x00000015 7137 #define IOC_IOCFG18_PORT_ID_UART1_TX 0x00000014 7138 #define IOC_IOCFG18_PORT_ID_UART1_RX 0x00000013 7139 #define IOC_IOCFG18_PORT_ID_UART0_RTS 0x00000012 7140 #define IOC_IOCFG18_PORT_ID_UART0_CTS 0x00000011 7141 #define IOC_IOCFG18_PORT_ID_UART0_TX 0x00000010 7142 #define IOC_IOCFG18_PORT_ID_UART0_RX 0x0000000F 7143 #define IOC_IOCFG18_PORT_ID_I2C_MSSCL 0x0000000E 7144 #define IOC_IOCFG18_PORT_ID_I2C_MSSDA 0x0000000D 7145 #define IOC_IOCFG18_PORT_ID_SSI0_CLK 0x0000000C 7146 #define IOC_IOCFG18_PORT_ID_SSI0_FSS 0x0000000B 7147 #define IOC_IOCFG18_PORT_ID_SSI0_TX 0x0000000A 7148 #define IOC_IOCFG18_PORT_ID_SSI0_RX 0x00000009 7149 #define IOC_IOCFG18_PORT_ID_AUX_IO 0x00000008 7150 #define IOC_IOCFG18_PORT_ID_AON_CLK32K 0x00000007 7151 #define IOC_IOCFG18_PORT_ID_GPIO 0x00000000 7152 7153 //***************************************************************************** 7154 // 7155 // Register: IOC_O_IOCFG19 7156 // 7157 //***************************************************************************** 7158 // Field: [30] HYST_EN 7159 // 7160 // 0: Input hysteresis disable 7161 // 1: Input hysteresis enable 7162 #define IOC_IOCFG19_HYST_EN 0x40000000 7163 #define IOC_IOCFG19_HYST_EN_BITN 30 7164 #define IOC_IOCFG19_HYST_EN_M 0x40000000 7165 #define IOC_IOCFG19_HYST_EN_S 30 7166 7167 // Field: [29] IE 7168 // 7169 // 0: Input disabled 7170 // 1: Input enabled 7171 // 7172 // Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be 7173 // ignored. 7174 #define IOC_IOCFG19_IE 0x20000000 7175 #define IOC_IOCFG19_IE_BITN 29 7176 #define IOC_IOCFG19_IE_M 0x20000000 7177 #define IOC_IOCFG19_IE_S 29 7178 7179 // Field: [28:27] WU_CFG 7180 // 7181 // If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or 7182 // >0x08: 7183 // 7184 // 00: No wake-up 7185 // 01: No wake-up 7186 // 10: Wakes up from shutdown if this pad is going low. 7187 // 11: Wakes up from shutdown if this pad is going high. 7188 // 7189 // If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, 7190 // this register only sets wakeup enable or not. 7191 // 7192 // 00, 01: Wakeup disabled 7193 // 10, 11: Wakeup enabled 7194 // 7195 // Polarity is controlled from AON registers. 7196 // 7197 // Note:When the MSB is set, the IOC will deactivate the output enable for the 7198 // DIO. 7199 #define IOC_IOCFG19_WU_CFG_W 2 7200 #define IOC_IOCFG19_WU_CFG_M 0x18000000 7201 #define IOC_IOCFG19_WU_CFG_S 27 7202 7203 // Field: [26:24] IOMODE 7204 // 7205 // IO Mode 7206 // Not applicable for IO configured for AON periph. signals and AUX PORT_ID 7207 // 0x01-0x08 7208 // AUX has its own open_source/drain configuration. 7209 // 7210 // 0x2: Reserved. Undefined behavior. 7211 // 0x3: Reserved. Undefined behavior. 7212 // ENUMs: 7213 // OPENSRC_INV Open Source 7214 // Inverted input / output 7215 // OPENSRC Open Source 7216 // Normal input / output 7217 // OPENDR_INV Open Drain 7218 // Inverted input / output 7219 // OPENDR Open Drain, 7220 // Normal input / output 7221 // INV Inverted input / ouput 7222 // NORMAL Normal input / output 7223 #define IOC_IOCFG19_IOMODE_W 3 7224 #define IOC_IOCFG19_IOMODE_M 0x07000000 7225 #define IOC_IOCFG19_IOMODE_S 24 7226 #define IOC_IOCFG19_IOMODE_OPENSRC_INV 0x07000000 7227 #define IOC_IOCFG19_IOMODE_OPENSRC 0x06000000 7228 #define IOC_IOCFG19_IOMODE_OPENDR_INV 0x05000000 7229 #define IOC_IOCFG19_IOMODE_OPENDR 0x04000000 7230 #define IOC_IOCFG19_IOMODE_INV 0x01000000 7231 #define IOC_IOCFG19_IOMODE_NORMAL 0x00000000 7232 7233 // Field: [23] IOEV_AON_PROG2_EN 7234 // 7235 // Event asserted by this IO when edge detection is enabled 7236 // 7237 // 0: Input edge detection does not assert AON_PROG2 event 7238 // 1: Input edge detection asserts AON_PROG2 event 7239 #define IOC_IOCFG19_IOEV_AON_PROG2_EN 0x00800000 7240 #define IOC_IOCFG19_IOEV_AON_PROG2_EN_BITN 23 7241 #define IOC_IOCFG19_IOEV_AON_PROG2_EN_M 0x00800000 7242 #define IOC_IOCFG19_IOEV_AON_PROG2_EN_S 23 7243 7244 // Field: [22] IOEV_AON_PROG1_EN 7245 // 7246 // Event asserted by this IO when edge detection is enabled 7247 // 7248 // 0: Input edge detection does not assert AON_PROG1 event 7249 // 1: Input edge detection asserts AON_PROG1 event 7250 #define IOC_IOCFG19_IOEV_AON_PROG1_EN 0x00400000 7251 #define IOC_IOCFG19_IOEV_AON_PROG1_EN_BITN 22 7252 #define IOC_IOCFG19_IOEV_AON_PROG1_EN_M 0x00400000 7253 #define IOC_IOCFG19_IOEV_AON_PROG1_EN_S 22 7254 7255 // Field: [21] IOEV_AON_PROG0_EN 7256 // 7257 // Event asserted by this IO when edge detection is enabled 7258 // 7259 // 0: Input edge detection does not assert AON_PROG0 event 7260 // 1: Input edge detection asserts AON_PROG0 event 7261 #define IOC_IOCFG19_IOEV_AON_PROG0_EN 0x00200000 7262 #define IOC_IOCFG19_IOEV_AON_PROG0_EN_BITN 21 7263 #define IOC_IOCFG19_IOEV_AON_PROG0_EN_M 0x00200000 7264 #define IOC_IOCFG19_IOEV_AON_PROG0_EN_S 21 7265 7266 // Field: [18] EDGE_IRQ_EN 7267 // 7268 // 0: No interrupt generation 7269 // 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is 7270 // enabled) 7271 #define IOC_IOCFG19_EDGE_IRQ_EN 0x00040000 7272 #define IOC_IOCFG19_EDGE_IRQ_EN_BITN 18 7273 #define IOC_IOCFG19_EDGE_IRQ_EN_M 0x00040000 7274 #define IOC_IOCFG19_EDGE_IRQ_EN_S 18 7275 7276 // Field: [17:16] EDGE_DET 7277 // 7278 // Enable generation of edge detection events on this IO 7279 // ENUMs: 7280 // BOTH Positive and negative edge detection 7281 // POS Positive edge detection 7282 // NEG Negative edge detection 7283 // NONE No edge detection 7284 #define IOC_IOCFG19_EDGE_DET_W 2 7285 #define IOC_IOCFG19_EDGE_DET_M 0x00030000 7286 #define IOC_IOCFG19_EDGE_DET_S 16 7287 #define IOC_IOCFG19_EDGE_DET_BOTH 0x00030000 7288 #define IOC_IOCFG19_EDGE_DET_POS 0x00020000 7289 #define IOC_IOCFG19_EDGE_DET_NEG 0x00010000 7290 #define IOC_IOCFG19_EDGE_DET_NONE 0x00000000 7291 7292 // Field: [14:13] PULL_CTL 7293 // 7294 // Pull control 7295 // ENUMs: 7296 // DIS No pull 7297 // UP Pull up 7298 // DWN Pull down 7299 #define IOC_IOCFG19_PULL_CTL_W 2 7300 #define IOC_IOCFG19_PULL_CTL_M 0x00006000 7301 #define IOC_IOCFG19_PULL_CTL_S 13 7302 #define IOC_IOCFG19_PULL_CTL_DIS 0x00006000 7303 #define IOC_IOCFG19_PULL_CTL_UP 0x00004000 7304 #define IOC_IOCFG19_PULL_CTL_DWN 0x00002000 7305 7306 // Field: [12] SLEW_RED 7307 // 7308 // 0: Normal slew rate 7309 // 1: Enables reduced slew rate in output driver. 7310 #define IOC_IOCFG19_SLEW_RED 0x00001000 7311 #define IOC_IOCFG19_SLEW_RED_BITN 12 7312 #define IOC_IOCFG19_SLEW_RED_M 0x00001000 7313 #define IOC_IOCFG19_SLEW_RED_S 12 7314 7315 // Field: [11:10] IOCURR 7316 // 7317 // Selects IO current mode of this IO. 7318 // ENUMs: 7319 // 4_8MA Extended-Current (EC) mode: Min 8 mA for double 7320 // drive strength IOs (min 4 mA for normal IOs) 7321 // when IOSTR is set to AUTO 7322 // 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set 7323 // to AUTO 7324 // 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set 7325 // to AUTO 7326 #define IOC_IOCFG19_IOCURR_W 2 7327 #define IOC_IOCFG19_IOCURR_M 0x00000C00 7328 #define IOC_IOCFG19_IOCURR_S 10 7329 #define IOC_IOCFG19_IOCURR_4_8MA 0x00000800 7330 #define IOC_IOCFG19_IOCURR_4MA 0x00000400 7331 #define IOC_IOCFG19_IOCURR_2MA 0x00000000 7332 7333 // Field: [9:8] IOSTR 7334 // 7335 // Select source for drive strength control of this IO. 7336 // This setting controls the drive strength of the Low-Current (LC) mode. 7337 // Higher drive strength can be selected in IOCURR 7338 // ENUMs: 7339 // MAX Maximum drive strength, controlled by 7340 // AON_IOC:IOSTRMAX (min 2 mA @1.8V with default 7341 // values) 7342 // MED Medium drive strength, controlled by 7343 // AON_IOC:IOSTRMED (min 2 mA @2.5V with default 7344 // values) 7345 // MIN Minimum drive strength, controlled by 7346 // AON_IOC:IOSTRMIN (min 2 mA @3.3V with default 7347 // values) 7348 // AUTO Automatic drive strength, controlled by AON BATMON 7349 // based on battery voltage. (min 2 mA @VDDS) 7350 #define IOC_IOCFG19_IOSTR_W 2 7351 #define IOC_IOCFG19_IOSTR_M 0x00000300 7352 #define IOC_IOCFG19_IOSTR_S 8 7353 #define IOC_IOCFG19_IOSTR_MAX 0x00000300 7354 #define IOC_IOCFG19_IOSTR_MED 0x00000200 7355 #define IOC_IOCFG19_IOSTR_MIN 0x00000100 7356 #define IOC_IOCFG19_IOSTR_AUTO 0x00000000 7357 7358 // Field: [7] IOEV_RTC_EN 7359 // 7360 // Event asserted by this IO when edge detection is enabled 7361 // 7362 // 0: Input edge detection does not assert RTC event 7363 // 1: Input edge detection asserts RTC event 7364 #define IOC_IOCFG19_IOEV_RTC_EN 0x00000080 7365 #define IOC_IOCFG19_IOEV_RTC_EN_BITN 7 7366 #define IOC_IOCFG19_IOEV_RTC_EN_M 0x00000080 7367 #define IOC_IOCFG19_IOEV_RTC_EN_S 7 7368 7369 // Field: [6] IOEV_MCU_WU_EN 7370 // 7371 // Event asserted by this IO when edge detection is enabled 7372 // 7373 // 0: Input edge detection does not assert MCU_WU event 7374 // 1: Input edge detection asserts MCU_WU event 7375 #define IOC_IOCFG19_IOEV_MCU_WU_EN 0x00000040 7376 #define IOC_IOCFG19_IOEV_MCU_WU_EN_BITN 6 7377 #define IOC_IOCFG19_IOEV_MCU_WU_EN_M 0x00000040 7378 #define IOC_IOCFG19_IOEV_MCU_WU_EN_S 6 7379 7380 // Field: [5:0] PORT_ID 7381 // 7382 // Selects usage for DIO19 7383 // Note: This field should not be written other than the times when PORT_ID 7384 // value is specifically required to change. 7385 // ENUMs: 7386 // RFC_SMI_CL_IN RF Core SMI Command Link In 7387 // RFC_SMI_CL_OUT RF Core SMI Command Link Out 7388 // RFC_SMI_DL_IN RF Core SMI Data Link In 7389 // RFC_SMI_DL_OUT RF Core SMI Data Link Out 7390 // RFC_GPI1 RF Core Data In 1 7391 // RFC_GPI0 RF Core Data In 0 7392 // RFC_GPO3 RF Core Data Out 3 7393 // RFC_GPO2 RF Core Data Out 2 7394 // RFC_GPO1 RF Core Data Out 1 7395 // RFC_GPO0 RF Core Data Out 0 7396 // RFC_TRC RF Core Trace 7397 // I2S_MCLK I2S MCLK 7398 // I2S_BCLK I2S BCLK 7399 // I2S_WCLK I2S WCLK 7400 // I2S_AD1 I2S Data 1 7401 // I2S_AD0 I2S Data 0 7402 // SSI1_CLK SSI1 CLK 7403 // SSI1_FSS SSI1 FSS 7404 // SSI1_TX SSI1 TX 7405 // SSI1_RX SSI1 RX 7406 // CPU_SWV CPU SWV 7407 // PORT_EVENT7 PORT EVENT 7 7408 // Can be used as a general 7409 // purpose IO event by selecting it through 7410 // registers in the EVENT module, for example 7411 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 7412 // and so on 7413 // PORT_EVENT6 PORT EVENT 6 7414 // Can be used as a general 7415 // purpose IO event by selecting it through 7416 // registers in the EVENT module, for example 7417 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 7418 // and so on 7419 // PORT_EVENT5 PORT EVENT 5 7420 // Can be used as a general 7421 // purpose IO event by selecting it through 7422 // registers in the EVENT module, for example 7423 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 7424 // and so on 7425 // PORT_EVENT4 PORT EVENT 4 7426 // Can be used as a general 7427 // purpose IO event by selecting it through 7428 // registers in the EVENT module, for example 7429 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 7430 // and so on 7431 // PORT_EVENT3 PORT EVENT 3 7432 // Can be used as a general 7433 // purpose IO event by selecting it through 7434 // registers in the EVENT module, for example 7435 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 7436 // and so on 7437 // PORT_EVENT2 PORT EVENT 2 7438 // Can be used as a general 7439 // purpose IO event by selecting it through 7440 // registers in the EVENT module, for example 7441 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 7442 // and so on 7443 // PORT_EVENT1 PORT EVENT 1 7444 // Can be used as a general 7445 // purpose IO event by selecting it through 7446 // registers in the EVENT module, for example 7447 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 7448 // and so on 7449 // PORT_EVENT0 PORT EVENT 0 7450 // Can be used as a general 7451 // purpose IO event by selecting it through 7452 // registers in the EVENT module, for example 7453 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 7454 // and so on 7455 // UART1_RTS UART1 RTS 7456 // UART1_CTS UART1 CTS 7457 // UART1_TX UART1 TX 7458 // UART1_RX UART1 RX 7459 // UART0_RTS UART0 RTS 7460 // UART0_CTS UART0 CTS 7461 // UART0_TX UART0 TX 7462 // UART0_RX UART0 RX 7463 // I2C_MSSCL I2C Clock 7464 // I2C_MSSDA I2C Data 7465 // SSI0_CLK SSI0 CLK 7466 // SSI0_FSS SSI0 FSS 7467 // SSI0_TX SSI0 TX 7468 // SSI0_RX SSI0 RX 7469 // AUX_IO AUX IO 7470 // AON_CLK32K AON 32 KHz clock (SCLK_LF) 7471 // GPIO General Purpose IO 7472 #define IOC_IOCFG19_PORT_ID_W 6 7473 #define IOC_IOCFG19_PORT_ID_M 0x0000003F 7474 #define IOC_IOCFG19_PORT_ID_S 0 7475 #define IOC_IOCFG19_PORT_ID_RFC_SMI_CL_IN 0x00000038 7476 #define IOC_IOCFG19_PORT_ID_RFC_SMI_CL_OUT 0x00000037 7477 #define IOC_IOCFG19_PORT_ID_RFC_SMI_DL_IN 0x00000036 7478 #define IOC_IOCFG19_PORT_ID_RFC_SMI_DL_OUT 0x00000035 7479 #define IOC_IOCFG19_PORT_ID_RFC_GPI1 0x00000034 7480 #define IOC_IOCFG19_PORT_ID_RFC_GPI0 0x00000033 7481 #define IOC_IOCFG19_PORT_ID_RFC_GPO3 0x00000032 7482 #define IOC_IOCFG19_PORT_ID_RFC_GPO2 0x00000031 7483 #define IOC_IOCFG19_PORT_ID_RFC_GPO1 0x00000030 7484 #define IOC_IOCFG19_PORT_ID_RFC_GPO0 0x0000002F 7485 #define IOC_IOCFG19_PORT_ID_RFC_TRC 0x0000002E 7486 #define IOC_IOCFG19_PORT_ID_I2S_MCLK 0x00000029 7487 #define IOC_IOCFG19_PORT_ID_I2S_BCLK 0x00000028 7488 #define IOC_IOCFG19_PORT_ID_I2S_WCLK 0x00000027 7489 #define IOC_IOCFG19_PORT_ID_I2S_AD1 0x00000026 7490 #define IOC_IOCFG19_PORT_ID_I2S_AD0 0x00000025 7491 #define IOC_IOCFG19_PORT_ID_SSI1_CLK 0x00000024 7492 #define IOC_IOCFG19_PORT_ID_SSI1_FSS 0x00000023 7493 #define IOC_IOCFG19_PORT_ID_SSI1_TX 0x00000022 7494 #define IOC_IOCFG19_PORT_ID_SSI1_RX 0x00000021 7495 #define IOC_IOCFG19_PORT_ID_CPU_SWV 0x00000020 7496 #define IOC_IOCFG19_PORT_ID_PORT_EVENT7 0x0000001E 7497 #define IOC_IOCFG19_PORT_ID_PORT_EVENT6 0x0000001D 7498 #define IOC_IOCFG19_PORT_ID_PORT_EVENT5 0x0000001C 7499 #define IOC_IOCFG19_PORT_ID_PORT_EVENT4 0x0000001B 7500 #define IOC_IOCFG19_PORT_ID_PORT_EVENT3 0x0000001A 7501 #define IOC_IOCFG19_PORT_ID_PORT_EVENT2 0x00000019 7502 #define IOC_IOCFG19_PORT_ID_PORT_EVENT1 0x00000018 7503 #define IOC_IOCFG19_PORT_ID_PORT_EVENT0 0x00000017 7504 #define IOC_IOCFG19_PORT_ID_UART1_RTS 0x00000016 7505 #define IOC_IOCFG19_PORT_ID_UART1_CTS 0x00000015 7506 #define IOC_IOCFG19_PORT_ID_UART1_TX 0x00000014 7507 #define IOC_IOCFG19_PORT_ID_UART1_RX 0x00000013 7508 #define IOC_IOCFG19_PORT_ID_UART0_RTS 0x00000012 7509 #define IOC_IOCFG19_PORT_ID_UART0_CTS 0x00000011 7510 #define IOC_IOCFG19_PORT_ID_UART0_TX 0x00000010 7511 #define IOC_IOCFG19_PORT_ID_UART0_RX 0x0000000F 7512 #define IOC_IOCFG19_PORT_ID_I2C_MSSCL 0x0000000E 7513 #define IOC_IOCFG19_PORT_ID_I2C_MSSDA 0x0000000D 7514 #define IOC_IOCFG19_PORT_ID_SSI0_CLK 0x0000000C 7515 #define IOC_IOCFG19_PORT_ID_SSI0_FSS 0x0000000B 7516 #define IOC_IOCFG19_PORT_ID_SSI0_TX 0x0000000A 7517 #define IOC_IOCFG19_PORT_ID_SSI0_RX 0x00000009 7518 #define IOC_IOCFG19_PORT_ID_AUX_IO 0x00000008 7519 #define IOC_IOCFG19_PORT_ID_AON_CLK32K 0x00000007 7520 #define IOC_IOCFG19_PORT_ID_GPIO 0x00000000 7521 7522 //***************************************************************************** 7523 // 7524 // Register: IOC_O_IOCFG20 7525 // 7526 //***************************************************************************** 7527 // Field: [30] HYST_EN 7528 // 7529 // 0: Input hysteresis disable 7530 // 1: Input hysteresis enable 7531 #define IOC_IOCFG20_HYST_EN 0x40000000 7532 #define IOC_IOCFG20_HYST_EN_BITN 30 7533 #define IOC_IOCFG20_HYST_EN_M 0x40000000 7534 #define IOC_IOCFG20_HYST_EN_S 30 7535 7536 // Field: [29] IE 7537 // 7538 // 0: Input disabled 7539 // 1: Input enabled 7540 // 7541 // Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be 7542 // ignored. 7543 #define IOC_IOCFG20_IE 0x20000000 7544 #define IOC_IOCFG20_IE_BITN 29 7545 #define IOC_IOCFG20_IE_M 0x20000000 7546 #define IOC_IOCFG20_IE_S 29 7547 7548 // Field: [28:27] WU_CFG 7549 // 7550 // If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or 7551 // >0x08: 7552 // 7553 // 00: No wake-up 7554 // 01: No wake-up 7555 // 10: Wakes up from shutdown if this pad is going low. 7556 // 11: Wakes up from shutdown if this pad is going high. 7557 // 7558 // If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, 7559 // this register only sets wakeup enable or not. 7560 // 7561 // 00, 01: Wakeup disabled 7562 // 10, 11: Wakeup enabled 7563 // 7564 // Polarity is controlled from AON registers. 7565 // 7566 // Note:When the MSB is set, the IOC will deactivate the output enable for the 7567 // DIO. 7568 #define IOC_IOCFG20_WU_CFG_W 2 7569 #define IOC_IOCFG20_WU_CFG_M 0x18000000 7570 #define IOC_IOCFG20_WU_CFG_S 27 7571 7572 // Field: [26:24] IOMODE 7573 // 7574 // IO Mode 7575 // Not applicable for IO configured for AON periph. signals and AUX PORT_ID 7576 // 0x01-0x08 7577 // AUX has its own open_source/drain configuration. 7578 // 7579 // 0x2: Reserved. Undefined behavior. 7580 // 0x3: Reserved. Undefined behavior. 7581 // ENUMs: 7582 // OPENSRC_INV Open Source 7583 // Inverted input / output 7584 // OPENSRC Open Source 7585 // Normal input / output 7586 // OPENDR_INV Open Drain 7587 // Inverted input / output 7588 // OPENDR Open Drain, 7589 // Normal input / output 7590 // INV Inverted input / ouput 7591 // NORMAL Normal input / output 7592 #define IOC_IOCFG20_IOMODE_W 3 7593 #define IOC_IOCFG20_IOMODE_M 0x07000000 7594 #define IOC_IOCFG20_IOMODE_S 24 7595 #define IOC_IOCFG20_IOMODE_OPENSRC_INV 0x07000000 7596 #define IOC_IOCFG20_IOMODE_OPENSRC 0x06000000 7597 #define IOC_IOCFG20_IOMODE_OPENDR_INV 0x05000000 7598 #define IOC_IOCFG20_IOMODE_OPENDR 0x04000000 7599 #define IOC_IOCFG20_IOMODE_INV 0x01000000 7600 #define IOC_IOCFG20_IOMODE_NORMAL 0x00000000 7601 7602 // Field: [23] IOEV_AON_PROG2_EN 7603 // 7604 // Event asserted by this IO when edge detection is enabled 7605 // 7606 // 0: Input edge detection does not assert AON_PROG2 event 7607 // 1: Input edge detection asserts AON_PROG2 event 7608 #define IOC_IOCFG20_IOEV_AON_PROG2_EN 0x00800000 7609 #define IOC_IOCFG20_IOEV_AON_PROG2_EN_BITN 23 7610 #define IOC_IOCFG20_IOEV_AON_PROG2_EN_M 0x00800000 7611 #define IOC_IOCFG20_IOEV_AON_PROG2_EN_S 23 7612 7613 // Field: [22] IOEV_AON_PROG1_EN 7614 // 7615 // Event asserted by this IO when edge detection is enabled 7616 // 7617 // 0: Input edge detection does not assert AON_PROG1 event 7618 // 1: Input edge detection asserts AON_PROG1 event 7619 #define IOC_IOCFG20_IOEV_AON_PROG1_EN 0x00400000 7620 #define IOC_IOCFG20_IOEV_AON_PROG1_EN_BITN 22 7621 #define IOC_IOCFG20_IOEV_AON_PROG1_EN_M 0x00400000 7622 #define IOC_IOCFG20_IOEV_AON_PROG1_EN_S 22 7623 7624 // Field: [21] IOEV_AON_PROG0_EN 7625 // 7626 // Event asserted by this IO when edge detection is enabled 7627 // 7628 // 0: Input edge detection does not assert AON_PROG0 event 7629 // 1: Input edge detection asserts AON_PROG0 event 7630 #define IOC_IOCFG20_IOEV_AON_PROG0_EN 0x00200000 7631 #define IOC_IOCFG20_IOEV_AON_PROG0_EN_BITN 21 7632 #define IOC_IOCFG20_IOEV_AON_PROG0_EN_M 0x00200000 7633 #define IOC_IOCFG20_IOEV_AON_PROG0_EN_S 21 7634 7635 // Field: [18] EDGE_IRQ_EN 7636 // 7637 // 0: No interrupt generation 7638 // 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is 7639 // enabled) 7640 #define IOC_IOCFG20_EDGE_IRQ_EN 0x00040000 7641 #define IOC_IOCFG20_EDGE_IRQ_EN_BITN 18 7642 #define IOC_IOCFG20_EDGE_IRQ_EN_M 0x00040000 7643 #define IOC_IOCFG20_EDGE_IRQ_EN_S 18 7644 7645 // Field: [17:16] EDGE_DET 7646 // 7647 // Enable generation of edge detection events on this IO 7648 // ENUMs: 7649 // BOTH Positive and negative edge detection 7650 // POS Positive edge detection 7651 // NEG Negative edge detection 7652 // NONE No edge detection 7653 #define IOC_IOCFG20_EDGE_DET_W 2 7654 #define IOC_IOCFG20_EDGE_DET_M 0x00030000 7655 #define IOC_IOCFG20_EDGE_DET_S 16 7656 #define IOC_IOCFG20_EDGE_DET_BOTH 0x00030000 7657 #define IOC_IOCFG20_EDGE_DET_POS 0x00020000 7658 #define IOC_IOCFG20_EDGE_DET_NEG 0x00010000 7659 #define IOC_IOCFG20_EDGE_DET_NONE 0x00000000 7660 7661 // Field: [14:13] PULL_CTL 7662 // 7663 // Pull control 7664 // ENUMs: 7665 // DIS No pull 7666 // UP Pull up 7667 // DWN Pull down 7668 #define IOC_IOCFG20_PULL_CTL_W 2 7669 #define IOC_IOCFG20_PULL_CTL_M 0x00006000 7670 #define IOC_IOCFG20_PULL_CTL_S 13 7671 #define IOC_IOCFG20_PULL_CTL_DIS 0x00006000 7672 #define IOC_IOCFG20_PULL_CTL_UP 0x00004000 7673 #define IOC_IOCFG20_PULL_CTL_DWN 0x00002000 7674 7675 // Field: [12] SLEW_RED 7676 // 7677 // 0: Normal slew rate 7678 // 1: Enables reduced slew rate in output driver. 7679 #define IOC_IOCFG20_SLEW_RED 0x00001000 7680 #define IOC_IOCFG20_SLEW_RED_BITN 12 7681 #define IOC_IOCFG20_SLEW_RED_M 0x00001000 7682 #define IOC_IOCFG20_SLEW_RED_S 12 7683 7684 // Field: [11:10] IOCURR 7685 // 7686 // Selects IO current mode of this IO. 7687 // ENUMs: 7688 // 4_8MA Extended-Current (EC) mode: Min 8 mA for double 7689 // drive strength IOs (min 4 mA for normal IOs) 7690 // when IOSTR is set to AUTO 7691 // 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set 7692 // to AUTO 7693 // 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set 7694 // to AUTO 7695 #define IOC_IOCFG20_IOCURR_W 2 7696 #define IOC_IOCFG20_IOCURR_M 0x00000C00 7697 #define IOC_IOCFG20_IOCURR_S 10 7698 #define IOC_IOCFG20_IOCURR_4_8MA 0x00000800 7699 #define IOC_IOCFG20_IOCURR_4MA 0x00000400 7700 #define IOC_IOCFG20_IOCURR_2MA 0x00000000 7701 7702 // Field: [9:8] IOSTR 7703 // 7704 // Select source for drive strength control of this IO. 7705 // This setting controls the drive strength of the Low-Current (LC) mode. 7706 // Higher drive strength can be selected in IOCURR 7707 // ENUMs: 7708 // MAX Maximum drive strength, controlled by 7709 // AON_IOC:IOSTRMAX (min 2 mA @1.8V with default 7710 // values) 7711 // MED Medium drive strength, controlled by 7712 // AON_IOC:IOSTRMED (min 2 mA @2.5V with default 7713 // values) 7714 // MIN Minimum drive strength, controlled by 7715 // AON_IOC:IOSTRMIN (min 2 mA @3.3V with default 7716 // values) 7717 // AUTO Automatic drive strength, controlled by AON BATMON 7718 // based on battery voltage. (min 2 mA @VDDS) 7719 #define IOC_IOCFG20_IOSTR_W 2 7720 #define IOC_IOCFG20_IOSTR_M 0x00000300 7721 #define IOC_IOCFG20_IOSTR_S 8 7722 #define IOC_IOCFG20_IOSTR_MAX 0x00000300 7723 #define IOC_IOCFG20_IOSTR_MED 0x00000200 7724 #define IOC_IOCFG20_IOSTR_MIN 0x00000100 7725 #define IOC_IOCFG20_IOSTR_AUTO 0x00000000 7726 7727 // Field: [7] IOEV_RTC_EN 7728 // 7729 // Event asserted by this IO when edge detection is enabled 7730 // 7731 // 0: Input edge detection does not assert RTC event 7732 // 1: Input edge detection asserts RTC event 7733 #define IOC_IOCFG20_IOEV_RTC_EN 0x00000080 7734 #define IOC_IOCFG20_IOEV_RTC_EN_BITN 7 7735 #define IOC_IOCFG20_IOEV_RTC_EN_M 0x00000080 7736 #define IOC_IOCFG20_IOEV_RTC_EN_S 7 7737 7738 // Field: [6] IOEV_MCU_WU_EN 7739 // 7740 // Event asserted by this IO when edge detection is enabled 7741 // 7742 // 0: Input edge detection does not assert MCU_WU event 7743 // 1: Input edge detection asserts MCU_WU event 7744 #define IOC_IOCFG20_IOEV_MCU_WU_EN 0x00000040 7745 #define IOC_IOCFG20_IOEV_MCU_WU_EN_BITN 6 7746 #define IOC_IOCFG20_IOEV_MCU_WU_EN_M 0x00000040 7747 #define IOC_IOCFG20_IOEV_MCU_WU_EN_S 6 7748 7749 // Field: [5:0] PORT_ID 7750 // 7751 // Selects usage for DIO20 7752 // Note: This field should not be written other than the times when PORT_ID 7753 // value is specifically required to change. 7754 // ENUMs: 7755 // RFC_SMI_CL_IN RF Core SMI Command Link In 7756 // RFC_SMI_CL_OUT RF Core SMI Command Link Out 7757 // RFC_SMI_DL_IN RF Core SMI Data Link In 7758 // RFC_SMI_DL_OUT RF Core SMI Data Link Out 7759 // RFC_GPI1 RF Core Data In 1 7760 // RFC_GPI0 RF Core Data In 0 7761 // RFC_GPO3 RF Core Data Out 3 7762 // RFC_GPO2 RF Core Data Out 2 7763 // RFC_GPO1 RF Core Data Out 1 7764 // RFC_GPO0 RF Core Data Out 0 7765 // RFC_TRC RF Core Trace 7766 // I2S_MCLK I2S MCLK 7767 // I2S_BCLK I2S BCLK 7768 // I2S_WCLK I2S WCLK 7769 // I2S_AD1 I2S Data 1 7770 // I2S_AD0 I2S Data 0 7771 // SSI1_CLK SSI1 CLK 7772 // SSI1_FSS SSI1 FSS 7773 // SSI1_TX SSI1 TX 7774 // SSI1_RX SSI1 RX 7775 // CPU_SWV CPU SWV 7776 // PORT_EVENT7 PORT EVENT 7 7777 // Can be used as a general 7778 // purpose IO event by selecting it through 7779 // registers in the EVENT module, for example 7780 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 7781 // and so on 7782 // PORT_EVENT6 PORT EVENT 6 7783 // Can be used as a general 7784 // purpose IO event by selecting it through 7785 // registers in the EVENT module, for example 7786 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 7787 // and so on 7788 // PORT_EVENT5 PORT EVENT 5 7789 // Can be used as a general 7790 // purpose IO event by selecting it through 7791 // registers in the EVENT module, for example 7792 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 7793 // and so on 7794 // PORT_EVENT4 PORT EVENT 4 7795 // Can be used as a general 7796 // purpose IO event by selecting it through 7797 // registers in the EVENT module, for example 7798 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 7799 // and so on 7800 // PORT_EVENT3 PORT EVENT 3 7801 // Can be used as a general 7802 // purpose IO event by selecting it through 7803 // registers in the EVENT module, for example 7804 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 7805 // and so on 7806 // PORT_EVENT2 PORT EVENT 2 7807 // Can be used as a general 7808 // purpose IO event by selecting it through 7809 // registers in the EVENT module, for example 7810 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 7811 // and so on 7812 // PORT_EVENT1 PORT EVENT 1 7813 // Can be used as a general 7814 // purpose IO event by selecting it through 7815 // registers in the EVENT module, for example 7816 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 7817 // and so on 7818 // PORT_EVENT0 PORT EVENT 0 7819 // Can be used as a general 7820 // purpose IO event by selecting it through 7821 // registers in the EVENT module, for example 7822 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 7823 // and so on 7824 // UART1_RTS UART1 RTS 7825 // UART1_CTS UART1 CTS 7826 // UART1_TX UART1 TX 7827 // UART1_RX UART1 RX 7828 // UART0_RTS UART0 RTS 7829 // UART0_CTS UART0 CTS 7830 // UART0_TX UART0 TX 7831 // UART0_RX UART0 RX 7832 // I2C_MSSCL I2C Clock 7833 // I2C_MSSDA I2C Data 7834 // SSI0_CLK SSI0 CLK 7835 // SSI0_FSS SSI0 FSS 7836 // SSI0_TX SSI0 TX 7837 // SSI0_RX SSI0 RX 7838 // AUX_IO AUX IO 7839 // AON_CLK32K AON 32 KHz clock (SCLK_LF) 7840 // GPIO General Purpose IO 7841 #define IOC_IOCFG20_PORT_ID_W 6 7842 #define IOC_IOCFG20_PORT_ID_M 0x0000003F 7843 #define IOC_IOCFG20_PORT_ID_S 0 7844 #define IOC_IOCFG20_PORT_ID_RFC_SMI_CL_IN 0x00000038 7845 #define IOC_IOCFG20_PORT_ID_RFC_SMI_CL_OUT 0x00000037 7846 #define IOC_IOCFG20_PORT_ID_RFC_SMI_DL_IN 0x00000036 7847 #define IOC_IOCFG20_PORT_ID_RFC_SMI_DL_OUT 0x00000035 7848 #define IOC_IOCFG20_PORT_ID_RFC_GPI1 0x00000034 7849 #define IOC_IOCFG20_PORT_ID_RFC_GPI0 0x00000033 7850 #define IOC_IOCFG20_PORT_ID_RFC_GPO3 0x00000032 7851 #define IOC_IOCFG20_PORT_ID_RFC_GPO2 0x00000031 7852 #define IOC_IOCFG20_PORT_ID_RFC_GPO1 0x00000030 7853 #define IOC_IOCFG20_PORT_ID_RFC_GPO0 0x0000002F 7854 #define IOC_IOCFG20_PORT_ID_RFC_TRC 0x0000002E 7855 #define IOC_IOCFG20_PORT_ID_I2S_MCLK 0x00000029 7856 #define IOC_IOCFG20_PORT_ID_I2S_BCLK 0x00000028 7857 #define IOC_IOCFG20_PORT_ID_I2S_WCLK 0x00000027 7858 #define IOC_IOCFG20_PORT_ID_I2S_AD1 0x00000026 7859 #define IOC_IOCFG20_PORT_ID_I2S_AD0 0x00000025 7860 #define IOC_IOCFG20_PORT_ID_SSI1_CLK 0x00000024 7861 #define IOC_IOCFG20_PORT_ID_SSI1_FSS 0x00000023 7862 #define IOC_IOCFG20_PORT_ID_SSI1_TX 0x00000022 7863 #define IOC_IOCFG20_PORT_ID_SSI1_RX 0x00000021 7864 #define IOC_IOCFG20_PORT_ID_CPU_SWV 0x00000020 7865 #define IOC_IOCFG20_PORT_ID_PORT_EVENT7 0x0000001E 7866 #define IOC_IOCFG20_PORT_ID_PORT_EVENT6 0x0000001D 7867 #define IOC_IOCFG20_PORT_ID_PORT_EVENT5 0x0000001C 7868 #define IOC_IOCFG20_PORT_ID_PORT_EVENT4 0x0000001B 7869 #define IOC_IOCFG20_PORT_ID_PORT_EVENT3 0x0000001A 7870 #define IOC_IOCFG20_PORT_ID_PORT_EVENT2 0x00000019 7871 #define IOC_IOCFG20_PORT_ID_PORT_EVENT1 0x00000018 7872 #define IOC_IOCFG20_PORT_ID_PORT_EVENT0 0x00000017 7873 #define IOC_IOCFG20_PORT_ID_UART1_RTS 0x00000016 7874 #define IOC_IOCFG20_PORT_ID_UART1_CTS 0x00000015 7875 #define IOC_IOCFG20_PORT_ID_UART1_TX 0x00000014 7876 #define IOC_IOCFG20_PORT_ID_UART1_RX 0x00000013 7877 #define IOC_IOCFG20_PORT_ID_UART0_RTS 0x00000012 7878 #define IOC_IOCFG20_PORT_ID_UART0_CTS 0x00000011 7879 #define IOC_IOCFG20_PORT_ID_UART0_TX 0x00000010 7880 #define IOC_IOCFG20_PORT_ID_UART0_RX 0x0000000F 7881 #define IOC_IOCFG20_PORT_ID_I2C_MSSCL 0x0000000E 7882 #define IOC_IOCFG20_PORT_ID_I2C_MSSDA 0x0000000D 7883 #define IOC_IOCFG20_PORT_ID_SSI0_CLK 0x0000000C 7884 #define IOC_IOCFG20_PORT_ID_SSI0_FSS 0x0000000B 7885 #define IOC_IOCFG20_PORT_ID_SSI0_TX 0x0000000A 7886 #define IOC_IOCFG20_PORT_ID_SSI0_RX 0x00000009 7887 #define IOC_IOCFG20_PORT_ID_AUX_IO 0x00000008 7888 #define IOC_IOCFG20_PORT_ID_AON_CLK32K 0x00000007 7889 #define IOC_IOCFG20_PORT_ID_GPIO 0x00000000 7890 7891 //***************************************************************************** 7892 // 7893 // Register: IOC_O_IOCFG21 7894 // 7895 //***************************************************************************** 7896 // Field: [30] HYST_EN 7897 // 7898 // 0: Input hysteresis disable 7899 // 1: Input hysteresis enable 7900 #define IOC_IOCFG21_HYST_EN 0x40000000 7901 #define IOC_IOCFG21_HYST_EN_BITN 30 7902 #define IOC_IOCFG21_HYST_EN_M 0x40000000 7903 #define IOC_IOCFG21_HYST_EN_S 30 7904 7905 // Field: [29] IE 7906 // 7907 // 0: Input disabled 7908 // 1: Input enabled 7909 // 7910 // Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be 7911 // ignored. 7912 #define IOC_IOCFG21_IE 0x20000000 7913 #define IOC_IOCFG21_IE_BITN 29 7914 #define IOC_IOCFG21_IE_M 0x20000000 7915 #define IOC_IOCFG21_IE_S 29 7916 7917 // Field: [28:27] WU_CFG 7918 // 7919 // If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or 7920 // >0x08: 7921 // 7922 // 00: No wake-up 7923 // 01: No wake-up 7924 // 10: Wakes up from shutdown if this pad is going low. 7925 // 11: Wakes up from shutdown if this pad is going high. 7926 // 7927 // If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, 7928 // this register only sets wakeup enable or not. 7929 // 7930 // 00, 01: Wakeup disabled 7931 // 10, 11: Wakeup enabled 7932 // 7933 // Polarity is controlled from AON registers. 7934 // 7935 // Note:When the MSB is set, the IOC will deactivate the output enable for the 7936 // DIO. 7937 #define IOC_IOCFG21_WU_CFG_W 2 7938 #define IOC_IOCFG21_WU_CFG_M 0x18000000 7939 #define IOC_IOCFG21_WU_CFG_S 27 7940 7941 // Field: [26:24] IOMODE 7942 // 7943 // IO Mode 7944 // Not applicable for IO configured for AON periph. signals and AUX PORT_ID 7945 // 0x01-0x08 7946 // AUX has its own open_source/drain configuration. 7947 // 7948 // 0x2: Reserved. Undefined behavior. 7949 // 0x3: Reserved. Undefined behavior. 7950 // ENUMs: 7951 // OPENSRC_INV Open Source 7952 // Inverted input / output 7953 // OPENSRC Open Source 7954 // Normal input / output 7955 // OPENDR_INV Open Drain 7956 // Inverted input / output 7957 // OPENDR Open Drain, 7958 // Normal input / output 7959 // INV Inverted input / ouput 7960 // NORMAL Normal input / output 7961 #define IOC_IOCFG21_IOMODE_W 3 7962 #define IOC_IOCFG21_IOMODE_M 0x07000000 7963 #define IOC_IOCFG21_IOMODE_S 24 7964 #define IOC_IOCFG21_IOMODE_OPENSRC_INV 0x07000000 7965 #define IOC_IOCFG21_IOMODE_OPENSRC 0x06000000 7966 #define IOC_IOCFG21_IOMODE_OPENDR_INV 0x05000000 7967 #define IOC_IOCFG21_IOMODE_OPENDR 0x04000000 7968 #define IOC_IOCFG21_IOMODE_INV 0x01000000 7969 #define IOC_IOCFG21_IOMODE_NORMAL 0x00000000 7970 7971 // Field: [23] IOEV_AON_PROG2_EN 7972 // 7973 // Event asserted by this IO when edge detection is enabled 7974 // 7975 // 0: Input edge detection does not assert AON_PROG2 event 7976 // 1: Input edge detection asserts AON_PROG2 event 7977 #define IOC_IOCFG21_IOEV_AON_PROG2_EN 0x00800000 7978 #define IOC_IOCFG21_IOEV_AON_PROG2_EN_BITN 23 7979 #define IOC_IOCFG21_IOEV_AON_PROG2_EN_M 0x00800000 7980 #define IOC_IOCFG21_IOEV_AON_PROG2_EN_S 23 7981 7982 // Field: [22] IOEV_AON_PROG1_EN 7983 // 7984 // Event asserted by this IO when edge detection is enabled 7985 // 7986 // 0: Input edge detection does not assert AON_PROG1 event 7987 // 1: Input edge detection asserts AON_PROG1 event 7988 #define IOC_IOCFG21_IOEV_AON_PROG1_EN 0x00400000 7989 #define IOC_IOCFG21_IOEV_AON_PROG1_EN_BITN 22 7990 #define IOC_IOCFG21_IOEV_AON_PROG1_EN_M 0x00400000 7991 #define IOC_IOCFG21_IOEV_AON_PROG1_EN_S 22 7992 7993 // Field: [21] IOEV_AON_PROG0_EN 7994 // 7995 // Event asserted by this IO when edge detection is enabled 7996 // 7997 // 0: Input edge detection does not assert AON_PROG0 event 7998 // 1: Input edge detection asserts AON_PROG0 event 7999 #define IOC_IOCFG21_IOEV_AON_PROG0_EN 0x00200000 8000 #define IOC_IOCFG21_IOEV_AON_PROG0_EN_BITN 21 8001 #define IOC_IOCFG21_IOEV_AON_PROG0_EN_M 0x00200000 8002 #define IOC_IOCFG21_IOEV_AON_PROG0_EN_S 21 8003 8004 // Field: [18] EDGE_IRQ_EN 8005 // 8006 // 0: No interrupt generation 8007 // 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is 8008 // enabled) 8009 #define IOC_IOCFG21_EDGE_IRQ_EN 0x00040000 8010 #define IOC_IOCFG21_EDGE_IRQ_EN_BITN 18 8011 #define IOC_IOCFG21_EDGE_IRQ_EN_M 0x00040000 8012 #define IOC_IOCFG21_EDGE_IRQ_EN_S 18 8013 8014 // Field: [17:16] EDGE_DET 8015 // 8016 // Enable generation of edge detection events on this IO 8017 // ENUMs: 8018 // BOTH Positive and negative edge detection 8019 // POS Positive edge detection 8020 // NEG Negative edge detection 8021 // NONE No edge detection 8022 #define IOC_IOCFG21_EDGE_DET_W 2 8023 #define IOC_IOCFG21_EDGE_DET_M 0x00030000 8024 #define IOC_IOCFG21_EDGE_DET_S 16 8025 #define IOC_IOCFG21_EDGE_DET_BOTH 0x00030000 8026 #define IOC_IOCFG21_EDGE_DET_POS 0x00020000 8027 #define IOC_IOCFG21_EDGE_DET_NEG 0x00010000 8028 #define IOC_IOCFG21_EDGE_DET_NONE 0x00000000 8029 8030 // Field: [14:13] PULL_CTL 8031 // 8032 // Pull control 8033 // ENUMs: 8034 // DIS No pull 8035 // UP Pull up 8036 // DWN Pull down 8037 #define IOC_IOCFG21_PULL_CTL_W 2 8038 #define IOC_IOCFG21_PULL_CTL_M 0x00006000 8039 #define IOC_IOCFG21_PULL_CTL_S 13 8040 #define IOC_IOCFG21_PULL_CTL_DIS 0x00006000 8041 #define IOC_IOCFG21_PULL_CTL_UP 0x00004000 8042 #define IOC_IOCFG21_PULL_CTL_DWN 0x00002000 8043 8044 // Field: [12] SLEW_RED 8045 // 8046 // 0: Normal slew rate 8047 // 1: Enables reduced slew rate in output driver. 8048 #define IOC_IOCFG21_SLEW_RED 0x00001000 8049 #define IOC_IOCFG21_SLEW_RED_BITN 12 8050 #define IOC_IOCFG21_SLEW_RED_M 0x00001000 8051 #define IOC_IOCFG21_SLEW_RED_S 12 8052 8053 // Field: [11:10] IOCURR 8054 // 8055 // Selects IO current mode of this IO. 8056 // ENUMs: 8057 // 4_8MA Extended-Current (EC) mode: Min 8 mA for double 8058 // drive strength IOs (min 4 mA for normal IOs) 8059 // when IOSTR is set to AUTO 8060 // 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set 8061 // to AUTO 8062 // 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set 8063 // to AUTO 8064 #define IOC_IOCFG21_IOCURR_W 2 8065 #define IOC_IOCFG21_IOCURR_M 0x00000C00 8066 #define IOC_IOCFG21_IOCURR_S 10 8067 #define IOC_IOCFG21_IOCURR_4_8MA 0x00000800 8068 #define IOC_IOCFG21_IOCURR_4MA 0x00000400 8069 #define IOC_IOCFG21_IOCURR_2MA 0x00000000 8070 8071 // Field: [9:8] IOSTR 8072 // 8073 // Select source for drive strength control of this IO. 8074 // This setting controls the drive strength of the Low-Current (LC) mode. 8075 // Higher drive strength can be selected in IOCURR 8076 // ENUMs: 8077 // MAX Maximum drive strength, controlled by 8078 // AON_IOC:IOSTRMAX (min 2 mA @1.8V with default 8079 // values) 8080 // MED Medium drive strength, controlled by 8081 // AON_IOC:IOSTRMED (min 2 mA @2.5V with default 8082 // values) 8083 // MIN Minimum drive strength, controlled by 8084 // AON_IOC:IOSTRMIN (min 2 mA @3.3V with default 8085 // values) 8086 // AUTO Automatic drive strength, controlled by AON BATMON 8087 // based on battery voltage. (min 2 mA @VDDS) 8088 #define IOC_IOCFG21_IOSTR_W 2 8089 #define IOC_IOCFG21_IOSTR_M 0x00000300 8090 #define IOC_IOCFG21_IOSTR_S 8 8091 #define IOC_IOCFG21_IOSTR_MAX 0x00000300 8092 #define IOC_IOCFG21_IOSTR_MED 0x00000200 8093 #define IOC_IOCFG21_IOSTR_MIN 0x00000100 8094 #define IOC_IOCFG21_IOSTR_AUTO 0x00000000 8095 8096 // Field: [7] IOEV_RTC_EN 8097 // 8098 // Event asserted by this IO when edge detection is enabled 8099 // 8100 // 0: Input edge detection does not assert RTC event 8101 // 1: Input edge detection asserts RTC event 8102 #define IOC_IOCFG21_IOEV_RTC_EN 0x00000080 8103 #define IOC_IOCFG21_IOEV_RTC_EN_BITN 7 8104 #define IOC_IOCFG21_IOEV_RTC_EN_M 0x00000080 8105 #define IOC_IOCFG21_IOEV_RTC_EN_S 7 8106 8107 // Field: [6] IOEV_MCU_WU_EN 8108 // 8109 // Event asserted by this IO when edge detection is enabled 8110 // 8111 // 0: Input edge detection does not assert MCU_WU event 8112 // 1: Input edge detection asserts MCU_WU event 8113 #define IOC_IOCFG21_IOEV_MCU_WU_EN 0x00000040 8114 #define IOC_IOCFG21_IOEV_MCU_WU_EN_BITN 6 8115 #define IOC_IOCFG21_IOEV_MCU_WU_EN_M 0x00000040 8116 #define IOC_IOCFG21_IOEV_MCU_WU_EN_S 6 8117 8118 // Field: [5:0] PORT_ID 8119 // 8120 // Selects usage for DIO21 8121 // Note: This field should not be written other than the times when PORT_ID 8122 // value is specifically required to change. 8123 // ENUMs: 8124 // RFC_SMI_CL_IN RF Core SMI Command Link In 8125 // RFC_SMI_CL_OUT RF Core SMI Command Link Out 8126 // RFC_SMI_DL_IN RF Core SMI Data Link In 8127 // RFC_SMI_DL_OUT RF Core SMI Data Link Out 8128 // RFC_GPI1 RF Core Data In 1 8129 // RFC_GPI0 RF Core Data In 0 8130 // RFC_GPO3 RF Core Data Out 3 8131 // RFC_GPO2 RF Core Data Out 2 8132 // RFC_GPO1 RF Core Data Out 1 8133 // RFC_GPO0 RF Core Data Out 0 8134 // RFC_TRC RF Core Trace 8135 // I2S_MCLK I2S MCLK 8136 // I2S_BCLK I2S BCLK 8137 // I2S_WCLK I2S WCLK 8138 // I2S_AD1 I2S Data 1 8139 // I2S_AD0 I2S Data 0 8140 // SSI1_CLK SSI1 CLK 8141 // SSI1_FSS SSI1 FSS 8142 // SSI1_TX SSI1 TX 8143 // SSI1_RX SSI1 RX 8144 // CPU_SWV CPU SWV 8145 // PORT_EVENT7 PORT EVENT 7 8146 // Can be used as a general 8147 // purpose IO event by selecting it through 8148 // registers in the EVENT module, for example 8149 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 8150 // and so on 8151 // PORT_EVENT6 PORT EVENT 6 8152 // Can be used as a general 8153 // purpose IO event by selecting it through 8154 // registers in the EVENT module, for example 8155 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 8156 // and so on 8157 // PORT_EVENT5 PORT EVENT 5 8158 // Can be used as a general 8159 // purpose IO event by selecting it through 8160 // registers in the EVENT module, for example 8161 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 8162 // and so on 8163 // PORT_EVENT4 PORT EVENT 4 8164 // Can be used as a general 8165 // purpose IO event by selecting it through 8166 // registers in the EVENT module, for example 8167 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 8168 // and so on 8169 // PORT_EVENT3 PORT EVENT 3 8170 // Can be used as a general 8171 // purpose IO event by selecting it through 8172 // registers in the EVENT module, for example 8173 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 8174 // and so on 8175 // PORT_EVENT2 PORT EVENT 2 8176 // Can be used as a general 8177 // purpose IO event by selecting it through 8178 // registers in the EVENT module, for example 8179 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 8180 // and so on 8181 // PORT_EVENT1 PORT EVENT 1 8182 // Can be used as a general 8183 // purpose IO event by selecting it through 8184 // registers in the EVENT module, for example 8185 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 8186 // and so on 8187 // PORT_EVENT0 PORT EVENT 0 8188 // Can be used as a general 8189 // purpose IO event by selecting it through 8190 // registers in the EVENT module, for example 8191 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 8192 // and so on 8193 // UART1_RTS UART1 RTS 8194 // UART1_CTS UART1 CTS 8195 // UART1_TX UART1 TX 8196 // UART1_RX UART1 RX 8197 // UART0_RTS UART0 RTS 8198 // UART0_CTS UART0 CTS 8199 // UART0_TX UART0 TX 8200 // UART0_RX UART0 RX 8201 // I2C_MSSCL I2C Clock 8202 // I2C_MSSDA I2C Data 8203 // SSI0_CLK SSI0 CLK 8204 // SSI0_FSS SSI0 FSS 8205 // SSI0_TX SSI0 TX 8206 // SSI0_RX SSI0 RX 8207 // AUX_IO AUX IO 8208 // AON_CLK32K AON 32 KHz clock (SCLK_LF) 8209 // GPIO General Purpose IO 8210 #define IOC_IOCFG21_PORT_ID_W 6 8211 #define IOC_IOCFG21_PORT_ID_M 0x0000003F 8212 #define IOC_IOCFG21_PORT_ID_S 0 8213 #define IOC_IOCFG21_PORT_ID_RFC_SMI_CL_IN 0x00000038 8214 #define IOC_IOCFG21_PORT_ID_RFC_SMI_CL_OUT 0x00000037 8215 #define IOC_IOCFG21_PORT_ID_RFC_SMI_DL_IN 0x00000036 8216 #define IOC_IOCFG21_PORT_ID_RFC_SMI_DL_OUT 0x00000035 8217 #define IOC_IOCFG21_PORT_ID_RFC_GPI1 0x00000034 8218 #define IOC_IOCFG21_PORT_ID_RFC_GPI0 0x00000033 8219 #define IOC_IOCFG21_PORT_ID_RFC_GPO3 0x00000032 8220 #define IOC_IOCFG21_PORT_ID_RFC_GPO2 0x00000031 8221 #define IOC_IOCFG21_PORT_ID_RFC_GPO1 0x00000030 8222 #define IOC_IOCFG21_PORT_ID_RFC_GPO0 0x0000002F 8223 #define IOC_IOCFG21_PORT_ID_RFC_TRC 0x0000002E 8224 #define IOC_IOCFG21_PORT_ID_I2S_MCLK 0x00000029 8225 #define IOC_IOCFG21_PORT_ID_I2S_BCLK 0x00000028 8226 #define IOC_IOCFG21_PORT_ID_I2S_WCLK 0x00000027 8227 #define IOC_IOCFG21_PORT_ID_I2S_AD1 0x00000026 8228 #define IOC_IOCFG21_PORT_ID_I2S_AD0 0x00000025 8229 #define IOC_IOCFG21_PORT_ID_SSI1_CLK 0x00000024 8230 #define IOC_IOCFG21_PORT_ID_SSI1_FSS 0x00000023 8231 #define IOC_IOCFG21_PORT_ID_SSI1_TX 0x00000022 8232 #define IOC_IOCFG21_PORT_ID_SSI1_RX 0x00000021 8233 #define IOC_IOCFG21_PORT_ID_CPU_SWV 0x00000020 8234 #define IOC_IOCFG21_PORT_ID_PORT_EVENT7 0x0000001E 8235 #define IOC_IOCFG21_PORT_ID_PORT_EVENT6 0x0000001D 8236 #define IOC_IOCFG21_PORT_ID_PORT_EVENT5 0x0000001C 8237 #define IOC_IOCFG21_PORT_ID_PORT_EVENT4 0x0000001B 8238 #define IOC_IOCFG21_PORT_ID_PORT_EVENT3 0x0000001A 8239 #define IOC_IOCFG21_PORT_ID_PORT_EVENT2 0x00000019 8240 #define IOC_IOCFG21_PORT_ID_PORT_EVENT1 0x00000018 8241 #define IOC_IOCFG21_PORT_ID_PORT_EVENT0 0x00000017 8242 #define IOC_IOCFG21_PORT_ID_UART1_RTS 0x00000016 8243 #define IOC_IOCFG21_PORT_ID_UART1_CTS 0x00000015 8244 #define IOC_IOCFG21_PORT_ID_UART1_TX 0x00000014 8245 #define IOC_IOCFG21_PORT_ID_UART1_RX 0x00000013 8246 #define IOC_IOCFG21_PORT_ID_UART0_RTS 0x00000012 8247 #define IOC_IOCFG21_PORT_ID_UART0_CTS 0x00000011 8248 #define IOC_IOCFG21_PORT_ID_UART0_TX 0x00000010 8249 #define IOC_IOCFG21_PORT_ID_UART0_RX 0x0000000F 8250 #define IOC_IOCFG21_PORT_ID_I2C_MSSCL 0x0000000E 8251 #define IOC_IOCFG21_PORT_ID_I2C_MSSDA 0x0000000D 8252 #define IOC_IOCFG21_PORT_ID_SSI0_CLK 0x0000000C 8253 #define IOC_IOCFG21_PORT_ID_SSI0_FSS 0x0000000B 8254 #define IOC_IOCFG21_PORT_ID_SSI0_TX 0x0000000A 8255 #define IOC_IOCFG21_PORT_ID_SSI0_RX 0x00000009 8256 #define IOC_IOCFG21_PORT_ID_AUX_IO 0x00000008 8257 #define IOC_IOCFG21_PORT_ID_AON_CLK32K 0x00000007 8258 #define IOC_IOCFG21_PORT_ID_GPIO 0x00000000 8259 8260 //***************************************************************************** 8261 // 8262 // Register: IOC_O_IOCFG22 8263 // 8264 //***************************************************************************** 8265 // Field: [30] HYST_EN 8266 // 8267 // 0: Input hysteresis disable 8268 // 1: Input hysteresis enable 8269 #define IOC_IOCFG22_HYST_EN 0x40000000 8270 #define IOC_IOCFG22_HYST_EN_BITN 30 8271 #define IOC_IOCFG22_HYST_EN_M 0x40000000 8272 #define IOC_IOCFG22_HYST_EN_S 30 8273 8274 // Field: [29] IE 8275 // 8276 // 0: Input disabled 8277 // 1: Input enabled 8278 // 8279 // Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be 8280 // ignored. 8281 #define IOC_IOCFG22_IE 0x20000000 8282 #define IOC_IOCFG22_IE_BITN 29 8283 #define IOC_IOCFG22_IE_M 0x20000000 8284 #define IOC_IOCFG22_IE_S 29 8285 8286 // Field: [28:27] WU_CFG 8287 // 8288 // If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or 8289 // >0x08: 8290 // 8291 // 00: No wake-up 8292 // 01: No wake-up 8293 // 10: Wakes up from shutdown if this pad is going low. 8294 // 11: Wakes up from shutdown if this pad is going high. 8295 // 8296 // If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, 8297 // this register only sets wakeup enable or not. 8298 // 8299 // 00, 01: Wakeup disabled 8300 // 10, 11: Wakeup enabled 8301 // 8302 // Polarity is controlled from AON registers. 8303 // 8304 // Note:When the MSB is set, the IOC will deactivate the output enable for the 8305 // DIO. 8306 #define IOC_IOCFG22_WU_CFG_W 2 8307 #define IOC_IOCFG22_WU_CFG_M 0x18000000 8308 #define IOC_IOCFG22_WU_CFG_S 27 8309 8310 // Field: [26:24] IOMODE 8311 // 8312 // IO Mode 8313 // Not applicable for IO configured for AON periph. signals and AUX PORT_ID 8314 // 0x01-0x08 8315 // AUX has its own open_source/drain configuration. 8316 // 8317 // 0x2: Reserved. Undefined behavior. 8318 // 0x3: Reserved. Undefined behavior. 8319 // ENUMs: 8320 // OPENSRC_INV Open Source 8321 // Inverted input / output 8322 // OPENSRC Open Source 8323 // Normal input / output 8324 // OPENDR_INV Open Drain 8325 // Inverted input / output 8326 // OPENDR Open Drain, 8327 // Normal input / output 8328 // INV Inverted input / ouput 8329 // NORMAL Normal input / output 8330 #define IOC_IOCFG22_IOMODE_W 3 8331 #define IOC_IOCFG22_IOMODE_M 0x07000000 8332 #define IOC_IOCFG22_IOMODE_S 24 8333 #define IOC_IOCFG22_IOMODE_OPENSRC_INV 0x07000000 8334 #define IOC_IOCFG22_IOMODE_OPENSRC 0x06000000 8335 #define IOC_IOCFG22_IOMODE_OPENDR_INV 0x05000000 8336 #define IOC_IOCFG22_IOMODE_OPENDR 0x04000000 8337 #define IOC_IOCFG22_IOMODE_INV 0x01000000 8338 #define IOC_IOCFG22_IOMODE_NORMAL 0x00000000 8339 8340 // Field: [23] IOEV_AON_PROG2_EN 8341 // 8342 // Event asserted by this IO when edge detection is enabled 8343 // 8344 // 0: Input edge detection does not assert AON_PROG2 event 8345 // 1: Input edge detection asserts AON_PROG2 event 8346 #define IOC_IOCFG22_IOEV_AON_PROG2_EN 0x00800000 8347 #define IOC_IOCFG22_IOEV_AON_PROG2_EN_BITN 23 8348 #define IOC_IOCFG22_IOEV_AON_PROG2_EN_M 0x00800000 8349 #define IOC_IOCFG22_IOEV_AON_PROG2_EN_S 23 8350 8351 // Field: [22] IOEV_AON_PROG1_EN 8352 // 8353 // Event asserted by this IO when edge detection is enabled 8354 // 8355 // 0: Input edge detection does not assert AON_PROG1 event 8356 // 1: Input edge detection asserts AON_PROG1 event 8357 #define IOC_IOCFG22_IOEV_AON_PROG1_EN 0x00400000 8358 #define IOC_IOCFG22_IOEV_AON_PROG1_EN_BITN 22 8359 #define IOC_IOCFG22_IOEV_AON_PROG1_EN_M 0x00400000 8360 #define IOC_IOCFG22_IOEV_AON_PROG1_EN_S 22 8361 8362 // Field: [21] IOEV_AON_PROG0_EN 8363 // 8364 // Event asserted by this IO when edge detection is enabled 8365 // 8366 // 0: Input edge detection does not assert AON_PROG0 event 8367 // 1: Input edge detection asserts AON_PROG0 event 8368 #define IOC_IOCFG22_IOEV_AON_PROG0_EN 0x00200000 8369 #define IOC_IOCFG22_IOEV_AON_PROG0_EN_BITN 21 8370 #define IOC_IOCFG22_IOEV_AON_PROG0_EN_M 0x00200000 8371 #define IOC_IOCFG22_IOEV_AON_PROG0_EN_S 21 8372 8373 // Field: [18] EDGE_IRQ_EN 8374 // 8375 // 0: No interrupt generation 8376 // 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is 8377 // enabled) 8378 #define IOC_IOCFG22_EDGE_IRQ_EN 0x00040000 8379 #define IOC_IOCFG22_EDGE_IRQ_EN_BITN 18 8380 #define IOC_IOCFG22_EDGE_IRQ_EN_M 0x00040000 8381 #define IOC_IOCFG22_EDGE_IRQ_EN_S 18 8382 8383 // Field: [17:16] EDGE_DET 8384 // 8385 // Enable generation of edge detection events on this IO 8386 // ENUMs: 8387 // BOTH Positive and negative edge detection 8388 // POS Positive edge detection 8389 // NEG Negative edge detection 8390 // NONE No edge detection 8391 #define IOC_IOCFG22_EDGE_DET_W 2 8392 #define IOC_IOCFG22_EDGE_DET_M 0x00030000 8393 #define IOC_IOCFG22_EDGE_DET_S 16 8394 #define IOC_IOCFG22_EDGE_DET_BOTH 0x00030000 8395 #define IOC_IOCFG22_EDGE_DET_POS 0x00020000 8396 #define IOC_IOCFG22_EDGE_DET_NEG 0x00010000 8397 #define IOC_IOCFG22_EDGE_DET_NONE 0x00000000 8398 8399 // Field: [14:13] PULL_CTL 8400 // 8401 // Pull control 8402 // ENUMs: 8403 // DIS No pull 8404 // UP Pull up 8405 // DWN Pull down 8406 #define IOC_IOCFG22_PULL_CTL_W 2 8407 #define IOC_IOCFG22_PULL_CTL_M 0x00006000 8408 #define IOC_IOCFG22_PULL_CTL_S 13 8409 #define IOC_IOCFG22_PULL_CTL_DIS 0x00006000 8410 #define IOC_IOCFG22_PULL_CTL_UP 0x00004000 8411 #define IOC_IOCFG22_PULL_CTL_DWN 0x00002000 8412 8413 // Field: [12] SLEW_RED 8414 // 8415 // 0: Normal slew rate 8416 // 1: Enables reduced slew rate in output driver. 8417 #define IOC_IOCFG22_SLEW_RED 0x00001000 8418 #define IOC_IOCFG22_SLEW_RED_BITN 12 8419 #define IOC_IOCFG22_SLEW_RED_M 0x00001000 8420 #define IOC_IOCFG22_SLEW_RED_S 12 8421 8422 // Field: [11:10] IOCURR 8423 // 8424 // Selects IO current mode of this IO. 8425 // ENUMs: 8426 // 4_8MA Extended-Current (EC) mode: Min 8 mA for double 8427 // drive strength IOs (min 4 mA for normal IOs) 8428 // when IOSTR is set to AUTO 8429 // 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set 8430 // to AUTO 8431 // 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set 8432 // to AUTO 8433 #define IOC_IOCFG22_IOCURR_W 2 8434 #define IOC_IOCFG22_IOCURR_M 0x00000C00 8435 #define IOC_IOCFG22_IOCURR_S 10 8436 #define IOC_IOCFG22_IOCURR_4_8MA 0x00000800 8437 #define IOC_IOCFG22_IOCURR_4MA 0x00000400 8438 #define IOC_IOCFG22_IOCURR_2MA 0x00000000 8439 8440 // Field: [9:8] IOSTR 8441 // 8442 // Select source for drive strength control of this IO. 8443 // This setting controls the drive strength of the Low-Current (LC) mode. 8444 // Higher drive strength can be selected in IOCURR 8445 // ENUMs: 8446 // MAX Maximum drive strength, controlled by 8447 // AON_IOC:IOSTRMAX (min 2 mA @1.8V with default 8448 // values) 8449 // MED Medium drive strength, controlled by 8450 // AON_IOC:IOSTRMED (min 2 mA @2.5V with default 8451 // values) 8452 // MIN Minimum drive strength, controlled by 8453 // AON_IOC:IOSTRMIN (min 2 mA @3.3V with default 8454 // values) 8455 // AUTO Automatic drive strength, controlled by AON BATMON 8456 // based on battery voltage. (min 2 mA @VDDS) 8457 #define IOC_IOCFG22_IOSTR_W 2 8458 #define IOC_IOCFG22_IOSTR_M 0x00000300 8459 #define IOC_IOCFG22_IOSTR_S 8 8460 #define IOC_IOCFG22_IOSTR_MAX 0x00000300 8461 #define IOC_IOCFG22_IOSTR_MED 0x00000200 8462 #define IOC_IOCFG22_IOSTR_MIN 0x00000100 8463 #define IOC_IOCFG22_IOSTR_AUTO 0x00000000 8464 8465 // Field: [7] IOEV_RTC_EN 8466 // 8467 // Event asserted by this IO when edge detection is enabled 8468 // 8469 // 0: Input edge detection does not assert RTC event 8470 // 1: Input edge detection asserts RTC event 8471 #define IOC_IOCFG22_IOEV_RTC_EN 0x00000080 8472 #define IOC_IOCFG22_IOEV_RTC_EN_BITN 7 8473 #define IOC_IOCFG22_IOEV_RTC_EN_M 0x00000080 8474 #define IOC_IOCFG22_IOEV_RTC_EN_S 7 8475 8476 // Field: [6] IOEV_MCU_WU_EN 8477 // 8478 // Event asserted by this IO when edge detection is enabled 8479 // 8480 // 0: Input edge detection does not assert MCU_WU event 8481 // 1: Input edge detection asserts MCU_WU event 8482 #define IOC_IOCFG22_IOEV_MCU_WU_EN 0x00000040 8483 #define IOC_IOCFG22_IOEV_MCU_WU_EN_BITN 6 8484 #define IOC_IOCFG22_IOEV_MCU_WU_EN_M 0x00000040 8485 #define IOC_IOCFG22_IOEV_MCU_WU_EN_S 6 8486 8487 // Field: [5:0] PORT_ID 8488 // 8489 // Selects usage for DIO22 8490 // Note: This field should not be written other than the times when PORT_ID 8491 // value is specifically required to change. 8492 // ENUMs: 8493 // RFC_SMI_CL_IN RF Core SMI Command Link In 8494 // RFC_SMI_CL_OUT RF Core SMI Command Link Out 8495 // RFC_SMI_DL_IN RF Core SMI Data Link In 8496 // RFC_SMI_DL_OUT RF Core SMI Data Link Out 8497 // RFC_GPI1 RF Core Data In 1 8498 // RFC_GPI0 RF Core Data In 0 8499 // RFC_GPO3 RF Core Data Out 3 8500 // RFC_GPO2 RF Core Data Out 2 8501 // RFC_GPO1 RF Core Data Out 1 8502 // RFC_GPO0 RF Core Data Out 0 8503 // RFC_TRC RF Core Trace 8504 // I2S_MCLK I2S MCLK 8505 // I2S_BCLK I2S BCLK 8506 // I2S_WCLK I2S WCLK 8507 // I2S_AD1 I2S Data 1 8508 // I2S_AD0 I2S Data 0 8509 // SSI1_CLK SSI1 CLK 8510 // SSI1_FSS SSI1 FSS 8511 // SSI1_TX SSI1 TX 8512 // SSI1_RX SSI1 RX 8513 // CPU_SWV CPU SWV 8514 // PORT_EVENT7 PORT EVENT 7 8515 // Can be used as a general 8516 // purpose IO event by selecting it through 8517 // registers in the EVENT module, for example 8518 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 8519 // and so on 8520 // PORT_EVENT6 PORT EVENT 6 8521 // Can be used as a general 8522 // purpose IO event by selecting it through 8523 // registers in the EVENT module, for example 8524 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 8525 // and so on 8526 // PORT_EVENT5 PORT EVENT 5 8527 // Can be used as a general 8528 // purpose IO event by selecting it through 8529 // registers in the EVENT module, for example 8530 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 8531 // and so on 8532 // PORT_EVENT4 PORT EVENT 4 8533 // Can be used as a general 8534 // purpose IO event by selecting it through 8535 // registers in the EVENT module, for example 8536 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 8537 // and so on 8538 // PORT_EVENT3 PORT EVENT 3 8539 // Can be used as a general 8540 // purpose IO event by selecting it through 8541 // registers in the EVENT module, for example 8542 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 8543 // and so on 8544 // PORT_EVENT2 PORT EVENT 2 8545 // Can be used as a general 8546 // purpose IO event by selecting it through 8547 // registers in the EVENT module, for example 8548 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 8549 // and so on 8550 // PORT_EVENT1 PORT EVENT 1 8551 // Can be used as a general 8552 // purpose IO event by selecting it through 8553 // registers in the EVENT module, for example 8554 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 8555 // and so on 8556 // PORT_EVENT0 PORT EVENT 0 8557 // Can be used as a general 8558 // purpose IO event by selecting it through 8559 // registers in the EVENT module, for example 8560 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 8561 // and so on 8562 // UART1_RTS UART1 RTS 8563 // UART1_CTS UART1 CTS 8564 // UART1_TX UART1 TX 8565 // UART1_RX UART1 RX 8566 // UART0_RTS UART0 RTS 8567 // UART0_CTS UART0 CTS 8568 // UART0_TX UART0 TX 8569 // UART0_RX UART0 RX 8570 // I2C_MSSCL I2C Clock 8571 // I2C_MSSDA I2C Data 8572 // SSI0_CLK SSI0 CLK 8573 // SSI0_FSS SSI0 FSS 8574 // SSI0_TX SSI0 TX 8575 // SSI0_RX SSI0 RX 8576 // AUX_IO AUX IO 8577 // AON_CLK32K AON 32 KHz clock (SCLK_LF) 8578 // GPIO General Purpose IO 8579 #define IOC_IOCFG22_PORT_ID_W 6 8580 #define IOC_IOCFG22_PORT_ID_M 0x0000003F 8581 #define IOC_IOCFG22_PORT_ID_S 0 8582 #define IOC_IOCFG22_PORT_ID_RFC_SMI_CL_IN 0x00000038 8583 #define IOC_IOCFG22_PORT_ID_RFC_SMI_CL_OUT 0x00000037 8584 #define IOC_IOCFG22_PORT_ID_RFC_SMI_DL_IN 0x00000036 8585 #define IOC_IOCFG22_PORT_ID_RFC_SMI_DL_OUT 0x00000035 8586 #define IOC_IOCFG22_PORT_ID_RFC_GPI1 0x00000034 8587 #define IOC_IOCFG22_PORT_ID_RFC_GPI0 0x00000033 8588 #define IOC_IOCFG22_PORT_ID_RFC_GPO3 0x00000032 8589 #define IOC_IOCFG22_PORT_ID_RFC_GPO2 0x00000031 8590 #define IOC_IOCFG22_PORT_ID_RFC_GPO1 0x00000030 8591 #define IOC_IOCFG22_PORT_ID_RFC_GPO0 0x0000002F 8592 #define IOC_IOCFG22_PORT_ID_RFC_TRC 0x0000002E 8593 #define IOC_IOCFG22_PORT_ID_I2S_MCLK 0x00000029 8594 #define IOC_IOCFG22_PORT_ID_I2S_BCLK 0x00000028 8595 #define IOC_IOCFG22_PORT_ID_I2S_WCLK 0x00000027 8596 #define IOC_IOCFG22_PORT_ID_I2S_AD1 0x00000026 8597 #define IOC_IOCFG22_PORT_ID_I2S_AD0 0x00000025 8598 #define IOC_IOCFG22_PORT_ID_SSI1_CLK 0x00000024 8599 #define IOC_IOCFG22_PORT_ID_SSI1_FSS 0x00000023 8600 #define IOC_IOCFG22_PORT_ID_SSI1_TX 0x00000022 8601 #define IOC_IOCFG22_PORT_ID_SSI1_RX 0x00000021 8602 #define IOC_IOCFG22_PORT_ID_CPU_SWV 0x00000020 8603 #define IOC_IOCFG22_PORT_ID_PORT_EVENT7 0x0000001E 8604 #define IOC_IOCFG22_PORT_ID_PORT_EVENT6 0x0000001D 8605 #define IOC_IOCFG22_PORT_ID_PORT_EVENT5 0x0000001C 8606 #define IOC_IOCFG22_PORT_ID_PORT_EVENT4 0x0000001B 8607 #define IOC_IOCFG22_PORT_ID_PORT_EVENT3 0x0000001A 8608 #define IOC_IOCFG22_PORT_ID_PORT_EVENT2 0x00000019 8609 #define IOC_IOCFG22_PORT_ID_PORT_EVENT1 0x00000018 8610 #define IOC_IOCFG22_PORT_ID_PORT_EVENT0 0x00000017 8611 #define IOC_IOCFG22_PORT_ID_UART1_RTS 0x00000016 8612 #define IOC_IOCFG22_PORT_ID_UART1_CTS 0x00000015 8613 #define IOC_IOCFG22_PORT_ID_UART1_TX 0x00000014 8614 #define IOC_IOCFG22_PORT_ID_UART1_RX 0x00000013 8615 #define IOC_IOCFG22_PORT_ID_UART0_RTS 0x00000012 8616 #define IOC_IOCFG22_PORT_ID_UART0_CTS 0x00000011 8617 #define IOC_IOCFG22_PORT_ID_UART0_TX 0x00000010 8618 #define IOC_IOCFG22_PORT_ID_UART0_RX 0x0000000F 8619 #define IOC_IOCFG22_PORT_ID_I2C_MSSCL 0x0000000E 8620 #define IOC_IOCFG22_PORT_ID_I2C_MSSDA 0x0000000D 8621 #define IOC_IOCFG22_PORT_ID_SSI0_CLK 0x0000000C 8622 #define IOC_IOCFG22_PORT_ID_SSI0_FSS 0x0000000B 8623 #define IOC_IOCFG22_PORT_ID_SSI0_TX 0x0000000A 8624 #define IOC_IOCFG22_PORT_ID_SSI0_RX 0x00000009 8625 #define IOC_IOCFG22_PORT_ID_AUX_IO 0x00000008 8626 #define IOC_IOCFG22_PORT_ID_AON_CLK32K 0x00000007 8627 #define IOC_IOCFG22_PORT_ID_GPIO 0x00000000 8628 8629 //***************************************************************************** 8630 // 8631 // Register: IOC_O_IOCFG23 8632 // 8633 //***************************************************************************** 8634 // Field: [30] HYST_EN 8635 // 8636 // 0: Input hysteresis disable 8637 // 1: Input hysteresis enable 8638 #define IOC_IOCFG23_HYST_EN 0x40000000 8639 #define IOC_IOCFG23_HYST_EN_BITN 30 8640 #define IOC_IOCFG23_HYST_EN_M 0x40000000 8641 #define IOC_IOCFG23_HYST_EN_S 30 8642 8643 // Field: [29] IE 8644 // 8645 // 0: Input disabled 8646 // 1: Input enabled 8647 // 8648 // Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be 8649 // ignored. 8650 #define IOC_IOCFG23_IE 0x20000000 8651 #define IOC_IOCFG23_IE_BITN 29 8652 #define IOC_IOCFG23_IE_M 0x20000000 8653 #define IOC_IOCFG23_IE_S 29 8654 8655 // Field: [28:27] WU_CFG 8656 // 8657 // If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or 8658 // >0x08: 8659 // 8660 // 00: No wake-up 8661 // 01: No wake-up 8662 // 10: Wakes up from shutdown if this pad is going low. 8663 // 11: Wakes up from shutdown if this pad is going high. 8664 // 8665 // If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, 8666 // this register only sets wakeup enable or not. 8667 // 8668 // 00, 01: Wakeup disabled 8669 // 10, 11: Wakeup enabled 8670 // 8671 // Polarity is controlled from AON registers. 8672 // 8673 // Note:When the MSB is set, the IOC will deactivate the output enable for the 8674 // DIO. 8675 #define IOC_IOCFG23_WU_CFG_W 2 8676 #define IOC_IOCFG23_WU_CFG_M 0x18000000 8677 #define IOC_IOCFG23_WU_CFG_S 27 8678 8679 // Field: [26:24] IOMODE 8680 // 8681 // IO Mode 8682 // Not applicable for IO configured for AON periph. signals and AUX PORT_ID 8683 // 0x01-0x08 8684 // AUX has its own open_source/drain configuration. 8685 // 8686 // 0x2: Reserved. Undefined behavior. 8687 // 0x3: Reserved. Undefined behavior. 8688 // ENUMs: 8689 // OPENSRC_INV Open Source 8690 // Inverted input / output 8691 // OPENSRC Open Source 8692 // Normal input / output 8693 // OPENDR_INV Open Drain 8694 // Inverted input / output 8695 // OPENDR Open Drain, 8696 // Normal input / output 8697 // INV Inverted input / ouput 8698 // NORMAL Normal input / output 8699 #define IOC_IOCFG23_IOMODE_W 3 8700 #define IOC_IOCFG23_IOMODE_M 0x07000000 8701 #define IOC_IOCFG23_IOMODE_S 24 8702 #define IOC_IOCFG23_IOMODE_OPENSRC_INV 0x07000000 8703 #define IOC_IOCFG23_IOMODE_OPENSRC 0x06000000 8704 #define IOC_IOCFG23_IOMODE_OPENDR_INV 0x05000000 8705 #define IOC_IOCFG23_IOMODE_OPENDR 0x04000000 8706 #define IOC_IOCFG23_IOMODE_INV 0x01000000 8707 #define IOC_IOCFG23_IOMODE_NORMAL 0x00000000 8708 8709 // Field: [23] IOEV_AON_PROG2_EN 8710 // 8711 // Event asserted by this IO when edge detection is enabled 8712 // 8713 // 0: Input edge detection does not assert AON_PROG2 event 8714 // 1: Input edge detection asserts AON_PROG2 event 8715 #define IOC_IOCFG23_IOEV_AON_PROG2_EN 0x00800000 8716 #define IOC_IOCFG23_IOEV_AON_PROG2_EN_BITN 23 8717 #define IOC_IOCFG23_IOEV_AON_PROG2_EN_M 0x00800000 8718 #define IOC_IOCFG23_IOEV_AON_PROG2_EN_S 23 8719 8720 // Field: [22] IOEV_AON_PROG1_EN 8721 // 8722 // Event asserted by this IO when edge detection is enabled 8723 // 8724 // 0: Input edge detection does not assert AON_PROG1 event 8725 // 1: Input edge detection asserts AON_PROG1 event 8726 #define IOC_IOCFG23_IOEV_AON_PROG1_EN 0x00400000 8727 #define IOC_IOCFG23_IOEV_AON_PROG1_EN_BITN 22 8728 #define IOC_IOCFG23_IOEV_AON_PROG1_EN_M 0x00400000 8729 #define IOC_IOCFG23_IOEV_AON_PROG1_EN_S 22 8730 8731 // Field: [21] IOEV_AON_PROG0_EN 8732 // 8733 // Event asserted by this IO when edge detection is enabled 8734 // 8735 // 0: Input edge detection does not assert AON_PROG0 event 8736 // 1: Input edge detection asserts AON_PROG0 event 8737 #define IOC_IOCFG23_IOEV_AON_PROG0_EN 0x00200000 8738 #define IOC_IOCFG23_IOEV_AON_PROG0_EN_BITN 21 8739 #define IOC_IOCFG23_IOEV_AON_PROG0_EN_M 0x00200000 8740 #define IOC_IOCFG23_IOEV_AON_PROG0_EN_S 21 8741 8742 // Field: [18] EDGE_IRQ_EN 8743 // 8744 // 0: No interrupt generation 8745 // 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is 8746 // enabled) 8747 #define IOC_IOCFG23_EDGE_IRQ_EN 0x00040000 8748 #define IOC_IOCFG23_EDGE_IRQ_EN_BITN 18 8749 #define IOC_IOCFG23_EDGE_IRQ_EN_M 0x00040000 8750 #define IOC_IOCFG23_EDGE_IRQ_EN_S 18 8751 8752 // Field: [17:16] EDGE_DET 8753 // 8754 // Enable generation of edge detection events on this IO 8755 // ENUMs: 8756 // BOTH Positive and negative edge detection 8757 // POS Positive edge detection 8758 // NEG Negative edge detection 8759 // NONE No edge detection 8760 #define IOC_IOCFG23_EDGE_DET_W 2 8761 #define IOC_IOCFG23_EDGE_DET_M 0x00030000 8762 #define IOC_IOCFG23_EDGE_DET_S 16 8763 #define IOC_IOCFG23_EDGE_DET_BOTH 0x00030000 8764 #define IOC_IOCFG23_EDGE_DET_POS 0x00020000 8765 #define IOC_IOCFG23_EDGE_DET_NEG 0x00010000 8766 #define IOC_IOCFG23_EDGE_DET_NONE 0x00000000 8767 8768 // Field: [14:13] PULL_CTL 8769 // 8770 // Pull control 8771 // ENUMs: 8772 // DIS No pull 8773 // UP Pull up 8774 // DWN Pull down 8775 #define IOC_IOCFG23_PULL_CTL_W 2 8776 #define IOC_IOCFG23_PULL_CTL_M 0x00006000 8777 #define IOC_IOCFG23_PULL_CTL_S 13 8778 #define IOC_IOCFG23_PULL_CTL_DIS 0x00006000 8779 #define IOC_IOCFG23_PULL_CTL_UP 0x00004000 8780 #define IOC_IOCFG23_PULL_CTL_DWN 0x00002000 8781 8782 // Field: [12] SLEW_RED 8783 // 8784 // 0: Normal slew rate 8785 // 1: Enables reduced slew rate in output driver. 8786 #define IOC_IOCFG23_SLEW_RED 0x00001000 8787 #define IOC_IOCFG23_SLEW_RED_BITN 12 8788 #define IOC_IOCFG23_SLEW_RED_M 0x00001000 8789 #define IOC_IOCFG23_SLEW_RED_S 12 8790 8791 // Field: [11:10] IOCURR 8792 // 8793 // Selects IO current mode of this IO. 8794 // ENUMs: 8795 // 4_8MA Extended-Current (EC) mode: Min 8 mA for double 8796 // drive strength IOs (min 4 mA for normal IOs) 8797 // when IOSTR is set to AUTO 8798 // 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set 8799 // to AUTO 8800 // 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set 8801 // to AUTO 8802 #define IOC_IOCFG23_IOCURR_W 2 8803 #define IOC_IOCFG23_IOCURR_M 0x00000C00 8804 #define IOC_IOCFG23_IOCURR_S 10 8805 #define IOC_IOCFG23_IOCURR_4_8MA 0x00000800 8806 #define IOC_IOCFG23_IOCURR_4MA 0x00000400 8807 #define IOC_IOCFG23_IOCURR_2MA 0x00000000 8808 8809 // Field: [9:8] IOSTR 8810 // 8811 // Select source for drive strength control of this IO. 8812 // This setting controls the drive strength of the Low-Current (LC) mode. 8813 // Higher drive strength can be selected in IOCURR 8814 // ENUMs: 8815 // MAX Maximum drive strength, controlled by 8816 // AON_IOC:IOSTRMAX (min 2 mA @1.8V with default 8817 // values) 8818 // MED Medium drive strength, controlled by 8819 // AON_IOC:IOSTRMED (min 2 mA @2.5V with default 8820 // values) 8821 // MIN Minimum drive strength, controlled by 8822 // AON_IOC:IOSTRMIN (min 2 mA @3.3V with default 8823 // values) 8824 // AUTO Automatic drive strength, controlled by AON BATMON 8825 // based on battery voltage. (min 2 mA @VDDS) 8826 #define IOC_IOCFG23_IOSTR_W 2 8827 #define IOC_IOCFG23_IOSTR_M 0x00000300 8828 #define IOC_IOCFG23_IOSTR_S 8 8829 #define IOC_IOCFG23_IOSTR_MAX 0x00000300 8830 #define IOC_IOCFG23_IOSTR_MED 0x00000200 8831 #define IOC_IOCFG23_IOSTR_MIN 0x00000100 8832 #define IOC_IOCFG23_IOSTR_AUTO 0x00000000 8833 8834 // Field: [7] IOEV_RTC_EN 8835 // 8836 // Event asserted by this IO when edge detection is enabled 8837 // 8838 // 0: Input edge detection does not assert RTC event 8839 // 1: Input edge detection asserts RTC event 8840 #define IOC_IOCFG23_IOEV_RTC_EN 0x00000080 8841 #define IOC_IOCFG23_IOEV_RTC_EN_BITN 7 8842 #define IOC_IOCFG23_IOEV_RTC_EN_M 0x00000080 8843 #define IOC_IOCFG23_IOEV_RTC_EN_S 7 8844 8845 // Field: [6] IOEV_MCU_WU_EN 8846 // 8847 // Event asserted by this IO when edge detection is enabled 8848 // 8849 // 0: Input edge detection does not assert MCU_WU event 8850 // 1: Input edge detection asserts MCU_WU event 8851 #define IOC_IOCFG23_IOEV_MCU_WU_EN 0x00000040 8852 #define IOC_IOCFG23_IOEV_MCU_WU_EN_BITN 6 8853 #define IOC_IOCFG23_IOEV_MCU_WU_EN_M 0x00000040 8854 #define IOC_IOCFG23_IOEV_MCU_WU_EN_S 6 8855 8856 // Field: [5:0] PORT_ID 8857 // 8858 // Selects usage for DIO23 8859 // Note: This field should not be written other than the times when PORT_ID 8860 // value is specifically required to change. 8861 // ENUMs: 8862 // RFC_SMI_CL_IN RF Core SMI Command Link In 8863 // RFC_SMI_CL_OUT RF Core SMI Command Link Out 8864 // RFC_SMI_DL_IN RF Core SMI Data Link In 8865 // RFC_SMI_DL_OUT RF Core SMI Data Link Out 8866 // RFC_GPI1 RF Core Data In 1 8867 // RFC_GPI0 RF Core Data In 0 8868 // RFC_GPO3 RF Core Data Out 3 8869 // RFC_GPO2 RF Core Data Out 2 8870 // RFC_GPO1 RF Core Data Out 1 8871 // RFC_GPO0 RF Core Data Out 0 8872 // RFC_TRC RF Core Trace 8873 // I2S_MCLK I2S MCLK 8874 // I2S_BCLK I2S BCLK 8875 // I2S_WCLK I2S WCLK 8876 // I2S_AD1 I2S Data 1 8877 // I2S_AD0 I2S Data 0 8878 // SSI1_CLK SSI1 CLK 8879 // SSI1_FSS SSI1 FSS 8880 // SSI1_TX SSI1 TX 8881 // SSI1_RX SSI1 RX 8882 // CPU_SWV CPU SWV 8883 // PORT_EVENT7 PORT EVENT 7 8884 // Can be used as a general 8885 // purpose IO event by selecting it through 8886 // registers in the EVENT module, for example 8887 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 8888 // and so on 8889 // PORT_EVENT6 PORT EVENT 6 8890 // Can be used as a general 8891 // purpose IO event by selecting it through 8892 // registers in the EVENT module, for example 8893 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 8894 // and so on 8895 // PORT_EVENT5 PORT EVENT 5 8896 // Can be used as a general 8897 // purpose IO event by selecting it through 8898 // registers in the EVENT module, for example 8899 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 8900 // and so on 8901 // PORT_EVENT4 PORT EVENT 4 8902 // Can be used as a general 8903 // purpose IO event by selecting it through 8904 // registers in the EVENT module, for example 8905 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 8906 // and so on 8907 // PORT_EVENT3 PORT EVENT 3 8908 // Can be used as a general 8909 // purpose IO event by selecting it through 8910 // registers in the EVENT module, for example 8911 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 8912 // and so on 8913 // PORT_EVENT2 PORT EVENT 2 8914 // Can be used as a general 8915 // purpose IO event by selecting it through 8916 // registers in the EVENT module, for example 8917 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 8918 // and so on 8919 // PORT_EVENT1 PORT EVENT 1 8920 // Can be used as a general 8921 // purpose IO event by selecting it through 8922 // registers in the EVENT module, for example 8923 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 8924 // and so on 8925 // PORT_EVENT0 PORT EVENT 0 8926 // Can be used as a general 8927 // purpose IO event by selecting it through 8928 // registers in the EVENT module, for example 8929 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 8930 // and so on 8931 // UART1_RTS UART1 RTS 8932 // UART1_CTS UART1 CTS 8933 // UART1_TX UART1 TX 8934 // UART1_RX UART1 RX 8935 // UART0_RTS UART0 RTS 8936 // UART0_CTS UART0 CTS 8937 // UART0_TX UART0 TX 8938 // UART0_RX UART0 RX 8939 // I2C_MSSCL I2C Clock 8940 // I2C_MSSDA I2C Data 8941 // SSI0_CLK SSI0 CLK 8942 // SSI0_FSS SSI0 FSS 8943 // SSI0_TX SSI0 TX 8944 // SSI0_RX SSI0 RX 8945 // AUX_IO AUX IO 8946 // AON_CLK32K AON 32 KHz clock (SCLK_LF) 8947 // GPIO General Purpose IO 8948 #define IOC_IOCFG23_PORT_ID_W 6 8949 #define IOC_IOCFG23_PORT_ID_M 0x0000003F 8950 #define IOC_IOCFG23_PORT_ID_S 0 8951 #define IOC_IOCFG23_PORT_ID_RFC_SMI_CL_IN 0x00000038 8952 #define IOC_IOCFG23_PORT_ID_RFC_SMI_CL_OUT 0x00000037 8953 #define IOC_IOCFG23_PORT_ID_RFC_SMI_DL_IN 0x00000036 8954 #define IOC_IOCFG23_PORT_ID_RFC_SMI_DL_OUT 0x00000035 8955 #define IOC_IOCFG23_PORT_ID_RFC_GPI1 0x00000034 8956 #define IOC_IOCFG23_PORT_ID_RFC_GPI0 0x00000033 8957 #define IOC_IOCFG23_PORT_ID_RFC_GPO3 0x00000032 8958 #define IOC_IOCFG23_PORT_ID_RFC_GPO2 0x00000031 8959 #define IOC_IOCFG23_PORT_ID_RFC_GPO1 0x00000030 8960 #define IOC_IOCFG23_PORT_ID_RFC_GPO0 0x0000002F 8961 #define IOC_IOCFG23_PORT_ID_RFC_TRC 0x0000002E 8962 #define IOC_IOCFG23_PORT_ID_I2S_MCLK 0x00000029 8963 #define IOC_IOCFG23_PORT_ID_I2S_BCLK 0x00000028 8964 #define IOC_IOCFG23_PORT_ID_I2S_WCLK 0x00000027 8965 #define IOC_IOCFG23_PORT_ID_I2S_AD1 0x00000026 8966 #define IOC_IOCFG23_PORT_ID_I2S_AD0 0x00000025 8967 #define IOC_IOCFG23_PORT_ID_SSI1_CLK 0x00000024 8968 #define IOC_IOCFG23_PORT_ID_SSI1_FSS 0x00000023 8969 #define IOC_IOCFG23_PORT_ID_SSI1_TX 0x00000022 8970 #define IOC_IOCFG23_PORT_ID_SSI1_RX 0x00000021 8971 #define IOC_IOCFG23_PORT_ID_CPU_SWV 0x00000020 8972 #define IOC_IOCFG23_PORT_ID_PORT_EVENT7 0x0000001E 8973 #define IOC_IOCFG23_PORT_ID_PORT_EVENT6 0x0000001D 8974 #define IOC_IOCFG23_PORT_ID_PORT_EVENT5 0x0000001C 8975 #define IOC_IOCFG23_PORT_ID_PORT_EVENT4 0x0000001B 8976 #define IOC_IOCFG23_PORT_ID_PORT_EVENT3 0x0000001A 8977 #define IOC_IOCFG23_PORT_ID_PORT_EVENT2 0x00000019 8978 #define IOC_IOCFG23_PORT_ID_PORT_EVENT1 0x00000018 8979 #define IOC_IOCFG23_PORT_ID_PORT_EVENT0 0x00000017 8980 #define IOC_IOCFG23_PORT_ID_UART1_RTS 0x00000016 8981 #define IOC_IOCFG23_PORT_ID_UART1_CTS 0x00000015 8982 #define IOC_IOCFG23_PORT_ID_UART1_TX 0x00000014 8983 #define IOC_IOCFG23_PORT_ID_UART1_RX 0x00000013 8984 #define IOC_IOCFG23_PORT_ID_UART0_RTS 0x00000012 8985 #define IOC_IOCFG23_PORT_ID_UART0_CTS 0x00000011 8986 #define IOC_IOCFG23_PORT_ID_UART0_TX 0x00000010 8987 #define IOC_IOCFG23_PORT_ID_UART0_RX 0x0000000F 8988 #define IOC_IOCFG23_PORT_ID_I2C_MSSCL 0x0000000E 8989 #define IOC_IOCFG23_PORT_ID_I2C_MSSDA 0x0000000D 8990 #define IOC_IOCFG23_PORT_ID_SSI0_CLK 0x0000000C 8991 #define IOC_IOCFG23_PORT_ID_SSI0_FSS 0x0000000B 8992 #define IOC_IOCFG23_PORT_ID_SSI0_TX 0x0000000A 8993 #define IOC_IOCFG23_PORT_ID_SSI0_RX 0x00000009 8994 #define IOC_IOCFG23_PORT_ID_AUX_IO 0x00000008 8995 #define IOC_IOCFG23_PORT_ID_AON_CLK32K 0x00000007 8996 #define IOC_IOCFG23_PORT_ID_GPIO 0x00000000 8997 8998 //***************************************************************************** 8999 // 9000 // Register: IOC_O_IOCFG24 9001 // 9002 //***************************************************************************** 9003 // Field: [30] HYST_EN 9004 // 9005 // 0: Input hysteresis disable 9006 // 1: Input hysteresis enable 9007 #define IOC_IOCFG24_HYST_EN 0x40000000 9008 #define IOC_IOCFG24_HYST_EN_BITN 30 9009 #define IOC_IOCFG24_HYST_EN_M 0x40000000 9010 #define IOC_IOCFG24_HYST_EN_S 30 9011 9012 // Field: [29] IE 9013 // 9014 // 0: Input disabled 9015 // 1: Input enabled 9016 // 9017 // Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be 9018 // ignored. 9019 #define IOC_IOCFG24_IE 0x20000000 9020 #define IOC_IOCFG24_IE_BITN 29 9021 #define IOC_IOCFG24_IE_M 0x20000000 9022 #define IOC_IOCFG24_IE_S 29 9023 9024 // Field: [28:27] WU_CFG 9025 // 9026 // If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or 9027 // >0x08: 9028 // 9029 // 00: No wake-up 9030 // 01: No wake-up 9031 // 10: Wakes up from shutdown if this pad is going low. 9032 // 11: Wakes up from shutdown if this pad is going high. 9033 // 9034 // If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, 9035 // this register only sets wakeup enable or not. 9036 // 9037 // 00, 01: Wakeup disabled 9038 // 10, 11: Wakeup enabled 9039 // 9040 // Polarity is controlled from AON registers. 9041 // 9042 // Note:When the MSB is set, the IOC will deactivate the output enable for the 9043 // DIO. 9044 #define IOC_IOCFG24_WU_CFG_W 2 9045 #define IOC_IOCFG24_WU_CFG_M 0x18000000 9046 #define IOC_IOCFG24_WU_CFG_S 27 9047 9048 // Field: [26:24] IOMODE 9049 // 9050 // IO Mode 9051 // Not applicable for IO configured for AON periph. signals and AUX PORT_ID 9052 // 0x01-0x08 9053 // AUX has its own open_source/drain configuration. 9054 // 9055 // 0x2: Reserved. Undefined behavior. 9056 // 0x3: Reserved. Undefined behavior. 9057 // ENUMs: 9058 // OPENSRC_INV Open Source 9059 // Inverted input / output 9060 // OPENSRC Open Source 9061 // Normal input / output 9062 // OPENDR_INV Open Drain 9063 // Inverted input / output 9064 // OPENDR Open Drain, 9065 // Normal input / output 9066 // INV Inverted input / ouput 9067 // NORMAL Normal input / output 9068 #define IOC_IOCFG24_IOMODE_W 3 9069 #define IOC_IOCFG24_IOMODE_M 0x07000000 9070 #define IOC_IOCFG24_IOMODE_S 24 9071 #define IOC_IOCFG24_IOMODE_OPENSRC_INV 0x07000000 9072 #define IOC_IOCFG24_IOMODE_OPENSRC 0x06000000 9073 #define IOC_IOCFG24_IOMODE_OPENDR_INV 0x05000000 9074 #define IOC_IOCFG24_IOMODE_OPENDR 0x04000000 9075 #define IOC_IOCFG24_IOMODE_INV 0x01000000 9076 #define IOC_IOCFG24_IOMODE_NORMAL 0x00000000 9077 9078 // Field: [23] IOEV_AON_PROG2_EN 9079 // 9080 // Event asserted by this IO when edge detection is enabled 9081 // 9082 // 0: Input edge detection does not assert AON_PROG2 event 9083 // 1: Input edge detection asserts AON_PROG2 event 9084 #define IOC_IOCFG24_IOEV_AON_PROG2_EN 0x00800000 9085 #define IOC_IOCFG24_IOEV_AON_PROG2_EN_BITN 23 9086 #define IOC_IOCFG24_IOEV_AON_PROG2_EN_M 0x00800000 9087 #define IOC_IOCFG24_IOEV_AON_PROG2_EN_S 23 9088 9089 // Field: [22] IOEV_AON_PROG1_EN 9090 // 9091 // Event asserted by this IO when edge detection is enabled 9092 // 9093 // 0: Input edge detection does not assert AON_PROG1 event 9094 // 1: Input edge detection asserts AON_PROG1 event 9095 #define IOC_IOCFG24_IOEV_AON_PROG1_EN 0x00400000 9096 #define IOC_IOCFG24_IOEV_AON_PROG1_EN_BITN 22 9097 #define IOC_IOCFG24_IOEV_AON_PROG1_EN_M 0x00400000 9098 #define IOC_IOCFG24_IOEV_AON_PROG1_EN_S 22 9099 9100 // Field: [21] IOEV_AON_PROG0_EN 9101 // 9102 // Event asserted by this IO when edge detection is enabled 9103 // 9104 // 0: Input edge detection does not assert AON_PROG0 event 9105 // 1: Input edge detection asserts AON_PROG0 event 9106 #define IOC_IOCFG24_IOEV_AON_PROG0_EN 0x00200000 9107 #define IOC_IOCFG24_IOEV_AON_PROG0_EN_BITN 21 9108 #define IOC_IOCFG24_IOEV_AON_PROG0_EN_M 0x00200000 9109 #define IOC_IOCFG24_IOEV_AON_PROG0_EN_S 21 9110 9111 // Field: [18] EDGE_IRQ_EN 9112 // 9113 // 0: No interrupt generation 9114 // 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is 9115 // enabled) 9116 #define IOC_IOCFG24_EDGE_IRQ_EN 0x00040000 9117 #define IOC_IOCFG24_EDGE_IRQ_EN_BITN 18 9118 #define IOC_IOCFG24_EDGE_IRQ_EN_M 0x00040000 9119 #define IOC_IOCFG24_EDGE_IRQ_EN_S 18 9120 9121 // Field: [17:16] EDGE_DET 9122 // 9123 // Enable generation of edge detection events on this IO 9124 // ENUMs: 9125 // BOTH Positive and negative edge detection 9126 // POS Positive edge detection 9127 // NEG Negative edge detection 9128 // NONE No edge detection 9129 #define IOC_IOCFG24_EDGE_DET_W 2 9130 #define IOC_IOCFG24_EDGE_DET_M 0x00030000 9131 #define IOC_IOCFG24_EDGE_DET_S 16 9132 #define IOC_IOCFG24_EDGE_DET_BOTH 0x00030000 9133 #define IOC_IOCFG24_EDGE_DET_POS 0x00020000 9134 #define IOC_IOCFG24_EDGE_DET_NEG 0x00010000 9135 #define IOC_IOCFG24_EDGE_DET_NONE 0x00000000 9136 9137 // Field: [14:13] PULL_CTL 9138 // 9139 // Pull control 9140 // ENUMs: 9141 // DIS No pull 9142 // UP Pull up 9143 // DWN Pull down 9144 #define IOC_IOCFG24_PULL_CTL_W 2 9145 #define IOC_IOCFG24_PULL_CTL_M 0x00006000 9146 #define IOC_IOCFG24_PULL_CTL_S 13 9147 #define IOC_IOCFG24_PULL_CTL_DIS 0x00006000 9148 #define IOC_IOCFG24_PULL_CTL_UP 0x00004000 9149 #define IOC_IOCFG24_PULL_CTL_DWN 0x00002000 9150 9151 // Field: [12] SLEW_RED 9152 // 9153 // 0: Normal slew rate 9154 // 1: Enables reduced slew rate in output driver. 9155 #define IOC_IOCFG24_SLEW_RED 0x00001000 9156 #define IOC_IOCFG24_SLEW_RED_BITN 12 9157 #define IOC_IOCFG24_SLEW_RED_M 0x00001000 9158 #define IOC_IOCFG24_SLEW_RED_S 12 9159 9160 // Field: [11:10] IOCURR 9161 // 9162 // Selects IO current mode of this IO. 9163 // ENUMs: 9164 // 4_8MA Extended-Current (EC) mode: Min 8 mA for double 9165 // drive strength IOs (min 4 mA for normal IOs) 9166 // when IOSTR is set to AUTO 9167 // 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set 9168 // to AUTO 9169 // 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set 9170 // to AUTO 9171 #define IOC_IOCFG24_IOCURR_W 2 9172 #define IOC_IOCFG24_IOCURR_M 0x00000C00 9173 #define IOC_IOCFG24_IOCURR_S 10 9174 #define IOC_IOCFG24_IOCURR_4_8MA 0x00000800 9175 #define IOC_IOCFG24_IOCURR_4MA 0x00000400 9176 #define IOC_IOCFG24_IOCURR_2MA 0x00000000 9177 9178 // Field: [9:8] IOSTR 9179 // 9180 // Select source for drive strength control of this IO. 9181 // This setting controls the drive strength of the Low-Current (LC) mode. 9182 // Higher drive strength can be selected in IOCURR 9183 // ENUMs: 9184 // MAX Maximum drive strength, controlled by 9185 // AON_IOC:IOSTRMAX (min 2 mA @1.8V with default 9186 // values) 9187 // MED Medium drive strength, controlled by 9188 // AON_IOC:IOSTRMED (min 2 mA @2.5V with default 9189 // values) 9190 // MIN Minimum drive strength, controlled by 9191 // AON_IOC:IOSTRMIN (min 2 mA @3.3V with default 9192 // values) 9193 // AUTO Automatic drive strength, controlled by AON BATMON 9194 // based on battery voltage. (min 2 mA @VDDS) 9195 #define IOC_IOCFG24_IOSTR_W 2 9196 #define IOC_IOCFG24_IOSTR_M 0x00000300 9197 #define IOC_IOCFG24_IOSTR_S 8 9198 #define IOC_IOCFG24_IOSTR_MAX 0x00000300 9199 #define IOC_IOCFG24_IOSTR_MED 0x00000200 9200 #define IOC_IOCFG24_IOSTR_MIN 0x00000100 9201 #define IOC_IOCFG24_IOSTR_AUTO 0x00000000 9202 9203 // Field: [7] IOEV_RTC_EN 9204 // 9205 // Event asserted by this IO when edge detection is enabled 9206 // 9207 // 0: Input edge detection does not assert RTC event 9208 // 1: Input edge detection asserts RTC event 9209 #define IOC_IOCFG24_IOEV_RTC_EN 0x00000080 9210 #define IOC_IOCFG24_IOEV_RTC_EN_BITN 7 9211 #define IOC_IOCFG24_IOEV_RTC_EN_M 0x00000080 9212 #define IOC_IOCFG24_IOEV_RTC_EN_S 7 9213 9214 // Field: [6] IOEV_MCU_WU_EN 9215 // 9216 // Event asserted by this IO when edge detection is enabled 9217 // 9218 // 0: Input edge detection does not assert MCU_WU event 9219 // 1: Input edge detection asserts MCU_WU event 9220 #define IOC_IOCFG24_IOEV_MCU_WU_EN 0x00000040 9221 #define IOC_IOCFG24_IOEV_MCU_WU_EN_BITN 6 9222 #define IOC_IOCFG24_IOEV_MCU_WU_EN_M 0x00000040 9223 #define IOC_IOCFG24_IOEV_MCU_WU_EN_S 6 9224 9225 // Field: [5:0] PORT_ID 9226 // 9227 // Selects usage for DIO24 9228 // Note: This field should not be written other than the times when PORT_ID 9229 // value is specifically required to change. 9230 // ENUMs: 9231 // RFC_SMI_CL_IN RF Core SMI Command Link In 9232 // RFC_SMI_CL_OUT RF Core SMI Command Link Out 9233 // RFC_SMI_DL_IN RF Core SMI Data Link In 9234 // RFC_SMI_DL_OUT RF Core SMI Data Link Out 9235 // RFC_GPI1 RF Core Data In 1 9236 // RFC_GPI0 RF Core Data In 0 9237 // RFC_GPO3 RF Core Data Out 3 9238 // RFC_GPO2 RF Core Data Out 2 9239 // RFC_GPO1 RF Core Data Out 1 9240 // RFC_GPO0 RF Core Data Out 0 9241 // RFC_TRC RF Core Trace 9242 // I2S_MCLK I2S MCLK 9243 // I2S_BCLK I2S BCLK 9244 // I2S_WCLK I2S WCLK 9245 // I2S_AD1 I2S Data 1 9246 // I2S_AD0 I2S Data 0 9247 // SSI1_CLK SSI1 CLK 9248 // SSI1_FSS SSI1 FSS 9249 // SSI1_TX SSI1 TX 9250 // SSI1_RX SSI1 RX 9251 // CPU_SWV CPU SWV 9252 // PORT_EVENT7 PORT EVENT 7 9253 // Can be used as a general 9254 // purpose IO event by selecting it through 9255 // registers in the EVENT module, for example 9256 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 9257 // and so on 9258 // PORT_EVENT6 PORT EVENT 6 9259 // Can be used as a general 9260 // purpose IO event by selecting it through 9261 // registers in the EVENT module, for example 9262 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 9263 // and so on 9264 // PORT_EVENT5 PORT EVENT 5 9265 // Can be used as a general 9266 // purpose IO event by selecting it through 9267 // registers in the EVENT module, for example 9268 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 9269 // and so on 9270 // PORT_EVENT4 PORT EVENT 4 9271 // Can be used as a general 9272 // purpose IO event by selecting it through 9273 // registers in the EVENT module, for example 9274 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 9275 // and so on 9276 // PORT_EVENT3 PORT EVENT 3 9277 // Can be used as a general 9278 // purpose IO event by selecting it through 9279 // registers in the EVENT module, for example 9280 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 9281 // and so on 9282 // PORT_EVENT2 PORT EVENT 2 9283 // Can be used as a general 9284 // purpose IO event by selecting it through 9285 // registers in the EVENT module, for example 9286 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 9287 // and so on 9288 // PORT_EVENT1 PORT EVENT 1 9289 // Can be used as a general 9290 // purpose IO event by selecting it through 9291 // registers in the EVENT module, for example 9292 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 9293 // and so on 9294 // PORT_EVENT0 PORT EVENT 0 9295 // Can be used as a general 9296 // purpose IO event by selecting it through 9297 // registers in the EVENT module, for example 9298 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 9299 // and so on 9300 // UART1_RTS UART1 RTS 9301 // UART1_CTS UART1 CTS 9302 // UART1_TX UART1 TX 9303 // UART1_RX UART1 RX 9304 // UART0_RTS UART0 RTS 9305 // UART0_CTS UART0 CTS 9306 // UART0_TX UART0 TX 9307 // UART0_RX UART0 RX 9308 // I2C_MSSCL I2C Clock 9309 // I2C_MSSDA I2C Data 9310 // SSI0_CLK SSI0 CLK 9311 // SSI0_FSS SSI0 FSS 9312 // SSI0_TX SSI0 TX 9313 // SSI0_RX SSI0 RX 9314 // AUX_IO AUX IO 9315 // AON_CLK32K AON 32 KHz clock (SCLK_LF) 9316 // GPIO General Purpose IO 9317 #define IOC_IOCFG24_PORT_ID_W 6 9318 #define IOC_IOCFG24_PORT_ID_M 0x0000003F 9319 #define IOC_IOCFG24_PORT_ID_S 0 9320 #define IOC_IOCFG24_PORT_ID_RFC_SMI_CL_IN 0x00000038 9321 #define IOC_IOCFG24_PORT_ID_RFC_SMI_CL_OUT 0x00000037 9322 #define IOC_IOCFG24_PORT_ID_RFC_SMI_DL_IN 0x00000036 9323 #define IOC_IOCFG24_PORT_ID_RFC_SMI_DL_OUT 0x00000035 9324 #define IOC_IOCFG24_PORT_ID_RFC_GPI1 0x00000034 9325 #define IOC_IOCFG24_PORT_ID_RFC_GPI0 0x00000033 9326 #define IOC_IOCFG24_PORT_ID_RFC_GPO3 0x00000032 9327 #define IOC_IOCFG24_PORT_ID_RFC_GPO2 0x00000031 9328 #define IOC_IOCFG24_PORT_ID_RFC_GPO1 0x00000030 9329 #define IOC_IOCFG24_PORT_ID_RFC_GPO0 0x0000002F 9330 #define IOC_IOCFG24_PORT_ID_RFC_TRC 0x0000002E 9331 #define IOC_IOCFG24_PORT_ID_I2S_MCLK 0x00000029 9332 #define IOC_IOCFG24_PORT_ID_I2S_BCLK 0x00000028 9333 #define IOC_IOCFG24_PORT_ID_I2S_WCLK 0x00000027 9334 #define IOC_IOCFG24_PORT_ID_I2S_AD1 0x00000026 9335 #define IOC_IOCFG24_PORT_ID_I2S_AD0 0x00000025 9336 #define IOC_IOCFG24_PORT_ID_SSI1_CLK 0x00000024 9337 #define IOC_IOCFG24_PORT_ID_SSI1_FSS 0x00000023 9338 #define IOC_IOCFG24_PORT_ID_SSI1_TX 0x00000022 9339 #define IOC_IOCFG24_PORT_ID_SSI1_RX 0x00000021 9340 #define IOC_IOCFG24_PORT_ID_CPU_SWV 0x00000020 9341 #define IOC_IOCFG24_PORT_ID_PORT_EVENT7 0x0000001E 9342 #define IOC_IOCFG24_PORT_ID_PORT_EVENT6 0x0000001D 9343 #define IOC_IOCFG24_PORT_ID_PORT_EVENT5 0x0000001C 9344 #define IOC_IOCFG24_PORT_ID_PORT_EVENT4 0x0000001B 9345 #define IOC_IOCFG24_PORT_ID_PORT_EVENT3 0x0000001A 9346 #define IOC_IOCFG24_PORT_ID_PORT_EVENT2 0x00000019 9347 #define IOC_IOCFG24_PORT_ID_PORT_EVENT1 0x00000018 9348 #define IOC_IOCFG24_PORT_ID_PORT_EVENT0 0x00000017 9349 #define IOC_IOCFG24_PORT_ID_UART1_RTS 0x00000016 9350 #define IOC_IOCFG24_PORT_ID_UART1_CTS 0x00000015 9351 #define IOC_IOCFG24_PORT_ID_UART1_TX 0x00000014 9352 #define IOC_IOCFG24_PORT_ID_UART1_RX 0x00000013 9353 #define IOC_IOCFG24_PORT_ID_UART0_RTS 0x00000012 9354 #define IOC_IOCFG24_PORT_ID_UART0_CTS 0x00000011 9355 #define IOC_IOCFG24_PORT_ID_UART0_TX 0x00000010 9356 #define IOC_IOCFG24_PORT_ID_UART0_RX 0x0000000F 9357 #define IOC_IOCFG24_PORT_ID_I2C_MSSCL 0x0000000E 9358 #define IOC_IOCFG24_PORT_ID_I2C_MSSDA 0x0000000D 9359 #define IOC_IOCFG24_PORT_ID_SSI0_CLK 0x0000000C 9360 #define IOC_IOCFG24_PORT_ID_SSI0_FSS 0x0000000B 9361 #define IOC_IOCFG24_PORT_ID_SSI0_TX 0x0000000A 9362 #define IOC_IOCFG24_PORT_ID_SSI0_RX 0x00000009 9363 #define IOC_IOCFG24_PORT_ID_AUX_IO 0x00000008 9364 #define IOC_IOCFG24_PORT_ID_AON_CLK32K 0x00000007 9365 #define IOC_IOCFG24_PORT_ID_GPIO 0x00000000 9366 9367 //***************************************************************************** 9368 // 9369 // Register: IOC_O_IOCFG25 9370 // 9371 //***************************************************************************** 9372 // Field: [30] HYST_EN 9373 // 9374 // 0: Input hysteresis disable 9375 // 1: Input hysteresis enable 9376 #define IOC_IOCFG25_HYST_EN 0x40000000 9377 #define IOC_IOCFG25_HYST_EN_BITN 30 9378 #define IOC_IOCFG25_HYST_EN_M 0x40000000 9379 #define IOC_IOCFG25_HYST_EN_S 30 9380 9381 // Field: [29] IE 9382 // 9383 // 0: Input disabled 9384 // 1: Input enabled 9385 // 9386 // Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be 9387 // ignored. 9388 #define IOC_IOCFG25_IE 0x20000000 9389 #define IOC_IOCFG25_IE_BITN 29 9390 #define IOC_IOCFG25_IE_M 0x20000000 9391 #define IOC_IOCFG25_IE_S 29 9392 9393 // Field: [28:27] WU_CFG 9394 // 9395 // If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or 9396 // >0x08: 9397 // 9398 // 00: No wake-up 9399 // 01: No wake-up 9400 // 10: Wakes up from shutdown if this pad is going low. 9401 // 11: Wakes up from shutdown if this pad is going high. 9402 // 9403 // If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, 9404 // this register only sets wakeup enable or not. 9405 // 9406 // 00, 01: Wakeup disabled 9407 // 10, 11: Wakeup enabled 9408 // 9409 // Polarity is controlled from AON registers. 9410 // 9411 // Note:When the MSB is set, the IOC will deactivate the output enable for the 9412 // DIO. 9413 #define IOC_IOCFG25_WU_CFG_W 2 9414 #define IOC_IOCFG25_WU_CFG_M 0x18000000 9415 #define IOC_IOCFG25_WU_CFG_S 27 9416 9417 // Field: [26:24] IOMODE 9418 // 9419 // IO Mode 9420 // Not applicable for IO configured for AON periph. signals and AUX PORT_ID 9421 // 0x01-0x08 9422 // AUX has its own open_source/drain configuration. 9423 // 9424 // 0x2: Reserved. Undefined behavior. 9425 // 0x3: Reserved. Undefined behavior. 9426 // ENUMs: 9427 // OPENSRC_INV Open Source 9428 // Inverted input / output 9429 // OPENSRC Open Source 9430 // Normal input / output 9431 // OPENDR_INV Open Drain 9432 // Inverted input / output 9433 // OPENDR Open Drain, 9434 // Normal input / output 9435 // INV Inverted input / ouput 9436 // NORMAL Normal input / output 9437 #define IOC_IOCFG25_IOMODE_W 3 9438 #define IOC_IOCFG25_IOMODE_M 0x07000000 9439 #define IOC_IOCFG25_IOMODE_S 24 9440 #define IOC_IOCFG25_IOMODE_OPENSRC_INV 0x07000000 9441 #define IOC_IOCFG25_IOMODE_OPENSRC 0x06000000 9442 #define IOC_IOCFG25_IOMODE_OPENDR_INV 0x05000000 9443 #define IOC_IOCFG25_IOMODE_OPENDR 0x04000000 9444 #define IOC_IOCFG25_IOMODE_INV 0x01000000 9445 #define IOC_IOCFG25_IOMODE_NORMAL 0x00000000 9446 9447 // Field: [23] IOEV_AON_PROG2_EN 9448 // 9449 // Event asserted by this IO when edge detection is enabled 9450 // 9451 // 0: Input edge detection does not assert AON_PROG2 event 9452 // 1: Input edge detection asserts AON_PROG2 event 9453 #define IOC_IOCFG25_IOEV_AON_PROG2_EN 0x00800000 9454 #define IOC_IOCFG25_IOEV_AON_PROG2_EN_BITN 23 9455 #define IOC_IOCFG25_IOEV_AON_PROG2_EN_M 0x00800000 9456 #define IOC_IOCFG25_IOEV_AON_PROG2_EN_S 23 9457 9458 // Field: [22] IOEV_AON_PROG1_EN 9459 // 9460 // Event asserted by this IO when edge detection is enabled 9461 // 9462 // 0: Input edge detection does not assert AON_PROG1 event 9463 // 1: Input edge detection asserts AON_PROG1 event 9464 #define IOC_IOCFG25_IOEV_AON_PROG1_EN 0x00400000 9465 #define IOC_IOCFG25_IOEV_AON_PROG1_EN_BITN 22 9466 #define IOC_IOCFG25_IOEV_AON_PROG1_EN_M 0x00400000 9467 #define IOC_IOCFG25_IOEV_AON_PROG1_EN_S 22 9468 9469 // Field: [21] IOEV_AON_PROG0_EN 9470 // 9471 // Event asserted by this IO when edge detection is enabled 9472 // 9473 // 0: Input edge detection does not assert AON_PROG0 event 9474 // 1: Input edge detection asserts AON_PROG0 event 9475 #define IOC_IOCFG25_IOEV_AON_PROG0_EN 0x00200000 9476 #define IOC_IOCFG25_IOEV_AON_PROG0_EN_BITN 21 9477 #define IOC_IOCFG25_IOEV_AON_PROG0_EN_M 0x00200000 9478 #define IOC_IOCFG25_IOEV_AON_PROG0_EN_S 21 9479 9480 // Field: [18] EDGE_IRQ_EN 9481 // 9482 // 0: No interrupt generation 9483 // 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is 9484 // enabled) 9485 #define IOC_IOCFG25_EDGE_IRQ_EN 0x00040000 9486 #define IOC_IOCFG25_EDGE_IRQ_EN_BITN 18 9487 #define IOC_IOCFG25_EDGE_IRQ_EN_M 0x00040000 9488 #define IOC_IOCFG25_EDGE_IRQ_EN_S 18 9489 9490 // Field: [17:16] EDGE_DET 9491 // 9492 // Enable generation of edge detection events on this IO 9493 // ENUMs: 9494 // BOTH Positive and negative edge detection 9495 // POS Positive edge detection 9496 // NEG Negative edge detection 9497 // NONE No edge detection 9498 #define IOC_IOCFG25_EDGE_DET_W 2 9499 #define IOC_IOCFG25_EDGE_DET_M 0x00030000 9500 #define IOC_IOCFG25_EDGE_DET_S 16 9501 #define IOC_IOCFG25_EDGE_DET_BOTH 0x00030000 9502 #define IOC_IOCFG25_EDGE_DET_POS 0x00020000 9503 #define IOC_IOCFG25_EDGE_DET_NEG 0x00010000 9504 #define IOC_IOCFG25_EDGE_DET_NONE 0x00000000 9505 9506 // Field: [14:13] PULL_CTL 9507 // 9508 // Pull control 9509 // ENUMs: 9510 // DIS No pull 9511 // UP Pull up 9512 // DWN Pull down 9513 #define IOC_IOCFG25_PULL_CTL_W 2 9514 #define IOC_IOCFG25_PULL_CTL_M 0x00006000 9515 #define IOC_IOCFG25_PULL_CTL_S 13 9516 #define IOC_IOCFG25_PULL_CTL_DIS 0x00006000 9517 #define IOC_IOCFG25_PULL_CTL_UP 0x00004000 9518 #define IOC_IOCFG25_PULL_CTL_DWN 0x00002000 9519 9520 // Field: [12] SLEW_RED 9521 // 9522 // 0: Normal slew rate 9523 // 1: Enables reduced slew rate in output driver. 9524 #define IOC_IOCFG25_SLEW_RED 0x00001000 9525 #define IOC_IOCFG25_SLEW_RED_BITN 12 9526 #define IOC_IOCFG25_SLEW_RED_M 0x00001000 9527 #define IOC_IOCFG25_SLEW_RED_S 12 9528 9529 // Field: [11:10] IOCURR 9530 // 9531 // Selects IO current mode of this IO. 9532 // ENUMs: 9533 // 4_8MA Extended-Current (EC) mode: Min 8 mA for double 9534 // drive strength IOs (min 4 mA for normal IOs) 9535 // when IOSTR is set to AUTO 9536 // 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set 9537 // to AUTO 9538 // 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set 9539 // to AUTO 9540 #define IOC_IOCFG25_IOCURR_W 2 9541 #define IOC_IOCFG25_IOCURR_M 0x00000C00 9542 #define IOC_IOCFG25_IOCURR_S 10 9543 #define IOC_IOCFG25_IOCURR_4_8MA 0x00000800 9544 #define IOC_IOCFG25_IOCURR_4MA 0x00000400 9545 #define IOC_IOCFG25_IOCURR_2MA 0x00000000 9546 9547 // Field: [9:8] IOSTR 9548 // 9549 // Select source for drive strength control of this IO. 9550 // This setting controls the drive strength of the Low-Current (LC) mode. 9551 // Higher drive strength can be selected in IOCURR 9552 // ENUMs: 9553 // MAX Maximum drive strength, controlled by 9554 // AON_IOC:IOSTRMAX (min 2 mA @1.8V with default 9555 // values) 9556 // MED Medium drive strength, controlled by 9557 // AON_IOC:IOSTRMED (min 2 mA @2.5V with default 9558 // values) 9559 // MIN Minimum drive strength, controlled by 9560 // AON_IOC:IOSTRMIN (min 2 mA @3.3V with default 9561 // values) 9562 // AUTO Automatic drive strength, controlled by AON BATMON 9563 // based on battery voltage. (min 2 mA @VDDS) 9564 #define IOC_IOCFG25_IOSTR_W 2 9565 #define IOC_IOCFG25_IOSTR_M 0x00000300 9566 #define IOC_IOCFG25_IOSTR_S 8 9567 #define IOC_IOCFG25_IOSTR_MAX 0x00000300 9568 #define IOC_IOCFG25_IOSTR_MED 0x00000200 9569 #define IOC_IOCFG25_IOSTR_MIN 0x00000100 9570 #define IOC_IOCFG25_IOSTR_AUTO 0x00000000 9571 9572 // Field: [7] IOEV_RTC_EN 9573 // 9574 // Event asserted by this IO when edge detection is enabled 9575 // 9576 // 0: Input edge detection does not assert RTC event 9577 // 1: Input edge detection asserts RTC event 9578 #define IOC_IOCFG25_IOEV_RTC_EN 0x00000080 9579 #define IOC_IOCFG25_IOEV_RTC_EN_BITN 7 9580 #define IOC_IOCFG25_IOEV_RTC_EN_M 0x00000080 9581 #define IOC_IOCFG25_IOEV_RTC_EN_S 7 9582 9583 // Field: [6] IOEV_MCU_WU_EN 9584 // 9585 // Event asserted by this IO when edge detection is enabled 9586 // 9587 // 0: Input edge detection does not assert MCU_WU event 9588 // 1: Input edge detection asserts MCU_WU event 9589 #define IOC_IOCFG25_IOEV_MCU_WU_EN 0x00000040 9590 #define IOC_IOCFG25_IOEV_MCU_WU_EN_BITN 6 9591 #define IOC_IOCFG25_IOEV_MCU_WU_EN_M 0x00000040 9592 #define IOC_IOCFG25_IOEV_MCU_WU_EN_S 6 9593 9594 // Field: [5:0] PORT_ID 9595 // 9596 // Selects usage for DIO25 9597 // Note: This field should not be written other than the times when PORT_ID 9598 // value is specifically required to change. 9599 // ENUMs: 9600 // RFC_SMI_CL_IN RF Core SMI Command Link In 9601 // RFC_SMI_CL_OUT RF Core SMI Command Link Out 9602 // RFC_SMI_DL_IN RF Core SMI Data Link In 9603 // RFC_SMI_DL_OUT RF Core SMI Data Link Out 9604 // RFC_GPI1 RF Core Data In 1 9605 // RFC_GPI0 RF Core Data In 0 9606 // RFC_GPO3 RF Core Data Out 3 9607 // RFC_GPO2 RF Core Data Out 2 9608 // RFC_GPO1 RF Core Data Out 1 9609 // RFC_GPO0 RF Core Data Out 0 9610 // RFC_TRC RF Core Trace 9611 // I2S_MCLK I2S MCLK 9612 // I2S_BCLK I2S BCLK 9613 // I2S_WCLK I2S WCLK 9614 // I2S_AD1 I2S Data 1 9615 // I2S_AD0 I2S Data 0 9616 // SSI1_CLK SSI1 CLK 9617 // SSI1_FSS SSI1 FSS 9618 // SSI1_TX SSI1 TX 9619 // SSI1_RX SSI1 RX 9620 // CPU_SWV CPU SWV 9621 // PORT_EVENT7 PORT EVENT 7 9622 // Can be used as a general 9623 // purpose IO event by selecting it through 9624 // registers in the EVENT module, for example 9625 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 9626 // and so on 9627 // PORT_EVENT6 PORT EVENT 6 9628 // Can be used as a general 9629 // purpose IO event by selecting it through 9630 // registers in the EVENT module, for example 9631 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 9632 // and so on 9633 // PORT_EVENT5 PORT EVENT 5 9634 // Can be used as a general 9635 // purpose IO event by selecting it through 9636 // registers in the EVENT module, for example 9637 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 9638 // and so on 9639 // PORT_EVENT4 PORT EVENT 4 9640 // Can be used as a general 9641 // purpose IO event by selecting it through 9642 // registers in the EVENT module, for example 9643 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 9644 // and so on 9645 // PORT_EVENT3 PORT EVENT 3 9646 // Can be used as a general 9647 // purpose IO event by selecting it through 9648 // registers in the EVENT module, for example 9649 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 9650 // and so on 9651 // PORT_EVENT2 PORT EVENT 2 9652 // Can be used as a general 9653 // purpose IO event by selecting it through 9654 // registers in the EVENT module, for example 9655 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 9656 // and so on 9657 // PORT_EVENT1 PORT EVENT 1 9658 // Can be used as a general 9659 // purpose IO event by selecting it through 9660 // registers in the EVENT module, for example 9661 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 9662 // and so on 9663 // PORT_EVENT0 PORT EVENT 0 9664 // Can be used as a general 9665 // purpose IO event by selecting it through 9666 // registers in the EVENT module, for example 9667 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 9668 // and so on 9669 // UART1_RTS UART1 RTS 9670 // UART1_CTS UART1 CTS 9671 // UART1_TX UART1 TX 9672 // UART1_RX UART1 RX 9673 // UART0_RTS UART0 RTS 9674 // UART0_CTS UART0 CTS 9675 // UART0_TX UART0 TX 9676 // UART0_RX UART0 RX 9677 // I2C_MSSCL I2C Clock 9678 // I2C_MSSDA I2C Data 9679 // SSI0_CLK SSI0 CLK 9680 // SSI0_FSS SSI0 FSS 9681 // SSI0_TX SSI0 TX 9682 // SSI0_RX SSI0 RX 9683 // AUX_IO AUX IO 9684 // AON_CLK32K AON 32 KHz clock (SCLK_LF) 9685 // GPIO General Purpose IO 9686 #define IOC_IOCFG25_PORT_ID_W 6 9687 #define IOC_IOCFG25_PORT_ID_M 0x0000003F 9688 #define IOC_IOCFG25_PORT_ID_S 0 9689 #define IOC_IOCFG25_PORT_ID_RFC_SMI_CL_IN 0x00000038 9690 #define IOC_IOCFG25_PORT_ID_RFC_SMI_CL_OUT 0x00000037 9691 #define IOC_IOCFG25_PORT_ID_RFC_SMI_DL_IN 0x00000036 9692 #define IOC_IOCFG25_PORT_ID_RFC_SMI_DL_OUT 0x00000035 9693 #define IOC_IOCFG25_PORT_ID_RFC_GPI1 0x00000034 9694 #define IOC_IOCFG25_PORT_ID_RFC_GPI0 0x00000033 9695 #define IOC_IOCFG25_PORT_ID_RFC_GPO3 0x00000032 9696 #define IOC_IOCFG25_PORT_ID_RFC_GPO2 0x00000031 9697 #define IOC_IOCFG25_PORT_ID_RFC_GPO1 0x00000030 9698 #define IOC_IOCFG25_PORT_ID_RFC_GPO0 0x0000002F 9699 #define IOC_IOCFG25_PORT_ID_RFC_TRC 0x0000002E 9700 #define IOC_IOCFG25_PORT_ID_I2S_MCLK 0x00000029 9701 #define IOC_IOCFG25_PORT_ID_I2S_BCLK 0x00000028 9702 #define IOC_IOCFG25_PORT_ID_I2S_WCLK 0x00000027 9703 #define IOC_IOCFG25_PORT_ID_I2S_AD1 0x00000026 9704 #define IOC_IOCFG25_PORT_ID_I2S_AD0 0x00000025 9705 #define IOC_IOCFG25_PORT_ID_SSI1_CLK 0x00000024 9706 #define IOC_IOCFG25_PORT_ID_SSI1_FSS 0x00000023 9707 #define IOC_IOCFG25_PORT_ID_SSI1_TX 0x00000022 9708 #define IOC_IOCFG25_PORT_ID_SSI1_RX 0x00000021 9709 #define IOC_IOCFG25_PORT_ID_CPU_SWV 0x00000020 9710 #define IOC_IOCFG25_PORT_ID_PORT_EVENT7 0x0000001E 9711 #define IOC_IOCFG25_PORT_ID_PORT_EVENT6 0x0000001D 9712 #define IOC_IOCFG25_PORT_ID_PORT_EVENT5 0x0000001C 9713 #define IOC_IOCFG25_PORT_ID_PORT_EVENT4 0x0000001B 9714 #define IOC_IOCFG25_PORT_ID_PORT_EVENT3 0x0000001A 9715 #define IOC_IOCFG25_PORT_ID_PORT_EVENT2 0x00000019 9716 #define IOC_IOCFG25_PORT_ID_PORT_EVENT1 0x00000018 9717 #define IOC_IOCFG25_PORT_ID_PORT_EVENT0 0x00000017 9718 #define IOC_IOCFG25_PORT_ID_UART1_RTS 0x00000016 9719 #define IOC_IOCFG25_PORT_ID_UART1_CTS 0x00000015 9720 #define IOC_IOCFG25_PORT_ID_UART1_TX 0x00000014 9721 #define IOC_IOCFG25_PORT_ID_UART1_RX 0x00000013 9722 #define IOC_IOCFG25_PORT_ID_UART0_RTS 0x00000012 9723 #define IOC_IOCFG25_PORT_ID_UART0_CTS 0x00000011 9724 #define IOC_IOCFG25_PORT_ID_UART0_TX 0x00000010 9725 #define IOC_IOCFG25_PORT_ID_UART0_RX 0x0000000F 9726 #define IOC_IOCFG25_PORT_ID_I2C_MSSCL 0x0000000E 9727 #define IOC_IOCFG25_PORT_ID_I2C_MSSDA 0x0000000D 9728 #define IOC_IOCFG25_PORT_ID_SSI0_CLK 0x0000000C 9729 #define IOC_IOCFG25_PORT_ID_SSI0_FSS 0x0000000B 9730 #define IOC_IOCFG25_PORT_ID_SSI0_TX 0x0000000A 9731 #define IOC_IOCFG25_PORT_ID_SSI0_RX 0x00000009 9732 #define IOC_IOCFG25_PORT_ID_AUX_IO 0x00000008 9733 #define IOC_IOCFG25_PORT_ID_AON_CLK32K 0x00000007 9734 #define IOC_IOCFG25_PORT_ID_GPIO 0x00000000 9735 9736 //***************************************************************************** 9737 // 9738 // Register: IOC_O_IOCFG26 9739 // 9740 //***************************************************************************** 9741 // Field: [30] HYST_EN 9742 // 9743 // 0: Input hysteresis disable 9744 // 1: Input hysteresis enable 9745 #define IOC_IOCFG26_HYST_EN 0x40000000 9746 #define IOC_IOCFG26_HYST_EN_BITN 30 9747 #define IOC_IOCFG26_HYST_EN_M 0x40000000 9748 #define IOC_IOCFG26_HYST_EN_S 30 9749 9750 // Field: [29] IE 9751 // 9752 // 0: Input disabled 9753 // 1: Input enabled 9754 // 9755 // Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be 9756 // ignored. 9757 #define IOC_IOCFG26_IE 0x20000000 9758 #define IOC_IOCFG26_IE_BITN 29 9759 #define IOC_IOCFG26_IE_M 0x20000000 9760 #define IOC_IOCFG26_IE_S 29 9761 9762 // Field: [28:27] WU_CFG 9763 // 9764 // If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or 9765 // >0x08: 9766 // 9767 // 00: No wake-up 9768 // 01: No wake-up 9769 // 10: Wakes up from shutdown if this pad is going low. 9770 // 11: Wakes up from shutdown if this pad is going high. 9771 // 9772 // If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, 9773 // this register only sets wakeup enable or not. 9774 // 9775 // 00, 01: Wakeup disabled 9776 // 10, 11: Wakeup enabled 9777 // 9778 // Polarity is controlled from AON registers. 9779 // 9780 // Note:When the MSB is set, the IOC will deactivate the output enable for the 9781 // DIO. 9782 #define IOC_IOCFG26_WU_CFG_W 2 9783 #define IOC_IOCFG26_WU_CFG_M 0x18000000 9784 #define IOC_IOCFG26_WU_CFG_S 27 9785 9786 // Field: [26:24] IOMODE 9787 // 9788 // IO Mode 9789 // Not applicable for IO configured for AON periph. signals and AUX PORT_ID 9790 // 0x01-0x08 9791 // AUX has its own open_source/drain configuration. 9792 // 9793 // 0x2: Reserved. Undefined behavior. 9794 // 0x3: Reserved. Undefined behavior. 9795 // ENUMs: 9796 // OPENSRC_INV Open Source 9797 // Inverted input / output 9798 // OPENSRC Open Source 9799 // Normal input / output 9800 // OPENDR_INV Open Drain 9801 // Inverted input / output 9802 // OPENDR Open Drain, 9803 // Normal input / output 9804 // INV Inverted input / ouput 9805 // NORMAL Normal input / output 9806 #define IOC_IOCFG26_IOMODE_W 3 9807 #define IOC_IOCFG26_IOMODE_M 0x07000000 9808 #define IOC_IOCFG26_IOMODE_S 24 9809 #define IOC_IOCFG26_IOMODE_OPENSRC_INV 0x07000000 9810 #define IOC_IOCFG26_IOMODE_OPENSRC 0x06000000 9811 #define IOC_IOCFG26_IOMODE_OPENDR_INV 0x05000000 9812 #define IOC_IOCFG26_IOMODE_OPENDR 0x04000000 9813 #define IOC_IOCFG26_IOMODE_INV 0x01000000 9814 #define IOC_IOCFG26_IOMODE_NORMAL 0x00000000 9815 9816 // Field: [23] IOEV_AON_PROG2_EN 9817 // 9818 // Event asserted by this IO when edge detection is enabled 9819 // 9820 // 0: Input edge detection does not assert AON_PROG2 event 9821 // 1: Input edge detection asserts AON_PROG2 event 9822 #define IOC_IOCFG26_IOEV_AON_PROG2_EN 0x00800000 9823 #define IOC_IOCFG26_IOEV_AON_PROG2_EN_BITN 23 9824 #define IOC_IOCFG26_IOEV_AON_PROG2_EN_M 0x00800000 9825 #define IOC_IOCFG26_IOEV_AON_PROG2_EN_S 23 9826 9827 // Field: [22] IOEV_AON_PROG1_EN 9828 // 9829 // Event asserted by this IO when edge detection is enabled 9830 // 9831 // 0: Input edge detection does not assert AON_PROG1 event 9832 // 1: Input edge detection asserts AON_PROG1 event 9833 #define IOC_IOCFG26_IOEV_AON_PROG1_EN 0x00400000 9834 #define IOC_IOCFG26_IOEV_AON_PROG1_EN_BITN 22 9835 #define IOC_IOCFG26_IOEV_AON_PROG1_EN_M 0x00400000 9836 #define IOC_IOCFG26_IOEV_AON_PROG1_EN_S 22 9837 9838 // Field: [21] IOEV_AON_PROG0_EN 9839 // 9840 // Event asserted by this IO when edge detection is enabled 9841 // 9842 // 0: Input edge detection does not assert AON_PROG0 event 9843 // 1: Input edge detection asserts AON_PROG0 event 9844 #define IOC_IOCFG26_IOEV_AON_PROG0_EN 0x00200000 9845 #define IOC_IOCFG26_IOEV_AON_PROG0_EN_BITN 21 9846 #define IOC_IOCFG26_IOEV_AON_PROG0_EN_M 0x00200000 9847 #define IOC_IOCFG26_IOEV_AON_PROG0_EN_S 21 9848 9849 // Field: [18] EDGE_IRQ_EN 9850 // 9851 // 0: No interrupt generation 9852 // 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is 9853 // enabled) 9854 #define IOC_IOCFG26_EDGE_IRQ_EN 0x00040000 9855 #define IOC_IOCFG26_EDGE_IRQ_EN_BITN 18 9856 #define IOC_IOCFG26_EDGE_IRQ_EN_M 0x00040000 9857 #define IOC_IOCFG26_EDGE_IRQ_EN_S 18 9858 9859 // Field: [17:16] EDGE_DET 9860 // 9861 // Enable generation of edge detection events on this IO 9862 // ENUMs: 9863 // BOTH Positive and negative edge detection 9864 // POS Positive edge detection 9865 // NEG Negative edge detection 9866 // NONE No edge detection 9867 #define IOC_IOCFG26_EDGE_DET_W 2 9868 #define IOC_IOCFG26_EDGE_DET_M 0x00030000 9869 #define IOC_IOCFG26_EDGE_DET_S 16 9870 #define IOC_IOCFG26_EDGE_DET_BOTH 0x00030000 9871 #define IOC_IOCFG26_EDGE_DET_POS 0x00020000 9872 #define IOC_IOCFG26_EDGE_DET_NEG 0x00010000 9873 #define IOC_IOCFG26_EDGE_DET_NONE 0x00000000 9874 9875 // Field: [14:13] PULL_CTL 9876 // 9877 // Pull control 9878 // ENUMs: 9879 // DIS No pull 9880 // UP Pull up 9881 // DWN Pull down 9882 #define IOC_IOCFG26_PULL_CTL_W 2 9883 #define IOC_IOCFG26_PULL_CTL_M 0x00006000 9884 #define IOC_IOCFG26_PULL_CTL_S 13 9885 #define IOC_IOCFG26_PULL_CTL_DIS 0x00006000 9886 #define IOC_IOCFG26_PULL_CTL_UP 0x00004000 9887 #define IOC_IOCFG26_PULL_CTL_DWN 0x00002000 9888 9889 // Field: [12] SLEW_RED 9890 // 9891 // 0: Normal slew rate 9892 // 1: Enables reduced slew rate in output driver. 9893 #define IOC_IOCFG26_SLEW_RED 0x00001000 9894 #define IOC_IOCFG26_SLEW_RED_BITN 12 9895 #define IOC_IOCFG26_SLEW_RED_M 0x00001000 9896 #define IOC_IOCFG26_SLEW_RED_S 12 9897 9898 // Field: [11:10] IOCURR 9899 // 9900 // Selects IO current mode of this IO. 9901 // ENUMs: 9902 // 4_8MA Extended-Current (EC) mode: Min 8 mA for double 9903 // drive strength IOs (min 4 mA for normal IOs) 9904 // when IOSTR is set to AUTO 9905 // 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set 9906 // to AUTO 9907 // 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set 9908 // to AUTO 9909 #define IOC_IOCFG26_IOCURR_W 2 9910 #define IOC_IOCFG26_IOCURR_M 0x00000C00 9911 #define IOC_IOCFG26_IOCURR_S 10 9912 #define IOC_IOCFG26_IOCURR_4_8MA 0x00000800 9913 #define IOC_IOCFG26_IOCURR_4MA 0x00000400 9914 #define IOC_IOCFG26_IOCURR_2MA 0x00000000 9915 9916 // Field: [9:8] IOSTR 9917 // 9918 // Select source for drive strength control of this IO. 9919 // This setting controls the drive strength of the Low-Current (LC) mode. 9920 // Higher drive strength can be selected in IOCURR 9921 // ENUMs: 9922 // MAX Maximum drive strength, controlled by 9923 // AON_IOC:IOSTRMAX (min 2 mA @1.8V with default 9924 // values) 9925 // MED Medium drive strength, controlled by 9926 // AON_IOC:IOSTRMED (min 2 mA @2.5V with default 9927 // values) 9928 // MIN Minimum drive strength, controlled by 9929 // AON_IOC:IOSTRMIN (min 2 mA @3.3V with default 9930 // values) 9931 // AUTO Automatic drive strength, controlled by AON BATMON 9932 // based on battery voltage. (min 2 mA @VDDS) 9933 #define IOC_IOCFG26_IOSTR_W 2 9934 #define IOC_IOCFG26_IOSTR_M 0x00000300 9935 #define IOC_IOCFG26_IOSTR_S 8 9936 #define IOC_IOCFG26_IOSTR_MAX 0x00000300 9937 #define IOC_IOCFG26_IOSTR_MED 0x00000200 9938 #define IOC_IOCFG26_IOSTR_MIN 0x00000100 9939 #define IOC_IOCFG26_IOSTR_AUTO 0x00000000 9940 9941 // Field: [7] IOEV_RTC_EN 9942 // 9943 // Event asserted by this IO when edge detection is enabled 9944 // 9945 // 0: Input edge detection does not assert RTC event 9946 // 1: Input edge detection asserts RTC event 9947 #define IOC_IOCFG26_IOEV_RTC_EN 0x00000080 9948 #define IOC_IOCFG26_IOEV_RTC_EN_BITN 7 9949 #define IOC_IOCFG26_IOEV_RTC_EN_M 0x00000080 9950 #define IOC_IOCFG26_IOEV_RTC_EN_S 7 9951 9952 // Field: [6] IOEV_MCU_WU_EN 9953 // 9954 // Event asserted by this IO when edge detection is enabled 9955 // 9956 // 0: Input edge detection does not assert MCU_WU event 9957 // 1: Input edge detection asserts MCU_WU event 9958 #define IOC_IOCFG26_IOEV_MCU_WU_EN 0x00000040 9959 #define IOC_IOCFG26_IOEV_MCU_WU_EN_BITN 6 9960 #define IOC_IOCFG26_IOEV_MCU_WU_EN_M 0x00000040 9961 #define IOC_IOCFG26_IOEV_MCU_WU_EN_S 6 9962 9963 // Field: [5:0] PORT_ID 9964 // 9965 // Selects usage for DIO26 9966 // Note: This field should not be written other than the times when PORT_ID 9967 // value is specifically required to change. 9968 // ENUMs: 9969 // RFC_SMI_CL_IN RF Core SMI Command Link In 9970 // RFC_SMI_CL_OUT RF Core SMI Command Link Out 9971 // RFC_SMI_DL_IN RF Core SMI Data Link In 9972 // RFC_SMI_DL_OUT RF Core SMI Data Link Out 9973 // RFC_GPI1 RF Core Data In 1 9974 // RFC_GPI0 RF Core Data In 0 9975 // RFC_GPO3 RF Core Data Out 3 9976 // RFC_GPO2 RF Core Data Out 2 9977 // RFC_GPO1 RF Core Data Out 1 9978 // RFC_GPO0 RF Core Data Out 0 9979 // RFC_TRC RF Core Trace 9980 // I2S_MCLK I2S MCLK 9981 // I2S_BCLK I2S BCLK 9982 // I2S_WCLK I2S WCLK 9983 // I2S_AD1 I2S Data 1 9984 // I2S_AD0 I2S Data 0 9985 // SSI1_CLK SSI1 CLK 9986 // SSI1_FSS SSI1 FSS 9987 // SSI1_TX SSI1 TX 9988 // SSI1_RX SSI1 RX 9989 // CPU_SWV CPU SWV 9990 // PORT_EVENT7 PORT EVENT 7 9991 // Can be used as a general 9992 // purpose IO event by selecting it through 9993 // registers in the EVENT module, for example 9994 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 9995 // and so on 9996 // PORT_EVENT6 PORT EVENT 6 9997 // Can be used as a general 9998 // purpose IO event by selecting it through 9999 // registers in the EVENT module, for example 10000 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 10001 // and so on 10002 // PORT_EVENT5 PORT EVENT 5 10003 // Can be used as a general 10004 // purpose IO event by selecting it through 10005 // registers in the EVENT module, for example 10006 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 10007 // and so on 10008 // PORT_EVENT4 PORT EVENT 4 10009 // Can be used as a general 10010 // purpose IO event by selecting it through 10011 // registers in the EVENT module, for example 10012 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 10013 // and so on 10014 // PORT_EVENT3 PORT EVENT 3 10015 // Can be used as a general 10016 // purpose IO event by selecting it through 10017 // registers in the EVENT module, for example 10018 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 10019 // and so on 10020 // PORT_EVENT2 PORT EVENT 2 10021 // Can be used as a general 10022 // purpose IO event by selecting it through 10023 // registers in the EVENT module, for example 10024 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 10025 // and so on 10026 // PORT_EVENT1 PORT EVENT 1 10027 // Can be used as a general 10028 // purpose IO event by selecting it through 10029 // registers in the EVENT module, for example 10030 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 10031 // and so on 10032 // PORT_EVENT0 PORT EVENT 0 10033 // Can be used as a general 10034 // purpose IO event by selecting it through 10035 // registers in the EVENT module, for example 10036 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 10037 // and so on 10038 // UART1_RTS UART1 RTS 10039 // UART1_CTS UART1 CTS 10040 // UART1_TX UART1 TX 10041 // UART1_RX UART1 RX 10042 // UART0_RTS UART0 RTS 10043 // UART0_CTS UART0 CTS 10044 // UART0_TX UART0 TX 10045 // UART0_RX UART0 RX 10046 // I2C_MSSCL I2C Clock 10047 // I2C_MSSDA I2C Data 10048 // SSI0_CLK SSI0 CLK 10049 // SSI0_FSS SSI0 FSS 10050 // SSI0_TX SSI0 TX 10051 // SSI0_RX SSI0 RX 10052 // AUX_IO AUX IO 10053 // AON_CLK32K AON 32 KHz clock (SCLK_LF) 10054 // GPIO General Purpose IO 10055 #define IOC_IOCFG26_PORT_ID_W 6 10056 #define IOC_IOCFG26_PORT_ID_M 0x0000003F 10057 #define IOC_IOCFG26_PORT_ID_S 0 10058 #define IOC_IOCFG26_PORT_ID_RFC_SMI_CL_IN 0x00000038 10059 #define IOC_IOCFG26_PORT_ID_RFC_SMI_CL_OUT 0x00000037 10060 #define IOC_IOCFG26_PORT_ID_RFC_SMI_DL_IN 0x00000036 10061 #define IOC_IOCFG26_PORT_ID_RFC_SMI_DL_OUT 0x00000035 10062 #define IOC_IOCFG26_PORT_ID_RFC_GPI1 0x00000034 10063 #define IOC_IOCFG26_PORT_ID_RFC_GPI0 0x00000033 10064 #define IOC_IOCFG26_PORT_ID_RFC_GPO3 0x00000032 10065 #define IOC_IOCFG26_PORT_ID_RFC_GPO2 0x00000031 10066 #define IOC_IOCFG26_PORT_ID_RFC_GPO1 0x00000030 10067 #define IOC_IOCFG26_PORT_ID_RFC_GPO0 0x0000002F 10068 #define IOC_IOCFG26_PORT_ID_RFC_TRC 0x0000002E 10069 #define IOC_IOCFG26_PORT_ID_I2S_MCLK 0x00000029 10070 #define IOC_IOCFG26_PORT_ID_I2S_BCLK 0x00000028 10071 #define IOC_IOCFG26_PORT_ID_I2S_WCLK 0x00000027 10072 #define IOC_IOCFG26_PORT_ID_I2S_AD1 0x00000026 10073 #define IOC_IOCFG26_PORT_ID_I2S_AD0 0x00000025 10074 #define IOC_IOCFG26_PORT_ID_SSI1_CLK 0x00000024 10075 #define IOC_IOCFG26_PORT_ID_SSI1_FSS 0x00000023 10076 #define IOC_IOCFG26_PORT_ID_SSI1_TX 0x00000022 10077 #define IOC_IOCFG26_PORT_ID_SSI1_RX 0x00000021 10078 #define IOC_IOCFG26_PORT_ID_CPU_SWV 0x00000020 10079 #define IOC_IOCFG26_PORT_ID_PORT_EVENT7 0x0000001E 10080 #define IOC_IOCFG26_PORT_ID_PORT_EVENT6 0x0000001D 10081 #define IOC_IOCFG26_PORT_ID_PORT_EVENT5 0x0000001C 10082 #define IOC_IOCFG26_PORT_ID_PORT_EVENT4 0x0000001B 10083 #define IOC_IOCFG26_PORT_ID_PORT_EVENT3 0x0000001A 10084 #define IOC_IOCFG26_PORT_ID_PORT_EVENT2 0x00000019 10085 #define IOC_IOCFG26_PORT_ID_PORT_EVENT1 0x00000018 10086 #define IOC_IOCFG26_PORT_ID_PORT_EVENT0 0x00000017 10087 #define IOC_IOCFG26_PORT_ID_UART1_RTS 0x00000016 10088 #define IOC_IOCFG26_PORT_ID_UART1_CTS 0x00000015 10089 #define IOC_IOCFG26_PORT_ID_UART1_TX 0x00000014 10090 #define IOC_IOCFG26_PORT_ID_UART1_RX 0x00000013 10091 #define IOC_IOCFG26_PORT_ID_UART0_RTS 0x00000012 10092 #define IOC_IOCFG26_PORT_ID_UART0_CTS 0x00000011 10093 #define IOC_IOCFG26_PORT_ID_UART0_TX 0x00000010 10094 #define IOC_IOCFG26_PORT_ID_UART0_RX 0x0000000F 10095 #define IOC_IOCFG26_PORT_ID_I2C_MSSCL 0x0000000E 10096 #define IOC_IOCFG26_PORT_ID_I2C_MSSDA 0x0000000D 10097 #define IOC_IOCFG26_PORT_ID_SSI0_CLK 0x0000000C 10098 #define IOC_IOCFG26_PORT_ID_SSI0_FSS 0x0000000B 10099 #define IOC_IOCFG26_PORT_ID_SSI0_TX 0x0000000A 10100 #define IOC_IOCFG26_PORT_ID_SSI0_RX 0x00000009 10101 #define IOC_IOCFG26_PORT_ID_AUX_IO 0x00000008 10102 #define IOC_IOCFG26_PORT_ID_AON_CLK32K 0x00000007 10103 #define IOC_IOCFG26_PORT_ID_GPIO 0x00000000 10104 10105 //***************************************************************************** 10106 // 10107 // Register: IOC_O_IOCFG27 10108 // 10109 //***************************************************************************** 10110 // Field: [30] HYST_EN 10111 // 10112 // 0: Input hysteresis disable 10113 // 1: Input hysteresis enable 10114 #define IOC_IOCFG27_HYST_EN 0x40000000 10115 #define IOC_IOCFG27_HYST_EN_BITN 30 10116 #define IOC_IOCFG27_HYST_EN_M 0x40000000 10117 #define IOC_IOCFG27_HYST_EN_S 30 10118 10119 // Field: [29] IE 10120 // 10121 // 0: Input disabled 10122 // 1: Input enabled 10123 // 10124 // Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be 10125 // ignored. 10126 #define IOC_IOCFG27_IE 0x20000000 10127 #define IOC_IOCFG27_IE_BITN 29 10128 #define IOC_IOCFG27_IE_M 0x20000000 10129 #define IOC_IOCFG27_IE_S 29 10130 10131 // Field: [28:27] WU_CFG 10132 // 10133 // If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or 10134 // >0x08: 10135 // 10136 // 00: No wake-up 10137 // 01: No wake-up 10138 // 10: Wakes up from shutdown if this pad is going low. 10139 // 11: Wakes up from shutdown if this pad is going high. 10140 // 10141 // If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, 10142 // this register only sets wakeup enable or not. 10143 // 10144 // 00, 01: Wakeup disabled 10145 // 10, 11: Wakeup enabled 10146 // 10147 // Polarity is controlled from AON registers. 10148 // 10149 // Note:When the MSB is set, the IOC will deactivate the output enable for the 10150 // DIO. 10151 #define IOC_IOCFG27_WU_CFG_W 2 10152 #define IOC_IOCFG27_WU_CFG_M 0x18000000 10153 #define IOC_IOCFG27_WU_CFG_S 27 10154 10155 // Field: [26:24] IOMODE 10156 // 10157 // IO Mode 10158 // Not applicable for IO configured for AON periph. signals and AUX PORT_ID 10159 // 0x01-0x08 10160 // AUX has its own open_source/drain configuration. 10161 // 10162 // 0x2: Reserved. Undefined behavior. 10163 // 0x3: Reserved. Undefined behavior. 10164 // ENUMs: 10165 // OPENSRC_INV Open Source 10166 // Inverted input / output 10167 // OPENSRC Open Source 10168 // Normal input / output 10169 // OPENDR_INV Open Drain 10170 // Inverted input / output 10171 // OPENDR Open Drain, 10172 // Normal input / output 10173 // INV Inverted input / ouput 10174 // NORMAL Normal input / output 10175 #define IOC_IOCFG27_IOMODE_W 3 10176 #define IOC_IOCFG27_IOMODE_M 0x07000000 10177 #define IOC_IOCFG27_IOMODE_S 24 10178 #define IOC_IOCFG27_IOMODE_OPENSRC_INV 0x07000000 10179 #define IOC_IOCFG27_IOMODE_OPENSRC 0x06000000 10180 #define IOC_IOCFG27_IOMODE_OPENDR_INV 0x05000000 10181 #define IOC_IOCFG27_IOMODE_OPENDR 0x04000000 10182 #define IOC_IOCFG27_IOMODE_INV 0x01000000 10183 #define IOC_IOCFG27_IOMODE_NORMAL 0x00000000 10184 10185 // Field: [23] IOEV_AON_PROG2_EN 10186 // 10187 // Event asserted by this IO when edge detection is enabled 10188 // 10189 // 0: Input edge detection does not assert AON_PROG2 event 10190 // 1: Input edge detection asserts AON_PROG2 event 10191 #define IOC_IOCFG27_IOEV_AON_PROG2_EN 0x00800000 10192 #define IOC_IOCFG27_IOEV_AON_PROG2_EN_BITN 23 10193 #define IOC_IOCFG27_IOEV_AON_PROG2_EN_M 0x00800000 10194 #define IOC_IOCFG27_IOEV_AON_PROG2_EN_S 23 10195 10196 // Field: [22] IOEV_AON_PROG1_EN 10197 // 10198 // Event asserted by this IO when edge detection is enabled 10199 // 10200 // 0: Input edge detection does not assert AON_PROG1 event 10201 // 1: Input edge detection asserts AON_PROG1 event 10202 #define IOC_IOCFG27_IOEV_AON_PROG1_EN 0x00400000 10203 #define IOC_IOCFG27_IOEV_AON_PROG1_EN_BITN 22 10204 #define IOC_IOCFG27_IOEV_AON_PROG1_EN_M 0x00400000 10205 #define IOC_IOCFG27_IOEV_AON_PROG1_EN_S 22 10206 10207 // Field: [21] IOEV_AON_PROG0_EN 10208 // 10209 // Event asserted by this IO when edge detection is enabled 10210 // 10211 // 0: Input edge detection does not assert AON_PROG0 event 10212 // 1: Input edge detection asserts AON_PROG0 event 10213 #define IOC_IOCFG27_IOEV_AON_PROG0_EN 0x00200000 10214 #define IOC_IOCFG27_IOEV_AON_PROG0_EN_BITN 21 10215 #define IOC_IOCFG27_IOEV_AON_PROG0_EN_M 0x00200000 10216 #define IOC_IOCFG27_IOEV_AON_PROG0_EN_S 21 10217 10218 // Field: [18] EDGE_IRQ_EN 10219 // 10220 // 0: No interrupt generation 10221 // 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is 10222 // enabled) 10223 #define IOC_IOCFG27_EDGE_IRQ_EN 0x00040000 10224 #define IOC_IOCFG27_EDGE_IRQ_EN_BITN 18 10225 #define IOC_IOCFG27_EDGE_IRQ_EN_M 0x00040000 10226 #define IOC_IOCFG27_EDGE_IRQ_EN_S 18 10227 10228 // Field: [17:16] EDGE_DET 10229 // 10230 // Enable generation of edge detection events on this IO 10231 // ENUMs: 10232 // BOTH Positive and negative edge detection 10233 // POS Positive edge detection 10234 // NEG Negative edge detection 10235 // NONE No edge detection 10236 #define IOC_IOCFG27_EDGE_DET_W 2 10237 #define IOC_IOCFG27_EDGE_DET_M 0x00030000 10238 #define IOC_IOCFG27_EDGE_DET_S 16 10239 #define IOC_IOCFG27_EDGE_DET_BOTH 0x00030000 10240 #define IOC_IOCFG27_EDGE_DET_POS 0x00020000 10241 #define IOC_IOCFG27_EDGE_DET_NEG 0x00010000 10242 #define IOC_IOCFG27_EDGE_DET_NONE 0x00000000 10243 10244 // Field: [14:13] PULL_CTL 10245 // 10246 // Pull control 10247 // ENUMs: 10248 // DIS No pull 10249 // UP Pull up 10250 // DWN Pull down 10251 #define IOC_IOCFG27_PULL_CTL_W 2 10252 #define IOC_IOCFG27_PULL_CTL_M 0x00006000 10253 #define IOC_IOCFG27_PULL_CTL_S 13 10254 #define IOC_IOCFG27_PULL_CTL_DIS 0x00006000 10255 #define IOC_IOCFG27_PULL_CTL_UP 0x00004000 10256 #define IOC_IOCFG27_PULL_CTL_DWN 0x00002000 10257 10258 // Field: [12] SLEW_RED 10259 // 10260 // 0: Normal slew rate 10261 // 1: Enables reduced slew rate in output driver. 10262 #define IOC_IOCFG27_SLEW_RED 0x00001000 10263 #define IOC_IOCFG27_SLEW_RED_BITN 12 10264 #define IOC_IOCFG27_SLEW_RED_M 0x00001000 10265 #define IOC_IOCFG27_SLEW_RED_S 12 10266 10267 // Field: [11:10] IOCURR 10268 // 10269 // Selects IO current mode of this IO. 10270 // ENUMs: 10271 // 4_8MA Extended-Current (EC) mode: Min 8 mA for double 10272 // drive strength IOs (min 4 mA for normal IOs) 10273 // when IOSTR is set to AUTO 10274 // 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set 10275 // to AUTO 10276 // 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set 10277 // to AUTO 10278 #define IOC_IOCFG27_IOCURR_W 2 10279 #define IOC_IOCFG27_IOCURR_M 0x00000C00 10280 #define IOC_IOCFG27_IOCURR_S 10 10281 #define IOC_IOCFG27_IOCURR_4_8MA 0x00000800 10282 #define IOC_IOCFG27_IOCURR_4MA 0x00000400 10283 #define IOC_IOCFG27_IOCURR_2MA 0x00000000 10284 10285 // Field: [9:8] IOSTR 10286 // 10287 // Select source for drive strength control of this IO. 10288 // This setting controls the drive strength of the Low-Current (LC) mode. 10289 // Higher drive strength can be selected in IOCURR 10290 // ENUMs: 10291 // MAX Maximum drive strength, controlled by 10292 // AON_IOC:IOSTRMAX (min 2 mA @1.8V with default 10293 // values) 10294 // MED Medium drive strength, controlled by 10295 // AON_IOC:IOSTRMED (min 2 mA @2.5V with default 10296 // values) 10297 // MIN Minimum drive strength, controlled by 10298 // AON_IOC:IOSTRMIN (min 2 mA @3.3V with default 10299 // values) 10300 // AUTO Automatic drive strength, controlled by AON BATMON 10301 // based on battery voltage. (min 2 mA @VDDS) 10302 #define IOC_IOCFG27_IOSTR_W 2 10303 #define IOC_IOCFG27_IOSTR_M 0x00000300 10304 #define IOC_IOCFG27_IOSTR_S 8 10305 #define IOC_IOCFG27_IOSTR_MAX 0x00000300 10306 #define IOC_IOCFG27_IOSTR_MED 0x00000200 10307 #define IOC_IOCFG27_IOSTR_MIN 0x00000100 10308 #define IOC_IOCFG27_IOSTR_AUTO 0x00000000 10309 10310 // Field: [7] IOEV_RTC_EN 10311 // 10312 // Event asserted by this IO when edge detection is enabled 10313 // 10314 // 0: Input edge detection does not assert RTC event 10315 // 1: Input edge detection asserts RTC event 10316 #define IOC_IOCFG27_IOEV_RTC_EN 0x00000080 10317 #define IOC_IOCFG27_IOEV_RTC_EN_BITN 7 10318 #define IOC_IOCFG27_IOEV_RTC_EN_M 0x00000080 10319 #define IOC_IOCFG27_IOEV_RTC_EN_S 7 10320 10321 // Field: [6] IOEV_MCU_WU_EN 10322 // 10323 // Event asserted by this IO when edge detection is enabled 10324 // 10325 // 0: Input edge detection does not assert MCU_WU event 10326 // 1: Input edge detection asserts MCU_WU event 10327 #define IOC_IOCFG27_IOEV_MCU_WU_EN 0x00000040 10328 #define IOC_IOCFG27_IOEV_MCU_WU_EN_BITN 6 10329 #define IOC_IOCFG27_IOEV_MCU_WU_EN_M 0x00000040 10330 #define IOC_IOCFG27_IOEV_MCU_WU_EN_S 6 10331 10332 // Field: [5:0] PORT_ID 10333 // 10334 // Selects usage for DIO27 10335 // Note: This field should not be written other than the times when PORT_ID 10336 // value is specifically required to change. 10337 // ENUMs: 10338 // RFC_SMI_CL_IN RF Core SMI Command Link In 10339 // RFC_SMI_CL_OUT RF Core SMI Command Link Out 10340 // RFC_SMI_DL_IN RF Core SMI Data Link In 10341 // RFC_SMI_DL_OUT RF Core SMI Data Link Out 10342 // RFC_GPI1 RF Core Data In 1 10343 // RFC_GPI0 RF Core Data In 0 10344 // RFC_GPO3 RF Core Data Out 3 10345 // RFC_GPO2 RF Core Data Out 2 10346 // RFC_GPO1 RF Core Data Out 1 10347 // RFC_GPO0 RF Core Data Out 0 10348 // RFC_TRC RF Core Trace 10349 // I2S_MCLK I2S MCLK 10350 // I2S_BCLK I2S BCLK 10351 // I2S_WCLK I2S WCLK 10352 // I2S_AD1 I2S Data 1 10353 // I2S_AD0 I2S Data 0 10354 // SSI1_CLK SSI1 CLK 10355 // SSI1_FSS SSI1 FSS 10356 // SSI1_TX SSI1 TX 10357 // SSI1_RX SSI1 RX 10358 // CPU_SWV CPU SWV 10359 // PORT_EVENT7 PORT EVENT 7 10360 // Can be used as a general 10361 // purpose IO event by selecting it through 10362 // registers in the EVENT module, for example 10363 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 10364 // and so on 10365 // PORT_EVENT6 PORT EVENT 6 10366 // Can be used as a general 10367 // purpose IO event by selecting it through 10368 // registers in the EVENT module, for example 10369 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 10370 // and so on 10371 // PORT_EVENT5 PORT EVENT 5 10372 // Can be used as a general 10373 // purpose IO event by selecting it through 10374 // registers in the EVENT module, for example 10375 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 10376 // and so on 10377 // PORT_EVENT4 PORT EVENT 4 10378 // Can be used as a general 10379 // purpose IO event by selecting it through 10380 // registers in the EVENT module, for example 10381 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 10382 // and so on 10383 // PORT_EVENT3 PORT EVENT 3 10384 // Can be used as a general 10385 // purpose IO event by selecting it through 10386 // registers in the EVENT module, for example 10387 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 10388 // and so on 10389 // PORT_EVENT2 PORT EVENT 2 10390 // Can be used as a general 10391 // purpose IO event by selecting it through 10392 // registers in the EVENT module, for example 10393 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 10394 // and so on 10395 // PORT_EVENT1 PORT EVENT 1 10396 // Can be used as a general 10397 // purpose IO event by selecting it through 10398 // registers in the EVENT module, for example 10399 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 10400 // and so on 10401 // PORT_EVENT0 PORT EVENT 0 10402 // Can be used as a general 10403 // purpose IO event by selecting it through 10404 // registers in the EVENT module, for example 10405 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 10406 // and so on 10407 // UART1_RTS UART1 RTS 10408 // UART1_CTS UART1 CTS 10409 // UART1_TX UART1 TX 10410 // UART1_RX UART1 RX 10411 // UART0_RTS UART0 RTS 10412 // UART0_CTS UART0 CTS 10413 // UART0_TX UART0 TX 10414 // UART0_RX UART0 RX 10415 // I2C_MSSCL I2C Clock 10416 // I2C_MSSDA I2C Data 10417 // SSI0_CLK SSI0 CLK 10418 // SSI0_FSS SSI0 FSS 10419 // SSI0_TX SSI0 TX 10420 // SSI0_RX SSI0 RX 10421 // AUX_IO AUX IO 10422 // AON_CLK32K AON 32 KHz clock (SCLK_LF) 10423 // GPIO General Purpose IO 10424 #define IOC_IOCFG27_PORT_ID_W 6 10425 #define IOC_IOCFG27_PORT_ID_M 0x0000003F 10426 #define IOC_IOCFG27_PORT_ID_S 0 10427 #define IOC_IOCFG27_PORT_ID_RFC_SMI_CL_IN 0x00000038 10428 #define IOC_IOCFG27_PORT_ID_RFC_SMI_CL_OUT 0x00000037 10429 #define IOC_IOCFG27_PORT_ID_RFC_SMI_DL_IN 0x00000036 10430 #define IOC_IOCFG27_PORT_ID_RFC_SMI_DL_OUT 0x00000035 10431 #define IOC_IOCFG27_PORT_ID_RFC_GPI1 0x00000034 10432 #define IOC_IOCFG27_PORT_ID_RFC_GPI0 0x00000033 10433 #define IOC_IOCFG27_PORT_ID_RFC_GPO3 0x00000032 10434 #define IOC_IOCFG27_PORT_ID_RFC_GPO2 0x00000031 10435 #define IOC_IOCFG27_PORT_ID_RFC_GPO1 0x00000030 10436 #define IOC_IOCFG27_PORT_ID_RFC_GPO0 0x0000002F 10437 #define IOC_IOCFG27_PORT_ID_RFC_TRC 0x0000002E 10438 #define IOC_IOCFG27_PORT_ID_I2S_MCLK 0x00000029 10439 #define IOC_IOCFG27_PORT_ID_I2S_BCLK 0x00000028 10440 #define IOC_IOCFG27_PORT_ID_I2S_WCLK 0x00000027 10441 #define IOC_IOCFG27_PORT_ID_I2S_AD1 0x00000026 10442 #define IOC_IOCFG27_PORT_ID_I2S_AD0 0x00000025 10443 #define IOC_IOCFG27_PORT_ID_SSI1_CLK 0x00000024 10444 #define IOC_IOCFG27_PORT_ID_SSI1_FSS 0x00000023 10445 #define IOC_IOCFG27_PORT_ID_SSI1_TX 0x00000022 10446 #define IOC_IOCFG27_PORT_ID_SSI1_RX 0x00000021 10447 #define IOC_IOCFG27_PORT_ID_CPU_SWV 0x00000020 10448 #define IOC_IOCFG27_PORT_ID_PORT_EVENT7 0x0000001E 10449 #define IOC_IOCFG27_PORT_ID_PORT_EVENT6 0x0000001D 10450 #define IOC_IOCFG27_PORT_ID_PORT_EVENT5 0x0000001C 10451 #define IOC_IOCFG27_PORT_ID_PORT_EVENT4 0x0000001B 10452 #define IOC_IOCFG27_PORT_ID_PORT_EVENT3 0x0000001A 10453 #define IOC_IOCFG27_PORT_ID_PORT_EVENT2 0x00000019 10454 #define IOC_IOCFG27_PORT_ID_PORT_EVENT1 0x00000018 10455 #define IOC_IOCFG27_PORT_ID_PORT_EVENT0 0x00000017 10456 #define IOC_IOCFG27_PORT_ID_UART1_RTS 0x00000016 10457 #define IOC_IOCFG27_PORT_ID_UART1_CTS 0x00000015 10458 #define IOC_IOCFG27_PORT_ID_UART1_TX 0x00000014 10459 #define IOC_IOCFG27_PORT_ID_UART1_RX 0x00000013 10460 #define IOC_IOCFG27_PORT_ID_UART0_RTS 0x00000012 10461 #define IOC_IOCFG27_PORT_ID_UART0_CTS 0x00000011 10462 #define IOC_IOCFG27_PORT_ID_UART0_TX 0x00000010 10463 #define IOC_IOCFG27_PORT_ID_UART0_RX 0x0000000F 10464 #define IOC_IOCFG27_PORT_ID_I2C_MSSCL 0x0000000E 10465 #define IOC_IOCFG27_PORT_ID_I2C_MSSDA 0x0000000D 10466 #define IOC_IOCFG27_PORT_ID_SSI0_CLK 0x0000000C 10467 #define IOC_IOCFG27_PORT_ID_SSI0_FSS 0x0000000B 10468 #define IOC_IOCFG27_PORT_ID_SSI0_TX 0x0000000A 10469 #define IOC_IOCFG27_PORT_ID_SSI0_RX 0x00000009 10470 #define IOC_IOCFG27_PORT_ID_AUX_IO 0x00000008 10471 #define IOC_IOCFG27_PORT_ID_AON_CLK32K 0x00000007 10472 #define IOC_IOCFG27_PORT_ID_GPIO 0x00000000 10473 10474 //***************************************************************************** 10475 // 10476 // Register: IOC_O_IOCFG28 10477 // 10478 //***************************************************************************** 10479 // Field: [30] HYST_EN 10480 // 10481 // 0: Input hysteresis disable 10482 // 1: Input hysteresis enable 10483 #define IOC_IOCFG28_HYST_EN 0x40000000 10484 #define IOC_IOCFG28_HYST_EN_BITN 30 10485 #define IOC_IOCFG28_HYST_EN_M 0x40000000 10486 #define IOC_IOCFG28_HYST_EN_S 30 10487 10488 // Field: [29] IE 10489 // 10490 // 0: Input disabled 10491 // 1: Input enabled 10492 // 10493 // Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be 10494 // ignored. 10495 #define IOC_IOCFG28_IE 0x20000000 10496 #define IOC_IOCFG28_IE_BITN 29 10497 #define IOC_IOCFG28_IE_M 0x20000000 10498 #define IOC_IOCFG28_IE_S 29 10499 10500 // Field: [28:27] WU_CFG 10501 // 10502 // If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or 10503 // >0x08: 10504 // 10505 // 00: No wake-up 10506 // 01: No wake-up 10507 // 10: Wakes up from shutdown if this pad is going low. 10508 // 11: Wakes up from shutdown if this pad is going high. 10509 // 10510 // If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, 10511 // this register only sets wakeup enable or not. 10512 // 10513 // 00, 01: Wakeup disabled 10514 // 10, 11: Wakeup enabled 10515 // 10516 // Polarity is controlled from AON registers. 10517 // 10518 // Note:When the MSB is set, the IOC will deactivate the output enable for the 10519 // DIO. 10520 #define IOC_IOCFG28_WU_CFG_W 2 10521 #define IOC_IOCFG28_WU_CFG_M 0x18000000 10522 #define IOC_IOCFG28_WU_CFG_S 27 10523 10524 // Field: [26:24] IOMODE 10525 // 10526 // IO Mode 10527 // Not applicable for IO configured for AON periph. signals and AUX PORT_ID 10528 // 0x01-0x08 10529 // AUX has its own open_source/drain configuration. 10530 // 10531 // 0x2: Reserved. Undefined behavior. 10532 // 0x3: Reserved. Undefined behavior. 10533 // ENUMs: 10534 // OPENSRC_INV Open Source 10535 // Inverted input / output 10536 // OPENSRC Open Source 10537 // Normal input / output 10538 // OPENDR_INV Open Drain 10539 // Inverted input / output 10540 // OPENDR Open Drain, 10541 // Normal input / output 10542 // INV Inverted input / ouput 10543 // NORMAL Normal input / output 10544 #define IOC_IOCFG28_IOMODE_W 3 10545 #define IOC_IOCFG28_IOMODE_M 0x07000000 10546 #define IOC_IOCFG28_IOMODE_S 24 10547 #define IOC_IOCFG28_IOMODE_OPENSRC_INV 0x07000000 10548 #define IOC_IOCFG28_IOMODE_OPENSRC 0x06000000 10549 #define IOC_IOCFG28_IOMODE_OPENDR_INV 0x05000000 10550 #define IOC_IOCFG28_IOMODE_OPENDR 0x04000000 10551 #define IOC_IOCFG28_IOMODE_INV 0x01000000 10552 #define IOC_IOCFG28_IOMODE_NORMAL 0x00000000 10553 10554 // Field: [23] IOEV_AON_PROG2_EN 10555 // 10556 // Event asserted by this IO when edge detection is enabled 10557 // 10558 // 0: Input edge detection does not assert AON_PROG2 event 10559 // 1: Input edge detection asserts AON_PROG2 event 10560 #define IOC_IOCFG28_IOEV_AON_PROG2_EN 0x00800000 10561 #define IOC_IOCFG28_IOEV_AON_PROG2_EN_BITN 23 10562 #define IOC_IOCFG28_IOEV_AON_PROG2_EN_M 0x00800000 10563 #define IOC_IOCFG28_IOEV_AON_PROG2_EN_S 23 10564 10565 // Field: [22] IOEV_AON_PROG1_EN 10566 // 10567 // Event asserted by this IO when edge detection is enabled 10568 // 10569 // 0: Input edge detection does not assert AON_PROG1 event 10570 // 1: Input edge detection asserts AON_PROG1 event 10571 #define IOC_IOCFG28_IOEV_AON_PROG1_EN 0x00400000 10572 #define IOC_IOCFG28_IOEV_AON_PROG1_EN_BITN 22 10573 #define IOC_IOCFG28_IOEV_AON_PROG1_EN_M 0x00400000 10574 #define IOC_IOCFG28_IOEV_AON_PROG1_EN_S 22 10575 10576 // Field: [21] IOEV_AON_PROG0_EN 10577 // 10578 // Event asserted by this IO when edge detection is enabled 10579 // 10580 // 0: Input edge detection does not assert AON_PROG0 event 10581 // 1: Input edge detection asserts AON_PROG0 event 10582 #define IOC_IOCFG28_IOEV_AON_PROG0_EN 0x00200000 10583 #define IOC_IOCFG28_IOEV_AON_PROG0_EN_BITN 21 10584 #define IOC_IOCFG28_IOEV_AON_PROG0_EN_M 0x00200000 10585 #define IOC_IOCFG28_IOEV_AON_PROG0_EN_S 21 10586 10587 // Field: [18] EDGE_IRQ_EN 10588 // 10589 // 0: No interrupt generation 10590 // 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is 10591 // enabled) 10592 #define IOC_IOCFG28_EDGE_IRQ_EN 0x00040000 10593 #define IOC_IOCFG28_EDGE_IRQ_EN_BITN 18 10594 #define IOC_IOCFG28_EDGE_IRQ_EN_M 0x00040000 10595 #define IOC_IOCFG28_EDGE_IRQ_EN_S 18 10596 10597 // Field: [17:16] EDGE_DET 10598 // 10599 // Enable generation of edge detection events on this IO 10600 // ENUMs: 10601 // BOTH Positive and negative edge detection 10602 // POS Positive edge detection 10603 // NEG Negative edge detection 10604 // NONE No edge detection 10605 #define IOC_IOCFG28_EDGE_DET_W 2 10606 #define IOC_IOCFG28_EDGE_DET_M 0x00030000 10607 #define IOC_IOCFG28_EDGE_DET_S 16 10608 #define IOC_IOCFG28_EDGE_DET_BOTH 0x00030000 10609 #define IOC_IOCFG28_EDGE_DET_POS 0x00020000 10610 #define IOC_IOCFG28_EDGE_DET_NEG 0x00010000 10611 #define IOC_IOCFG28_EDGE_DET_NONE 0x00000000 10612 10613 // Field: [14:13] PULL_CTL 10614 // 10615 // Pull control 10616 // ENUMs: 10617 // DIS No pull 10618 // UP Pull up 10619 // DWN Pull down 10620 #define IOC_IOCFG28_PULL_CTL_W 2 10621 #define IOC_IOCFG28_PULL_CTL_M 0x00006000 10622 #define IOC_IOCFG28_PULL_CTL_S 13 10623 #define IOC_IOCFG28_PULL_CTL_DIS 0x00006000 10624 #define IOC_IOCFG28_PULL_CTL_UP 0x00004000 10625 #define IOC_IOCFG28_PULL_CTL_DWN 0x00002000 10626 10627 // Field: [12] SLEW_RED 10628 // 10629 // 0: Normal slew rate 10630 // 1: Enables reduced slew rate in output driver. 10631 #define IOC_IOCFG28_SLEW_RED 0x00001000 10632 #define IOC_IOCFG28_SLEW_RED_BITN 12 10633 #define IOC_IOCFG28_SLEW_RED_M 0x00001000 10634 #define IOC_IOCFG28_SLEW_RED_S 12 10635 10636 // Field: [11:10] IOCURR 10637 // 10638 // Selects IO current mode of this IO. 10639 // ENUMs: 10640 // 4_8MA Extended-Current (EC) mode: Min 8 mA for double 10641 // drive strength IOs (min 4 mA for normal IOs) 10642 // when IOSTR is set to AUTO 10643 // 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set 10644 // to AUTO 10645 // 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set 10646 // to AUTO 10647 #define IOC_IOCFG28_IOCURR_W 2 10648 #define IOC_IOCFG28_IOCURR_M 0x00000C00 10649 #define IOC_IOCFG28_IOCURR_S 10 10650 #define IOC_IOCFG28_IOCURR_4_8MA 0x00000800 10651 #define IOC_IOCFG28_IOCURR_4MA 0x00000400 10652 #define IOC_IOCFG28_IOCURR_2MA 0x00000000 10653 10654 // Field: [9:8] IOSTR 10655 // 10656 // Select source for drive strength control of this IO. 10657 // This setting controls the drive strength of the Low-Current (LC) mode. 10658 // Higher drive strength can be selected in IOCURR 10659 // ENUMs: 10660 // MAX Maximum drive strength, controlled by 10661 // AON_IOC:IOSTRMAX (min 2 mA @1.8V with default 10662 // values) 10663 // MED Medium drive strength, controlled by 10664 // AON_IOC:IOSTRMED (min 2 mA @2.5V with default 10665 // values) 10666 // MIN Minimum drive strength, controlled by 10667 // AON_IOC:IOSTRMIN (min 2 mA @3.3V with default 10668 // values) 10669 // AUTO Automatic drive strength, controlled by AON BATMON 10670 // based on battery voltage. (min 2 mA @VDDS) 10671 #define IOC_IOCFG28_IOSTR_W 2 10672 #define IOC_IOCFG28_IOSTR_M 0x00000300 10673 #define IOC_IOCFG28_IOSTR_S 8 10674 #define IOC_IOCFG28_IOSTR_MAX 0x00000300 10675 #define IOC_IOCFG28_IOSTR_MED 0x00000200 10676 #define IOC_IOCFG28_IOSTR_MIN 0x00000100 10677 #define IOC_IOCFG28_IOSTR_AUTO 0x00000000 10678 10679 // Field: [7] IOEV_RTC_EN 10680 // 10681 // Event asserted by this IO when edge detection is enabled 10682 // 10683 // 0: Input edge detection does not assert RTC event 10684 // 1: Input edge detection asserts RTC event 10685 #define IOC_IOCFG28_IOEV_RTC_EN 0x00000080 10686 #define IOC_IOCFG28_IOEV_RTC_EN_BITN 7 10687 #define IOC_IOCFG28_IOEV_RTC_EN_M 0x00000080 10688 #define IOC_IOCFG28_IOEV_RTC_EN_S 7 10689 10690 // Field: [6] IOEV_MCU_WU_EN 10691 // 10692 // Event asserted by this IO when edge detection is enabled 10693 // 10694 // 0: Input edge detection does not assert MCU_WU event 10695 // 1: Input edge detection asserts MCU_WU event 10696 #define IOC_IOCFG28_IOEV_MCU_WU_EN 0x00000040 10697 #define IOC_IOCFG28_IOEV_MCU_WU_EN_BITN 6 10698 #define IOC_IOCFG28_IOEV_MCU_WU_EN_M 0x00000040 10699 #define IOC_IOCFG28_IOEV_MCU_WU_EN_S 6 10700 10701 // Field: [5:0] PORT_ID 10702 // 10703 // Selects usage for DIO28 10704 // Note: This field should not be written other than the times when PORT_ID 10705 // value is specifically required to change. 10706 // ENUMs: 10707 // RFC_SMI_CL_IN RF Core SMI Command Link In 10708 // RFC_SMI_CL_OUT RF Core SMI Command Link Out 10709 // RFC_SMI_DL_IN RF Core SMI Data Link In 10710 // RFC_SMI_DL_OUT RF Core SMI Data Link Out 10711 // RFC_GPI1 RF Core Data In 1 10712 // RFC_GPI0 RF Core Data In 0 10713 // RFC_GPO3 RF Core Data Out 3 10714 // RFC_GPO2 RF Core Data Out 2 10715 // RFC_GPO1 RF Core Data Out 1 10716 // RFC_GPO0 RF Core Data Out 0 10717 // RFC_TRC RF Core Trace 10718 // I2S_MCLK I2S MCLK 10719 // I2S_BCLK I2S BCLK 10720 // I2S_WCLK I2S WCLK 10721 // I2S_AD1 I2S Data 1 10722 // I2S_AD0 I2S Data 0 10723 // SSI1_CLK SSI1 CLK 10724 // SSI1_FSS SSI1 FSS 10725 // SSI1_TX SSI1 TX 10726 // SSI1_RX SSI1 RX 10727 // CPU_SWV CPU SWV 10728 // PORT_EVENT7 PORT EVENT 7 10729 // Can be used as a general 10730 // purpose IO event by selecting it through 10731 // registers in the EVENT module, for example 10732 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 10733 // and so on 10734 // PORT_EVENT6 PORT EVENT 6 10735 // Can be used as a general 10736 // purpose IO event by selecting it through 10737 // registers in the EVENT module, for example 10738 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 10739 // and so on 10740 // PORT_EVENT5 PORT EVENT 5 10741 // Can be used as a general 10742 // purpose IO event by selecting it through 10743 // registers in the EVENT module, for example 10744 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 10745 // and so on 10746 // PORT_EVENT4 PORT EVENT 4 10747 // Can be used as a general 10748 // purpose IO event by selecting it through 10749 // registers in the EVENT module, for example 10750 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 10751 // and so on 10752 // PORT_EVENT3 PORT EVENT 3 10753 // Can be used as a general 10754 // purpose IO event by selecting it through 10755 // registers in the EVENT module, for example 10756 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 10757 // and so on 10758 // PORT_EVENT2 PORT EVENT 2 10759 // Can be used as a general 10760 // purpose IO event by selecting it through 10761 // registers in the EVENT module, for example 10762 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 10763 // and so on 10764 // PORT_EVENT1 PORT EVENT 1 10765 // Can be used as a general 10766 // purpose IO event by selecting it through 10767 // registers in the EVENT module, for example 10768 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 10769 // and so on 10770 // PORT_EVENT0 PORT EVENT 0 10771 // Can be used as a general 10772 // purpose IO event by selecting it through 10773 // registers in the EVENT module, for example 10774 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 10775 // and so on 10776 // UART1_RTS UART1 RTS 10777 // UART1_CTS UART1 CTS 10778 // UART1_TX UART1 TX 10779 // UART1_RX UART1 RX 10780 // UART0_RTS UART0 RTS 10781 // UART0_CTS UART0 CTS 10782 // UART0_TX UART0 TX 10783 // UART0_RX UART0 RX 10784 // I2C_MSSCL I2C Clock 10785 // I2C_MSSDA I2C Data 10786 // SSI0_CLK SSI0 CLK 10787 // SSI0_FSS SSI0 FSS 10788 // SSI0_TX SSI0 TX 10789 // SSI0_RX SSI0 RX 10790 // AUX_IO AUX IO 10791 // AON_CLK32K AON 32 KHz clock (SCLK_LF) 10792 // GPIO General Purpose IO 10793 #define IOC_IOCFG28_PORT_ID_W 6 10794 #define IOC_IOCFG28_PORT_ID_M 0x0000003F 10795 #define IOC_IOCFG28_PORT_ID_S 0 10796 #define IOC_IOCFG28_PORT_ID_RFC_SMI_CL_IN 0x00000038 10797 #define IOC_IOCFG28_PORT_ID_RFC_SMI_CL_OUT 0x00000037 10798 #define IOC_IOCFG28_PORT_ID_RFC_SMI_DL_IN 0x00000036 10799 #define IOC_IOCFG28_PORT_ID_RFC_SMI_DL_OUT 0x00000035 10800 #define IOC_IOCFG28_PORT_ID_RFC_GPI1 0x00000034 10801 #define IOC_IOCFG28_PORT_ID_RFC_GPI0 0x00000033 10802 #define IOC_IOCFG28_PORT_ID_RFC_GPO3 0x00000032 10803 #define IOC_IOCFG28_PORT_ID_RFC_GPO2 0x00000031 10804 #define IOC_IOCFG28_PORT_ID_RFC_GPO1 0x00000030 10805 #define IOC_IOCFG28_PORT_ID_RFC_GPO0 0x0000002F 10806 #define IOC_IOCFG28_PORT_ID_RFC_TRC 0x0000002E 10807 #define IOC_IOCFG28_PORT_ID_I2S_MCLK 0x00000029 10808 #define IOC_IOCFG28_PORT_ID_I2S_BCLK 0x00000028 10809 #define IOC_IOCFG28_PORT_ID_I2S_WCLK 0x00000027 10810 #define IOC_IOCFG28_PORT_ID_I2S_AD1 0x00000026 10811 #define IOC_IOCFG28_PORT_ID_I2S_AD0 0x00000025 10812 #define IOC_IOCFG28_PORT_ID_SSI1_CLK 0x00000024 10813 #define IOC_IOCFG28_PORT_ID_SSI1_FSS 0x00000023 10814 #define IOC_IOCFG28_PORT_ID_SSI1_TX 0x00000022 10815 #define IOC_IOCFG28_PORT_ID_SSI1_RX 0x00000021 10816 #define IOC_IOCFG28_PORT_ID_CPU_SWV 0x00000020 10817 #define IOC_IOCFG28_PORT_ID_PORT_EVENT7 0x0000001E 10818 #define IOC_IOCFG28_PORT_ID_PORT_EVENT6 0x0000001D 10819 #define IOC_IOCFG28_PORT_ID_PORT_EVENT5 0x0000001C 10820 #define IOC_IOCFG28_PORT_ID_PORT_EVENT4 0x0000001B 10821 #define IOC_IOCFG28_PORT_ID_PORT_EVENT3 0x0000001A 10822 #define IOC_IOCFG28_PORT_ID_PORT_EVENT2 0x00000019 10823 #define IOC_IOCFG28_PORT_ID_PORT_EVENT1 0x00000018 10824 #define IOC_IOCFG28_PORT_ID_PORT_EVENT0 0x00000017 10825 #define IOC_IOCFG28_PORT_ID_UART1_RTS 0x00000016 10826 #define IOC_IOCFG28_PORT_ID_UART1_CTS 0x00000015 10827 #define IOC_IOCFG28_PORT_ID_UART1_TX 0x00000014 10828 #define IOC_IOCFG28_PORT_ID_UART1_RX 0x00000013 10829 #define IOC_IOCFG28_PORT_ID_UART0_RTS 0x00000012 10830 #define IOC_IOCFG28_PORT_ID_UART0_CTS 0x00000011 10831 #define IOC_IOCFG28_PORT_ID_UART0_TX 0x00000010 10832 #define IOC_IOCFG28_PORT_ID_UART0_RX 0x0000000F 10833 #define IOC_IOCFG28_PORT_ID_I2C_MSSCL 0x0000000E 10834 #define IOC_IOCFG28_PORT_ID_I2C_MSSDA 0x0000000D 10835 #define IOC_IOCFG28_PORT_ID_SSI0_CLK 0x0000000C 10836 #define IOC_IOCFG28_PORT_ID_SSI0_FSS 0x0000000B 10837 #define IOC_IOCFG28_PORT_ID_SSI0_TX 0x0000000A 10838 #define IOC_IOCFG28_PORT_ID_SSI0_RX 0x00000009 10839 #define IOC_IOCFG28_PORT_ID_AUX_IO 0x00000008 10840 #define IOC_IOCFG28_PORT_ID_AON_CLK32K 0x00000007 10841 #define IOC_IOCFG28_PORT_ID_GPIO 0x00000000 10842 10843 //***************************************************************************** 10844 // 10845 // Register: IOC_O_IOCFG29 10846 // 10847 //***************************************************************************** 10848 // Field: [30] HYST_EN 10849 // 10850 // 0: Input hysteresis disable 10851 // 1: Input hysteresis enable 10852 #define IOC_IOCFG29_HYST_EN 0x40000000 10853 #define IOC_IOCFG29_HYST_EN_BITN 30 10854 #define IOC_IOCFG29_HYST_EN_M 0x40000000 10855 #define IOC_IOCFG29_HYST_EN_S 30 10856 10857 // Field: [29] IE 10858 // 10859 // 0: Input disabled 10860 // 1: Input enabled 10861 // 10862 // Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be 10863 // ignored. 10864 #define IOC_IOCFG29_IE 0x20000000 10865 #define IOC_IOCFG29_IE_BITN 29 10866 #define IOC_IOCFG29_IE_M 0x20000000 10867 #define IOC_IOCFG29_IE_S 29 10868 10869 // Field: [28:27] WU_CFG 10870 // 10871 // If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or 10872 // >0x08: 10873 // 10874 // 00: No wake-up 10875 // 01: No wake-up 10876 // 10: Wakes up from shutdown if this pad is going low. 10877 // 11: Wakes up from shutdown if this pad is going high. 10878 // 10879 // If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, 10880 // this register only sets wakeup enable or not. 10881 // 10882 // 00, 01: Wakeup disabled 10883 // 10, 11: Wakeup enabled 10884 // 10885 // Polarity is controlled from AON registers. 10886 // 10887 // Note:When the MSB is set, the IOC will deactivate the output enable for the 10888 // DIO. 10889 #define IOC_IOCFG29_WU_CFG_W 2 10890 #define IOC_IOCFG29_WU_CFG_M 0x18000000 10891 #define IOC_IOCFG29_WU_CFG_S 27 10892 10893 // Field: [26:24] IOMODE 10894 // 10895 // IO Mode 10896 // Not applicable for IO configured for AON periph. signals and AUX PORT_ID 10897 // 0x01-0x08 10898 // AUX has its own open_source/drain configuration. 10899 // 10900 // 0x2: Reserved. Undefined behavior. 10901 // 0x3: Reserved. Undefined behavior. 10902 // ENUMs: 10903 // OPENSRC_INV Open Source 10904 // Inverted input / output 10905 // OPENSRC Open Source 10906 // Normal input / output 10907 // OPENDR_INV Open Drain 10908 // Inverted input / output 10909 // OPENDR Open Drain, 10910 // Normal input / output 10911 // INV Inverted input / ouput 10912 // NORMAL Normal input / output 10913 #define IOC_IOCFG29_IOMODE_W 3 10914 #define IOC_IOCFG29_IOMODE_M 0x07000000 10915 #define IOC_IOCFG29_IOMODE_S 24 10916 #define IOC_IOCFG29_IOMODE_OPENSRC_INV 0x07000000 10917 #define IOC_IOCFG29_IOMODE_OPENSRC 0x06000000 10918 #define IOC_IOCFG29_IOMODE_OPENDR_INV 0x05000000 10919 #define IOC_IOCFG29_IOMODE_OPENDR 0x04000000 10920 #define IOC_IOCFG29_IOMODE_INV 0x01000000 10921 #define IOC_IOCFG29_IOMODE_NORMAL 0x00000000 10922 10923 // Field: [23] IOEV_AON_PROG2_EN 10924 // 10925 // Event asserted by this IO when edge detection is enabled 10926 // 10927 // 0: Input edge detection does not assert AON_PROG2 event 10928 // 1: Input edge detection asserts AON_PROG2 event 10929 #define IOC_IOCFG29_IOEV_AON_PROG2_EN 0x00800000 10930 #define IOC_IOCFG29_IOEV_AON_PROG2_EN_BITN 23 10931 #define IOC_IOCFG29_IOEV_AON_PROG2_EN_M 0x00800000 10932 #define IOC_IOCFG29_IOEV_AON_PROG2_EN_S 23 10933 10934 // Field: [22] IOEV_AON_PROG1_EN 10935 // 10936 // Event asserted by this IO when edge detection is enabled 10937 // 10938 // 0: Input edge detection does not assert AON_PROG1 event 10939 // 1: Input edge detection asserts AON_PROG1 event 10940 #define IOC_IOCFG29_IOEV_AON_PROG1_EN 0x00400000 10941 #define IOC_IOCFG29_IOEV_AON_PROG1_EN_BITN 22 10942 #define IOC_IOCFG29_IOEV_AON_PROG1_EN_M 0x00400000 10943 #define IOC_IOCFG29_IOEV_AON_PROG1_EN_S 22 10944 10945 // Field: [21] IOEV_AON_PROG0_EN 10946 // 10947 // Event asserted by this IO when edge detection is enabled 10948 // 10949 // 0: Input edge detection does not assert AON_PROG0 event 10950 // 1: Input edge detection asserts AON_PROG0 event 10951 #define IOC_IOCFG29_IOEV_AON_PROG0_EN 0x00200000 10952 #define IOC_IOCFG29_IOEV_AON_PROG0_EN_BITN 21 10953 #define IOC_IOCFG29_IOEV_AON_PROG0_EN_M 0x00200000 10954 #define IOC_IOCFG29_IOEV_AON_PROG0_EN_S 21 10955 10956 // Field: [18] EDGE_IRQ_EN 10957 // 10958 // 0: No interrupt generation 10959 // 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is 10960 // enabled) 10961 #define IOC_IOCFG29_EDGE_IRQ_EN 0x00040000 10962 #define IOC_IOCFG29_EDGE_IRQ_EN_BITN 18 10963 #define IOC_IOCFG29_EDGE_IRQ_EN_M 0x00040000 10964 #define IOC_IOCFG29_EDGE_IRQ_EN_S 18 10965 10966 // Field: [17:16] EDGE_DET 10967 // 10968 // Enable generation of edge detection events on this IO 10969 // ENUMs: 10970 // BOTH Positive and negative edge detection 10971 // POS Positive edge detection 10972 // NEG Negative edge detection 10973 // NONE No edge detection 10974 #define IOC_IOCFG29_EDGE_DET_W 2 10975 #define IOC_IOCFG29_EDGE_DET_M 0x00030000 10976 #define IOC_IOCFG29_EDGE_DET_S 16 10977 #define IOC_IOCFG29_EDGE_DET_BOTH 0x00030000 10978 #define IOC_IOCFG29_EDGE_DET_POS 0x00020000 10979 #define IOC_IOCFG29_EDGE_DET_NEG 0x00010000 10980 #define IOC_IOCFG29_EDGE_DET_NONE 0x00000000 10981 10982 // Field: [14:13] PULL_CTL 10983 // 10984 // Pull control 10985 // ENUMs: 10986 // DIS No pull 10987 // UP Pull up 10988 // DWN Pull down 10989 #define IOC_IOCFG29_PULL_CTL_W 2 10990 #define IOC_IOCFG29_PULL_CTL_M 0x00006000 10991 #define IOC_IOCFG29_PULL_CTL_S 13 10992 #define IOC_IOCFG29_PULL_CTL_DIS 0x00006000 10993 #define IOC_IOCFG29_PULL_CTL_UP 0x00004000 10994 #define IOC_IOCFG29_PULL_CTL_DWN 0x00002000 10995 10996 // Field: [12] SLEW_RED 10997 // 10998 // 0: Normal slew rate 10999 // 1: Enables reduced slew rate in output driver. 11000 #define IOC_IOCFG29_SLEW_RED 0x00001000 11001 #define IOC_IOCFG29_SLEW_RED_BITN 12 11002 #define IOC_IOCFG29_SLEW_RED_M 0x00001000 11003 #define IOC_IOCFG29_SLEW_RED_S 12 11004 11005 // Field: [11:10] IOCURR 11006 // 11007 // Selects IO current mode of this IO. 11008 // ENUMs: 11009 // 4_8MA Extended-Current (EC) mode: Min 8 mA for double 11010 // drive strength IOs (min 4 mA for normal IOs) 11011 // when IOSTR is set to AUTO 11012 // 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set 11013 // to AUTO 11014 // 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set 11015 // to AUTO 11016 #define IOC_IOCFG29_IOCURR_W 2 11017 #define IOC_IOCFG29_IOCURR_M 0x00000C00 11018 #define IOC_IOCFG29_IOCURR_S 10 11019 #define IOC_IOCFG29_IOCURR_4_8MA 0x00000800 11020 #define IOC_IOCFG29_IOCURR_4MA 0x00000400 11021 #define IOC_IOCFG29_IOCURR_2MA 0x00000000 11022 11023 // Field: [9:8] IOSTR 11024 // 11025 // Select source for drive strength control of this IO. 11026 // This setting controls the drive strength of the Low-Current (LC) mode. 11027 // Higher drive strength can be selected in IOCURR 11028 // ENUMs: 11029 // MAX Maximum drive strength, controlled by 11030 // AON_IOC:IOSTRMAX (min 2 mA @1.8V with default 11031 // values) 11032 // MED Medium drive strength, controlled by 11033 // AON_IOC:IOSTRMED (min 2 mA @2.5V with default 11034 // values) 11035 // MIN Minimum drive strength, controlled by 11036 // AON_IOC:IOSTRMIN (min 2 mA @3.3V with default 11037 // values) 11038 // AUTO Automatic drive strength, controlled by AON BATMON 11039 // based on battery voltage. (min 2 mA @VDDS) 11040 #define IOC_IOCFG29_IOSTR_W 2 11041 #define IOC_IOCFG29_IOSTR_M 0x00000300 11042 #define IOC_IOCFG29_IOSTR_S 8 11043 #define IOC_IOCFG29_IOSTR_MAX 0x00000300 11044 #define IOC_IOCFG29_IOSTR_MED 0x00000200 11045 #define IOC_IOCFG29_IOSTR_MIN 0x00000100 11046 #define IOC_IOCFG29_IOSTR_AUTO 0x00000000 11047 11048 // Field: [7] IOEV_RTC_EN 11049 // 11050 // Event asserted by this IO when edge detection is enabled 11051 // 11052 // 0: Input edge detection does not assert RTC event 11053 // 1: Input edge detection asserts RTC event 11054 #define IOC_IOCFG29_IOEV_RTC_EN 0x00000080 11055 #define IOC_IOCFG29_IOEV_RTC_EN_BITN 7 11056 #define IOC_IOCFG29_IOEV_RTC_EN_M 0x00000080 11057 #define IOC_IOCFG29_IOEV_RTC_EN_S 7 11058 11059 // Field: [6] IOEV_MCU_WU_EN 11060 // 11061 // Event asserted by this IO when edge detection is enabled 11062 // 11063 // 0: Input edge detection does not assert MCU_WU event 11064 // 1: Input edge detection asserts MCU_WU event 11065 #define IOC_IOCFG29_IOEV_MCU_WU_EN 0x00000040 11066 #define IOC_IOCFG29_IOEV_MCU_WU_EN_BITN 6 11067 #define IOC_IOCFG29_IOEV_MCU_WU_EN_M 0x00000040 11068 #define IOC_IOCFG29_IOEV_MCU_WU_EN_S 6 11069 11070 // Field: [5:0] PORT_ID 11071 // 11072 // Selects usage for DIO29 11073 // Note: This field should not be written other than the times when PORT_ID 11074 // value is specifically required to change. 11075 // ENUMs: 11076 // RFC_SMI_CL_IN RF Core SMI Command Link In 11077 // RFC_SMI_CL_OUT RF Core SMI Command Link Out 11078 // RFC_SMI_DL_IN RF Core SMI Data Link In 11079 // RFC_SMI_DL_OUT RF Core SMI Data Link Out 11080 // RFC_GPI1 RF Core Data In 1 11081 // RFC_GPI0 RF Core Data In 0 11082 // RFC_GPO3 RF Core Data Out 3 11083 // RFC_GPO2 RF Core Data Out 2 11084 // RFC_GPO1 RF Core Data Out 1 11085 // RFC_GPO0 RF Core Data Out 0 11086 // RFC_TRC RF Core Trace 11087 // I2S_MCLK I2S MCLK 11088 // I2S_BCLK I2S BCLK 11089 // I2S_WCLK I2S WCLK 11090 // I2S_AD1 I2S Data 1 11091 // I2S_AD0 I2S Data 0 11092 // SSI1_CLK SSI1 CLK 11093 // SSI1_FSS SSI1 FSS 11094 // SSI1_TX SSI1 TX 11095 // SSI1_RX SSI1 RX 11096 // CPU_SWV CPU SWV 11097 // PORT_EVENT7 PORT EVENT 7 11098 // Can be used as a general 11099 // purpose IO event by selecting it through 11100 // registers in the EVENT module, for example 11101 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 11102 // and so on 11103 // PORT_EVENT6 PORT EVENT 6 11104 // Can be used as a general 11105 // purpose IO event by selecting it through 11106 // registers in the EVENT module, for example 11107 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 11108 // and so on 11109 // PORT_EVENT5 PORT EVENT 5 11110 // Can be used as a general 11111 // purpose IO event by selecting it through 11112 // registers in the EVENT module, for example 11113 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 11114 // and so on 11115 // PORT_EVENT4 PORT EVENT 4 11116 // Can be used as a general 11117 // purpose IO event by selecting it through 11118 // registers in the EVENT module, for example 11119 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 11120 // and so on 11121 // PORT_EVENT3 PORT EVENT 3 11122 // Can be used as a general 11123 // purpose IO event by selecting it through 11124 // registers in the EVENT module, for example 11125 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 11126 // and so on 11127 // PORT_EVENT2 PORT EVENT 2 11128 // Can be used as a general 11129 // purpose IO event by selecting it through 11130 // registers in the EVENT module, for example 11131 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 11132 // and so on 11133 // PORT_EVENT1 PORT EVENT 1 11134 // Can be used as a general 11135 // purpose IO event by selecting it through 11136 // registers in the EVENT module, for example 11137 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 11138 // and so on 11139 // PORT_EVENT0 PORT EVENT 0 11140 // Can be used as a general 11141 // purpose IO event by selecting it through 11142 // registers in the EVENT module, for example 11143 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 11144 // and so on 11145 // UART1_RTS UART1 RTS 11146 // UART1_CTS UART1 CTS 11147 // UART1_TX UART1 TX 11148 // UART1_RX UART1 RX 11149 // UART0_RTS UART0 RTS 11150 // UART0_CTS UART0 CTS 11151 // UART0_TX UART0 TX 11152 // UART0_RX UART0 RX 11153 // I2C_MSSCL I2C Clock 11154 // I2C_MSSDA I2C Data 11155 // SSI0_CLK SSI0 CLK 11156 // SSI0_FSS SSI0 FSS 11157 // SSI0_TX SSI0 TX 11158 // SSI0_RX SSI0 RX 11159 // AUX_IO AUX IO 11160 // AON_CLK32K AON 32 KHz clock (SCLK_LF) 11161 // GPIO General Purpose IO 11162 #define IOC_IOCFG29_PORT_ID_W 6 11163 #define IOC_IOCFG29_PORT_ID_M 0x0000003F 11164 #define IOC_IOCFG29_PORT_ID_S 0 11165 #define IOC_IOCFG29_PORT_ID_RFC_SMI_CL_IN 0x00000038 11166 #define IOC_IOCFG29_PORT_ID_RFC_SMI_CL_OUT 0x00000037 11167 #define IOC_IOCFG29_PORT_ID_RFC_SMI_DL_IN 0x00000036 11168 #define IOC_IOCFG29_PORT_ID_RFC_SMI_DL_OUT 0x00000035 11169 #define IOC_IOCFG29_PORT_ID_RFC_GPI1 0x00000034 11170 #define IOC_IOCFG29_PORT_ID_RFC_GPI0 0x00000033 11171 #define IOC_IOCFG29_PORT_ID_RFC_GPO3 0x00000032 11172 #define IOC_IOCFG29_PORT_ID_RFC_GPO2 0x00000031 11173 #define IOC_IOCFG29_PORT_ID_RFC_GPO1 0x00000030 11174 #define IOC_IOCFG29_PORT_ID_RFC_GPO0 0x0000002F 11175 #define IOC_IOCFG29_PORT_ID_RFC_TRC 0x0000002E 11176 #define IOC_IOCFG29_PORT_ID_I2S_MCLK 0x00000029 11177 #define IOC_IOCFG29_PORT_ID_I2S_BCLK 0x00000028 11178 #define IOC_IOCFG29_PORT_ID_I2S_WCLK 0x00000027 11179 #define IOC_IOCFG29_PORT_ID_I2S_AD1 0x00000026 11180 #define IOC_IOCFG29_PORT_ID_I2S_AD0 0x00000025 11181 #define IOC_IOCFG29_PORT_ID_SSI1_CLK 0x00000024 11182 #define IOC_IOCFG29_PORT_ID_SSI1_FSS 0x00000023 11183 #define IOC_IOCFG29_PORT_ID_SSI1_TX 0x00000022 11184 #define IOC_IOCFG29_PORT_ID_SSI1_RX 0x00000021 11185 #define IOC_IOCFG29_PORT_ID_CPU_SWV 0x00000020 11186 #define IOC_IOCFG29_PORT_ID_PORT_EVENT7 0x0000001E 11187 #define IOC_IOCFG29_PORT_ID_PORT_EVENT6 0x0000001D 11188 #define IOC_IOCFG29_PORT_ID_PORT_EVENT5 0x0000001C 11189 #define IOC_IOCFG29_PORT_ID_PORT_EVENT4 0x0000001B 11190 #define IOC_IOCFG29_PORT_ID_PORT_EVENT3 0x0000001A 11191 #define IOC_IOCFG29_PORT_ID_PORT_EVENT2 0x00000019 11192 #define IOC_IOCFG29_PORT_ID_PORT_EVENT1 0x00000018 11193 #define IOC_IOCFG29_PORT_ID_PORT_EVENT0 0x00000017 11194 #define IOC_IOCFG29_PORT_ID_UART1_RTS 0x00000016 11195 #define IOC_IOCFG29_PORT_ID_UART1_CTS 0x00000015 11196 #define IOC_IOCFG29_PORT_ID_UART1_TX 0x00000014 11197 #define IOC_IOCFG29_PORT_ID_UART1_RX 0x00000013 11198 #define IOC_IOCFG29_PORT_ID_UART0_RTS 0x00000012 11199 #define IOC_IOCFG29_PORT_ID_UART0_CTS 0x00000011 11200 #define IOC_IOCFG29_PORT_ID_UART0_TX 0x00000010 11201 #define IOC_IOCFG29_PORT_ID_UART0_RX 0x0000000F 11202 #define IOC_IOCFG29_PORT_ID_I2C_MSSCL 0x0000000E 11203 #define IOC_IOCFG29_PORT_ID_I2C_MSSDA 0x0000000D 11204 #define IOC_IOCFG29_PORT_ID_SSI0_CLK 0x0000000C 11205 #define IOC_IOCFG29_PORT_ID_SSI0_FSS 0x0000000B 11206 #define IOC_IOCFG29_PORT_ID_SSI0_TX 0x0000000A 11207 #define IOC_IOCFG29_PORT_ID_SSI0_RX 0x00000009 11208 #define IOC_IOCFG29_PORT_ID_AUX_IO 0x00000008 11209 #define IOC_IOCFG29_PORT_ID_AON_CLK32K 0x00000007 11210 #define IOC_IOCFG29_PORT_ID_GPIO 0x00000000 11211 11212 //***************************************************************************** 11213 // 11214 // Register: IOC_O_IOCFG30 11215 // 11216 //***************************************************************************** 11217 // Field: [30] HYST_EN 11218 // 11219 // 0: Input hysteresis disable 11220 // 1: Input hysteresis enable 11221 #define IOC_IOCFG30_HYST_EN 0x40000000 11222 #define IOC_IOCFG30_HYST_EN_BITN 30 11223 #define IOC_IOCFG30_HYST_EN_M 0x40000000 11224 #define IOC_IOCFG30_HYST_EN_S 30 11225 11226 // Field: [29] IE 11227 // 11228 // 0: Input disabled 11229 // 1: Input enabled 11230 // 11231 // Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be 11232 // ignored. 11233 #define IOC_IOCFG30_IE 0x20000000 11234 #define IOC_IOCFG30_IE_BITN 29 11235 #define IOC_IOCFG30_IE_M 0x20000000 11236 #define IOC_IOCFG30_IE_S 29 11237 11238 // Field: [28:27] WU_CFG 11239 // 11240 // If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or 11241 // >0x08: 11242 // 11243 // 00: No wake-up 11244 // 01: No wake-up 11245 // 10: Wakes up from shutdown if this pad is going low. 11246 // 11: Wakes up from shutdown if this pad is going high. 11247 // 11248 // If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, 11249 // this register only sets wakeup enable or not. 11250 // 11251 // 00, 01: Wakeup disabled 11252 // 10, 11: Wakeup enabled 11253 // 11254 // Polarity is controlled from AON registers. 11255 // 11256 // Note:When the MSB is set, the IOC will deactivate the output enable for the 11257 // DIO. 11258 #define IOC_IOCFG30_WU_CFG_W 2 11259 #define IOC_IOCFG30_WU_CFG_M 0x18000000 11260 #define IOC_IOCFG30_WU_CFG_S 27 11261 11262 // Field: [26:24] IOMODE 11263 // 11264 // IO Mode 11265 // Not applicable for IO configured for AON periph. signals and AUX PORT_ID 11266 // 0x01-0x08 11267 // AUX has its own open_source/drain configuration. 11268 // 11269 // 0x2: Reserved. Undefined behavior. 11270 // 0x3: Reserved. Undefined behavior. 11271 // ENUMs: 11272 // OPENSRC_INV Open Source 11273 // Inverted input / output 11274 // OPENSRC Open Source 11275 // Normal input / output 11276 // OPENDR_INV Open Drain 11277 // Inverted input / output 11278 // OPENDR Open Drain, 11279 // Normal input / output 11280 // INV Inverted input / ouput 11281 // NORMAL Normal input / output 11282 #define IOC_IOCFG30_IOMODE_W 3 11283 #define IOC_IOCFG30_IOMODE_M 0x07000000 11284 #define IOC_IOCFG30_IOMODE_S 24 11285 #define IOC_IOCFG30_IOMODE_OPENSRC_INV 0x07000000 11286 #define IOC_IOCFG30_IOMODE_OPENSRC 0x06000000 11287 #define IOC_IOCFG30_IOMODE_OPENDR_INV 0x05000000 11288 #define IOC_IOCFG30_IOMODE_OPENDR 0x04000000 11289 #define IOC_IOCFG30_IOMODE_INV 0x01000000 11290 #define IOC_IOCFG30_IOMODE_NORMAL 0x00000000 11291 11292 // Field: [23] IOEV_AON_PROG2_EN 11293 // 11294 // Event asserted by this IO when edge detection is enabled 11295 // 11296 // 0: Input edge detection does not assert AON_PROG2 event 11297 // 1: Input edge detection asserts AON_PROG2 event 11298 #define IOC_IOCFG30_IOEV_AON_PROG2_EN 0x00800000 11299 #define IOC_IOCFG30_IOEV_AON_PROG2_EN_BITN 23 11300 #define IOC_IOCFG30_IOEV_AON_PROG2_EN_M 0x00800000 11301 #define IOC_IOCFG30_IOEV_AON_PROG2_EN_S 23 11302 11303 // Field: [22] IOEV_AON_PROG1_EN 11304 // 11305 // Event asserted by this IO when edge detection is enabled 11306 // 11307 // 0: Input edge detection does not assert AON_PROG1 event 11308 // 1: Input edge detection asserts AON_PROG1 event 11309 #define IOC_IOCFG30_IOEV_AON_PROG1_EN 0x00400000 11310 #define IOC_IOCFG30_IOEV_AON_PROG1_EN_BITN 22 11311 #define IOC_IOCFG30_IOEV_AON_PROG1_EN_M 0x00400000 11312 #define IOC_IOCFG30_IOEV_AON_PROG1_EN_S 22 11313 11314 // Field: [21] IOEV_AON_PROG0_EN 11315 // 11316 // Event asserted by this IO when edge detection is enabled 11317 // 11318 // 0: Input edge detection does not assert AON_PROG0 event 11319 // 1: Input edge detection asserts AON_PROG0 event 11320 #define IOC_IOCFG30_IOEV_AON_PROG0_EN 0x00200000 11321 #define IOC_IOCFG30_IOEV_AON_PROG0_EN_BITN 21 11322 #define IOC_IOCFG30_IOEV_AON_PROG0_EN_M 0x00200000 11323 #define IOC_IOCFG30_IOEV_AON_PROG0_EN_S 21 11324 11325 // Field: [18] EDGE_IRQ_EN 11326 // 11327 // 0: No interrupt generation 11328 // 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is 11329 // enabled) 11330 #define IOC_IOCFG30_EDGE_IRQ_EN 0x00040000 11331 #define IOC_IOCFG30_EDGE_IRQ_EN_BITN 18 11332 #define IOC_IOCFG30_EDGE_IRQ_EN_M 0x00040000 11333 #define IOC_IOCFG30_EDGE_IRQ_EN_S 18 11334 11335 // Field: [17:16] EDGE_DET 11336 // 11337 // Enable generation of edge detection events on this IO 11338 // ENUMs: 11339 // BOTH Positive and negative edge detection 11340 // POS Positive edge detection 11341 // NEG Negative edge detection 11342 // NONE No edge detection 11343 #define IOC_IOCFG30_EDGE_DET_W 2 11344 #define IOC_IOCFG30_EDGE_DET_M 0x00030000 11345 #define IOC_IOCFG30_EDGE_DET_S 16 11346 #define IOC_IOCFG30_EDGE_DET_BOTH 0x00030000 11347 #define IOC_IOCFG30_EDGE_DET_POS 0x00020000 11348 #define IOC_IOCFG30_EDGE_DET_NEG 0x00010000 11349 #define IOC_IOCFG30_EDGE_DET_NONE 0x00000000 11350 11351 // Field: [14:13] PULL_CTL 11352 // 11353 // Pull control 11354 // ENUMs: 11355 // DIS No pull 11356 // UP Pull up 11357 // DWN Pull down 11358 #define IOC_IOCFG30_PULL_CTL_W 2 11359 #define IOC_IOCFG30_PULL_CTL_M 0x00006000 11360 #define IOC_IOCFG30_PULL_CTL_S 13 11361 #define IOC_IOCFG30_PULL_CTL_DIS 0x00006000 11362 #define IOC_IOCFG30_PULL_CTL_UP 0x00004000 11363 #define IOC_IOCFG30_PULL_CTL_DWN 0x00002000 11364 11365 // Field: [12] SLEW_RED 11366 // 11367 // 0: Normal slew rate 11368 // 1: Enables reduced slew rate in output driver. 11369 #define IOC_IOCFG30_SLEW_RED 0x00001000 11370 #define IOC_IOCFG30_SLEW_RED_BITN 12 11371 #define IOC_IOCFG30_SLEW_RED_M 0x00001000 11372 #define IOC_IOCFG30_SLEW_RED_S 12 11373 11374 // Field: [11:10] IOCURR 11375 // 11376 // Selects IO current mode of this IO. 11377 // ENUMs: 11378 // 4_8MA Extended-Current (EC) mode: Min 8 mA for double 11379 // drive strength IOs (min 4 mA for normal IOs) 11380 // when IOSTR is set to AUTO 11381 // 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set 11382 // to AUTO 11383 // 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set 11384 // to AUTO 11385 #define IOC_IOCFG30_IOCURR_W 2 11386 #define IOC_IOCFG30_IOCURR_M 0x00000C00 11387 #define IOC_IOCFG30_IOCURR_S 10 11388 #define IOC_IOCFG30_IOCURR_4_8MA 0x00000800 11389 #define IOC_IOCFG30_IOCURR_4MA 0x00000400 11390 #define IOC_IOCFG30_IOCURR_2MA 0x00000000 11391 11392 // Field: [9:8] IOSTR 11393 // 11394 // Select source for drive strength control of this IO. 11395 // This setting controls the drive strength of the Low-Current (LC) mode. 11396 // Higher drive strength can be selected in IOCURR 11397 // ENUMs: 11398 // MAX Maximum drive strength, controlled by 11399 // AON_IOC:IOSTRMAX (min 2 mA @1.8V with default 11400 // values) 11401 // MED Medium drive strength, controlled by 11402 // AON_IOC:IOSTRMED (min 2 mA @2.5V with default 11403 // values) 11404 // MIN Minimum drive strength, controlled by 11405 // AON_IOC:IOSTRMIN (min 2 mA @3.3V with default 11406 // values) 11407 // AUTO Automatic drive strength, controlled by AON BATMON 11408 // based on battery voltage. (min 2 mA @VDDS) 11409 #define IOC_IOCFG30_IOSTR_W 2 11410 #define IOC_IOCFG30_IOSTR_M 0x00000300 11411 #define IOC_IOCFG30_IOSTR_S 8 11412 #define IOC_IOCFG30_IOSTR_MAX 0x00000300 11413 #define IOC_IOCFG30_IOSTR_MED 0x00000200 11414 #define IOC_IOCFG30_IOSTR_MIN 0x00000100 11415 #define IOC_IOCFG30_IOSTR_AUTO 0x00000000 11416 11417 // Field: [7] IOEV_RTC_EN 11418 // 11419 // Event asserted by this IO when edge detection is enabled 11420 // 11421 // 0: Input edge detection does not assert RTC event 11422 // 1: Input edge detection asserts RTC event 11423 #define IOC_IOCFG30_IOEV_RTC_EN 0x00000080 11424 #define IOC_IOCFG30_IOEV_RTC_EN_BITN 7 11425 #define IOC_IOCFG30_IOEV_RTC_EN_M 0x00000080 11426 #define IOC_IOCFG30_IOEV_RTC_EN_S 7 11427 11428 // Field: [6] IOEV_MCU_WU_EN 11429 // 11430 // Event asserted by this IO when edge detection is enabled 11431 // 11432 // 0: Input edge detection does not assert MCU_WU event 11433 // 1: Input edge detection asserts MCU_WU event 11434 #define IOC_IOCFG30_IOEV_MCU_WU_EN 0x00000040 11435 #define IOC_IOCFG30_IOEV_MCU_WU_EN_BITN 6 11436 #define IOC_IOCFG30_IOEV_MCU_WU_EN_M 0x00000040 11437 #define IOC_IOCFG30_IOEV_MCU_WU_EN_S 6 11438 11439 // Field: [5:0] PORT_ID 11440 // 11441 // Selects usage for DIO30 11442 // Note: This field should not be written other than the times when PORT_ID 11443 // value is specifically required to change. 11444 // ENUMs: 11445 // RFC_SMI_CL_IN RF Core SMI Command Link In 11446 // RFC_SMI_CL_OUT RF Core SMI Command Link Out 11447 // RFC_SMI_DL_IN RF Core SMI Data Link In 11448 // RFC_SMI_DL_OUT RF Core SMI Data Link Out 11449 // RFC_GPI1 RF Core Data In 1 11450 // RFC_GPI0 RF Core Data In 0 11451 // RFC_GPO3 RF Core Data Out 3 11452 // RFC_GPO2 RF Core Data Out 2 11453 // RFC_GPO1 RF Core Data Out 1 11454 // RFC_GPO0 RF Core Data Out 0 11455 // RFC_TRC RF Core Trace 11456 // I2S_MCLK I2S MCLK 11457 // I2S_BCLK I2S BCLK 11458 // I2S_WCLK I2S WCLK 11459 // I2S_AD1 I2S Data 1 11460 // I2S_AD0 I2S Data 0 11461 // SSI1_CLK SSI1 CLK 11462 // SSI1_FSS SSI1 FSS 11463 // SSI1_TX SSI1 TX 11464 // SSI1_RX SSI1 RX 11465 // CPU_SWV CPU SWV 11466 // PORT_EVENT7 PORT EVENT 7 11467 // Can be used as a general 11468 // purpose IO event by selecting it through 11469 // registers in the EVENT module, for example 11470 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 11471 // and so on 11472 // PORT_EVENT6 PORT EVENT 6 11473 // Can be used as a general 11474 // purpose IO event by selecting it through 11475 // registers in the EVENT module, for example 11476 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 11477 // and so on 11478 // PORT_EVENT5 PORT EVENT 5 11479 // Can be used as a general 11480 // purpose IO event by selecting it through 11481 // registers in the EVENT module, for example 11482 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 11483 // and so on 11484 // PORT_EVENT4 PORT EVENT 4 11485 // Can be used as a general 11486 // purpose IO event by selecting it through 11487 // registers in the EVENT module, for example 11488 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 11489 // and so on 11490 // PORT_EVENT3 PORT EVENT 3 11491 // Can be used as a general 11492 // purpose IO event by selecting it through 11493 // registers in the EVENT module, for example 11494 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 11495 // and so on 11496 // PORT_EVENT2 PORT EVENT 2 11497 // Can be used as a general 11498 // purpose IO event by selecting it through 11499 // registers in the EVENT module, for example 11500 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 11501 // and so on 11502 // PORT_EVENT1 PORT EVENT 1 11503 // Can be used as a general 11504 // purpose IO event by selecting it through 11505 // registers in the EVENT module, for example 11506 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 11507 // and so on 11508 // PORT_EVENT0 PORT EVENT 0 11509 // Can be used as a general 11510 // purpose IO event by selecting it through 11511 // registers in the EVENT module, for example 11512 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 11513 // and so on 11514 // UART1_RTS UART1 RTS 11515 // UART1_CTS UART1 CTS 11516 // UART1_TX UART1 TX 11517 // UART1_RX UART1 RX 11518 // UART0_RTS UART0 RTS 11519 // UART0_CTS UART0 CTS 11520 // UART0_TX UART0 TX 11521 // UART0_RX UART0 RX 11522 // I2C_MSSCL I2C Clock 11523 // I2C_MSSDA I2C Data 11524 // SSI0_CLK SSI0 CLK 11525 // SSI0_FSS SSI0 FSS 11526 // SSI0_TX SSI0 TX 11527 // SSI0_RX SSI0 RX 11528 // AUX_IO AUX IO 11529 // AON_CLK32K AON 32 KHz clock (SCLK_LF) 11530 // GPIO General Purpose IO 11531 #define IOC_IOCFG30_PORT_ID_W 6 11532 #define IOC_IOCFG30_PORT_ID_M 0x0000003F 11533 #define IOC_IOCFG30_PORT_ID_S 0 11534 #define IOC_IOCFG30_PORT_ID_RFC_SMI_CL_IN 0x00000038 11535 #define IOC_IOCFG30_PORT_ID_RFC_SMI_CL_OUT 0x00000037 11536 #define IOC_IOCFG30_PORT_ID_RFC_SMI_DL_IN 0x00000036 11537 #define IOC_IOCFG30_PORT_ID_RFC_SMI_DL_OUT 0x00000035 11538 #define IOC_IOCFG30_PORT_ID_RFC_GPI1 0x00000034 11539 #define IOC_IOCFG30_PORT_ID_RFC_GPI0 0x00000033 11540 #define IOC_IOCFG30_PORT_ID_RFC_GPO3 0x00000032 11541 #define IOC_IOCFG30_PORT_ID_RFC_GPO2 0x00000031 11542 #define IOC_IOCFG30_PORT_ID_RFC_GPO1 0x00000030 11543 #define IOC_IOCFG30_PORT_ID_RFC_GPO0 0x0000002F 11544 #define IOC_IOCFG30_PORT_ID_RFC_TRC 0x0000002E 11545 #define IOC_IOCFG30_PORT_ID_I2S_MCLK 0x00000029 11546 #define IOC_IOCFG30_PORT_ID_I2S_BCLK 0x00000028 11547 #define IOC_IOCFG30_PORT_ID_I2S_WCLK 0x00000027 11548 #define IOC_IOCFG30_PORT_ID_I2S_AD1 0x00000026 11549 #define IOC_IOCFG30_PORT_ID_I2S_AD0 0x00000025 11550 #define IOC_IOCFG30_PORT_ID_SSI1_CLK 0x00000024 11551 #define IOC_IOCFG30_PORT_ID_SSI1_FSS 0x00000023 11552 #define IOC_IOCFG30_PORT_ID_SSI1_TX 0x00000022 11553 #define IOC_IOCFG30_PORT_ID_SSI1_RX 0x00000021 11554 #define IOC_IOCFG30_PORT_ID_CPU_SWV 0x00000020 11555 #define IOC_IOCFG30_PORT_ID_PORT_EVENT7 0x0000001E 11556 #define IOC_IOCFG30_PORT_ID_PORT_EVENT6 0x0000001D 11557 #define IOC_IOCFG30_PORT_ID_PORT_EVENT5 0x0000001C 11558 #define IOC_IOCFG30_PORT_ID_PORT_EVENT4 0x0000001B 11559 #define IOC_IOCFG30_PORT_ID_PORT_EVENT3 0x0000001A 11560 #define IOC_IOCFG30_PORT_ID_PORT_EVENT2 0x00000019 11561 #define IOC_IOCFG30_PORT_ID_PORT_EVENT1 0x00000018 11562 #define IOC_IOCFG30_PORT_ID_PORT_EVENT0 0x00000017 11563 #define IOC_IOCFG30_PORT_ID_UART1_RTS 0x00000016 11564 #define IOC_IOCFG30_PORT_ID_UART1_CTS 0x00000015 11565 #define IOC_IOCFG30_PORT_ID_UART1_TX 0x00000014 11566 #define IOC_IOCFG30_PORT_ID_UART1_RX 0x00000013 11567 #define IOC_IOCFG30_PORT_ID_UART0_RTS 0x00000012 11568 #define IOC_IOCFG30_PORT_ID_UART0_CTS 0x00000011 11569 #define IOC_IOCFG30_PORT_ID_UART0_TX 0x00000010 11570 #define IOC_IOCFG30_PORT_ID_UART0_RX 0x0000000F 11571 #define IOC_IOCFG30_PORT_ID_I2C_MSSCL 0x0000000E 11572 #define IOC_IOCFG30_PORT_ID_I2C_MSSDA 0x0000000D 11573 #define IOC_IOCFG30_PORT_ID_SSI0_CLK 0x0000000C 11574 #define IOC_IOCFG30_PORT_ID_SSI0_FSS 0x0000000B 11575 #define IOC_IOCFG30_PORT_ID_SSI0_TX 0x0000000A 11576 #define IOC_IOCFG30_PORT_ID_SSI0_RX 0x00000009 11577 #define IOC_IOCFG30_PORT_ID_AUX_IO 0x00000008 11578 #define IOC_IOCFG30_PORT_ID_AON_CLK32K 0x00000007 11579 #define IOC_IOCFG30_PORT_ID_GPIO 0x00000000 11580 11581 //***************************************************************************** 11582 // 11583 // Register: IOC_O_IOCFG31 11584 // 11585 //***************************************************************************** 11586 // Field: [30] HYST_EN 11587 // 11588 // 0: Input hysteresis disable 11589 // 1: Input hysteresis enable 11590 #define IOC_IOCFG31_HYST_EN 0x40000000 11591 #define IOC_IOCFG31_HYST_EN_BITN 30 11592 #define IOC_IOCFG31_HYST_EN_M 0x40000000 11593 #define IOC_IOCFG31_HYST_EN_S 30 11594 11595 // Field: [29] IE 11596 // 11597 // 0: Input disabled 11598 // 1: Input enabled 11599 // 11600 // Note: If IO is configured for AUX PORT_ID = 0x08, the enable will be 11601 // ignored. 11602 #define IOC_IOCFG31_IE 0x20000000 11603 #define IOC_IOCFG31_IE_BITN 29 11604 #define IOC_IOCFG31_IE_M 0x20000000 11605 #define IOC_IOCFG31_IE_S 29 11606 11607 // Field: [28:27] WU_CFG 11608 // 11609 // If DIO is configured GPIO or non-AON peripheral signals, PORT_ID 0x00 or 11610 // >0x08: 11611 // 11612 // 00: No wake-up 11613 // 01: No wake-up 11614 // 10: Wakes up from shutdown if this pad is going low. 11615 // 11: Wakes up from shutdown if this pad is going high. 11616 // 11617 // If IO is configured for AON peripheral signals or AUX PORT_ID 0x01-0x08, 11618 // this register only sets wakeup enable or not. 11619 // 11620 // 00, 01: Wakeup disabled 11621 // 10, 11: Wakeup enabled 11622 // 11623 // Polarity is controlled from AON registers. 11624 // 11625 // Note:When the MSB is set, the IOC will deactivate the output enable for the 11626 // DIO. 11627 #define IOC_IOCFG31_WU_CFG_W 2 11628 #define IOC_IOCFG31_WU_CFG_M 0x18000000 11629 #define IOC_IOCFG31_WU_CFG_S 27 11630 11631 // Field: [26:24] IOMODE 11632 // 11633 // IO Mode 11634 // Not applicable for IO configured for AON periph. signals and AUX PORT_ID 11635 // 0x01-0x08 11636 // AUX has its own open_source/drain configuration. 11637 // 11638 // 0x2: Reserved. Undefined behavior. 11639 // 0x3: Reserved. Undefined behavior. 11640 // ENUMs: 11641 // OPENSRC_INV Open Source 11642 // Inverted input / output 11643 // OPENSRC Open Source 11644 // Normal input / output 11645 // OPENDR_INV Open Drain 11646 // Inverted input / output 11647 // OPENDR Open Drain, 11648 // Normal input / output 11649 // INV Inverted input / ouput 11650 // NORMAL Normal input / output 11651 #define IOC_IOCFG31_IOMODE_W 3 11652 #define IOC_IOCFG31_IOMODE_M 0x07000000 11653 #define IOC_IOCFG31_IOMODE_S 24 11654 #define IOC_IOCFG31_IOMODE_OPENSRC_INV 0x07000000 11655 #define IOC_IOCFG31_IOMODE_OPENSRC 0x06000000 11656 #define IOC_IOCFG31_IOMODE_OPENDR_INV 0x05000000 11657 #define IOC_IOCFG31_IOMODE_OPENDR 0x04000000 11658 #define IOC_IOCFG31_IOMODE_INV 0x01000000 11659 #define IOC_IOCFG31_IOMODE_NORMAL 0x00000000 11660 11661 // Field: [23] IOEV_AON_PROG2_EN 11662 // 11663 // Event asserted by this IO when edge detection is enabled 11664 // 11665 // 0: Input edge detection does not assert AON_PROG2 event 11666 // 1: Input edge detection asserts AON_PROG2 event 11667 #define IOC_IOCFG31_IOEV_AON_PROG2_EN 0x00800000 11668 #define IOC_IOCFG31_IOEV_AON_PROG2_EN_BITN 23 11669 #define IOC_IOCFG31_IOEV_AON_PROG2_EN_M 0x00800000 11670 #define IOC_IOCFG31_IOEV_AON_PROG2_EN_S 23 11671 11672 // Field: [22] IOEV_AON_PROG1_EN 11673 // 11674 // Event asserted by this IO when edge detection is enabled 11675 // 11676 // 0: Input edge detection does not assert AON_PROG1 event 11677 // 1: Input edge detection asserts AON_PROG1 event 11678 #define IOC_IOCFG31_IOEV_AON_PROG1_EN 0x00400000 11679 #define IOC_IOCFG31_IOEV_AON_PROG1_EN_BITN 22 11680 #define IOC_IOCFG31_IOEV_AON_PROG1_EN_M 0x00400000 11681 #define IOC_IOCFG31_IOEV_AON_PROG1_EN_S 22 11682 11683 // Field: [21] IOEV_AON_PROG0_EN 11684 // 11685 // Event asserted by this IO when edge detection is enabled 11686 // 11687 // 0: Input edge detection does not assert AON_PROG0 event 11688 // 1: Input edge detection asserts AON_PROG0 event 11689 #define IOC_IOCFG31_IOEV_AON_PROG0_EN 0x00200000 11690 #define IOC_IOCFG31_IOEV_AON_PROG0_EN_BITN 21 11691 #define IOC_IOCFG31_IOEV_AON_PROG0_EN_M 0x00200000 11692 #define IOC_IOCFG31_IOEV_AON_PROG0_EN_S 21 11693 11694 // Field: [18] EDGE_IRQ_EN 11695 // 11696 // 0: No interrupt generation 11697 // 1: Enable interrupt generation for this IO (Only effective if EDGE_DET is 11698 // enabled) 11699 #define IOC_IOCFG31_EDGE_IRQ_EN 0x00040000 11700 #define IOC_IOCFG31_EDGE_IRQ_EN_BITN 18 11701 #define IOC_IOCFG31_EDGE_IRQ_EN_M 0x00040000 11702 #define IOC_IOCFG31_EDGE_IRQ_EN_S 18 11703 11704 // Field: [17:16] EDGE_DET 11705 // 11706 // Enable generation of edge detection events on this IO 11707 // ENUMs: 11708 // BOTH Positive and negative edge detection 11709 // POS Positive edge detection 11710 // NEG Negative edge detection 11711 // NONE No edge detection 11712 #define IOC_IOCFG31_EDGE_DET_W 2 11713 #define IOC_IOCFG31_EDGE_DET_M 0x00030000 11714 #define IOC_IOCFG31_EDGE_DET_S 16 11715 #define IOC_IOCFG31_EDGE_DET_BOTH 0x00030000 11716 #define IOC_IOCFG31_EDGE_DET_POS 0x00020000 11717 #define IOC_IOCFG31_EDGE_DET_NEG 0x00010000 11718 #define IOC_IOCFG31_EDGE_DET_NONE 0x00000000 11719 11720 // Field: [14:13] PULL_CTL 11721 // 11722 // Pull control 11723 // ENUMs: 11724 // DIS No pull 11725 // UP Pull up 11726 // DWN Pull down 11727 #define IOC_IOCFG31_PULL_CTL_W 2 11728 #define IOC_IOCFG31_PULL_CTL_M 0x00006000 11729 #define IOC_IOCFG31_PULL_CTL_S 13 11730 #define IOC_IOCFG31_PULL_CTL_DIS 0x00006000 11731 #define IOC_IOCFG31_PULL_CTL_UP 0x00004000 11732 #define IOC_IOCFG31_PULL_CTL_DWN 0x00002000 11733 11734 // Field: [12] SLEW_RED 11735 // 11736 // 0: Normal slew rate 11737 // 1: Enables reduced slew rate in output driver. 11738 #define IOC_IOCFG31_SLEW_RED 0x00001000 11739 #define IOC_IOCFG31_SLEW_RED_BITN 12 11740 #define IOC_IOCFG31_SLEW_RED_M 0x00001000 11741 #define IOC_IOCFG31_SLEW_RED_S 12 11742 11743 // Field: [11:10] IOCURR 11744 // 11745 // Selects IO current mode of this IO. 11746 // ENUMs: 11747 // 4_8MA Extended-Current (EC) mode: Min 8 mA for double 11748 // drive strength IOs (min 4 mA for normal IOs) 11749 // when IOSTR is set to AUTO 11750 // 4MA High-Current (HC) mode: Min 4 mA when IOSTR is set 11751 // to AUTO 11752 // 2MA Low-Current (LC) mode: Min 2 mA when IOSTR is set 11753 // to AUTO 11754 #define IOC_IOCFG31_IOCURR_W 2 11755 #define IOC_IOCFG31_IOCURR_M 0x00000C00 11756 #define IOC_IOCFG31_IOCURR_S 10 11757 #define IOC_IOCFG31_IOCURR_4_8MA 0x00000800 11758 #define IOC_IOCFG31_IOCURR_4MA 0x00000400 11759 #define IOC_IOCFG31_IOCURR_2MA 0x00000000 11760 11761 // Field: [9:8] IOSTR 11762 // 11763 // Select source for drive strength control of this IO. 11764 // This setting controls the drive strength of the Low-Current (LC) mode. 11765 // Higher drive strength can be selected in IOCURR 11766 // ENUMs: 11767 // MAX Maximum drive strength, controlled by 11768 // AON_IOC:IOSTRMAX (min 2 mA @1.8V with default 11769 // values) 11770 // MED Medium drive strength, controlled by 11771 // AON_IOC:IOSTRMED (min 2 mA @2.5V with default 11772 // values) 11773 // MIN Minimum drive strength, controlled by 11774 // AON_IOC:IOSTRMIN (min 2 mA @3.3V with default 11775 // values) 11776 // AUTO Automatic drive strength, controlled by AON BATMON 11777 // based on battery voltage. (min 2 mA @VDDS) 11778 #define IOC_IOCFG31_IOSTR_W 2 11779 #define IOC_IOCFG31_IOSTR_M 0x00000300 11780 #define IOC_IOCFG31_IOSTR_S 8 11781 #define IOC_IOCFG31_IOSTR_MAX 0x00000300 11782 #define IOC_IOCFG31_IOSTR_MED 0x00000200 11783 #define IOC_IOCFG31_IOSTR_MIN 0x00000100 11784 #define IOC_IOCFG31_IOSTR_AUTO 0x00000000 11785 11786 // Field: [7] IOEV_RTC_EN 11787 // 11788 // Event asserted by this IO when edge detection is enabled 11789 // 11790 // 0: Input edge detection does not assert RTC event 11791 // 1: Input edge detection asserts RTC event 11792 #define IOC_IOCFG31_IOEV_RTC_EN 0x00000080 11793 #define IOC_IOCFG31_IOEV_RTC_EN_BITN 7 11794 #define IOC_IOCFG31_IOEV_RTC_EN_M 0x00000080 11795 #define IOC_IOCFG31_IOEV_RTC_EN_S 7 11796 11797 // Field: [6] IOEV_MCU_WU_EN 11798 // 11799 // Event asserted by this IO when edge detection is enabled 11800 // 11801 // 0: Input edge detection does not assert MCU_WU event 11802 // 1: Input edge detection asserts MCU_WU event 11803 #define IOC_IOCFG31_IOEV_MCU_WU_EN 0x00000040 11804 #define IOC_IOCFG31_IOEV_MCU_WU_EN_BITN 6 11805 #define IOC_IOCFG31_IOEV_MCU_WU_EN_M 0x00000040 11806 #define IOC_IOCFG31_IOEV_MCU_WU_EN_S 6 11807 11808 // Field: [5:0] PORT_ID 11809 // 11810 // Selects usage for DIO31 11811 // Note: This field should not be written other than the times when PORT_ID 11812 // value is specifically required to change. 11813 // ENUMs: 11814 // RFC_SMI_CL_IN RF Core SMI Command Link In 11815 // RFC_SMI_CL_OUT RF Core SMI Command Link Out 11816 // RFC_SMI_DL_IN RF Core SMI Data Link In 11817 // RFC_SMI_DL_OUT RF Core SMI Data Link Out 11818 // RFC_GPI1 RF Core Data In 1 11819 // RFC_GPI0 RF Core Data In 0 11820 // RFC_GPO3 RF Core Data Out 3 11821 // RFC_GPO2 RF Core Data Out 2 11822 // RFC_GPO1 RF Core Data Out 1 11823 // RFC_GPO0 RF Core Data Out 0 11824 // RFC_TRC RF Core Trace 11825 // I2S_MCLK I2S MCLK 11826 // I2S_BCLK I2S BCLK 11827 // I2S_WCLK I2S WCLK 11828 // I2S_AD1 I2S Data 1 11829 // I2S_AD0 I2S Data 0 11830 // SSI1_CLK SSI1 CLK 11831 // SSI1_FSS SSI1 FSS 11832 // SSI1_TX SSI1 TX 11833 // SSI1_RX SSI1 RX 11834 // CPU_SWV CPU SWV 11835 // PORT_EVENT7 PORT EVENT 7 11836 // Can be used as a general 11837 // purpose IO event by selecting it through 11838 // registers in the EVENT module, for example 11839 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 11840 // and so on 11841 // PORT_EVENT6 PORT EVENT 6 11842 // Can be used as a general 11843 // purpose IO event by selecting it through 11844 // registers in the EVENT module, for example 11845 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 11846 // and so on 11847 // PORT_EVENT5 PORT EVENT 5 11848 // Can be used as a general 11849 // purpose IO event by selecting it through 11850 // registers in the EVENT module, for example 11851 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 11852 // and so on 11853 // PORT_EVENT4 PORT EVENT 4 11854 // Can be used as a general 11855 // purpose IO event by selecting it through 11856 // registers in the EVENT module, for example 11857 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 11858 // and so on 11859 // PORT_EVENT3 PORT EVENT 3 11860 // Can be used as a general 11861 // purpose IO event by selecting it through 11862 // registers in the EVENT module, for example 11863 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 11864 // and so on 11865 // PORT_EVENT2 PORT EVENT 2 11866 // Can be used as a general 11867 // purpose IO event by selecting it through 11868 // registers in the EVENT module, for example 11869 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 11870 // and so on 11871 // PORT_EVENT1 PORT EVENT 1 11872 // Can be used as a general 11873 // purpose IO event by selecting it through 11874 // registers in the EVENT module, for example 11875 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 11876 // and so on 11877 // PORT_EVENT0 PORT EVENT 0 11878 // Can be used as a general 11879 // purpose IO event by selecting it through 11880 // registers in the EVENT module, for example 11881 // EVENT:GPT0ACAPTSEL.EV, EVENT:UDMACH14BSEL.EV, 11882 // and so on 11883 // UART1_RTS UART1 RTS 11884 // UART1_CTS UART1 CTS 11885 // UART1_TX UART1 TX 11886 // UART1_RX UART1 RX 11887 // UART0_RTS UART0 RTS 11888 // UART0_CTS UART0 CTS 11889 // UART0_TX UART0 TX 11890 // UART0_RX UART0 RX 11891 // I2C_MSSCL I2C Clock 11892 // I2C_MSSDA I2C Data 11893 // SSI0_CLK SSI0 CLK 11894 // SSI0_FSS SSI0 FSS 11895 // SSI0_TX SSI0 TX 11896 // SSI0_RX SSI0 RX 11897 // AUX_IO AUX IO 11898 // AON_CLK32K AON 32 KHz clock (SCLK_LF) 11899 // GPIO General Purpose IO 11900 #define IOC_IOCFG31_PORT_ID_W 6 11901 #define IOC_IOCFG31_PORT_ID_M 0x0000003F 11902 #define IOC_IOCFG31_PORT_ID_S 0 11903 #define IOC_IOCFG31_PORT_ID_RFC_SMI_CL_IN 0x00000038 11904 #define IOC_IOCFG31_PORT_ID_RFC_SMI_CL_OUT 0x00000037 11905 #define IOC_IOCFG31_PORT_ID_RFC_SMI_DL_IN 0x00000036 11906 #define IOC_IOCFG31_PORT_ID_RFC_SMI_DL_OUT 0x00000035 11907 #define IOC_IOCFG31_PORT_ID_RFC_GPI1 0x00000034 11908 #define IOC_IOCFG31_PORT_ID_RFC_GPI0 0x00000033 11909 #define IOC_IOCFG31_PORT_ID_RFC_GPO3 0x00000032 11910 #define IOC_IOCFG31_PORT_ID_RFC_GPO2 0x00000031 11911 #define IOC_IOCFG31_PORT_ID_RFC_GPO1 0x00000030 11912 #define IOC_IOCFG31_PORT_ID_RFC_GPO0 0x0000002F 11913 #define IOC_IOCFG31_PORT_ID_RFC_TRC 0x0000002E 11914 #define IOC_IOCFG31_PORT_ID_I2S_MCLK 0x00000029 11915 #define IOC_IOCFG31_PORT_ID_I2S_BCLK 0x00000028 11916 #define IOC_IOCFG31_PORT_ID_I2S_WCLK 0x00000027 11917 #define IOC_IOCFG31_PORT_ID_I2S_AD1 0x00000026 11918 #define IOC_IOCFG31_PORT_ID_I2S_AD0 0x00000025 11919 #define IOC_IOCFG31_PORT_ID_SSI1_CLK 0x00000024 11920 #define IOC_IOCFG31_PORT_ID_SSI1_FSS 0x00000023 11921 #define IOC_IOCFG31_PORT_ID_SSI1_TX 0x00000022 11922 #define IOC_IOCFG31_PORT_ID_SSI1_RX 0x00000021 11923 #define IOC_IOCFG31_PORT_ID_CPU_SWV 0x00000020 11924 #define IOC_IOCFG31_PORT_ID_PORT_EVENT7 0x0000001E 11925 #define IOC_IOCFG31_PORT_ID_PORT_EVENT6 0x0000001D 11926 #define IOC_IOCFG31_PORT_ID_PORT_EVENT5 0x0000001C 11927 #define IOC_IOCFG31_PORT_ID_PORT_EVENT4 0x0000001B 11928 #define IOC_IOCFG31_PORT_ID_PORT_EVENT3 0x0000001A 11929 #define IOC_IOCFG31_PORT_ID_PORT_EVENT2 0x00000019 11930 #define IOC_IOCFG31_PORT_ID_PORT_EVENT1 0x00000018 11931 #define IOC_IOCFG31_PORT_ID_PORT_EVENT0 0x00000017 11932 #define IOC_IOCFG31_PORT_ID_UART1_RTS 0x00000016 11933 #define IOC_IOCFG31_PORT_ID_UART1_CTS 0x00000015 11934 #define IOC_IOCFG31_PORT_ID_UART1_TX 0x00000014 11935 #define IOC_IOCFG31_PORT_ID_UART1_RX 0x00000013 11936 #define IOC_IOCFG31_PORT_ID_UART0_RTS 0x00000012 11937 #define IOC_IOCFG31_PORT_ID_UART0_CTS 0x00000011 11938 #define IOC_IOCFG31_PORT_ID_UART0_TX 0x00000010 11939 #define IOC_IOCFG31_PORT_ID_UART0_RX 0x0000000F 11940 #define IOC_IOCFG31_PORT_ID_I2C_MSSCL 0x0000000E 11941 #define IOC_IOCFG31_PORT_ID_I2C_MSSDA 0x0000000D 11942 #define IOC_IOCFG31_PORT_ID_SSI0_CLK 0x0000000C 11943 #define IOC_IOCFG31_PORT_ID_SSI0_FSS 0x0000000B 11944 #define IOC_IOCFG31_PORT_ID_SSI0_TX 0x0000000A 11945 #define IOC_IOCFG31_PORT_ID_SSI0_RX 0x00000009 11946 #define IOC_IOCFG31_PORT_ID_AUX_IO 0x00000008 11947 #define IOC_IOCFG31_PORT_ID_AON_CLK32K 0x00000007 11948 #define IOC_IOCFG31_PORT_ID_GPIO 0x00000000 11949 11950 11951 #endif // __IOC__ 11952
