1 /******************************************************************************
2 *  Filename:       interrupt.h
3 *
4 *  Description:    Defines and prototypes for the NVIC Interrupt Controller
5 *
6 *  Copyright (c) 2015 - 2022, Texas Instruments Incorporated
7 *  All rights reserved.
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10 *  modification, are permitted provided that the following conditions are met:
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13 *     this list of conditions and the following disclaimer.
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15 *  2) Redistributions in binary form must reproduce the above copyright notice,
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36 
37 //*****************************************************************************
38 //
39 //! \addtogroup system_cpu_group
40 //! @{
41 //! \addtogroup interrupt_api
42 //! @{
43 //
44 //*****************************************************************************
45 
46 #ifndef __INTERRUPT_H__
47 #define __INTERRUPT_H__
48 
49 //*****************************************************************************
50 //
51 // If building with a C++ compiler, make all of the definitions in this header
52 // have a C binding.
53 //
54 //*****************************************************************************
55 #ifdef __cplusplus
56 extern "C"
57 {
58 #endif
59 
60 #include <stdbool.h>
61 #include <stdint.h>
62 #include "../inc/hw_ints.h"
63 #include "../inc/hw_types.h"
64 #include "../inc/hw_nvic.h"
65 #include "debug.h"
66 #include "cpu.h"
67 
68 //*****************************************************************************
69 //
70 // Support for DriverLib in ROM:
71 // This section renames all functions that are not "static inline", so that
72 // calling these functions will default to implementation in flash. At the end
73 // of this file a second renaming will change the defaults to implementation in
74 // ROM for available functions.
75 //
76 // To force use of the implementation in flash, e.g. for debugging:
77 // - Globally: Define DRIVERLIB_NOROM at project level
78 // - Per function: Use prefix "NOROM_" when calling the function
79 //
80 //*****************************************************************************
81 #if !defined(DOXYGEN)
82     #define IntRegister                     NOROM_IntRegister
83     #define IntUnregister                   NOROM_IntUnregister
84     #define IntPriorityGroupingSet          NOROM_IntPriorityGroupingSet
85     #define IntPriorityGroupingGet          NOROM_IntPriorityGroupingGet
86     #define IntPrioritySet                  NOROM_IntPrioritySet
87     #define IntPriorityGet                  NOROM_IntPriorityGet
88     #define IntEnable                       NOROM_IntEnable
89     #define IntDisable                      NOROM_IntDisable
90     #define IntPendSet                      NOROM_IntPendSet
91     #define IntPendGet                      NOROM_IntPendGet
92     #define IntPendClear                    NOROM_IntPendClear
93 #endif
94 
95 //*****************************************************************************
96 //
97 // Macro to generate an interrupt priority mask based on the number of bits
98 // of priority supported by the hardware. For CC26xx the number of priority
99 // bit is 3 as defined in <tt>hw_types.h</tt>. The priority mask is
100 // defined as
101 //
102 // INT_PRIORITY_MASK = ((0xFF << (8 - NUM_PRIORITY_BITS)) & 0xFF)
103 //
104 //*****************************************************************************
105 #define INT_PRIORITY_MASK       0x000000E0
106 #define INT_PRI_LEVEL0          0x00000000
107 #define INT_PRI_LEVEL1          0x00000020
108 #define INT_PRI_LEVEL2          0x00000040
109 #define INT_PRI_LEVEL3          0x00000060
110 #define INT_PRI_LEVEL4          0x00000080
111 #define INT_PRI_LEVEL5          0x000000A0
112 #define INT_PRI_LEVEL6          0x000000C0
113 #define INT_PRI_LEVEL7          0x000000E0
114 
115 //*****************************************************************************
116 //
117 // API Functions and prototypes
118 //
119 //*****************************************************************************
120 
121 //*****************************************************************************
122 //
123 //! \brief Registers a function as an interrupt handler in the dynamic vector table.
124 //!
125 //! \note Only use this function if you want to use the dynamic vector table (in SRAM)!
126 //!
127 //! This function writes a function pointer to the dynamic interrupt vector table
128 //! in SRAM to register the function as an interrupt handler (ISR). When the corresponding
129 //! interrupt occurs, and it has been enabled (see \ref IntEnable()), the function
130 //! pointer is fetched from the dynamic vector table, and the System CPU will
131 //! execute the interrupt handler.
132 //!
133 //! \note The first call to this function (directly or indirectly via a peripheral
134 //! driver interrupt register function) copies the interrupt vector table from
135 //! Flash to SRAM. NVIC uses the static vector table (in Flash) until this function
136 //! is called.
137 //!
138 //! \param ui32Interrupt specifies the index in the vector table to modify.
139 //! - System exceptions (vectors 0 to 15):
140 //!   - INT_NMI_FAULT
141 //!   - INT_HARD_FAULT
142 //!   - INT_MEMMANAGE_FAULT
143 //!   - INT_BUS_FAULT
144 //!   - INT_USAGE_FAULT
145 //!   - INT_SVCALL
146 //!   - INT_DEBUG
147 //!   - INT_PENDSV
148 //!   - INT_SYSTICK
149 //! - Interrupts (vectors >15):
150 //!   - INT_AON_GPIO_EDGE
151 //!   - INT_I2C_IRQ
152 //!   - INT_RFC_CPE_1
153 //!   - INT_AON_RTC_COMB
154 //!   - INT_UART0_COMB
155 //!   - INT_AUX_SWEV0
156 //!   - INT_SSI0_COMB
157 //!   - INT_RFC_CPE_0
158 //!   - INT_RFC_HW_COMB
159 //!   - INT_RFC_CMD_ACK
160 //!   - INT_I2S_IRQ
161 //!   - INT_AUX_SWEV1
162 //!   - INT_WDT_IRQ
163 //!   - INT_GPT0A
164 //!   - INT_GPT0B
165 //!   - INT_GPT1A
166 //!   - INT_GPT1B
167 //!   - INT_GPT2A
168 //!   - INT_GPT2B
169 //!   - INT_GPT3A
170 //!   - INT_GPT3B
171 //!   - INT_CRYPTO_RESULT_AVAIL_IRQ
172 //!   - INT_DMA_DONE_COMB
173 //!   - INT_DMA_ERR
174 //!   - INT_FLASH
175 //!   - INT_SWEV0
176 //!   - INT_AUX_COMB
177 //!   - INT_AON_PROG0
178 //!   - INT_PROG0 (Programmable interrupt, see \ref EventRegister())
179 //!   - INT_AUX_COMPA
180 //!   - INT_AUX_ADC_IRQ
181 //!   - INT_TRNG_IRQ
182 //!   - INT_OSC_COMB
183 //!   - INT_BATMON_COMB
184 //!   - INT_PKA_IRQ
185 //!   - INT_SSI1_COMB
186 //!   - INT_UART1_COMB
187 //!   - INT_AUX_TIMER2_EV0
188 //! \param pfnHandler is a pointer to the function to register as interrupt handler.
189 //!
190 //! \return None.
191 //!
192 //! \sa \ref IntUnregister(), \ref IntEnable()
193 //
194 //*****************************************************************************
195 extern void IntRegister(uint32_t ui32Interrupt, void (*pfnHandler)(void));
196 
197 //*****************************************************************************
198 //
199 //! \brief Unregisters an interrupt handler in the dynamic vector table.
200 //!
201 //! This function removes an interrupt handler from the dynamic vector table and
202 //! replaces it with the default interrupt handler \ref IntDefaultHandler().
203 //!
204 //! \note Remember to disable the interrupt before removing its interrupt handler
205 //! from the vector table.
206 //!
207 //! \param ui32Interrupt specifies the index in the vector table to modify.
208 //! - See \ref IntRegister() for list of valid arguments.
209 //!
210 //! \return None.
211 //!
212 //! \sa \ref IntRegister(), \ref IntDisable()
213 //
214 //*****************************************************************************
215 extern void IntUnregister(uint32_t ui32Interrupt);
216 
217 //*****************************************************************************
218 //
219 //! \brief Sets the priority grouping of the interrupt controller.
220 //!
221 //! This function specifies the split between preemptable priority levels and
222 //! subpriority levels in the interrupt priority specification.
223 //!
224 //! Three bits are available for hardware interrupt prioritization thus priority
225 //! grouping values of three through seven have the same effect.
226 //!
227 //! \param ui32Bits specifies the number of bits of preemptable priority.
228 //! - 0   : No pre-emption priority, eight bits of subpriority.
229 //! - 1   : One bit of pre-emption priority, seven bits of subpriority
230 //! - 2   : Two bits of pre-emption priority, six bits of subpriority
231 //! - 3-7 : Three bits of pre-emption priority, five bits of subpriority
232 //!
233 //! \return None
234 //!
235 //! \sa \ref IntPrioritySet()
236 //
237 //*****************************************************************************
238 extern void IntPriorityGroupingSet(uint32_t ui32Bits);
239 
240 //*****************************************************************************
241 //
242 //! \brief Gets the priority grouping of the interrupt controller.
243 //!
244 //! This function returns the split between preemptable priority levels and
245 //! subpriority levels in the interrupt priority specification.
246 //!
247 //! \return Returns the number of bits of preemptable priority.
248 //! - 0   : No pre-emption priority, eight bits of subpriority.
249 //! - 1   : One bit of pre-emption priority, seven bits of subpriority
250 //! - 2   : Two bits of pre-emption priority, six bits of subpriority
251 //! - 3-7 : Three bits of pre-emption priority, five bits of subpriority
252 //
253 //*****************************************************************************
254 extern uint32_t IntPriorityGroupingGet(void);
255 
256 //*****************************************************************************
257 //
258 //! \brief Sets the priority of an interrupt.
259 //!
260 //! This function sets the priority of an interrupt, including system exceptions.
261 //! When multiple interrupts are asserted simultaneously, the ones with the highest
262 //! priority are processed before the lower priority interrupts. Smaller numbers
263 //! correspond to higher interrupt priorities thus priority 0 is the highest
264 //! interrupt priority.
265 //!
266 //! \warning This function does not support setting priority of interrupt vectors
267 //! one through three which are:
268 //! - 1: Reset handler
269 //! - 2: NMI handler
270 //! - 3: Hard fault handler
271 //!
272 //! \param ui32Interrupt specifies the index in the vector table to change priority for.
273 //! - System exceptions:
274 //!   - INT_MEMMANAGE_FAULT
275 //!   - INT_BUS_FAULT
276 //!   - INT_USAGE_FAULT
277 //!   - INT_SVCALL
278 //!   - INT_DEBUG
279 //!   - INT_PENDSV
280 //!   - INT_SYSTICK
281 //! - Interrupts:
282 //!   - INT_AON_GPIO_EDGE
283 //!   - INT_I2C_IRQ
284 //!   - INT_RFC_CPE_1
285 //!   - INT_AON_RTC_COMB
286 //!   - INT_UART0_COMB
287 //!   - INT_AUX_SWEV0
288 //!   - INT_SSI0_COMB
289 //!   - INT_RFC_CPE_0
290 //!   - INT_RFC_HW_COMB
291 //!   - INT_RFC_CMD_ACK
292 //!   - INT_I2S_IRQ
293 //!   - INT_AUX_SWEV1
294 //!   - INT_WDT_IRQ
295 //!   - INT_GPT0A
296 //!   - INT_GPT0B
297 //!   - INT_GPT1A
298 //!   - INT_GPT1B
299 //!   - INT_GPT2A
300 //!   - INT_GPT2B
301 //!   - INT_GPT3A
302 //!   - INT_GPT3B
303 //!   - INT_CRYPTO_RESULT_AVAIL_IRQ
304 //!   - INT_DMA_DONE_COMB
305 //!   - INT_DMA_ERR
306 //!   - INT_FLASH
307 //!   - INT_SWEV0
308 //!   - INT_AUX_COMB
309 //!   - INT_AON_PROG0
310 //!   - INT_PROG0 (Programmable interrupt, see \ref EventRegister())
311 //!   - INT_AUX_COMPA
312 //!   - INT_AUX_ADC_IRQ
313 //!   - INT_TRNG_IRQ
314 //!   - INT_OSC_COMB
315 //!   - INT_BATMON_COMB
316 //!   - INT_PKA_IRQ
317 //!   - INT_SSI1_COMB
318 //!   - INT_UART1_COMB
319 //!   - INT_AUX_TIMER2_EV0
320 //! \param ui8Priority specifies the priority of the interrupt.
321 //! - \ref INT_PRI_LEVEL0 : Highest priority.
322 //! - \ref INT_PRI_LEVEL1
323 //! - \ref INT_PRI_LEVEL2
324 //! - \ref INT_PRI_LEVEL3
325 //! - \ref INT_PRI_LEVEL4
326 //! - \ref INT_PRI_LEVEL5
327 //! - \ref INT_PRI_LEVEL6
328 //! - \ref INT_PRI_LEVEL7 : Lowest priority.
329 //!
330 //! \return None
331 //!
332 //! \sa \ref IntPriorityGroupingSet()
333 //
334 //*****************************************************************************
335 extern void IntPrioritySet(uint32_t ui32Interrupt, uint8_t ui8Priority);
336 
337 //*****************************************************************************
338 //
339 //! \brief Gets the priority of an interrupt.
340 //!
341 //! This function gets the priority of an interrupt.
342 //!
343 //! \warning This function does not support getting priority of interrupt vectors
344 //! one through three which are:
345 //! - 1: Reset handler
346 //! - 2: NMI handler
347 //! - 3: Hard fault handler
348 //!
349 //! \param ui32Interrupt specifies the index in the vector table to read priority of.
350 //! - See \ref IntPrioritySet() for list of valid arguments.
351 //!
352 //! \return Returns the interrupt priority:
353 //! - \ref INT_PRI_LEVEL0 : Highest priority.
354 //! - \ref INT_PRI_LEVEL1
355 //! - \ref INT_PRI_LEVEL2
356 //! - \ref INT_PRI_LEVEL3
357 //! - \ref INT_PRI_LEVEL4
358 //! - \ref INT_PRI_LEVEL5
359 //! - \ref INT_PRI_LEVEL6
360 //! - \ref INT_PRI_LEVEL7 : Lowest priority.
361 //
362 //*****************************************************************************
363 extern int32_t IntPriorityGet(uint32_t ui32Interrupt);
364 
365 //*****************************************************************************
366 //
367 //! \brief Enables an interrupt or system exception.
368 //!
369 //! This function enables the specified interrupt in the interrupt controller.
370 //!
371 //! \note If a fault condition occurs while the corresponding system exception
372 //! is disabled, the fault is treated as a Hard Fault.
373 //!
374 //! \param ui32Interrupt specifies the index in the vector table to enable.
375 //! - System exceptions:
376 //!   - INT_MEMMANAGE_FAULT
377 //!   - INT_BUS_FAULT
378 //!   - INT_USAGE_FAULT
379 //!   - INT_SYSTICK
380 //! - Interrupts:
381 //!   - INT_AON_GPIO_EDGE
382 //!   - INT_I2C_IRQ
383 //!   - INT_RFC_CPE_1
384 //!   - INT_AON_RTC_COMB
385 //!   - INT_UART0_COMB
386 //!   - INT_AUX_SWEV0
387 //!   - INT_SSI0_COMB
388 //!   - INT_RFC_CPE_0
389 //!   - INT_RFC_HW_COMB
390 //!   - INT_RFC_CMD_ACK
391 //!   - INT_I2S_IRQ
392 //!   - INT_AUX_SWEV1
393 //!   - INT_WDT_IRQ
394 //!   - INT_GPT0A
395 //!   - INT_GPT0B
396 //!   - INT_GPT1A
397 //!   - INT_GPT1B
398 //!   - INT_GPT2A
399 //!   - INT_GPT2B
400 //!   - INT_GPT3A
401 //!   - INT_GPT3B
402 //!   - INT_CRYPTO_RESULT_AVAIL_IRQ
403 //!   - INT_DMA_DONE_COMB
404 //!   - INT_DMA_ERR
405 //!   - INT_FLASH
406 //!   - INT_SWEV0
407 //!   - INT_AUX_COMB
408 //!   - INT_AON_PROG0
409 //!   - INT_PROG0 (Programmable interrupt, see \ref EventRegister())
410 //!   - INT_AUX_COMPA
411 //!   - INT_AUX_ADC_IRQ
412 //!   - INT_TRNG_IRQ
413 //!   - INT_OSC_COMB
414 //!   - INT_BATMON_COMB
415 //!   - INT_PKA_IRQ
416 //!   - INT_SSI1_COMB
417 //!   - INT_UART1_COMB
418 //!   - INT_AUX_TIMER2_EV0
419 //!
420 //! \return None
421 //!
422 //! \sa \ref IntDisable()
423 //
424 //*****************************************************************************
425 extern void IntEnable(uint32_t ui32Interrupt);
426 
427 //*****************************************************************************
428 //
429 //! \brief Disables an interrupt or system exception.
430 //!
431 //! This function disables the specified interrupt in the interrupt controller.
432 //!
433 //! \param ui32Interrupt specifies the index in the vector table to disable.
434 //! - See \ref IntEnable() for list of valid arguments.
435 //!
436 //! \return None
437 //!
438 //! \sa \ref IntEnable()
439 //
440 //*****************************************************************************
441 extern void IntDisable(uint32_t ui32Interrupt);
442 
443 //*****************************************************************************
444 //
445 //! \brief Pends an interrupt.
446 //!
447 //! This function pends the specified interrupt in the interrupt controller.
448 //! This causes the interrupt controller to execute the corresponding interrupt
449 //! handler at the next available time, based on the current interrupt state
450 //! priorities.
451 //!
452 //! This interrupt controller automatically clears the pending interrupt once the
453 //! interrupt handler is executed.
454 //!
455 //! \param ui32Interrupt specifies the index in the vector table to pend.
456 //! - System exceptions:
457 //!   - INT_NMI_FAULT
458 //!   - INT_PENDSV
459 //!   - INT_SYSTICK
460 //! - Interrupts:
461 //!   - INT_AON_GPIO_EDGE
462 //!   - INT_I2C_IRQ
463 //!   - INT_RFC_CPE_1
464 //!   - INT_AON_RTC_COMB
465 //!   - INT_UART0_COMB
466 //!   - INT_AUX_SWEV0
467 //!   - INT_SSI0_COMB
468 //!   - INT_RFC_CPE_0
469 //!   - INT_RFC_HW_COMB
470 //!   - INT_RFC_CMD_ACK
471 //!   - INT_I2S_IRQ
472 //!   - INT_AUX_SWEV1
473 //!   - INT_WDT_IRQ
474 //!   - INT_GPT0A
475 //!   - INT_GPT0B
476 //!   - INT_GPT1A
477 //!   - INT_GPT1B
478 //!   - INT_GPT2A
479 //!   - INT_GPT2B
480 //!   - INT_GPT3A
481 //!   - INT_GPT3B
482 //!   - INT_CRYPTO_RESULT_AVAIL_IRQ
483 //!   - INT_DMA_DONE_COMB
484 //!   - INT_DMA_ERR
485 //!   - INT_FLASH
486 //!   - INT_SWEV0
487 //!   - INT_AUX_COMB
488 //!   - INT_AON_PROG0
489 //!   - INT_PROG0 (Programmable interrupt, see \ref EventRegister())
490 //!   - INT_AUX_COMPA
491 //!   - INT_AUX_ADC_IRQ
492 //!   - INT_TRNG_IRQ
493 //!   - INT_OSC_COMB
494 //!   - INT_BATMON_COMB
495 //!   - INT_PKA_IRQ
496 //!   - INT_SSI1_COMB
497 //!   - INT_UART1_COMB
498 //!   - INT_AUX_TIMER2_EV0
499 //!
500 //! \return None
501 //!
502 //! \sa \ref IntEnable()
503 //
504 //*****************************************************************************
505 extern void IntPendSet(uint32_t ui32Interrupt);
506 
507 //*****************************************************************************
508 //
509 //! \brief Checks if an interrupt is pending.
510 //!
511 //! This function checks the interrupt controller to see if an interrupt is pending.
512 //!
513 //! The interrupt must be enabled in order for the corresponding interrupt handler
514 //! to be executed, so an interrupt can be pending waiting to be enabled or waiting
515 //! for an interrupt of higher priority to be done executing.
516 //!
517 //! \note This function does not support reading pending status for system exceptions
518 //! (vector table indexes <16).
519 //!
520 //! \param ui32Interrupt specifies the index in the vector table to check pending
521 //! status for.
522 //! - See \ref IntPendSet() for list of valid arguments (except system exceptions).
523 //!
524 //! \return Returns:
525 //! - \c true  : Specified interrupt is pending.
526 //! - \c false : Specified interrupt is not pending.
527 //
528 //*****************************************************************************
529 extern bool IntPendGet(uint32_t ui32Interrupt);
530 
531 //*****************************************************************************
532 //
533 //! \brief Unpends an interrupt.
534 //!
535 //! This function unpends the specified interrupt in the interrupt controller.
536 //! This causes any previously generated interrupts that have not been handled yet
537 //! (due to higher priority interrupts or the interrupt no having been enabled
538 //! yet) to be discarded.
539 //!
540 //! \note It is not possible to unpend the NMI because it takes effect
541 //! immediately when being pended.
542 //!
543 //! \param ui32Interrupt specifies the index in the vector table to unpend.
544 //! - See \ref IntPendSet() for list of valid arguments (except NMI).
545 //!
546 //! \return None
547 //
548 //*****************************************************************************
549 extern void IntPendClear(uint32_t ui32Interrupt);
550 
551 //*****************************************************************************
552 //
553 //! \brief Enables the CPU interrupt.
554 //!
555 //! Allows the CPU to respond to interrupts.
556 //!
557 //! \return Returns:
558 //! - \c true  : Interrupts were disabled and are now enabled.
559 //! - \c false : Interrupts were already enabled when the function was called.
560 //
561 //*****************************************************************************
562 __STATIC_INLINE bool
IntMasterEnable(void)563 IntMasterEnable(void)
564 {
565     // Enable CPU interrupts.
566     return(CPUcpsie());
567 }
568 
569 //*****************************************************************************
570 //
571 //! \brief Disables the CPU interrupts with configurable priority.
572 //!
573 //! Prevents the CPU from receiving interrupts except NMI and hard fault. This
574 //! does not affect the set of interrupts enabled in the interrupt controller;
575 //! it just gates the interrupt from the interrupt controller to the CPU.
576 //!
577 //! \return Returns:
578 //! - \c true  : Interrupts were already disabled when the function was called.
579 //! - \c false : Interrupts were enabled and are now disabled.
580 //
581 //*****************************************************************************
582 __STATIC_INLINE bool
IntMasterDisable(void)583 IntMasterDisable(void)
584 {
585     // Disable CPU interrupts.
586     return(CPUcpsid());
587 }
588 
589 //*****************************************************************************
590 //
591 //! \brief Sets the priority masking level.
592 //!
593 //! This function sets the interrupt priority masking level so that all
594 //! interrupts at the specified or lesser priority level are masked. This
595 //! can be used to globally disable a set of interrupts with priority below
596 //! a predetermined threshold. A value of 0 disables priority
597 //! masking.
598 //!
599 //! Smaller numbers correspond to higher interrupt priorities. So for example
600 //! a priority level mask of 4 will allow interrupts of priority level 0-3,
601 //! and interrupts with a numerical priority of 4 and greater will be blocked.
602 //! The device supports priority levels 0 through 7.
603 //!
604 //! \param ui32PriorityMask is the priority level that will be masked.
605 //! - 0 : Disable priority masking.
606 //! - 1 : Allow priority 0 interrupts, mask interrupts with priority 1-7.
607 //! - 2 : Allow priority 0-1 interrupts, mask interrupts with priority 2-7.
608 //! - 3 : Allow priority 0-2 interrupts, mask interrupts with priority 3-7.
609 //! - 4 : Allow priority 0-3 interrupts, mask interrupts with priority 4-7.
610 //! - 5 : Allow priority 0-4 interrupts, mask interrupts with priority 5-7.
611 //! - 6 : Allow priority 0-5 interrupts, mask interrupts with priority 6-7.
612 //! - 7 : Allow priority 0-6 interrupts, mask interrupts with priority 7.
613 //!
614 //! \return None.
615 //
616 //*****************************************************************************
617 __STATIC_INLINE void
IntPriorityMaskSet(uint32_t ui32PriorityMask)618 IntPriorityMaskSet(uint32_t ui32PriorityMask)
619 {
620     CPUbasepriSet(ui32PriorityMask);
621 }
622 
623 //*****************************************************************************
624 //
625 //! \brief Gets the priority masking level.
626 //!
627 //! This function gets the current setting of the interrupt priority masking
628 //! level. The value returned is the priority level such that all interrupts
629 //! of that and lesser priority are masked. A value of 0 means that priority
630 //! masking is disabled.
631 //!
632 //! Smaller numbers correspond to higher interrupt priorities. So for example
633 //! a priority level mask of 4 will allow interrupts of priority level 0-3,
634 //! and interrupts with a numerical priority of 4 and greater will be blocked.
635 //!
636 //! \return Returns the value of the interrupt priority level mask.
637 //
638 //*****************************************************************************
639 __STATIC_INLINE uint32_t
IntPriorityMaskGet(void)640 IntPriorityMaskGet(void)
641 {
642     return(CPUbasepriGet());
643 }
644 
645 //*****************************************************************************
646 //
647 // Support for DriverLib in ROM:
648 // Redirect to implementation in ROM when available.
649 //
650 //*****************************************************************************
651 #if !defined(DRIVERLIB_NOROM) && !defined(DOXYGEN)
652     #include "../driverlib/rom.h"
653     #ifdef ROM_IntRegister
654         #undef  IntRegister
655         #define IntRegister                     ROM_IntRegister
656     #endif
657     #ifdef ROM_IntUnregister
658         #undef  IntUnregister
659         #define IntUnregister                   ROM_IntUnregister
660     #endif
661     #ifdef ROM_IntPriorityGroupingSet
662         #undef  IntPriorityGroupingSet
663         #define IntPriorityGroupingSet          ROM_IntPriorityGroupingSet
664     #endif
665     #ifdef ROM_IntPriorityGroupingGet
666         #undef  IntPriorityGroupingGet
667         #define IntPriorityGroupingGet          ROM_IntPriorityGroupingGet
668     #endif
669     #ifdef ROM_IntPrioritySet
670         #undef  IntPrioritySet
671         #define IntPrioritySet                  ROM_IntPrioritySet
672     #endif
673     #ifdef ROM_IntPriorityGet
674         #undef  IntPriorityGet
675         #define IntPriorityGet                  ROM_IntPriorityGet
676     #endif
677     #ifdef ROM_IntEnable
678         #undef  IntEnable
679         #define IntEnable                       ROM_IntEnable
680     #endif
681     #ifdef ROM_IntDisable
682         #undef  IntDisable
683         #define IntDisable                      ROM_IntDisable
684     #endif
685     #ifdef ROM_IntPendSet
686         #undef  IntPendSet
687         #define IntPendSet                      ROM_IntPendSet
688     #endif
689     #ifdef ROM_IntPendGet
690         #undef  IntPendGet
691         #define IntPendGet                      ROM_IntPendGet
692     #endif
693     #ifdef ROM_IntPendClear
694         #undef  IntPendClear
695         #define IntPendClear                    ROM_IntPendClear
696     #endif
697 #endif
698 
699 //*****************************************************************************
700 //
701 // Mark the end of the C bindings section for C++ compilers.
702 //
703 //*****************************************************************************
704 #ifdef __cplusplus
705 }
706 #endif
707 
708 #endif // __INTERRUPT_H__
709 
710 //*****************************************************************************
711 //
712 //! Close the Doxygen group.
713 //! @}
714 //! @}
715 //
716 //*****************************************************************************
717