1 /****************************************************************************** 2 * Copyright (c) 2022 Telink Semiconductor (Shanghai) Co., Ltd. ("TELINK") 3 * All rights reserved. 4 * 5 * Licensed under the Apache License, Version 2.0 (the "License"); 6 * you may not use this file except in compliance with the License. 7 * You may obtain a copy of the License at 8 * 9 * http://www.apache.org/licenses/LICENSE-2.0 10 * 11 * Unless required by applicable law or agreed to in writing, software 12 * distributed under the License is distributed on an "AS IS" BASIS, 13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 * See the License for the specific language governing permissions and 15 * limitations under the License. 16 * 17 *****************************************************************************/ 18 #ifndef STACK_BLE_DEBUG_H_ 19 #define STACK_BLE_DEBUG_H_ 20 21 22 23 24 #ifndef DEBUG_PAIRING_ENCRYPTION 25 #define DEBUG_PAIRING_ENCRYPTION 0 26 #endif 27 28 29 /* BLE rf irq timing && log enable */ 30 #ifndef BLE_IRQ_DBG_EN 31 #define BLE_IRQ_DBG_EN 0 32 #endif 33 34 /* BLE Tx fifo log enable */ 35 #ifndef TX_FIFO_DBG_EN 36 #define TX_FIFO_DBG_EN 0 37 #endif 38 39 /* BLE smp trans.. log enable */ 40 #ifndef SMP_DBG_EN 41 #define SMP_DBG_EN 0 42 #endif 43 44 45 #ifndef TX_PUSH_DATA_LOG 46 #define TX_PUSH_DATA_LOG 0 47 #endif 48 49 #ifndef RX_L2CAP_DATA_LOG 50 #define RX_L2CAP_DATA_LOG 0 51 #endif 52 53 54 #ifndef SCHE_DEBUG_DUMP_EN 55 #define SCHE_DEBUG_DUMP_EN 0 56 #endif 57 58 #ifndef SCHE_TIMING_DEBUG_EN 59 #define SCHE_TIMING_DEBUG_EN 0 60 #endif 61 62 63 #ifndef DBG_BOUNDARY_RX 64 #define DBG_BOUNDARY_RX 0 65 #endif 66 67 68 #ifndef DBG_LL_CTRL_LOG_EN 69 #define DBG_LL_CTRL_LOG_EN 0 70 #endif 71 72 73 #ifndef DBG_DLE_DUMP_EN 74 #define DBG_DLE_DUMP_EN 0 75 #endif 76 77 #ifndef DBG_SCHE_TIMING_EN 78 #define DBG_SCHE_TIMING_EN 0 79 #endif 80 81 82 #ifndef DBG_IAL_EN 83 #define DBG_IAL_EN 0 84 #endif 85 86 #ifndef DEB_CIG_MST_EN 87 #define DEB_CIG_MST_EN 0 88 #endif 89 90 #ifndef DEB_CIG_SLV_EN 91 #define DEB_CIG_SLV_EN 0 92 #endif 93 94 #ifndef DEB_BIG_BCST_EN 95 #define DEB_BIG_BCST_EN 0 96 #endif 97 98 #ifndef DEB_BIG_SYNC_EN 99 #define DEB_BIG_SYNC_EN 0 100 #endif 101 102 #ifndef DEB_ISO_TEST_EN 103 #define DEG_ISO_TEST_EN 1 104 #endif 105 106 #ifndef DEB_STRUCT_BUFFER_SIZE_CHECK 107 #define DEB_STRUCT_BUFFER_SIZE_CHECK 1 108 #endif 109 110 111 #if (DBG_SLAVE_CONN_UPDATE) 112 #define SLET_upt_cmd_1 10 113 #define SLET_upt_cmd_2 11 114 #define SLET_upt_cmd_3 12 115 #define SLET_upt_cmd_4 13 116 #define SLET_upt_sync_1 20 117 #define SLET_upt_sync_2 21 118 #define SLET_upt_sync_3 22 119 #define SLET_upt_sync_4 23 120 #endif 121 122 #if 0 123 #define SLET_05_rx_crc 5 124 #define SLET_06_rx_1st 6 125 #define SLET_07_rx_new 7 126 #define SLET_10_tx 10 127 #define SLET_11_c_cmdone 11 128 #define SLET_12_c_1stRxTmt 12 129 #define SLET_13_c_rxTmt 13 130 #define SLET_14_c_rxCrc2 14 131 #endif 132 133 134 135 136 137 #if 0 138 #define SLEV_txFifo_push 17 139 #define SLEV_txFifo_empty 18 140 #define SLEV_txFifo_RX 19 141 #define SLEV_txFifo_post 20 142 #define SLEV_test_event 31 143 144 #define SL16_tf_hw_push 1 145 #define SL16_tf_sw_push 2 146 #define SL16_tf_hw_load1 3 147 #define SL16_tf_sw_load1 4 148 #define SL16_tf_hw_load2 5 149 #define SL16_tf_sw_load2 6 150 #define SL16_tf_hw_RX 7 151 #define SL16_tf_sw_RX 8 152 #define SL16_tf_hw_TX 9 153 #define SL16_tf_sw_TX 10 154 #define SL16_tf_hw_post 11 155 #define SL16_tf_sw_post 12 156 #define SL16_tf_save 13 157 158 #define SL16_seq_notify 15 159 #define SL16_seq_write 16 160 #define SL16_test_2B 17 161 #endif 162 163 164 165 166 #endif /* STACK_BLE_DEBUG_H_ */ 167
