1 /**
2 ******************************************************************************
3 * @file stm32h7rsxx_hal.c
4 * @author MCD Application Team
5 * @brief HAL module driver.
6 * This is the common part of the HAL initialization
7 *
8 ******************************************************************************
9 * @attention
10 *
11 * Copyright (c) 2022 STMicroelectronics.
12 * All rights reserved.
13 *
14 * This software is licensed under terms that can be found in the LICENSE file
15 * in the root directory of this software component.
16 * If no LICENSE file comes with this software, it is provided AS-IS.
17 *
18 ******************************************************************************
19 @verbatim
20 ==============================================================================
21 ##### How to use this driver #####
22 ==============================================================================
23 [..]
24 The common HAL driver contains a set of generic and common APIs that can be
25 used by the PPP peripheral drivers and the user to start using the HAL.
26 [..]
27 The HAL contains two APIs' categories:
28 (+) Common HAL APIs (Version, Init, Tick)
29 (+) Services HAL APIs (DBGMCU, SBS)
30
31 @endverbatim
32 */
33
34 /* Includes ------------------------------------------------------------------*/
35 #include "stm32h7rsxx_hal.h"
36
37 /** @addtogroup STM32H7RSxx_HAL_Driver
38 * @{
39 */
40
41 /** @defgroup HAL HAL
42 * @brief HAL module driver
43 * @{
44 */
45
46 #ifdef HAL_MODULE_ENABLED
47
48 /* Private typedef -----------------------------------------------------------*/
49 /* Private define ------------------------------------------------------------*/
50
51 #define VREFBUF_TIMEOUT_VALUE (uint32_t)10 /* 10 ms */
52
53 /* Value used to increment hide protection level */
54 #define SBS_HDPL_INCREMENT_VALUE (uint8_t)0x6A
55
56 /* Value used to lock/unlock debug functionalities */
57 #define SBS_DEBUG_LOCK_VALUE (uint8_t)0xC3
58 #define SBS_DEBUG_UNLOCK_VALUE (uint8_t)0xB4
59
60 /* Mask for SBS_BKLOCKR register update */
61 #define SBS_BKLOCKR_MASK (SBS_BKLOCKR_PVD_BL | \
62 SBS_BKLOCKR_FLASHECC_BL | \
63 SBS_BKLOCKR_CM7LCKUP_BL | \
64 SBS_BKLOCKR_BKRAMECC_BL | \
65 SBS_BKLOCKR_DTCMECC_BL | \
66 SBS_BKLOCKR_ITCMECC_BL | \
67 SBS_BKLOCKR_ARAM3ECC_BL | \
68 SBS_BKLOCKR_ARAM1ECC_BL)
69
70 /* Private macro -------------------------------------------------------------*/
71 /** @defgroup SBS_Private_Macros Private Macros
72 * @{
73 */
74 #define IS_SBS_TIMER_BREAK_INPUT(__VALUE__) \
75 ((((__VALUE__) & SBS_BKLOCKR_MASK) != 0U) && \
76 (((__VALUE__) & ~SBS_BKLOCKR_MASK) == 0U))
77
78 #define IS_SBS_IO_COMPENSATION_CODE(__VALUE__) \
79 (((__VALUE__) == SBS_IO_CELL_CODE) || \
80 ((__VALUE__) == SBS_IO_REGISTER_CODE))
81
82 #define IS_SBS_IO_COMPENSATION_CELL_PMOS_VALUE(__VALUE__) (((__VALUE__) < 16U))
83 #define IS_SBS_IO_COMPENSATION_CELL_NMOS_VALUE(__VALUE__) (((__VALUE__) < 16U))
84
85 #define IS_SBS_ETHERNET_PHY(__VALUE__) \
86 (((__VALUE__) == SBS_ETHERNET_PHY_GMII_OR_MII) || \
87 ((__VALUE__) == SBS_ETHERNET_PHY_RMII))
88
89 #define IS_SBS_AXISRAM_WS(__VALUE__) \
90 (((__VALUE__) == SBS_AXISRAM_WS_0) || \
91 ((__VALUE__) == SBS_AXISRAM_WS_1))
92 /**
93 * @}
94 */
95
96 /* Private variables ---------------------------------------------------------*/
97 /* Private function prototypes -----------------------------------------------*/
98
99 /* Exported variables --------------------------------------------------------*/
100
101 /** @defgroup HAL_Exported_Variables HAL Exported Variables
102 * @{
103 */
104 __IO uint32_t uwTick;
105 uint32_t uwTickPrio = (1UL << __NVIC_PRIO_BITS); /* Invalid priority */
106 HAL_TickFreqTypeDef uwTickFreq = HAL_TICK_FREQ_DEFAULT; /* 1KHz */
107 /**
108 * @}
109 */
110
111 /* Exported functions --------------------------------------------------------*/
112
113 /** @defgroup HAL_Exported_Functions HAL Exported Functions
114 * @{
115 */
116
117 /** @defgroup HAL_Exported_Functions_Group1 Initialization and de-initialization Functions
118 * @brief Initialization and de-initialization functions
119 *
120 @verbatim
121 ===============================================================================
122 ##### Initialization and de-initialization functions #####
123 ===============================================================================
124 [..] This section provides functions allowing to:
125 (+) Initialize the Flash interface the NVIC allocation and initial time base
126 clock configuration.
127 (+) De-initialize common part of the HAL.
128 (+) Configure the time base source to have 1ms time base with a dedicated
129 Tick interrupt priority.
130 (++) SysTick timer is used by default as source of time base, but user
131 can eventually implement his proper time base source (a general purpose
132 timer for example or other time source), keeping in mind that Time base
133 duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and
134 handled in milliseconds basis.
135 (++) Time base configuration function (HAL_InitTick ()) is called automatically
136 at the beginning of the program after reset by HAL_Init() or at any time
137 when clock is configured, by HAL_RCC_ClockConfig().
138 (++) Source of time base is configured to generate interrupts at regular
139 time intervals. Care must be taken if HAL_Delay() is called from a
140 peripheral ISR process, the Tick interrupt line must have higher priority
141 (numerically lower) than the peripheral interrupt. Otherwise the caller
142 ISR process will be blocked.
143 (++) functions affecting time base configurations are declared as __weak
144 to make override possible in case of other implementations in user file.
145 @endverbatim
146 * @{
147 */
148
149 /**
150 * @brief Configure the time base source, NVIC and any required global low level hardware
151 * by calling the HAL_MspInit() callback function to be optionally defined in user file
152 * stm32h7rsxx_hal_msp.c.
153 *
154 * @note HAL_Init() function is called at the beginning of program after reset and before
155 * the clock configuration.
156 *
157 * @note In the default implementation the System Timer (Systick) is used as source of time base.
158 * The Systick configuration is based on HSI clock, as HSI is the clock
159 * used after a system Reset and the NVIC configuration is set to Priority group 4.
160 * Once done, time base tick starts incrementing: the tick variable counter is incremented
161 * each 1ms in the SysTick_Handler() interrupt handler.
162 *
163 * @retval HAL status
164 */
HAL_Init(void)165 HAL_StatusTypeDef HAL_Init(void)
166 {
167 HAL_StatusTypeDef status = HAL_OK;
168
169 /* Set Interrupt Group Priority */
170 HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
171
172 /* Use SysTick as time base source and configure 1ms tick */
173 if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK)
174 {
175 status = HAL_ERROR;
176 }
177 else
178 {
179 /* Init the low level hardware */
180 HAL_MspInit();
181 }
182
183 /* Return function status */
184 return status;
185 }
186
187 /**
188 * @brief De-initialize common part of the HAL and stop the source of time base.
189 * @note This function is optional.
190 * @retval HAL status
191 */
HAL_DeInit(void)192 HAL_StatusTypeDef HAL_DeInit(void)
193 {
194 /* Reset of all peripherals */
195 __HAL_RCC_APB1_FORCE_RESET();
196 __HAL_RCC_APB1_RELEASE_RESET();
197
198 __HAL_RCC_APB2_FORCE_RESET();
199 __HAL_RCC_APB2_RELEASE_RESET();
200
201 __HAL_RCC_APB4_FORCE_RESET();
202 __HAL_RCC_APB4_RELEASE_RESET();
203
204 __HAL_RCC_APB5_FORCE_RESET();
205 __HAL_RCC_APB5_RELEASE_RESET();
206
207 __HAL_RCC_AHB1_FORCE_RESET();
208 __HAL_RCC_AHB1_RELEASE_RESET();
209
210 __HAL_RCC_AHB2_FORCE_RESET();
211 __HAL_RCC_AHB2_RELEASE_RESET();
212
213 __HAL_RCC_AHB3_FORCE_RESET();
214 __HAL_RCC_AHB3_RELEASE_RESET();
215
216 __HAL_RCC_AHB4_FORCE_RESET();
217 __HAL_RCC_AHB4_RELEASE_RESET();
218
219 __HAL_RCC_AHB5_FORCE_RESET();
220 __HAL_RCC_AHB5_RELEASE_RESET();
221
222 /* De-Init the low level hardware */
223 HAL_MspDeInit();
224
225 /* Return function status */
226 return HAL_OK;
227 }
228
229 /**
230 * @brief Initialize the MSP.
231 * @retval None
232 */
HAL_MspInit(void)233 __weak void HAL_MspInit(void)
234 {
235 /* NOTE : This function should not be modified, when the callback is needed,
236 the HAL_MspInit could be implemented in the user file
237 */
238 }
239
240 /**
241 * @brief DeInitialize the MSP.
242 * @retval None
243 */
HAL_MspDeInit(void)244 __weak void HAL_MspDeInit(void)
245 {
246 /* NOTE : This function should not be modified, when the callback is needed,
247 the HAL_MspDeInit could be implemented in the user file
248 */
249 }
250
251 /**
252 * @brief This function configures the source of the time base:
253 * The time source is configured to have 1ms time base with a dedicated
254 * Tick interrupt priority.
255 * @note This function is called automatically at the beginning of program after
256 * reset by HAL_Init() or at any time when clock is reconfigured by HAL_RCC_ClockConfig().
257 * @note In the default implementation, SysTick timer is the source of time base.
258 * It is used to generate interrupts at regular time intervals.
259 * Care must be taken if HAL_Delay() is called from a peripheral ISR process,
260 * The SysTick interrupt must have higher priority (numerically lower)
261 * than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
262 * The function is declared as __weak to be overwritten in case of other
263 * implementation in user file.
264 * @param TickPriority Tick interrupt priority.
265 * @retval HAL status
266 */
HAL_InitTick(uint32_t TickPriority)267 __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
268 {
269 HAL_StatusTypeDef status = HAL_OK;
270
271 /* Check uwTickFreq for MisraC 2012 (even if uwTickFreq is a enum type that doesn't take the value zero)*/
272 if ((uint32_t)uwTickFreq != 0U)
273 {
274 /*Configure the SysTick to have interrupt in 1ms time basis*/
275 if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / (uint32_t)uwTickFreq)) == 0U)
276 {
277 /* Configure the SysTick IRQ priority */
278 if (TickPriority < (1UL << __NVIC_PRIO_BITS))
279 {
280 HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
281 uwTickPrio = TickPriority;
282 }
283 else
284 {
285 status = HAL_ERROR;
286 }
287 }
288 else
289 {
290 status = HAL_ERROR;
291 }
292 }
293 else
294 {
295 status = HAL_ERROR;
296 }
297
298 /* Return function status */
299 return status;
300 }
301
302 /**
303 * @}
304 */
305
306 /** @defgroup HAL_Exported_Functions_Group2 HAL Control functions
307 * @brief HAL Control functions
308 *
309 @verbatim
310 ===============================================================================
311 ##### HAL Control functions #####
312 ===============================================================================
313 [..] This section provides functions allowing to:
314 (+) Provide a tick value in millisecond
315 (+) Provide a blocking delay in millisecond
316 (+) Suspend the time base source interrupt
317 (+) Resume the time base source interrupt
318 (+) Get the HAL API driver version
319 (+) Get the device identifier
320 (+) Get the device revision identifier
321
322 @endverbatim
323 * @{
324 */
325
326 /**
327 * @brief This function is called to increment a global variable "uwTick"
328 * used as application time base.
329 * @note In the default implementation, this variable is incremented each 1ms
330 * in SysTick ISR.
331 * @note This function is declared as __weak to be overwritten in case of other
332 * implementations in user file.
333 * @retval None
334 */
HAL_IncTick(void)335 __weak void HAL_IncTick(void)
336 {
337 uwTick += (uint32_t)uwTickFreq;
338 }
339
340 /**
341 * @brief Provide a tick value in millisecond.
342 * @note This function is declared as __weak to be overwritten in case of other
343 * implementations in user file.
344 * @retval tick value
345 */
HAL_GetTick(void)346 __weak uint32_t HAL_GetTick(void)
347 {
348 return uwTick;
349 }
350
351 /**
352 * @brief This function returns a tick priority.
353 * @retval tick priority
354 */
HAL_GetTickPrio(void)355 uint32_t HAL_GetTickPrio(void)
356 {
357 return uwTickPrio;
358 }
359
360 /**
361 * @brief Set new tick Freq.
362 * @param Freq tick frequency
363 * @retval HAL status
364 */
HAL_SetTickFreq(HAL_TickFreqTypeDef Freq)365 HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq)
366 {
367 HAL_StatusTypeDef status = HAL_OK;
368 HAL_TickFreqTypeDef prevTickFreq;
369
370 if (uwTickFreq != Freq)
371 {
372 /* Back up uwTickFreq frequency */
373 prevTickFreq = uwTickFreq;
374
375 /* Update uwTickFreq global variable used by HAL_InitTick() */
376 uwTickFreq = Freq;
377
378 /* Apply the new tick Freq */
379 status = HAL_InitTick(uwTickPrio);
380 if (status != HAL_OK)
381 {
382 /* Restore previous tick frequency */
383 uwTickFreq = prevTickFreq;
384 }
385 }
386
387 return status;
388 }
389
390 /**
391 * @brief Return tick frequency.
392 * @retval Tick frequency.
393 * Value of @ref HAL_TickFreqTypeDef.
394 */
HAL_GetTickFreq(void)395 HAL_TickFreqTypeDef HAL_GetTickFreq(void)
396 {
397 return uwTickFreq;
398 }
399
400 /**
401 * @brief This function provides minimum delay (in milliseconds) based
402 * on variable incremented.
403 * @note In the default implementation , SysTick timer is the source of time base.
404 * It is used to generate interrupts at regular time intervals where uwTick
405 * is incremented.
406 * @note This function is declared as __weak to be overwritten in case of other
407 * implementations in user file.
408 * @param Delay specifies the delay time length, in milliseconds.
409 * @retval None
410 */
HAL_Delay(uint32_t Delay)411 __weak void HAL_Delay(uint32_t Delay)
412 {
413 uint32_t tickstart = HAL_GetTick();
414 uint32_t wait = Delay;
415
416 /* Add a period to ensure minimum wait */
417 if (wait < HAL_MAX_DELAY)
418 {
419 wait += (uint32_t)uwTickFreq;
420 }
421
422 while ((HAL_GetTick() - tickstart) < wait)
423 {
424 }
425 }
426
427 /**
428 * @brief Suspend Tick increment.
429 * @note In the default implementation , SysTick timer is the source of time base. It is
430 * used to generate interrupts at regular time intervals. Once HAL_SuspendTick()
431 * is called, the SysTick interrupt will be disabled and so Tick increment
432 * is suspended.
433 * @note This function is declared as __weak to be overwritten in case of other
434 * implementations in user file.
435 * @retval None
436 */
HAL_SuspendTick(void)437 __weak void HAL_SuspendTick(void)
438 {
439 /* Disable SysTick Interrupt */
440 SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk;
441 }
442
443 /**
444 * @brief Resume Tick increment.
445 * @note In the default implementation , SysTick timer is the source of time base. It is
446 * used to generate interrupts at regular time intervals. Once HAL_ResumeTick()
447 * is called, the SysTick interrupt will be enabled and so Tick increment
448 * is resumed.
449 * @note This function is declared as __weak to be overwritten in case of other
450 * implementations in user file.
451 * @retval None
452 */
HAL_ResumeTick(void)453 __weak void HAL_ResumeTick(void)
454 {
455 /* Enable SysTick Interrupt */
456 SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk;
457 }
458
459 /**
460 * @brief Return the HAL revision.
461 * @retval version : 0xXYZR (8bits for each decimal, R for RC)
462 */
HAL_GetHalVersion(void)463 uint32_t HAL_GetHalVersion(void)
464 {
465 return STM32H7RSXX_HAL_VERSION;
466 }
467
468 /**
469 * @brief Return the device revision identifier.
470 * @retval Device revision identifier
471 */
HAL_GetREVID(void)472 uint32_t HAL_GetREVID(void)
473 {
474 return ((DBGMCU->IDCODE & DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos);
475 }
476
477 /**
478 * @brief Return the device identifier.
479 * @retval Device identifier
480 */
HAL_GetDEVID(void)481 uint32_t HAL_GetDEVID(void)
482 {
483 return (DBGMCU->IDCODE & DBGMCU_IDCODE_DEV_ID);
484 }
485
486 /**
487 * @brief Return the first word of the unique device identifier (UID based on 96 bits)
488 * @note The read address belongs to an area which may contain virgin data generating
489 * double ECC error (as never programmed). Thus, in case of cache activation
490 * the address range 0x08FFF000-0x08FFFFFF should be defined as non-cacheable
491 * through the MPU.
492 * @retval Device identifier
493 */
HAL_GetUIDw0(void)494 uint32_t HAL_GetUIDw0(void)
495 {
496 return (READ_REG(*((uint32_t *)UID_BASE)));
497 }
498
499 /**
500 * @brief Return the second word of the unique device identifier (UID based on 96 bits)
501 * @note The read address belongs to an area which may contain virgin data generating
502 * double ECC error (as never programmed). Thus, in case of cache activation
503 * the address range 0x08FFF000-0x08FFFFFF should be defined as non-cacheable
504 * through the MPU.
505 * @retval Device identifier
506 */
HAL_GetUIDw1(void)507 uint32_t HAL_GetUIDw1(void)
508 {
509 return (READ_REG(*((uint32_t *)(UID_BASE + 4U))));
510 }
511
512 /**
513 * @brief Return the third word of the unique device identifier (UID based on 96 bits)
514 * @note The read address belongs to an area which may contain virgin data generating
515 * double ECC error (as never programmed). Thus, in case of cache activation
516 * the address range 0x08FFF000-0x08FFFFFF should be defined as non-cacheable
517 * through the MPU.
518 * @retval Device identifier
519 */
HAL_GetUIDw2(void)520 uint32_t HAL_GetUIDw2(void)
521 {
522 return (READ_REG(*((uint32_t *)(UID_BASE + 8U))));
523 }
524 /**
525 * @}
526 */
527
528 /** @defgroup HAL_Exported_Functions_Group3 HAL Debug functions
529 * @brief HAL Debug functions
530 *
531 @verbatim
532 ===============================================================================
533 ##### HAL Debug functions #####
534 ===============================================================================
535 [..] This section provides functions allowing to:
536 (+) Enable/Disable Debug module during SLEEP mode
537 (+) Enable/Disable Debug module during STOP mode
538 (+) Enable/Disable Debug module during STANDBY mode
539
540 @endverbatim
541 * @{
542 */
543
544 /**
545 * @brief Enable the Debug Module during SLEEP mode.
546 * @retval None
547 */
HAL_DBGMCU_EnableDBGSleepMode(void)548 void HAL_DBGMCU_EnableDBGSleepMode(void)
549 {
550 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
551 }
552
553 /**
554 * @brief Disable the Debug Module during SLEEP mode.
555 * @retval None
556 */
HAL_DBGMCU_DisableDBGSleepMode(void)557 void HAL_DBGMCU_DisableDBGSleepMode(void)
558 {
559 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
560 }
561
562 /**
563 * @brief Enable the Debug Module during STOP mode.
564 * @retval None
565 */
HAL_DBGMCU_EnableDBGStopMode(void)566 void HAL_DBGMCU_EnableDBGStopMode(void)
567 {
568 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
569 }
570
571 /**
572 * @brief Disable the Debug Module during STOP mode.
573 * @retval None
574 */
HAL_DBGMCU_DisableDBGStopMode(void)575 void HAL_DBGMCU_DisableDBGStopMode(void)
576 {
577 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
578 }
579
580 /**
581 * @brief Enable the Debug Module during STANDBY mode.
582 * @retval None
583 */
HAL_DBGMCU_EnableDBGStandbyMode(void)584 void HAL_DBGMCU_EnableDBGStandbyMode(void)
585 {
586 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
587 }
588
589 /**
590 * @brief Disable the Debug Module during STANDBY mode.
591 * @retval None
592 */
HAL_DBGMCU_DisableDBGStandbyMode(void)593 void HAL_DBGMCU_DisableDBGStandbyMode(void)
594 {
595 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
596 }
597
598 /**
599 * @}
600 */
601
602 /** @defgroup HAL_Exported_Functions_Group4 HAL SBS configuration functions
603 * @brief HAL SBS configuration functions
604 *
605 @verbatim
606 ===============================================================================
607 ##### HAL SBS configuration functions #####
608 ===============================================================================
609 [..] This section provides functions allowing to:
610 (+) Increment/get the HDPL value
611 (+) Configure the debug access
612 (+) Configure timer break inputs
613 (+) Enable/Disable the I/O analog switch voltage booster
614 (+) Enable/Disable the I/O analog switch supplied by VDD
615 (+) Configure/Enable/Disable the compensation cell (IO, XSPI1, XSPI2)
616
617 @endverbatim
618 * @{
619 */
620
621 /**
622 * @brief Get the boot address holding the initial vector table for Cortex-M7.
623 * @retval Physical boot address used by the Cortex-M7 after reset
624 */
HAL_SBS_GetBootAddress(void)625 uint32_t HAL_SBS_GetBootAddress(void)
626 {
627 return SBS->BOOTSR;
628 }
629
630 /**
631 * @brief Increment hise protection level.
632 * @retval None
633 */
HAL_SBS_IncrementHDPLValue(void)634 void HAL_SBS_IncrementHDPLValue(void)
635 {
636 MODIFY_REG(SBS->HDPLCR, SBS_HDPLCR_INCR_HDPL, SBS_HDPL_INCREMENT_VALUE);
637 }
638
639 /**
640 * @brief Get the current value of the hide protection level.
641 * @retval Current hide protection level
642 * This value is one of @ref SBS_HDPL_Value
643 */
HAL_SBS_GetHDPLValue(void)644 uint32_t HAL_SBS_GetHDPLValue(void)
645 {
646 return (SBS->HDPLSR & SBS_HDPLSR_HDPL);
647 }
648
649 /**
650 * @brief Open the device access port.
651 * @note This function can be only used when device state is Closed.
652 * @retval None
653 */
HAL_SBS_OpenAccessPort(void)654 void HAL_SBS_OpenAccessPort(void)
655 {
656 MODIFY_REG(SBS->DBGCR, SBS_DBGCR_AP_UNLOCK, SBS_DEBUG_UNLOCK_VALUE);
657 }
658
659 /**
660 * @brief Open the debug when the hide protection level is authorized.
661 * @note This function can be only used when device state is Closed.
662 * @retval None
663 */
HAL_SBS_OpenDebug(void)664 void HAL_SBS_OpenDebug(void)
665 {
666 MODIFY_REG(SBS->DBGCR, SBS_DBGCR_DBG_UNLOCK, (SBS_DEBUG_UNLOCK_VALUE << SBS_DBGCR_DBG_UNLOCK_Pos));
667 }
668
669 /**
670 * @brief Configure the authenticated debug hide protection level.
671 * @note This function can be only used when device state is Closed.
672 * @param Level Hide protection level where the authenticated debug opens
673 * This value is one of @ref SBS_HDPL_Value (except SBS_HDPL_VALUE_0)
674 * @retval HAL_OK if parameter is correct
675 * HAL_ERROR otherwise
676 */
HAL_SBS_ConfigDebugLevel(uint32_t Level)677 HAL_StatusTypeDef HAL_SBS_ConfigDebugLevel(uint32_t Level)
678 {
679 /* Check the parameter */
680 assert_param(IS_SBS_HDPL(Level));
681
682 if (Level != SBS_HDPL_VALUE_0)
683 {
684 MODIFY_REG(SBS->DBGCR, SBS_DBGCR_DBG_AUTH_HDPL, (Level << SBS_DBGCR_DBG_AUTH_HDPL_Pos));
685 return HAL_OK;
686 }
687 else
688 {
689 return HAL_ERROR;
690 }
691 }
692
693 /**
694 * @brief Get the current value of the hide protection level.
695 * @note This function can be only used when device state is Closed.
696 * @retval Current hide protection level
697 * This value is one of @ref SBS_HDPL_Value
698 */
HAL_SBS_GetDebugLevel(void)699 uint32_t HAL_SBS_GetDebugLevel(void)
700 {
701 return ((SBS->DBGCR & SBS_DBGCR_DBG_AUTH_HDPL) >> SBS_DBGCR_DBG_AUTH_HDPL_Pos);
702 }
703
704 /**
705 * @brief Unlock the access to the debug control register.
706 * @note This function can be only used when device state is Closed.
707 * @retval None
708 */
HAL_SBS_UnlockDebugConfig(void)709 void HAL_SBS_UnlockDebugConfig(void)
710 {
711 MODIFY_REG(SBS->DBGLOCKR, SBS_DBGLOCKR_DBGCFG_LOCK, SBS_DEBUG_UNLOCK_VALUE);
712 }
713
714 /**
715 * @brief Lock the access to the debug control register.
716 * @note This function can be only used when device state is Closed.
717 * @retval None
718 */
HAL_SBS_LockDebugConfig(void)719 void HAL_SBS_LockDebugConfig(void)
720 {
721 MODIFY_REG(SBS->DBGLOCKR, SBS_DBGLOCKR_DBGCFG_LOCK, SBS_DEBUG_LOCK_VALUE);
722 }
723
724 /**
725 * @brief Configure the command passed to the RSS for execution at next reset.
726 * @param Cmd Command passed to the RSS for execution at next reset
727 * This value is between 0 and 0xFFFF
728 * @retval None
729 */
HAL_SBS_ConfigRSSCommand(uint32_t Cmd)730 void HAL_SBS_ConfigRSSCommand(uint32_t Cmd)
731 {
732 MODIFY_REG(SBS->RSSCMDR, SBS_RSSCMDR_RSSCMD, Cmd);
733 }
734
735 /**
736 * @brief Get the command passed to the RSS for execution at next reset.
737 * @retval Command passed to the RSS for execution at next reset
738 */
HAL_SBS_GetRSSCommand(void)739 uint32_t HAL_SBS_GetRSSCommand(void)
740 {
741 return (SBS->RSSCMDR & SBS_RSSCMDR_RSSCMD);
742 }
743
744 /**
745 * @brief Enable the I/O analog switch voltage booster
746 * @note Insure low VDDA voltage operation with I/O analog switch control
747 * @retval None
748 */
HAL_SBS_EnableIOAnalogBooster(void)749 void HAL_SBS_EnableIOAnalogBooster(void)
750 {
751 MODIFY_REG(SBS->PMCR, (SBS_PMCR_BOOSTEN | SBS_PMCR_BOOSTVDDSEL), SBS_PMCR_BOOSTEN);
752 }
753
754 /**
755 * @brief Disable the I/O analog switch voltage booster
756 * @retval None
757 */
HAL_SBS_DisableIOAnalogBooster(void)758 void HAL_SBS_DisableIOAnalogBooster(void)
759 {
760 CLEAR_BIT(SBS->PMCR, SBS_PMCR_BOOSTEN);
761 }
762
763 /**
764 * @brief Enable the I/O analog switch supplied by VDD
765 * @note To be used when I/O analog switch voltage booster is not enabled
766 * @retval None
767 */
HAL_SBS_EnableIOAnalogSwitchVdd(void)768 void HAL_SBS_EnableIOAnalogSwitchVdd(void)
769 {
770 MODIFY_REG(SBS->PMCR, (SBS_PMCR_BOOSTEN | SBS_PMCR_BOOSTVDDSEL), SBS_PMCR_BOOSTVDDSEL);
771 }
772
773 /**
774 * @brief Disable the I/O analog switch supplied by VDD
775 * @retval None
776 */
HAL_SBS_DisableIOAnalogSwitchVdd(void)777 void HAL_SBS_DisableIOAnalogSwitchVdd(void)
778 {
779 CLEAR_BIT(SBS->PMCR, SBS_PMCR_BOOSTVDDSEL);
780 }
781
782 /**
783 * @brief Configure the Ethernet PHY interface
784 * @param Config specifies the Ethernet PHY interface
785 * This parameter can be one of the following values:
786 * @arg SBS_ETHERNET_PHY_GMII_OR_MII GMMI or MII selection
787 * @arg SBS_ETHERNET_PHY_RMII RMII selection
788 * @retval None
789 */
HAL_SBS_ConfigEthernetPHY(uint32_t Config)790 void HAL_SBS_ConfigEthernetPHY(uint32_t Config)
791 {
792 /* Check the parameter */
793 assert_param(IS_SBS_ETHERNET_PHY(Config));
794
795 MODIFY_REG(SBS->PMCR, SBS_PMCR_ETH_PHYSEL, Config);
796 }
797
798 /**
799 * @brief Configure the ECC AXISRAMs wait state when ECC=0
800 * @param Config specifies the number of wait state
801 * This parameter can be one of the following values:
802 * @arg SBS_AXISRAM_WS_0 0 wait state selection
803 * @arg SBS_AXISRAM_WS_1 1 wait state selection
804 * @retval None
805 */
HAL_SBS_ConfigAXISRAMWaitState(uint32_t Config)806 void HAL_SBS_ConfigAXISRAMWaitState(uint32_t Config)
807 {
808 /* Check the parameter */
809 assert_param(IS_SBS_AXISRAM_WS(Config));
810
811 MODIFY_REG(SBS->PMCR, SBS_PMCR_AXISRAM_WS, Config);
812 }
813
814 /**
815 * @brief Enable the compensation cell
816 * @param Selection specifies the concerned compensation cell
817 * This parameter can the combination of the following values:
818 * @arg SBS_IO_ANALOG_CELL Compensation cell for the I/O analog switches
819 * @arg SBS_IO_XSPI1_CELL Compensation cell for the I/O of the XSPI1
820 * @arg SBS_IO_XSPI2_CELL Compensation cell for the I/O of the XSPI2
821 * @retval None
822 */
HAL_SBS_EnableCompensationCell(uint32_t Selection)823 void HAL_SBS_EnableCompensationCell(uint32_t Selection)
824 {
825 /* Check the parameter */
826 assert_param(IS_SBS_COMPENSATION_CELL(Selection));
827
828 SET_BIT(SBS->CCCSR, Selection);
829 }
830
831 /**
832 * @brief Disable the compensation cell
833 * @param Selection specifies the concerned compensation cell
834 * This parameter can the combination of the following values:
835 * @arg SBS_IO_ANALOG_CELL Compensation cell for the I/O analog switches
836 * @arg SBS_IO_XSPI1_CELL Compensation cell for the I/O of the XSPI1
837 * @arg SBS_IO_XSPI2_CELL Compensation cell for the I/O of the XSPI2
838 * @retval None
839 */
HAL_SBS_DisableCompensationCell(uint32_t Selection)840 void HAL_SBS_DisableCompensationCell(uint32_t Selection)
841 {
842 /* Check the parameter */
843 assert_param(IS_SBS_COMPENSATION_CELL(Selection));
844
845 MODIFY_REG(SBS->CCCSR, Selection, 0U);
846 }
847
848 /**
849 * @brief Get the compensation cell ready status
850 * @param Selection specifies the concerned compensation cell
851 * This parameter can one of the following values:
852 * @arg SBS_IO_ANALOG_CELL_READY Compensation cell for the I/O analog switches
853 * @arg SBS_IO_XSPI1_CELL_READY Compensation cell for the I/O of the XSPI1
854 * @arg SBS_IO_XSPI2_CELL_READY Compensation cell for the I/O of the XSPI2
855 * @retval Ready status (1 or 0)
856 */
HAL_SBS_GetCompensationCellReadyStatus(uint32_t Selection)857 uint32_t HAL_SBS_GetCompensationCellReadyStatus(uint32_t Selection)
858 {
859 /* Check the parameter */
860 assert_param(IS_SBS_COMPENSATION_CELL_READY(Selection));
861
862 return (((SBS->CCCSR & Selection) == 0U) ? 0UL : 1UL);
863 }
864
865 /**
866 * @brief Configure the code selection for the compensation cell
867 * @param Selection specifies the concerned compensation cell
868 * This parameter can one of the following values:
869 * @arg SBS_IO_ANALOG_CELL Compensation cell for the I/O analog switches
870 * @arg SBS_IO_XSPI1_CELL Compensation cell for the I/O of the XSPI1
871 * @arg SBS_IO_XSPI2_CELL Compensation cell for the I/O of the XSPI2
872 * @param Code code selection to be applied for the I/O compensation cell
873 * This parameter can be one of the following values:
874 * @arg SBS_IO_CELL_CODE Code from the cell (available in the SBS_CCVALR)
875 * @arg SBS_IO_REGISTER_CODE Code from the compensation cell code register (SBS_CCSWVALR)
876 * @param NmosValue In case SBS_IO_REGISTER_CODE is selected, it provides the Nmos value
877 * to apply in range 0 to 15 else this parameter is not used
878 * @param PmosValue In case SBS_IO_REGISTER_CODE is selected, it provides the Pmos value
879 * to apply in range 0 to 15 else this parameter is not used
880 * @retval None
881 */
HAL_SBS_ConfigCompensationCell(uint32_t Selection,uint32_t Code,uint32_t NmosValue,uint32_t PmosValue)882 void HAL_SBS_ConfigCompensationCell(uint32_t Selection, uint32_t Code, uint32_t NmosValue, uint32_t PmosValue)
883 {
884 uint32_t offset;
885
886 /* Check the parameters */
887 assert_param(IS_SBS_COMPENSATION_CELL(Selection));
888 assert_param(IS_SBS_IO_COMPENSATION_CODE(Code));
889
890 if (Code == SBS_IO_REGISTER_CODE)
891 {
892 /* Check the parameters */
893 assert_param(IS_SBS_IO_COMPENSATION_CELL_NMOS_VALUE(NmosValue));
894 assert_param(IS_SBS_IO_COMPENSATION_CELL_PMOS_VALUE(PmosValue));
895
896 offset = ((Selection == SBS_IO_ANALOG_CELL) ? 0U : ((Selection == SBS_IO_XSPI1_CELL) ? 8U : 16U));
897
898 MODIFY_REG(SBS->CCSWVALR, (0xFFU << offset), ((NmosValue << offset) | (PmosValue << (offset + 4U))));
899 }
900
901 MODIFY_REG(SBS->CCCSR, (Selection << 1U), (Code << (POSITION_VAL(Selection) + 1U)));
902 }
903
904 /**
905 * @brief Get the code selection for the compensation cell
906 * @param Selection specifies the concerned compensation cell
907 * This parameter can one of the following values:
908 * @arg SBS_IO_ANALOG_CELL Compensation cell for the I/O analog switches
909 * @arg SBS_IO_XSPI1_CELL Compensation cell for the I/O of the XSPI1
910 * @arg SBS_IO_XSPI2_CELL Compensation cell for the I/O of the XSPI2
911 * @param pCode pointer code selection
912 * This parameter can be one of the following values:
913 * @arg SBS_IO_CELL_CODE Code from the cell (available in the SBS_CCVALR)
914 * @arg SBS_IO_REGISTER_CODE Code from the compensation cell code register (SBS_CCSWVALR)
915 * @param pNmosValue pointer to the Nmos value in range 0 to 15
916 * @param pPmosValue pointer to the Pmos value in range 0 to 15
917 * @retval HAL_OK (all values available) or HAL_ERROR (check parameters)
918 */
HAL_SBS_GetCompensationCell(uint32_t Selection,uint32_t * pCode,uint32_t * pNmosValue,uint32_t * pPmosValue)919 HAL_StatusTypeDef HAL_SBS_GetCompensationCell(uint32_t Selection, uint32_t *pCode, uint32_t *pNmosValue,
920 uint32_t *pPmosValue)
921 {
922 uint32_t reg;
923 uint32_t offset;
924 HAL_StatusTypeDef status = HAL_ERROR;
925
926 /* Check parameters */
927 if ((pCode != NULL) && (pNmosValue != NULL) && (pPmosValue != NULL))
928 {
929 *pCode = ((SBS->CCCSR & (Selection << 1U)) == 0U) ? SBS_IO_CELL_CODE : SBS_IO_REGISTER_CODE;
930
931 reg = (*pCode == SBS_IO_CELL_CODE) ? (SBS->CCVALR) : (SBS->CCSWVALR);
932 offset = ((Selection == SBS_IO_ANALOG_CELL) ? 0U : ((Selection == SBS_IO_XSPI1_CELL) ? 8U : 16U));
933
934 *pNmosValue = ((reg >> offset) & 0xFU);
935 *pPmosValue = ((reg >> (offset + 4U)) & 0xFU);
936
937 status = HAL_OK;
938 }
939 return status;
940 }
941
942 /**
943 * @brief Enable the high speed at low voltage
944 * @param Selection specifies the concerned IOs
945 * This parameter can the combination of the following values:
946 * @arg SBS_IO_ANALOG_HSLV High speed at low voltage for the I/O analog switches
947 * @arg SBS_IO_XSPI1_HSLV High speed at low voltage for the I/O of the XSPI1
948 * @arg SBS_IO_XSPI2_HSLV High speed at low voltage for the I/O of the XSPI2
949 * @retval None
950 */
HAL_SBS_EnableIOSpeedOptimize(uint32_t Selection)951 void HAL_SBS_EnableIOSpeedOptimize(uint32_t Selection)
952 {
953 /* Check the parameter */
954 assert_param(IS_SBS_IOHSLV(Selection));
955
956 SET_BIT(SBS->CCCSR, Selection);
957 }
958
959 /**
960 * @brief Disable the high speed at low voltage
961 * @param Selection specifies the concerned IOs
962 * This parameter can the combination of the following values:
963 * @arg SBS_IO_ANALOG_HSLV High speed at low voltage for the I/O analog switches
964 * @arg SBS_IO_XSPI1_HSLV High speed at low voltage for the I/O of the XSPI1
965 * @arg SBS_IO_XSPI2_HSLV High speed at low voltage for the I/O of the XSPI2
966 * @retval None
967 */
HAL_SBS_DisableIOSpeedOptimize(uint32_t Selection)968 void HAL_SBS_DisableIOSpeedOptimize(uint32_t Selection)
969 {
970 /* Check the parameter */
971 assert_param(IS_SBS_IOHSLV(Selection));
972
973 MODIFY_REG(SBS->CCCSR, Selection, 0U);
974 }
975
976 /**
977 * @brief Configure the Timer Break input for error flag(s).
978 * @note When a configuration is set, only a system reset can reset it.
979 * @param Input input configuration
980 * This parameter can be one or a combinartion of the following values:
981 * @arg SBS_TIMER_BREAK_LOCK_PVD PVD flag
982 * @arg SBS_TIMER_BREAK_LOCK_FLASH FLASH double ECC error flag
983 * @arg SBS_TIMER_BREAK_LOCK_CORE M7 LOCKUP (Hardfault) output
984 * @arg SBS_TIMER_BREAK_LOCK_ITCM ITCM double ECC error flag
985 * @arg SBS_TIMER_BREAK_LOCK_DTCM DTCM double ECC error flag
986 * @arg SBS_TIMER_BREAK_LOCK_AXISRAM1 AXISRAM1 double ECC error flag
987 * @arg SBS_TIMER_BREAK_LOCK_AXISRAM3 AXISRAM3 double ECC error flag
988 * @arg SBS_TIMER_BREAK_LOCK_BKPRAM Backup SRAM double ECC error flag
989 * @retval None
990 */
HAL_SBS_ConfigTimerBreakInput(uint32_t Input)991 void HAL_SBS_ConfigTimerBreakInput(uint32_t Input)
992 {
993 /* Check the parameter */
994 assert_param(IS_SBS_TIMER_BREAK_INPUT(Input));
995
996 SET_BIT(SBS->BKLOCKR, Input);
997 }
998
999 /**
1000 * @brief Get the Timer Break input configuration.
1001 * @note When a configuration is set, only a system reset can reset it.
1002 * @retval Timer break input configuration
1003 * This return value can be one or a combinartion of the following values:
1004 * @arg SBS_TIMER_BREAK_LOCK_PVD PVD flag
1005 * @arg SBS_TIMER_BREAK_LOCK_FLASH FLASH double ECC error flag
1006 * @arg SBS_TIMER_BREAK_LOCK_CORE M7 LOCKUP (Hardfault) output
1007 * @arg SBS_TIMER_BREAK_LOCK_ITCM ITCM double ECC error flag
1008 * @arg SBS_TIMER_BREAK_LOCK_DTCM DTCM double ECC error flag
1009 * @arg SBS_TIMER_BREAK_LOCK_AXISRAM1 AXISRAM1 double ECC error flag
1010 * @arg SBS_TIMER_BREAK_LOCK_AXISRAM3 AXISRAM3 double ECC error flag
1011 * @arg SBS_TIMER_BREAK_LOCK_BKPRAM Backup SRAM double ECC error flag
1012 */
HAL_SBS_GetTimerBreakInputConfig(void)1013 uint32_t HAL_SBS_GetTimerBreakInputConfig(void)
1014 {
1015 return (SBS->BKLOCKR & SBS_BKLOCKR_MASK);
1016 }
1017
1018 /**
1019 * @brief Configure the source input used for EXTI.
1020 * @param Exti EXTI event to be configured
1021 * This parameter should be between 0 and 15
1022 * @param Port Port whom pin is used
1023 * This parameter can be one of the following values:
1024 * @arg SBS_EXTI_PIN_PORTA Port A pin input of EXTI event detection
1025 * @arg SBS_EXTI_PIN_PORTB Port B pin input of EXTI event detection
1026 * @arg SBS_EXTI_PIN_PORTC Port C pin input of EXTI event detection
1027 * @arg SBS_EXTI_PIN_PORTD Port D pin input of EXTI event detection
1028 * @arg SBS_EXTI_PIN_PORTE Port E pin input of EXTI event detection
1029 * @arg SBS_EXTI_PIN_PORTF Port F pin input of EXTI event detection
1030 * @arg SBS_EXTI_PIN_PORTG Port G pin input of EXTI event detection
1031 * @arg SBS_EXTI_PIN_PORTH Port H pin input of EXTI event detection
1032 * @arg SBS_EXTI_PIN_PORTM Port M pin input of EXTI event detection
1033 * @arg SBS_EXTI_PIN_PORTN Port N pin input of EXTI event detection
1034 * @arg SBS_EXTI_PIN_PORTO Port O pin input of EXTI event detection
1035 * @arg SBS_EXTI_PIN_PORTP Port P pin input of EXTI event detection
1036 * @retval None
1037 */
HAL_SBS_EXTIConfig(uint32_t Exti,uint32_t Port)1038 void HAL_SBS_EXTIConfig(uint32_t Exti, uint32_t Port)
1039 {
1040 uint32_t reg;
1041 uint32_t offset;
1042
1043 /* Check the parameters */
1044 assert_param(IS_SBS_EXTI_INPUT(Exti));
1045 assert_param(IS_SBS_EXTI_PIN(Port));
1046
1047 reg = (Exti / 4U);
1048 offset = (4U * (Exti % 4U));
1049
1050 MODIFY_REG(SBS->EXTICR[reg], (0xFU << offset), (Port << offset));
1051 }
1052
1053 /**
1054 * @brief Get the source input used for EXTI.
1055 * @param Exti EXTI configuration requested
1056 * This parameter should be between 0 and 15
1057 * @retval Return value is port whom pin is used
1058 * This return value can be one of the following values:
1059 * @arg SBS_EXTI_PIN_PORTA Port A pin input of EXTI event detection
1060 * @arg SBS_EXTI_PIN_PORTB Port B pin input of EXTI event detection
1061 * @arg SBS_EXTI_PIN_PORTC Port C pin input of EXTI event detection
1062 * @arg SBS_EXTI_PIN_PORTD Port D pin input of EXTI event detection
1063 * @arg SBS_EXTI_PIN_PORTE Port E pin input of EXTI event detection
1064 * @arg SBS_EXTI_PIN_PORTF Port F pin input of EXTI event detection
1065 * @arg SBS_EXTI_PIN_PORTG Port G pin input of EXTI event detection
1066 * @arg SBS_EXTI_PIN_PORTH Port H pin input of EXTI event detection
1067 * @arg SBS_EXTI_PIN_PORTM Port M pin input of EXTI event detection
1068 * @arg SBS_EXTI_PIN_PORTN Port N pin input of EXTI event detection
1069 * @arg SBS_EXTI_PIN_PORTO Port O pin input of EXTI event detection
1070 * @arg SBS_EXTI_PIN_PORTP Port P pin input of EXTI event detection
1071 */
HAL_SBS_GetEXTIConfig(uint32_t Exti)1072 uint32_t HAL_SBS_GetEXTIConfig(uint32_t Exti)
1073 {
1074 uint32_t reg;
1075 uint32_t offset;
1076
1077 /* Check the parameters */
1078 assert_param(IS_SBS_EXTI_INPUT(Exti));
1079
1080 reg = (Exti / 4U);
1081 offset = (4U * (Exti % 4U));
1082
1083 return ((SBS->EXTICR[reg] & (0xFUL << offset)) >> offset);
1084 }
1085 /**
1086 * @}
1087 */
1088
1089 /** @defgroup HAL_Exported_Functions_Group5 VREFBUF Control functions
1090 * @brief HAL Control functions
1091 *
1092 @verbatim
1093 ===============================================================================
1094 ##### HAL Control functions #####
1095 ===============================================================================
1096 [..] This section provides functions allowing to:
1097 (+) Configure the internal voltage reference buffer voltage scale
1098 (+) Configure the internal voltage reference buffer high impedance mode
1099 (+) Tune the Internal Voltage Reference buffer
1100 (+) Enable the Internal Voltage Reference buffer
1101 (+) Disable the Internal Voltage Reference buffer
1102
1103 @endverbatim
1104 * @{
1105 */
1106
1107 /**
1108 * @brief Configure the internal voltage reference buffer voltage scale.
1109 * @param VoltageScaling specifies the output voltage to achieve
1110 * This parameter can be one of the following values:
1111 * @arg VREFBUF_VOLTAGE_SCALE0: VREF_OUT1 around 2.5 V.
1112 * This requires VDDA equal to or higher than 2.8 V.
1113 * @arg VREFBUF_VOLTAGE_SCALE1: VREF_OUT2 around 2.048 V.
1114 * This requires VDDA equal to or higher than 2.4 V.
1115 * @arg VREFBUF_VOLTAGE_SCALE2: VREF_OUT3 around 1.8 V.
1116 * This requires VDDA equal to or higher than 2.1 V.
1117 * @arg VREFBUF_VOLTAGE_SCALE3: VREF_OUT4 around 1.5 V.
1118 * This requires VDDA equal to or higher than 1.8 V.
1119 * @retval None
1120 */
HAL_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling)1121 void HAL_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling)
1122 {
1123 /* Check the parameters */
1124 assert_param(IS_VREFBUF_VOLTAGE_SCALE(VoltageScaling));
1125
1126 MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_VRS, VoltageScaling);
1127 }
1128
1129 /**
1130 * @brief Configure the internal voltage reference buffer high impedance mode.
1131 * @param Mode specifies the high impedance mode
1132 * This parameter can be one of the following values:
1133 * @arg VREFBUF_HIGH_IMPEDANCE_DISABLE: VREF+ pin is internally connect to VREFINT output.
1134 * @arg VREFBUF_HIGH_IMPEDANCE_ENABLE: VREF+ pin is high impedance.
1135 * @retval None
1136 */
HAL_VREFBUF_HighImpedanceConfig(uint32_t Mode)1137 void HAL_VREFBUF_HighImpedanceConfig(uint32_t Mode)
1138 {
1139 /* Check the parameters */
1140 assert_param(IS_VREFBUF_HIGH_IMPEDANCE(Mode));
1141
1142 MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_HIZ, Mode);
1143 }
1144
1145 /**
1146 * @brief Tune the Internal Voltage Reference buffer (VREFBUF).
1147 * @retval None
1148 */
HAL_VREFBUF_TrimmingConfig(uint32_t TrimmingValue)1149 void HAL_VREFBUF_TrimmingConfig(uint32_t TrimmingValue)
1150 {
1151 /* Check the parameters */
1152 assert_param(IS_VREFBUF_TRIMMING(TrimmingValue));
1153
1154 MODIFY_REG(VREFBUF->CCR, VREFBUF_CCR_TRIM, TrimmingValue);
1155 }
1156
1157 /**
1158 * @brief Enable the Internal Voltage Reference buffer (VREFBUF).
1159 * @retval HAL_OK/HAL_TIMEOUT
1160 */
HAL_VREFBUF_Enable(void)1161 HAL_StatusTypeDef HAL_VREFBUF_Enable(void)
1162 {
1163 uint32_t tickstart;
1164
1165 SET_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR);
1166
1167 /* Get Start Tick*/
1168 tickstart = HAL_GetTick();
1169
1170 /* Wait for VRR bit */
1171 while (READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRR) == 0UL)
1172 {
1173 if ((HAL_GetTick() - tickstart) > VREFBUF_TIMEOUT_VALUE)
1174 {
1175 return HAL_TIMEOUT;
1176 }
1177 }
1178
1179 return HAL_OK;
1180 }
1181
1182 /**
1183 * @brief Disable the Internal Voltage Reference buffer (VREFBUF).
1184 *
1185 * @retval None
1186 */
HAL_VREFBUF_Disable(void)1187 void HAL_VREFBUF_Disable(void)
1188 {
1189 CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR);
1190 }
1191 /**
1192 * @}
1193 */
1194
1195 /** @defgroup HAL_Exported_Functions_Group6 HAL AXIM configuration functions
1196 * @brief HAL AXI Interconnect Matrix (AXIM) configuration functions
1197 *
1198 @verbatim
1199 ===============================================================================
1200 ##### HAL AXIM configuration functions #####
1201 ===============================================================================
1202 [..] This section provides functions allowing to:
1203 (+) Configures ASIB (AMBA slave interface blocks) and AMIB (AMBA master interface blocks) parameters,
1204 such as the QoS (quality of service) level.
1205 @endverbatim
1206 * @{
1207 */
1208
1209 /**
1210 * @brief Enable packing for ASIB.
1211 * @note Normal operation, Enable packing of beats to match the output data width.
1212 * @param AsibInstance specifies the ASIB to configure
1213 * This parameter can be one of the following values:
1214 * @arg AXIM_ASIB_1 : ASIB 1 connected to AHB master
1215 * @arg AXIM_ASIB_2 : ASIB 2 connected to SDMMC1 master
1216 * @retval None
1217 */
HAL_AXIM_ASIB_EnablePacking(AXIM_ASIB_TypeDef * AsibInstance)1218 void HAL_AXIM_ASIB_EnablePacking(AXIM_ASIB_TypeDef *AsibInstance)
1219 {
1220 /* Check the parameters */
1221 assert_param(IS_AXIM_ASIB_ALL_INSTANCE(AsibInstance));
1222
1223 /* Apply packing configuration for the selected ASIB */
1224 WRITE_REG(AsibInstance->FNMOD2, 0U);
1225 }
1226
1227 /**
1228 * @brief Disable packing for ASIB.
1229 * @note Network does not perform any packing of beats to match the output data width.
1230 * @note Unaligned transactions are not realigned to the input data word boundary.
1231 * @param AsibInstance specifies the ASIB to configure
1232 * This parameter can be one of the following values:
1233 * @arg AXIM_ASIB_1 : ASIB 1 connected to AHB master
1234 * @arg AXIM_ASIB_2 : ASIB 2 connected to SDMMC1 master
1235 * @retval None
1236 */
HAL_AXIM_ASIB_DisablePacking(AXIM_ASIB_TypeDef * AsibInstance)1237 void HAL_AXIM_ASIB_DisablePacking(AXIM_ASIB_TypeDef *AsibInstance)
1238 {
1239 /* Check the parameters */
1240 assert_param(IS_AXIM_ASIB_ALL_INSTANCE(AsibInstance));
1241
1242 /* Apply packing configuration for the selected ASIB */
1243 WRITE_REG(AsibInstance->FNMOD2, AXIM_ASIB_FNMOD2_BYPASS_MERGE);
1244 }
1245
1246 /**
1247 * @brief Configure ASIB read/write issuing capability.
1248 * @param AsibInstance specifies the ASIB to configure
1249 * This parameter can be one of the following values:
1250 * @arg AXIM_ASIB_1 : ASIB 1 connected to AHB master
1251 * @arg AXIM_ASIB_2 : ASIB 2 connected to SDMMC1 master
1252 * @arg AXIM_ASIB_3 : ASIB 3 connected to HPDMA master
1253 * @arg AXIM_ASIB_4 : ASIB 4 connected to C-M7 master
1254 * @arg AXIM_ASIB_5 : ASIB 5 connected to GPU master
1255 * @arg AXIM_ASIB_6 : ASIB 6 connected to GPU master
1256 * @arg AXIM_ASIB_7 : ASIB 7 connected to GPU master
1257 * @arg AXIM_ASIB_8 : ASIB 8 connected to DCMIPP master
1258 * @arg AXIM_ASIB_9 : ASIB 9 connected to GFXMMU master
1259 * @arg AXIM_ASIB_10 : ASIB 10 connected to LTDC master
1260 * @arg AXIM_ASIB_11 : ASIB 11 connected to DMA2D master
1261 * @param ReadIssuing specifies the Read issuing capability to configure
1262 * This parameter can be one of the following values:
1263 * @arg AXIM_ASIB_READ_ISS_NORMAL : Normal issuing capability, default value.
1264 * @arg AXIM_ASIB_READ_ISS_FORCE_TO_1: Force issuing capability to 1.
1265 * @param WriteIssuing specifies the write issuing capability to configure
1266 * This parameter can be one of the following values:
1267 * @arg AXIM_ASIB_WRITE_ISS_NORMAL : Normal issuing capability, default value.
1268 * @arg AXIM_ASIB_WRITE_ISS_FORCE_TO_1: Force issuing capability to 1.
1269 * @retval None
1270 */
HAL_AXIM_ASIB_IssuingConfig(AXIM_ASIB_TypeDef * AsibInstance,uint32_t ReadIssuing,uint32_t WriteIssuing)1271 void HAL_AXIM_ASIB_IssuingConfig(AXIM_ASIB_TypeDef *AsibInstance, uint32_t ReadIssuing, uint32_t WriteIssuing)
1272 {
1273 /* Check the parameters */
1274 assert_param(IS_AXIM_ASIB_ALL_INSTANCE(AsibInstance));
1275 assert_param(IS_AXIM_ASIB_READ_ISS(ReadIssuing));
1276 assert_param(IS_AXIM_ASIB_WRITE_ISS(WriteIssuing));
1277
1278 /* Apply read/write issuing configuration for the selected ASIB */
1279 WRITE_REG(AsibInstance->FNMOD, (ReadIssuing | WriteIssuing));
1280 }
1281
1282 /**
1283 * @brief Configure ASIB read QOS priority.
1284 * @param AsibInstance specifies the ASIB to configure
1285 * This parameter can be one of the following values:
1286 * @arg AXIM_ASIB_1 : ASIB 1 connected to AHB master
1287 * @arg AXIM_ASIB_2 : ASIB 2 connected to SDMMC1 master
1288 * @arg AXIM_ASIB_3 : ASIB 3 connected to HPDMA master
1289 * @arg AXIM_ASIB_4 : ASIB 4 connected to C-M7 master
1290 * @arg AXIM_ASIB_5 : ASIB 5 connected to GPU master
1291 * @arg AXIM_ASIB_6 : ASIB 6 connected to GPU master
1292 * @arg AXIM_ASIB_7 : ASIB 7 connected to GPU master
1293 * @arg AXIM_ASIB_8 : ASIB 8 connected to DCMIPP master
1294 * @arg AXIM_ASIB_9 : ASIB 9 connected to GFXMMU master
1295 * @arg AXIM_ASIB_10 : ASIB 10 connected to LTDC master
1296 * @arg AXIM_ASIB_11 : ASIB 11 connected to DMA2D master
1297 * @param QosPriority specifies read channel QoS setting
1298 * This parameter can be a value between 0 to 15.
1299 * With 0 value (default value) for the lowest priority and 15 value for Highest priority.
1300 * @retval None
1301 */
HAL_AXIM_ASIB_ReadQoSConfig(AXIM_ASIB_TypeDef * AsibInstance,uint32_t QosPriority)1302 void HAL_AXIM_ASIB_ReadQoSConfig(AXIM_ASIB_TypeDef *AsibInstance, uint32_t QosPriority)
1303 {
1304 /* Check the parameters */
1305 assert_param(IS_AXIM_ASIB_ALL_INSTANCE(AsibInstance));
1306 assert_param(IS_AXIM_QOS(QosPriority));
1307
1308 /* Apply read QOS priority setting for the selected ASIB */
1309 WRITE_REG(AsibInstance->READQOS, QosPriority);
1310 }
1311
1312 /**
1313 * @brief Configure ASIB write QOS priority.
1314 * @param AsibInstance specifies the ASIB to configure
1315 * This parameter can be one of the following values:
1316 * @arg AXIM_ASIB_1 : ASIB 1 connected to AHB master
1317 * @arg AXIM_ASIB_2 : ASIB 2 connected to SDMMC1 master
1318 * @arg AXIM_ASIB_3 : ASIB 3 connected to HPDMA master
1319 * @arg AXIM_ASIB_4 : ASIB 4 connected to C-M7 master
1320 * @arg AXIM_ASIB_5 : ASIB 5 connected to GPU master
1321 * @arg AXIM_ASIB_6 : ASIB 6 connected to GPU master
1322 * @arg AXIM_ASIB_7 : ASIB 7 connected to GPU master
1323 * @arg AXIM_ASIB_8 : ASIB 8 connected to DCMIPP master
1324 * @arg AXIM_ASIB_9 : ASIB 9 connected to GFXMMU master
1325 * @arg AXIM_ASIB_10 : ASIB 10 connected to LTDC master
1326 * @arg AXIM_ASIB_11 : ASIB 11 connected to DMA2D master
1327 * @param QosPriority specifies write channel QoS setting
1328 * This parameter can be a value between 0 to 15.
1329 * With 0 value (default value) for the lowest priority and 15 value for highest priority.
1330 *
1331 * @retval None
1332 */
HAL_AXIM_ASIB_WriteQoSConfig(AXIM_ASIB_TypeDef * AsibInstance,uint32_t QosPriority)1333 void HAL_AXIM_ASIB_WriteQoSConfig(AXIM_ASIB_TypeDef *AsibInstance, uint32_t QosPriority)
1334 {
1335 /* Check the parameters */
1336 assert_param(IS_AXIM_ASIB_ALL_INSTANCE(AsibInstance));
1337 assert_param(IS_AXIM_QOS(QosPriority));
1338
1339 /* Apply write QOS priority setting for the selected ASIB */
1340 WRITE_REG(AsibInstance->WRITEQOS, QosPriority);
1341 }
1342
1343 /**
1344 * @brief Enable Packing for AMIB.
1345 * @note Normal operation, Enable packing of beats to match the output data width.
1346 * @param AmibInstance specifies the AMIB to configure
1347 * This parameter can be one of the following values:
1348 * @arg AXIM_AMIB_2 : AMIB 2 connected to AHB Sram slave
1349 * @retval None
1350 */
HAL_AXIM_AMIB_EnablePacking(AXIM_AMIB_TypeDef * AmibInstance)1351 void HAL_AXIM_AMIB_EnablePacking(AXIM_AMIB_TypeDef *AmibInstance)
1352 {
1353 /* Check the parameters */
1354 assert_param(IS_AXIM_AMIB_ALL_INSTANCE(AmibInstance));
1355
1356 /* Apply packing configuration for the selected AMIB */
1357 WRITE_REG(AmibInstance->FNMOD2, 0U);
1358 }
1359
1360 /**
1361 * @brief Disable Packing for AMIB.
1362 * @note Network does not perform any packing of beats to match the output data width.
1363 * @note Unaligned transactions are not realigned to the input data word boundary.
1364 * @param AmibInstance specifies the AMIB to configure
1365 * This parameter can be one of the following values:
1366 * @arg AXIM_AMIB_2 : AMIB 2 connected to AHB Sram slave
1367 * @retval None
1368 */
HAL_AXIM_AMIB_DisablePacking(AXIM_AMIB_TypeDef * AmibInstance)1369 void HAL_AXIM_AMIB_DisablePacking(AXIM_AMIB_TypeDef *AmibInstance)
1370 {
1371 /* Check the parameters */
1372 assert_param(IS_AXIM_AMIB_ALL_INSTANCE(AmibInstance));
1373
1374 /* Apply packing configuration for the selected AMIB */
1375 WRITE_REG(AmibInstance->FNMOD2, AXIM_AMIB_FNMOD2_BYPASS_MERGE);
1376 }
1377
1378 /**
1379 * @brief Configure AMIB read/write issuing capability.
1380 * @param AmibInstance specifies the AMIB to configure
1381 * This parameter can be one of the following values:
1382 * @arg AXIM_AMIB_1 : AMIB 1 connected to GFXMMU slave
1383 * @arg AXIM_AMIB_2 : AMIB 2 connected to AHB Sram slave
1384 * @arg AXIM_AMIB_3 : AMIB 3 connected to FMC slave
1385 * @arg AXIM_AMIB_4 : AMIB 4 connected to XSPI1 slave
1386 * @arg AXIM_AMIB_5 : AMIB 5 connected to XSPI2 slave
1387 * @arg AXIM_AMIB_6 : AMIB 6 connected to AXI SRAM4 slave
1388 * @arg AXIM_AMIB_7 : AMIB 7 connected to AXI SRAM3 slave
1389 * @arg AXIM_AMIB_8 : AMIB 8 connected to AXI SRAM2 slave
1390 * @arg AXIM_AMIB_9 : AMIB 9 connected to AXI SRAM1 slave
1391 * @arg AXIM_AMIB_10 : AMIB 10 connected to FLASH slave
1392 * @param ReadIssuing specifies the Read issuing capability to configure
1393 * This parameter can be one of the following values:
1394 * @arg AXIM_AMIB_READ_ISS_NORMAL : Normal issuing capability, default value.
1395 * @arg AXIM_AMIB_READ_ISS_FORCE_TO_1: Force issuing capability to 1.
1396 * @param WriteIssuing specifies the write issuing capability to configure
1397 * This parameter can be one of the following values:
1398 * @arg AXIM_AMIB_WRITE_ISS_NORMAL : Normal issuing capability, default value.
1399 * @arg AXIM_AMIB_WRITE_ISS_FORCE_TO_1: Force issuing capability to 1.
1400 * @retval None
1401 */
HAL_AXIM_AMIB_IssuingConfig(AXIM_AMIB_TypeDef * AmibInstance,uint32_t ReadIssuing,uint32_t WriteIssuing)1402 void HAL_AXIM_AMIB_IssuingConfig(AXIM_AMIB_TypeDef *AmibInstance, uint32_t ReadIssuing, uint32_t WriteIssuing)
1403 {
1404 /* Check the parameters */
1405 assert_param(IS_AXIM_AMIB_ALL_INSTANCE(AmibInstance));
1406 assert_param(IS_AXIM_AMIB_READ_ISS(ReadIssuing));
1407 assert_param(IS_AXIM_AMIB_WRITE_ISS(WriteIssuing));
1408
1409 /* Apply read/write issuing configuration for the selected AMIB */
1410 WRITE_REG(AmibInstance->FNMOD, (ReadIssuing | WriteIssuing));
1411 }
1412
1413 /**
1414 * @brief Configure AMIB read/write issuing bus matrix capability.
1415 * @param AmibInstance specifies the AMIB to configure
1416 * This parameter can be one of the following values:
1417 * @arg AXIM_AMIB_1 : AMIB 1 connected to GFXMMU slave
1418 * @arg AXIM_AMIB_2 : AMIB 2 connected to AHB Sram slave
1419 * @arg AXIM_AMIB_3 : AMIB 3 connected to FMC slave
1420 * @arg AXIM_AMIB_4 : AMIB 4 connected to XSPI1 slave
1421 * @arg AXIM_AMIB_5 : AMIB 5 connected to XSPI2 slave
1422 * @arg AXIM_AMIB_6 : AMIB 6 connected to AXI SRAM4 slave
1423 * @arg AXIM_AMIB_7 : AMIB 7 connected to AXI SRAM3 slave
1424 * @arg AXIM_AMIB_8 : AMIB 8 connected to AXI SRAM2 slave
1425 * @arg AXIM_AMIB_9 : AMIB 9 connected to AXI SRAM1 slave
1426 * @arg AXIM_AMIB_10 : AMIB 10 connected to FLASH slave
1427 * @param ReadIssuing specifies the Read issuing capability to configure
1428 * This parameter can be one of the following values:
1429 * @arg AXIM_AMIB_READ_ISS_NORMAL : Normal issuing capability, default value.
1430 * @arg AXIM_AMIB_READ_ISS_FORCE_TO_1: Force issuing capability to 1.
1431 * @param WriteIssuing specifies the write issuing capability to configure
1432 * This parameter can be one of the following values:
1433 * @arg AXIM_AMIB_WRITE_ISS_NORMAL : Normal issuing capability, default value.
1434 * @arg AXIM_AMIB_WRITE_ISS_FORCE_TO_1: Force issuing capability to 1.
1435 * @retval None
1436 */
HAL_AXIM_AMIB_IssuingConfigBusMatrix(AXIM_AMIB_TypeDef * AmibInstance,uint32_t ReadIssuing,uint32_t WriteIssuing)1437 void HAL_AXIM_AMIB_IssuingConfigBusMatrix(AXIM_AMIB_TypeDef *AmibInstance, uint32_t ReadIssuing, uint32_t WriteIssuing)
1438 {
1439 /* Check the parameters */
1440 assert_param(IS_AXIM_AMIB_ALL_INSTANCE(AmibInstance));
1441 assert_param(IS_AXIM_AMIB_READ_ISS_BM(ReadIssuing));
1442 assert_param(IS_AXIM_AMIB_WRITE_ISS_BM(WriteIssuing));
1443
1444 /* Apply read/write issuing configuration for the selected AMIB */
1445 WRITE_REG(AmibInstance->FNMODBMISS, (ReadIssuing | WriteIssuing));
1446 }
1447
1448 /**
1449 * @brief Enable Long burst for AMIB.
1450 * @note Long bursts can be generated at the output of the AMIB.
1451 * @param AmibInstance specifies the AMIB to configure
1452 * This parameter can be one of the following values:
1453 * @arg AXIM_AMIB_2 : AMIB 2 connected to AHB Sram slave
1454 * @retval None
1455 */
HAL_AXIM_AMIB_EnableLongBurst(AXIM_AMIB_TypeDef * AmibInstance)1456 void HAL_AXIM_AMIB_EnableLongBurst(AXIM_AMIB_TypeDef *AmibInstance)
1457 {
1458 /* Check the parameters */
1459 assert_param(IS_AXIM_AMIB_ALL_INSTANCE(AmibInstance));
1460
1461 /* Apply Long burst configuration for the selected AMIB */
1462 WRITE_REG(AmibInstance->FNMODLB, AXIM_AMIB_FNMODLB_LONG_BURST);
1463 }
1464
1465 /**
1466 * @brief Disable Long burst for AMIB.
1467 * @note Long bursts can not be generated at the output of the AMIB.
1468 * @param AmibInstance specifies the AMIB to configure
1469 * This parameter can be one of the following values:
1470 * @arg AXIM_AMIB_2 : AMIB 2 connected to AHB Sram slave
1471 * @retval None
1472 */
HAL_AXIM_AMIB_DisableLongBurst(AXIM_AMIB_TypeDef * AmibInstance)1473 void HAL_AXIM_AMIB_DisableLongBurst(AXIM_AMIB_TypeDef *AmibInstance)
1474 {
1475 /* Check the parameters */
1476 assert_param(IS_AXIM_AMIB_ALL_INSTANCE(AmibInstance));
1477
1478 /* Apply Long burst configuration for the selected AMIB */
1479 WRITE_REG(AmibInstance->FNMODLB, 0U);
1480 }
1481 /**
1482 * @}
1483 */
1484
1485 /**
1486 * @}
1487 */
1488
1489 #endif /* HAL_MODULE_ENABLED */
1490
1491 /**
1492 * @}
1493 */
1494
1495 /**
1496 * @}
1497 */
1498
