1 /**
2 ******************************************************************************
3 * @file stm32mp1xx_ll_spi.h
4 * @author MCD Application Team
5 * @brief Header file of SPI LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2019 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32MP1xx_LL_SPI_H
21 #define STM32MP1xx_LL_SPI_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32mp1xx.h"
29
30 /** @addtogroup STM32MP1xx_LL_Driver
31 * @{
32 */
33
34 #if defined(SPI1) || defined(SPI2) || defined(SPI3) || defined(SPI4) || defined(SPI5) || defined(SPI6)
35
36 /** @defgroup SPI_LL SPI
37 * @{
38 */
39
40 /* Private variables ---------------------------------------------------------*/
41
42 /* Private constants ---------------------------------------------------------*/
43
44 /* Private macros ------------------------------------------------------------*/
45 /** @defgroup SPI_LL_Private_Macros SPI Private Macros
46 * @{
47 */
48 /**
49 * @}
50 */
51
52 /* Exported types ------------------------------------------------------------*/
53 #if defined(USE_FULL_LL_DRIVER)
54 /** @defgroup SPI_LL_Exported_Types SPI Exported Types
55 * @{
56 */
57
58 /**
59 * @brief SPI Init structures definition
60 */
61 typedef struct
62 {
63 uint32_t TransferDirection; /*!< Specifies the SPI unidirectional or bidirectional data mode.
64 This parameter can be a value of @ref SPI_LL_EC_TRANSFER_MODE.
65
66 This feature can be modified afterwards using unitary function
67 @ref LL_SPI_SetTransferDirection().*/
68
69 uint32_t Mode; /*!< Specifies the SPI mode (Master/Slave).
70 This parameter can be a value of @ref SPI_LL_EC_MODE.
71
72 This feature can be modified afterwards using unitary function
73 @ref LL_SPI_SetMode().*/
74
75 uint32_t DataWidth; /*!< Specifies the SPI data width.
76 This parameter can be a value of @ref SPI_LL_EC_DATAWIDTH.
77
78 This feature can be modified afterwards using unitary function
79 @ref LL_SPI_SetDataWidth().*/
80
81 uint32_t ClockPolarity; /*!< Specifies the serial clock steady state.
82 This parameter can be a value of @ref SPI_LL_EC_POLARITY.
83
84 This feature can be modified afterwards using unitary function
85 @ref LL_SPI_SetClockPolarity().*/
86
87 uint32_t ClockPhase; /*!< Specifies the clock active edge for the bit capture.
88 This parameter can be a value of @ref SPI_LL_EC_PHASE.
89
90 This feature can be modified afterwards using unitary function
91 @ref LL_SPI_SetClockPhase().*/
92
93 uint32_t NSS; /*!< Specifies whether the NSS signal is managed by hardware (NSS pin)
94 or by software using the SSI bit.
95
96 This parameter can be a value of @ref SPI_LL_EC_NSS_MODE.
97
98 This feature can be modified afterwards using unitary function
99 @ref LL_SPI_SetNSSMode().*/
100
101 uint32_t BaudRate; /*!< Specifies the BaudRate prescaler value which will be used to configure
102 the transmit and receive SCK clock.
103 This parameter can be a value of @ref SPI_LL_EC_BAUDRATEPRESCALER.
104 @note The communication clock is derived from the master clock.
105 The slave clock does not need to be set.
106
107 This feature can be modified afterwards using unitary function
108 @ref LL_SPI_SetBaudRatePrescaler().*/
109
110 uint32_t BitOrder; /*!< Specifies whether data transfers start from MSB or LSB bit.
111 This parameter can be a value of @ref SPI_LL_EC_BIT_ORDER.
112
113 This feature can be modified afterwards using unitary function
114 @ref LL_SPI_SetTransferBitOrder().*/
115
116 uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not.
117 This parameter can be a value of @ref SPI_LL_EC_CRC_CALCULATION.
118
119 This feature can be modified afterwards using unitary functions
120 @ref LL_SPI_EnableCRC() and @ref LL_SPI_DisableCRC().*/
121
122 uint32_t CRCPoly; /*!< Specifies the polynomial used for the CRC calculation.
123 This parameter must be a number between Min_Data = 0x00
124 and Max_Data = 0xFFFFFFFF.
125
126 This feature can be modified afterwards using unitary function
127 @ref LL_SPI_SetCRCPolynomial().*/
128
129 } LL_SPI_InitTypeDef;
130
131 /**
132 * @}
133 */
134 #endif /*USE_FULL_LL_DRIVER*/
135
136 /* Exported types ------------------------------------------------------------*/
137
138 /* Exported constants --------------------------------------------------------*/
139 /** @defgroup SPI_LL_Exported_Constants SPI Exported Constants
140 * @{
141 */
142
143 /** @defgroup SPI_LL_EC_GET_FLAG Get Flags Defines
144 * @brief Flags defines which can be used with LL_SPI_ReadReg function
145 * @{
146 */
147 #define LL_SPI_SR_RXP (SPI_SR_RXP)
148 #define LL_SPI_SR_TXP (SPI_SR_TXP)
149 #define LL_SPI_SR_DXP (SPI_SR_DXP)
150 #define LL_SPI_SR_EOT (SPI_SR_EOT)
151 #define LL_SPI_SR_TXTF (SPI_SR_TXTF)
152 #define LL_SPI_SR_UDR (SPI_SR_UDR)
153 #define LL_SPI_SR_CRCE (SPI_SR_CRCE)
154 #define LL_SPI_SR_MODF (SPI_SR_MODF)
155 #define LL_SPI_SR_OVR (SPI_SR_OVR)
156 #define LL_SPI_SR_TIFRE (SPI_SR_TIFRE)
157 #define LL_SPI_SR_TSERF (SPI_SR_TSERF)
158 #define LL_SPI_SR_SUSP (SPI_SR_SUSP)
159 #define LL_SPI_SR_TXC (SPI_SR_TXC)
160 #define LL_SPI_SR_RXWNE (SPI_SR_RXWNE)
161 /**
162 * @}
163 */
164
165 /** @defgroup SPI_LL_EC_IT IT Defines
166 * @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions
167 * @{
168 */
169 #define LL_SPI_IER_RXPIE (SPI_IER_RXPIE)
170 #define LL_SPI_IER_TXPIE (SPI_IER_TXPIE)
171 #define LL_SPI_IER_DXPIE (SPI_IER_DXPIE)
172 #define LL_SPI_IER_EOTIE (SPI_IER_EOTIE)
173 #define LL_SPI_IER_TXTFIE (SPI_IER_TXTFIE)
174 #define LL_SPI_IER_UDRIE (SPI_IER_UDRIE)
175 #define LL_SPI_IER_OVRIE (SPI_IER_OVRIE)
176 #define LL_SPI_IER_CRCEIE (SPI_IER_CRCEIE)
177 #define LL_SPI_IER_TIFREIE (SPI_IER_TIFREIE)
178 #define LL_SPI_IER_MODFIE (SPI_IER_MODFIE)
179 #define LL_SPI_IER_TSERFIE (SPI_IER_TSERFIE)
180 /**
181 * @}
182 */
183
184 /** @defgroup SPI_LL_EC_MODE Mode
185 * @{
186 */
187 #define LL_SPI_MODE_MASTER (SPI_CFG2_MASTER)
188 #define LL_SPI_MODE_SLAVE (0x00000000UL)
189 /**
190 * @}
191 */
192
193 /** @defgroup SPI_LL_EC_SS_LEVEL SS Level
194 * @{
195 */
196 #define LL_SPI_SS_LEVEL_HIGH (SPI_CR1_SSI)
197 #define LL_SPI_SS_LEVEL_LOW (0x00000000UL)
198 /**
199 * @}
200 */
201
202 /** @defgroup SPI_LL_EC_SS_IDLENESS SS Idleness
203 * @{
204 */
205 #define LL_SPI_SS_IDLENESS_00CYCLE (0x00000000UL)
206 #define LL_SPI_SS_IDLENESS_01CYCLE (SPI_CFG2_MSSI_0)
207 #define LL_SPI_SS_IDLENESS_02CYCLE (SPI_CFG2_MSSI_1)
208 #define LL_SPI_SS_IDLENESS_03CYCLE (SPI_CFG2_MSSI_0 | SPI_CFG2_MSSI_1)
209 #define LL_SPI_SS_IDLENESS_04CYCLE (SPI_CFG2_MSSI_2)
210 #define LL_SPI_SS_IDLENESS_05CYCLE (SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_0)
211 #define LL_SPI_SS_IDLENESS_06CYCLE (SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_1)
212 #define LL_SPI_SS_IDLENESS_07CYCLE (SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_1 | SPI_CFG2_MSSI_0)
213 #define LL_SPI_SS_IDLENESS_08CYCLE (SPI_CFG2_MSSI_3)
214 #define LL_SPI_SS_IDLENESS_09CYCLE (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_0)
215 #define LL_SPI_SS_IDLENESS_10CYCLE (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_1)
216 #define LL_SPI_SS_IDLENESS_11CYCLE (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_1 | SPI_CFG2_MSSI_0)
217 #define LL_SPI_SS_IDLENESS_12CYCLE (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_2)
218 #define LL_SPI_SS_IDLENESS_13CYCLE (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_0)
219 #define LL_SPI_SS_IDLENESS_14CYCLE (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_1)
220 #define LL_SPI_SS_IDLENESS_15CYCLE (SPI_CFG2_MSSI_3\
221 | SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_1 | SPI_CFG2_MSSI_0)
222 /**
223 * @}
224 */
225
226 /** @defgroup SPI_LL_EC_ID_IDLENESS Master Inter-Data Idleness
227 * @{
228 */
229 #define LL_SPI_ID_IDLENESS_00CYCLE (0x00000000UL)
230 #define LL_SPI_ID_IDLENESS_01CYCLE (SPI_CFG2_MIDI_0)
231 #define LL_SPI_ID_IDLENESS_02CYCLE (SPI_CFG2_MIDI_1)
232 #define LL_SPI_ID_IDLENESS_03CYCLE (SPI_CFG2_MIDI_0 | SPI_CFG2_MIDI_1)
233 #define LL_SPI_ID_IDLENESS_04CYCLE (SPI_CFG2_MIDI_2)
234 #define LL_SPI_ID_IDLENESS_05CYCLE (SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_0)
235 #define LL_SPI_ID_IDLENESS_06CYCLE (SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_1)
236 #define LL_SPI_ID_IDLENESS_07CYCLE (SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_1 | SPI_CFG2_MIDI_0)
237 #define LL_SPI_ID_IDLENESS_08CYCLE (SPI_CFG2_MIDI_3)
238 #define LL_SPI_ID_IDLENESS_09CYCLE (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_0)
239 #define LL_SPI_ID_IDLENESS_10CYCLE (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_1)
240 #define LL_SPI_ID_IDLENESS_11CYCLE (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_1 | SPI_CFG2_MIDI_0)
241 #define LL_SPI_ID_IDLENESS_12CYCLE (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_2)
242 #define LL_SPI_ID_IDLENESS_13CYCLE (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_0)
243 #define LL_SPI_ID_IDLENESS_14CYCLE (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_1)
244 #define LL_SPI_ID_IDLENESS_15CYCLE (SPI_CFG2_MIDI_3\
245 | SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_1 | SPI_CFG2_MIDI_0)
246 /**
247 * @}
248 */
249
250 /** @defgroup SPI_LL_EC_TXCRCINIT_ALL TXCRC Init All
251 * @{
252 */
253 #define LL_SPI_TXCRCINIT_ALL_ZERO_PATTERN (0x00000000UL)
254 #define LL_SPI_TXCRCINIT_ALL_ONES_PATTERN (SPI_CR1_TCRCINI)
255 /**
256 * @}
257 */
258
259 /** @defgroup SPI_LL_EC_RXCRCINIT_ALL RXCRC Init All
260 * @{
261 */
262 #define LL_SPI_RXCRCINIT_ALL_ZERO_PATTERN (0x00000000UL)
263 #define LL_SPI_RXCRCINIT_ALL_ONES_PATTERN (SPI_CR1_RCRCINI)
264 /**
265 * @}
266 */
267
268 /** @defgroup SPI_LL_EC_UDR_CONFIG_REGISTER UDR Config Register
269 * @{
270 */
271 #define LL_SPI_UDR_CONFIG_REGISTER_PATTERN (0x00000000UL)
272 #define LL_SPI_UDR_CONFIG_LAST_RECEIVED (SPI_CFG1_UDRCFG_0)
273 #define LL_SPI_UDR_CONFIG_LAST_TRANSMITTED (SPI_CFG1_UDRCFG_1)
274 /**
275 * @}
276 */
277
278 /** @defgroup SPI_LL_EC_UDR_DETECT_BEGIN_DATA UDR Detect Begin Data
279 * @{
280 */
281 #define LL_SPI_UDR_DETECT_BEGIN_DATA_FRAME (0x00000000UL)
282 #define LL_SPI_UDR_DETECT_END_DATA_FRAME (SPI_CFG1_UDRDET_0)
283 #define LL_SPI_UDR_DETECT_BEGIN_ACTIVE_NSS (SPI_CFG1_UDRDET_1)
284 /**
285 * @}
286 */
287
288 /** @defgroup SPI_LL_EC_PROTOCOL Protocol
289 * @{
290 */
291 #define LL_SPI_PROTOCOL_MOTOROLA (0x00000000UL)
292 #define LL_SPI_PROTOCOL_TI (SPI_CFG2_SP_0)
293 /**
294 * @}
295 */
296
297 /** @defgroup SPI_LL_EC_PHASE Phase
298 * @{
299 */
300 #define LL_SPI_PHASE_1EDGE (0x00000000UL)
301 #define LL_SPI_PHASE_2EDGE (SPI_CFG2_CPHA)
302 /**
303 * @}
304 */
305
306 /** @defgroup SPI_LL_EC_POLARITY Polarity
307 * @{
308 */
309 #define LL_SPI_POLARITY_LOW (0x00000000UL)
310 #define LL_SPI_POLARITY_HIGH (SPI_CFG2_CPOL)
311 /**
312 * @}
313 */
314
315 /** @defgroup SPI_LL_EC_NSS_POLARITY NSS Polarity
316 * @{
317 */
318 #define LL_SPI_NSS_POLARITY_LOW (0x00000000UL)
319 #define LL_SPI_NSS_POLARITY_HIGH (SPI_CFG2_SSIOP)
320 /**
321 * @}
322 */
323
324 /** @defgroup SPI_LL_EC_BAUDRATEPRESCALER Baud Rate Prescaler
325 * @{
326 */
327 #define LL_SPI_BAUDRATEPRESCALER_DIV2 (0x00000000UL)
328 #define LL_SPI_BAUDRATEPRESCALER_DIV4 (SPI_CFG1_MBR_0)
329 #define LL_SPI_BAUDRATEPRESCALER_DIV8 (SPI_CFG1_MBR_1)
330 #define LL_SPI_BAUDRATEPRESCALER_DIV16 (SPI_CFG1_MBR_1 | SPI_CFG1_MBR_0)
331 #define LL_SPI_BAUDRATEPRESCALER_DIV32 (SPI_CFG1_MBR_2)
332 #define LL_SPI_BAUDRATEPRESCALER_DIV64 (SPI_CFG1_MBR_2 | SPI_CFG1_MBR_0)
333 #define LL_SPI_BAUDRATEPRESCALER_DIV128 (SPI_CFG1_MBR_2 | SPI_CFG1_MBR_1)
334 #define LL_SPI_BAUDRATEPRESCALER_DIV256 (SPI_CFG1_MBR_2 | SPI_CFG1_MBR_1 | SPI_CFG1_MBR_0)
335 /**
336 * @}
337 */
338
339 /** @defgroup SPI_LL_EC_BIT_ORDER Bit Order
340 * @{
341 */
342 #define LL_SPI_LSB_FIRST (SPI_CFG2_LSBFRST)
343 #define LL_SPI_MSB_FIRST (0x00000000UL)
344 /**
345 * @}
346 */
347
348 /** @defgroup SPI_LL_EC_TRANSFER_MODE Transfer Mode
349 * @{
350 */
351 #define LL_SPI_FULL_DUPLEX (0x00000000UL)
352 #define LL_SPI_SIMPLEX_TX (SPI_CFG2_COMM_0)
353 #define LL_SPI_SIMPLEX_RX (SPI_CFG2_COMM_1)
354 #define LL_SPI_HALF_DUPLEX_RX (SPI_CFG2_COMM_0|SPI_CFG2_COMM_1)
355 #define LL_SPI_HALF_DUPLEX_TX (SPI_CFG2_COMM_0|SPI_CFG2_COMM_1|SPI_CR1_HDDIR)
356 /**
357 * @}
358 */
359
360 /** @defgroup SPI_LL_EC_DATAWIDTH Data Width
361 * @{
362 */
363 #define LL_SPI_DATAWIDTH_4BIT (SPI_CFG1_DSIZE_0 | SPI_CFG1_DSIZE_1)
364 #define LL_SPI_DATAWIDTH_5BIT (SPI_CFG1_DSIZE_2)
365 #define LL_SPI_DATAWIDTH_6BIT (SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_0)
366 #define LL_SPI_DATAWIDTH_7BIT (SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1)
367 #define LL_SPI_DATAWIDTH_8BIT (SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0)
368 #define LL_SPI_DATAWIDTH_9BIT (SPI_CFG1_DSIZE_3)
369 #define LL_SPI_DATAWIDTH_10BIT (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_0)
370 #define LL_SPI_DATAWIDTH_11BIT (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_1)
371 #define LL_SPI_DATAWIDTH_12BIT (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0)
372 #define LL_SPI_DATAWIDTH_13BIT (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2)
373 #define LL_SPI_DATAWIDTH_14BIT (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_0)
374 #define LL_SPI_DATAWIDTH_15BIT (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1)
375 #define LL_SPI_DATAWIDTH_16BIT (SPI_CFG1_DSIZE_3\
376 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0)
377 #define LL_SPI_DATAWIDTH_17BIT (SPI_CFG1_DSIZE_4)
378 #define LL_SPI_DATAWIDTH_18BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_0)
379 #define LL_SPI_DATAWIDTH_19BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_1)
380 #define LL_SPI_DATAWIDTH_20BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_0 | SPI_CFG1_DSIZE_1)
381 #define LL_SPI_DATAWIDTH_21BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_2)
382 #define LL_SPI_DATAWIDTH_22BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_0)
383 #define LL_SPI_DATAWIDTH_23BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1)
384 #define LL_SPI_DATAWIDTH_24BIT (SPI_CFG1_DSIZE_4\
385 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0)
386 #define LL_SPI_DATAWIDTH_25BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3)
387 #define LL_SPI_DATAWIDTH_26BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_0)
388 #define LL_SPI_DATAWIDTH_27BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_1)
389 #define LL_SPI_DATAWIDTH_28BIT (SPI_CFG1_DSIZE_4\
390 | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0)
391 #define LL_SPI_DATAWIDTH_29BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2)
392 #define LL_SPI_DATAWIDTH_30BIT (SPI_CFG1_DSIZE_4\
393 | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_0)
394 #define LL_SPI_DATAWIDTH_31BIT (SPI_CFG1_DSIZE_4\
395 | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1)
396 #define LL_SPI_DATAWIDTH_32BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3\
397 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0)
398 /**
399 * @}
400 */
401
402 /** @defgroup SPI_LL_EC_FIFO_TH FIFO Threshold
403 * @{
404 */
405 #define LL_SPI_FIFO_TH_01DATA (0x00000000UL)
406 #define LL_SPI_FIFO_TH_02DATA (SPI_CFG1_FTHLV_0)
407 #define LL_SPI_FIFO_TH_03DATA (SPI_CFG1_FTHLV_1)
408 #define LL_SPI_FIFO_TH_04DATA (SPI_CFG1_FTHLV_0 | SPI_CFG1_FTHLV_1)
409 #define LL_SPI_FIFO_TH_05DATA (SPI_CFG1_FTHLV_2)
410 #define LL_SPI_FIFO_TH_06DATA (SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_0)
411 #define LL_SPI_FIFO_TH_07DATA (SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_1)
412 #define LL_SPI_FIFO_TH_08DATA (SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_1 | SPI_CFG1_FTHLV_0)
413 #define LL_SPI_FIFO_TH_09DATA (SPI_CFG1_FTHLV_3)
414 #define LL_SPI_FIFO_TH_10DATA (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_0)
415 #define LL_SPI_FIFO_TH_11DATA (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_1)
416 #define LL_SPI_FIFO_TH_12DATA (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_1 | SPI_CFG1_FTHLV_0)
417 #define LL_SPI_FIFO_TH_13DATA (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_2)
418 #define LL_SPI_FIFO_TH_14DATA (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_0)
419 #define LL_SPI_FIFO_TH_15DATA (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_1)
420 #define LL_SPI_FIFO_TH_16DATA (SPI_CFG1_FTHLV_3\
421 | SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_1 | SPI_CFG1_FTHLV_0)
422 /**
423 * @}
424 */
425
426 #if defined(USE_FULL_LL_DRIVER)
427
428 /** @defgroup SPI_LL_EC_CRC_CALCULATION CRC Calculation
429 * @{
430 */
431 #define LL_SPI_CRCCALCULATION_DISABLE (0x00000000UL) /*!< CRC calculation disabled */
432 #define LL_SPI_CRCCALCULATION_ENABLE (SPI_CFG1_CRCEN) /*!< CRC calculation enabled */
433 /**
434 * @}
435 */
436 #endif /* USE_FULL_LL_DRIVER */
437
438 /** @defgroup SPI_LL_EC_CRC CRC
439 * @{
440 */
441 #define LL_SPI_CRC_4BIT (SPI_CFG1_CRCSIZE_0 | SPI_CFG1_CRCSIZE_1)
442 #define LL_SPI_CRC_5BIT (SPI_CFG1_CRCSIZE_2)
443 #define LL_SPI_CRC_6BIT (SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_0)
444 #define LL_SPI_CRC_7BIT (SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1)
445 #define LL_SPI_CRC_8BIT (SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0)
446 #define LL_SPI_CRC_9BIT (SPI_CFG1_CRCSIZE_3)
447 #define LL_SPI_CRC_10BIT (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_0)
448 #define LL_SPI_CRC_11BIT (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_1)
449 #define LL_SPI_CRC_12BIT (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0)
450 #define LL_SPI_CRC_13BIT (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2)
451 #define LL_SPI_CRC_14BIT (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_0)
452 #define LL_SPI_CRC_15BIT (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1)
453 #define LL_SPI_CRC_16BIT (SPI_CFG1_CRCSIZE_3\
454 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0)
455 #define LL_SPI_CRC_17BIT (SPI_CFG1_CRCSIZE_4)
456 #define LL_SPI_CRC_18BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_0)
457 #define LL_SPI_CRC_19BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_1)
458 #define LL_SPI_CRC_20BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_0 | SPI_CFG1_CRCSIZE_1)
459 #define LL_SPI_CRC_21BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_2)
460 #define LL_SPI_CRC_22BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_0)
461 #define LL_SPI_CRC_23BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1)
462 #define LL_SPI_CRC_24BIT (SPI_CFG1_CRCSIZE_4\
463 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0)
464 #define LL_SPI_CRC_25BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3)
465 #define LL_SPI_CRC_26BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_0)
466 #define LL_SPI_CRC_27BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_1)
467 #define LL_SPI_CRC_28BIT (SPI_CFG1_CRCSIZE_4\
468 | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0)
469 #define LL_SPI_CRC_29BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2)
470 #define LL_SPI_CRC_30BIT (SPI_CFG1_CRCSIZE_4\
471 | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_0)
472 #define LL_SPI_CRC_31BIT (SPI_CFG1_CRCSIZE_4\
473 | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1)
474 #define LL_SPI_CRC_32BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3\
475 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0)
476 /**
477 * @}
478 */
479
480 /** @defgroup SPI_LL_EC_NSS_MODE NSS Mode
481 * @{
482 */
483 #define LL_SPI_NSS_SOFT (SPI_CFG2_SSM)
484 #define LL_SPI_NSS_HARD_INPUT (0x00000000UL)
485 #define LL_SPI_NSS_HARD_OUTPUT (SPI_CFG2_SSOE)
486 /**
487 * @}
488 */
489
490 /** @defgroup SPI_LL_EC_RX_FIFO RxFIFO Packing LeVel
491 * @{
492 */
493 #define LL_SPI_RX_FIFO_0PACKET (0x00000000UL) /* 0 or multiple of 4 packet available is the RxFIFO */
494 #define LL_SPI_RX_FIFO_1PACKET (SPI_SR_RXPLVL_0)
495 #define LL_SPI_RX_FIFO_2PACKET (SPI_SR_RXPLVL_1)
496 #define LL_SPI_RX_FIFO_3PACKET (SPI_SR_RXPLVL_1 | SPI_SR_RXPLVL_0)
497 /**
498 * @}
499 */
500
501 /**
502 * @}
503 */
504
505 /* Exported macro ------------------------------------------------------------*/
506 /** @defgroup SPI_LL_Exported_Macros SPI Exported Macros
507 * @{
508 */
509
510 /** @defgroup SPI_LL_EM_WRITE_READ Common Write and read registers Macros
511 * @{
512 */
513
514 /**
515 * @brief Write a value in SPI register
516 * @param __INSTANCE__ SPI Instance
517 * @param __REG__ Register to be written
518 * @param __VALUE__ Value to be written in the register
519 * @retval None
520 */
521 #define LL_SPI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
522
523 /**
524 * @brief Read a value in SPI register
525 * @param __INSTANCE__ SPI Instance
526 * @param __REG__ Register to be read
527 * @retval Register value
528 */
529 #define LL_SPI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
530 /**
531 * @}
532 */
533
534 /**
535 * @}
536 */
537
538
539 /* Exported functions --------------------------------------------------------*/
540
541 /** @defgroup SPI_LL_Exported_Functions SPI Exported Functions
542 * @{
543 */
544
545 /** @defgroup SPI_LL_EF_Configuration Configuration
546 * @{
547 */
548
549 /**
550 * @brief Enable SPI peripheral
551 * @rmtoll CR1 SPE LL_SPI_Enable
552 * @param SPIx SPI Instance
553 * @retval None
554 */
LL_SPI_Enable(SPI_TypeDef * SPIx)555 __STATIC_INLINE void LL_SPI_Enable(SPI_TypeDef *SPIx)
556 {
557 SET_BIT(SPIx->CR1, SPI_CR1_SPE);
558 }
559
560 /**
561 * @brief Disable SPI peripheral
562 * @note When disabling the SPI, follow the procedure described in the Reference Manual.
563 * @rmtoll CR1 SPE LL_SPI_Disable
564 * @param SPIx SPI Instance
565 * @retval None
566 */
LL_SPI_Disable(SPI_TypeDef * SPIx)567 __STATIC_INLINE void LL_SPI_Disable(SPI_TypeDef *SPIx)
568 {
569 CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
570 }
571
572 /**
573 * @brief Check if SPI peripheral is enabled
574 * @rmtoll CR1 SPE LL_SPI_IsEnabled
575 * @param SPIx SPI Instance
576 * @retval State of bit (1 or 0)
577 */
LL_SPI_IsEnabled(SPI_TypeDef * SPIx)578 __STATIC_INLINE uint32_t LL_SPI_IsEnabled(SPI_TypeDef *SPIx)
579 {
580 return ((READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE)) ? 1UL : 0UL);
581 }
582
583 /**
584 * @brief Swap the MOSI and MISO pin
585 * @note This configuration can not be changed when SPI is enabled.
586 * @rmtoll CFG2 IOSWP LL_SPI_EnableIOSwap
587 * @param SPIx SPI Instance
588 * @retval None
589 */
LL_SPI_EnableIOSwap(SPI_TypeDef * SPIx)590 __STATIC_INLINE void LL_SPI_EnableIOSwap(SPI_TypeDef *SPIx)
591 {
592 SET_BIT(SPIx->CFG2, SPI_CFG2_IOSWP);
593 }
594
595 /**
596 * @brief Restore default function for MOSI and MISO pin
597 * @note This configuration can not be changed when SPI is enabled.
598 * @rmtoll CFG2 IOSWP LL_SPI_DisableIOSwap
599 * @param SPIx SPI Instance
600 * @retval None
601 */
LL_SPI_DisableIOSwap(SPI_TypeDef * SPIx)602 __STATIC_INLINE void LL_SPI_DisableIOSwap(SPI_TypeDef *SPIx)
603 {
604 CLEAR_BIT(SPIx->CFG2, SPI_CFG2_IOSWP);
605 }
606
607 /**
608 * @brief Check if MOSI and MISO pin are swapped
609 * @rmtoll CFG2 IOSWP LL_SPI_IsEnabledIOSwap
610 * @param SPIx SPI Instance
611 * @retval State of bit (1 or 0)
612 */
LL_SPI_IsEnabledIOSwap(SPI_TypeDef * SPIx)613 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIOSwap(SPI_TypeDef *SPIx)
614 {
615 return ((READ_BIT(SPIx->CFG2, SPI_CFG2_IOSWP) == (SPI_CFG2_IOSWP)) ? 1UL : 0UL);
616 }
617
618 /**
619 * @brief Enable GPIO control
620 * @note This configuration can not be changed when SPI is enabled.
621 * @rmtoll CFG2 AFCNTR LL_SPI_EnableGPIOControl
622 * @param SPIx SPI Instance
623 * @retval None
624 */
LL_SPI_EnableGPIOControl(SPI_TypeDef * SPIx)625 __STATIC_INLINE void LL_SPI_EnableGPIOControl(SPI_TypeDef *SPIx)
626 {
627 SET_BIT(SPIx->CFG2, SPI_CFG2_AFCNTR);
628 }
629
630 /**
631 * @brief Disable GPIO control
632 * @note This configuration can not be changed when SPI is enabled.
633 * @rmtoll CFG2 AFCNTR LL_SPI_DisableGPIOControl
634 * @param SPIx SPI Instance
635 * @retval None
636 */
LL_SPI_DisableGPIOControl(SPI_TypeDef * SPIx)637 __STATIC_INLINE void LL_SPI_DisableGPIOControl(SPI_TypeDef *SPIx)
638 {
639 CLEAR_BIT(SPIx->CFG2, SPI_CFG2_AFCNTR);
640 }
641
642 /**
643 * @brief Check if GPIO control is active
644 * @rmtoll CFG2 AFCNTR LL_SPI_IsEnabledGPIOControl
645 * @param SPIx SPI Instance
646 * @retval State of bit (1 or 0)
647 */
LL_SPI_IsEnabledGPIOControl(SPI_TypeDef * SPIx)648 __STATIC_INLINE uint32_t LL_SPI_IsEnabledGPIOControl(SPI_TypeDef *SPIx)
649 {
650 return ((READ_BIT(SPIx->CFG2, SPI_CFG2_AFCNTR) == (SPI_CFG2_AFCNTR)) ? 1UL : 0UL);
651 }
652
653 /**
654 * @brief Set SPI Mode to Master or Slave
655 * @note This configuration can not be changed when SPI is enabled.
656 * @rmtoll CFG2 MASTER LL_SPI_SetMode
657 * @param SPIx SPI Instance
658 * @param Mode This parameter can be one of the following values:
659 * @arg @ref LL_SPI_MODE_MASTER
660 * @arg @ref LL_SPI_MODE_SLAVE
661 * @retval None
662 */
LL_SPI_SetMode(SPI_TypeDef * SPIx,uint32_t Mode)663 __STATIC_INLINE void LL_SPI_SetMode(SPI_TypeDef *SPIx, uint32_t Mode)
664 {
665 MODIFY_REG(SPIx->CFG2, SPI_CFG2_MASTER, Mode);
666 }
667
668 /**
669 * @brief Get SPI Mode (Master or Slave)
670 * @rmtoll CFG2 MASTER LL_SPI_GetMode
671 * @param SPIx SPI Instance
672 * @retval Returned value can be one of the following values:
673 * @arg @ref LL_SPI_MODE_MASTER
674 * @arg @ref LL_SPI_MODE_SLAVE
675 */
LL_SPI_GetMode(SPI_TypeDef * SPIx)676 __STATIC_INLINE uint32_t LL_SPI_GetMode(SPI_TypeDef *SPIx)
677 {
678 return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_MASTER));
679 }
680
681 /**
682 * @brief Configure the Idleness applied by master between active edge of SS and first send data
683 * @rmtoll CFG2 MSSI LL_SPI_SetMasterSSIdleness
684 * @param SPIx SPI Instance
685 * @param MasterSSIdleness This parameter can be one of the following values:
686 * @arg @ref LL_SPI_SS_IDLENESS_00CYCLE
687 * @arg @ref LL_SPI_SS_IDLENESS_01CYCLE
688 * @arg @ref LL_SPI_SS_IDLENESS_02CYCLE
689 * @arg @ref LL_SPI_SS_IDLENESS_03CYCLE
690 * @arg @ref LL_SPI_SS_IDLENESS_04CYCLE
691 * @arg @ref LL_SPI_SS_IDLENESS_05CYCLE
692 * @arg @ref LL_SPI_SS_IDLENESS_06CYCLE
693 * @arg @ref LL_SPI_SS_IDLENESS_07CYCLE
694 * @arg @ref LL_SPI_SS_IDLENESS_08CYCLE
695 * @arg @ref LL_SPI_SS_IDLENESS_09CYCLE
696 * @arg @ref LL_SPI_SS_IDLENESS_10CYCLE
697 * @arg @ref LL_SPI_SS_IDLENESS_11CYCLE
698 * @arg @ref LL_SPI_SS_IDLENESS_12CYCLE
699 * @arg @ref LL_SPI_SS_IDLENESS_13CYCLE
700 * @arg @ref LL_SPI_SS_IDLENESS_14CYCLE
701 * @arg @ref LL_SPI_SS_IDLENESS_15CYCLE
702 * @retval None
703 */
LL_SPI_SetMasterSSIdleness(SPI_TypeDef * SPIx,uint32_t MasterSSIdleness)704 __STATIC_INLINE void LL_SPI_SetMasterSSIdleness(SPI_TypeDef *SPIx, uint32_t MasterSSIdleness)
705 {
706 MODIFY_REG(SPIx->CFG2, SPI_CFG2_MSSI, MasterSSIdleness);
707 }
708
709 /**
710 * @brief Get the configured Idleness applied by master
711 * @rmtoll CFG2 MSSI LL_SPI_GetMasterSSIdleness
712 * @param SPIx SPI Instance
713 * @retval Returned value can be one of the following values:
714 * @arg @ref LL_SPI_SS_IDLENESS_00CYCLE
715 * @arg @ref LL_SPI_SS_IDLENESS_01CYCLE
716 * @arg @ref LL_SPI_SS_IDLENESS_02CYCLE
717 * @arg @ref LL_SPI_SS_IDLENESS_03CYCLE
718 * @arg @ref LL_SPI_SS_IDLENESS_04CYCLE
719 * @arg @ref LL_SPI_SS_IDLENESS_05CYCLE
720 * @arg @ref LL_SPI_SS_IDLENESS_06CYCLE
721 * @arg @ref LL_SPI_SS_IDLENESS_07CYCLE
722 * @arg @ref LL_SPI_SS_IDLENESS_08CYCLE
723 * @arg @ref LL_SPI_SS_IDLENESS_09CYCLE
724 * @arg @ref LL_SPI_SS_IDLENESS_10CYCLE
725 * @arg @ref LL_SPI_SS_IDLENESS_11CYCLE
726 * @arg @ref LL_SPI_SS_IDLENESS_12CYCLE
727 * @arg @ref LL_SPI_SS_IDLENESS_13CYCLE
728 * @arg @ref LL_SPI_SS_IDLENESS_14CYCLE
729 * @arg @ref LL_SPI_SS_IDLENESS_15CYCLE
730 */
LL_SPI_GetMasterSSIdleness(SPI_TypeDef * SPIx)731 __STATIC_INLINE uint32_t LL_SPI_GetMasterSSIdleness(SPI_TypeDef *SPIx)
732 {
733 return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_MSSI));
734 }
735
736 /**
737 * @brief Configure the idleness applied by master between data frame
738 * @rmtoll CFG2 MIDI LL_SPI_SetInterDataIdleness
739 * @param SPIx SPI Instance
740 * @param MasterInterDataIdleness This parameter can be one of the following values:
741 * @arg @ref LL_SPI_ID_IDLENESS_00CYCLE
742 * @arg @ref LL_SPI_ID_IDLENESS_01CYCLE
743 * @arg @ref LL_SPI_ID_IDLENESS_02CYCLE
744 * @arg @ref LL_SPI_ID_IDLENESS_03CYCLE
745 * @arg @ref LL_SPI_ID_IDLENESS_04CYCLE
746 * @arg @ref LL_SPI_ID_IDLENESS_05CYCLE
747 * @arg @ref LL_SPI_ID_IDLENESS_06CYCLE
748 * @arg @ref LL_SPI_ID_IDLENESS_07CYCLE
749 * @arg @ref LL_SPI_ID_IDLENESS_08CYCLE
750 * @arg @ref LL_SPI_ID_IDLENESS_09CYCLE
751 * @arg @ref LL_SPI_ID_IDLENESS_10CYCLE
752 * @arg @ref LL_SPI_ID_IDLENESS_11CYCLE
753 * @arg @ref LL_SPI_ID_IDLENESS_12CYCLE
754 * @arg @ref LL_SPI_ID_IDLENESS_13CYCLE
755 * @arg @ref LL_SPI_ID_IDLENESS_14CYCLE
756 * @arg @ref LL_SPI_ID_IDLENESS_15CYCLE
757 * @retval None
758 */
LL_SPI_SetInterDataIdleness(SPI_TypeDef * SPIx,uint32_t MasterInterDataIdleness)759 __STATIC_INLINE void LL_SPI_SetInterDataIdleness(SPI_TypeDef *SPIx, uint32_t MasterInterDataIdleness)
760 {
761 MODIFY_REG(SPIx->CFG2, SPI_CFG2_MIDI, MasterInterDataIdleness);
762 }
763
764 /**
765 * @brief Get the configured inter data idleness
766 * @rmtoll CFG2 MIDI LL_SPI_SetInterDataIdleness
767 * @param SPIx SPI Instance
768 * @retval Returned value can be one of the following values:
769 * @arg @ref LL_SPI_ID_IDLENESS_00CYCLE
770 * @arg @ref LL_SPI_ID_IDLENESS_01CYCLE
771 * @arg @ref LL_SPI_ID_IDLENESS_02CYCLE
772 * @arg @ref LL_SPI_ID_IDLENESS_03CYCLE
773 * @arg @ref LL_SPI_ID_IDLENESS_04CYCLE
774 * @arg @ref LL_SPI_ID_IDLENESS_05CYCLE
775 * @arg @ref LL_SPI_ID_IDLENESS_06CYCLE
776 * @arg @ref LL_SPI_ID_IDLENESS_07CYCLE
777 * @arg @ref LL_SPI_ID_IDLENESS_08CYCLE
778 * @arg @ref LL_SPI_ID_IDLENESS_09CYCLE
779 * @arg @ref LL_SPI_ID_IDLENESS_10CYCLE
780 * @arg @ref LL_SPI_ID_IDLENESS_11CYCLE
781 * @arg @ref LL_SPI_ID_IDLENESS_12CYCLE
782 * @arg @ref LL_SPI_ID_IDLENESS_13CYCLE
783 * @arg @ref LL_SPI_ID_IDLENESS_14CYCLE
784 * @arg @ref LL_SPI_ID_IDLENESS_15CYCLE
785 */
LL_SPI_GetInterDataIdleness(SPI_TypeDef * SPIx)786 __STATIC_INLINE uint32_t LL_SPI_GetInterDataIdleness(SPI_TypeDef *SPIx)
787 {
788 return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_MIDI));
789 }
790
791 /**
792 * @brief Set transfer size
793 * @note Count is the number of frame to be transferred
794 * @rmtoll CR2 TSIZE LL_SPI_SetTransferSize
795 * @param SPIx SPI Instance
796 * @param Count 0..0xFFFF
797 * @retval None
798 */
LL_SPI_SetTransferSize(SPI_TypeDef * SPIx,uint32_t Count)799 __STATIC_INLINE void LL_SPI_SetTransferSize(SPI_TypeDef *SPIx, uint32_t Count)
800 {
801 MODIFY_REG(SPIx->CR2, SPI_CR2_TSIZE, Count);
802 }
803
804 /**
805 * @brief Get transfer size
806 * @note Count is the number of frame to be transferred
807 * @rmtoll CR2 TSIZE LL_SPI_GetTransferSize
808 * @param SPIx SPI Instance
809 * @retval 0..0xFFFF
810 */
LL_SPI_GetTransferSize(SPI_TypeDef * SPIx)811 __STATIC_INLINE uint32_t LL_SPI_GetTransferSize(SPI_TypeDef *SPIx)
812 {
813 return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_TSIZE));
814 }
815
816 /**
817 * @brief Set reload transfer size
818 * @note Count is the number of frame to be transferred
819 * @rmtoll CR2 TSER LL_SPI_SetReloadSize
820 * @param SPIx SPI Instance
821 * @param Count 0..0xFFFF
822 * @retval None
823 */
LL_SPI_SetReloadSize(SPI_TypeDef * SPIx,uint32_t Count)824 __STATIC_INLINE void LL_SPI_SetReloadSize(SPI_TypeDef *SPIx, uint32_t Count)
825 {
826 MODIFY_REG(SPIx->CR2, SPI_CR2_TSER, Count << SPI_CR2_TSER_Pos);
827 }
828
829 /**
830 * @brief Get reload transfer size
831 * @note Count is the number of frame to be transferred
832 * @rmtoll CR2 TSER LL_SPI_GetReloadSize
833 * @param SPIx SPI Instance
834 * @retval 0..0xFFFF
835 */
LL_SPI_GetReloadSize(SPI_TypeDef * SPIx)836 __STATIC_INLINE uint32_t LL_SPI_GetReloadSize(SPI_TypeDef *SPIx)
837 {
838 return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_TSER) >> SPI_CR2_TSER_Pos);
839 }
840
841 /**
842 * @brief Lock the AF configuration of associated IOs
843 * @note Once this bit is set, the AF configuration remains locked until a hardware reset occurs.
844 * the reset of the IOLock bit is done by hardware. for that, LL_SPI_DisableIOLock can not exist.
845 * @rmtoll CR1 IOLOCK LL_SPI_EnableIOLock
846 * @param SPIx SPI Instance
847 * @retval None
848 */
LL_SPI_EnableIOLock(SPI_TypeDef * SPIx)849 __STATIC_INLINE void LL_SPI_EnableIOLock(SPI_TypeDef *SPIx)
850 {
851 SET_BIT(SPIx->CR1, SPI_CR1_IOLOCK);
852 }
853
854 /**
855 * @brief Check if the AF configuration is locked.
856 * @rmtoll CR1 IOLOCK LL_SPI_IsEnabledIOLock
857 * @param SPIx SPI Instance
858 * @retval State of bit (1 or 0)
859 */
LL_SPI_IsEnabledIOLock(SPI_TypeDef * SPIx)860 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIOLock(SPI_TypeDef *SPIx)
861 {
862 return ((READ_BIT(SPIx->CR1, SPI_CR1_IOLOCK) == (SPI_CR1_IOLOCK)) ? 1UL : 0UL);
863 }
864
865 /**
866 * @brief Set Tx CRC Initialization Pattern
867 * @rmtoll CR1 TCRCINI LL_SPI_SetTxCRCInitPattern
868 * @param SPIx SPI Instance
869 * @param TXCRCInitAll This parameter can be one of the following values:
870 * @arg @ref LL_SPI_TXCRCINIT_ALL_ZERO_PATTERN
871 * @arg @ref LL_SPI_TXCRCINIT_ALL_ONES_PATTERN
872 * @retval None
873 */
LL_SPI_SetTxCRCInitPattern(SPI_TypeDef * SPIx,uint32_t TXCRCInitAll)874 __STATIC_INLINE void LL_SPI_SetTxCRCInitPattern(SPI_TypeDef *SPIx, uint32_t TXCRCInitAll)
875 {
876 MODIFY_REG(SPIx->CR1, SPI_CR1_RCRCINI, TXCRCInitAll);
877 }
878
879 /**
880 * @brief Get Tx CRC Initialization Pattern
881 * @rmtoll CR1 TCRCINI LL_SPI_GetTxCRCInitPattern
882 * @param SPIx SPI Instance
883 * @retval Returned value can be one of the following values:
884 * @arg @ref LL_SPI_TXCRCINIT_ALL_ZERO_PATTERN
885 * @arg @ref LL_SPI_TXCRCINIT_ALL_ONES_PATTERN
886 */
LL_SPI_GetTxCRCInitPattern(SPI_TypeDef * SPIx)887 __STATIC_INLINE uint32_t LL_SPI_GetTxCRCInitPattern(SPI_TypeDef *SPIx)
888 {
889 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_TCRCINI));
890 }
891
892 /**
893 * @brief Set Rx CRC Initialization Pattern
894 * @rmtoll CR1 RCRCINI LL_SPI_SetRxCRCInitPattern
895 * @param SPIx SPI Instance
896 * @param RXCRCInitAll This parameter can be one of the following values:
897 * @arg @ref LL_SPI_RXCRCINIT_ALL_ZERO_PATTERN
898 * @arg @ref LL_SPI_RXCRCINIT_ALL_ONES_PATTERN
899 * @retval None
900 */
LL_SPI_SetRxCRCInitPattern(SPI_TypeDef * SPIx,uint32_t RXCRCInitAll)901 __STATIC_INLINE void LL_SPI_SetRxCRCInitPattern(SPI_TypeDef *SPIx, uint32_t RXCRCInitAll)
902 {
903 MODIFY_REG(SPIx->CR1, SPI_CR1_RCRCINI, RXCRCInitAll);
904 }
905
906 /**
907 * @brief Get Rx CRC Initialization Pattern
908 * @rmtoll CR1 RCRCINI LL_SPI_GetRxCRCInitPattern
909 * @param SPIx SPI Instance
910 * @retval Returned value can be one of the following values:
911 * @arg @ref LL_SPI_RXCRCINIT_ALL_ZERO_PATTERN
912 * @arg @ref LL_SPI_RXCRCINIT_ALL_ONES_PATTERN
913 */
LL_SPI_GetRxCRCInitPattern(SPI_TypeDef * SPIx)914 __STATIC_INLINE uint32_t LL_SPI_GetRxCRCInitPattern(SPI_TypeDef *SPIx)
915 {
916 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_RCRCINI));
917 }
918
919 /**
920 * @brief Set internal SS input level ignoring what comes from PIN.
921 * @note This configuration has effect only with config LL_SPI_NSS_SOFT
922 * @rmtoll CR1 SSI LL_SPI_SetInternalSSLevel
923 * @param SPIx SPI Instance
924 * @param SSLevel This parameter can be one of the following values:
925 * @arg @ref LL_SPI_SS_LEVEL_HIGH
926 * @arg @ref LL_SPI_SS_LEVEL_LOW
927 * @retval None
928 */
LL_SPI_SetInternalSSLevel(SPI_TypeDef * SPIx,uint32_t SSLevel)929 __STATIC_INLINE void LL_SPI_SetInternalSSLevel(SPI_TypeDef *SPIx, uint32_t SSLevel)
930 {
931 MODIFY_REG(SPIx->CR1, SPI_CR1_SSI, SSLevel);
932 }
933
934 /**
935 * @brief Get internal SS input level
936 * @rmtoll CR1 SSI LL_SPI_GetInternalSSLevel
937 * @param SPIx SPI Instance
938 * @retval Returned value can be one of the following values:
939 * @arg @ref LL_SPI_SS_LEVEL_HIGH
940 * @arg @ref LL_SPI_SS_LEVEL_LOW
941 */
LL_SPI_GetInternalSSLevel(SPI_TypeDef * SPIx)942 __STATIC_INLINE uint32_t LL_SPI_GetInternalSSLevel(SPI_TypeDef *SPIx)
943 {
944 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_SSI));
945 }
946
947 /**
948 * @brief Enable CRC computation on 33/17 bits
949 * @rmtoll CR1 CRC33_17 LL_SPI_EnableFullSizeCRC
950 * @param SPIx SPI Instance
951 * @retval None
952 */
LL_SPI_EnableFullSizeCRC(SPI_TypeDef * SPIx)953 __STATIC_INLINE void LL_SPI_EnableFullSizeCRC(SPI_TypeDef *SPIx)
954 {
955 SET_BIT(SPIx->CR1, SPI_CR1_CRC33_17);
956 }
957
958 /**
959 * @brief Disable CRC computation on 33/17 bits
960 * @rmtoll CR1 CRC33_17 LL_SPI_DisableFullSizeCRC
961 * @param SPIx SPI Instance
962 * @retval None
963 */
LL_SPI_DisableFullSizeCRC(SPI_TypeDef * SPIx)964 __STATIC_INLINE void LL_SPI_DisableFullSizeCRC(SPI_TypeDef *SPIx)
965 {
966 CLEAR_BIT(SPIx->CR1, SPI_CR1_CRC33_17);
967 }
968
969 /**
970 * @brief Check if Enable CRC computation on 33/17 bits is enabled
971 * @rmtoll CR1 CRC33_17 LL_SPI_IsEnabledFullSizeCRC
972 * @param SPIx SPI Instance
973 * @retval State of bit (1 or 0)
974 */
LL_SPI_IsEnabledFullSizeCRC(SPI_TypeDef * SPIx)975 __STATIC_INLINE uint32_t LL_SPI_IsEnabledFullSizeCRC(SPI_TypeDef *SPIx)
976 {
977 return ((READ_BIT(SPIx->CR1, SPI_CR1_CRC33_17) == (SPI_CR1_CRC33_17)) ? 1UL : 0UL);
978 }
979
980 /**
981 * @brief Suspend an ongoing transfer for Master configuration
982 * @rmtoll CR1 CSUSP LL_SPI_SuspendMasterTransfer
983 * @param SPIx SPI Instance
984 * @retval None
985 */
LL_SPI_SuspendMasterTransfer(SPI_TypeDef * SPIx)986 __STATIC_INLINE void LL_SPI_SuspendMasterTransfer(SPI_TypeDef *SPIx)
987 {
988 SET_BIT(SPIx->CR1, SPI_CR1_CSUSP);
989 }
990
991 /**
992 * @brief Start effective transfer on wire for Master configuration
993 * @rmtoll CR1 CSTART LL_SPI_StartMasterTransfer
994 * @param SPIx SPI Instance
995 * @retval None
996 */
LL_SPI_StartMasterTransfer(SPI_TypeDef * SPIx)997 __STATIC_INLINE void LL_SPI_StartMasterTransfer(SPI_TypeDef *SPIx)
998 {
999 SET_BIT(SPIx->CR1, SPI_CR1_CSTART);
1000 }
1001
1002 /**
1003 * @brief Check if there is an unfinished master transfer
1004 * @rmtoll CR1 CSTART LL_SPI_IsActiveMasterTransfer
1005 * @param SPIx SPI Instance
1006 * @retval State of bit (1 or 0)
1007 */
LL_SPI_IsActiveMasterTransfer(SPI_TypeDef * SPIx)1008 __STATIC_INLINE uint32_t LL_SPI_IsActiveMasterTransfer(SPI_TypeDef *SPIx)
1009 {
1010 return ((READ_BIT(SPIx->CR1, SPI_CR1_CSTART) == (SPI_CR1_CSTART)) ? 1UL : 0UL);
1011 }
1012
1013 /**
1014 * @brief Enable Master Rx auto suspend in case of overrun
1015 * @rmtoll CR1 MASRX LL_SPI_EnableMasterRxAutoSuspend
1016 * @param SPIx SPI Instance
1017 * @retval None
1018 */
LL_SPI_EnableMasterRxAutoSuspend(SPI_TypeDef * SPIx)1019 __STATIC_INLINE void LL_SPI_EnableMasterRxAutoSuspend(SPI_TypeDef *SPIx)
1020 {
1021 SET_BIT(SPIx->CR1, SPI_CR1_MASRX);
1022 }
1023
1024 /**
1025 * @brief Disable Master Rx auto suspend in case of overrun
1026 * @rmtoll CR1 MASRX LL_SPI_DisableMasterRxAutoSuspend
1027 * @param SPIx SPI Instance
1028 * @retval None
1029 */
LL_SPI_DisableMasterRxAutoSuspend(SPI_TypeDef * SPIx)1030 __STATIC_INLINE void LL_SPI_DisableMasterRxAutoSuspend(SPI_TypeDef *SPIx)
1031 {
1032 CLEAR_BIT(SPIx->CR1, SPI_CR1_MASRX);
1033 }
1034
1035 /**
1036 * @brief Check if Master Rx auto suspend is activated
1037 * @rmtoll CR1 MASRX LL_SPI_IsEnabledMasterRxAutoSuspend
1038 * @param SPIx SPI Instance
1039 * @retval State of bit (1 or 0)
1040 */
LL_SPI_IsEnabledMasterRxAutoSuspend(SPI_TypeDef * SPIx)1041 __STATIC_INLINE uint32_t LL_SPI_IsEnabledMasterRxAutoSuspend(SPI_TypeDef *SPIx)
1042 {
1043 return ((READ_BIT(SPIx->CR1, SPI_CR1_MASRX) == (SPI_CR1_MASRX)) ? 1UL : 0UL);
1044 }
1045
1046 /**
1047 * @brief Set Underrun behavior
1048 * @note This configuration can not be changed when SPI is enabled.
1049 * @rmtoll CFG1 UDRCFG LL_SPI_SetUDRConfiguration
1050 * @param SPIx SPI Instance
1051 * @param UDRConfig This parameter can be one of the following values:
1052 * @arg @ref LL_SPI_UDR_CONFIG_REGISTER_PATTERN
1053 * @arg @ref LL_SPI_UDR_CONFIG_LAST_RECEIVED
1054 * @arg @ref LL_SPI_UDR_CONFIG_LAST_TRANSMITTED
1055 * @retval None
1056 */
LL_SPI_SetUDRConfiguration(SPI_TypeDef * SPIx,uint32_t UDRConfig)1057 __STATIC_INLINE void LL_SPI_SetUDRConfiguration(SPI_TypeDef *SPIx, uint32_t UDRConfig)
1058 {
1059 MODIFY_REG(SPIx->CFG1, SPI_CFG1_UDRCFG, UDRConfig);
1060 }
1061
1062 /**
1063 * @brief Get Underrun behavior
1064 * @rmtoll CFG1 UDRCFG LL_SPI_GetUDRConfiguration
1065 * @param SPIx SPI Instance
1066 * @retval Returned value can be one of the following values:
1067 * @arg @ref LL_SPI_UDR_CONFIG_REGISTER_PATTERN
1068 * @arg @ref LL_SPI_UDR_CONFIG_LAST_RECEIVED
1069 * @arg @ref LL_SPI_UDR_CONFIG_LAST_TRANSMITTED
1070 */
LL_SPI_GetUDRConfiguration(SPI_TypeDef * SPIx)1071 __STATIC_INLINE uint32_t LL_SPI_GetUDRConfiguration(SPI_TypeDef *SPIx)
1072 {
1073 return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_UDRCFG));
1074 }
1075
1076 /**
1077 * @brief Set Underrun Detection method
1078 * @note This configuration can not be changed when SPI is enabled.
1079 * @rmtoll CFG1 UDRDET LL_SPI_SetUDRDetection
1080 * @param SPIx SPI Instance
1081 * @param UDRDetection This parameter can be one of the following values:
1082 * @arg @ref LL_SPI_UDR_DETECT_BEGIN_DATA_FRAME
1083 * @arg @ref LL_SPI_UDR_DETECT_END_DATA_FRAME
1084 * @arg @ref LL_SPI_UDR_DETECT_BEGIN_ACTIVE_NSS
1085 * @retval None
1086 */
LL_SPI_SetUDRDetection(SPI_TypeDef * SPIx,uint32_t UDRDetection)1087 __STATIC_INLINE void LL_SPI_SetUDRDetection(SPI_TypeDef *SPIx, uint32_t UDRDetection)
1088 {
1089 MODIFY_REG(SPIx->CFG1, SPI_CFG1_UDRDET, UDRDetection);
1090 }
1091
1092 /**
1093 * @brief Get Underrun Detection method
1094 * @rmtoll CFG1 UDRDET LL_SPI_GetUDRDetection
1095 * @param SPIx SPI Instance
1096 * @retval Returned value can be one of the following values:
1097 * @arg @ref LL_SPI_UDR_DETECT_BEGIN_DATA_FRAME
1098 * @arg @ref LL_SPI_UDR_DETECT_END_DATA_FRAME
1099 * @arg @ref LL_SPI_UDR_DETECT_BEGIN_ACTIVE_NSS
1100 */
LL_SPI_GetUDRDetection(SPI_TypeDef * SPIx)1101 __STATIC_INLINE uint32_t LL_SPI_GetUDRDetection(SPI_TypeDef *SPIx)
1102 {
1103 return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_UDRDET));
1104 }
1105
1106 /**
1107 * @brief Set Serial protocol used
1108 * @note This configuration can not be changed when SPI is enabled.
1109 * @rmtoll CFG2 SP LL_SPI_SetStandard
1110 * @param SPIx SPI Instance
1111 * @param Standard This parameter can be one of the following values:
1112 * @arg @ref LL_SPI_PROTOCOL_MOTOROLA
1113 * @arg @ref LL_SPI_PROTOCOL_TI
1114 * @retval None
1115 */
LL_SPI_SetStandard(SPI_TypeDef * SPIx,uint32_t Standard)1116 __STATIC_INLINE void LL_SPI_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
1117 {
1118 MODIFY_REG(SPIx->CFG2, SPI_CFG2_SP, Standard);
1119 }
1120
1121 /**
1122 * @brief Get Serial protocol used
1123 * @rmtoll CFG2 SP LL_SPI_GetStandard
1124 * @param SPIx SPI Instance
1125 * @retval Returned value can be one of the following values:
1126 * @arg @ref LL_SPI_PROTOCOL_MOTOROLA
1127 * @arg @ref LL_SPI_PROTOCOL_TI
1128 */
LL_SPI_GetStandard(SPI_TypeDef * SPIx)1129 __STATIC_INLINE uint32_t LL_SPI_GetStandard(SPI_TypeDef *SPIx)
1130 {
1131 return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_SP));
1132 }
1133
1134 /**
1135 * @brief Set Clock phase
1136 * @note This configuration can not be changed when SPI is enabled.
1137 * This bit is not used in SPI TI mode.
1138 * @rmtoll CFG2 CPHA LL_SPI_SetClockPhase
1139 * @param SPIx SPI Instance
1140 * @param ClockPhase This parameter can be one of the following values:
1141 * @arg @ref LL_SPI_PHASE_1EDGE
1142 * @arg @ref LL_SPI_PHASE_2EDGE
1143 * @retval None
1144 */
LL_SPI_SetClockPhase(SPI_TypeDef * SPIx,uint32_t ClockPhase)1145 __STATIC_INLINE void LL_SPI_SetClockPhase(SPI_TypeDef *SPIx, uint32_t ClockPhase)
1146 {
1147 MODIFY_REG(SPIx->CFG2, SPI_CFG2_CPHA, ClockPhase);
1148 }
1149
1150 /**
1151 * @brief Get Clock phase
1152 * @rmtoll CFG2 CPHA LL_SPI_GetClockPhase
1153 * @param SPIx SPI Instance
1154 * @retval Returned value can be one of the following values:
1155 * @arg @ref LL_SPI_PHASE_1EDGE
1156 * @arg @ref LL_SPI_PHASE_2EDGE
1157 */
LL_SPI_GetClockPhase(SPI_TypeDef * SPIx)1158 __STATIC_INLINE uint32_t LL_SPI_GetClockPhase(SPI_TypeDef *SPIx)
1159 {
1160 return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_CPHA));
1161 }
1162
1163 /**
1164 * @brief Set Clock polarity
1165 * @note This configuration can not be changed when SPI is enabled.
1166 * This bit is not used in SPI TI mode.
1167 * @rmtoll CFG2 CPOL LL_SPI_SetClockPolarity
1168 * @param SPIx SPI Instance
1169 * @param ClockPolarity This parameter can be one of the following values:
1170 * @arg @ref LL_SPI_POLARITY_LOW
1171 * @arg @ref LL_SPI_POLARITY_HIGH
1172 * @retval None
1173 */
LL_SPI_SetClockPolarity(SPI_TypeDef * SPIx,uint32_t ClockPolarity)1174 __STATIC_INLINE void LL_SPI_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
1175 {
1176 MODIFY_REG(SPIx->CFG2, SPI_CFG2_CPOL, ClockPolarity);
1177 }
1178
1179 /**
1180 * @brief Get Clock polarity
1181 * @rmtoll CFG2 CPOL LL_SPI_GetClockPolarity
1182 * @param SPIx SPI Instance
1183 * @retval Returned value can be one of the following values:
1184 * @arg @ref LL_SPI_POLARITY_LOW
1185 * @arg @ref LL_SPI_POLARITY_HIGH
1186 */
LL_SPI_GetClockPolarity(SPI_TypeDef * SPIx)1187 __STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(SPI_TypeDef *SPIx)
1188 {
1189 return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_CPOL));
1190 }
1191
1192 /**
1193 * @brief Set NSS polarity
1194 * @note This configuration can not be changed when SPI is enabled.
1195 * This bit is not used in SPI TI mode.
1196 * @rmtoll CFG2 SSIOP LL_SPI_SetNSSPolarity
1197 * @param SPIx SPI Instance
1198 * @param NSSPolarity This parameter can be one of the following values:
1199 * @arg @ref LL_SPI_NSS_POLARITY_LOW
1200 * @arg @ref LL_SPI_NSS_POLARITY_HIGH
1201 * @retval None
1202 */
LL_SPI_SetNSSPolarity(SPI_TypeDef * SPIx,uint32_t NSSPolarity)1203 __STATIC_INLINE void LL_SPI_SetNSSPolarity(SPI_TypeDef *SPIx, uint32_t NSSPolarity)
1204 {
1205 MODIFY_REG(SPIx->CFG2, SPI_CFG2_SSIOP, NSSPolarity);
1206 }
1207
1208 /**
1209 * @brief Get NSS polarity
1210 * @rmtoll CFG2 SSIOP LL_SPI_GetNSSPolarity
1211 * @param SPIx SPI Instance
1212 * @retval Returned value can be one of the following values:
1213 * @arg @ref LL_SPI_NSS_POLARITY_LOW
1214 * @arg @ref LL_SPI_NSS_POLARITY_HIGH
1215 */
LL_SPI_GetNSSPolarity(SPI_TypeDef * SPIx)1216 __STATIC_INLINE uint32_t LL_SPI_GetNSSPolarity(SPI_TypeDef *SPIx)
1217 {
1218 return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_SSIOP));
1219 }
1220
1221 /**
1222 * @brief Set Baudrate Prescaler
1223 * @note This configuration can not be changed when SPI is enabled.
1224 * SPI BaudRate = fPCLK/Pescaler.
1225 * @rmtoll CFG1 MBR LL_SPI_SetBaudRatePrescaler
1226 * @param SPIx SPI Instance
1227 * @param Baudrate This parameter can be one of the following values:
1228 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
1229 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
1230 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
1231 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
1232 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
1233 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
1234 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
1235 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
1236 * @retval None
1237 */
LL_SPI_SetBaudRatePrescaler(SPI_TypeDef * SPIx,uint32_t Baudrate)1238 __STATIC_INLINE void LL_SPI_SetBaudRatePrescaler(SPI_TypeDef *SPIx, uint32_t Baudrate)
1239 {
1240 MODIFY_REG(SPIx->CFG1, SPI_CFG1_MBR, Baudrate);
1241 }
1242
1243 /**
1244 * @brief Get Baudrate Prescaler
1245 * @rmtoll CFG1 MBR LL_SPI_GetBaudRatePrescaler
1246 * @param SPIx SPI Instance
1247 * @retval Returned value can be one of the following values:
1248 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2
1249 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4
1250 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8
1251 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16
1252 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32
1253 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64
1254 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128
1255 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256
1256 */
LL_SPI_GetBaudRatePrescaler(SPI_TypeDef * SPIx)1257 __STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(SPI_TypeDef *SPIx)
1258 {
1259 return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_MBR));
1260 }
1261
1262 /**
1263 * @brief Set Transfer Bit Order
1264 * @note This configuration can not be changed when SPI is enabled.
1265 * This bit is not used in SPI TI mode.
1266 * @rmtoll CFG2 LSBFRST LL_SPI_SetTransferBitOrder
1267 * @param SPIx SPI Instance
1268 * @param BitOrder This parameter can be one of the following values:
1269 * @arg @ref LL_SPI_LSB_FIRST
1270 * @arg @ref LL_SPI_MSB_FIRST
1271 * @retval None
1272 */
LL_SPI_SetTransferBitOrder(SPI_TypeDef * SPIx,uint32_t BitOrder)1273 __STATIC_INLINE void LL_SPI_SetTransferBitOrder(SPI_TypeDef *SPIx, uint32_t BitOrder)
1274 {
1275 MODIFY_REG(SPIx->CFG2, SPI_CFG2_LSBFRST, BitOrder);
1276 }
1277
1278 /**
1279 * @brief Get Transfer Bit Order
1280 * @rmtoll CFG2 LSBFRST LL_SPI_GetTransferBitOrder
1281 * @param SPIx SPI Instance
1282 * @retval Returned value can be one of the following values:
1283 * @arg @ref LL_SPI_LSB_FIRST
1284 * @arg @ref LL_SPI_MSB_FIRST
1285 */
LL_SPI_GetTransferBitOrder(SPI_TypeDef * SPIx)1286 __STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(SPI_TypeDef *SPIx)
1287 {
1288 return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_LSBFRST));
1289 }
1290
1291 /**
1292 * @brief Set Transfer Mode
1293 * @note This configuration can not be changed when SPI is enabled except for half duplex direction
1294 * using LL_SPI_SetHalfDuplexDirection.
1295 * @rmtoll CR1 HDDIR LL_SPI_SetTransferDirection\n
1296 * CFG2 COMM LL_SPI_SetTransferDirection
1297 * @param SPIx SPI Instance
1298 * @param TransferDirection This parameter can be one of the following values:
1299 * @arg @ref LL_SPI_FULL_DUPLEX
1300 * @arg @ref LL_SPI_SIMPLEX_TX
1301 * @arg @ref LL_SPI_SIMPLEX_RX
1302 * @arg @ref LL_SPI_HALF_DUPLEX_RX
1303 * @arg @ref LL_SPI_HALF_DUPLEX_TX
1304 * @retval None
1305 */
LL_SPI_SetTransferDirection(SPI_TypeDef * SPIx,uint32_t TransferDirection)1306 __STATIC_INLINE void LL_SPI_SetTransferDirection(SPI_TypeDef *SPIx, uint32_t TransferDirection)
1307 {
1308 MODIFY_REG(SPIx->CR1, SPI_CR1_HDDIR, TransferDirection & SPI_CR1_HDDIR);
1309 MODIFY_REG(SPIx->CFG2, SPI_CFG2_COMM, TransferDirection & SPI_CFG2_COMM);
1310 }
1311
1312 /**
1313 * @brief Get Transfer Mode
1314 * @rmtoll CR1 HDDIR LL_SPI_GetTransferDirection\n
1315 * CFG2 COMM LL_SPI_GetTransferDirection
1316 * @param SPIx SPI Instance
1317 * @retval Returned value can be one of the following values:
1318 * @arg @ref LL_SPI_FULL_DUPLEX
1319 * @arg @ref LL_SPI_SIMPLEX_TX
1320 * @arg @ref LL_SPI_SIMPLEX_RX
1321 * @arg @ref LL_SPI_HALF_DUPLEX_RX
1322 * @arg @ref LL_SPI_HALF_DUPLEX_TX
1323 */
LL_SPI_GetTransferDirection(SPI_TypeDef * SPIx)1324 __STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(SPI_TypeDef *SPIx)
1325 {
1326 uint32_t Hddir = READ_BIT(SPIx->CR1, SPI_CR1_HDDIR);
1327 uint32_t Comm = READ_BIT(SPIx->CFG2, SPI_CFG2_COMM);
1328 return (Hddir | Comm);
1329 }
1330
1331 /**
1332 * @brief Set direction for Half-Duplex Mode
1333 * @note In master mode the MOSI pin is used and in slave mode the MISO pin is used for Half-Duplex.
1334 * @rmtoll CR1 HDDIR LL_SPI_SetHalfDuplexDirection
1335 * @param SPIx SPI Instance
1336 * @param HalfDuplexDirection This parameter can be one of the following values:
1337 * @arg @ref LL_SPI_HALF_DUPLEX_RX
1338 * @arg @ref LL_SPI_HALF_DUPLEX_TX
1339 * @retval None
1340 */
LL_SPI_SetHalfDuplexDirection(SPI_TypeDef * SPIx,uint32_t HalfDuplexDirection)1341 __STATIC_INLINE void LL_SPI_SetHalfDuplexDirection(SPI_TypeDef *SPIx, uint32_t HalfDuplexDirection)
1342 {
1343 MODIFY_REG(SPIx->CR1, SPI_CR1_HDDIR, HalfDuplexDirection & SPI_CR1_HDDIR);
1344 }
1345
1346 /**
1347 * @brief Get direction for Half-Duplex Mode
1348 * @note In master mode the MOSI pin is used and in slave mode the MISO pin is used for Half-Duplex.
1349 * @rmtoll CR1 HDDIR LL_SPI_GetHalfDuplexDirection
1350 * @param SPIx SPI Instance
1351 * @retval Returned value can be one of the following values:
1352 * @arg @ref LL_SPI_HALF_DUPLEX_RX
1353 * @arg @ref LL_SPI_HALF_DUPLEX_TX
1354 */
LL_SPI_GetHalfDuplexDirection(SPI_TypeDef * SPIx)1355 __STATIC_INLINE uint32_t LL_SPI_GetHalfDuplexDirection(SPI_TypeDef *SPIx)
1356 {
1357 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_HDDIR) | SPI_CFG2_COMM);
1358 }
1359
1360 /**
1361 * @brief Set Frame Data Size
1362 * @note This configuration can not be changed when SPI is enabled.
1363 * @rmtoll CFG1 DSIZE LL_SPI_SetDataWidth
1364 * @param SPIx SPI Instance
1365 * @param DataWidth This parameter can be one of the following values:
1366 * @arg @ref LL_SPI_DATAWIDTH_4BIT
1367 * @arg @ref LL_SPI_DATAWIDTH_5BIT
1368 * @arg @ref LL_SPI_DATAWIDTH_6BIT
1369 * @arg @ref LL_SPI_DATAWIDTH_7BIT
1370 * @arg @ref LL_SPI_DATAWIDTH_8BIT
1371 * @arg @ref LL_SPI_DATAWIDTH_9BIT
1372 * @arg @ref LL_SPI_DATAWIDTH_10BIT
1373 * @arg @ref LL_SPI_DATAWIDTH_11BIT
1374 * @arg @ref LL_SPI_DATAWIDTH_12BIT
1375 * @arg @ref LL_SPI_DATAWIDTH_13BIT
1376 * @arg @ref LL_SPI_DATAWIDTH_14BIT
1377 * @arg @ref LL_SPI_DATAWIDTH_15BIT
1378 * @arg @ref LL_SPI_DATAWIDTH_16BIT
1379 * @arg @ref LL_SPI_DATAWIDTH_17BIT
1380 * @arg @ref LL_SPI_DATAWIDTH_18BIT
1381 * @arg @ref LL_SPI_DATAWIDTH_19BIT
1382 * @arg @ref LL_SPI_DATAWIDTH_20BIT
1383 * @arg @ref LL_SPI_DATAWIDTH_21BIT
1384 * @arg @ref LL_SPI_DATAWIDTH_22BIT
1385 * @arg @ref LL_SPI_DATAWIDTH_23BIT
1386 * @arg @ref LL_SPI_DATAWIDTH_24BIT
1387 * @arg @ref LL_SPI_DATAWIDTH_25BIT
1388 * @arg @ref LL_SPI_DATAWIDTH_26BIT
1389 * @arg @ref LL_SPI_DATAWIDTH_27BIT
1390 * @arg @ref LL_SPI_DATAWIDTH_28BIT
1391 * @arg @ref LL_SPI_DATAWIDTH_29BIT
1392 * @arg @ref LL_SPI_DATAWIDTH_30BIT
1393 * @arg @ref LL_SPI_DATAWIDTH_31BIT
1394 * @arg @ref LL_SPI_DATAWIDTH_32BIT
1395 * @retval None
1396 */
LL_SPI_SetDataWidth(SPI_TypeDef * SPIx,uint32_t DataWidth)1397 __STATIC_INLINE void LL_SPI_SetDataWidth(SPI_TypeDef *SPIx, uint32_t DataWidth)
1398 {
1399 MODIFY_REG(SPIx->CFG1, SPI_CFG1_DSIZE, DataWidth);
1400 }
1401
1402 /**
1403 * @brief Get Frame Data Size
1404 * @rmtoll CFG1 DSIZE LL_SPI_GetDataWidth
1405 * @param SPIx SPI Instance
1406 * @retval Returned value can be one of the following values:
1407 * @arg @ref LL_SPI_DATAWIDTH_4BIT
1408 * @arg @ref LL_SPI_DATAWIDTH_5BIT
1409 * @arg @ref LL_SPI_DATAWIDTH_6BIT
1410 * @arg @ref LL_SPI_DATAWIDTH_7BIT
1411 * @arg @ref LL_SPI_DATAWIDTH_8BIT
1412 * @arg @ref LL_SPI_DATAWIDTH_9BIT
1413 * @arg @ref LL_SPI_DATAWIDTH_10BIT
1414 * @arg @ref LL_SPI_DATAWIDTH_11BIT
1415 * @arg @ref LL_SPI_DATAWIDTH_12BIT
1416 * @arg @ref LL_SPI_DATAWIDTH_13BIT
1417 * @arg @ref LL_SPI_DATAWIDTH_14BIT
1418 * @arg @ref LL_SPI_DATAWIDTH_15BIT
1419 * @arg @ref LL_SPI_DATAWIDTH_16BIT
1420 * @arg @ref LL_SPI_DATAWIDTH_17BIT
1421 * @arg @ref LL_SPI_DATAWIDTH_18BIT
1422 * @arg @ref LL_SPI_DATAWIDTH_19BIT
1423 * @arg @ref LL_SPI_DATAWIDTH_20BIT
1424 * @arg @ref LL_SPI_DATAWIDTH_21BIT
1425 * @arg @ref LL_SPI_DATAWIDTH_22BIT
1426 * @arg @ref LL_SPI_DATAWIDTH_23BIT
1427 * @arg @ref LL_SPI_DATAWIDTH_24BIT
1428 * @arg @ref LL_SPI_DATAWIDTH_25BIT
1429 * @arg @ref LL_SPI_DATAWIDTH_26BIT
1430 * @arg @ref LL_SPI_DATAWIDTH_27BIT
1431 * @arg @ref LL_SPI_DATAWIDTH_28BIT
1432 * @arg @ref LL_SPI_DATAWIDTH_29BIT
1433 * @arg @ref LL_SPI_DATAWIDTH_30BIT
1434 * @arg @ref LL_SPI_DATAWIDTH_31BIT
1435 * @arg @ref LL_SPI_DATAWIDTH_32BIT
1436 */
LL_SPI_GetDataWidth(SPI_TypeDef * SPIx)1437 __STATIC_INLINE uint32_t LL_SPI_GetDataWidth(SPI_TypeDef *SPIx)
1438 {
1439 return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_DSIZE));
1440 }
1441
1442 /**
1443 * @brief Set threshold of FIFO that triggers a transfer event
1444 * @note This configuration can not be changed when SPI is enabled.
1445 * @rmtoll CFG1 FTHLV LL_SPI_SetFIFOThreshold
1446 * @param SPIx SPI Instance
1447 * @param Threshold This parameter can be one of the following values:
1448 * @arg @ref LL_SPI_FIFO_TH_01DATA
1449 * @arg @ref LL_SPI_FIFO_TH_02DATA
1450 * @arg @ref LL_SPI_FIFO_TH_03DATA
1451 * @arg @ref LL_SPI_FIFO_TH_04DATA
1452 * @arg @ref LL_SPI_FIFO_TH_05DATA
1453 * @arg @ref LL_SPI_FIFO_TH_06DATA
1454 * @arg @ref LL_SPI_FIFO_TH_07DATA
1455 * @arg @ref LL_SPI_FIFO_TH_08DATA
1456 * @arg @ref LL_SPI_FIFO_TH_09DATA
1457 * @arg @ref LL_SPI_FIFO_TH_10DATA
1458 * @arg @ref LL_SPI_FIFO_TH_11DATA
1459 * @arg @ref LL_SPI_FIFO_TH_12DATA
1460 * @arg @ref LL_SPI_FIFO_TH_13DATA
1461 * @arg @ref LL_SPI_FIFO_TH_14DATA
1462 * @arg @ref LL_SPI_FIFO_TH_15DATA
1463 * @arg @ref LL_SPI_FIFO_TH_16DATA
1464 * @retval None
1465 */
LL_SPI_SetFIFOThreshold(SPI_TypeDef * SPIx,uint32_t Threshold)1466 __STATIC_INLINE void LL_SPI_SetFIFOThreshold(SPI_TypeDef *SPIx, uint32_t Threshold)
1467 {
1468 MODIFY_REG(SPIx->CFG1, SPI_CFG1_FTHLV, Threshold);
1469 }
1470
1471 /**
1472 * @brief Get threshold of FIFO that triggers a transfer event
1473 * @rmtoll CFG1 FTHLV LL_SPI_GetFIFOThreshold
1474 * @param SPIx SPI Instance
1475 * @retval Returned value can be one of the following values:
1476 * @arg @ref LL_SPI_FIFO_TH_01DATA
1477 * @arg @ref LL_SPI_FIFO_TH_02DATA
1478 * @arg @ref LL_SPI_FIFO_TH_03DATA
1479 * @arg @ref LL_SPI_FIFO_TH_04DATA
1480 * @arg @ref LL_SPI_FIFO_TH_05DATA
1481 * @arg @ref LL_SPI_FIFO_TH_06DATA
1482 * @arg @ref LL_SPI_FIFO_TH_07DATA
1483 * @arg @ref LL_SPI_FIFO_TH_08DATA
1484 * @arg @ref LL_SPI_FIFO_TH_09DATA
1485 * @arg @ref LL_SPI_FIFO_TH_10DATA
1486 * @arg @ref LL_SPI_FIFO_TH_11DATA
1487 * @arg @ref LL_SPI_FIFO_TH_12DATA
1488 * @arg @ref LL_SPI_FIFO_TH_13DATA
1489 * @arg @ref LL_SPI_FIFO_TH_14DATA
1490 * @arg @ref LL_SPI_FIFO_TH_15DATA
1491 * @arg @ref LL_SPI_FIFO_TH_16DATA
1492 */
LL_SPI_GetFIFOThreshold(SPI_TypeDef * SPIx)1493 __STATIC_INLINE uint32_t LL_SPI_GetFIFOThreshold(SPI_TypeDef *SPIx)
1494 {
1495 return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_FTHLV));
1496 }
1497
1498 /**
1499 * @brief Enable CRC
1500 * @note This configuration can not be changed when SPI is enabled.
1501 * @rmtoll CFG1 CRCEN LL_SPI_EnableCRC
1502 * @param SPIx SPI Instance
1503 * @retval None
1504 */
LL_SPI_EnableCRC(SPI_TypeDef * SPIx)1505 __STATIC_INLINE void LL_SPI_EnableCRC(SPI_TypeDef *SPIx)
1506 {
1507 SET_BIT(SPIx->CFG1, SPI_CFG1_CRCEN);
1508 }
1509
1510 /**
1511 * @brief Disable CRC
1512 * @rmtoll CFG1 CRCEN LL_SPI_DisableCRC
1513 * @param SPIx SPI Instance
1514 * @retval None
1515 */
LL_SPI_DisableCRC(SPI_TypeDef * SPIx)1516 __STATIC_INLINE void LL_SPI_DisableCRC(SPI_TypeDef *SPIx)
1517 {
1518 CLEAR_BIT(SPIx->CFG1, SPI_CFG1_CRCEN);
1519 }
1520
1521 /**
1522 * @brief Check if CRC is enabled
1523 * @rmtoll CFG1 CRCEN LL_SPI_IsEnabledCRC
1524 * @param SPIx SPI Instance
1525 * @retval State of bit (1 or 0).
1526 */
LL_SPI_IsEnabledCRC(SPI_TypeDef * SPIx)1527 __STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(SPI_TypeDef *SPIx)
1528 {
1529 return ((READ_BIT(SPIx->CFG1, SPI_CFG1_CRCEN) == SPI_CFG1_CRCEN) ? 1UL : 0UL);
1530 }
1531
1532 /**
1533 * @brief Set CRC Length
1534 * @note This configuration can not be changed when SPI is enabled.
1535 * @rmtoll CFG1 CRCSIZE LL_SPI_SetCRCWidth
1536 * @param SPIx SPI Instance
1537 * @param CRCLength This parameter can be one of the following values:
1538 * @arg @ref LL_SPI_CRC_4BIT
1539 * @arg @ref LL_SPI_CRC_5BIT
1540 * @arg @ref LL_SPI_CRC_6BIT
1541 * @arg @ref LL_SPI_CRC_7BIT
1542 * @arg @ref LL_SPI_CRC_8BIT
1543 * @arg @ref LL_SPI_CRC_9BIT
1544 * @arg @ref LL_SPI_CRC_10BIT
1545 * @arg @ref LL_SPI_CRC_11BIT
1546 * @arg @ref LL_SPI_CRC_12BIT
1547 * @arg @ref LL_SPI_CRC_13BIT
1548 * @arg @ref LL_SPI_CRC_14BIT
1549 * @arg @ref LL_SPI_CRC_15BIT
1550 * @arg @ref LL_SPI_CRC_16BIT
1551 * @arg @ref LL_SPI_CRC_17BIT
1552 * @arg @ref LL_SPI_CRC_18BIT
1553 * @arg @ref LL_SPI_CRC_19BIT
1554 * @arg @ref LL_SPI_CRC_20BIT
1555 * @arg @ref LL_SPI_CRC_21BIT
1556 * @arg @ref LL_SPI_CRC_22BIT
1557 * @arg @ref LL_SPI_CRC_23BIT
1558 * @arg @ref LL_SPI_CRC_24BIT
1559 * @arg @ref LL_SPI_CRC_25BIT
1560 * @arg @ref LL_SPI_CRC_26BIT
1561 * @arg @ref LL_SPI_CRC_27BIT
1562 * @arg @ref LL_SPI_CRC_28BIT
1563 * @arg @ref LL_SPI_CRC_29BIT
1564 * @arg @ref LL_SPI_CRC_30BIT
1565 * @arg @ref LL_SPI_CRC_31BIT
1566 * @arg @ref LL_SPI_CRC_32BIT
1567 * @retval None
1568 */
LL_SPI_SetCRCWidth(SPI_TypeDef * SPIx,uint32_t CRCLength)1569 __STATIC_INLINE void LL_SPI_SetCRCWidth(SPI_TypeDef *SPIx, uint32_t CRCLength)
1570 {
1571 MODIFY_REG(SPIx->CFG1, SPI_CFG1_CRCSIZE, CRCLength);
1572 }
1573
1574 /**
1575 * @brief Get CRC Length
1576 * @rmtoll CFG1 CRCSIZE LL_SPI_GetCRCWidth
1577 * @param SPIx SPI Instance
1578 * @retval Returned value can be one of the following values:
1579 * @arg @ref LL_SPI_CRC_4BIT
1580 * @arg @ref LL_SPI_CRC_5BIT
1581 * @arg @ref LL_SPI_CRC_6BIT
1582 * @arg @ref LL_SPI_CRC_7BIT
1583 * @arg @ref LL_SPI_CRC_8BIT
1584 * @arg @ref LL_SPI_CRC_9BIT
1585 * @arg @ref LL_SPI_CRC_10BIT
1586 * @arg @ref LL_SPI_CRC_11BIT
1587 * @arg @ref LL_SPI_CRC_12BIT
1588 * @arg @ref LL_SPI_CRC_13BIT
1589 * @arg @ref LL_SPI_CRC_14BIT
1590 * @arg @ref LL_SPI_CRC_15BIT
1591 * @arg @ref LL_SPI_CRC_16BIT
1592 * @arg @ref LL_SPI_CRC_17BIT
1593 * @arg @ref LL_SPI_CRC_18BIT
1594 * @arg @ref LL_SPI_CRC_19BIT
1595 * @arg @ref LL_SPI_CRC_20BIT
1596 * @arg @ref LL_SPI_CRC_21BIT
1597 * @arg @ref LL_SPI_CRC_22BIT
1598 * @arg @ref LL_SPI_CRC_23BIT
1599 * @arg @ref LL_SPI_CRC_24BIT
1600 * @arg @ref LL_SPI_CRC_25BIT
1601 * @arg @ref LL_SPI_CRC_26BIT
1602 * @arg @ref LL_SPI_CRC_27BIT
1603 * @arg @ref LL_SPI_CRC_28BIT
1604 * @arg @ref LL_SPI_CRC_29BIT
1605 * @arg @ref LL_SPI_CRC_30BIT
1606 * @arg @ref LL_SPI_CRC_31BIT
1607 * @arg @ref LL_SPI_CRC_32BIT
1608 */
LL_SPI_GetCRCWidth(SPI_TypeDef * SPIx)1609 __STATIC_INLINE uint32_t LL_SPI_GetCRCWidth(SPI_TypeDef *SPIx)
1610 {
1611 return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_CRCSIZE));
1612 }
1613
1614 /**
1615 * @brief Set NSS Mode
1616 * @note This configuration can not be changed when SPI is enabled.
1617 * This bit is not used in SPI TI mode.
1618 * @rmtoll CFG2 SSM LL_SPI_SetNSSMode\n
1619 * CFG2 SSOE LL_SPI_SetNSSMode
1620 * @param SPIx SPI Instance
1621 * @param NSS This parameter can be one of the following values:
1622 * @arg @ref LL_SPI_NSS_SOFT
1623 * @arg @ref LL_SPI_NSS_HARD_INPUT
1624 * @arg @ref LL_SPI_NSS_HARD_OUTPUT
1625 * @retval None
1626 */
LL_SPI_SetNSSMode(SPI_TypeDef * SPIx,uint32_t NSS)1627 __STATIC_INLINE void LL_SPI_SetNSSMode(SPI_TypeDef *SPIx, uint32_t NSS)
1628 {
1629 MODIFY_REG(SPIx->CFG2, SPI_CFG2_SSM | SPI_CFG2_SSOE, NSS);
1630 }
1631
1632 /**
1633 * @brief Set NSS Mode
1634 * @rmtoll CFG2 SSM LL_SPI_GetNSSMode\n
1635 * CFG2 SSOE LL_SPI_GetNSSMode
1636 * @param SPIx SPI Instance
1637 * @retval Returned value can be one of the following values:
1638 * @arg @ref LL_SPI_NSS_SOFT
1639 * @arg @ref LL_SPI_NSS_HARD_INPUT
1640 * @arg @ref LL_SPI_NSS_HARD_OUTPUT
1641 */
LL_SPI_GetNSSMode(SPI_TypeDef * SPIx)1642 __STATIC_INLINE uint32_t LL_SPI_GetNSSMode(SPI_TypeDef *SPIx)
1643 {
1644 return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_SSM | SPI_CFG2_SSOE));
1645 }
1646
1647 /**
1648 * @brief Enable NSS pulse mgt
1649 * @note This configuration can not be changed when SPI is enabled.
1650 * This bit is not used in SPI TI mode.
1651 * @rmtoll CFG2 SSOM LL_SPI_EnableNSSPulseMgt
1652 * @param SPIx SPI Instance
1653 * @retval None
1654 */
LL_SPI_EnableNSSPulseMgt(SPI_TypeDef * SPIx)1655 __STATIC_INLINE void LL_SPI_EnableNSSPulseMgt(SPI_TypeDef *SPIx)
1656 {
1657 SET_BIT(SPIx->CFG2, SPI_CFG2_SSOM);
1658 }
1659
1660 /**
1661 * @brief Disable NSS pulse mgt
1662 * @note This configuration can not be changed when SPI is enabled.
1663 * This bit is not used in SPI TI mode.
1664 * @rmtoll CFG2 SSOM LL_SPI_DisableNSSPulseMgt
1665 * @param SPIx SPI Instance
1666 * @retval None
1667 */
LL_SPI_DisableNSSPulseMgt(SPI_TypeDef * SPIx)1668 __STATIC_INLINE void LL_SPI_DisableNSSPulseMgt(SPI_TypeDef *SPIx)
1669 {
1670 CLEAR_BIT(SPIx->CFG2, SPI_CFG2_SSOM);
1671 }
1672
1673 /**
1674 * @brief Check if NSS pulse is enabled
1675 * @rmtoll CFG2 SSOM LL_SPI_IsEnabledNSSPulse
1676 * @param SPIx SPI Instance
1677 * @retval State of bit (1 or 0)
1678 */
LL_SPI_IsEnabledNSSPulse(SPI_TypeDef * SPIx)1679 __STATIC_INLINE uint32_t LL_SPI_IsEnabledNSSPulse(SPI_TypeDef *SPIx)
1680 {
1681 return ((READ_BIT(SPIx->CFG2, SPI_CFG2_SSOM) == SPI_CFG2_SSOM) ? 1UL : 0UL);
1682 }
1683
1684 /**
1685 * @}
1686 */
1687
1688 /** @defgroup SPI_LL_EF_FLAG_Management FLAG_Management
1689 * @{
1690 */
1691
1692 /**
1693 * @brief Check if there is enough data in FIFO to read a full packet
1694 * @rmtoll SR RXP LL_SPI_IsActiveFlag_RXP
1695 * @param SPIx SPI Instance
1696 * @retval State of bit (1 or 0)
1697 */
LL_SPI_IsActiveFlag_RXP(SPI_TypeDef * SPIx)1698 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXP(SPI_TypeDef *SPIx)
1699 {
1700 return ((READ_BIT(SPIx->SR, SPI_SR_RXP) == (SPI_SR_RXP)) ? 1UL : 0UL);
1701 }
1702
1703 /**
1704 * @brief Check if there is enough space in FIFO to hold a full packet
1705 * @rmtoll SR TXP LL_SPI_IsActiveFlag_TXP
1706 * @param SPIx SPI Instance
1707 * @retval State of bit (1 or 0)
1708 */
LL_SPI_IsActiveFlag_TXP(SPI_TypeDef * SPIx)1709 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXP(SPI_TypeDef *SPIx)
1710 {
1711 return ((READ_BIT(SPIx->SR, SPI_SR_TXP) == (SPI_SR_TXP)) ? 1UL : 0UL);
1712 }
1713
1714 /**
1715 * @brief Check if there enough space in FIFO to hold a full packet, AND enough data to read a full packet
1716 * @rmtoll SR DXP LL_SPI_IsActiveFlag_DXP
1717 * @param SPIx SPI Instance
1718 * @retval State of bit (1 or 0)
1719 */
LL_SPI_IsActiveFlag_DXP(SPI_TypeDef * SPIx)1720 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_DXP(SPI_TypeDef *SPIx)
1721 {
1722 return ((READ_BIT(SPIx->SR, SPI_SR_DXP) == (SPI_SR_DXP)) ? 1UL : 0UL);
1723 }
1724
1725 /**
1726 * @brief Check that end of transfer event occurred
1727 * @rmtoll SR EOT LL_SPI_IsActiveFlag_EOT
1728 * @param SPIx SPI Instance
1729 * @retval State of bit (1 or 0).
1730 */
LL_SPI_IsActiveFlag_EOT(SPI_TypeDef * SPIx)1731 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_EOT(SPI_TypeDef *SPIx)
1732 {
1733 return ((READ_BIT(SPIx->SR, SPI_SR_EOT) == (SPI_SR_EOT)) ? 1UL : 0UL);
1734 }
1735
1736 /**
1737 * @brief Check that all required data has been filled in the fifo according to transfer size
1738 * @rmtoll SR TXTF LL_SPI_IsActiveFlag_TXTF
1739 * @param SPIx SPI Instance
1740 * @retval State of bit (1 or 0).
1741 */
LL_SPI_IsActiveFlag_TXTF(SPI_TypeDef * SPIx)1742 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXTF(SPI_TypeDef *SPIx)
1743 {
1744 return ((READ_BIT(SPIx->SR, SPI_SR_TXTF) == (SPI_SR_TXTF)) ? 1UL : 0UL);
1745 }
1746
1747 /**
1748 * @brief Get Underrun error flag
1749 * @rmtoll SR UDR LL_SPI_IsActiveFlag_UDR
1750 * @param SPIx SPI Instance
1751 * @retval State of bit (1 or 0).
1752 */
LL_SPI_IsActiveFlag_UDR(SPI_TypeDef * SPIx)1753 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_UDR(SPI_TypeDef *SPIx)
1754 {
1755 return ((READ_BIT(SPIx->SR, SPI_SR_UDR) == (SPI_SR_UDR)) ? 1UL : 0UL);
1756 }
1757
1758 /**
1759 * @brief Get CRC error flag
1760 * @rmtoll SR CRCE LL_SPI_IsActiveFlag_CRCERR
1761 * @param SPIx SPI Instance
1762 * @retval State of bit (1 or 0).
1763 */
LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef * SPIx)1764 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx)
1765 {
1766 return ((READ_BIT(SPIx->SR, SPI_SR_CRCE) == (SPI_SR_CRCE)) ? 1UL : 0UL);
1767 }
1768
1769 /**
1770 * @brief Get Mode fault error flag
1771 * @rmtoll SR MODF LL_SPI_IsActiveFlag_MODF
1772 * @param SPIx SPI Instance
1773 * @retval State of bit (1 or 0).
1774 */
LL_SPI_IsActiveFlag_MODF(SPI_TypeDef * SPIx)1775 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx)
1776 {
1777 return ((READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF)) ? 1UL : 0UL);
1778 }
1779
1780 /**
1781 * @brief Get Overrun error flag
1782 * @rmtoll SR OVR LL_SPI_IsActiveFlag_OVR
1783 * @param SPIx SPI Instance
1784 * @retval State of bit (1 or 0).
1785 */
LL_SPI_IsActiveFlag_OVR(SPI_TypeDef * SPIx)1786 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
1787 {
1788 return ((READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR)) ? 1UL : 0UL);
1789 }
1790
1791 /**
1792 * @brief Get TI Frame format error flag
1793 * @rmtoll SR TIFRE LL_SPI_IsActiveFlag_FRE
1794 * @param SPIx SPI Instance
1795 * @retval State of bit (1 or 0).
1796 */
LL_SPI_IsActiveFlag_FRE(SPI_TypeDef * SPIx)1797 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(SPI_TypeDef *SPIx)
1798 {
1799 return ((READ_BIT(SPIx->SR, SPI_SR_TIFRE) == (SPI_SR_TIFRE)) ? 1UL : 0UL);
1800 }
1801
1802 /**
1803 * @brief Check if the additional number of data has been reloaded
1804 * @rmtoll SR TSERF LL_SPI_IsActiveFlag_TSER
1805 * @param SPIx SPI Instance
1806 * @retval State of bit (1 or 0).
1807 */
LL_SPI_IsActiveFlag_TSER(SPI_TypeDef * SPIx)1808 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TSER(SPI_TypeDef *SPIx)
1809 {
1810 return ((READ_BIT(SPIx->SR, SPI_SR_TSERF) == (SPI_SR_TSERF)) ? 1UL : 0UL);
1811 }
1812
1813 /**
1814 * @brief Check if a suspend operation is done
1815 * @rmtoll SR SUSP LL_SPI_IsActiveFlag_SUSP
1816 * @param SPIx SPI Instance
1817 * @retval State of bit (1 or 0)
1818 */
LL_SPI_IsActiveFlag_SUSP(SPI_TypeDef * SPIx)1819 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_SUSP(SPI_TypeDef *SPIx)
1820 {
1821 return ((READ_BIT(SPIx->SR, SPI_SR_SUSP) == (SPI_SR_SUSP)) ? 1UL : 0UL);
1822 }
1823
1824 /**
1825 * @brief Check if last TxFIFO or CRC frame transmission is completed
1826 * @rmtoll SR TXC LL_SPI_IsActiveFlag_TXC
1827 * @param SPIx SPI Instance
1828 * @retval State of bit (1 or 0).
1829 */
LL_SPI_IsActiveFlag_TXC(SPI_TypeDef * SPIx)1830 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXC(SPI_TypeDef *SPIx)
1831 {
1832 return ((READ_BIT(SPIx->SR, SPI_SR_TXC) == (SPI_SR_TXC)) ? 1UL : 0UL);
1833 }
1834
1835 /**
1836 * @brief Check if at least one 32-bit data is available in RxFIFO
1837 * @rmtoll SR RXWNE LL_SPI_IsActiveFlag_RXWNE
1838 * @param SPIx SPI Instance
1839 * @retval State of bit (1 or 0)
1840 */
LL_SPI_IsActiveFlag_RXWNE(SPI_TypeDef * SPIx)1841 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXWNE(SPI_TypeDef *SPIx)
1842 {
1843 return ((READ_BIT(SPIx->SR, SPI_SR_RXWNE) == (SPI_SR_RXWNE)) ? 1UL : 0UL);
1844 }
1845
1846 /**
1847 * @brief Get number of data framed remaining in current TSIZE
1848 * @rmtoll SR CTSIZE LL_SPI_GetRemainingDataFrames
1849 * @param SPIx SPI Instance
1850 * @retval 0..0xFFFF
1851 */
LL_SPI_GetRemainingDataFrames(SPI_TypeDef * SPIx)1852 __STATIC_INLINE uint32_t LL_SPI_GetRemainingDataFrames(SPI_TypeDef *SPIx)
1853 {
1854 return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_CTSIZE) >> SPI_SR_CTSIZE_Pos);
1855 }
1856
1857 /**
1858 * @brief Get RxFIFO packing Level
1859 * @rmtoll SR RXPLVL LL_SPI_GetRxFIFOPackingLevel
1860 * @param SPIx SPI Instance
1861 * @retval Returned value can be one of the following values:
1862 * @arg @ref LL_SPI_RX_FIFO_0PACKET
1863 * @arg @ref LL_SPI_RX_FIFO_1PACKET
1864 * @arg @ref LL_SPI_RX_FIFO_2PACKET
1865 * @arg @ref LL_SPI_RX_FIFO_3PACKET
1866 */
LL_SPI_GetRxFIFOPackingLevel(SPI_TypeDef * SPIx)1867 __STATIC_INLINE uint32_t LL_SPI_GetRxFIFOPackingLevel(SPI_TypeDef *SPIx)
1868 {
1869 return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_RXPLVL));
1870 }
1871
1872 /**
1873 * @brief Clear End Of Transfer flag
1874 * @rmtoll IFCR EOTC LL_SPI_ClearFlag_EOT
1875 * @param SPIx SPI Instance
1876 * @retval None
1877 */
LL_SPI_ClearFlag_EOT(SPI_TypeDef * SPIx)1878 __STATIC_INLINE void LL_SPI_ClearFlag_EOT(SPI_TypeDef *SPIx)
1879 {
1880 SET_BIT(SPIx->IFCR, SPI_IFCR_EOTC);
1881 }
1882
1883 /**
1884 * @brief Clear TXTF flag
1885 * @rmtoll IFCR TXTFC LL_SPI_ClearFlag_TXTF
1886 * @param SPIx SPI Instance
1887 * @retval None
1888 */
LL_SPI_ClearFlag_TXTF(SPI_TypeDef * SPIx)1889 __STATIC_INLINE void LL_SPI_ClearFlag_TXTF(SPI_TypeDef *SPIx)
1890 {
1891 SET_BIT(SPIx->IFCR, SPI_IFCR_TXTFC);
1892 }
1893
1894 /**
1895 * @brief Clear Underrun error flag
1896 * @rmtoll IFCR UDRC LL_SPI_ClearFlag_UDR
1897 * @param SPIx SPI Instance
1898 * @retval None
1899 */
LL_SPI_ClearFlag_UDR(SPI_TypeDef * SPIx)1900 __STATIC_INLINE void LL_SPI_ClearFlag_UDR(SPI_TypeDef *SPIx)
1901 {
1902 SET_BIT(SPIx->IFCR, SPI_IFCR_UDRC);
1903 }
1904
1905 /**
1906 * @brief Clear Overrun error flag
1907 * @rmtoll IFCR OVRC LL_SPI_ClearFlag_OVR
1908 * @param SPIx SPI Instance
1909 * @retval None
1910 */
LL_SPI_ClearFlag_OVR(SPI_TypeDef * SPIx)1911 __STATIC_INLINE void LL_SPI_ClearFlag_OVR(SPI_TypeDef *SPIx)
1912 {
1913 SET_BIT(SPIx->IFCR, SPI_IFCR_OVRC);
1914 }
1915
1916 /**
1917 * @brief Clear CRC error flag
1918 * @rmtoll IFCR CRCEC LL_SPI_ClearFlag_CRCERR
1919 * @param SPIx SPI Instance
1920 * @retval None
1921 */
LL_SPI_ClearFlag_CRCERR(SPI_TypeDef * SPIx)1922 __STATIC_INLINE void LL_SPI_ClearFlag_CRCERR(SPI_TypeDef *SPIx)
1923 {
1924 SET_BIT(SPIx->IFCR, SPI_IFCR_CRCEC);
1925 }
1926
1927 /**
1928 * @brief Clear Mode fault error flag
1929 * @rmtoll IFCR MODFC LL_SPI_ClearFlag_MODF
1930 * @param SPIx SPI Instance
1931 * @retval None
1932 */
LL_SPI_ClearFlag_MODF(SPI_TypeDef * SPIx)1933 __STATIC_INLINE void LL_SPI_ClearFlag_MODF(SPI_TypeDef *SPIx)
1934 {
1935 SET_BIT(SPIx->IFCR, SPI_IFCR_MODFC);
1936 }
1937
1938 /**
1939 * @brief Clear Frame format error flag
1940 * @rmtoll IFCR TIFREC LL_SPI_ClearFlag_FRE
1941 * @param SPIx SPI Instance
1942 * @retval None
1943 */
LL_SPI_ClearFlag_FRE(SPI_TypeDef * SPIx)1944 __STATIC_INLINE void LL_SPI_ClearFlag_FRE(SPI_TypeDef *SPIx)
1945 {
1946 SET_BIT(SPIx->IFCR, SPI_IFCR_TIFREC);
1947 }
1948
1949 /**
1950 * @brief Clear TSER flag
1951 * @rmtoll IFCR TSERFC LL_SPI_ClearFlag_TSER
1952 * @param SPIx SPI Instance
1953 * @retval None
1954 */
LL_SPI_ClearFlag_TSER(SPI_TypeDef * SPIx)1955 __STATIC_INLINE void LL_SPI_ClearFlag_TSER(SPI_TypeDef *SPIx)
1956 {
1957 SET_BIT(SPIx->IFCR, SPI_IFCR_TSERFC);
1958 }
1959
1960 /**
1961 * @brief Clear SUSP flag
1962 * @rmtoll IFCR SUSPC LL_SPI_ClearFlag_SUSP
1963 * @param SPIx SPI Instance
1964 * @retval None
1965 */
LL_SPI_ClearFlag_SUSP(SPI_TypeDef * SPIx)1966 __STATIC_INLINE void LL_SPI_ClearFlag_SUSP(SPI_TypeDef *SPIx)
1967 {
1968 SET_BIT(SPIx->IFCR, SPI_IFCR_SUSPC);
1969 }
1970
1971 /**
1972 * @}
1973 */
1974
1975 /** @defgroup SPI_LL_EF_IT_Management IT_Management
1976 * @{
1977 */
1978
1979 /**
1980 * @brief Enable Rx Packet available IT
1981 * @rmtoll IER RXPIE LL_SPI_EnableIT_RXP
1982 * @param SPIx SPI Instance
1983 * @retval None
1984 */
LL_SPI_EnableIT_RXP(SPI_TypeDef * SPIx)1985 __STATIC_INLINE void LL_SPI_EnableIT_RXP(SPI_TypeDef *SPIx)
1986 {
1987 SET_BIT(SPIx->IER, SPI_IER_RXPIE);
1988 }
1989
1990 /**
1991 * @brief Enable Tx Packet space available IT
1992 * @rmtoll IER TXPIE LL_SPI_EnableIT_TXP
1993 * @param SPIx SPI Instance
1994 * @retval None
1995 */
LL_SPI_EnableIT_TXP(SPI_TypeDef * SPIx)1996 __STATIC_INLINE void LL_SPI_EnableIT_TXP(SPI_TypeDef *SPIx)
1997 {
1998 SET_BIT(SPIx->IER, SPI_IER_TXPIE);
1999 }
2000
2001 /**
2002 * @brief Enable Duplex Packet available IT
2003 * @rmtoll IER DXPIE LL_SPI_EnableIT_DXP
2004 * @param SPIx SPI Instance
2005 * @retval None
2006 */
LL_SPI_EnableIT_DXP(SPI_TypeDef * SPIx)2007 __STATIC_INLINE void LL_SPI_EnableIT_DXP(SPI_TypeDef *SPIx)
2008 {
2009 SET_BIT(SPIx->IER, SPI_IER_DXPIE);
2010 }
2011
2012 /**
2013 * @brief Enable End Of Transfer IT
2014 * @rmtoll IER EOTIE LL_SPI_EnableIT_EOT
2015 * @param SPIx SPI Instance
2016 * @retval None
2017 */
LL_SPI_EnableIT_EOT(SPI_TypeDef * SPIx)2018 __STATIC_INLINE void LL_SPI_EnableIT_EOT(SPI_TypeDef *SPIx)
2019 {
2020 SET_BIT(SPIx->IER, SPI_IER_EOTIE);
2021 }
2022
2023 /**
2024 * @brief Enable TXTF IT
2025 * @rmtoll IER TXTFIE LL_SPI_EnableIT_TXTF
2026 * @param SPIx SPI Instance
2027 * @retval None
2028 */
LL_SPI_EnableIT_TXTF(SPI_TypeDef * SPIx)2029 __STATIC_INLINE void LL_SPI_EnableIT_TXTF(SPI_TypeDef *SPIx)
2030 {
2031 SET_BIT(SPIx->IER, SPI_IER_TXTFIE);
2032 }
2033
2034 /**
2035 * @brief Enable Underrun IT
2036 * @rmtoll IER UDRIE LL_SPI_EnableIT_UDR
2037 * @param SPIx SPI Instance
2038 * @retval None
2039 */
LL_SPI_EnableIT_UDR(SPI_TypeDef * SPIx)2040 __STATIC_INLINE void LL_SPI_EnableIT_UDR(SPI_TypeDef *SPIx)
2041 {
2042 SET_BIT(SPIx->IER, SPI_IER_UDRIE);
2043 }
2044
2045 /**
2046 * @brief Enable Overrun IT
2047 * @rmtoll IER OVRIE LL_SPI_EnableIT_OVR
2048 * @param SPIx SPI Instance
2049 * @retval None
2050 */
LL_SPI_EnableIT_OVR(SPI_TypeDef * SPIx)2051 __STATIC_INLINE void LL_SPI_EnableIT_OVR(SPI_TypeDef *SPIx)
2052 {
2053 SET_BIT(SPIx->IER, SPI_IER_OVRIE);
2054 }
2055
2056 /**
2057 * @brief Enable CRC Error IT
2058 * @rmtoll IER CRCEIE LL_SPI_EnableIT_CRCERR
2059 * @param SPIx SPI Instance
2060 * @retval None
2061 */
LL_SPI_EnableIT_CRCERR(SPI_TypeDef * SPIx)2062 __STATIC_INLINE void LL_SPI_EnableIT_CRCERR(SPI_TypeDef *SPIx)
2063 {
2064 SET_BIT(SPIx->IER, SPI_IER_CRCEIE);
2065 }
2066
2067 /**
2068 * @brief Enable TI Frame Format Error IT
2069 * @rmtoll IER TIFREIE LL_SPI_EnableIT_FRE
2070 * @param SPIx SPI Instance
2071 * @retval None
2072 */
LL_SPI_EnableIT_FRE(SPI_TypeDef * SPIx)2073 __STATIC_INLINE void LL_SPI_EnableIT_FRE(SPI_TypeDef *SPIx)
2074 {
2075 SET_BIT(SPIx->IER, SPI_IER_TIFREIE);
2076 }
2077
2078 /**
2079 * @brief Enable MODF IT
2080 * @rmtoll IER MODFIE LL_SPI_EnableIT_MODF
2081 * @param SPIx SPI Instance
2082 * @retval None
2083 */
LL_SPI_EnableIT_MODF(SPI_TypeDef * SPIx)2084 __STATIC_INLINE void LL_SPI_EnableIT_MODF(SPI_TypeDef *SPIx)
2085 {
2086 SET_BIT(SPIx->IER, SPI_IER_MODFIE);
2087 }
2088
2089 /**
2090 * @brief Enable TSER reload IT
2091 * @rmtoll IER TSERFIE LL_SPI_EnableIT_TSER
2092 * @param SPIx SPI Instance
2093 * @retval None
2094 */
LL_SPI_EnableIT_TSER(SPI_TypeDef * SPIx)2095 __STATIC_INLINE void LL_SPI_EnableIT_TSER(SPI_TypeDef *SPIx)
2096 {
2097 SET_BIT(SPIx->IER, SPI_IER_TSERFIE);
2098 }
2099
2100 /**
2101 * @brief Disable Rx Packet available IT
2102 * @rmtoll IER RXPIE LL_SPI_DisableIT_RXP
2103 * @param SPIx SPI Instance
2104 * @retval None
2105 */
LL_SPI_DisableIT_RXP(SPI_TypeDef * SPIx)2106 __STATIC_INLINE void LL_SPI_DisableIT_RXP(SPI_TypeDef *SPIx)
2107 {
2108 CLEAR_BIT(SPIx->IER, SPI_IER_RXPIE);
2109 }
2110
2111 /**
2112 * @brief Disable Tx Packet space available IT
2113 * @rmtoll IER TXPIE LL_SPI_DisableIT_TXP
2114 * @param SPIx SPI Instance
2115 * @retval None
2116 */
LL_SPI_DisableIT_TXP(SPI_TypeDef * SPIx)2117 __STATIC_INLINE void LL_SPI_DisableIT_TXP(SPI_TypeDef *SPIx)
2118 {
2119 CLEAR_BIT(SPIx->IER, SPI_IER_TXPIE);
2120 }
2121
2122 /**
2123 * @brief Disable Duplex Packet available IT
2124 * @rmtoll IER DXPIE LL_SPI_DisableIT_DXP
2125 * @param SPIx SPI Instance
2126 * @retval None
2127 */
LL_SPI_DisableIT_DXP(SPI_TypeDef * SPIx)2128 __STATIC_INLINE void LL_SPI_DisableIT_DXP(SPI_TypeDef *SPIx)
2129 {
2130 CLEAR_BIT(SPIx->IER, SPI_IER_DXPIE);
2131 }
2132
2133 /**
2134 * @brief Disable End Of Transfer IT
2135 * @rmtoll IER EOTIE LL_SPI_DisableIT_EOT
2136 * @param SPIx SPI Instance
2137 * @retval None
2138 */
LL_SPI_DisableIT_EOT(SPI_TypeDef * SPIx)2139 __STATIC_INLINE void LL_SPI_DisableIT_EOT(SPI_TypeDef *SPIx)
2140 {
2141 CLEAR_BIT(SPIx->IER, SPI_IER_EOTIE);
2142 }
2143
2144 /**
2145 * @brief Disable TXTF IT
2146 * @rmtoll IER TXTFIE LL_SPI_DisableIT_TXTF
2147 * @param SPIx SPI Instance
2148 * @retval None
2149 */
LL_SPI_DisableIT_TXTF(SPI_TypeDef * SPIx)2150 __STATIC_INLINE void LL_SPI_DisableIT_TXTF(SPI_TypeDef *SPIx)
2151 {
2152 CLEAR_BIT(SPIx->IER, SPI_IER_TXTFIE);
2153 }
2154
2155 /**
2156 * @brief Disable Underrun IT
2157 * @rmtoll IER UDRIE LL_SPI_DisableIT_UDR
2158 * @param SPIx SPI Instance
2159 * @retval None
2160 */
LL_SPI_DisableIT_UDR(SPI_TypeDef * SPIx)2161 __STATIC_INLINE void LL_SPI_DisableIT_UDR(SPI_TypeDef *SPIx)
2162 {
2163 CLEAR_BIT(SPIx->IER, SPI_IER_UDRIE);
2164 }
2165
2166 /**
2167 * @brief Disable Overrun IT
2168 * @rmtoll IER OVRIE LL_SPI_DisableIT_OVR
2169 * @param SPIx SPI Instance
2170 * @retval None
2171 */
LL_SPI_DisableIT_OVR(SPI_TypeDef * SPIx)2172 __STATIC_INLINE void LL_SPI_DisableIT_OVR(SPI_TypeDef *SPIx)
2173 {
2174 CLEAR_BIT(SPIx->IER, SPI_IER_OVRIE);
2175 }
2176
2177 /**
2178 * @brief Disable CRC Error IT
2179 * @rmtoll IER CRCEIE LL_SPI_DisableIT_CRCERR
2180 * @param SPIx SPI Instance
2181 * @retval None
2182 */
LL_SPI_DisableIT_CRCERR(SPI_TypeDef * SPIx)2183 __STATIC_INLINE void LL_SPI_DisableIT_CRCERR(SPI_TypeDef *SPIx)
2184 {
2185 CLEAR_BIT(SPIx->IER, SPI_IER_CRCEIE);
2186 }
2187
2188 /**
2189 * @brief Disable TI Frame Format Error IT
2190 * @rmtoll IER TIFREIE LL_SPI_DisableIT_FRE
2191 * @param SPIx SPI Instance
2192 * @retval None
2193 */
LL_SPI_DisableIT_FRE(SPI_TypeDef * SPIx)2194 __STATIC_INLINE void LL_SPI_DisableIT_FRE(SPI_TypeDef *SPIx)
2195 {
2196 CLEAR_BIT(SPIx->IER, SPI_IER_TIFREIE);
2197 }
2198
2199 /**
2200 * @brief Disable MODF IT
2201 * @rmtoll IER MODFIE LL_SPI_DisableIT_MODF
2202 * @param SPIx SPI Instance
2203 * @retval None
2204 */
LL_SPI_DisableIT_MODF(SPI_TypeDef * SPIx)2205 __STATIC_INLINE void LL_SPI_DisableIT_MODF(SPI_TypeDef *SPIx)
2206 {
2207 CLEAR_BIT(SPIx->IER, SPI_IER_MODFIE);
2208 }
2209
2210 /**
2211 * @brief Disable TSER reload IT
2212 * @rmtoll IER TSERFIE LL_SPI_DisableIT_TSER
2213 * @param SPIx SPI Instance
2214 * @retval None
2215 */
LL_SPI_DisableIT_TSER(SPI_TypeDef * SPIx)2216 __STATIC_INLINE void LL_SPI_DisableIT_TSER(SPI_TypeDef *SPIx)
2217 {
2218 CLEAR_BIT(SPIx->IER, SPI_IER_TSERFIE);
2219 }
2220
2221 /**
2222 * @brief Check if Rx Packet available IT is enabled
2223 * @rmtoll IER RXPIE LL_SPI_IsEnabledIT_RXP
2224 * @param SPIx SPI Instance
2225 * @retval State of bit (1 or 0)
2226 */
LL_SPI_IsEnabledIT_RXP(SPI_TypeDef * SPIx)2227 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXP(SPI_TypeDef *SPIx)
2228 {
2229 return ((READ_BIT(SPIx->IER, SPI_IER_RXPIE) == (SPI_IER_RXPIE)) ? 1UL : 0UL);
2230 }
2231
2232 /**
2233 * @brief Check if Tx Packet space available IT is enabled
2234 * @rmtoll IER TXPIE LL_SPI_IsEnabledIT_TXP
2235 * @param SPIx SPI Instance
2236 * @retval State of bit (1 or 0)
2237 */
LL_SPI_IsEnabledIT_TXP(SPI_TypeDef * SPIx)2238 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXP(SPI_TypeDef *SPIx)
2239 {
2240 return ((READ_BIT(SPIx->IER, SPI_IER_TXPIE) == (SPI_IER_TXPIE)) ? 1UL : 0UL);
2241 }
2242
2243 /**
2244 * @brief Check if Duplex Packet available IT is enabled
2245 * @rmtoll IER DXPIE LL_SPI_IsEnabledIT_DXP
2246 * @param SPIx SPI Instance
2247 * @retval State of bit (1 or 0)
2248 */
LL_SPI_IsEnabledIT_DXP(SPI_TypeDef * SPIx)2249 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_DXP(SPI_TypeDef *SPIx)
2250 {
2251 return ((READ_BIT(SPIx->IER, SPI_IER_DXPIE) == (SPI_IER_DXPIE)) ? 1UL : 0UL);
2252 }
2253
2254 /**
2255 * @brief Check if End Of Transfer IT is enabled
2256 * @rmtoll IER EOTIE LL_SPI_IsEnabledIT_EOT
2257 * @param SPIx SPI Instance
2258 * @retval State of bit (1 or 0)
2259 */
LL_SPI_IsEnabledIT_EOT(SPI_TypeDef * SPIx)2260 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_EOT(SPI_TypeDef *SPIx)
2261 {
2262 return ((READ_BIT(SPIx->IER, SPI_IER_EOTIE) == (SPI_IER_EOTIE)) ? 1UL : 0UL);
2263 }
2264
2265 /**
2266 * @brief Check if TXTF IT is enabled
2267 * @rmtoll IER TXTFIE LL_SPI_IsEnabledIT_TXTF
2268 * @param SPIx SPI Instance
2269 * @retval State of bit (1 or 0)
2270 */
LL_SPI_IsEnabledIT_TXTF(SPI_TypeDef * SPIx)2271 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXTF(SPI_TypeDef *SPIx)
2272 {
2273 return ((READ_BIT(SPIx->IER, SPI_IER_TXTFIE) == (SPI_IER_TXTFIE)) ? 1UL : 0UL);
2274 }
2275
2276 /**
2277 * @brief Check if Underrun IT is enabled
2278 * @rmtoll IER UDRIE LL_SPI_IsEnabledIT_UDR
2279 * @param SPIx SPI Instance
2280 * @retval State of bit (1 or 0)
2281 */
LL_SPI_IsEnabledIT_UDR(SPI_TypeDef * SPIx)2282 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_UDR(SPI_TypeDef *SPIx)
2283 {
2284 return ((READ_BIT(SPIx->IER, SPI_IER_UDRIE) == (SPI_IER_UDRIE)) ? 1UL : 0UL);
2285 }
2286
2287 /**
2288 * @brief Check if Overrun IT is enabled
2289 * @rmtoll IER OVRIE LL_SPI_IsEnabledIT_OVR
2290 * @param SPIx SPI Instance
2291 * @retval State of bit (1 or 0)
2292 */
LL_SPI_IsEnabledIT_OVR(SPI_TypeDef * SPIx)2293 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_OVR(SPI_TypeDef *SPIx)
2294 {
2295 return ((READ_BIT(SPIx->IER, SPI_IER_OVRIE) == (SPI_IER_OVRIE)) ? 1UL : 0UL);
2296 }
2297
2298 /**
2299 * @brief Check if CRC Error IT is enabled
2300 * @rmtoll IER CRCEIE LL_SPI_IsEnabledIT_CRCERR
2301 * @param SPIx SPI Instance
2302 * @retval State of bit (1 or 0)
2303 */
LL_SPI_IsEnabledIT_CRCERR(SPI_TypeDef * SPIx)2304 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_CRCERR(SPI_TypeDef *SPIx)
2305 {
2306 return ((READ_BIT(SPIx->IER, SPI_IER_CRCEIE) == (SPI_IER_CRCEIE)) ? 1UL : 0UL);
2307 }
2308
2309 /**
2310 * @brief Check if TI Frame Format Error IT is enabled
2311 * @rmtoll IER TIFREIE LL_SPI_IsEnabledIT_FRE
2312 * @param SPIx SPI Instance
2313 * @retval State of bit (1 or 0)
2314 */
LL_SPI_IsEnabledIT_FRE(SPI_TypeDef * SPIx)2315 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_FRE(SPI_TypeDef *SPIx)
2316 {
2317 return ((READ_BIT(SPIx->IER, SPI_IER_TIFREIE) == (SPI_IER_TIFREIE)) ? 1UL : 0UL);
2318 }
2319
2320 /**
2321 * @brief Check if MODF IT is enabled
2322 * @rmtoll IER MODFIE LL_SPI_IsEnabledIT_MODF
2323 * @param SPIx SPI Instance
2324 * @retval State of bit (1 or 0)
2325 */
LL_SPI_IsEnabledIT_MODF(SPI_TypeDef * SPIx)2326 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_MODF(SPI_TypeDef *SPIx)
2327 {
2328 return ((READ_BIT(SPIx->IER, SPI_IER_MODFIE) == (SPI_IER_MODFIE)) ? 1UL : 0UL);
2329 }
2330
2331 /**
2332 * @brief Check if TSER reload IT is enabled
2333 * @rmtoll IER TSERFIE LL_SPI_IsEnabledIT_TSER
2334 * @param SPIx SPI Instance
2335 * @retval State of bit (1 or 0)
2336 */
LL_SPI_IsEnabledIT_TSER(SPI_TypeDef * SPIx)2337 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TSER(SPI_TypeDef *SPIx)
2338 {
2339 return ((READ_BIT(SPIx->IER, SPI_IER_TSERFIE) == (SPI_IER_TSERFIE)) ? 1UL : 0UL);
2340 }
2341
2342 /**
2343 * @}
2344 */
2345
2346 /** @defgroup SPI_LL_EF_DMA_Management DMA Management
2347 * @{
2348 */
2349
2350 /**
2351 * @brief Enable DMA Rx
2352 * @rmtoll CFG1 RXDMAEN LL_SPI_EnableDMAReq_RX
2353 * @param SPIx SPI Instance
2354 * @retval None
2355 */
LL_SPI_EnableDMAReq_RX(SPI_TypeDef * SPIx)2356 __STATIC_INLINE void LL_SPI_EnableDMAReq_RX(SPI_TypeDef *SPIx)
2357 {
2358 SET_BIT(SPIx->CFG1, SPI_CFG1_RXDMAEN);
2359 }
2360
2361 /**
2362 * @brief Disable DMA Rx
2363 * @rmtoll CFG1 RXDMAEN LL_SPI_DisableDMAReq_RX
2364 * @param SPIx SPI Instance
2365 * @retval None
2366 */
LL_SPI_DisableDMAReq_RX(SPI_TypeDef * SPIx)2367 __STATIC_INLINE void LL_SPI_DisableDMAReq_RX(SPI_TypeDef *SPIx)
2368 {
2369 CLEAR_BIT(SPIx->CFG1, SPI_CFG1_RXDMAEN);
2370 }
2371
2372 /**
2373 * @brief Check if DMA Rx is enabled
2374 * @rmtoll CFG1 RXDMAEN LL_SPI_IsEnabledDMAReq_RX
2375 * @param SPIx SPI Instance
2376 * @retval State of bit (1 or 0)
2377 */
LL_SPI_IsEnabledDMAReq_RX(SPI_TypeDef * SPIx)2378 __STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
2379 {
2380 return ((READ_BIT(SPIx->CFG1, SPI_CFG1_RXDMAEN) == (SPI_CFG1_RXDMAEN)) ? 1UL : 0UL);
2381 }
2382
2383 /**
2384 * @brief Enable DMA Tx
2385 * @rmtoll CFG1 TXDMAEN LL_SPI_EnableDMAReq_TX
2386 * @param SPIx SPI Instance
2387 * @retval None
2388 */
LL_SPI_EnableDMAReq_TX(SPI_TypeDef * SPIx)2389 __STATIC_INLINE void LL_SPI_EnableDMAReq_TX(SPI_TypeDef *SPIx)
2390 {
2391 SET_BIT(SPIx->CFG1, SPI_CFG1_TXDMAEN);
2392 }
2393
2394 /**
2395 * @brief Disable DMA Tx
2396 * @rmtoll CFG1 TXDMAEN LL_SPI_DisableDMAReq_TX
2397 * @param SPIx SPI Instance
2398 * @retval None
2399 */
LL_SPI_DisableDMAReq_TX(SPI_TypeDef * SPIx)2400 __STATIC_INLINE void LL_SPI_DisableDMAReq_TX(SPI_TypeDef *SPIx)
2401 {
2402 CLEAR_BIT(SPIx->CFG1, SPI_CFG1_TXDMAEN);
2403 }
2404
2405 /**
2406 * @brief Check if DMA Tx is enabled
2407 * @rmtoll CFG1 TXDMAEN LL_SPI_IsEnabledDMAReq_TX
2408 * @param SPIx SPI Instance
2409 * @retval State of bit (1 or 0)
2410 */
LL_SPI_IsEnabledDMAReq_TX(SPI_TypeDef * SPIx)2411 __STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
2412 {
2413 return ((READ_BIT(SPIx->CFG1, SPI_CFG1_TXDMAEN) == (SPI_CFG1_TXDMAEN)) ? 1UL : 0UL);
2414 }
2415 /**
2416 * @brief Get the data register address used for DMA transfer
2417 * @rmtoll TXDR TXDR LL_SPI_DMA_GetTxRegAddr
2418 * @param SPIx SPI Instance
2419 * @retval Address of data register
2420 */
LL_SPI_DMA_GetTxRegAddr(SPI_TypeDef * SPIx)2421 __STATIC_INLINE uint32_t LL_SPI_DMA_GetTxRegAddr(SPI_TypeDef *SPIx)
2422 {
2423 return (uint32_t) &(SPIx->TXDR);
2424 }
2425
2426 /**
2427 * @brief Get the data register address used for DMA transfer
2428 * @rmtoll RXDR RXDR LL_SPI_DMA_GetRxRegAddr
2429 * @param SPIx SPI Instance
2430 * @retval Address of data register
2431 */
LL_SPI_DMA_GetRxRegAddr(SPI_TypeDef * SPIx)2432 __STATIC_INLINE uint32_t LL_SPI_DMA_GetRxRegAddr(SPI_TypeDef *SPIx)
2433 {
2434 return (uint32_t) &(SPIx->RXDR);
2435 }
2436 /**
2437 * @}
2438 */
2439
2440 /** @defgroup SPI_LL_EF_DATA_Management DATA_Management
2441 * @{
2442 */
2443
2444 /**
2445 * @brief Read Data Register
2446 * @rmtoll RXDR . LL_SPI_ReceiveData8
2447 * @param SPIx SPI Instance
2448 * @retval 0..0xFF
2449 */
LL_SPI_ReceiveData8(SPI_TypeDef * SPIx)2450 __STATIC_INLINE uint8_t LL_SPI_ReceiveData8(SPI_TypeDef *SPIx)
2451 {
2452 return (*((__IO uint8_t *)&SPIx->RXDR));
2453 }
2454
2455 /**
2456 * @brief Read Data Register
2457 * @rmtoll RXDR . LL_SPI_ReceiveData16
2458 * @param SPIx SPI Instance
2459 * @retval 0..0xFFFF
2460 */
LL_SPI_ReceiveData16(SPI_TypeDef * SPIx)2461 __STATIC_INLINE uint16_t LL_SPI_ReceiveData16(SPI_TypeDef *SPIx)
2462 {
2463 #if defined (__GNUC__)
2464 __IO uint16_t *spirxdr = (__IO uint16_t *)(&(SPIx->RXDR));
2465 return (*spirxdr);
2466 #else
2467 return (*((__IO uint16_t *)&SPIx->RXDR));
2468 #endif /* __GNUC__ */
2469 }
2470
2471 /**
2472 * @brief Read Data Register
2473 * @rmtoll RXDR . LL_SPI_ReceiveData32
2474 * @param SPIx SPI Instance
2475 * @retval 0..0xFFFFFFFF
2476 */
LL_SPI_ReceiveData32(SPI_TypeDef * SPIx)2477 __STATIC_INLINE uint32_t LL_SPI_ReceiveData32(SPI_TypeDef *SPIx)
2478 {
2479 return (*((__IO uint32_t *)&SPIx->RXDR));
2480 }
2481
2482 /**
2483 * @brief Write Data Register
2484 * @rmtoll TXDR . LL_SPI_TransmitData8
2485 * @param SPIx SPI Instance
2486 * @param TxData 0..0xFF
2487 * @retval None
2488 */
LL_SPI_TransmitData8(SPI_TypeDef * SPIx,uint8_t TxData)2489 __STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData)
2490 {
2491 *((__IO uint8_t *)&SPIx->TXDR) = TxData;
2492 }
2493
2494 /**
2495 * @brief Write Data Register
2496 * @rmtoll TXDR . LL_SPI_TransmitData16
2497 * @param SPIx SPI Instance
2498 * @param TxData 0..0xFFFF
2499 * @retval None
2500 */
LL_SPI_TransmitData16(SPI_TypeDef * SPIx,uint16_t TxData)2501 __STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
2502 {
2503 #if defined (__GNUC__)
2504 __IO uint16_t *spitxdr = ((__IO uint16_t *)&SPIx->TXDR);
2505 *spitxdr = TxData;
2506 #else
2507 *((__IO uint16_t *)&SPIx->TXDR) = TxData;
2508 #endif /* __GNUC__ */
2509 }
2510
2511 /**
2512 * @brief Write Data Register
2513 * @rmtoll TXDR . LL_SPI_TransmitData32
2514 * @param SPIx SPI Instance
2515 * @param TxData 0..0xFFFFFFFF
2516 * @retval None
2517 */
LL_SPI_TransmitData32(SPI_TypeDef * SPIx,uint32_t TxData)2518 __STATIC_INLINE void LL_SPI_TransmitData32(SPI_TypeDef *SPIx, uint32_t TxData)
2519 {
2520 *((__IO uint32_t *)&SPIx->TXDR) = TxData;
2521 }
2522
2523 /**
2524 * @brief Set polynomial for CRC calcul
2525 * @rmtoll CRCPOLY CRCPOLY LL_SPI_SetCRCPolynomial
2526 * @param SPIx SPI Instance
2527 * @param CRCPoly 0..0xFFFFFFFF
2528 * @retval None
2529 */
LL_SPI_SetCRCPolynomial(SPI_TypeDef * SPIx,uint32_t CRCPoly)2530 __STATIC_INLINE void LL_SPI_SetCRCPolynomial(SPI_TypeDef *SPIx, uint32_t CRCPoly)
2531 {
2532 WRITE_REG(SPIx->CRCPOLY, CRCPoly);
2533 }
2534
2535 /**
2536 * @brief Get polynomial for CRC calcul
2537 * @rmtoll CRCPOLY CRCPOLY LL_SPI_GetCRCPolynomial
2538 * @param SPIx SPI Instance
2539 * @retval 0..0xFFFFFFFF
2540 */
LL_SPI_GetCRCPolynomial(SPI_TypeDef * SPIx)2541 __STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(SPI_TypeDef *SPIx)
2542 {
2543 return (uint32_t)(READ_REG(SPIx->CRCPOLY));
2544 }
2545
2546 /**
2547 * @brief Set the underrun pattern
2548 * @rmtoll UDRDR UDRDR LL_SPI_SetUDRPattern
2549 * @param SPIx SPI Instance
2550 * @param Pattern 0..0xFFFFFFFF
2551 * @retval None
2552 */
LL_SPI_SetUDRPattern(SPI_TypeDef * SPIx,uint32_t Pattern)2553 __STATIC_INLINE void LL_SPI_SetUDRPattern(SPI_TypeDef *SPIx, uint32_t Pattern)
2554 {
2555 WRITE_REG(SPIx->UDRDR, Pattern);
2556 }
2557
2558 /**
2559 * @brief Get the underrun pattern
2560 * @rmtoll UDRDR UDRDR LL_SPI_GetUDRPattern
2561 * @param SPIx SPI Instance
2562 * @retval 0..0xFFFFFFFF
2563 */
LL_SPI_GetUDRPattern(SPI_TypeDef * SPIx)2564 __STATIC_INLINE uint32_t LL_SPI_GetUDRPattern(SPI_TypeDef *SPIx)
2565 {
2566 return (uint32_t)(READ_REG(SPIx->UDRDR));
2567 }
2568
2569 /**
2570 * @brief Get Rx CRC
2571 * @rmtoll RXCRCR RXCRC LL_SPI_GetRxCRC
2572 * @param SPIx SPI Instance
2573 * @retval 0..0xFFFFFFFF
2574 */
LL_SPI_GetRxCRC(SPI_TypeDef * SPIx)2575 __STATIC_INLINE uint32_t LL_SPI_GetRxCRC(SPI_TypeDef *SPIx)
2576 {
2577 return (uint32_t)(READ_REG(SPIx->RXCRC));
2578 }
2579
2580 /**
2581 * @brief Get Tx CRC
2582 * @rmtoll TXCRCR TXCRC LL_SPI_GetTxCRC
2583 * @param SPIx SPI Instance
2584 * @retval 0..0xFFFFFFFF
2585 */
LL_SPI_GetTxCRC(SPI_TypeDef * SPIx)2586 __STATIC_INLINE uint32_t LL_SPI_GetTxCRC(SPI_TypeDef *SPIx)
2587 {
2588 return (uint32_t)(READ_REG(SPIx->TXCRC));
2589 }
2590
2591 /**
2592 * @}
2593 */
2594
2595 #if defined(USE_FULL_LL_DRIVER)
2596 /** @defgroup SPI_LL_EF_Init Initialization and de-initialization functions
2597 * @{
2598 */
2599
2600 ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx);
2601 ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct);
2602 void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct);
2603
2604 /**
2605 * @}
2606 */
2607 #endif /* USE_FULL_LL_DRIVER */
2608 /**
2609 * @}
2610 */
2611
2612 /** @defgroup I2S_LL I2S
2613 * @{
2614 */
2615
2616 /* Private variables ---------------------------------------------------------*/
2617 /* Private constants ---------------------------------------------------------*/
2618 /* Private macros ------------------------------------------------------------*/
2619
2620 /* Exported types ------------------------------------------------------------*/
2621 #if defined(USE_FULL_LL_DRIVER)
2622 /** @defgroup I2S_LL_ES_INIT I2S Exported Init structure
2623 * @{
2624 */
2625
2626 /**
2627 * @brief I2S Init structure definition
2628 */
2629
2630 typedef struct
2631 {
2632 uint32_t Mode; /*!< Specifies the I2S operating mode.
2633 This parameter can be a value of @ref I2S_LL_EC_MODE
2634
2635 This feature can be modified afterwards using unitary function
2636 @ref LL_I2S_SetTransferMode().*/
2637
2638 uint32_t Standard; /*!< Specifies the standard used for the I2S communication.
2639 This parameter can be a value of @ref I2S_LL_EC_STANDARD
2640
2641 This feature can be modified afterwards using unitary function
2642 @ref LL_I2S_SetStandard().*/
2643
2644
2645 uint32_t DataFormat; /*!< Specifies the data format for the I2S communication.
2646 This parameter can be a value of @ref I2S_LL_EC_DATA_FORMAT
2647
2648 This feature can be modified afterwards using unitary function
2649 @ref LL_I2S_SetDataFormat().*/
2650
2651
2652 uint32_t MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.
2653 This parameter can be a value of @ref I2S_LL_EC_MCLK_OUTPUT
2654
2655 This feature can be modified afterwards using unitary functions
2656 @ref LL_I2S_EnableMasterClock() or @ref LL_I2S_DisableMasterClock.*/
2657
2658
2659 uint32_t AudioFreq; /*!< Specifies the frequency selected for the I2S communication.
2660 This parameter can be a value of @ref I2S_LL_EC_AUDIO_FREQ
2661
2662 Audio Frequency can be modified afterwards using Reference manual formulas
2663 to calculate Prescaler Linear, Parity and unitary functions
2664 @ref LL_I2S_SetPrescalerLinear() and @ref LL_I2S_SetPrescalerParity()
2665 to set it.*/
2666
2667
2668 uint32_t ClockPolarity; /*!< Specifies the idle state of the I2S clock.
2669 This parameter can be a value of @ref I2S_LL_EC_POLARITY
2670
2671 This feature can be modified afterwards using unitary function
2672 @ref LL_I2S_SetClockPolarity().*/
2673
2674 } LL_I2S_InitTypeDef;
2675
2676 /**
2677 * @}
2678 */
2679 #endif /*USE_FULL_LL_DRIVER*/
2680
2681 /* Exported constants --------------------------------------------------------*/
2682 /** @defgroup I2S_LL_Exported_Constants I2S Exported Constants
2683 * @{
2684 */
2685
2686 /** @defgroup I2S_LL_EC_DATA_FORMAT Data Format
2687 * @{
2688 */
2689 #define LL_I2S_DATAFORMAT_16B (0x00000000UL)
2690 #define LL_I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN)
2691 #define LL_I2S_DATAFORMAT_24B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0)
2692 #define LL_I2S_DATAFORMAT_24B_LEFT_ALIGNED (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0 | SPI_I2SCFGR_DATFMT)
2693 #define LL_I2S_DATAFORMAT_32B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1)
2694 /**
2695 * @}
2696 */
2697
2698 /** @defgroup I2S_LL_EC_CHANNEL_LENGTH_TYPE Type of Channel Length
2699 * @{
2700 */
2701 #define LL_I2S_SLAVE_VARIABLE_CH_LENGTH (0x00000000UL)
2702 #define LL_I2S_SLAVE_FIXED_CH_LENGTH (SPI_I2SCFGR_FIXCH)
2703 /**
2704 * @}
2705 */
2706
2707 /** @defgroup I2S_LL_EC_POLARITY Clock Polarity
2708 * @{
2709 */
2710 #define LL_I2S_POLARITY_LOW (0x00000000UL)
2711 #define LL_I2S_POLARITY_HIGH (SPI_I2SCFGR_CKPOL)
2712 /**
2713 * @}
2714 */
2715
2716 /** @defgroup I2S_LL_EC_STANDARD I2S Standard
2717 * @{
2718 */
2719 #define LL_I2S_STANDARD_PHILIPS (0x00000000UL)
2720 #define LL_I2S_STANDARD_MSB (SPI_I2SCFGR_I2SSTD_0)
2721 #define LL_I2S_STANDARD_LSB (SPI_I2SCFGR_I2SSTD_1)
2722 #define LL_I2S_STANDARD_PCM_SHORT (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1)
2723 #define LL_I2S_STANDARD_PCM_LONG (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1 | SPI_I2SCFGR_PCMSYNC)
2724 /**
2725 * @}
2726 */
2727
2728 /** @defgroup I2S_LL_EC_MODE Operation Mode
2729 * @{
2730 */
2731 #define LL_I2S_MODE_SLAVE_TX (0x00000000UL)
2732 #define LL_I2S_MODE_SLAVE_RX (SPI_I2SCFGR_I2SCFG_0)
2733 #define LL_I2S_MODE_SLAVE_FULL_DUPLEX (SPI_I2SCFGR_I2SCFG_2)
2734 #define LL_I2S_MODE_MASTER_TX (SPI_I2SCFGR_I2SCFG_1)
2735 #define LL_I2S_MODE_MASTER_RX (SPI_I2SCFGR_I2SCFG_1 | SPI_I2SCFGR_I2SCFG_0)
2736 #define LL_I2S_MODE_MASTER_FULL_DUPLEX (SPI_I2SCFGR_I2SCFG_2 | SPI_I2SCFGR_I2SCFG_0)
2737 /**
2738 * @}
2739 */
2740
2741 /** @defgroup I2S_LL_EC_PRESCALER_PARITY Prescaler Factor
2742 * @{
2743 */
2744 #define LL_I2S_PRESCALER_PARITY_EVEN (0x00000000UL) /*!< Odd factor: Real divider value is = I2SDIV * 2 */
2745 #define LL_I2S_PRESCALER_PARITY_ODD (0x00000001UL) /*!< Odd factor: Real divider value is = (I2SDIV * 2)+1 */
2746 /**
2747 * @}
2748 */
2749
2750 /** @defgroup I2S_LL_EC_FIFO_TH FIFO Threshold Level
2751 * @{
2752 */
2753 #define LL_I2S_FIFO_TH_01DATA (LL_SPI_FIFO_TH_01DATA)
2754 #define LL_I2S_FIFO_TH_02DATA (LL_SPI_FIFO_TH_02DATA)
2755 #define LL_I2S_FIFO_TH_03DATA (LL_SPI_FIFO_TH_03DATA)
2756 #define LL_I2S_FIFO_TH_04DATA (LL_SPI_FIFO_TH_04DATA)
2757 #define LL_I2S_FIFO_TH_05DATA (LL_SPI_FIFO_TH_05DATA)
2758 #define LL_I2S_FIFO_TH_06DATA (LL_SPI_FIFO_TH_06DATA)
2759 #define LL_I2S_FIFO_TH_07DATA (LL_SPI_FIFO_TH_07DATA)
2760 #define LL_I2S_FIFO_TH_08DATA (LL_SPI_FIFO_TH_08DATA)
2761 /**
2762 * @}
2763 */
2764
2765 /** @defgroup I2S_LL_EC_BIT_ORDER Transmission Bit Order
2766 * @{
2767 */
2768 #define LL_I2S_LSB_FIRST (LL_SPI_LSB_FIRST)
2769 #define LL_I2S_MSB_FIRST (LL_SPI_MSB_FIRST)
2770 /**
2771 * @}
2772 */
2773
2774 #if defined(USE_FULL_LL_DRIVER)
2775
2776 /** @defgroup I2S_LL_EC_MCLK_OUTPUT MCLK Output
2777 * @{
2778 */
2779 #define LL_I2S_MCLK_OUTPUT_DISABLE (0x00000000UL)
2780 #define LL_I2S_MCLK_OUTPUT_ENABLE (SPI_I2SCFGR_MCKOE)
2781 /**
2782 * @}
2783 */
2784
2785 /** @defgroup I2S_LL_EC_AUDIO_FREQ Audio Frequency
2786 * @{
2787 */
2788
2789 #define LL_I2S_AUDIOFREQ_192K 192000UL /*!< Audio Frequency configuration 192000 Hz */
2790 #define LL_I2S_AUDIOFREQ_96K 96000UL /*!< Audio Frequency configuration 96000 Hz */
2791 #define LL_I2S_AUDIOFREQ_48K 48000UL /*!< Audio Frequency configuration 48000 Hz */
2792 #define LL_I2S_AUDIOFREQ_44K 44100UL /*!< Audio Frequency configuration 44100 Hz */
2793 #define LL_I2S_AUDIOFREQ_32K 32000UL /*!< Audio Frequency configuration 32000 Hz */
2794 #define LL_I2S_AUDIOFREQ_22K 22050UL /*!< Audio Frequency configuration 22050 Hz */
2795 #define LL_I2S_AUDIOFREQ_16K 16000UL /*!< Audio Frequency configuration 16000 Hz */
2796 #define LL_I2S_AUDIOFREQ_11K 11025UL /*!< Audio Frequency configuration 11025 Hz */
2797 #define LL_I2S_AUDIOFREQ_8K 8000UL /*!< Audio Frequency configuration 8000 Hz */
2798 #define LL_I2S_AUDIOFREQ_DEFAULT 0UL /*!< Audio Freq not specified. Register I2SDIV = 0 */
2799 /**
2800 * @}
2801 */
2802 #endif /* USE_FULL_LL_DRIVER */
2803
2804 /**
2805 * @}
2806 */
2807
2808 /* Exported macro ------------------------------------------------------------*/
2809 /** @defgroup I2S_LL_Exported_Macros I2S Exported Macros
2810 * @{
2811 */
2812
2813 /** @defgroup I2S_LL_EM_WRITE_READ Common Write and read registers Macros
2814 * @{
2815 */
2816
2817 /**
2818 * @brief Write a value in I2S register
2819 * @param __INSTANCE__ I2S Instance
2820 * @param __REG__ Register to be written
2821 * @param __VALUE__ Value to be written in the register
2822 * @retval None
2823 */
2824 #define LL_I2S_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
2825
2826 /**
2827 * @brief Read a value in I2S register
2828 * @param __INSTANCE__ I2S Instance
2829 * @param __REG__ Register to be read
2830 * @retval Register value
2831 */
2832 #define LL_I2S_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
2833 /**
2834 * @}
2835 */
2836
2837 /**
2838 * @}
2839 */
2840
2841
2842 /* Exported functions --------------------------------------------------------*/
2843
2844 /** @defgroup I2S_LL_Exported_Functions I2S Exported Functions
2845 * @{
2846 */
2847
2848 /** @defgroup I2S_LL_EF_Configuration Configuration
2849 * @{
2850 */
2851
2852 /**
2853 * @brief Set I2S Data frame format
2854 * @rmtoll I2SCFGR DATLEN LL_I2S_SetDataFormat\n
2855 * I2SCFGR CHLEN LL_I2S_SetDataFormat\n
2856 * I2SCFGR DATFMT LL_I2S_SetDataFormat
2857 * @param SPIx SPI Handle
2858 * @param DataLength This parameter can be one of the following values:
2859 * @arg @ref LL_I2S_DATAFORMAT_16B
2860 * @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED
2861 * @arg @ref LL_I2S_DATAFORMAT_24B
2862 * @arg @ref LL_I2S_DATAFORMAT_24B_LEFT_ALIGNED
2863 * @arg @ref LL_I2S_DATAFORMAT_32B
2864 * @retval None
2865 */
LL_I2S_SetDataFormat(SPI_TypeDef * SPIx,uint32_t DataLength)2866 __STATIC_INLINE void LL_I2S_SetDataFormat(SPI_TypeDef *SPIx, uint32_t DataLength)
2867 {
2868 MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATFMT, DataLength);
2869 }
2870
2871 /**
2872 * @brief Get I2S Data frame format
2873 * @rmtoll I2SCFGR DATLEN LL_I2S_GetDataFormat\n
2874 * I2SCFGR CHLEN LL_I2S_GetDataFormat\n
2875 * I2SCFGR DATFMT LL_I2S_GetDataFormat
2876 * @param SPIx SPI Handle
2877 * @retval Return value can be one of the following values:
2878 * @arg @ref LL_I2S_DATAFORMAT_16B
2879 * @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED
2880 * @arg @ref LL_I2S_DATAFORMAT_24B
2881 * @arg @ref LL_I2S_DATAFORMAT_24B_LEFT_ALIGNED
2882 * @arg @ref LL_I2S_DATAFORMAT_32B
2883 */
LL_I2S_GetDataFormat(SPI_TypeDef * SPIx)2884 __STATIC_INLINE uint32_t LL_I2S_GetDataFormat(SPI_TypeDef *SPIx)
2885 {
2886 return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATFMT));
2887 }
2888
2889 /**
2890 * @brief Set I2S Channel Length Type
2891 * @note This feature is useful with SLAVE only
2892 * @rmtoll I2SCFGR FIXCH LL_I2S_SetChannelLengthType
2893 * @param SPIx SPI Handle
2894 * @param ChannelLengthType This parameter can be one of the following values:
2895 * @arg @ref LL_I2S_SLAVE_VARIABLE_CH_LENGTH
2896 * @arg @ref LL_I2S_SLAVE_FIXED_CH_LENGTH
2897 * @retval None
2898 */
LL_I2S_SetChannelLengthType(SPI_TypeDef * SPIx,uint32_t ChannelLengthType)2899 __STATIC_INLINE void LL_I2S_SetChannelLengthType(SPI_TypeDef *SPIx, uint32_t ChannelLengthType)
2900 {
2901 MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_FIXCH, ChannelLengthType);
2902 }
2903
2904 /**
2905 * @brief Get I2S Channel Length Type
2906 * @note This feature is useful with SLAVE only
2907 * @rmtoll I2SCFGR FIXCH LL_I2S_GetChannelLengthType
2908 * @param SPIx SPI Handle
2909 * @retval Return value can be one of the following values:
2910 * @arg @ref LL_I2S_SLAVE_VARIABLE_CH_LENGTH
2911 * @arg @ref LL_I2S_SLAVE_FIXED_CH_LENGTH
2912 */
LL_I2S_GetChannelLengthType(SPI_TypeDef * SPIx)2913 __STATIC_INLINE uint32_t LL_I2S_GetChannelLengthType(SPI_TypeDef *SPIx)
2914 {
2915 return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_FIXCH));
2916 }
2917
2918 /**
2919 * @brief Invert the default polarity of WS signal
2920 * @rmtoll I2SCFGR WSINV LL_I2S_EnableWordSelectInversion
2921 * @param SPIx SPI Handle
2922 * @retval None
2923 */
LL_I2S_EnableWordSelectInversion(SPI_TypeDef * SPIx)2924 __STATIC_INLINE void LL_I2S_EnableWordSelectInversion(SPI_TypeDef *SPIx)
2925 {
2926 SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_WSINV);
2927 }
2928
2929 /**
2930 * @brief Use the default polarity of WS signal
2931 * @rmtoll I2SCFGR WSINV LL_I2S_DisableWordSelectInversion
2932 * @param SPIx SPI Handle
2933 * @retval None
2934 */
LL_I2S_DisableWordSelectInversion(SPI_TypeDef * SPIx)2935 __STATIC_INLINE void LL_I2S_DisableWordSelectInversion(SPI_TypeDef *SPIx)
2936 {
2937 CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_WSINV);
2938 }
2939
2940 /**
2941 * @brief Check if polarity of WS signal is inverted
2942 * @rmtoll I2SCFGR WSINV LL_I2S_IsEnabledWordSelectInversion
2943 * @param SPIx SPI Handle
2944 * @retval State of bit (1 or 0)
2945 */
LL_I2S_IsEnabledWordSelectInversion(SPI_TypeDef * SPIx)2946 __STATIC_INLINE uint32_t LL_I2S_IsEnabledWordSelectInversion(SPI_TypeDef *SPIx)
2947 {
2948 return ((READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_WSINV) == (SPI_I2SCFGR_WSINV)) ? 1UL : 0UL);
2949 }
2950
2951 /**
2952 * @brief Set 2S Clock Polarity
2953 * @rmtoll I2SCFGR CKPOL LL_I2S_SetClockPolarity
2954 * @param SPIx SPI Handle
2955 * @param ClockPolarity This parameter can be one of the following values:
2956 * @arg @ref LL_I2S_POLARITY_LOW
2957 * @arg @ref LL_I2S_POLARITY_HIGH
2958 * @retval None
2959 */
LL_I2S_SetClockPolarity(SPI_TypeDef * SPIx,uint32_t ClockPolarity)2960 __STATIC_INLINE void LL_I2S_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
2961 {
2962 MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_CKPOL, ClockPolarity);
2963 }
2964
2965 /**
2966 * @brief Get 2S Clock Polarity
2967 * @rmtoll I2SCFGR CKPOL LL_I2S_GetClockPolarity
2968 * @param SPIx SPI Handle
2969 * @retval Return value can be one of the following values:
2970 * @arg @ref LL_I2S_POLARITY_LOW
2971 * @arg @ref LL_I2S_POLARITY_HIGH
2972 */
LL_I2S_GetClockPolarity(SPI_TypeDef * SPIx)2973 __STATIC_INLINE uint32_t LL_I2S_GetClockPolarity(SPI_TypeDef *SPIx)
2974 {
2975 return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_CKPOL));
2976 }
2977
2978 /**
2979 * @brief Set I2S standard
2980 * @rmtoll I2SCFGR I2SSTD LL_I2S_SetStandard\n
2981 * I2SCFGR PCMSYNC LL_I2S_SetStandard
2982 * @param SPIx SPI Handle
2983 * @param Standard This parameter can be one of the following values:
2984 * @arg @ref LL_I2S_STANDARD_PHILIPS
2985 * @arg @ref LL_I2S_STANDARD_MSB
2986 * @arg @ref LL_I2S_STANDARD_LSB
2987 * @arg @ref LL_I2S_STANDARD_PCM_SHORT
2988 * @arg @ref LL_I2S_STANDARD_PCM_LONG
2989 * @retval None
2990 */
LL_I2S_SetStandard(SPI_TypeDef * SPIx,uint32_t Standard)2991 __STATIC_INLINE void LL_I2S_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
2992 {
2993 MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC, Standard);
2994 }
2995
2996 /**
2997 * @brief Get I2S standard
2998 * @rmtoll I2SCFGR I2SSTD LL_I2S_GetStandard\n
2999 * I2SCFGR PCMSYNC LL_I2S_GetStandard
3000 * @param SPIx SPI Handle
3001 * @retval Return value can be one of the following values:
3002 * @arg @ref LL_I2S_STANDARD_PHILIPS
3003 * @arg @ref LL_I2S_STANDARD_MSB
3004 * @arg @ref LL_I2S_STANDARD_LSB
3005 * @arg @ref LL_I2S_STANDARD_PCM_SHORT
3006 * @arg @ref LL_I2S_STANDARD_PCM_LONG
3007 */
LL_I2S_GetStandard(SPI_TypeDef * SPIx)3008 __STATIC_INLINE uint32_t LL_I2S_GetStandard(SPI_TypeDef *SPIx)
3009 {
3010 return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC));
3011 }
3012
3013 /**
3014 * @brief Set I2S config
3015 * @rmtoll I2SCFGR I2SCFG LL_I2S_SetTransferMode
3016 * @param SPIx SPI Handle
3017 * @param Standard This parameter can be one of the following values:
3018 * @arg @ref LL_I2S_MODE_SLAVE_TX
3019 * @arg @ref LL_I2S_MODE_SLAVE_RX
3020 * @arg @ref LL_I2S_MODE_SLAVE_FULL_DUPLEX
3021 * @arg @ref LL_I2S_MODE_MASTER_TX
3022 * @arg @ref LL_I2S_MODE_MASTER_RX
3023 * @arg @ref LL_I2S_MODE_MASTER_FULL_DUPLEX
3024 * @retval None
3025 */
LL_I2S_SetTransferMode(SPI_TypeDef * SPIx,uint32_t Standard)3026 __STATIC_INLINE void LL_I2S_SetTransferMode(SPI_TypeDef *SPIx, uint32_t Standard)
3027 {
3028 MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG, Standard);
3029 }
3030
3031 /**
3032 * @brief Get I2S config
3033 * @rmtoll I2SCFGR I2SCFG LL_I2S_GetTransferMode
3034 * @param SPIx SPI Handle
3035 * @retval Return value can be one of the following values:
3036 * @arg @ref LL_I2S_MODE_SLAVE_TX
3037 * @arg @ref LL_I2S_MODE_SLAVE_RX
3038 * @arg @ref LL_I2S_MODE_SLAVE_FULL_DUPLEX
3039 * @arg @ref LL_I2S_MODE_MASTER_TX
3040 * @arg @ref LL_I2S_MODE_MASTER_RX
3041 * @arg @ref LL_I2S_MODE_MASTER_FULL_DUPLEX
3042 */
LL_I2S_GetTransferMode(SPI_TypeDef * SPIx)3043 __STATIC_INLINE uint32_t LL_I2S_GetTransferMode(SPI_TypeDef *SPIx)
3044 {
3045 return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG));
3046 }
3047
3048 /**
3049 * @brief Select I2S mode and Enable I2S peripheral
3050 * @rmtoll I2SCFGR I2SMOD LL_I2S_Enable\n
3051 * CR1 SPE LL_I2S_Enable
3052 * @param SPIx SPI Handle
3053 * @retval None
3054 */
LL_I2S_Enable(SPI_TypeDef * SPIx)3055 __STATIC_INLINE void LL_I2S_Enable(SPI_TypeDef *SPIx)
3056 {
3057 SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD);
3058 SET_BIT(SPIx->CR1, SPI_CR1_SPE);
3059 }
3060
3061 /**
3062 * @brief Disable I2S peripheral and disable I2S mode
3063 * @rmtoll CR1 SPE LL_I2S_Disable\n
3064 * I2SCFGR I2SMOD LL_I2S_Disable
3065 * @param SPIx SPI Handle
3066 * @retval None
3067 */
LL_I2S_Disable(SPI_TypeDef * SPIx)3068 __STATIC_INLINE void LL_I2S_Disable(SPI_TypeDef *SPIx)
3069 {
3070 CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
3071 CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD);
3072 }
3073
3074 /**
3075 * @brief Swap the SDO and SDI pin
3076 * @note This configuration can not be changed when I2S is enabled.
3077 * @rmtoll CFG2 IOSWP LL_I2S_EnableIOSwap
3078 * @param SPIx SPI Instance
3079 * @retval None
3080 */
LL_I2S_EnableIOSwap(SPI_TypeDef * SPIx)3081 __STATIC_INLINE void LL_I2S_EnableIOSwap(SPI_TypeDef *SPIx)
3082 {
3083 LL_SPI_EnableIOSwap(SPIx);
3084 }
3085
3086 /**
3087 * @brief Restore default function for SDO and SDI pin
3088 * @note This configuration can not be changed when I2S is enabled.
3089 * @rmtoll CFG2 IOSWP LL_I2S_DisableIOSwap
3090 * @param SPIx SPI Instance
3091 * @retval None
3092 */
LL_I2S_DisableIOSwap(SPI_TypeDef * SPIx)3093 __STATIC_INLINE void LL_I2S_DisableIOSwap(SPI_TypeDef *SPIx)
3094 {
3095 LL_SPI_DisableIOSwap(SPIx);
3096 }
3097
3098 /**
3099 * @brief Check if SDO and SDI pin are swapped
3100 * @rmtoll CFG2 IOSWP LL_I2S_IsEnabledIOSwap
3101 * @param SPIx SPI Instance
3102 * @retval State of bit (1 or 0)
3103 */
LL_I2S_IsEnabledIOSwap(SPI_TypeDef * SPIx)3104 __STATIC_INLINE uint32_t LL_I2S_IsEnabledIOSwap(SPI_TypeDef *SPIx)
3105 {
3106 return LL_SPI_IsEnabledIOSwap(SPIx);
3107 }
3108
3109 /**
3110 * @brief Enable GPIO control
3111 * @note This configuration can not be changed when I2S is enabled.
3112 * @rmtoll CFG2 AFCNTR LL_I2S_EnableGPIOControl
3113 * @param SPIx SPI Instance
3114 * @retval None
3115 */
LL_I2S_EnableGPIOControl(SPI_TypeDef * SPIx)3116 __STATIC_INLINE void LL_I2S_EnableGPIOControl(SPI_TypeDef *SPIx)
3117 {
3118 LL_SPI_EnableGPIOControl(SPIx);
3119 }
3120
3121 /**
3122 * @brief Disable GPIO control
3123 * @note This configuration can not be changed when I2S is enabled.
3124 * @rmtoll CFG2 AFCNTR LL_I2S_DisableGPIOControl
3125 * @param SPIx SPI Instance
3126 * @retval None
3127 */
LL_I2S_DisableGPIOControl(SPI_TypeDef * SPIx)3128 __STATIC_INLINE void LL_I2S_DisableGPIOControl(SPI_TypeDef *SPIx)
3129 {
3130 LL_SPI_DisableGPIOControl(SPIx);
3131 }
3132
3133 /**
3134 * @brief Check if GPIO control is active
3135 * @rmtoll CFG2 AFCNTR LL_I2S_IsEnabledGPIOControl
3136 * @param SPIx SPI Instance
3137 * @retval State of bit (1 or 0)
3138 */
LL_I2S_IsEnabledGPIOControl(SPI_TypeDef * SPIx)3139 __STATIC_INLINE uint32_t LL_I2S_IsEnabledGPIOControl(SPI_TypeDef *SPIx)
3140 {
3141 return LL_SPI_IsEnabledGPIOControl(SPIx);
3142 }
3143
3144 /**
3145 * @brief Lock the AF configuration of associated IOs
3146 * @note Once this bit is set, the SPI_CFG2 register content can not be modified until a hardware reset occurs.
3147 * The reset of the IOLock bit is done by hardware. for that, LL_SPI_DisableIOLock can not exist.
3148 * @rmtoll CR1 IOLOCK LL_SPI_EnableIOLock
3149 * @param SPIx SPI Instance
3150 * @retval None
3151 */
LL_I2S_EnableIOLock(SPI_TypeDef * SPIx)3152 __STATIC_INLINE void LL_I2S_EnableIOLock(SPI_TypeDef *SPIx)
3153 {
3154 LL_SPI_EnableIOLock(SPIx);
3155 }
3156
3157 /**
3158 * @brief Check if the the SPI_CFG2 register is locked
3159 * @rmtoll CR1 IOLOCK LL_I2S_IsEnabledIOLock
3160 * @param SPIx SPI Instance
3161 * @retval State of bit (1 or 0)
3162 */
LL_I2S_IsEnabledIOLock(SPI_TypeDef * SPIx)3163 __STATIC_INLINE uint32_t LL_I2S_IsEnabledIOLock(SPI_TypeDef *SPIx)
3164 {
3165 return LL_SPI_IsEnabledIOLock(SPIx);
3166 }
3167
3168 /**
3169 * @brief Set Transfer Bit Order
3170 * @note This configuration can not be changed when I2S is enabled.
3171 * @rmtoll CFG2 LSBFRST LL_I2S_SetTransferBitOrder
3172 * @param SPIx SPI Instance
3173 * @param BitOrder This parameter can be one of the following values:
3174 * @arg @ref LL_I2S_LSB_FIRST
3175 * @arg @ref LL_I2S_MSB_FIRST
3176 * @retval None
3177 */
LL_I2S_SetTransferBitOrder(SPI_TypeDef * SPIx,uint32_t BitOrder)3178 __STATIC_INLINE void LL_I2S_SetTransferBitOrder(SPI_TypeDef *SPIx, uint32_t BitOrder)
3179 {
3180 LL_SPI_SetTransferBitOrder(SPIx, BitOrder);
3181 }
3182 /**
3183 * @brief Get Transfer Bit Order
3184 * @rmtoll CFG2 LSBFRST LL_I2S_GetTransferBitOrder
3185 * @param SPIx SPI Instance
3186 * @retval Returned value can be one of the following values:
3187 * @arg @ref LL_I2S_LSB_FIRST
3188 * @arg @ref LL_I2S_MSB_FIRST
3189 */
LL_I2S_GetTransferBitOrder(SPI_TypeDef * SPIx)3190 __STATIC_INLINE uint32_t LL_I2S_GetTransferBitOrder(SPI_TypeDef *SPIx)
3191 {
3192 return LL_SPI_GetTransferBitOrder(SPIx);
3193 }
3194
3195 /**
3196 * @brief Start effective transfer on wire
3197 * @rmtoll CR1 CSTART LL_I2S_StartTransfer
3198 * @param SPIx SPI Instance
3199 * @retval None
3200 */
LL_I2S_StartTransfer(SPI_TypeDef * SPIx)3201 __STATIC_INLINE void LL_I2S_StartTransfer(SPI_TypeDef *SPIx)
3202 {
3203 LL_SPI_StartMasterTransfer(SPIx);
3204 }
3205
3206 /**
3207 * @brief Check if there is an unfinished transfer
3208 * @rmtoll CR1 CSTART LL_I2S_IsTransferActive
3209 * @param SPIx SPI Instance
3210 * @retval State of bit (1 or 0)
3211 */
LL_I2S_IsActiveTransfer(SPI_TypeDef * SPIx)3212 __STATIC_INLINE uint32_t LL_I2S_IsActiveTransfer(SPI_TypeDef *SPIx)
3213 {
3214 return LL_SPI_IsActiveMasterTransfer(SPIx);
3215 }
3216
3217 /**
3218 * @brief Set threshold of FIFO that triggers a transfer event
3219 * @note This configuration can not be changed when I2S is enabled.
3220 * @rmtoll CFG1 FTHLV LL_I2S_SetFIFOThreshold
3221 * @param SPIx SPI Instance
3222 * @param Threshold This parameter can be one of the following values:
3223 * @arg @ref LL_I2S_FIFO_TH_01DATA
3224 * @arg @ref LL_I2S_FIFO_TH_02DATA
3225 * @arg @ref LL_I2S_FIFO_TH_03DATA
3226 * @arg @ref LL_I2S_FIFO_TH_04DATA
3227 * @arg @ref LL_I2S_FIFO_TH_05DATA
3228 * @arg @ref LL_I2S_FIFO_TH_06DATA
3229 * @arg @ref LL_I2S_FIFO_TH_07DATA
3230 * @arg @ref LL_I2S_FIFO_TH_08DATA
3231 * @retval None
3232 */
LL_I2S_SetFIFOThreshold(SPI_TypeDef * SPIx,uint32_t Threshold)3233 __STATIC_INLINE void LL_I2S_SetFIFOThreshold(SPI_TypeDef *SPIx, uint32_t Threshold)
3234 {
3235 LL_SPI_SetFIFOThreshold(SPIx, Threshold);
3236 }
3237
3238 /**
3239 * @brief Get threshold of FIFO that triggers a transfer event
3240 * @rmtoll CFG1 FTHLV LL_I2S_GetFIFOThreshold
3241 * @param SPIx SPI Instance
3242 * @retval Returned value can be one of the following values:
3243 * @arg @ref LL_I2S_FIFO_TH_01DATA
3244 * @arg @ref LL_I2S_FIFO_TH_02DATA
3245 * @arg @ref LL_I2S_FIFO_TH_03DATA
3246 * @arg @ref LL_I2S_FIFO_TH_04DATA
3247 * @arg @ref LL_I2S_FIFO_TH_05DATA
3248 * @arg @ref LL_I2S_FIFO_TH_06DATA
3249 * @arg @ref LL_I2S_FIFO_TH_07DATA
3250 * @arg @ref LL_I2S_FIFO_TH_08DATA
3251 */
LL_I2S_GetFIFOThreshold(SPI_TypeDef * SPIx)3252 __STATIC_INLINE uint32_t LL_I2S_GetFIFOThreshold(SPI_TypeDef *SPIx)
3253 {
3254 return LL_SPI_GetFIFOThreshold(SPIx);
3255 }
3256
3257 /**
3258 * @brief Set I2S linear prescaler
3259 * @rmtoll I2SCFGR I2SDIV LL_I2S_SetPrescalerLinear
3260 * @param SPIx SPI Instance
3261 * @param PrescalerLinear Value between Min_Data=0x00 and Max_Data=0xFF
3262 * @note PrescalerLinear '1' is not authorized with parity LL_I2S_PRESCALER_PARITY_ODD
3263 * @retval None
3264 */
LL_I2S_SetPrescalerLinear(SPI_TypeDef * SPIx,uint32_t PrescalerLinear)3265 __STATIC_INLINE void LL_I2S_SetPrescalerLinear(SPI_TypeDef *SPIx, uint32_t PrescalerLinear)
3266 {
3267 MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SDIV, (PrescalerLinear << SPI_I2SCFGR_I2SDIV_Pos));
3268 }
3269
3270 /**
3271 * @brief Get I2S linear prescaler
3272 * @rmtoll I2SCFGR I2SDIV LL_I2S_GetPrescalerLinear
3273 * @param SPIx SPI Instance
3274 * @retval PrescalerLinear Value between Min_Data=0x00 and Max_Data=0xFF
3275 */
LL_I2S_GetPrescalerLinear(SPI_TypeDef * SPIx)3276 __STATIC_INLINE uint32_t LL_I2S_GetPrescalerLinear(SPI_TypeDef *SPIx)
3277 {
3278 return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SDIV) >> SPI_I2SCFGR_I2SDIV_Pos);
3279 }
3280
3281 /**
3282 * @brief Set I2S parity prescaler
3283 * @rmtoll I2SCFGR ODD LL_I2S_SetPrescalerParity
3284 * @param SPIx SPI Instance
3285 * @param PrescalerParity This parameter can be one of the following values:
3286 * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
3287 * @arg @ref LL_I2S_PRESCALER_PARITY_ODD
3288 * @retval None
3289 */
LL_I2S_SetPrescalerParity(SPI_TypeDef * SPIx,uint32_t PrescalerParity)3290 __STATIC_INLINE void LL_I2S_SetPrescalerParity(SPI_TypeDef *SPIx, uint32_t PrescalerParity)
3291 {
3292 MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_ODD, PrescalerParity << SPI_I2SCFGR_ODD_Pos);
3293 }
3294
3295 /**
3296 * @brief Get I2S parity prescaler
3297 * @rmtoll I2SCFGR ODD LL_I2S_GetPrescalerParity
3298 * @param SPIx SPI Instance
3299 * @retval Returned value can be one of the following values:
3300 * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN
3301 * @arg @ref LL_I2S_PRESCALER_PARITY_ODD
3302 */
LL_I2S_GetPrescalerParity(SPI_TypeDef * SPIx)3303 __STATIC_INLINE uint32_t LL_I2S_GetPrescalerParity(SPI_TypeDef *SPIx)
3304 {
3305 return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ODD) >> SPI_I2SCFGR_ODD_Pos);
3306 }
3307
3308 /**
3309 * @brief Enable the Master Clock Output (Pin MCK)
3310 * @rmtoll I2SCFGR MCKOE LL_I2S_EnableMasterClock
3311 * @param SPIx SPI Handle
3312 * @retval None
3313 */
LL_I2S_EnableMasterClock(SPI_TypeDef * SPIx)3314 __STATIC_INLINE void LL_I2S_EnableMasterClock(SPI_TypeDef *SPIx)
3315 {
3316 SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_MCKOE);
3317 }
3318
3319 /**
3320 * @brief Disable the Master Clock Output (Pin MCK)
3321 * @rmtoll I2SCFGR MCKOE LL_I2S_DisableMasterClock
3322 * @param SPIx SPI Handle
3323 * @retval None
3324 */
LL_I2S_DisableMasterClock(SPI_TypeDef * SPIx)3325 __STATIC_INLINE void LL_I2S_DisableMasterClock(SPI_TypeDef *SPIx)
3326 {
3327 CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_MCKOE);
3328 }
3329
3330 /**
3331 * @brief Check if the master clock output (Pin MCK) is enabled
3332 * @rmtoll I2SCFGR MCKOE LL_I2S_IsEnabledMasterClock
3333 * @param SPIx SPI Instance
3334 * @retval State of bit (1 or 0)
3335 */
LL_I2S_IsEnabledMasterClock(SPI_TypeDef * SPIx)3336 __STATIC_INLINE uint32_t LL_I2S_IsEnabledMasterClock(SPI_TypeDef *SPIx)
3337 {
3338 return ((READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_MCKOE) == (SPI_I2SCFGR_MCKOE)) ? 1UL : 0UL);
3339 }
3340
3341 /**
3342 * @}
3343 */
3344
3345
3346 /** @defgroup I2S_LL_EF_FLAG_Management FLAG_Management
3347 * @{
3348 */
3349
3350 /**
3351 * @brief Check if there enough data in FIFO to read a full packet
3352 * @rmtoll SR RXP LL_I2S_IsActiveFlag_RXP
3353 * @param SPIx SPI Instance
3354 * @retval State of bit (1 or 0)
3355 */
LL_I2S_IsActiveFlag_RXP(SPI_TypeDef * SPIx)3356 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_RXP(SPI_TypeDef *SPIx)
3357 {
3358 return LL_SPI_IsActiveFlag_RXP(SPIx);
3359 }
3360
3361 /**
3362 * @brief Check if there enough space in FIFO to hold a full packet
3363 * @rmtoll SR TXP LL_I2S_IsActiveFlag_TXP
3364 * @param SPIx SPI Instance
3365 * @retval State of bit (1 or 0)
3366 */
LL_I2S_IsActiveFlag_TXP(SPI_TypeDef * SPIx)3367 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_TXP(SPI_TypeDef *SPIx)
3368 {
3369 return LL_SPI_IsActiveFlag_TXP(SPIx);
3370 }
3371
3372 /**
3373 * @brief Get Underrun error flag
3374 * @rmtoll SR UDR LL_I2S_IsActiveFlag_UDR
3375 * @param SPIx SPI Instance
3376 * @retval State of bit (1 or 0)
3377 */
LL_I2S_IsActiveFlag_UDR(SPI_TypeDef * SPIx)3378 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_UDR(SPI_TypeDef *SPIx)
3379 {
3380 return LL_SPI_IsActiveFlag_UDR(SPIx);
3381 }
3382
3383 /**
3384 * @brief Get Overrun error flag
3385 * @rmtoll SR OVR LL_I2S_IsActiveFlag_OVR
3386 * @param SPIx SPI Instance
3387 * @retval State of bit (1 or 0).
3388 */
LL_I2S_IsActiveFlag_OVR(SPI_TypeDef * SPIx)3389 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_OVR(SPI_TypeDef *SPIx)
3390 {
3391 return LL_SPI_IsActiveFlag_OVR(SPIx);
3392 }
3393
3394 /**
3395 * @brief Get TI Frame format error flag
3396 * @rmtoll SR TIFRE LL_I2S_IsActiveFlag_FRE
3397 * @param SPIx SPI Instance
3398 * @retval State of bit (1 or 0).
3399 */
LL_I2S_IsActiveFlag_FRE(SPI_TypeDef * SPIx)3400 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_FRE(SPI_TypeDef *SPIx)
3401 {
3402 return LL_SPI_IsActiveFlag_FRE(SPIx);
3403 }
3404
3405 /**
3406 * @brief Clear Underrun error flag
3407 * @rmtoll IFCR UDRC LL_I2S_ClearFlag_UDR
3408 * @param SPIx SPI Instance
3409 * @retval None
3410 */
LL_I2S_ClearFlag_UDR(SPI_TypeDef * SPIx)3411 __STATIC_INLINE void LL_I2S_ClearFlag_UDR(SPI_TypeDef *SPIx)
3412 {
3413 LL_SPI_ClearFlag_UDR(SPIx);
3414 }
3415
3416 /**
3417 * @brief Clear Overrun error flag
3418 * @rmtoll IFCR OVRC LL_I2S_ClearFlag_OVR
3419 * @param SPIx SPI Instance
3420 * @retval None
3421 */
LL_I2S_ClearFlag_OVR(SPI_TypeDef * SPIx)3422 __STATIC_INLINE void LL_I2S_ClearFlag_OVR(SPI_TypeDef *SPIx)
3423 {
3424 LL_SPI_ClearFlag_OVR(SPIx);
3425 }
3426
3427 /**
3428 * @brief Clear Frame format error flag
3429 * @rmtoll IFCR TIFREC LL_I2S_ClearFlag_FRE
3430 * @param SPIx SPI Instance
3431 * @retval None
3432 */
LL_I2S_ClearFlag_FRE(SPI_TypeDef * SPIx)3433 __STATIC_INLINE void LL_I2S_ClearFlag_FRE(SPI_TypeDef *SPIx)
3434 {
3435 LL_SPI_ClearFlag_FRE(SPIx);
3436 }
3437
3438 /**
3439 * @}
3440 */
3441
3442 /** @defgroup I2S_LL_EF_IT_Management IT_Management
3443 * @{
3444 */
3445
3446 /**
3447 * @brief Enable Rx Packet available IT
3448 * @rmtoll IER RXPIE LL_I2S_EnableIT_RXP
3449 * @param SPIx SPI Instance
3450 * @retval None
3451 */
LL_I2S_EnableIT_RXP(SPI_TypeDef * SPIx)3452 __STATIC_INLINE void LL_I2S_EnableIT_RXP(SPI_TypeDef *SPIx)
3453 {
3454 LL_SPI_EnableIT_RXP(SPIx);
3455 }
3456
3457 /**
3458 * @brief Enable Tx Packet space available IT
3459 * @rmtoll IER TXPIE LL_I2S_EnableIT_TXP
3460 * @param SPIx SPI Instance
3461 * @retval None
3462 */
LL_I2S_EnableIT_TXP(SPI_TypeDef * SPIx)3463 __STATIC_INLINE void LL_I2S_EnableIT_TXP(SPI_TypeDef *SPIx)
3464 {
3465 LL_SPI_EnableIT_TXP(SPIx);
3466 }
3467
3468 /**
3469 * @brief Enable Underrun IT
3470 * @rmtoll IER UDRIE LL_I2S_EnableIT_UDR
3471 * @param SPIx SPI Instance
3472 * @retval None
3473 */
LL_I2S_EnableIT_UDR(SPI_TypeDef * SPIx)3474 __STATIC_INLINE void LL_I2S_EnableIT_UDR(SPI_TypeDef *SPIx)
3475 {
3476 LL_SPI_EnableIT_UDR(SPIx);
3477 }
3478
3479 /**
3480 * @brief Enable Overrun IT
3481 * @rmtoll IER OVRIE LL_I2S_EnableIT_OVR
3482 * @param SPIx SPI Instance
3483 * @retval None
3484 */
LL_I2S_EnableIT_OVR(SPI_TypeDef * SPIx)3485 __STATIC_INLINE void LL_I2S_EnableIT_OVR(SPI_TypeDef *SPIx)
3486 {
3487 LL_SPI_EnableIT_OVR(SPIx);
3488 }
3489
3490 /**
3491 * @brief Enable TI Frame Format Error IT
3492 * @rmtoll IER TIFREIE LL_I2S_EnableIT_FRE
3493 * @param SPIx SPI Instance
3494 * @retval None
3495 */
LL_I2S_EnableIT_FRE(SPI_TypeDef * SPIx)3496 __STATIC_INLINE void LL_I2S_EnableIT_FRE(SPI_TypeDef *SPIx)
3497 {
3498 LL_SPI_EnableIT_FRE(SPIx);
3499 }
3500
3501 /**
3502 * @brief Disable Rx Packet available IT
3503 * @rmtoll IER RXPIE LL_I2S_DisableIT_RXP
3504 * @param SPIx SPI Instance
3505 * @retval None
3506 */
LL_I2S_DisableIT_RXP(SPI_TypeDef * SPIx)3507 __STATIC_INLINE void LL_I2S_DisableIT_RXP(SPI_TypeDef *SPIx)
3508 {
3509 LL_SPI_DisableIT_RXP(SPIx);
3510 }
3511
3512 /**
3513 * @brief Disable Tx Packet space available IT
3514 * @rmtoll IER TXPIE LL_I2S_DisableIT_TXP
3515 * @param SPIx SPI Instance
3516 * @retval None
3517 */
LL_I2S_DisableIT_TXP(SPI_TypeDef * SPIx)3518 __STATIC_INLINE void LL_I2S_DisableIT_TXP(SPI_TypeDef *SPIx)
3519 {
3520 LL_SPI_DisableIT_TXP(SPIx);
3521 }
3522
3523 /**
3524 * @brief Disable Underrun IT
3525 * @rmtoll IER UDRIE LL_I2S_DisableIT_UDR
3526 * @param SPIx SPI Instance
3527 * @retval None
3528 */
LL_I2S_DisableIT_UDR(SPI_TypeDef * SPIx)3529 __STATIC_INLINE void LL_I2S_DisableIT_UDR(SPI_TypeDef *SPIx)
3530 {
3531 LL_SPI_DisableIT_UDR(SPIx);
3532 }
3533
3534 /**
3535 * @brief Disable Overrun IT
3536 * @rmtoll IER OVRIE LL_I2S_DisableIT_OVR
3537 * @param SPIx SPI Instance
3538 * @retval None
3539 */
LL_I2S_DisableIT_OVR(SPI_TypeDef * SPIx)3540 __STATIC_INLINE void LL_I2S_DisableIT_OVR(SPI_TypeDef *SPIx)
3541 {
3542 LL_SPI_DisableIT_OVR(SPIx);
3543 }
3544
3545 /**
3546 * @brief Disable TI Frame Format Error IT
3547 * @rmtoll IER TIFREIE LL_I2S_DisableIT_FRE
3548 * @param SPIx SPI Instance
3549 * @retval None
3550 */
LL_I2S_DisableIT_FRE(SPI_TypeDef * SPIx)3551 __STATIC_INLINE void LL_I2S_DisableIT_FRE(SPI_TypeDef *SPIx)
3552 {
3553 LL_SPI_DisableIT_FRE(SPIx);
3554 }
3555
3556 /**
3557 * @brief Check if Rx Packet available IT is enabled
3558 * @rmtoll IER RXPIE LL_I2S_IsEnabledIT_RXP
3559 * @param SPIx SPI Instance
3560 * @retval State of bit (1 or 0)
3561 */
LL_I2S_IsEnabledIT_RXP(SPI_TypeDef * SPIx)3562 __STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_RXP(SPI_TypeDef *SPIx)
3563 {
3564 return LL_SPI_IsEnabledIT_RXP(SPIx);
3565 }
3566
3567 /**
3568 * @brief Check if Tx Packet space available IT is enabled
3569 * @rmtoll IER TXPIE LL_I2S_IsEnabledIT_TXP
3570 * @param SPIx SPI Instance
3571 * @retval State of bit (1 or 0)
3572 */
LL_I2S_IsEnabledIT_TXP(SPI_TypeDef * SPIx)3573 __STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_TXP(SPI_TypeDef *SPIx)
3574 {
3575 return LL_SPI_IsEnabledIT_TXP(SPIx);
3576 }
3577
3578 /**
3579 * @brief Check if Underrun IT is enabled
3580 * @rmtoll IER UDRIE LL_I2S_IsEnabledIT_UDR
3581 * @param SPIx SPI Instance
3582 * @retval State of bit (1 or 0)
3583 */
LL_I2S_IsEnabledIT_UDR(SPI_TypeDef * SPIx)3584 __STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_UDR(SPI_TypeDef *SPIx)
3585 {
3586 return LL_SPI_IsEnabledIT_UDR(SPIx);
3587 }
3588
3589 /**
3590 * @brief Check if Overrun IT is enabled
3591 * @rmtoll IER OVRIE LL_I2S_IsEnabledIT_OVR
3592 * @param SPIx SPI Instance
3593 * @retval State of bit (1 or 0)
3594 */
LL_I2S_IsEnabledIT_OVR(SPI_TypeDef * SPIx)3595 __STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_OVR(SPI_TypeDef *SPIx)
3596 {
3597 return LL_SPI_IsEnabledIT_OVR(SPIx);
3598 }
3599
3600 /**
3601 * @brief Check if TI Frame Format Error IT is enabled
3602 * @rmtoll IER TIFREIE LL_I2S_IsEnabledIT_FRE
3603 * @param SPIx SPI Instance
3604 * @retval State of bit (1 or 0)
3605 */
LL_I2S_IsEnabledIT_FRE(SPI_TypeDef * SPIx)3606 __STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_FRE(SPI_TypeDef *SPIx)
3607 {
3608 return LL_SPI_IsEnabledIT_FRE(SPIx);
3609 }
3610
3611 /**
3612 * @}
3613 */
3614
3615 /** @defgroup I2S_LL_EF_DMA_Management DMA_Management
3616 * @{
3617 */
3618
3619 /**
3620 * @brief Enable DMA Rx
3621 * @rmtoll CFG1 RXDMAEN LL_I2S_EnableDMAReq_RX
3622 * @param SPIx SPI Instance
3623 * @retval None
3624 */
LL_I2S_EnableDMAReq_RX(SPI_TypeDef * SPIx)3625 __STATIC_INLINE void LL_I2S_EnableDMAReq_RX(SPI_TypeDef *SPIx)
3626 {
3627 LL_SPI_EnableDMAReq_RX(SPIx);
3628 }
3629
3630 /**
3631 * @brief Disable DMA Rx
3632 * @rmtoll CFG1 RXDMAEN LL_I2S_DisableDMAReq_RX
3633 * @param SPIx SPI Instance
3634 * @retval None
3635 */
LL_I2S_DisableDMAReq_RX(SPI_TypeDef * SPIx)3636 __STATIC_INLINE void LL_I2S_DisableDMAReq_RX(SPI_TypeDef *SPIx)
3637 {
3638 LL_SPI_DisableDMAReq_RX(SPIx);
3639 }
3640
3641 /**
3642 * @brief Check if DMA Rx is enabled
3643 * @rmtoll CFG1 RXDMAEN LL_I2S_IsEnabledDMAReq_RX
3644 * @param SPIx SPI Instance
3645 * @retval State of bit (1 or 0)
3646 */
LL_I2S_IsEnabledDMAReq_RX(SPI_TypeDef * SPIx)3647 __STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)
3648 {
3649 return LL_SPI_IsEnabledDMAReq_RX(SPIx);
3650 }
3651
3652 /**
3653 * @brief Enable DMA Tx
3654 * @rmtoll CFG1 TXDMAEN LL_I2S_EnableDMAReq_TX
3655 * @param SPIx SPI Instance
3656 * @retval None
3657 */
LL_I2S_EnableDMAReq_TX(SPI_TypeDef * SPIx)3658 __STATIC_INLINE void LL_I2S_EnableDMAReq_TX(SPI_TypeDef *SPIx)
3659 {
3660 LL_SPI_EnableDMAReq_TX(SPIx);
3661 }
3662
3663 /**
3664 * @brief Disable DMA Tx
3665 * @rmtoll CFG1 TXDMAEN LL_I2S_DisableDMAReq_TX
3666 * @param SPIx SPI Instance
3667 * @retval None
3668 */
LL_I2S_DisableDMAReq_TX(SPI_TypeDef * SPIx)3669 __STATIC_INLINE void LL_I2S_DisableDMAReq_TX(SPI_TypeDef *SPIx)
3670 {
3671 LL_SPI_DisableDMAReq_TX(SPIx);
3672 }
3673
3674 /**
3675 * @brief Check if DMA Tx is enabled
3676 * @rmtoll CFG1 TXDMAEN LL_I2S_IsEnabledDMAReq_TX
3677 * @param SPIx SPI Instance
3678 * @retval State of bit (1 or 0)
3679 */
LL_I2S_IsEnabledDMAReq_TX(SPI_TypeDef * SPIx)3680 __STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)
3681 {
3682 return LL_SPI_IsEnabledDMAReq_TX(SPIx);
3683 }
3684
3685 /**
3686 * @}
3687 */
3688
3689 /** @defgroup I2S_LL_EF_DATA_Management DATA_Management
3690 * @{
3691 */
3692
3693 /**
3694 * @brief Read Data Register
3695 * @rmtoll RXDR . LL_I2S_ReceiveData16
3696 * @param SPIx SPI Instance
3697 * @retval 0..0xFFFF
3698 */
LL_I2S_ReceiveData16(SPI_TypeDef * SPIx)3699 __STATIC_INLINE uint16_t LL_I2S_ReceiveData16(SPI_TypeDef *SPIx)
3700 {
3701 return LL_SPI_ReceiveData16(SPIx);
3702 }
3703
3704 /**
3705 * @brief Read Data Register
3706 * @rmtoll RXDR . LL_I2S_ReceiveData32
3707 * @param SPIx SPI Instance
3708 * @retval 0..0xFFFFFFFF
3709 */
LL_I2S_ReceiveData32(SPI_TypeDef * SPIx)3710 __STATIC_INLINE uint32_t LL_I2S_ReceiveData32(SPI_TypeDef *SPIx)
3711 {
3712 return LL_SPI_ReceiveData32(SPIx);
3713 }
3714
3715 /**
3716 * @brief Write Data Register
3717 * @rmtoll TXDR . LL_I2S_TransmitData16
3718 * @param SPIx SPI Instance
3719 * @param TxData 0..0xFFFF
3720 * @retval None
3721 */
LL_I2S_TransmitData16(SPI_TypeDef * SPIx,uint16_t TxData)3722 __STATIC_INLINE void LL_I2S_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
3723 {
3724 LL_SPI_TransmitData16(SPIx, TxData);
3725 }
3726
3727 /**
3728 * @brief Write Data Register
3729 * @rmtoll TXDR . LL_I2S_TransmitData32
3730 * @param SPIx SPI Instance
3731 * @param TxData 0..0xFFFFFFFF
3732 * @retval None
3733 */
LL_I2S_TransmitData32(SPI_TypeDef * SPIx,uint32_t TxData)3734 __STATIC_INLINE void LL_I2S_TransmitData32(SPI_TypeDef *SPIx, uint32_t TxData)
3735 {
3736 LL_SPI_TransmitData32(SPIx, TxData);
3737 }
3738
3739
3740 /**
3741 * @}
3742 */
3743
3744
3745 #if defined(USE_FULL_LL_DRIVER)
3746 /** @defgroup SPI_LL_EF_Init Initialization and de-initialization functions
3747 * @{
3748 */
3749
3750 ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx);
3751 ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct);
3752 void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct);
3753 void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity);
3754
3755 /**
3756 * @}
3757 */
3758 #endif /* USE_FULL_LL_DRIVER */
3759
3760 /**
3761 * @}
3762 */
3763
3764 /**
3765 * @}
3766 */
3767
3768 #endif /* defined(SPI1) || defined(SPI2) || defined(SPI3) || defined(SPI4) || defined(SPI5) || defined(SPI6) */
3769
3770 /**
3771 * @}
3772 */
3773
3774 /**
3775 * @}
3776 */
3777 #ifdef __cplusplus
3778 }
3779 #endif
3780
3781 #endif /* STM32MP1xx_LL_SPI_H */
3782
