1 /** 2 ****************************************************************************** 3 * @file stm32mp1xx_hal_qspi.h 4 * @author MCD Application Team 5 * @brief Header file of QSPI HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2019 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32MP1xx_HAL_QSPI_H 21 #define STM32MP1xx_HAL_QSPI_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32mp1xx_hal_def.h" 29 #include "stm32mp1xx_hal_mdma.h" 30 31 #if defined(QUADSPI) || defined(QUADSPI1) || defined(QUADSPI2) 32 33 /** @addtogroup STM32MP1xx_HAL_Driver 34 * @{ 35 */ 36 37 /** @addtogroup QSPI 38 * @{ 39 */ 40 41 /* Exported types ------------------------------------------------------------*/ 42 /** @defgroup QSPI_Exported_Types QSPI Exported Types 43 * @{ 44 */ 45 46 /** 47 * @brief QSPI Init structure definition 48 */ 49 typedef struct 50 { 51 uint32_t ClockPrescaler; /* Specifies the prescaler factor for generating clock based on the AHB clock. 52 This parameter can be a number between 0 and 255 */ 53 uint32_t FifoThreshold; /* Specifies the threshold number of bytes in the FIFO (used only in indirect mode) 54 This parameter can be a value between 1 and 32 */ 55 uint32_t SampleShifting; /* Specifies the Sample Shift. The data is sampled 1/2 clock cycle delay later to 56 take in account external signal delays. (It should be QSPI_SAMPLE_SHIFTING_NONE in DDR mode) 57 This parameter can be a value of @ref QSPI_SampleShifting */ 58 uint32_t FlashSize; /* Specifies the Flash Size. FlashSize+1 is effectively the number of address bits 59 required to address the flash memory. The flash capacity can be up to 4GB 60 (addressed using 32 bits) in indirect mode, but the addressable space in 61 memory-mapped mode is limited to 256MB 62 This parameter can be a number between 0 and 31 */ 63 uint32_t ChipSelectHighTime; /* Specifies the Chip Select High Time. ChipSelectHighTime+1 defines the minimum number 64 of clock cycles which the chip select must remain high between commands. 65 This parameter can be a value of @ref QSPI_ChipSelectHighTime */ 66 uint32_t ClockMode; /* Specifies the Clock Mode. It indicates the level that clock takes between commands. 67 This parameter can be a value of @ref QSPI_ClockMode */ 68 uint32_t FlashID; /* Specifies the Flash which will be used, 69 This parameter can be a value of @ref QSPI_Flash_Select */ 70 uint32_t DualFlash; /* Specifies the Dual Flash Mode State 71 This parameter can be a value of @ref QSPI_DualFlash_Mode */ 72 }QSPI_InitTypeDef; 73 74 /** 75 * @brief HAL QSPI State structures definition 76 */ 77 typedef enum 78 { 79 HAL_QSPI_STATE_RESET = 0x00U, /*!< Peripheral not initialized */ 80 HAL_QSPI_STATE_READY = 0x01U, /*!< Peripheral initialized and ready for use */ 81 HAL_QSPI_STATE_BUSY = 0x02U, /*!< Peripheral in indirect mode and busy */ 82 HAL_QSPI_STATE_BUSY_INDIRECT_TX = 0x12U, /*!< Peripheral in indirect mode with transmission ongoing */ 83 HAL_QSPI_STATE_BUSY_INDIRECT_RX = 0x22U, /*!< Peripheral in indirect mode with reception ongoing */ 84 HAL_QSPI_STATE_BUSY_AUTO_POLLING = 0x42U, /*!< Peripheral in auto polling mode ongoing */ 85 HAL_QSPI_STATE_BUSY_MEM_MAPPED = 0x82U, /*!< Peripheral in memory mapped mode ongoing */ 86 HAL_QSPI_STATE_ABORT = 0x08U, /*!< Peripheral with abort request ongoing */ 87 HAL_QSPI_STATE_ERROR = 0x04U /*!< Peripheral in error */ 88 }HAL_QSPI_StateTypeDef; 89 90 /** 91 * @brief QSPI Handle Structure definition 92 */ 93 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) 94 typedef struct __QSPI_HandleTypeDef 95 #else 96 typedef struct 97 #endif 98 { 99 QUADSPI_TypeDef *Instance; /* QSPI registers base address */ 100 QSPI_InitTypeDef Init; /* QSPI communication parameters */ 101 uint8_t *pTxBuffPtr; /* Pointer to QSPI Tx transfer Buffer */ 102 __IO uint32_t TxXferSize; /* QSPI Tx Transfer size */ 103 __IO uint32_t TxXferCount; /* QSPI Tx Transfer Counter */ 104 uint8_t *pRxBuffPtr; /* Pointer to QSPI Rx transfer Buffer */ 105 __IO uint32_t RxXferSize; /* QSPI Rx Transfer size */ 106 __IO uint32_t RxXferCount; /* QSPI Rx Transfer Counter */ 107 MDMA_HandleTypeDef *hmdma; /* QSPI Rx/Tx MDMA Handle parameters */ 108 __IO HAL_LockTypeDef Lock; /* Locking object */ 109 __IO HAL_QSPI_StateTypeDef State; /* QSPI communication state */ 110 __IO uint32_t ErrorCode; /* QSPI Error code */ 111 uint32_t Timeout; /* Timeout for the QSPI memory access */ 112 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) 113 void (* ErrorCallback) (struct __QSPI_HandleTypeDef *hqspi); 114 void (* AbortCpltCallback) (struct __QSPI_HandleTypeDef *hqspi); 115 void (* FifoThresholdCallback)(struct __QSPI_HandleTypeDef *hqspi); 116 void (* CmdCpltCallback) (struct __QSPI_HandleTypeDef *hqspi); 117 void (* RxCpltCallback) (struct __QSPI_HandleTypeDef *hqspi); 118 void (* TxCpltCallback) (struct __QSPI_HandleTypeDef *hqspi); 119 void (* RxHalfCpltCallback) (struct __QSPI_HandleTypeDef *hqspi); 120 void (* TxHalfCpltCallback) (struct __QSPI_HandleTypeDef *hqspi); 121 void (* StatusMatchCallback) (struct __QSPI_HandleTypeDef *hqspi); 122 void (* TimeOutCallback) (struct __QSPI_HandleTypeDef *hqspi); 123 124 void (* MspInitCallback) (struct __QSPI_HandleTypeDef *hqspi); 125 void (* MspDeInitCallback) (struct __QSPI_HandleTypeDef *hqspi); 126 #endif 127 }QSPI_HandleTypeDef; 128 129 /** 130 * @brief QSPI Command structure definition 131 */ 132 typedef struct 133 { 134 uint32_t Instruction; /* Specifies the Instruction to be sent 135 This parameter can be a value (8-bit) between 0x00 and 0xFF */ 136 uint32_t Address; /* Specifies the Address to be sent (Size from 1 to 4 bytes according AddressSize) 137 This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFF */ 138 uint32_t AlternateBytes; /* Specifies the Alternate Bytes to be sent (Size from 1 to 4 bytes according AlternateBytesSize) 139 This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFF */ 140 uint32_t AddressSize; /* Specifies the Address Size 141 This parameter can be a value of @ref QSPI_AddressSize */ 142 uint32_t AlternateBytesSize; /* Specifies the Alternate Bytes Size 143 This parameter can be a value of @ref QSPI_AlternateBytesSize */ 144 uint32_t DummyCycles; /* Specifies the Number of Dummy Cycles. 145 This parameter can be a number between 0 and 31 */ 146 uint32_t InstructionMode; /* Specifies the Instruction Mode 147 This parameter can be a value of @ref QSPI_InstructionMode */ 148 uint32_t AddressMode; /* Specifies the Address Mode 149 This parameter can be a value of @ref QSPI_AddressMode */ 150 uint32_t AlternateByteMode; /* Specifies the Alternate Bytes Mode 151 This parameter can be a value of @ref QSPI_AlternateBytesMode */ 152 uint32_t DataMode; /* Specifies the Data Mode (used for dummy cycles and data phases) 153 This parameter can be a value of @ref QSPI_DataMode */ 154 uint32_t NbData; /* Specifies the number of data to transfer. (This is the number of bytes) 155 This parameter can be any value between 0 and 0xFFFFFFFF (0 means undefined length 156 until end of memory)*/ 157 uint32_t DdrMode; /* Specifies the double data rate mode for address, alternate byte and data phase 158 This parameter can be a value of @ref QSPI_DdrMode */ 159 uint32_t DdrHoldHalfCycle; /* Specifies if the DDR hold is enabled. When enabled it delays the data 160 output by one half of system clock in DDR mode. 161 This parameter can be a value of @ref QSPI_DdrHoldHalfCycle */ 162 uint32_t SIOOMode; /* Specifies the send instruction only once mode 163 This parameter can be a value of @ref QSPI_SIOOMode */ 164 }QSPI_CommandTypeDef; 165 166 /** 167 * @brief QSPI Auto Polling mode configuration structure definition 168 */ 169 typedef struct 170 { 171 uint32_t Match; /* Specifies the value to be compared with the masked status register to get a match. 172 This parameter can be any value between 0 and 0xFFFFFFFF */ 173 uint32_t Mask; /* Specifies the mask to be applied to the status bytes received. 174 This parameter can be any value between 0 and 0xFFFFFFFF */ 175 uint32_t Interval; /* Specifies the number of clock cycles between two read during automatic polling phases. 176 This parameter can be any value between 0 and 0xFFFF */ 177 uint32_t StatusBytesSize; /* Specifies the size of the status bytes received. 178 This parameter can be any value between 1 and 4 */ 179 uint32_t MatchMode; /* Specifies the method used for determining a match. 180 This parameter can be a value of @ref QSPI_MatchMode */ 181 uint32_t AutomaticStop; /* Specifies if automatic polling is stopped after a match. 182 This parameter can be a value of @ref QSPI_AutomaticStop */ 183 }QSPI_AutoPollingTypeDef; 184 185 /** 186 * @brief QSPI Memory Mapped mode configuration structure definition 187 */ 188 typedef struct 189 { 190 uint32_t TimeOutPeriod; /* Specifies the number of clock to wait when the FIFO is full before to release the chip select. 191 This parameter can be any value between 0 and 0xFFFF */ 192 uint32_t TimeOutActivation; /* Specifies if the timeout counter is enabled to release the chip select. 193 This parameter can be a value of @ref QSPI_TimeOutActivation */ 194 }QSPI_MemoryMappedTypeDef; 195 196 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) 197 /** 198 * @brief HAL QSPI Callback ID enumeration definition 199 */ 200 typedef enum 201 { 202 HAL_QSPI_ERROR_CB_ID = 0x00U, /*!< QSPI Error Callback ID */ 203 HAL_QSPI_ABORT_CB_ID = 0x01U, /*!< QSPI Abort Callback ID */ 204 HAL_QSPI_FIFO_THRESHOLD_CB_ID = 0x02U, /*!< QSPI FIFO Threshold Callback ID */ 205 HAL_QSPI_CMD_CPLT_CB_ID = 0x03U, /*!< QSPI Command Complete Callback ID */ 206 HAL_QSPI_RX_CPLT_CB_ID = 0x04U, /*!< QSPI Rx Complete Callback ID */ 207 HAL_QSPI_TX_CPLT_CB_ID = 0x05U, /*!< QSPI Tx Complete Callback ID */ 208 HAL_QSPI_RX_HALF_CPLT_CB_ID = 0x06U, /*!< QSPI Rx Half Complete Callback ID */ 209 HAL_QSPI_TX_HALF_CPLT_CB_ID = 0x07U, /*!< QSPI Tx Half Complete Callback ID */ 210 HAL_QSPI_STATUS_MATCH_CB_ID = 0x08U, /*!< QSPI Status Match Callback ID */ 211 HAL_QSPI_TIMEOUT_CB_ID = 0x09U, /*!< QSPI Timeout Callback ID */ 212 213 HAL_QSPI_MSP_INIT_CB_ID = 0x0AU, /*!< QSPI MspInit Callback ID */ 214 HAL_QSPI_MSP_DEINIT_CB_ID = 0x0B0 /*!< QSPI MspDeInit Callback ID */ 215 }HAL_QSPI_CallbackIDTypeDef; 216 217 /** 218 * @brief HAL QSPI Callback pointer definition 219 */ 220 typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi); 221 #endif 222 /** 223 * @} 224 */ 225 226 /* Exported constants --------------------------------------------------------*/ 227 /** @defgroup QSPI_Exported_Constants QSPI Exported Constants 228 * @{ 229 */ 230 231 /** @defgroup QSPI_ErrorCode QSPI Error Code 232 * @{ 233 */ 234 #define HAL_QSPI_ERROR_NONE 0x00000000U /*!< No error */ 235 #define HAL_QSPI_ERROR_TIMEOUT 0x00000001U /*!< Timeout error */ 236 #define HAL_QSPI_ERROR_TRANSFER 0x00000002U /*!< Transfer error */ 237 #define HAL_QSPI_ERROR_DMA 0x00000004U /*!< DMA transfer error */ 238 #define HAL_QSPI_ERROR_INVALID_PARAM 0x00000008U /*!< Invalid parameters error */ 239 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) 240 #define HAL_QSPI_ERROR_INVALID_CALLBACK 0x00000010U /*!< Invalid callback error */ 241 #endif 242 /** 243 * @} 244 */ 245 246 /** @defgroup QSPI_SampleShifting QSPI Sample Shifting 247 * @{ 248 */ 249 #define QSPI_SAMPLE_SHIFTING_NONE 0x00000000U /*!<No clock cycle shift to sample data*/ 250 #define QSPI_SAMPLE_SHIFTING_HALFCYCLE ((uint32_t)QUADSPI_CR_SSHIFT) /*!<1/2 clock cycle shift to sample data*/ 251 /** 252 * @} 253 */ 254 255 /** @defgroup QSPI_ChipSelectHighTime QSPI ChipSelect High Time 256 * @{ 257 */ 258 #define QSPI_CS_HIGH_TIME_1_CYCLE 0x00000000U /*!<nCS stay high for at least 1 clock cycle between commands*/ 259 #define QSPI_CS_HIGH_TIME_2_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0) /*!<nCS stay high for at least 2 clock cycles between commands*/ 260 #define QSPI_CS_HIGH_TIME_3_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 3 clock cycles between commands*/ 261 #define QSPI_CS_HIGH_TIME_4_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0 | QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 4 clock cycles between commands*/ 262 #define QSPI_CS_HIGH_TIME_5_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2) /*!<nCS stay high for at least 5 clock cycles between commands*/ 263 #define QSPI_CS_HIGH_TIME_6_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_0) /*!<nCS stay high for at least 6 clock cycles between commands*/ 264 #define QSPI_CS_HIGH_TIME_7_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 7 clock cycles between commands*/ 265 #define QSPI_CS_HIGH_TIME_8_CYCLE ((uint32_t)QUADSPI_DCR_CSHT) /*!<nCS stay high for at least 8 clock cycles between commands*/ 266 /** 267 * @} 268 */ 269 270 /** @defgroup QSPI_ClockMode QSPI Clock Mode 271 * @{ 272 */ 273 #define QSPI_CLOCK_MODE_0 0x00000000U /*!<Clk stays low while nCS is released*/ 274 #define QSPI_CLOCK_MODE_3 ((uint32_t)QUADSPI_DCR_CKMODE) /*!<Clk goes high while nCS is released*/ 275 /** 276 * @} 277 */ 278 279 /** @defgroup QSPI_Flash_Select QSPI Flash Select 280 * @{ 281 */ 282 #define QSPI_FLASH_ID_1 0x00000000U /*!<FLASH 1 selected*/ 283 #define QSPI_FLASH_ID_2 ((uint32_t)QUADSPI_CR_FSEL) /*!<FLASH 2 selected*/ 284 /** 285 * @} 286 */ 287 288 /** @defgroup QSPI_DualFlash_Mode QSPI Dual Flash Mode 289 * @{ 290 */ 291 #define QSPI_DUALFLASH_ENABLE ((uint32_t)QUADSPI_CR_DFM) /*!<Dual-flash mode enabled*/ 292 #define QSPI_DUALFLASH_DISABLE 0x00000000U /*!<Dual-flash mode disabled*/ 293 /** 294 * @} 295 */ 296 297 /** @defgroup QSPI_AddressSize QSPI Address Size 298 * @{ 299 */ 300 #define QSPI_ADDRESS_8_BITS 0x00000000U /*!<8-bit address*/ 301 #define QSPI_ADDRESS_16_BITS ((uint32_t)QUADSPI_CCR_ADSIZE_0) /*!<16-bit address*/ 302 #define QSPI_ADDRESS_24_BITS ((uint32_t)QUADSPI_CCR_ADSIZE_1) /*!<24-bit address*/ 303 #define QSPI_ADDRESS_32_BITS ((uint32_t)QUADSPI_CCR_ADSIZE) /*!<32-bit address*/ 304 /** 305 * @} 306 */ 307 308 /** @defgroup QSPI_AlternateBytesSize QSPI Alternate Bytes Size 309 * @{ 310 */ 311 #define QSPI_ALTERNATE_BYTES_8_BITS 0x00000000U /*!<8-bit alternate bytes*/ 312 #define QSPI_ALTERNATE_BYTES_16_BITS ((uint32_t)QUADSPI_CCR_ABSIZE_0) /*!<16-bit alternate bytes*/ 313 #define QSPI_ALTERNATE_BYTES_24_BITS ((uint32_t)QUADSPI_CCR_ABSIZE_1) /*!<24-bit alternate bytes*/ 314 #define QSPI_ALTERNATE_BYTES_32_BITS ((uint32_t)QUADSPI_CCR_ABSIZE) /*!<32-bit alternate bytes*/ 315 /** 316 * @} 317 */ 318 319 /** @defgroup QSPI_InstructionMode QSPI Instruction Mode 320 * @{ 321 */ 322 #define QSPI_INSTRUCTION_NONE 0x00000000U /*!<No instruction*/ 323 #define QSPI_INSTRUCTION_1_LINE ((uint32_t)QUADSPI_CCR_IMODE_0) /*!<Instruction on a single line*/ 324 #define QSPI_INSTRUCTION_2_LINES ((uint32_t)QUADSPI_CCR_IMODE_1) /*!<Instruction on two lines*/ 325 #define QSPI_INSTRUCTION_4_LINES ((uint32_t)QUADSPI_CCR_IMODE) /*!<Instruction on four lines*/ 326 /** 327 * @} 328 */ 329 330 /** @defgroup QSPI_AddressMode QSPI Address Mode 331 * @{ 332 */ 333 #define QSPI_ADDRESS_NONE 0x00000000U /*!<No address*/ 334 #define QSPI_ADDRESS_1_LINE ((uint32_t)QUADSPI_CCR_ADMODE_0) /*!<Address on a single line*/ 335 #define QSPI_ADDRESS_2_LINES ((uint32_t)QUADSPI_CCR_ADMODE_1) /*!<Address on two lines*/ 336 #define QSPI_ADDRESS_4_LINES ((uint32_t)QUADSPI_CCR_ADMODE) /*!<Address on four lines*/ 337 /** 338 * @} 339 */ 340 341 /** @defgroup QSPI_AlternateBytesMode QSPI Alternate Bytes Mode 342 * @{ 343 */ 344 #define QSPI_ALTERNATE_BYTES_NONE 0x00000000U /*!<No alternate bytes*/ 345 #define QSPI_ALTERNATE_BYTES_1_LINE ((uint32_t)QUADSPI_CCR_ABMODE_0) /*!<Alternate bytes on a single line*/ 346 #define QSPI_ALTERNATE_BYTES_2_LINES ((uint32_t)QUADSPI_CCR_ABMODE_1) /*!<Alternate bytes on two lines*/ 347 #define QSPI_ALTERNATE_BYTES_4_LINES ((uint32_t)QUADSPI_CCR_ABMODE) /*!<Alternate bytes on four lines*/ 348 /** 349 * @} 350 */ 351 352 /** @defgroup QSPI_DataMode QSPI Data Mode 353 * @{ 354 */ 355 #define QSPI_DATA_NONE 0x00000000U /*!<No data*/ 356 #define QSPI_DATA_1_LINE ((uint32_t)QUADSPI_CCR_DMODE_0) /*!<Data on a single line*/ 357 #define QSPI_DATA_2_LINES ((uint32_t)QUADSPI_CCR_DMODE_1) /*!<Data on two lines*/ 358 #define QSPI_DATA_4_LINES ((uint32_t)QUADSPI_CCR_DMODE) /*!<Data on four lines*/ 359 /** 360 * @} 361 */ 362 363 /** @defgroup QSPI_DdrMode QSPI DDR Mode 364 * @{ 365 */ 366 #define QSPI_DDR_MODE_DISABLE 0x00000000U /*!<Double data rate mode disabled*/ 367 #define QSPI_DDR_MODE_ENABLE ((uint32_t)QUADSPI_CCR_DDRM) /*!<Double data rate mode enabled*/ 368 /** 369 * @} 370 */ 371 372 /** @defgroup QSPI_DdrHoldHalfCycle QSPI DDR Data Output Delay 373 * @{ 374 */ 375 #define QSPI_DDR_HHC_ANALOG_DELAY 0x00000000U /*!<Delay the data output using analog delay in DDR mode*/ 376 #define QSPI_DDR_HHC_HALF_CLK_DELAY ((uint32_t)QUADSPI_CCR_DHHC) /*!<Delay the data output by one half of system clock in DDR mode*/ 377 /** 378 * @} 379 */ 380 381 /** @defgroup QSPI_SIOOMode QSPI Send Instruction Mode 382 * @{ 383 */ 384 #define QSPI_SIOO_INST_EVERY_CMD 0x00000000U /*!<Send instruction on every transaction*/ 385 #define QSPI_SIOO_INST_ONLY_FIRST_CMD ((uint32_t)QUADSPI_CCR_SIOO) /*!<Send instruction only for the first command*/ 386 /** 387 * @} 388 */ 389 390 /** @defgroup QSPI_MatchMode QSPI Match Mode 391 * @{ 392 */ 393 #define QSPI_MATCH_MODE_AND 0x00000000U /*!<AND match mode between unmasked bits*/ 394 #define QSPI_MATCH_MODE_OR ((uint32_t)QUADSPI_CR_PMM) /*!<OR match mode between unmasked bits*/ 395 /** 396 * @} 397 */ 398 399 /** @defgroup QSPI_AutomaticStop QSPI Automatic Stop 400 * @{ 401 */ 402 #define QSPI_AUTOMATIC_STOP_DISABLE 0x00000000U /*!<AutoPolling stops only with abort or QSPI disabling*/ 403 #define QSPI_AUTOMATIC_STOP_ENABLE ((uint32_t)QUADSPI_CR_APMS) /*!<AutoPolling stops as soon as there is a match*/ 404 /** 405 * @} 406 */ 407 408 /** @defgroup QSPI_TimeOutActivation QSPI Timeout Activation 409 * @{ 410 */ 411 #define QSPI_TIMEOUT_COUNTER_DISABLE 0x00000000U /*!<Timeout counter disabled, nCS remains active*/ 412 #define QSPI_TIMEOUT_COUNTER_ENABLE ((uint32_t)QUADSPI_CR_TCEN) /*!<Timeout counter enabled, nCS released when timeout expires*/ 413 /** 414 * @} 415 */ 416 417 /** @defgroup QSPI_Flags QSPI Flags 418 * @{ 419 */ 420 #define QSPI_FLAG_BUSY QUADSPI_SR_BUSY /*!<Busy flag: operation is ongoing*/ 421 #define QSPI_FLAG_TO QUADSPI_SR_TOF /*!<Timeout flag: timeout occurs in memory-mapped mode*/ 422 #define QSPI_FLAG_SM QUADSPI_SR_SMF /*!<Status match flag: received data matches in autopolling mode*/ 423 #define QSPI_FLAG_FT QUADSPI_SR_FTF /*!<Fifo threshold flag: Fifo threshold reached or data left after read from memory is complete*/ 424 #define QSPI_FLAG_TC QUADSPI_SR_TCF /*!<Transfer complete flag: programmed number of data have been transferred or the transfer has been aborted*/ 425 #define QSPI_FLAG_TE QUADSPI_SR_TEF /*!<Transfer error flag: invalid address is being accessed*/ 426 /** 427 * @} 428 */ 429 430 /** @defgroup QSPI_Interrupts QSPI Interrupts 431 * @{ 432 */ 433 #define QSPI_IT_TO QUADSPI_CR_TOIE /*!<Interrupt on the timeout flag*/ 434 #define QSPI_IT_SM QUADSPI_CR_SMIE /*!<Interrupt on the status match flag*/ 435 #define QSPI_IT_FT QUADSPI_CR_FTIE /*!<Interrupt on the fifo threshold flag*/ 436 #define QSPI_IT_TC QUADSPI_CR_TCIE /*!<Interrupt on the transfer complete flag*/ 437 #define QSPI_IT_TE QUADSPI_CR_TEIE /*!<Interrupt on the transfer error flag*/ 438 /** 439 * @} 440 */ 441 442 /** @defgroup QSPI_Timeout_definition QSPI Timeout definition 443 * @brief QSPI Timeout definition 444 * @{ 445 */ 446 #define HAL_QPSI_TIMEOUT_DEFAULT_VALUE 5000U /* 5 s */ 447 /** 448 * @} 449 */ 450 451 /** 452 * @} 453 */ 454 455 /* Exported macros -----------------------------------------------------------*/ 456 /** @defgroup QSPI_Exported_Macros QSPI Exported Macros 457 * @{ 458 */ 459 /** @brief Reset QSPI handle state. 460 * @param __HANDLE__ QSPI handle. 461 * @retval None 462 */ 463 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) 464 #define __HAL_QSPI_RESET_HANDLE_STATE(__HANDLE__) do { \ 465 (__HANDLE__)->State = HAL_QSPI_STATE_RESET; \ 466 (__HANDLE__)->MspInitCallback = NULL; \ 467 (__HANDLE__)->MspDeInitCallback = NULL; \ 468 } while(0) 469 #else 470 #define __HAL_QSPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_QSPI_STATE_RESET) 471 #endif 472 473 /** @brief Enable the QSPI peripheral. 474 * @param __HANDLE__ specifies the QSPI Handle. 475 * @retval None 476 */ 477 #define __HAL_QSPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN) 478 479 /** @brief Disable the QSPI peripheral. 480 * @param __HANDLE__ specifies the QSPI Handle. 481 * @retval None 482 */ 483 #define __HAL_QSPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN) 484 485 /** @brief Enable the specified QSPI interrupt. 486 * @param __HANDLE__ specifies the QSPI Handle. 487 * @param __INTERRUPT__ specifies the QSPI interrupt source to enable. 488 * This parameter can be one of the following values: 489 * @arg QSPI_IT_TO: QSPI Timeout interrupt 490 * @arg QSPI_IT_SM: QSPI Status match interrupt 491 * @arg QSPI_IT_FT: QSPI FIFO threshold interrupt 492 * @arg QSPI_IT_TC: QSPI Transfer complete interrupt 493 * @arg QSPI_IT_TE: QSPI Transfer error interrupt 494 * @retval None 495 */ 496 #define __HAL_QSPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) 497 498 499 /** @brief Disable the specified QSPI interrupt. 500 * @param __HANDLE__ specifies the QSPI Handle. 501 * @param __INTERRUPT__ specifies the QSPI interrupt source to disable. 502 * This parameter can be one of the following values: 503 * @arg QSPI_IT_TO: QSPI Timeout interrupt 504 * @arg QSPI_IT_SM: QSPI Status match interrupt 505 * @arg QSPI_IT_FT: QSPI FIFO threshold interrupt 506 * @arg QSPI_IT_TC: QSPI Transfer complete interrupt 507 * @arg QSPI_IT_TE: QSPI Transfer error interrupt 508 * @retval None 509 */ 510 #define __HAL_QSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) 511 512 /** @brief Check whether the specified QSPI interrupt source is enabled or not. 513 * @param __HANDLE__ specifies the QSPI Handle. 514 * @param __INTERRUPT__ specifies the QSPI interrupt source to check. 515 * This parameter can be one of the following values: 516 * @arg QSPI_IT_TO: QSPI Timeout interrupt 517 * @arg QSPI_IT_SM: QSPI Status match interrupt 518 * @arg QSPI_IT_FT: QSPI FIFO threshold interrupt 519 * @arg QSPI_IT_TC: QSPI Transfer complete interrupt 520 * @arg QSPI_IT_TE: QSPI Transfer error interrupt 521 * @retval The new state of __INTERRUPT__ (TRUE or FALSE). 522 */ 523 #define __HAL_QSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) == (__INTERRUPT__)) 524 525 /** 526 * @brief Check whether the selected QSPI flag is set or not. 527 * @param __HANDLE__ specifies the QSPI Handle. 528 * @param __FLAG__ specifies the QSPI flag to check. 529 * This parameter can be one of the following values: 530 * @arg QSPI_FLAG_BUSY: QSPI Busy flag 531 * @arg QSPI_FLAG_TO: QSPI Timeout flag 532 * @arg QSPI_FLAG_SM: QSPI Status match flag 533 * @arg QSPI_FLAG_FT: QSPI FIFO threshold flag 534 * @arg QSPI_FLAG_TC: QSPI Transfer complete flag 535 * @arg QSPI_FLAG_TE: QSPI Transfer error flag 536 * @retval None 537 */ 538 #define __HAL_QSPI_GET_FLAG(__HANDLE__, __FLAG__) ((READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0U) ? SET : RESET) 539 540 /** @brief Clears the specified QSPI's flag status. 541 * @param __HANDLE__ specifies the QSPI Handle. 542 * @param __FLAG__ specifies the QSPI clear register flag that needs to be set 543 * This parameter can be one of the following values: 544 * @arg QSPI_FLAG_TO: QSPI Timeout flag 545 * @arg QSPI_FLAG_SM: QSPI Status match flag 546 * @arg QSPI_FLAG_TC: QSPI Transfer complete flag 547 * @arg QSPI_FLAG_TE: QSPI Transfer error flag 548 * @retval None 549 */ 550 #define __HAL_QSPI_CLEAR_FLAG(__HANDLE__, __FLAG__) WRITE_REG((__HANDLE__)->Instance->FCR, (__FLAG__)) 551 /** 552 * @} 553 */ 554 555 /* Exported functions --------------------------------------------------------*/ 556 /** @addtogroup QSPI_Exported_Functions 557 * @{ 558 */ 559 560 /** @addtogroup QSPI_Exported_Functions_Group1 561 * @{ 562 */ 563 /* Initialization/de-initialization functions ********************************/ 564 HAL_StatusTypeDef HAL_QSPI_Init (QSPI_HandleTypeDef *hqspi); 565 HAL_StatusTypeDef HAL_QSPI_DeInit (QSPI_HandleTypeDef *hqspi); 566 void HAL_QSPI_MspInit (QSPI_HandleTypeDef *hqspi); 567 void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi); 568 /** 569 * @} 570 */ 571 572 /** @addtogroup QSPI_Exported_Functions_Group2 573 * @{ 574 */ 575 /* IO operation functions *****************************************************/ 576 /* QSPI IRQ handler method */ 577 void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi); 578 579 /* QSPI indirect mode */ 580 HAL_StatusTypeDef HAL_QSPI_Command (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t Timeout); 581 HAL_StatusTypeDef HAL_QSPI_Transmit (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout); 582 HAL_StatusTypeDef HAL_QSPI_Receive (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout); 583 HAL_StatusTypeDef HAL_QSPI_Command_IT (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd); 584 HAL_StatusTypeDef HAL_QSPI_Transmit_IT (QSPI_HandleTypeDef *hqspi, uint8_t *pData); 585 HAL_StatusTypeDef HAL_QSPI_Receive_IT (QSPI_HandleTypeDef *hqspi, uint8_t *pData); 586 HAL_StatusTypeDef HAL_QSPI_Transmit_DMA (QSPI_HandleTypeDef *hqspi, uint8_t *pData); 587 HAL_StatusTypeDef HAL_QSPI_Receive_DMA (QSPI_HandleTypeDef *hqspi, uint8_t *pData); 588 589 /* QSPI status flag polling mode */ 590 HAL_StatusTypeDef HAL_QSPI_AutoPolling (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg, uint32_t Timeout); 591 HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg); 592 593 /* QSPI memory-mapped mode */ 594 HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_MemoryMappedTypeDef *cfg); 595 596 /* Callback functions in non-blocking modes ***********************************/ 597 void HAL_QSPI_ErrorCallback (QSPI_HandleTypeDef *hqspi); 598 void HAL_QSPI_AbortCpltCallback (QSPI_HandleTypeDef *hqspi); 599 void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi); 600 601 /* QSPI indirect mode */ 602 void HAL_QSPI_CmdCpltCallback (QSPI_HandleTypeDef *hqspi); 603 void HAL_QSPI_RxCpltCallback (QSPI_HandleTypeDef *hqspi); 604 void HAL_QSPI_TxCpltCallback (QSPI_HandleTypeDef *hqspi); 605 void HAL_QSPI_RxHalfCpltCallback (QSPI_HandleTypeDef *hqspi); 606 void HAL_QSPI_TxHalfCpltCallback (QSPI_HandleTypeDef *hqspi); 607 608 /* QSPI status flag polling mode */ 609 void HAL_QSPI_StatusMatchCallback (QSPI_HandleTypeDef *hqspi); 610 611 /* QSPI memory-mapped mode */ 612 void HAL_QSPI_TimeOutCallback (QSPI_HandleTypeDef *hqspi); 613 614 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) 615 /* QSPI callback registering/unregistering */ 616 HAL_StatusTypeDef HAL_QSPI_RegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDef CallbackId, pQSPI_CallbackTypeDef pCallback); 617 HAL_StatusTypeDef HAL_QSPI_UnRegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDef CallbackId); 618 #endif 619 /** 620 * @} 621 */ 622 623 /** @addtogroup QSPI_Exported_Functions_Group3 624 * @{ 625 */ 626 /* Peripheral Control and State functions ************************************/ 627 HAL_QSPI_StateTypeDef HAL_QSPI_GetState (QSPI_HandleTypeDef *hqspi); 628 uint32_t HAL_QSPI_GetError (QSPI_HandleTypeDef *hqspi); 629 HAL_StatusTypeDef HAL_QSPI_Abort (QSPI_HandleTypeDef *hqspi); 630 HAL_StatusTypeDef HAL_QSPI_Abort_IT (QSPI_HandleTypeDef *hqspi); 631 void HAL_QSPI_SetTimeout (QSPI_HandleTypeDef *hqspi, uint32_t Timeout); 632 HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t Threshold); 633 uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi); 634 HAL_StatusTypeDef HAL_QSPI_SetFlashID (QSPI_HandleTypeDef *hqspi, uint32_t FlashID); 635 /** 636 * @} 637 */ 638 639 /** 640 * @} 641 */ 642 /* End of exported functions -------------------------------------------------*/ 643 644 /* Private macros ------------------------------------------------------------*/ 645 /** @defgroup QSPI_Private_Macros QSPI Private Macros 646 * @{ 647 */ 648 #define IS_QSPI_CLOCK_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFFU) 649 650 #define IS_QSPI_FIFO_THRESHOLD(THR) (((THR) > 0U) && ((THR) <= 32U)) 651 652 #define IS_QSPI_SSHIFT(SSHIFT) (((SSHIFT) == QSPI_SAMPLE_SHIFTING_NONE) || \ 653 ((SSHIFT) == QSPI_SAMPLE_SHIFTING_HALFCYCLE)) 654 655 #define IS_QSPI_FLASH_SIZE(FSIZE) (((FSIZE) <= 31U)) 656 657 #define IS_QSPI_CS_HIGH_TIME(CSHTIME) (((CSHTIME) == QSPI_CS_HIGH_TIME_1_CYCLE) || \ 658 ((CSHTIME) == QSPI_CS_HIGH_TIME_2_CYCLE) || \ 659 ((CSHTIME) == QSPI_CS_HIGH_TIME_3_CYCLE) || \ 660 ((CSHTIME) == QSPI_CS_HIGH_TIME_4_CYCLE) || \ 661 ((CSHTIME) == QSPI_CS_HIGH_TIME_5_CYCLE) || \ 662 ((CSHTIME) == QSPI_CS_HIGH_TIME_6_CYCLE) || \ 663 ((CSHTIME) == QSPI_CS_HIGH_TIME_7_CYCLE) || \ 664 ((CSHTIME) == QSPI_CS_HIGH_TIME_8_CYCLE)) 665 666 #define IS_QSPI_CLOCK_MODE(CLKMODE) (((CLKMODE) == QSPI_CLOCK_MODE_0) || \ 667 ((CLKMODE) == QSPI_CLOCK_MODE_3)) 668 669 #define IS_QSPI_FLASH_ID(FLASH_ID) (((FLASH_ID) == QSPI_FLASH_ID_1) || \ 670 ((FLASH_ID) == QSPI_FLASH_ID_2)) 671 672 #define IS_QSPI_DUAL_FLASH_MODE(MODE) (((MODE) == QSPI_DUALFLASH_ENABLE) || \ 673 ((MODE) == QSPI_DUALFLASH_DISABLE)) 674 675 #define IS_QSPI_INSTRUCTION(INSTRUCTION) ((INSTRUCTION) <= 0xFFU) 676 677 #define IS_QSPI_ADDRESS_SIZE(ADDR_SIZE) (((ADDR_SIZE) == QSPI_ADDRESS_8_BITS) || \ 678 ((ADDR_SIZE) == QSPI_ADDRESS_16_BITS) || \ 679 ((ADDR_SIZE) == QSPI_ADDRESS_24_BITS) || \ 680 ((ADDR_SIZE) == QSPI_ADDRESS_32_BITS)) 681 682 #define IS_QSPI_ALTERNATE_BYTES_SIZE(SIZE) (((SIZE) == QSPI_ALTERNATE_BYTES_8_BITS) || \ 683 ((SIZE) == QSPI_ALTERNATE_BYTES_16_BITS) || \ 684 ((SIZE) == QSPI_ALTERNATE_BYTES_24_BITS) || \ 685 ((SIZE) == QSPI_ALTERNATE_BYTES_32_BITS)) 686 687 #define IS_QSPI_DUMMY_CYCLES(DCY) ((DCY) <= 31U) 688 689 #define IS_QSPI_INSTRUCTION_MODE(MODE) (((MODE) == QSPI_INSTRUCTION_NONE) || \ 690 ((MODE) == QSPI_INSTRUCTION_1_LINE) || \ 691 ((MODE) == QSPI_INSTRUCTION_2_LINES) || \ 692 ((MODE) == QSPI_INSTRUCTION_4_LINES)) 693 694 #define IS_QSPI_ADDRESS_MODE(MODE) (((MODE) == QSPI_ADDRESS_NONE) || \ 695 ((MODE) == QSPI_ADDRESS_1_LINE) || \ 696 ((MODE) == QSPI_ADDRESS_2_LINES) || \ 697 ((MODE) == QSPI_ADDRESS_4_LINES)) 698 699 #define IS_QSPI_ALTERNATE_BYTES_MODE(MODE) (((MODE) == QSPI_ALTERNATE_BYTES_NONE) || \ 700 ((MODE) == QSPI_ALTERNATE_BYTES_1_LINE) || \ 701 ((MODE) == QSPI_ALTERNATE_BYTES_2_LINES) || \ 702 ((MODE) == QSPI_ALTERNATE_BYTES_4_LINES)) 703 704 #define IS_QSPI_DATA_MODE(MODE) (((MODE) == QSPI_DATA_NONE) || \ 705 ((MODE) == QSPI_DATA_1_LINE) || \ 706 ((MODE) == QSPI_DATA_2_LINES) || \ 707 ((MODE) == QSPI_DATA_4_LINES)) 708 709 #define IS_QSPI_DDR_MODE(DDR_MODE) (((DDR_MODE) == QSPI_DDR_MODE_DISABLE) || \ 710 ((DDR_MODE) == QSPI_DDR_MODE_ENABLE)) 711 712 #define IS_QSPI_DDR_HHC(DDR_HHC) (((DDR_HHC) == QSPI_DDR_HHC_ANALOG_DELAY) || \ 713 ((DDR_HHC) == QSPI_DDR_HHC_HALF_CLK_DELAY)) 714 715 #define IS_QSPI_SIOO_MODE(SIOO_MODE) (((SIOO_MODE) == QSPI_SIOO_INST_EVERY_CMD) || \ 716 ((SIOO_MODE) == QSPI_SIOO_INST_ONLY_FIRST_CMD)) 717 718 #define IS_QSPI_INTERVAL(INTERVAL) ((INTERVAL) <= QUADSPI_PIR_INTERVAL) 719 720 #define IS_QSPI_STATUS_BYTES_SIZE(SIZE) (((SIZE) >= 1U) && ((SIZE) <= 4U)) 721 722 #define IS_QSPI_MATCH_MODE(MODE) (((MODE) == QSPI_MATCH_MODE_AND) || \ 723 ((MODE) == QSPI_MATCH_MODE_OR)) 724 725 #define IS_QSPI_AUTOMATIC_STOP(APMS) (((APMS) == QSPI_AUTOMATIC_STOP_DISABLE) || \ 726 ((APMS) == QSPI_AUTOMATIC_STOP_ENABLE)) 727 728 #define IS_QSPI_TIMEOUT_ACTIVATION(TCEN) (((TCEN) == QSPI_TIMEOUT_COUNTER_DISABLE) || \ 729 ((TCEN) == QSPI_TIMEOUT_COUNTER_ENABLE)) 730 731 #define IS_QSPI_TIMEOUT_PERIOD(PERIOD) ((PERIOD) <= 0xFFFFU) 732 /** 733 * @} 734 */ 735 /* End of private macros -----------------------------------------------------*/ 736 737 /** 738 * @} 739 */ 740 741 /** 742 * @} 743 */ 744 745 #endif /* defined(QUADSPI) */ 746 747 #ifdef __cplusplus 748 } 749 #endif 750 751 #endif /* STM32MP1xx_HAL_QSPI_H */ 752
