1 /**
2 ******************************************************************************
3 * @file stm32l5xx_ll_pwr.h
4 * @author MCD Application Team
5 * @brief Header file of PWR LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2019 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file in
13 * the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 ******************************************************************************
16 */
17
18 /* Define to prevent recursive inclusion -------------------------------------*/
19 #ifndef STM32L5xx_LL_PWR_H
20 #define STM32L5xx_LL_PWR_H
21
22 #ifdef __cplusplus
23 extern "C" {
24 #endif
25
26 /* Includes ------------------------------------------------------------------*/
27 #include "stm32l5xx.h"
28
29 /** @addtogroup STM32L5xx_LL_Driver
30 * @{
31 */
32
33 #if defined(PWR)
34
35 /** @defgroup PWR_LL PWR
36 * @{
37 */
38
39 /* Private types -------------------------------------------------------------*/
40 /* Private variables ---------------------------------------------------------*/
41
42 /* Private constants ---------------------------------------------------------*/
43
44 /* Private macros ------------------------------------------------------------*/
45
46 /* Exported types ------------------------------------------------------------*/
47 /* Exported constants --------------------------------------------------------*/
48 /** @defgroup PWR_LL_Exported_Constants PWR Exported Constants
49 * @{
50 */
51
52 /** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines
53 * @brief Flags defines which can be used with LL_PWR_WriteReg function
54 * @{
55 */
56 #define LL_PWR_SCR_CSBF PWR_SCR_CSBF
57 #define LL_PWR_SCR_CWUF PWR_SCR_CWUF
58 #define LL_PWR_SCR_CWUF5 PWR_SCR_CWUF5
59 #define LL_PWR_SCR_CWUF4 PWR_SCR_CWUF4
60 #define LL_PWR_SCR_CWUF3 PWR_SCR_CWUF3
61 #define LL_PWR_SCR_CWUF2 PWR_SCR_CWUF2
62 #define LL_PWR_SCR_CWUF1 PWR_SCR_CWUF1
63 /**
64 * @}
65 */
66
67 /** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines
68 * @brief Flags defines which can be used with LL_PWR_ReadReg function
69 * @{
70 */
71 #define LL_PWR_SR1_SMSHPRDY PWR_SR1_SMSHPRDY
72 #define LL_PWR_SR1_EXTSMSRDY PWR_SR1_EXTSMSRDY
73 #define LL_PWR_SR1_SMSBYPRDY PWR_SR1_SMSBYPRDYY
74 #define LL_PWR_SR1_SBF PWR_SR1_SBF
75 #define LL_PWR_SR1_WUF5 PWR_SR1_WUF5
76 #define LL_PWR_SR1_WUF4 PWR_SR1_WUF4
77 #define LL_PWR_SR1_WUF3 PWR_SR1_WUF3
78 #define LL_PWR_SR1_WUF2 PWR_SR1_WUF2
79 #define LL_PWR_SR1_WUF1 PWR_SR1_WUF1
80 #define LL_PWR_SR2_PVMO4 PWR_SR2_PVMO4
81 #define LL_PWR_SR2_PVMO3 PWR_SR2_PVMO3
82 #define LL_PWR_SR2_PVMO2 PWR_SR2_PVMO2
83 #define LL_PWR_SR2_PVMO1 PWR_SR2_PVMO1
84 #define LL_PWR_SR2_PVDO PWR_SR2_PVDO
85 #define LL_PWR_SR2_VOSF PWR_SR2_VOSF
86 #define LL_PWR_SR2_REGLPF PWR_SR2_REGLPF
87 #define LL_PWR_SR2_REGLPS PWR_SR2_REGLPS
88 /**
89 * @}
90 */
91
92 /** @defgroup PWR_LL_EC_REGU_VOLTAGE REGU VOLTAGE
93 * @{
94 */
95 #define LL_PWR_REGU_VOLTAGE_SCALE0 0U
96 #define LL_PWR_REGU_VOLTAGE_SCALE1 (PWR_CR1_VOS_0)
97 #define LL_PWR_REGU_VOLTAGE_SCALE2 (PWR_CR1_VOS_1)
98 /**
99 * @}
100 */
101
102 /** @defgroup PWR_LL_EC_MODE_PWR MODE PWR
103 * @{
104 */
105 #define LL_PWR_MODE_STOP0 (PWR_CR1_LPMS_STOP0)
106 #define LL_PWR_MODE_STOP1 (PWR_CR1_LPMS_STOP1)
107 #define LL_PWR_MODE_STOP2 (PWR_CR1_LPMS_STOP2)
108 #define LL_PWR_MODE_STANDBY (PWR_CR1_LPMS_STANDBY)
109 #define LL_PWR_MODE_SHUTDOWN (PWR_CR1_LPMS_SHUTDOWN)
110 /**
111 * @}
112 */
113
114 /** @defgroup PWR_LL_EC_PVM_VDDUSB_1 Peripheral voltage monitoring
115 * @{
116 */
117 #define LL_PWR_PVM_VDDUSB_1_2V (PWR_CR2_PVME1) /* Monitoring VDDUSB vs. 1.2 V */
118 #define LL_PWR_PVM_VDDIO2_0_9V (PWR_CR2_PVME2) /* Monitoring VDDIO2 vs. 0.9 V */
119 #define LL_PWR_PVM_VDDA_1_62V (PWR_CR2_PVME3) /* Monitoring VDDA vs. 1.62 V */
120 #define LL_PWR_PVM_VDDA_1_8V (PWR_CR2_PVME4) /* Monitoring VDDA vs. 1.8 V */
121 /**
122 * @}
123 */
124
125 /** @defgroup PWR_LL_EC_PVDLEVEL PVDLEVEL
126 * @{
127 */
128 #define LL_PWR_PVDLEVEL_0 (PWR_CR2_PLS_LEV0) /* VPVD0 around 2.0 V */
129 #define LL_PWR_PVDLEVEL_1 (PWR_CR2_PLS_LEV1) /* VPVD1 around 2.2 V */
130 #define LL_PWR_PVDLEVEL_2 (PWR_CR2_PLS_LEV2) /* VPVD2 around 2.4 V */
131 #define LL_PWR_PVDLEVEL_3 (PWR_CR2_PLS_LEV3) /* VPVD3 around 2.5 V */
132 #define LL_PWR_PVDLEVEL_4 (PWR_CR2_PLS_LEV4) /* VPVD4 around 2.6 V */
133 #define LL_PWR_PVDLEVEL_5 (PWR_CR2_PLS_LEV5) /* VPVD5 around 2.8 V */
134 #define LL_PWR_PVDLEVEL_6 (PWR_CR2_PLS_LEV6) /* VPVD6 around 2.9 V */
135 #define LL_PWR_PVDLEVEL_7 (PWR_CR2_PLS_LEV7) /* External input analog voltage (Compare internally to VREFINT) */
136 /**
137 * @}
138 */
139
140 /** @defgroup PWR_LL_EC_WAKEUP WAKEUP
141 * @{
142 */
143 #define LL_PWR_WAKEUP_PIN1 (PWR_CR3_EWUP1)
144 #define LL_PWR_WAKEUP_PIN2 (PWR_CR3_EWUP2)
145 #define LL_PWR_WAKEUP_PIN3 (PWR_CR3_EWUP3)
146 #define LL_PWR_WAKEUP_PIN4 (PWR_CR3_EWUP4)
147 #define LL_PWR_WAKEUP_PIN5 (PWR_CR3_EWUP5)
148 /**
149 * @}
150 */
151
152 /** @defgroup PWR_LL_EC_BATT_CHARG_RESISTOR BATT CHARG RESISTOR
153 * @{
154 */
155 #define LL_PWR_BATT_CHARG_RESISTOR_5K (0x00000000U)
156 #define LL_PWR_BATT_CHARGRESISTOR_1_5K (PWR_CR4_VBRS)
157 /**
158 * @}
159 */
160
161 /** @defgroup PWR_LL_EC_GPIO GPIO
162 * @{
163 */
164 #define LL_PWR_GPIO_A ((uint32_t)(&(PWR->PUCRA)))
165 #define LL_PWR_GPIO_B ((uint32_t)(&(PWR->PUCRB)))
166 #define LL_PWR_GPIO_C ((uint32_t)(&(PWR->PUCRC)))
167 #define LL_PWR_GPIO_D ((uint32_t)(&(PWR->PUCRD)))
168 #define LL_PWR_GPIO_E ((uint32_t)(&(PWR->PUCRE)))
169 #define LL_PWR_GPIO_F ((uint32_t)(&(PWR->PUCRF)))
170 #define LL_PWR_GPIO_G ((uint32_t)(&(PWR->PUCRG)))
171 #define LL_PWR_GPIO_H ((uint32_t)(&(PWR->PUCRH)))
172 /**
173 * @}
174 */
175
176 /** @defgroup PWR_LL_EC_GPIO_BIT GPIO BIT
177 * @{
178 */
179 #define LL_PWR_GPIO_BIT_0 (0x00000001U)
180 #define LL_PWR_GPIO_BIT_1 (0x00000002U)
181 #define LL_PWR_GPIO_BIT_2 (0x00000004U)
182 #define LL_PWR_GPIO_BIT_3 (0x00000008U)
183 #define LL_PWR_GPIO_BIT_4 (0x00000010U)
184 #define LL_PWR_GPIO_BIT_5 (0x00000020U)
185 #define LL_PWR_GPIO_BIT_6 (0x00000040U)
186 #define LL_PWR_GPIO_BIT_7 (0x00000080U)
187 #define LL_PWR_GPIO_BIT_8 (0x00000100U)
188 #define LL_PWR_GPIO_BIT_9 (0x00000200U)
189 #define LL_PWR_GPIO_BIT_10 (0x00000400U)
190 #define LL_PWR_GPIO_BIT_11 (0x00000800U)
191 #define LL_PWR_GPIO_BIT_12 (0x00001000U)
192 #define LL_PWR_GPIO_BIT_13 (0x00002000U)
193 #define LL_PWR_GPIO_BIT_14 (0x00004000U)
194 #define LL_PWR_GPIO_BIT_15 (0x00008000U)
195 /**
196 * @}
197 */
198
199 /** @defgroup PWR_LL_EC_SRAM2_STANDBY_RETENTION SRAM2 STANDBY RETENTION
200 * @{
201 */
202 #define LL_PWR_SRAM2_NO_RETENTION 0x00000000U
203 #define LL_PWR_SRAM2_FULL_RETENTION (PWR_CR3_RRS_0)
204 #define LL_PWR_SRAM2_4KB_RETENTION (PWR_CR3_RRS_1)
205 /**
206 * @}
207 */
208
209 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
210 /** @defgroup PWR_LL_EC_SECURE_ATTRIBUTES SECURE ATTRIBUTES
211 * @{
212 */
213 #define LL_PWR_WAKEUP_PINS_SEC PWR_SECCFGR_WUPSEC
214 #define LL_PWR_WAKEUP_PINS_NSEC 0x00000000U
215 #define LL_PWR_WAKEUP_PIN1_SEC PWR_SECCFGR_WUP1SEC
216 #define LL_PWR_WAKEUP_PIN1_NSEC 0x00000000U
217 #define LL_PWR_WAKEUP_PIN2_SEC PWR_SECCFGR_WUP2SEC
218 #define LL_PWR_WAKEUP_PIN2_NSEC 0x00000000U
219 #define LL_PWR_WAKEUP_PIN3_SEC PWR_SECCFGR_WUP3SEC
220 #define LL_PWR_WAKEUP_PIN3_NSEC 0x00000000U
221 #define LL_PWR_WAKEUP_PIN4_SEC PWR_SECCFGR_WUP4SEC
222 #define LL_PWR_WAKEUP_PIN4_NSEC 0x00000000U
223 #define LL_PWR_WAKEUP_PIN5_SEC PWR_SECCFGR_WUP5SEC
224 #define LL_PWR_WAKEUP_PIN5_NSEC 0x00000000U
225 #define LL_PWR_LPM_SEC PWR_SECCFGR_LPMSEC
226 #define LL_PWR_LPM_NSEC 0x00000000U
227 #define LL_PWR_VDM_SEC PWR_SECCFGR_VDMSEC
228 #define LL_PWR_VDM_NSEC 0x00000000U
229 #define LL_PWR_VB_SEC PWR_SECCFGR_VBSEC
230 #define LL_PWR_VB_NSEC 0x00000000U
231 #define LL_PWR_APC_SEC PWR_SECCFGR_APCSEC
232 #define LL_PWR_APC_NSEC 0x00000000U
233 /**
234 * @}
235 */
236 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
237
238 /**
239 * @}
240 */
241
242 /* Exported macro ------------------------------------------------------------*/
243 /** @defgroup PWR_LL_Exported_Macros PWR Exported Macros
244 * @{
245 */
246
247 /** @defgroup PWR_LL_EM_WRITE_READ Common Write and read registers Macros
248 * @{
249 */
250
251 /**
252 * @brief Write a value in PWR register
253 * @param __REG__ Register to be written
254 * @param __VALUE__ Value to be written in the register
255 * @retval None
256 */
257 #define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__))
258
259 /**
260 * @brief Read a value in PWR register
261 * @param __REG__ Register to be read
262 * @retval Register value
263 */
264 #define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__)
265 /**
266 * @}
267 */
268
269 /**
270 * @}
271 */
272
273
274 /* Exported functions --------------------------------------------------------*/
275 /** @defgroup PWR_LL_Exported_Functions PWR Exported Functions
276 * @{
277 */
278
279 /** @defgroup PWR_LL_EF_Configuration Configuration
280 * @{
281 */
282
283 /**
284 * @brief Switch the regulator from main mode to low-power mode
285 * @rmtoll CR1 LPR LL_PWR_EnableLowPowerRunMode
286 * @retval None
287 */
LL_PWR_EnableLowPowerRunMode(void)288 __STATIC_INLINE void LL_PWR_EnableLowPowerRunMode(void)
289 {
290 SET_BIT(PWR->CR1, PWR_CR1_LPR);
291 }
292
293 /**
294 * @brief Switch the regulator from low-power mode to main mode
295 * @rmtoll CR1 LPR LL_PWR_DisableLowPowerRunMode
296 * @retval None
297 */
LL_PWR_DisableLowPowerRunMode(void)298 __STATIC_INLINE void LL_PWR_DisableLowPowerRunMode(void)
299 {
300 CLEAR_BIT(PWR->CR1, PWR_CR1_LPR);
301 }
302
303 /**
304 * @brief Check if the regulator is in low-power mode
305 * @rmtoll CR1 LPR LL_PWR_IsEnabledLowPowerRunMode
306 * @retval State of bit (1 or 0).
307 */
LL_PWR_IsEnabledLowPowerRunMode(void)308 __STATIC_INLINE uint32_t LL_PWR_IsEnabledLowPowerRunMode(void)
309 {
310 return ((READ_BIT(PWR->CR1, PWR_CR1_LPR) == (PWR_CR1_LPR)) ? 1UL : 0UL);
311 }
312
313 /**
314 * @brief Switch from run main mode to run low-power mode.
315 * @rmtoll CR1 LPR LL_PWR_EnterLowPowerRunMode
316 * @retval None
317 */
LL_PWR_EnterLowPowerRunMode(void)318 __STATIC_INLINE void LL_PWR_EnterLowPowerRunMode(void)
319 {
320 LL_PWR_EnableLowPowerRunMode();
321 }
322
323 /**
324 * @brief Switch from run main mode to low-power mode.
325 * @rmtoll CR1 LPR LL_PWR_ExitLowPowerRunMode
326 * @retval None
327 */
LL_PWR_ExitLowPowerRunMode(void)328 __STATIC_INLINE void LL_PWR_ExitLowPowerRunMode(void)
329 {
330 LL_PWR_DisableLowPowerRunMode();
331 }
332
333 /**
334 * @brief Set the main internal regulator output voltage
335 * @rmtoll CR1 VOS LL_PWR_SetRegulVoltageScaling
336 * @param VoltageScaling This parameter can be one of the following values:
337 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE0
338 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1
339 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
340 * @retval None
341 */
LL_PWR_SetRegulVoltageScaling(uint32_t VoltageScaling)342 __STATIC_INLINE void LL_PWR_SetRegulVoltageScaling(uint32_t VoltageScaling)
343 {
344 MODIFY_REG(PWR->CR1, PWR_CR1_VOS, VoltageScaling);
345 }
346
347 /**
348 * @brief Get the main internal regulator output voltage
349 * @rmtoll CR1 VOS LL_PWR_GetRegulVoltageScaling
350 * @retval Returned value can be one of the following values:
351 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE0
352 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1
353 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
354 */
LL_PWR_GetRegulVoltageScaling(void)355 __STATIC_INLINE uint32_t LL_PWR_GetRegulVoltageScaling(void)
356 {
357 return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_VOS));
358 }
359
360 /**
361 * @brief Enable access to the backup domain
362 * @rmtoll CR1 DBP LL_PWR_EnableBkUpAccess
363 * @retval None
364 */
LL_PWR_EnableBkUpAccess(void)365 __STATIC_INLINE void LL_PWR_EnableBkUpAccess(void)
366 {
367 SET_BIT(PWR->CR1, PWR_CR1_DBP);
368 }
369
370 /**
371 * @brief Disable access to the backup domain
372 * @rmtoll CR1 DBP LL_PWR_DisableBkUpAccess
373 * @retval None
374 */
LL_PWR_DisableBkUpAccess(void)375 __STATIC_INLINE void LL_PWR_DisableBkUpAccess(void)
376 {
377 CLEAR_BIT(PWR->CR1, PWR_CR1_DBP);
378 }
379
380 /**
381 * @brief Check if the backup domain is enabled
382 * @rmtoll CR1 DBP LL_PWR_IsEnabledBkUpAccess
383 * @retval State of bit (1 or 0).
384 */
LL_PWR_IsEnabledBkUpAccess(void)385 __STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void)
386 {
387 return ((READ_BIT(PWR->CR1, PWR_CR1_DBP) == (PWR_CR1_DBP)) ? 1UL : 0UL);
388 }
389
390 /**
391 * @brief Set Low-Power mode
392 * @rmtoll CR1 LPMS LL_PWR_SetPowerMode
393 * @param LowPowerMode This parameter can be one of the following values:
394 * @arg @ref LL_PWR_MODE_STOP0
395 * @arg @ref LL_PWR_MODE_STOP1
396 * @arg @ref LL_PWR_MODE_STOP2
397 * @arg @ref LL_PWR_MODE_STANDBY
398 * @arg @ref LL_PWR_MODE_SHUTDOWN
399 * @retval None
400 */
LL_PWR_SetPowerMode(uint32_t LowPowerMode)401 __STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t LowPowerMode)
402 {
403 MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, LowPowerMode);
404 }
405
406 /**
407 * @brief Get Low-Power mode
408 * @rmtoll CR1 LPMS LL_PWR_GetPowerMode
409 * @retval Returned value can be one of the following values:
410 * @arg @ref LL_PWR_MODE_STOP0
411 * @arg @ref LL_PWR_MODE_STOP1
412 * @arg @ref LL_PWR_MODE_STOP2
413 * @arg @ref LL_PWR_MODE_STANDBY
414 * @arg @ref LL_PWR_MODE_SHUTDOWN
415 */
LL_PWR_GetPowerMode(void)416 __STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void)
417 {
418 return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_LPMS));
419 }
420
421 /**
422 * @brief Enable the USB Type-C and Power Delivery memorization in Standby mode.
423 * @note This function must be called just before entering Standby mode.
424 * @rmtoll CR3 UCPD_STDBY LL_PWR_EnableUCPDStandbyMode
425 * @retval None
426 */
LL_PWR_EnableUCPDStandbyMode(void)427 __STATIC_INLINE void LL_PWR_EnableUCPDStandbyMode(void)
428 {
429 SET_BIT(PWR->CR3, PWR_CR3_UCPD_STDBY);
430 }
431
432 /**
433 * @brief Disable the USB Type-C and Power Delivery memorization in Standby mode.
434 * @note This function must be called after exiting Standby mode and before any
435 * UCPD configuration update.
436 * @rmtoll CR3 UCPD_STDBY LL_PWR_DisableUCPDStandbyMode
437 * @retval None
438 */
LL_PWR_DisableUCPDStandbyMode(void)439 __STATIC_INLINE void LL_PWR_DisableUCPDStandbyMode(void)
440 {
441 CLEAR_BIT(PWR->CR3, PWR_CR3_UCPD_STDBY);
442 }
443
444 /**
445 * @brief Check the USB Type-C and Power Delivery Standby mode memorization state.
446 * @rmtoll CR3 UCPD_STDBY LL_PWR_IsEnabledUCPDStandbyMode
447 * @retval State of bit (1 or 0).
448 */
LL_PWR_IsEnabledUCPDStandbyMode(void)449 __STATIC_INLINE uint32_t LL_PWR_IsEnabledUCPDStandbyMode(void)
450 {
451
452 return ((READ_BIT(PWR->CR3, PWR_CR3_UCPD_STDBY) == (PWR_CR3_UCPD_STDBY)) ? 1UL : 0UL);
453
454 }
455
456 /**
457 * @brief Enable the USB Type-C and power delivery dead battery pull-down behavior
458 * on UCPD CC1 and CC2 pins.
459 * @note After exiting reset, the USB Type-C dead battery behavior is enabled,
460 * which may have a pull-down effect on CC1 and CC2 pins. It is recommended
461 * to disable it in all cases, either to stop this pull-down or to hand over
462 * control to the UCPD (which should therefore be initialized before doing the disable).
463 * @rmtoll CR3 UCPD_DBDIS LL_PWR_EnableUCPDDeadBattery
464 * @retval None
465 */
LL_PWR_EnableUCPDDeadBattery(void)466 __STATIC_INLINE void LL_PWR_EnableUCPDDeadBattery(void)
467 {
468 CLEAR_BIT(PWR->CR3, PWR_CR3_UCPD_DBDIS);
469 }
470
471 /**
472 * @brief Disable the USB Type-C and power delivery dead battery pull-down behavior
473 * on UCPD CC1 and CC2 pins.
474 * @note After exiting reset, the USB Type-C dead battery behavior is enabled,
475 * which may have a pull-down effect on CC1 and CC2 pins. It is recommended
476 * to disable it in all cases, either to stop this pull-down or to hand over
477 * control to the UCPD (which should therefore be initialized before doing the disable).
478 * @rmtoll CR3 UCPD_DBDIS LL_PWR_DisableUCPDDeadBattery
479 * @retval None
480 */
LL_PWR_DisableUCPDDeadBattery(void)481 __STATIC_INLINE void LL_PWR_DisableUCPDDeadBattery(void)
482 {
483 SET_BIT(PWR->CR3, PWR_CR3_UCPD_DBDIS);
484 }
485
486 /**
487 * @brief Check the USB Type-C and power delivery dead battery pull-down behavior
488 * on UCPD CC1 and CC2 pins.
489 * @note After exiting reset, the USB Type-C dead battery behavior is enabled,
490 * which may have a pull-down effect on CC1 and CC2 pins. It is recommended
491 * to disable it in all cases, either to stop this pull-down or to hand over
492 * control to the UCPD (which should therefore be initialized before doing the disable).
493 * @rmtoll CR3 UCPD_DBDIS LL_PWR_IsEnabledUCPDDeadBattery
494 * @retval State of feature (1 : enabled; 0 : disabled).
495 */
LL_PWR_IsEnabledUCPDDeadBattery(void)496 __STATIC_INLINE uint32_t LL_PWR_IsEnabledUCPDDeadBattery(void)
497 {
498 return ((READ_BIT(PWR->CR3, PWR_CR3_UCPD_DBDIS) == (PWR_CR3_UCPD_DBDIS)) ? 0UL : 1UL);
499 }
500
501 /**
502 * @brief Enable VDDUSB supply
503 * @rmtoll CR2 USV LL_PWR_EnableVddUSB
504 * @retval None
505 */
LL_PWR_EnableVddUSB(void)506 __STATIC_INLINE void LL_PWR_EnableVddUSB(void)
507 {
508 SET_BIT(PWR->CR2, PWR_CR2_USV);
509 }
510
511 /**
512 * @brief Disable VDDUSB supply
513 * @rmtoll CR2 USV LL_PWR_DisableVddUSB
514 * @retval None
515 */
LL_PWR_DisableVddUSB(void)516 __STATIC_INLINE void LL_PWR_DisableVddUSB(void)
517 {
518 CLEAR_BIT(PWR->CR2, PWR_CR2_USV);
519 }
520
521 /**
522 * @brief Check if VDDUSB supply is enabled
523 * @rmtoll CR2 USV LL_PWR_IsEnabledVddUSB
524 * @retval State of bit (1 or 0).
525 */
LL_PWR_IsEnabledVddUSB(void)526 __STATIC_INLINE uint32_t LL_PWR_IsEnabledVddUSB(void)
527 {
528 return ((READ_BIT(PWR->CR2, PWR_CR2_USV) == (PWR_CR2_USV)) ? 1UL : 0UL);
529 }
530
531 /**
532 * @brief Enable VDDIO2 supply
533 * @rmtoll CR2 IOSV LL_PWR_EnableVddIO2
534 * @retval None
535 */
LL_PWR_EnableVddIO2(void)536 __STATIC_INLINE void LL_PWR_EnableVddIO2(void)
537 {
538 SET_BIT(PWR->CR2, PWR_CR2_IOSV);
539 }
540
541 /**
542 * @brief Disable VDDIO2 supply
543 * @rmtoll CR2 IOSV LL_PWR_DisableVddIO2
544 * @retval None
545 */
LL_PWR_DisableVddIO2(void)546 __STATIC_INLINE void LL_PWR_DisableVddIO2(void)
547 {
548 CLEAR_BIT(PWR->CR2, PWR_CR2_IOSV);
549 }
550
551 /**
552 * @brief Check if VDDIO2 supply is enabled
553 * @rmtoll CR2 IOSV LL_PWR_IsEnabledVddIO2
554 * @retval State of bit (1 or 0).
555 */
LL_PWR_IsEnabledVddIO2(void)556 __STATIC_INLINE uint32_t LL_PWR_IsEnabledVddIO2(void)
557 {
558 return ((READ_BIT(PWR->CR2, PWR_CR2_IOSV) == (PWR_CR2_IOSV)) ? 1UL : 0UL);
559 }
560
561 /**
562 * @brief Enable the Power Voltage Monitoring on a peripheral
563 * @rmtoll CR2 PVME1 LL_PWR_EnablePVM\n
564 * CR2 PVME2 LL_PWR_EnablePVM\n
565 * CR2 PVME3 LL_PWR_EnablePVM\n
566 * CR2 PVME4 LL_PWR_EnablePVM
567 * @param PeriphVoltage This parameter can be one of the following values:
568 * @arg @ref LL_PWR_PVM_VDDUSB_1_2V
569 * @arg @ref LL_PWR_PVM_VDDIO2_0_9V
570 * @arg @ref LL_PWR_PVM_VDDA_1_62V
571 * @arg @ref LL_PWR_PVM_VDDA_1_8V
572 * @retval None
573 */
LL_PWR_EnablePVM(uint32_t PeriphVoltage)574 __STATIC_INLINE void LL_PWR_EnablePVM(uint32_t PeriphVoltage)
575 {
576 SET_BIT(PWR->CR2, PeriphVoltage);
577 }
578
579 /**
580 * @brief Disable the Power Voltage Monitoring on a peripheral
581 * @rmtoll CR2 PVME1 LL_PWR_DisablePVM\n
582 * CR2 PVME2 LL_PWR_DisablePVM\n
583 * CR2 PVME3 LL_PWR_DisablePVM\n
584 * CR2 PVME4 LL_PWR_DisablePVM
585 * @param PeriphVoltage This parameter can be one of the following values:
586 * @arg @ref LL_PWR_PVM_VDDUSB_1_2V
587 * @arg @ref LL_PWR_PVM_VDDIO2_0_9V
588 * @arg @ref LL_PWR_PVM_VDDA_1_62V
589 * @arg @ref LL_PWR_PVM_VDDA_1_8V
590 * @retval None
591 */
LL_PWR_DisablePVM(uint32_t PeriphVoltage)592 __STATIC_INLINE void LL_PWR_DisablePVM(uint32_t PeriphVoltage)
593 {
594 CLEAR_BIT(PWR->CR2, PeriphVoltage);
595 }
596
597 /**
598 * @brief Check if Power Voltage Monitoring is enabled on a peripheral
599 * @rmtoll CR2 PVME1 LL_PWR_IsEnabledPVM\n
600 * CR2 PVME2 LL_PWR_IsEnabledPVM\n
601 * CR2 PVME3 LL_PWR_IsEnabledPVM\n
602 * CR2 PVME4 LL_PWR_IsEnabledPVM
603 * @param PeriphVoltage This parameter can be one of the following values:
604 * @arg @ref LL_PWR_PVM_VDDUSB_1_2V
605 * @arg @ref LL_PWR_PVM_VDDIO2_0_9V
606 * @arg @ref LL_PWR_PVM_VDDA_1_62V
607 * @arg @ref LL_PWR_PVM_VDDA_1_8V
608 * @retval State of bit (1 or 0).
609 */
LL_PWR_IsEnabledPVM(uint32_t PeriphVoltage)610 __STATIC_INLINE uint32_t LL_PWR_IsEnabledPVM(uint32_t PeriphVoltage)
611 {
612 return ((READ_BIT(PWR->CR2, PeriphVoltage) == (PeriphVoltage)) ? 1UL : 0UL);
613 }
614
615 /**
616 * @brief Configure the voltage threshold detected by the Power Voltage Detector
617 * @rmtoll CR2 PLS LL_PWR_SetPVDLevel
618 * @param PVDLevel This parameter can be one of the following values:
619 * @arg @ref LL_PWR_PVDLEVEL_0
620 * @arg @ref LL_PWR_PVDLEVEL_1
621 * @arg @ref LL_PWR_PVDLEVEL_2
622 * @arg @ref LL_PWR_PVDLEVEL_3
623 * @arg @ref LL_PWR_PVDLEVEL_4
624 * @arg @ref LL_PWR_PVDLEVEL_5
625 * @arg @ref LL_PWR_PVDLEVEL_6
626 * @arg @ref LL_PWR_PVDLEVEL_7
627 * @retval None
628 */
LL_PWR_SetPVDLevel(uint32_t PVDLevel)629 __STATIC_INLINE void LL_PWR_SetPVDLevel(uint32_t PVDLevel)
630 {
631 MODIFY_REG(PWR->CR2, PWR_CR2_PLS, PVDLevel);
632 }
633
634 /**
635 * @brief Get the voltage threshold detection
636 * @rmtoll CR2 PLS LL_PWR_GetPVDLevel
637 * @retval Returned value can be one of the following values:
638 * @arg @ref LL_PWR_PVDLEVEL_0
639 * @arg @ref LL_PWR_PVDLEVEL_1
640 * @arg @ref LL_PWR_PVDLEVEL_2
641 * @arg @ref LL_PWR_PVDLEVEL_3
642 * @arg @ref LL_PWR_PVDLEVEL_4
643 * @arg @ref LL_PWR_PVDLEVEL_5
644 * @arg @ref LL_PWR_PVDLEVEL_6
645 * @arg @ref LL_PWR_PVDLEVEL_7
646 */
LL_PWR_GetPVDLevel(void)647 __STATIC_INLINE uint32_t LL_PWR_GetPVDLevel(void)
648 {
649 return (uint32_t)(READ_BIT(PWR->CR2, PWR_CR2_PLS));
650 }
651
652 /**
653 * @brief Enable Power Voltage Detector
654 * @rmtoll CR2 PVDE LL_PWR_EnablePVD
655 * @retval None
656 */
LL_PWR_EnablePVD(void)657 __STATIC_INLINE void LL_PWR_EnablePVD(void)
658 {
659 SET_BIT(PWR->CR2, PWR_CR2_PVDE);
660 }
661
662 /**
663 * @brief Disable Power Voltage Detector
664 * @rmtoll CR2 PVDE LL_PWR_DisablePVD
665 * @retval None
666 */
LL_PWR_DisablePVD(void)667 __STATIC_INLINE void LL_PWR_DisablePVD(void)
668 {
669 CLEAR_BIT(PWR->CR2, PWR_CR2_PVDE);
670 }
671
672 /**
673 * @brief Check if Power Voltage Detector is enabled
674 * @rmtoll CR2 PVDE LL_PWR_IsEnabledPVD
675 * @retval State of bit (1 or 0).
676 */
LL_PWR_IsEnabledPVD(void)677 __STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void)
678 {
679 return ((READ_BIT(PWR->CR2, PWR_CR2_PVDE) == (PWR_CR2_PVDE)) ? 1UL : 0UL);
680 }
681
682 /**
683 * @brief Enable SMPS low-power mode
684 * @rmtoll CR4 SMPSLPEN LL_PWR_EnableSMPSLowPowerMode
685 * @retval None
686 */
LL_PWR_EnableSMPSLowPowerMode(void)687 __STATIC_INLINE void LL_PWR_EnableSMPSLowPowerMode(void)
688 {
689 SET_BIT(PWR->CR4, PWR_CR4_SMPSLPEN);
690 }
691
692 /**
693 * @brief Disable SMPS low-power mode
694 * @rmtoll CR4 SMPSLPEN LL_PWR_DisableSMPSLowPowerMode
695 * @retval None
696 */
LL_PWR_DisableSMPSLowPowerMode(void)697 __STATIC_INLINE void LL_PWR_DisableSMPSLowPowerMode(void)
698 {
699 CLEAR_BIT(PWR->CR4, PWR_CR4_SMPSLPEN);
700 }
701
702 /**
703 * @brief Check if SMPS low-power mode is enabled
704 * @rmtoll CR4 SMPSLPEN LL_PWR_IsEnabledSMPSLowPowerMode
705 * @retval State of bit (1 or 0).
706 */
LL_PWR_IsEnabledSMPSLowPowerMode(void)707 __STATIC_INLINE uint32_t LL_PWR_IsEnabledSMPSLowPowerMode(void)
708 {
709 return ((READ_BIT(PWR->CR4, PWR_CR4_SMPSLPEN) == (PWR_CR4_SMPSLPEN)) ? 1UL : 0UL);
710 }
711
712 /**
713 * @brief Enable SMPS fast start
714 * @rmtoll CR4 SMPSFSTEN LL_PWR_EnableSMPSFastStart
715 * @retval None
716 */
LL_PWR_EnableSMPSFastStart(void)717 __STATIC_INLINE void LL_PWR_EnableSMPSFastStart(void)
718 {
719 SET_BIT(PWR->CR4, PWR_CR4_SMPSFSTEN);
720 }
721
722 /**
723 * @brief Disable SMPS fast start
724 * @rmtoll CR4 SMPSFSTEN LL_PWR_DisableSMPSFastStart
725 * @retval None
726 */
LL_PWR_DisableSMPSFastStart(void)727 __STATIC_INLINE void LL_PWR_DisableSMPSFastStart(void)
728 {
729 CLEAR_BIT(PWR->CR4, PWR_CR4_SMPSFSTEN);
730 }
731
732 /**
733 * @brief Check if SMPS fast start is enabled
734 * @rmtoll CR4 SMPSFSTEN LL_PWR_IsEnabledSMPSFastStart
735 * @retval State of bit (1 or 0).
736 */
LL_PWR_IsEnabledSMPSFastStart(void)737 __STATIC_INLINE uint32_t LL_PWR_IsEnabledSMPSFastStart(void)
738 {
739 return ((READ_BIT(PWR->CR4, PWR_CR4_SMPSFSTEN) == (PWR_CR4_SMPSFSTEN)) ? 1UL : 0UL);
740 }
741
742 /**
743 * @brief Enable SMPS bypass mode
744 * @rmtoll CR4 SMPSBYP LL_PWR_EnableSMPSBypassMode
745 * @retval None
746 */
LL_PWR_EnableSMPSBypassMode(void)747 __STATIC_INLINE void LL_PWR_EnableSMPSBypassMode(void)
748 {
749 SET_BIT(PWR->CR4, PWR_CR4_SMPSBYP);
750 }
751
752 /**
753 * @brief Disable SMPS bypass mode
754 * @rmtoll CR4 SMPSBYP LL_PWR_DisableSMPSBypassMode
755 * @retval None
756 */
LL_PWR_DisableSMPSBypassMode(void)757 __STATIC_INLINE void LL_PWR_DisableSMPSBypassMode(void)
758 {
759 CLEAR_BIT(PWR->CR4, PWR_CR4_SMPSBYP);
760 }
761
762 /**
763 * @brief Check if SMPS bypass mode is enabled
764 * @rmtoll CR4 SMPSBYP LL_PWR_IsEnabledSMPSBypassMode
765 * @retval State of bit (1 or 0).
766 */
LL_PWR_IsEnabledSMPSBypassMode(void)767 __STATIC_INLINE uint32_t LL_PWR_IsEnabledSMPSBypassMode(void)
768 {
769 return ((READ_BIT(PWR->CR4, PWR_CR4_SMPSBYP) == (PWR_CR4_SMPSBYP)) ? 1UL : 0UL);
770 }
771
772 /**
773 * @brief Enable external SMPS
774 * @rmtoll CR4 EXTSMPSEN LL_PWR_EnableExtSMPS
775 * @retval None
776 */
LL_PWR_EnableExtSMPS(void)777 __STATIC_INLINE void LL_PWR_EnableExtSMPS(void)
778 {
779 SET_BIT(PWR->CR4, PWR_CR4_EXTSMPSEN);
780 }
781
782 /**
783 * @brief Disable external SMPS
784 * @rmtoll CR4 EXTSMPSEN LL_PWR_DisableExtSMPS
785 * @retval None
786 */
LL_PWR_DisableExtSMPS(void)787 __STATIC_INLINE void LL_PWR_DisableExtSMPS(void)
788 {
789 CLEAR_BIT(PWR->CR4, PWR_CR4_EXTSMPSEN);
790 }
791
792 /**
793 * @brief Check if external SMPS is enabled
794 * @rmtoll CR4 EXTSMPSEN LL_PWR_IsEnabledExtSMPS
795 * @retval State of bit (1 or 0).
796 */
LL_PWR_IsEnabledExtSMPS(void)797 __STATIC_INLINE uint32_t LL_PWR_IsEnabledExtSMPS(void)
798 {
799 return ((READ_BIT(PWR->CR4, PWR_CR4_EXTSMPSEN) == (PWR_CR4_EXTSMPSEN)) ? 1UL : 0UL);
800 }
801
802 /**
803 * @brief Enable ultra low-power mode
804 * @rmtoll CR3 UPLMEN LL_PWR_EnableUltraLowPowerMode
805 * @retval None
806 */
LL_PWR_EnableUltraLowPowerMode(void)807 __STATIC_INLINE void LL_PWR_EnableUltraLowPowerMode(void)
808 {
809 SET_BIT(PWR->CR3, PWR_CR3_ULPMEN);
810 }
811
812 /**
813 * @brief Disable ultra low-power mode
814 * @rmtoll CR3 UPLMEN LL_PWR_DisableUltraLowPowerMode
815 * @retval None
816 */
LL_PWR_DisableUltraLowPowerMode(void)817 __STATIC_INLINE void LL_PWR_DisableUltraLowPowerMode(void)
818 {
819 CLEAR_BIT(PWR->CR3, PWR_CR3_ULPMEN);
820 }
821
822 /**
823 * @brief Check if ultra low-power mode is enabled
824 * @rmtoll CR3 UPLMEN LL_PWR_IsEnabledUltraLowPowerMode
825 * @retval State of bit (1 or 0).
826 */
LL_PWR_IsEnabledUltraLowPowerMode(void)827 __STATIC_INLINE uint32_t LL_PWR_IsEnabledUltraLowPowerMode(void)
828 {
829 return ((READ_BIT(PWR->CR3, PWR_CR3_ULPMEN) == (PWR_CR3_ULPMEN)) ? 1UL : 0UL);
830 }
831
832 /**
833 * @brief Enable pull-up and pull-down configuration
834 * @rmtoll CR3 APC LL_PWR_EnablePUPDCfg
835 * @retval None
836 */
LL_PWR_EnablePUPDCfg(void)837 __STATIC_INLINE void LL_PWR_EnablePUPDCfg(void)
838 {
839 SET_BIT(PWR->CR3, PWR_CR3_APC);
840 }
841
842 /**
843 * @brief Disable pull-up and pull-down configuration
844 * @rmtoll CR3 APC LL_PWR_DisablePUPDCfg
845 * @retval None
846 */
LL_PWR_DisablePUPDCfg(void)847 __STATIC_INLINE void LL_PWR_DisablePUPDCfg(void)
848 {
849 CLEAR_BIT(PWR->CR3, PWR_CR3_APC);
850 }
851
852 /**
853 * @brief Check if pull-up and pull-down configuration is enabled
854 * @rmtoll CR3 APC LL_PWR_IsEnabledPUPDCfg
855 * @retval State of bit (1 or 0).
856 */
LL_PWR_IsEnabledPUPDCfg(void)857 __STATIC_INLINE uint32_t LL_PWR_IsEnabledPUPDCfg(void)
858 {
859 return ((READ_BIT(PWR->CR3, PWR_CR3_APC) == (PWR_CR3_APC)) ? 1UL : 0UL);
860 }
861
862 /**
863 * @brief Set the SRAM2 retention in Standby mode
864 * @rmtoll CR3 RRS LL_PWR_SetSRAM2Retention
865 * @param SRAM2Retention This parameter can be one of the following values:
866 * @arg @ref LL_PWR_SRAM2_NO_RETENTION
867 * @arg @ref LL_PWR_SRAM2_FULL_RETENTION
868 * @arg @ref LL_PWR_SRAM2_4KB_RETENTION
869 * @retval None
870 */
LL_PWR_SetSRAM2Retention(uint32_t SRAM2Retention)871 __STATIC_INLINE void LL_PWR_SetSRAM2Retention(uint32_t SRAM2Retention)
872 {
873 MODIFY_REG(PWR->CR3, PWR_CR3_RRS, SRAM2Retention);
874 }
875
876 /**
877 * @brief Get the SRAM2 retention in Standby mode
878 * @rmtoll CR3 RRS LL_PWR_GetSRAM2Retention
879 * @retval Returned value can be one of the following values:
880 * @arg @ref LL_PWR_SRAM2_NO_RETENTION
881 * @arg @ref LL_PWR_SRAM2_FULL_RETENTION
882 * @arg @ref LL_PWR_SRAM2_4KB_RETENTION
883 */
LL_PWR_GetSRAM2Retention(void)884 __STATIC_INLINE uint32_t LL_PWR_GetSRAM2Retention(void)
885 {
886 return (uint32_t)(READ_BIT(PWR->CR3, PWR_CR3_RRS));
887 }
888
889 /**
890 * @brief Enable the WakeUp PINx functionality
891 * @rmtoll CR3 EWUP1 LL_PWR_EnableWakeUpPin\n
892 * CR3 EWUP2 LL_PWR_EnableWakeUpPin\n
893 * CR3 EWUP3 LL_PWR_EnableWakeUpPin\n
894 * CR3 EWUP4 LL_PWR_EnableWakeUpPin\n
895 * CR3 EWUP5 LL_PWR_EnableWakeUpPin\n
896 * @param WakeUpPin This parameter can be one of the following values:
897 * @arg @ref LL_PWR_WAKEUP_PIN1
898 * @arg @ref LL_PWR_WAKEUP_PIN2
899 * @arg @ref LL_PWR_WAKEUP_PIN3
900 * @arg @ref LL_PWR_WAKEUP_PIN4
901 * @arg @ref LL_PWR_WAKEUP_PIN5
902 * @retval None
903 */
LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin)904 __STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin)
905 {
906 SET_BIT(PWR->CR3, WakeUpPin);
907 }
908
909 /**
910 * @brief Disable the WakeUp PINx functionality
911 * @rmtoll CR3 EWUP1 LL_PWR_DisableWakeUpPin\n
912 * CR3 EWUP2 LL_PWR_DisableWakeUpPin\n
913 * CR3 EWUP3 LL_PWR_DisableWakeUpPin\n
914 * CR3 EWUP4 LL_PWR_DisableWakeUpPin\n
915 * CR3 EWUP5 LL_PWR_DisableWakeUpPin\n
916 * @param WakeUpPin This parameter can be one of the following values:
917 * @arg @ref LL_PWR_WAKEUP_PIN1
918 * @arg @ref LL_PWR_WAKEUP_PIN2
919 * @arg @ref LL_PWR_WAKEUP_PIN3
920 * @arg @ref LL_PWR_WAKEUP_PIN4
921 * @arg @ref LL_PWR_WAKEUP_PIN5
922 * @retval None
923 */
LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin)924 __STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin)
925 {
926 CLEAR_BIT(PWR->CR3, WakeUpPin);
927 }
928
929 /**
930 * @brief Check if the WakeUp PINx functionality is enabled
931 * @rmtoll CR3 EWUP1 LL_PWR_IsEnabledWakeUpPin\n
932 * CR3 EWUP2 LL_PWR_IsEnabledWakeUpPin\n
933 * CR3 EWUP3 LL_PWR_IsEnabledWakeUpPin\n
934 * CR3 EWUP4 LL_PWR_IsEnabledWakeUpPin\n
935 * CR3 EWUP5 LL_PWR_IsEnabledWakeUpPin\n
936 * @param WakeUpPin This parameter can be one of the following values:
937 * @arg @ref LL_PWR_WAKEUP_PIN1
938 * @arg @ref LL_PWR_WAKEUP_PIN2
939 * @arg @ref LL_PWR_WAKEUP_PIN3
940 * @arg @ref LL_PWR_WAKEUP_PIN4
941 * @arg @ref LL_PWR_WAKEUP_PIN5
942 * @retval State of bit (1 or 0).
943 */
LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)944 __STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)
945 {
946 return ((READ_BIT(PWR->CR3, WakeUpPin) == (WakeUpPin)) ? 1UL : 0UL);
947 }
948
949 /**
950 * @brief Set the resistor impedance
951 * @rmtoll CR4 VBRS LL_PWR_SetBattChargResistor
952 * @param Resistor This parameter can be one of the following values:
953 * @arg @ref LL_PWR_BATT_CHARG_RESISTOR_5K
954 * @arg @ref LL_PWR_BATT_CHARGRESISTOR_1_5K
955 * @retval None
956 */
LL_PWR_SetBattChargResistor(uint32_t Resistor)957 __STATIC_INLINE void LL_PWR_SetBattChargResistor(uint32_t Resistor)
958 {
959 MODIFY_REG(PWR->CR4, PWR_CR4_VBRS, Resistor);
960 }
961
962 /**
963 * @brief Get the resistor impedance
964 * @rmtoll CR4 VBRS LL_PWR_GetBattChargResistor
965 * @retval Returned value can be one of the following values:
966 * @arg @ref LL_PWR_BATT_CHARG_RESISTOR_5K
967 * @arg @ref LL_PWR_BATT_CHARGRESISTOR_1_5K
968 */
LL_PWR_GetBattChargResistor(void)969 __STATIC_INLINE uint32_t LL_PWR_GetBattChargResistor(void)
970 {
971 return (uint32_t)(READ_BIT(PWR->CR4, PWR_CR4_VBRS));
972 }
973
974 /**
975 * @brief Enable battery charging
976 * @rmtoll CR4 VBE LL_PWR_EnableBatteryCharging
977 * @retval None
978 */
LL_PWR_EnableBatteryCharging(void)979 __STATIC_INLINE void LL_PWR_EnableBatteryCharging(void)
980 {
981 SET_BIT(PWR->CR4, PWR_CR4_VBE);
982 }
983
984 /**
985 * @brief Disable battery charging
986 * @rmtoll CR4 VBE LL_PWR_DisableBatteryCharging
987 * @retval None
988 */
LL_PWR_DisableBatteryCharging(void)989 __STATIC_INLINE void LL_PWR_DisableBatteryCharging(void)
990 {
991 CLEAR_BIT(PWR->CR4, PWR_CR4_VBE);
992 }
993
994 /**
995 * @brief Check if battery charging is enabled
996 * @rmtoll CR4 VBE LL_PWR_IsEnabledBatteryCharging
997 * @retval State of bit (1 or 0).
998 */
LL_PWR_IsEnabledBatteryCharging(void)999 __STATIC_INLINE uint32_t LL_PWR_IsEnabledBatteryCharging(void)
1000 {
1001 return ((READ_BIT(PWR->CR4, PWR_CR4_VBE) == (PWR_CR4_VBE)) ? 1UL : 0UL);
1002 }
1003
1004 /**
1005 * @brief Set the Wake-Up pin polarity low for the event detection
1006 * @rmtoll CR4 WUPP1 LL_PWR_SetWakeUpPinPolarityLow\n
1007 * CR4 WUPP2 LL_PWR_SetWakeUpPinPolarityLow\n
1008 * CR4 WUPP3 LL_PWR_SetWakeUpPinPolarityLow\n
1009 * CR4 WUPP4 LL_PWR_SetWakeUpPinPolarityLow\n
1010 * CR4 WUPP5 LL_PWR_SetWakeUpPinPolarityLow
1011 * @param WakeUpPin This parameter can be one of the following values:
1012 * @arg @ref LL_PWR_WAKEUP_PIN1
1013 * @arg @ref LL_PWR_WAKEUP_PIN2
1014 * @arg @ref LL_PWR_WAKEUP_PIN3
1015 * @arg @ref LL_PWR_WAKEUP_PIN4
1016 * @arg @ref LL_PWR_WAKEUP_PIN5
1017 * @retval None
1018 */
LL_PWR_SetWakeUpPinPolarityLow(uint32_t WakeUpPin)1019 __STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityLow(uint32_t WakeUpPin)
1020 {
1021 SET_BIT(PWR->CR4, WakeUpPin);
1022 }
1023
1024 /**
1025 * @brief Set the Wake-Up pin polarity high for the event detection
1026 * @rmtoll CR4 WUPP1 LL_PWR_SetWakeUpPinPolarityHigh\n
1027 * CR4 WUPP2 LL_PWR_SetWakeUpPinPolarityHigh\n
1028 * CR4 WUPP3 LL_PWR_SetWakeUpPinPolarityHigh\n
1029 * CR4 WUPP4 LL_PWR_SetWakeUpPinPolarityHigh\n
1030 * CR4 WUPP5 LL_PWR_SetWakeUpPinPolarityHigh
1031 * @param WakeUpPin This parameter can be one of the following values:
1032 * @arg @ref LL_PWR_WAKEUP_PIN1
1033 * @arg @ref LL_PWR_WAKEUP_PIN2
1034 * @arg @ref LL_PWR_WAKEUP_PIN3
1035 * @arg @ref LL_PWR_WAKEUP_PIN4
1036 * @arg @ref LL_PWR_WAKEUP_PIN5
1037 * @retval None
1038 */
LL_PWR_SetWakeUpPinPolarityHigh(uint32_t WakeUpPin)1039 __STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityHigh(uint32_t WakeUpPin)
1040 {
1041 CLEAR_BIT(PWR->CR4, WakeUpPin);
1042 }
1043
1044 /**
1045 * @brief Get the Wake-Up pin polarity for the event detection
1046 * @rmtoll CR4 WUPP1 LL_PWR_IsWakeUpPinPolarityLow\n
1047 * CR4 WUPP2 LL_PWR_IsWakeUpPinPolarityLow\n
1048 * CR4 WUPP3 LL_PWR_IsWakeUpPinPolarityLow\n
1049 * CR4 WUPP4 LL_PWR_IsWakeUpPinPolarityLow\n
1050 * CR4 WUPP5 LL_PWR_IsWakeUpPinPolarityLow
1051 * @param WakeUpPin This parameter can be one of the following values:
1052 * @arg @ref LL_PWR_WAKEUP_PIN1
1053 * @arg @ref LL_PWR_WAKEUP_PIN2
1054 * @arg @ref LL_PWR_WAKEUP_PIN3
1055 * @arg @ref LL_PWR_WAKEUP_PIN4
1056 * @arg @ref LL_PWR_WAKEUP_PIN5
1057 * @retval State of bit (1 or 0).
1058 */
LL_PWR_IsWakeUpPinPolarityLow(uint32_t WakeUpPin)1059 __STATIC_INLINE uint32_t LL_PWR_IsWakeUpPinPolarityLow(uint32_t WakeUpPin)
1060 {
1061 return ((READ_BIT(PWR->CR4, WakeUpPin) == (WakeUpPin)) ? 1UL : 0UL);
1062 }
1063
1064 /**
1065 * @brief Enable GPIO pull-up state in Standby and Shutdown modes
1066 * @rmtoll PUCRA PU0-15 LL_PWR_EnableGPIOPullUp\n
1067 * PUCRB PU0-15 LL_PWR_EnableGPIOPullUp\n
1068 * PUCRC PU0-15 LL_PWR_EnableGPIOPullUp\n
1069 * PUCRD PU0-15 LL_PWR_EnableGPIOPullUp\n
1070 * PUCRE PU0-15 LL_PWR_EnableGPIOPullUp\n
1071 * PUCRF PU0-15 LL_PWR_EnableGPIOPullUp\n
1072 * PUCRG PU0-15 LL_PWR_EnableGPIOPullUp\n
1073 * PUCRH PU0-15 LL_PWR_EnableGPIOPullUp
1074 * @param GPIO This parameter can be one of the following values:
1075 * @arg @ref LL_PWR_GPIO_A
1076 * @arg @ref LL_PWR_GPIO_B
1077 * @arg @ref LL_PWR_GPIO_C
1078 * @arg @ref LL_PWR_GPIO_D
1079 * @arg @ref LL_PWR_GPIO_E
1080 * @arg @ref LL_PWR_GPIO_F
1081 * @arg @ref LL_PWR_GPIO_G
1082 * @arg @ref LL_PWR_GPIO_H
1083 * @param GPIONumber This parameter can be one of the following values:
1084 * @arg @ref LL_PWR_GPIO_BIT_0
1085 * @arg @ref LL_PWR_GPIO_BIT_1
1086 * @arg @ref LL_PWR_GPIO_BIT_2
1087 * @arg @ref LL_PWR_GPIO_BIT_3
1088 * @arg @ref LL_PWR_GPIO_BIT_4
1089 * @arg @ref LL_PWR_GPIO_BIT_5
1090 * @arg @ref LL_PWR_GPIO_BIT_6
1091 * @arg @ref LL_PWR_GPIO_BIT_7
1092 * @arg @ref LL_PWR_GPIO_BIT_8
1093 * @arg @ref LL_PWR_GPIO_BIT_9
1094 * @arg @ref LL_PWR_GPIO_BIT_10
1095 * @arg @ref LL_PWR_GPIO_BIT_11
1096 * @arg @ref LL_PWR_GPIO_BIT_12
1097 * @arg @ref LL_PWR_GPIO_BIT_13
1098 * @arg @ref LL_PWR_GPIO_BIT_14
1099 * @arg @ref LL_PWR_GPIO_BIT_15
1100 * @retval None
1101 */
LL_PWR_EnableGPIOPullUp(uint32_t GPIO,uint32_t GPIONumber)1102 __STATIC_INLINE void LL_PWR_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)
1103 {
1104 SET_BIT(*((__IO uint32_t *)GPIO), GPIONumber);
1105 }
1106
1107 /**
1108 * @brief Disable GPIO pull-up state in Standby and Shutdown modes
1109 * @rmtoll PUCRA PU0-15 LL_PWR_DisableGPIOPullUp\n
1110 * PUCRB PU0-15 LL_PWR_DisableGPIOPullUp\n
1111 * PUCRC PU0-15 LL_PWR_DisableGPIOPullUp\n
1112 * PUCRD PU0-15 LL_PWR_DisableGPIOPullUp\n
1113 * PUCRE PU0-15 LL_PWR_DisableGPIOPullUp\n
1114 * PUCRF PU0-15 LL_PWR_DisableGPIOPullUp\n
1115 * PUCRG PU0-15 LL_PWR_DisableGPIOPullUp\n
1116 * PUCRH PU0-15 LL_PWR_DisableGPIOPullUp
1117 * @param GPIO This parameter can be one of the following values:
1118 * @arg @ref LL_PWR_GPIO_A
1119 * @arg @ref LL_PWR_GPIO_B
1120 * @arg @ref LL_PWR_GPIO_C
1121 * @arg @ref LL_PWR_GPIO_D
1122 * @arg @ref LL_PWR_GPIO_E
1123 * @arg @ref LL_PWR_GPIO_F
1124 * @arg @ref LL_PWR_GPIO_G
1125 * @arg @ref LL_PWR_GPIO_H
1126 * @param GPIONumber This parameter can be one of the following values:
1127 * @arg @ref LL_PWR_GPIO_BIT_0
1128 * @arg @ref LL_PWR_GPIO_BIT_1
1129 * @arg @ref LL_PWR_GPIO_BIT_2
1130 * @arg @ref LL_PWR_GPIO_BIT_3
1131 * @arg @ref LL_PWR_GPIO_BIT_4
1132 * @arg @ref LL_PWR_GPIO_BIT_5
1133 * @arg @ref LL_PWR_GPIO_BIT_6
1134 * @arg @ref LL_PWR_GPIO_BIT_7
1135 * @arg @ref LL_PWR_GPIO_BIT_8
1136 * @arg @ref LL_PWR_GPIO_BIT_9
1137 * @arg @ref LL_PWR_GPIO_BIT_10
1138 * @arg @ref LL_PWR_GPIO_BIT_11
1139 * @arg @ref LL_PWR_GPIO_BIT_12
1140 * @arg @ref LL_PWR_GPIO_BIT_13
1141 * @arg @ref LL_PWR_GPIO_BIT_14
1142 * @arg @ref LL_PWR_GPIO_BIT_15
1143 * @retval None
1144 */
LL_PWR_DisableGPIOPullUp(uint32_t GPIO,uint32_t GPIONumber)1145 __STATIC_INLINE void LL_PWR_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)
1146 {
1147 CLEAR_BIT(*((__IO uint32_t *)GPIO), GPIONumber);
1148 }
1149
1150 /**
1151 * @brief Check if GPIO pull-up state is enabled
1152 * @rmtoll PUCRA PU0-15 LL_PWR_IsEnabledGPIOPullUp\n
1153 * PUCRB PU0-15 LL_PWR_IsEnabledGPIOPullUp\n
1154 * PUCRC PU0-15 LL_PWR_IsEnabledGPIOPullUp\n
1155 * PUCRD PU0-15 LL_PWR_IsEnabledGPIOPullUp\n
1156 * PUCRE PU0-15 LL_PWR_IsEnabledGPIOPullUp\n
1157 * PUCRF PU0-15 LL_PWR_IsEnabledGPIOPullUp\n
1158 * PUCRG PU0-15 LL_PWR_IsEnabledGPIOPullUp\n
1159 * PUCRH PU0-15 LL_PWR_IsEnabledGPIOPullUp
1160 * @param GPIO This parameter can be one of the following values:
1161 * @arg @ref LL_PWR_GPIO_A
1162 * @arg @ref LL_PWR_GPIO_B
1163 * @arg @ref LL_PWR_GPIO_C
1164 * @arg @ref LL_PWR_GPIO_D
1165 * @arg @ref LL_PWR_GPIO_E
1166 * @arg @ref LL_PWR_GPIO_F
1167 * @arg @ref LL_PWR_GPIO_G
1168 * @arg @ref LL_PWR_GPIO_H
1169 * @param GPIONumber This parameter can be one of the following values:
1170 * @arg @ref LL_PWR_GPIO_BIT_0
1171 * @arg @ref LL_PWR_GPIO_BIT_1
1172 * @arg @ref LL_PWR_GPIO_BIT_2
1173 * @arg @ref LL_PWR_GPIO_BIT_3
1174 * @arg @ref LL_PWR_GPIO_BIT_4
1175 * @arg @ref LL_PWR_GPIO_BIT_5
1176 * @arg @ref LL_PWR_GPIO_BIT_6
1177 * @arg @ref LL_PWR_GPIO_BIT_7
1178 * @arg @ref LL_PWR_GPIO_BIT_8
1179 * @arg @ref LL_PWR_GPIO_BIT_9
1180 * @arg @ref LL_PWR_GPIO_BIT_10
1181 * @arg @ref LL_PWR_GPIO_BIT_11
1182 * @arg @ref LL_PWR_GPIO_BIT_12
1183 * @arg @ref LL_PWR_GPIO_BIT_13
1184 * @arg @ref LL_PWR_GPIO_BIT_14
1185 * @arg @ref LL_PWR_GPIO_BIT_15
1186 * @retval State of bit (1 or 0).
1187 */
LL_PWR_IsEnabledGPIOPullUp(uint32_t GPIO,uint32_t GPIONumber)1188 __STATIC_INLINE uint32_t LL_PWR_IsEnabledGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)
1189 {
1190 return ((READ_BIT(*((__IO uint32_t *)GPIO), GPIONumber) == (GPIONumber)) ? 1UL : 0UL);
1191 }
1192
1193 /**
1194 * @brief Enable GPIO pull-down state in Standby and Shutdown modes
1195 * @rmtoll PDCRA PD0-15 LL_PWR_EnableGPIOPullDown\n
1196 * PDCRB PD0-15 LL_PWR_EnableGPIOPullDown\n
1197 * PDCRC PD0-15 LL_PWR_EnableGPIOPullDown\n
1198 * PDCRD PD0-15 LL_PWR_EnableGPIOPullDown\n
1199 * PDCRE PD0-15 LL_PWR_EnableGPIOPullDown\n
1200 * PDCRF PD0-15 LL_PWR_EnableGPIOPullDown\n
1201 * PDCRG PD0-15 LL_PWR_EnableGPIOPullDown\n
1202 * PDCRH PD0-15 LL_PWR_EnableGPIOPullDown
1203 * @param GPIO This parameter can be one of the following values:
1204 * @arg @ref LL_PWR_GPIO_A
1205 * @arg @ref LL_PWR_GPIO_B
1206 * @arg @ref LL_PWR_GPIO_C
1207 * @arg @ref LL_PWR_GPIO_D
1208 * @arg @ref LL_PWR_GPIO_E
1209 * @arg @ref LL_PWR_GPIO_F
1210 * @arg @ref LL_PWR_GPIO_G
1211 * @arg @ref LL_PWR_GPIO_H
1212 * @param GPIONumber This parameter can be one of the following values:
1213 * @arg @ref LL_PWR_GPIO_BIT_0
1214 * @arg @ref LL_PWR_GPIO_BIT_1
1215 * @arg @ref LL_PWR_GPIO_BIT_2
1216 * @arg @ref LL_PWR_GPIO_BIT_3
1217 * @arg @ref LL_PWR_GPIO_BIT_4
1218 * @arg @ref LL_PWR_GPIO_BIT_5
1219 * @arg @ref LL_PWR_GPIO_BIT_6
1220 * @arg @ref LL_PWR_GPIO_BIT_7
1221 * @arg @ref LL_PWR_GPIO_BIT_8
1222 * @arg @ref LL_PWR_GPIO_BIT_9
1223 * @arg @ref LL_PWR_GPIO_BIT_10
1224 * @arg @ref LL_PWR_GPIO_BIT_11
1225 * @arg @ref LL_PWR_GPIO_BIT_12
1226 * @arg @ref LL_PWR_GPIO_BIT_13
1227 * @arg @ref LL_PWR_GPIO_BIT_14
1228 * @arg @ref LL_PWR_GPIO_BIT_15
1229 * @retval None
1230 */
LL_PWR_EnableGPIOPullDown(uint32_t GPIO,uint32_t GPIONumber)1231 __STATIC_INLINE void LL_PWR_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber)
1232 {
1233 SET_BIT(*((__IO uint32_t *)(GPIO + 4U)), GPIONumber);
1234 }
1235
1236 /**
1237 * @brief Disable GPIO pull-down state in Standby and Shutdown modes
1238 * @rmtoll PDCRA PD0-15 LL_PWR_DisableGPIOPullDown\n
1239 * PDCRB PD0-15 LL_PWR_DisableGPIOPullDown\n
1240 * PDCRC PD0-15 LL_PWR_DisableGPIOPullDown\n
1241 * PDCRD PD0-15 LL_PWR_DisableGPIOPullDown\n
1242 * PDCRE PD0-15 LL_PWR_DisableGPIOPullDown\n
1243 * PDCRF PD0-15 LL_PWR_DisableGPIOPullDown\n
1244 * PDCRG PD0-15 LL_PWR_DisableGPIOPullDown\n
1245 * PDCRH PD0-15 LL_PWR_DisableGPIOPullDown
1246 * @param GPIO This parameter can be one of the following values:
1247 * @arg @ref LL_PWR_GPIO_A
1248 * @arg @ref LL_PWR_GPIO_B
1249 * @arg @ref LL_PWR_GPIO_C
1250 * @arg @ref LL_PWR_GPIO_D
1251 * @arg @ref LL_PWR_GPIO_E
1252 * @arg @ref LL_PWR_GPIO_F
1253 * @arg @ref LL_PWR_GPIO_G
1254 * @arg @ref LL_PWR_GPIO_H
1255 * @param GPIONumber This parameter can be one of the following values:
1256 * @arg @ref LL_PWR_GPIO_BIT_0
1257 * @arg @ref LL_PWR_GPIO_BIT_1
1258 * @arg @ref LL_PWR_GPIO_BIT_2
1259 * @arg @ref LL_PWR_GPIO_BIT_3
1260 * @arg @ref LL_PWR_GPIO_BIT_4
1261 * @arg @ref LL_PWR_GPIO_BIT_5
1262 * @arg @ref LL_PWR_GPIO_BIT_6
1263 * @arg @ref LL_PWR_GPIO_BIT_7
1264 * @arg @ref LL_PWR_GPIO_BIT_8
1265 * @arg @ref LL_PWR_GPIO_BIT_9
1266 * @arg @ref LL_PWR_GPIO_BIT_10
1267 * @arg @ref LL_PWR_GPIO_BIT_11
1268 * @arg @ref LL_PWR_GPIO_BIT_12
1269 * @arg @ref LL_PWR_GPIO_BIT_13
1270 * @arg @ref LL_PWR_GPIO_BIT_14
1271 * @arg @ref LL_PWR_GPIO_BIT_15
1272 * @retval None
1273 */
LL_PWR_DisableGPIOPullDown(uint32_t GPIO,uint32_t GPIONumber)1274 __STATIC_INLINE void LL_PWR_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber)
1275 {
1276 CLEAR_BIT(*((__IO uint32_t *)(GPIO + 4U)), GPIONumber);
1277 }
1278
1279 /**
1280 * @brief Check if GPIO pull-down state is enabled
1281 * @rmtoll PDCRA PD0-15 LL_PWR_IsEnabledGPIOPullDown\n
1282 * PDCRB PD0-15 LL_PWR_IsEnabledGPIOPullDown\n
1283 * PDCRC PD0-15 LL_PWR_IsEnabledGPIOPullDown\n
1284 * PDCRD PD0-15 LL_PWR_IsEnabledGPIOPullDown\n
1285 * PDCRE PD0-15 LL_PWR_IsEnabledGPIOPullDown\n
1286 * PDCRF PD0-15 LL_PWR_IsEnabledGPIOPullDown\n
1287 * PDCRG PD0-15 LL_PWR_IsEnabledGPIOPullDown\n
1288 * PDCRH PD0-15 LL_PWR_IsEnabledGPIOPullDown
1289 * @param GPIO This parameter can be one of the following values:
1290 * @arg @ref LL_PWR_GPIO_A
1291 * @arg @ref LL_PWR_GPIO_B
1292 * @arg @ref LL_PWR_GPIO_C
1293 * @arg @ref LL_PWR_GPIO_D
1294 * @arg @ref LL_PWR_GPIO_E
1295 * @arg @ref LL_PWR_GPIO_F
1296 * @arg @ref LL_PWR_GPIO_G
1297 * @arg @ref LL_PWR_GPIO_H
1298 * @param GPIONumber This parameter can be one of the following values:
1299 * @arg @ref LL_PWR_GPIO_BIT_0
1300 * @arg @ref LL_PWR_GPIO_BIT_1
1301 * @arg @ref LL_PWR_GPIO_BIT_2
1302 * @arg @ref LL_PWR_GPIO_BIT_3
1303 * @arg @ref LL_PWR_GPIO_BIT_4
1304 * @arg @ref LL_PWR_GPIO_BIT_5
1305 * @arg @ref LL_PWR_GPIO_BIT_6
1306 * @arg @ref LL_PWR_GPIO_BIT_7
1307 * @arg @ref LL_PWR_GPIO_BIT_8
1308 * @arg @ref LL_PWR_GPIO_BIT_9
1309 * @arg @ref LL_PWR_GPIO_BIT_10
1310 * @arg @ref LL_PWR_GPIO_BIT_11
1311 * @arg @ref LL_PWR_GPIO_BIT_12
1312 * @arg @ref LL_PWR_GPIO_BIT_13
1313 * @arg @ref LL_PWR_GPIO_BIT_14
1314 * @arg @ref LL_PWR_GPIO_BIT_15
1315 * @retval State of bit (1 or 0).
1316 */
LL_PWR_IsEnabledGPIOPullDown(uint32_t GPIO,uint32_t GPIONumber)1317 __STATIC_INLINE uint32_t LL_PWR_IsEnabledGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber)
1318 {
1319 return ((READ_BIT(*((__IO uint32_t *)(GPIO + 4U)), GPIONumber) == (GPIONumber)) ? 1UL : 0UL);
1320 }
1321
1322 /**
1323 * @}
1324 */
1325
1326 /** @defgroup PWR_LL_EF_FLAG_Management FLAG_Management
1327 * @{
1328 */
1329
1330 /**
1331 * @brief Get SMPS High-power mode ready Flag
1332 * @rmtoll SR1 SMPSHPRDY LL_PWR_IsActiveFlag_SMPSHPRDY
1333 * @retval State of bit (1 or 0).
1334 */
LL_PWR_IsActiveFlag_SMPSHPRDY(void)1335 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SMPSHPRDY(void)
1336 {
1337 return ((READ_BIT(PWR->SR1, PWR_SR1_SMPSHPRDY) == (PWR_SR1_SMPSHPRDY)) ? 1UL : 0UL);
1338 }
1339
1340 /**
1341 * @brief Get External SMPS mode ready Flag
1342 * @rmtoll SR1 EXTSMPSRDY LL_PWR_IsActiveFlag_EXTSMPSRDY
1343 * @retval State of bit (1 or 0).
1344 */
LL_PWR_IsActiveFlag_EXTSMPSRDY(void)1345 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_EXTSMPSRDY(void)
1346 {
1347 return ((READ_BIT(PWR->SR1, PWR_SR1_EXTSMPSRDY) == (PWR_SR1_EXTSMPSRDY)) ? 1UL : 0UL);
1348 }
1349
1350 /**
1351 * @brief Get SMPS Bypass mode ready Flag
1352 * @rmtoll SR1 SMPSBYPRDY LL_PWR_IsActiveFlag_SMPSBYPRDY
1353 * @retval State of bit (1 or 0).
1354 */
LL_PWR_IsActiveFlag_SMPSBYPRDY(void)1355 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SMPSBYPRDY(void)
1356 {
1357 return ((READ_BIT(PWR->SR1, PWR_SR1_SMPSBYPRDY) == (PWR_SR1_SMPSBYPRDY)) ? 1UL : 0UL);
1358 }
1359
1360 /**
1361 * @brief Get Stand-By Flag
1362 * @rmtoll SR1 SBF LL_PWR_IsActiveFlag_SB
1363 * @retval State of bit (1 or 0).
1364 */
LL_PWR_IsActiveFlag_SB(void)1365 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SB(void)
1366 {
1367 return ((READ_BIT(PWR->SR1, PWR_SR1_SBF) == (PWR_SR1_SBF)) ? 1UL : 0UL);
1368 }
1369
1370 /**
1371 * @brief Get Wake-up Flag 5
1372 * @rmtoll SR1 WUF5 LL_PWR_IsActiveFlag_WU5
1373 * @retval State of bit (1 or 0).
1374 */
LL_PWR_IsActiveFlag_WU5(void)1375 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU5(void)
1376 {
1377 return ((READ_BIT(PWR->SR1, PWR_SR1_WUF5) == (PWR_SR1_WUF5)) ? 1UL : 0UL);
1378 }
1379
1380 /**
1381 * @brief Get Wake-up Flag 4
1382 * @rmtoll SR1 WUF4 LL_PWR_IsActiveFlag_WU4
1383 * @retval State of bit (1 or 0).
1384 */
LL_PWR_IsActiveFlag_WU4(void)1385 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU4(void)
1386 {
1387 return ((READ_BIT(PWR->SR1, PWR_SR1_WUF4) == (PWR_SR1_WUF4)) ? 1UL : 0UL);
1388 }
1389
1390 /**
1391 * @brief Get Wake-up Flag 3
1392 * @rmtoll SR1 WUF3 LL_PWR_IsActiveFlag_WU3
1393 * @retval State of bit (1 or 0).
1394 */
LL_PWR_IsActiveFlag_WU3(void)1395 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU3(void)
1396 {
1397 return ((READ_BIT(PWR->SR1, PWR_SR1_WUF3) == (PWR_SR1_WUF3)) ? 1UL : 0UL);
1398 }
1399
1400 /**
1401 * @brief Get Wake-up Flag 2
1402 * @rmtoll SR1 WUF2 LL_PWR_IsActiveFlag_WU2
1403 * @retval State of bit (1 or 0).
1404 */
LL_PWR_IsActiveFlag_WU2(void)1405 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU2(void)
1406 {
1407 return ((READ_BIT(PWR->SR1, PWR_SR1_WUF2) == (PWR_SR1_WUF2)) ? 1UL : 0UL);
1408 }
1409
1410 /**
1411 * @brief Get Wake-up Flag 1
1412 * @rmtoll SR1 WUF1 LL_PWR_IsActiveFlag_WU1
1413 * @retval State of bit (1 or 0).
1414 */
LL_PWR_IsActiveFlag_WU1(void)1415 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU1(void)
1416 {
1417 return ((READ_BIT(PWR->SR1, PWR_SR1_WUF1) == (PWR_SR1_WUF1)) ? 1UL : 0UL);
1418 }
1419
1420 /**
1421 * @brief Clear Stand-By Flag
1422 * @rmtoll SCR CSBF LL_PWR_ClearFlag_SB
1423 * @retval None
1424 */
LL_PWR_ClearFlag_SB(void)1425 __STATIC_INLINE void LL_PWR_ClearFlag_SB(void)
1426 {
1427 WRITE_REG(PWR->SCR, PWR_SCR_CSBF);
1428 }
1429
1430 /**
1431 * @brief Clear Wake-up Flags
1432 * @rmtoll SCR CWUF LL_PWR_ClearFlag_WU
1433 * @retval None
1434 */
LL_PWR_ClearFlag_WU(void)1435 __STATIC_INLINE void LL_PWR_ClearFlag_WU(void)
1436 {
1437 WRITE_REG(PWR->SCR, PWR_SCR_CWUF);
1438 }
1439
1440 /**
1441 * @brief Clear Wake-up Flag 5
1442 * @rmtoll SCR CWUF5 LL_PWR_ClearFlag_WU5
1443 * @retval None
1444 */
LL_PWR_ClearFlag_WU5(void)1445 __STATIC_INLINE void LL_PWR_ClearFlag_WU5(void)
1446 {
1447 WRITE_REG(PWR->SCR, PWR_SCR_CWUF5);
1448 }
1449
1450 /**
1451 * @brief Clear Wake-up Flag 4
1452 * @rmtoll SCR CWUF4 LL_PWR_ClearFlag_WU4
1453 * @retval None
1454 */
LL_PWR_ClearFlag_WU4(void)1455 __STATIC_INLINE void LL_PWR_ClearFlag_WU4(void)
1456 {
1457 WRITE_REG(PWR->SCR, PWR_SCR_CWUF4);
1458 }
1459
1460 /**
1461 * @brief Clear Wake-up Flag 3
1462 * @rmtoll SCR CWUF3 LL_PWR_ClearFlag_WU3
1463 * @retval None
1464 */
LL_PWR_ClearFlag_WU3(void)1465 __STATIC_INLINE void LL_PWR_ClearFlag_WU3(void)
1466 {
1467 WRITE_REG(PWR->SCR, PWR_SCR_CWUF3);
1468 }
1469
1470 /**
1471 * @brief Clear Wake-up Flag 2
1472 * @rmtoll SCR CWUF2 LL_PWR_ClearFlag_WU2
1473 * @retval None
1474 */
LL_PWR_ClearFlag_WU2(void)1475 __STATIC_INLINE void LL_PWR_ClearFlag_WU2(void)
1476 {
1477 WRITE_REG(PWR->SCR, PWR_SCR_CWUF2);
1478 }
1479
1480 /**
1481 * @brief Clear Wake-up Flag 1
1482 * @rmtoll SCR CWUF1 LL_PWR_ClearFlag_WU1
1483 * @retval None
1484 */
LL_PWR_ClearFlag_WU1(void)1485 __STATIC_INLINE void LL_PWR_ClearFlag_WU1(void)
1486 {
1487 WRITE_REG(PWR->SCR, PWR_SCR_CWUF1);
1488 }
1489
1490 /**
1491 * @brief Indicate whether VDDA voltage is below or above PVM4 threshold
1492 * @rmtoll SR2 PVMO4 LL_PWR_IsActiveFlag_PVMO4
1493 * @retval State of bit (1 or 0).
1494 */
LL_PWR_IsActiveFlag_PVMO4(void)1495 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMO4(void)
1496 {
1497 return ((READ_BIT(PWR->SR2, PWR_SR2_PVMO4) == (PWR_SR2_PVMO4)) ? 1UL : 0UL);
1498 }
1499
1500 /**
1501 * @brief Indicate whether VDDA voltage is below or above PVM3 threshold
1502 * @rmtoll SR2 PVMO3 LL_PWR_IsActiveFlag_PVMO3
1503 * @retval State of bit (1 or 0).
1504 */
LL_PWR_IsActiveFlag_PVMO3(void)1505 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMO3(void)
1506 {
1507 return ((READ_BIT(PWR->SR2, PWR_SR2_PVMO3) == (PWR_SR2_PVMO3)) ? 1UL : 0UL);
1508 }
1509
1510 /**
1511 * @brief Indicate whether VDDIO2 voltage is below or above PVM2 threshold
1512 * @rmtoll SR2 PVMO2 LL_PWR_IsActiveFlag_PVMO2
1513 * @retval State of bit (1 or 0).
1514 */
LL_PWR_IsActiveFlag_PVMO2(void)1515 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMO2(void)
1516 {
1517 return ((READ_BIT(PWR->SR2, PWR_SR2_PVMO2) == (PWR_SR2_PVMO2)) ? 1UL : 0UL);
1518 }
1519
1520 /**
1521 * @brief Indicate whether VDDUSB voltage is below or above PVM1 threshold
1522 * @rmtoll SR2 PVMO1 LL_PWR_IsActiveFlag_PVMO1
1523 * @retval State of bit (1 or 0).
1524 */
LL_PWR_IsActiveFlag_PVMO1(void)1525 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMO1(void)
1526 {
1527 return ((READ_BIT(PWR->SR2, PWR_SR2_PVMO1) == (PWR_SR2_PVMO1)) ? 1UL : 0UL);
1528 }
1529
1530 /**
1531 * @brief Indicate whether VDD voltage is below or above the selected PVD threshold
1532 * @rmtoll SR2 PVDO LL_PWR_IsActiveFlag_PVDO
1533 * @retval State of bit (1 or 0).
1534 */
LL_PWR_IsActiveFlag_PVDO(void)1535 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void)
1536 {
1537 return ((READ_BIT(PWR->SR2, PWR_SR2_PVDO) == (PWR_SR2_PVDO)) ? 1UL : 0UL);
1538 }
1539
1540 /**
1541 * @brief Indicate whether the regulator is ready in the selected voltage range or if its output voltage is still changing to the required voltage level
1542 * @rmtoll SR2 VOSF LL_PWR_IsActiveFlag_VOS
1543 * @retval State of bit (1 or 0).
1544 */
LL_PWR_IsActiveFlag_VOS(void)1545 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VOS(void)
1546 {
1547 return ((READ_BIT(PWR->SR2, PWR_SR2_VOSF) == (PWR_SR2_VOSF)) ? 1UL : 0UL);
1548 }
1549
1550 /**
1551 * @brief Indicate whether the regulator is ready in main mode or is in low-power mode
1552 * @note: Take care, return value "0" means the regulator is ready. Return value "1" means the output voltage range is still changing.
1553 * @rmtoll SR2 REGLPF LL_PWR_IsActiveFlag_REGLPF
1554 * @retval State of bit (1 or 0).
1555 */
LL_PWR_IsActiveFlag_REGLPF(void)1556 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_REGLPF(void)
1557 {
1558 return ((READ_BIT(PWR->SR2, PWR_SR2_REGLPF) == (PWR_SR2_REGLPF)) ? 1UL : 0UL);
1559 }
1560
1561 /**
1562 * @brief Indicate whether or not the low-power regulator is ready
1563 * @rmtoll SR2 REGLPS LL_PWR_IsActiveFlag_REGLPS
1564 * @retval State of bit (1 or 0).
1565 */
LL_PWR_IsActiveFlag_REGLPS(void)1566 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_REGLPS(void)
1567 {
1568 return ((READ_BIT(PWR->SR2, PWR_SR2_REGLPS) == (PWR_SR2_REGLPS)) ? 1UL : 0UL);
1569 }
1570
1571 /**
1572 * @}
1573 */
1574
1575 /** @defgroup PWR_LL_EF_Privilege_Management Privilege_Management
1576 * @{
1577 */
1578
1579 /**
1580 * @brief Enable Privileged mode
1581 * @rmtoll PRIVCFGR PRIV LL_PWR_EnablePrivilege
1582 * @retval None
1583 */
LL_PWR_EnablePrivilege(void)1584 __STATIC_INLINE void LL_PWR_EnablePrivilege(void)
1585 {
1586 SET_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_PRIV);
1587 }
1588
1589 /**
1590 * @brief Disable Privileged mode
1591 * @rmtoll PRIVCFGR PRIV LL_PWR_DisablePrivilege
1592 * @retval None
1593 */
LL_PWR_DisablePrivilege(void)1594 __STATIC_INLINE void LL_PWR_DisablePrivilege(void)
1595 {
1596 CLEAR_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_PRIV);
1597 }
1598
1599 /**
1600 * @brief Check if Privileged mode has been enabled or not
1601 * @rmtoll PRIVCFGR PRIV LL_PWR_IsEnabledPrivilege
1602 * @retval State of bit (1 or 0).
1603 */
LL_PWR_IsEnabledPrivilege(void)1604 __STATIC_INLINE uint32_t LL_PWR_IsEnabledPrivilege(void)
1605 {
1606 return ((READ_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_PRIV) == PWR_PRIVCFGR_PRIV) ? 1UL : 0UL);
1607 }
1608
1609 /**
1610 * @}
1611 */
1612
1613 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
1614
1615 /** @defgroup PWR_LL_EF_Secure_Management Secure_Management
1616 * @{
1617 */
1618
1619 /**
1620 * @brief Configure Secure mode
1621 * @note Only available from secure state when system implements security (TZEN=1)
1622 * @rmtoll SECCFGR WUPSEC LL_PWR_ConfigSecure\n
1623 * SECCFGR WUP1SEC LL_PWR_ConfigSecure\n
1624 * SECCFGR WUP2SEC LL_PWR_ConfigSecure\n
1625 * SECCFGR WUP3SEC LL_PWR_ConfigSecure\n
1626 * SECCFGR WUP4SEC LL_PWR_ConfigSecure\n
1627 * SECCFGR WUP5SEC LL_PWR_ConfigSecure\n
1628 * SECCFGR LPMSEC LL_PWR_ConfigSecure\n
1629 * SECCFGR VDMSEC LL_PWR_ConfigSecure\n
1630 * SECCFGR VBSEC LL_PWR_ConfigSecure\n
1631 * SECCFGR APCSEC LL_PWR_ConfigSecure
1632 * @param Configuration This parameter shall be the full combination
1633 * of the following values:
1634 * @arg @ref LL_PWR_WAKEUP_PINS_SEC or LL_PWR_WAKEUP_PINS_NSEC
1635 * @arg @ref LL_PWR_WAKEUP_PIN1_SEC or LL_PWR_WAKEUP_PIN1_NSEC
1636 * @arg @ref LL_PWR_WAKEUP_PIN2_SEC or LL_PWR_WAKEUP_PIN2_NSEC
1637 * @arg @ref LL_PWR_WAKEUP_PIN3_SEC or LL_PWR_WAKEUP_PIN3_NSEC
1638 * @arg @ref LL_PWR_WAKEUP_PIN4_SEC or LL_PWR_WAKEUP_PIN4_NSEC
1639 * @arg @ref LL_PWR_WAKEUP_PIN5_SEC or LL_PWR_WAKEUP_PIN5_NSEC
1640 * @arg @ref LL_PWR_LPM_SEC or LL_PWR_LPM_NSEC
1641 * @arg @ref LL_PWR_VDM_SEC or LL_PWR_VDM_NSEC
1642 * @arg @ref LL_PWR_VB_SEC or LL_PWR_VB_NSEC
1643 * @arg @ref LL_PWR_APC_SEC or LL_PWR_APC_NSEC
1644 * @retval None
1645 */
LL_PWR_ConfigSecure(uint32_t Configuration)1646 __STATIC_INLINE void LL_PWR_ConfigSecure(uint32_t Configuration)
1647 {
1648 WRITE_REG(PWR->SECCFGR, Configuration);
1649 }
1650
1651 /**
1652 * @brief Get Secure mode configuration
1653 * @note Only available from secure state when system implements security (TZEN=1)
1654 * @rmtoll SECCFGR WUPSEC LL_PWR_GetConfigSecure\n
1655 * SECCFGR WUP1SEC LL_PWR_GetConfigSecure\n
1656 * SECCFGR WUP2SEC LL_PWR_GetConfigSecure\n
1657 * SECCFGR WUP3SEC LL_PWR_GetConfigSecure\n
1658 * SECCFGR WUP4SEC LL_PWR_GetConfigSecure\n
1659 * SECCFGR WUP5SEC LL_PWR_GetConfigSecure\n
1660 * SECCFGR LPMSEC LL_PWR_GetConfigSecure\n
1661 * SECCFGR VDMSEC LL_PWR_GetConfigSecure\n
1662 * SECCFGR VBSEC LL_PWR_GetConfigSecure\n
1663 * SECCFGR APCSEC LL_PWR_GetConfigSecure
1664 * @retval Returned value is the combination of the following values:
1665 * @arg @ref LL_PWR_WAKEUP_PINS_SEC or LL_PWR_WAKEUP_PINS_NSEC
1666 * @arg @ref LL_PWR_WAKEUP_PIN1_SEC or LL_PWR_WAKEUP_PIN1_NSEC
1667 * @arg @ref LL_PWR_WAKEUP_PIN2_SEC or LL_PWR_WAKEUP_PIN2_NSEC
1668 * @arg @ref LL_PWR_WAKEUP_PIN3_SEC or LL_PWR_WAKEUP_PIN3_NSEC
1669 * @arg @ref LL_PWR_WAKEUP_PIN4_SEC or LL_PWR_WAKEUP_PIN4_NSEC
1670 * @arg @ref LL_PWR_WAKEUP_PIN5_SEC or LL_PWR_WAKEUP_PIN5_NSEC
1671 * @arg @ref LL_PWR_LPM_SEC or LL_PWR_LPM_NSEC
1672 * @arg @ref LL_PWR_VDM_SEC or LL_PWR_VDM_NSEC
1673 * @arg @ref LL_PWR_VB_SEC or LL_PWR_VB_NSEC
1674 * @arg @ref LL_PWR_APC_SEC or LL_PWR_APC_NSEC
1675 */
LL_PWR_GetConfigSecure(void)1676 __STATIC_INLINE uint32_t LL_PWR_GetConfigSecure(void)
1677 {
1678 return (uint32_t)(READ_REG(PWR->SECCFGR));
1679 }
1680
1681 /**
1682 * @}
1683 */
1684 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
1685
1686
1687 #if defined(USE_FULL_LL_DRIVER)
1688 /** @defgroup PWR_LL_EF_Init De-initialization function
1689 * @{
1690 */
1691 ErrorStatus LL_PWR_DeInit(void);
1692 /**
1693 * @}
1694 */
1695 #endif /* USE_FULL_LL_DRIVER */
1696
1697 /** @defgroup PWR_LL_EF_Legacy_Functions Legacy functions name
1698 * @{
1699 */
1700 /* Old functions name kept for legacy purpose, to be replaced by the */
1701 /* current functions name. */
1702 #define LL_PWR_IsActiveFlag_VOSF LL_PWR_IsActiveFlag_VOS
1703 /**
1704 * @}
1705 */
1706
1707 /**
1708 * @}
1709 */
1710
1711 /**
1712 * @}
1713 */
1714
1715 #endif /* defined(PWR) */
1716
1717 /**
1718 * @}
1719 */
1720
1721 #ifdef __cplusplus
1722 }
1723 #endif
1724
1725 #endif /* STM32L5xx_LL_PWR_H */
1726
