1 /** 2 ****************************************************************************** 3 * @file stm32l4xx_hal_adc.h 4 * @author MCD Application Team 5 * @brief Header file of ADC HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2017 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32L4xx_HAL_ADC_H 21 #define STM32L4xx_HAL_ADC_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32l4xx_hal_def.h" 29 30 /* Include low level driver */ 31 #include "stm32l4xx_ll_adc.h" 32 33 /** @addtogroup STM32L4xx_HAL_Driver 34 * @{ 35 */ 36 37 /** @addtogroup ADC 38 * @{ 39 */ 40 41 /* Exported types ------------------------------------------------------------*/ 42 /** @defgroup ADC_Exported_Types ADC Exported Types 43 * @{ 44 */ 45 46 /** 47 * @brief ADC group regular oversampling structure definition 48 */ 49 typedef struct 50 { 51 uint32_t Ratio; /*!< Configures the oversampling ratio. 52 This parameter can be a value of @ref ADC_HAL_EC_OVS_RATIO */ 53 54 uint32_t RightBitShift; /*!< Configures the division coefficient for the Oversampler. 55 This parameter can be a value of @ref ADC_HAL_EC_OVS_SHIFT */ 56 57 uint32_t TriggeredMode; /*!< Selects the regular triggered oversampling mode. 58 This parameter can be a value of @ref ADC_HAL_EC_OVS_DISCONT_MODE */ 59 60 uint32_t OversamplingStopReset; /*!< Selects the regular oversampling mode. 61 The oversampling is either temporary stopped or reset upon an injected 62 sequence interruption. 63 If oversampling is enabled on both regular and injected groups, this parameter 64 is discarded and forced to setting "ADC_REGOVERSAMPLING_RESUMED_MODE" 65 (the oversampling buffer is zeroed during injection sequence). 66 This parameter can be a value of @ref ADC_HAL_EC_OVS_SCOPE_REG */ 67 68 } ADC_OversamplingTypeDef; 69 70 /** 71 * @brief Structure definition of ADC instance and ADC group regular. 72 * @note Parameters of this structure are shared within 2 scopes: 73 * - Scope entire ADC (affects ADC groups regular and injected): ClockPrescaler, Resolution, DataAlign, 74 * ScanConvMode, EOCSelection, LowPowerAutoWait. 75 * - Scope ADC group regular: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, NbrOfDiscConversion, 76 * ExternalTrigConv, ExternalTrigConvEdge, DMAContinuousRequests, Overrun, OversamplingMode, Oversampling. 77 * @note The setting of these parameters by function HAL_ADC_Init() is conditioned to ADC state. 78 * ADC state can be either: 79 * - For all parameters: ADC disabled 80 * - For all parameters except 'LowPowerAutoWait', 'DMAContinuousRequests' and 'Oversampling': ADC enabled without conversion on going on group regular. 81 * - For parameters 'LowPowerAutoWait' and 'DMAContinuousRequests': ADC enabled without conversion on going on groups regular and injected. 82 * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed 83 * without error reporting (as it can be the expected behavior in case of intended action to update another parameter 84 * (which fulfills the ADC state condition) on the fly). 85 */ 86 typedef struct 87 { 88 uint32_t ClockPrescaler; /*!< Select ADC clock source (synchronous clock derived from APB clock or asynchronous clock derived from system clock or PLL (Refer to reference manual for list of clocks available)) and clock prescaler. 89 This parameter can be a value of @ref ADC_HAL_EC_COMMON_CLOCK_SOURCE. 90 Note: The ADC clock configuration is common to all ADC instances. 91 Note: In case of usage of channels on injected group, ADC frequency should be lower than AHB clock frequency /4 for resolution 12 or 10 bits, 92 AHB clock frequency /3 for resolution 8 bits, AHB clock frequency /2 for resolution 6 bits. 93 Note: In case of synchronous clock mode based on HCLK/1, the configuration must be enabled only 94 if the system clock has a 50% duty clock cycle (APB prescaler configured inside RCC 95 must be bypassed and PCLK clock must have 50% duty cycle). Refer to reference manual for details. 96 Note: In case of usage of asynchronous clock, the selected clock must be preliminarily enabled at RCC top level. 97 Note: This parameter can be modified only if all ADC instances are disabled. */ 98 99 uint32_t Resolution; /*!< Configure the ADC resolution. 100 This parameter can be a value of @ref ADC_HAL_EC_RESOLUTION */ 101 102 uint32_t DataAlign; /*!< Specify ADC data alignment in conversion data register (right or left). 103 Refer to reference manual for alignments formats versus resolutions. 104 This parameter can be a value of @ref ADC_HAL_EC_DATA_ALIGN */ 105 106 uint32_t ScanConvMode; /*!< Configure the sequencer of ADC groups regular and injected. 107 This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts. 108 If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1). 109 Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1). 110 If enabled: Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion' or 'InjectedNbrOfConversion' and rank of each channel in sequencer). 111 Scan direction is upward: from rank 1 to rank 'n'. 112 This parameter can be a value of @ref ADC_Scan_mode */ 113 114 uint32_t EOCSelection; /*!< Specify which EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of unitary conversion or end of sequence conversions. 115 This parameter can be a value of @ref ADC_EOCSelection. */ 116 117 FunctionalState LowPowerAutoWait; /*!< Select the dynamic low power Auto Delay: new conversion start only when the previous 118 conversion (for ADC group regular) or previous sequence (for ADC group injected) has been retrieved by user software, 119 using function HAL_ADC_GetValue() or HAL_ADCEx_InjectedGetValue(). 120 This feature automatically adapts the frequency of ADC conversions triggers to the speed of the system that reads the data. Moreover, this avoids risk of overrun 121 for low frequency applications. 122 This parameter can be set to ENABLE or DISABLE. 123 Note: It is not recommended to use with interruption or DMA (HAL_ADC_Start_IT(), HAL_ADC_Start_DMA()) since these modes have to clear immediately the EOC flag (by CPU to free the IRQ pending event or by DMA). 124 Auto wait will work but fort a very short time, discarding its intended benefit (except specific case of high load of CPU or DMA transfers which can justify usage of auto wait). 125 Do use with polling: 1. Start conversion with HAL_ADC_Start(), 2. Later on, when ADC conversion data is needed: 126 use HAL_ADC_PollForConversion() to ensure that conversion is completed and HAL_ADC_GetValue() to retrieve conversion result and trig another conversion start. 127 (in case of usage of ADC group injected, use the equivalent functions HAL_ADCExInjected_Start(), HAL_ADCEx_InjectedGetValue(), ...). */ 128 129 FunctionalState ContinuousConvMode; /*!< Specify whether the conversion is performed in single mode (one conversion) or continuous mode for ADC group regular, 130 after the first ADC conversion start trigger occurred (software start or external trigger). 131 This parameter can be set to ENABLE or DISABLE. */ 132 133 uint32_t NbrOfConversion; /*!< Specify the number of ranks that will be converted within the regular group sequencer. 134 To use the regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled. 135 This parameter must be a number between Min_Data = 1 and Max_Data = 16. 136 Note: This parameter must be modified when no conversion is on going on regular group (ADC disabled, or ADC enabled without 137 continuous mode or external trigger that could launch a conversion). */ 138 139 FunctionalState DiscontinuousConvMode; /*!< Specify whether the conversions sequence of ADC group regular is performed in Complete-sequence/Discontinuous-sequence 140 (main sequence subdivided in successive parts). 141 Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. 142 Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded. 143 This parameter can be set to ENABLE or DISABLE. */ 144 145 uint32_t NbrOfDiscConversion; /*!< Specifies the number of discontinuous conversions in which the main sequence of ADC group regular (parameter NbrOfConversion) will be subdivided. 146 If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded. 147 This parameter must be a number between Min_Data = 1 and Max_Data = 8. */ 148 149 uint32_t ExternalTrigConv; /*!< Select the external event source used to trigger ADC group regular conversion start. 150 If set to ADC_SOFTWARE_START, external triggers are disabled and software trigger is used instead. 151 This parameter can be a value of @ref ADC_regular_external_trigger_source. 152 Caution: external trigger source is common to all ADC instances. */ 153 154 uint32_t ExternalTrigConvEdge; /*!< Select the external event edge used to trigger ADC group regular conversion start. 155 If trigger source is set to ADC_SOFTWARE_START, this parameter is discarded. 156 This parameter can be a value of @ref ADC_regular_external_trigger_edge */ 157 158 FunctionalState DMAContinuousRequests; /*!< Specify whether the DMA requests are performed in one shot mode (DMA transfer stops when number of conversions is reached) 159 or in continuous mode (DMA transfer unlimited, whatever number of conversions). 160 This parameter can be set to ENABLE or DISABLE. 161 Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached. */ 162 163 uint32_t Overrun; /*!< Select the behavior in case of overrun: data overwritten or preserved (default). 164 This parameter applies to ADC group regular only. 165 This parameter can be a value of @ref ADC_HAL_EC_REG_OVR_DATA_BEHAVIOR. 166 Note: In case of overrun set to data preserved and usage with programming model with interruption (HAL_Start_IT()): ADC IRQ handler has to clear 167 end of conversion flags, this induces the release of the preserved data. If needed, this data can be saved in function 168 HAL_ADC_ConvCpltCallback(), placed in user program code (called before end of conversion flags clear). 169 Note: Error reporting with respect to the conversion mode: 170 - Usage with ADC conversion by polling for event or interruption: Error is reported only if overrun is set to data preserved. If overrun is set to data 171 overwritten, user can willingly not read all the converted data, this is not considered as an erroneous case. 172 - Usage with ADC conversion by DMA: Error is reported whatever overrun setting (DMA is expected to process all data from data register). */ 173 174 FunctionalState OversamplingMode; /*!< Specify whether the oversampling feature is enabled or disabled. 175 This parameter can be set to ENABLE or DISABLE. 176 Note: This parameter can be modified only if there is no conversion is ongoing on ADC groups regular and injected */ 177 178 ADC_OversamplingTypeDef Oversampling; /*!< Specify the Oversampling parameters. 179 Caution: this setting overwrites the previous oversampling configuration if oversampling is already enabled. */ 180 181 #if defined(ADC_CFGR_DFSDMCFG) &&defined(DFSDM1_Channel0) 182 uint32_t DFSDMConfig; /*!< Specify whether ADC conversion data is sent directly to DFSDM. 183 This parameter can be a value of @ref ADC_HAL_EC_REG_DFSDM_TRANSFER. 184 Note: This parameter can be modified only if there is no conversion is ongoing (both ADSTART and JADSTART cleared). */ 185 186 #endif /* ADC_CFGR_DFSDMCFG */ 187 } ADC_InitTypeDef; 188 189 /** 190 * @brief Structure definition of ADC channel for regular group 191 * @note The setting of these parameters by function HAL_ADC_ConfigChannel() is conditioned to ADC state. 192 * ADC state can be either: 193 * - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'SingleDiff') 194 * - For all except parameters 'SamplingTime', 'Offset', 'OffsetNumber': ADC enabled without conversion on going on regular group. 195 * - For parameters 'SamplingTime', 'Offset', 'OffsetNumber': ADC enabled without conversion on going on regular and injected groups. 196 * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed 197 * without error reporting (as it can be the expected behavior in case of intended action to update another parameter (which fulfills the ADC state condition) 198 * on the fly). 199 */ 200 typedef struct 201 { 202 uint32_t Channel; /*!< Specify the channel to configure into ADC regular group. 203 This parameter can be a value of @ref ADC_HAL_EC_CHANNEL 204 Note: Depending on devices and ADC instances, some channels may not be available on device package pins. Refer to device datasheet for channels availability. */ 205 206 uint32_t Rank; /*!< Specify the rank in the regular group sequencer. 207 This parameter can be a value of @ref ADC_HAL_EC_REG_SEQ_RANKS 208 Note: to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by 209 the new channel setting (or parameter number of conversions adjusted) */ 210 211 uint32_t SamplingTime; /*!< Sampling time value to be set for the selected channel. 212 Unit: ADC clock cycles 213 Conversion time is the addition of sampling time and processing time 214 (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits). 215 This parameter can be a value of @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME 216 Caution: This parameter applies to a channel that can be used into regular and/or injected group. 217 It overwrites the last setting. 218 Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor), 219 sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting) 220 Refer to device datasheet for timings values. */ 221 222 uint32_t SingleDiff; /*!< Select single-ended or differential input. 223 In differential mode: Differential measurement is carried out between the selected channel 'i' (positive input) and channel 'i+1' (negative input). 224 Only channel 'i' has to be configured, channel 'i+1' is configured automatically. 225 This parameter must be a value of @ref ADC_HAL_EC_CHANNEL_SINGLE_DIFF_ENDING 226 Caution: This parameter applies to a channel that can be used in a regular and/or injected group. 227 It overwrites the last setting. 228 Note: Refer to Reference Manual to ensure the selected channel is available in differential mode. 229 Note: When configuring a channel 'i' in differential mode, the channel 'i+1' is not usable separately. 230 Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). 231 If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behavior in case 232 of another parameter update on the fly) */ 233 234 uint32_t OffsetNumber; /*!< Select the offset number 235 This parameter can be a value of @ref ADC_HAL_EC_OFFSET_NB 236 Caution: Only one offset is allowed per channel. This parameter overwrites the last setting. */ 237 238 uint32_t Offset; /*!< Define the offset to be subtracted from the raw converted data. 239 Offset value must be a positive number. 240 Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 241 0x3FF, 0xFF or 0x3F respectively. 242 Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled 243 without continuous mode or external trigger that could launch a conversion). */ 244 245 } ADC_ChannelConfTypeDef; 246 247 /** 248 * @brief Structure definition of ADC analog watchdog 249 * @note The setting of these parameters by function HAL_ADC_AnalogWDGConfig() is conditioned to ADC state. 250 * ADC state can be either: 251 * - For all parameters: ADC disabled or ADC enabled without conversion on going on ADC groups regular and injected. 252 */ 253 typedef struct 254 { 255 uint32_t WatchdogNumber; /*!< Select which ADC analog watchdog is monitoring the selected channel. 256 For Analog Watchdog 1: Only 1 channel can be monitored (or overall group of channels by setting parameter 'WatchdogMode') 257 For Analog Watchdog 2 and 3: Several channels can be monitored (by successive calls of 'HAL_ADC_AnalogWDGConfig()' for each channel) 258 This parameter can be a value of @ref ADC_HAL_EC_AWD_NUMBER. */ 259 260 uint32_t WatchdogMode; /*!< Configure the ADC analog watchdog mode: single/all/none channels. 261 For Analog Watchdog 1: Configure the ADC analog watchdog mode: single channel or all channels, ADC groups regular and-or injected. 262 For Analog Watchdog 2 and 3: Several channels can be monitored by applying successively the AWD init structure. Channels on ADC group regular and injected are not differentiated: Set value 'ADC_ANALOGWATCHDOG_SINGLE_xxx' to monitor 1 channel, value 'ADC_ANALOGWATCHDOG_ALL_xxx' to monitor all channels, 'ADC_ANALOGWATCHDOG_NONE' to monitor no channel. 263 This parameter can be a value of @ref ADC_analog_watchdog_mode. */ 264 265 uint32_t Channel; /*!< Select which ADC channel to monitor by analog watchdog. 266 For Analog Watchdog 1: this parameter has an effect only if parameter 'WatchdogMode' is configured on single channel (only 1 channel can be monitored). 267 For Analog Watchdog 2 and 3: Several channels can be monitored. To use this feature, call successively the function HAL_ADC_AnalogWDGConfig() for each channel to be added (or removed with value 'ADC_ANALOGWATCHDOG_NONE'). 268 This parameter can be a value of @ref ADC_HAL_EC_CHANNEL. */ 269 270 FunctionalState ITMode; /*!< Specify whether the analog watchdog is configured in interrupt or polling mode. 271 This parameter can be set to ENABLE or DISABLE */ 272 273 uint32_t HighThreshold; /*!< Configure the ADC analog watchdog High threshold value. 274 Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number 275 between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. 276 Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC resolution is 12 bits 277 the 4 LSB are ignored, if ADC resolution is 10 bits the 2 LSB are ignored. 278 Note: If ADC oversampling is enabled, ADC analog watchdog thresholds are 279 impacted: the comparison of analog watchdog thresholds is done on 280 oversampling final computation (after ratio and shift application): 281 ADC data register bitfield [15:4] (12 most significant bits). */ 282 283 uint32_t LowThreshold; /*!< Configures the ADC analog watchdog Low threshold value. 284 Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number 285 between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. 286 Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC resolution is 12 bits 287 the 4 LSB are ignored, if ADC resolution is 10 bits the 2 LSB are ignored. 288 Note: If ADC oversampling is enabled, ADC analog watchdog thresholds are 289 impacted: the comparison of analog watchdog thresholds is done on 290 oversampling final computation (after ratio and shift application): 291 ADC data register bitfield [15:4] (12 most significant bits). */ 292 } ADC_AnalogWDGConfTypeDef; 293 294 /** 295 * @brief ADC group injected contexts queue configuration 296 * @note Structure intended to be used only through structure "ADC_HandleTypeDef" 297 */ 298 typedef struct 299 { 300 uint32_t ContextQueue; /*!< Injected channel configuration context: build-up over each 301 HAL_ADCEx_InjectedConfigChannel() call to finally initialize 302 JSQR register at HAL_ADCEx_InjectedConfigChannel() last call */ 303 304 uint32_t ChannelCount; /*!< Number of channels in the injected sequence */ 305 } ADC_InjectionConfigTypeDef; 306 307 /** @defgroup ADC_States ADC States 308 * @{ 309 */ 310 311 /** 312 * @brief HAL ADC state machine: ADC states definition (bitfields) 313 * @note ADC state machine is managed by bitfields, state must be compared 314 * with bit by bit. 315 * For example: 316 * " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_REG_BUSY) != 0UL) " 317 * " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD1) != 0UL) " 318 */ 319 /* States of ADC global scope */ 320 #define HAL_ADC_STATE_RESET (0x00000000UL) /*!< ADC not yet initialized or disabled */ 321 #define HAL_ADC_STATE_READY (0x00000001UL) /*!< ADC peripheral ready for use */ 322 #define HAL_ADC_STATE_BUSY_INTERNAL (0x00000002UL) /*!< ADC is busy due to an internal process (initialization, calibration) */ 323 #define HAL_ADC_STATE_TIMEOUT (0x00000004UL) /*!< TimeOut occurrence */ 324 325 /* States of ADC errors */ 326 #define HAL_ADC_STATE_ERROR_INTERNAL (0x00000010UL) /*!< Internal error occurrence */ 327 #define HAL_ADC_STATE_ERROR_CONFIG (0x00000020UL) /*!< Configuration error occurrence */ 328 #define HAL_ADC_STATE_ERROR_DMA (0x00000040UL) /*!< DMA error occurrence */ 329 330 /* States of ADC group regular */ 331 #define HAL_ADC_STATE_REG_BUSY (0x00000100UL) /*!< A conversion on ADC group regular is ongoing or can occur (either by continuous mode, 332 external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */ 333 #define HAL_ADC_STATE_REG_EOC (0x00000200UL) /*!< Conversion data available on group regular */ 334 #define HAL_ADC_STATE_REG_OVR (0x00000400UL) /*!< Overrun occurrence */ 335 #define HAL_ADC_STATE_REG_EOSMP (0x00000800UL) /*!< Not available on this STM32 series: End Of Sampling flag raised */ 336 337 /* States of ADC group injected */ 338 #define HAL_ADC_STATE_INJ_BUSY (0x00001000UL) /*!< A conversion on ADC group injected is ongoing or can occur (either by auto-injection mode, 339 external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */ 340 #define HAL_ADC_STATE_INJ_EOC (0x00002000UL) /*!< Conversion data available on group injected */ 341 #define HAL_ADC_STATE_INJ_JQOVF (0x00004000UL) /*!< Injected queue overflow occurrence */ 342 343 /* States of ADC analog watchdogs */ 344 #define HAL_ADC_STATE_AWD1 (0x00010000UL) /*!< Out-of-window occurrence of ADC analog watchdog 1 */ 345 #define HAL_ADC_STATE_AWD2 (0x00020000UL) /*!< Out-of-window occurrence of ADC analog watchdog 2 */ 346 #define HAL_ADC_STATE_AWD3 (0x00040000UL) /*!< Out-of-window occurrence of ADC analog watchdog 3 */ 347 348 /* States of ADC multi-mode */ 349 #define HAL_ADC_STATE_MULTIMODE_SLAVE (0x00100000UL) /*!< ADC in multimode slave state, controlled by another ADC master (when feature available) */ 350 351 /** 352 * @} 353 */ 354 355 /** 356 * @brief ADC handle Structure definition 357 */ 358 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 359 typedef struct __ADC_HandleTypeDef 360 #else 361 typedef struct 362 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 363 { 364 ADC_TypeDef *Instance; /*!< Register base address */ 365 ADC_InitTypeDef Init; /*!< ADC initialization parameters and regular conversions setting */ 366 DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */ 367 HAL_LockTypeDef Lock; /*!< ADC locking object */ 368 __IO uint32_t State; /*!< ADC communication state (bitmap of ADC states) */ 369 __IO uint32_t ErrorCode; /*!< ADC Error code */ 370 ADC_InjectionConfigTypeDef InjectionConfig ; /*!< ADC injected channel configuration build-up structure */ 371 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 372 void (* ConvCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion complete callback */ 373 void (* ConvHalfCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion DMA half-transfer callback */ 374 void (* LevelOutOfWindowCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 1 callback */ 375 void (* ErrorCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC error callback */ 376 void (* InjectedConvCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC group injected conversion complete callback */ 377 void (* InjectedQueueOverflowCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC group injected context queue overflow callback */ 378 void (* LevelOutOfWindow2Callback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 2 callback */ 379 void (* LevelOutOfWindow3Callback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 3 callback */ 380 void (* EndOfSamplingCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC end of sampling callback */ 381 void (* MspInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp Init callback */ 382 void (* MspDeInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp DeInit callback */ 383 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 384 } ADC_HandleTypeDef; 385 386 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 387 /** 388 * @brief HAL ADC Callback ID enumeration definition 389 */ 390 typedef enum 391 { 392 HAL_ADC_CONVERSION_COMPLETE_CB_ID = 0x00U, /*!< ADC conversion complete callback ID */ 393 HAL_ADC_CONVERSION_HALF_CB_ID = 0x01U, /*!< ADC conversion DMA half-transfer callback ID */ 394 HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID = 0x02U, /*!< ADC analog watchdog 1 callback ID */ 395 HAL_ADC_ERROR_CB_ID = 0x03U, /*!< ADC error callback ID */ 396 HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID = 0x04U, /*!< ADC group injected conversion complete callback ID */ 397 HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID = 0x05U, /*!< ADC group injected context queue overflow callback ID */ 398 HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID = 0x06U, /*!< ADC analog watchdog 2 callback ID */ 399 HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID = 0x07U, /*!< ADC analog watchdog 3 callback ID */ 400 HAL_ADC_END_OF_SAMPLING_CB_ID = 0x08U, /*!< ADC end of sampling callback ID */ 401 HAL_ADC_MSPINIT_CB_ID = 0x09U, /*!< ADC Msp Init callback ID */ 402 HAL_ADC_MSPDEINIT_CB_ID = 0x0AU /*!< ADC Msp DeInit callback ID */ 403 } HAL_ADC_CallbackIDTypeDef; 404 405 /** 406 * @brief HAL ADC Callback pointer definition 407 */ 408 typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to a ADC callback function */ 409 410 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 411 412 /** 413 * @} 414 */ 415 416 417 /* Exported constants --------------------------------------------------------*/ 418 419 /** @defgroup ADC_Exported_Constants ADC Exported Constants 420 * @{ 421 */ 422 423 /** @defgroup ADC_Error_Code ADC Error Code 424 * @{ 425 */ 426 #define HAL_ADC_ERROR_NONE (0x00U) /*!< No error */ 427 #define HAL_ADC_ERROR_INTERNAL (0x01U) /*!< ADC peripheral internal error (problem of clocking, 428 enable/disable, erroneous state, ...) */ 429 #define HAL_ADC_ERROR_OVR (0x02U) /*!< Overrun error */ 430 #define HAL_ADC_ERROR_DMA (0x04U) /*!< DMA transfer error */ 431 #define HAL_ADC_ERROR_JQOVF (0x08U) /*!< Injected context queue overflow error */ 432 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 433 #define HAL_ADC_ERROR_INVALID_CALLBACK (0x10U) /*!< Invalid Callback error */ 434 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 435 /** 436 * @} 437 */ 438 439 /** @defgroup ADC_HAL_EC_COMMON_CLOCK_SOURCE ADC common - Clock source 440 * @{ 441 */ 442 #define ADC_CLOCK_SYNC_PCLK_DIV1 (LL_ADC_CLOCK_SYNC_PCLK_DIV1) /*!< ADC synchronous clock derived from AHB clock without prescaler */ 443 #define ADC_CLOCK_SYNC_PCLK_DIV2 (LL_ADC_CLOCK_SYNC_PCLK_DIV2) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 2 */ 444 #define ADC_CLOCK_SYNC_PCLK_DIV4 (LL_ADC_CLOCK_SYNC_PCLK_DIV4) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 4 */ 445 446 #define ADC_CLOCK_ASYNC_DIV1 (LL_ADC_CLOCK_ASYNC_DIV1) /*!< ADC asynchronous clock without prescaler */ 447 #define ADC_CLOCK_ASYNC_DIV2 (LL_ADC_CLOCK_ASYNC_DIV2) /*!< ADC asynchronous clock with prescaler division by 2 */ 448 #define ADC_CLOCK_ASYNC_DIV4 (LL_ADC_CLOCK_ASYNC_DIV4) /*!< ADC asynchronous clock with prescaler division by 4 */ 449 #define ADC_CLOCK_ASYNC_DIV6 (LL_ADC_CLOCK_ASYNC_DIV6) /*!< ADC asynchronous clock with prescaler division by 6 */ 450 #define ADC_CLOCK_ASYNC_DIV8 (LL_ADC_CLOCK_ASYNC_DIV8) /*!< ADC asynchronous clock with prescaler division by 8 */ 451 #define ADC_CLOCK_ASYNC_DIV10 (LL_ADC_CLOCK_ASYNC_DIV10) /*!< ADC asynchronous clock with prescaler division by 10 */ 452 #define ADC_CLOCK_ASYNC_DIV12 (LL_ADC_CLOCK_ASYNC_DIV12) /*!< ADC asynchronous clock with prescaler division by 12 */ 453 #define ADC_CLOCK_ASYNC_DIV16 (LL_ADC_CLOCK_ASYNC_DIV16) /*!< ADC asynchronous clock with prescaler division by 16 */ 454 #define ADC_CLOCK_ASYNC_DIV32 (LL_ADC_CLOCK_ASYNC_DIV32) /*!< ADC asynchronous clock with prescaler division by 32 */ 455 #define ADC_CLOCK_ASYNC_DIV64 (LL_ADC_CLOCK_ASYNC_DIV64) /*!< ADC asynchronous clock with prescaler division by 64 */ 456 #define ADC_CLOCK_ASYNC_DIV128 (LL_ADC_CLOCK_ASYNC_DIV128) /*!< ADC asynchronous clock with prescaler division by 128 */ 457 #define ADC_CLOCK_ASYNC_DIV256 (LL_ADC_CLOCK_ASYNC_DIV256) /*!< ADC asynchronous clock with prescaler division by 256 */ 458 /** 459 * @} 460 */ 461 462 /** @defgroup ADC_HAL_EC_RESOLUTION ADC instance - Resolution 463 * @{ 464 */ 465 #define ADC_RESOLUTION_12B (LL_ADC_RESOLUTION_12B) /*!< ADC resolution 12 bits */ 466 #define ADC_RESOLUTION_10B (LL_ADC_RESOLUTION_10B) /*!< ADC resolution 10 bits */ 467 #define ADC_RESOLUTION_8B (LL_ADC_RESOLUTION_8B) /*!< ADC resolution 8 bits */ 468 #define ADC_RESOLUTION_6B (LL_ADC_RESOLUTION_6B) /*!< ADC resolution 6 bits */ 469 /** 470 * @} 471 */ 472 473 /** @defgroup ADC_HAL_EC_DATA_ALIGN ADC conversion data alignment 474 * @{ 475 */ 476 #define ADC_DATAALIGN_RIGHT (LL_ADC_DATA_ALIGN_RIGHT)/*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/ 477 #define ADC_DATAALIGN_LEFT (LL_ADC_DATA_ALIGN_LEFT) /*!< ADC conversion data alignment: left aligned (alignment on data register MSB bit 15)*/ 478 /** 479 * @} 480 */ 481 482 /** @defgroup ADC_Scan_mode ADC sequencer scan mode 483 * @{ 484 */ 485 #define ADC_SCAN_DISABLE (0x00000000UL) /*!< Scan mode disabled */ 486 #define ADC_SCAN_ENABLE (0x00000001UL) /*!< Scan mode enabled */ 487 /** 488 * @} 489 */ 490 491 /** @defgroup ADC_regular_external_trigger_source ADC group regular trigger source 492 * @{ 493 */ 494 /* ADC group regular trigger sources for all ADC instances */ 495 #define ADC_SOFTWARE_START (LL_ADC_REG_TRIG_SOFTWARE) /*!< ADC group regular conversion trigger internal: SW start. */ 496 #define ADC_EXTERNALTRIG_T1_TRGO (LL_ADC_REG_TRIG_EXT_TIM1_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM1 TRGO. Trigger edge set to rising edge (default setting). */ 497 #define ADC_EXTERNALTRIG_T1_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) /*!< ADC group regular conversion trigger from external peripheral: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */ 498 #define ADC_EXTERNALTRIG_T1_CC1 (LL_ADC_REG_TRIG_EXT_TIM1_CH1) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 499 #define ADC_EXTERNALTRIG_T1_CC2 (LL_ADC_REG_TRIG_EXT_TIM1_CH2) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 500 #define ADC_EXTERNALTRIG_T1_CC3 (LL_ADC_REG_TRIG_EXT_TIM1_CH3) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 501 #define ADC_EXTERNALTRIG_T2_TRGO (LL_ADC_REG_TRIG_EXT_TIM2_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM2 TRGO. Trigger edge set to rising edge (default setting). */ 502 #define ADC_EXTERNALTRIG_T2_CC2 (LL_ADC_REG_TRIG_EXT_TIM2_CH2) /*!< ADC group regular conversion trigger from external peripheral: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 503 #define ADC_EXTERNALTRIG_T3_TRGO (LL_ADC_REG_TRIG_EXT_TIM3_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM3 TRGO. Trigger edge set to rising edge (default setting). */ 504 #define ADC_EXTERNALTRIG_T3_CC4 (LL_ADC_REG_TRIG_EXT_TIM3_CH4) /*!< ADC group regular conversion trigger from external peripheral: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 505 #define ADC_EXTERNALTRIG_T4_TRGO (LL_ADC_REG_TRIG_EXT_TIM4_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM4 TRGO. Trigger edge set to rising edge (default setting). */ 506 #define ADC_EXTERNALTRIG_T4_CC4 (LL_ADC_REG_TRIG_EXT_TIM4_CH4) /*!< ADC group regular conversion trigger from external peripheral: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 507 #define ADC_EXTERNALTRIG_T6_TRGO (LL_ADC_REG_TRIG_EXT_TIM6_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM6 TRGO. Trigger edge set to rising edge (default setting). */ 508 #define ADC_EXTERNALTRIG_T8_TRGO (LL_ADC_REG_TRIG_EXT_TIM8_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM8 TRGO. Trigger edge set to rising edge (default setting). */ 509 #define ADC_EXTERNALTRIG_T8_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM8_TRGO2) /*!< ADC group regular conversion trigger from external peripheral: TIM8 TRGO2. Trigger edge set to rising edge (default setting). */ 510 #define ADC_EXTERNALTRIG_T15_TRGO (LL_ADC_REG_TRIG_EXT_TIM15_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM15 TRGO. Trigger edge set to rising edge (default setting). */ 511 #define ADC_EXTERNALTRIG_EXT_IT11 (LL_ADC_REG_TRIG_EXT_EXTI_LINE11) /*!< ADC group regular conversion trigger from external peripheral: external interrupt line 11. Trigger edge set to rising edge (default setting). */ 512 /** 513 * @} 514 */ 515 516 /** @defgroup ADC_regular_external_trigger_edge ADC group regular trigger edge (when external trigger is selected) 517 * @{ 518 */ 519 #define ADC_EXTERNALTRIGCONVEDGE_NONE (0x00000000UL) /*!< Regular conversions hardware trigger detection disabled */ 520 #define ADC_EXTERNALTRIGCONVEDGE_RISING (LL_ADC_REG_TRIG_EXT_RISING) /*!< ADC group regular conversion trigger polarity set to rising edge */ 521 #define ADC_EXTERNALTRIGCONVEDGE_FALLING (LL_ADC_REG_TRIG_EXT_FALLING) /*!< ADC group regular conversion trigger polarity set to falling edge */ 522 #define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING (LL_ADC_REG_TRIG_EXT_RISINGFALLING) /*!< ADC group regular conversion trigger polarity set to both rising and falling edges */ 523 /** 524 * @} 525 */ 526 527 /** @defgroup ADC_EOCSelection ADC sequencer end of unitary conversion or sequence conversions 528 * @{ 529 */ 530 #define ADC_EOC_SINGLE_CONV (ADC_ISR_EOC) /*!< End of unitary conversion flag */ 531 #define ADC_EOC_SEQ_CONV (ADC_ISR_EOS) /*!< End of sequence conversions flag */ 532 /** 533 * @} 534 */ 535 536 /** @defgroup ADC_HAL_EC_REG_OVR_DATA_BEHAVIOR ADC group regular - Overrun behavior on conversion data 537 * @{ 538 */ 539 #define ADC_OVR_DATA_PRESERVED (LL_ADC_REG_OVR_DATA_PRESERVED) /*!< ADC group regular behavior in case of overrun: data preserved */ 540 #define ADC_OVR_DATA_OVERWRITTEN (LL_ADC_REG_OVR_DATA_OVERWRITTEN) /*!< ADC group regular behavior in case of overrun: data overwritten */ 541 /** 542 * @} 543 */ 544 545 /** @defgroup ADC_HAL_EC_REG_SEQ_RANKS ADC group regular - Sequencer ranks 546 * @{ 547 */ 548 #define ADC_REGULAR_RANK_1 (LL_ADC_REG_RANK_1) /*!< ADC group regular sequencer rank 1 */ 549 #define ADC_REGULAR_RANK_2 (LL_ADC_REG_RANK_2) /*!< ADC group regular sequencer rank 2 */ 550 #define ADC_REGULAR_RANK_3 (LL_ADC_REG_RANK_3) /*!< ADC group regular sequencer rank 3 */ 551 #define ADC_REGULAR_RANK_4 (LL_ADC_REG_RANK_4) /*!< ADC group regular sequencer rank 4 */ 552 #define ADC_REGULAR_RANK_5 (LL_ADC_REG_RANK_5) /*!< ADC group regular sequencer rank 5 */ 553 #define ADC_REGULAR_RANK_6 (LL_ADC_REG_RANK_6) /*!< ADC group regular sequencer rank 6 */ 554 #define ADC_REGULAR_RANK_7 (LL_ADC_REG_RANK_7) /*!< ADC group regular sequencer rank 7 */ 555 #define ADC_REGULAR_RANK_8 (LL_ADC_REG_RANK_8) /*!< ADC group regular sequencer rank 8 */ 556 #define ADC_REGULAR_RANK_9 (LL_ADC_REG_RANK_9) /*!< ADC group regular sequencer rank 9 */ 557 #define ADC_REGULAR_RANK_10 (LL_ADC_REG_RANK_10) /*!< ADC group regular sequencer rank 10 */ 558 #define ADC_REGULAR_RANK_11 (LL_ADC_REG_RANK_11) /*!< ADC group regular sequencer rank 11 */ 559 #define ADC_REGULAR_RANK_12 (LL_ADC_REG_RANK_12) /*!< ADC group regular sequencer rank 12 */ 560 #define ADC_REGULAR_RANK_13 (LL_ADC_REG_RANK_13) /*!< ADC group regular sequencer rank 13 */ 561 #define ADC_REGULAR_RANK_14 (LL_ADC_REG_RANK_14) /*!< ADC group regular sequencer rank 14 */ 562 #define ADC_REGULAR_RANK_15 (LL_ADC_REG_RANK_15) /*!< ADC group regular sequencer rank 15 */ 563 #define ADC_REGULAR_RANK_16 (LL_ADC_REG_RANK_16) /*!< ADC group regular sequencer rank 16 */ 564 /** 565 * @} 566 */ 567 568 /** @defgroup ADC_HAL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time 569 * @{ 570 */ 571 #define ADC_SAMPLETIME_2CYCLES_5 (LL_ADC_SAMPLINGTIME_2CYCLES_5) /*!< Sampling time 2.5 ADC clock cycles */ 572 #define ADC_SAMPLETIME_6CYCLES_5 (LL_ADC_SAMPLINGTIME_6CYCLES_5) /*!< Sampling time 6.5 ADC clock cycles */ 573 #define ADC_SAMPLETIME_12CYCLES_5 (LL_ADC_SAMPLINGTIME_12CYCLES_5) /*!< Sampling time 12.5 ADC clock cycles */ 574 #define ADC_SAMPLETIME_24CYCLES_5 (LL_ADC_SAMPLINGTIME_24CYCLES_5) /*!< Sampling time 24.5 ADC clock cycles */ 575 #define ADC_SAMPLETIME_47CYCLES_5 (LL_ADC_SAMPLINGTIME_47CYCLES_5) /*!< Sampling time 47.5 ADC clock cycles */ 576 #define ADC_SAMPLETIME_92CYCLES_5 (LL_ADC_SAMPLINGTIME_92CYCLES_5) /*!< Sampling time 92.5 ADC clock cycles */ 577 #define ADC_SAMPLETIME_247CYCLES_5 (LL_ADC_SAMPLINGTIME_247CYCLES_5) /*!< Sampling time 247.5 ADC clock cycles */ 578 #define ADC_SAMPLETIME_640CYCLES_5 (LL_ADC_SAMPLINGTIME_640CYCLES_5) /*!< Sampling time 640.5 ADC clock cycles */ 579 #if defined(ADC_SMPR1_SMPPLUS) 580 #define ADC_SAMPLETIME_3CYCLES_5 (ADC_SMPR1_SMPPLUS | LL_ADC_SAMPLINGTIME_2CYCLES_5) /*!< Sampling time 3.5 ADC clock cycles. If selected, this sampling time replaces all sampling time 2.5 ADC clock cycles. These 2 sampling times cannot be used simultaneously. */ 581 #endif /* ADC_SMPR1_SMPPLUS */ 582 /** 583 * @} 584 */ 585 586 /** @defgroup ADC_HAL_EC_CHANNEL ADC instance - Channel number 587 * @{ 588 */ 589 /* Note: VrefInt, TempSensor and Vbat internal channels are not available on */ 590 /* all ADC instances (refer to Reference Manual). */ 591 #define ADC_CHANNEL_0 (LL_ADC_CHANNEL_0) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN0 */ 592 #define ADC_CHANNEL_1 (LL_ADC_CHANNEL_1) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN1 */ 593 #define ADC_CHANNEL_2 (LL_ADC_CHANNEL_2) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN2 */ 594 #define ADC_CHANNEL_3 (LL_ADC_CHANNEL_3) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN3 */ 595 #define ADC_CHANNEL_4 (LL_ADC_CHANNEL_4) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN4 */ 596 #define ADC_CHANNEL_5 (LL_ADC_CHANNEL_5) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN5 */ 597 #define ADC_CHANNEL_6 (LL_ADC_CHANNEL_6) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN6 */ 598 #define ADC_CHANNEL_7 (LL_ADC_CHANNEL_7) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN7 */ 599 #define ADC_CHANNEL_8 (LL_ADC_CHANNEL_8) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN8 */ 600 #define ADC_CHANNEL_9 (LL_ADC_CHANNEL_9) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN9 */ 601 #define ADC_CHANNEL_10 (LL_ADC_CHANNEL_10) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN10 */ 602 #define ADC_CHANNEL_11 (LL_ADC_CHANNEL_11) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN11 */ 603 #define ADC_CHANNEL_12 (LL_ADC_CHANNEL_12) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN12 */ 604 #define ADC_CHANNEL_13 (LL_ADC_CHANNEL_13) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN13 */ 605 #define ADC_CHANNEL_14 (LL_ADC_CHANNEL_14) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN14 */ 606 #define ADC_CHANNEL_15 (LL_ADC_CHANNEL_15) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN15 */ 607 #define ADC_CHANNEL_16 (LL_ADC_CHANNEL_16) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN16 */ 608 #define ADC_CHANNEL_17 (LL_ADC_CHANNEL_17) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN17 */ 609 #define ADC_CHANNEL_18 (LL_ADC_CHANNEL_18) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN18 */ 610 #define ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_VREFINT) /*!< ADC internal channel connected to VrefInt: Internal voltage reference. */ 611 #define ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_TEMPSENSOR) /*!< ADC internal channel connected to Temperature sensor. */ 612 #define ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_VBAT) /*!< ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda. */ 613 #if defined(ADC1) && !defined(ADC2) 614 #define ADC_CHANNEL_DAC1CH1 (LL_ADC_CHANNEL_DAC1CH1) /*!< ADC internal channel connected to DAC1 channel 1, channel specific to ADC1. This channel is shared with ADC internal channel connected to temperature sensor, selection is done using function @ref LL_ADC_SetCommonPathInternalCh(). */ 615 #define ADC_CHANNEL_DAC1CH2 (LL_ADC_CHANNEL_DAC1CH2) /*!< ADC internal channel connected to DAC1 channel 2, channel specific to ADC1. This channel is shared with ADC internal channel connected to Vbat, selection is done using function @ref LL_ADC_SetCommonPathInternalCh(). */ 616 #elif defined(ADC2) 617 #define ADC_CHANNEL_DAC1CH1_ADC2 (LL_ADC_CHANNEL_DAC1CH1_ADC2) /*!< ADC internal channel connected to DAC1 channel 1, channel specific to ADC2 */ 618 #define ADC_CHANNEL_DAC1CH2_ADC2 (LL_ADC_CHANNEL_DAC1CH2_ADC2) /*!< ADC internal channel connected to DAC1 channel 2, channel specific to ADC2 */ 619 #if defined(ADC3) 620 #define ADC_CHANNEL_DAC1CH1_ADC3 (LL_ADC_CHANNEL_DAC1CH1_ADC3) /*!< ADC internal channel connected to DAC1 channel 1, channel specific to ADC3 */ 621 #define ADC_CHANNEL_DAC1CH2_ADC3 (LL_ADC_CHANNEL_DAC1CH2_ADC3) /*!< ADC internal channel connected to DAC1 channel 2, channel specific to ADC3 */ 622 #endif /* ADC3 */ 623 #endif /* ADC1 && !ADC2 */ 624 /** 625 * @} 626 */ 627 628 /** @defgroup ADC_HAL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number 629 * @{ 630 */ 631 #define ADC_ANALOGWATCHDOG_1 (LL_ADC_AWD1) /*!< ADC analog watchdog number 1 */ 632 #define ADC_ANALOGWATCHDOG_2 (LL_ADC_AWD2) /*!< ADC analog watchdog number 2 */ 633 #define ADC_ANALOGWATCHDOG_3 (LL_ADC_AWD3) /*!< ADC analog watchdog number 3 */ 634 /** 635 * @} 636 */ 637 638 /** @defgroup ADC_analog_watchdog_mode ADC Analog Watchdog Mode 639 * @{ 640 */ 641 #define ADC_ANALOGWATCHDOG_NONE (0x00000000UL) /*!< No analog watchdog selected */ 642 #define ADC_ANALOGWATCHDOG_SINGLE_REG (ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN) /*!< Analog watchdog applied to a regular group single channel */ 643 #define ADC_ANALOGWATCHDOG_SINGLE_INJEC (ADC_CFGR_AWD1SGL | ADC_CFGR_JAWD1EN) /*!< Analog watchdog applied to an injected group single channel */ 644 #define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC (ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN | ADC_CFGR_JAWD1EN) /*!< Analog watchdog applied to a regular and injected groups single channel */ 645 #define ADC_ANALOGWATCHDOG_ALL_REG (ADC_CFGR_AWD1EN) /*!< Analog watchdog applied to regular group all channels */ 646 #define ADC_ANALOGWATCHDOG_ALL_INJEC (ADC_CFGR_JAWD1EN) /*!< Analog watchdog applied to injected group all channels */ 647 #define ADC_ANALOGWATCHDOG_ALL_REGINJEC (ADC_CFGR_AWD1EN | ADC_CFGR_JAWD1EN) /*!< Analog watchdog applied to regular and injected groups all channels */ 648 /** 649 * @} 650 */ 651 652 /** @defgroup ADC_HAL_EC_OVS_RATIO Oversampling - Ratio 653 * @{ 654 */ 655 #define ADC_OVERSAMPLING_RATIO_2 (LL_ADC_OVS_RATIO_2) /*!< ADC oversampling ratio of 2 (2 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ 656 #define ADC_OVERSAMPLING_RATIO_4 (LL_ADC_OVS_RATIO_4) /*!< ADC oversampling ratio of 4 (4 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ 657 #define ADC_OVERSAMPLING_RATIO_8 (LL_ADC_OVS_RATIO_8) /*!< ADC oversampling ratio of 8 (8 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ 658 #define ADC_OVERSAMPLING_RATIO_16 (LL_ADC_OVS_RATIO_16) /*!< ADC oversampling ratio of 16 (16 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ 659 #define ADC_OVERSAMPLING_RATIO_32 (LL_ADC_OVS_RATIO_32) /*!< ADC oversampling ratio of 32 (32 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ 660 #define ADC_OVERSAMPLING_RATIO_64 (LL_ADC_OVS_RATIO_64) /*!< ADC oversampling ratio of 64 (64 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ 661 #define ADC_OVERSAMPLING_RATIO_128 (LL_ADC_OVS_RATIO_128) /*!< ADC oversampling ratio of 128 (128 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ 662 #define ADC_OVERSAMPLING_RATIO_256 (LL_ADC_OVS_RATIO_256) /*!< ADC oversampling ratio of 256 (256 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ 663 /** 664 * @} 665 */ 666 667 /** @defgroup ADC_HAL_EC_OVS_SHIFT Oversampling - Data shift 668 * @{ 669 */ 670 #define ADC_RIGHTBITSHIFT_NONE (LL_ADC_OVS_SHIFT_NONE) /*!< ADC oversampling no shift (sum of the ADC conversions data is not divided to result as the ADC oversampling conversion data) */ 671 #define ADC_RIGHTBITSHIFT_1 (LL_ADC_OVS_SHIFT_RIGHT_1) /*!< ADC oversampling shift of 1 (sum of the ADC conversions data is divided by 2 to result as the ADC oversampling conversion data) */ 672 #define ADC_RIGHTBITSHIFT_2 (LL_ADC_OVS_SHIFT_RIGHT_2) /*!< ADC oversampling shift of 2 (sum of the ADC conversions data is divided by 4 to result as the ADC oversampling conversion data) */ 673 #define ADC_RIGHTBITSHIFT_3 (LL_ADC_OVS_SHIFT_RIGHT_3) /*!< ADC oversampling shift of 3 (sum of the ADC conversions data is divided by 8 to result as the ADC oversampling conversion data) */ 674 #define ADC_RIGHTBITSHIFT_4 (LL_ADC_OVS_SHIFT_RIGHT_4) /*!< ADC oversampling shift of 4 (sum of the ADC conversions data is divided by 16 to result as the ADC oversampling conversion data) */ 675 #define ADC_RIGHTBITSHIFT_5 (LL_ADC_OVS_SHIFT_RIGHT_5) /*!< ADC oversampling shift of 5 (sum of the ADC conversions data is divided by 32 to result as the ADC oversampling conversion data) */ 676 #define ADC_RIGHTBITSHIFT_6 (LL_ADC_OVS_SHIFT_RIGHT_6) /*!< ADC oversampling shift of 6 (sum of the ADC conversions data is divided by 64 to result as the ADC oversampling conversion data) */ 677 #define ADC_RIGHTBITSHIFT_7 (LL_ADC_OVS_SHIFT_RIGHT_7) /*!< ADC oversampling shift of 7 (sum of the ADC conversions data is divided by 128 to result as the ADC oversampling conversion data) */ 678 #define ADC_RIGHTBITSHIFT_8 (LL_ADC_OVS_SHIFT_RIGHT_8) /*!< ADC oversampling shift of 8 (sum of the ADC conversions data is divided by 256 to result as the ADC oversampling conversion data) */ 679 /** 680 * @} 681 */ 682 683 /** @defgroup ADC_HAL_EC_OVS_DISCONT_MODE Oversampling - Discontinuous mode 684 * @{ 685 */ 686 #define ADC_TRIGGEREDMODE_SINGLE_TRIGGER (LL_ADC_OVS_REG_CONT) /*!< ADC oversampling discontinuous mode: continuous mode (all conversions of oversampling ratio are done from 1 trigger) */ 687 #define ADC_TRIGGEREDMODE_MULTI_TRIGGER (LL_ADC_OVS_REG_DISCONT) /*!< ADC oversampling discontinuous mode: discontinuous mode (each conversion of oversampling ratio needs a trigger) */ 688 /** 689 * @} 690 */ 691 692 /** @defgroup ADC_HAL_EC_OVS_SCOPE_REG Oversampling - Oversampling scope for ADC group regular 693 * @{ 694 */ 695 #define ADC_REGOVERSAMPLING_CONTINUED_MODE (LL_ADC_OVS_GRP_REGULAR_CONTINUED) /*!< Oversampling buffer maintained during injection sequence */ 696 #define ADC_REGOVERSAMPLING_RESUMED_MODE (LL_ADC_OVS_GRP_REGULAR_RESUMED) /*!< Oversampling buffer zeroed during injection sequence */ 697 /** 698 * @} 699 */ 700 701 /** @defgroup ADC_Event_type ADC Event type 702 * @{ 703 */ 704 #define ADC_EOSMP_EVENT (ADC_FLAG_EOSMP) /*!< ADC End of Sampling event */ 705 #define ADC_AWD1_EVENT (ADC_FLAG_AWD1) /*!< ADC Analog watchdog 1 event (main analog watchdog, present on all STM32 series) */ 706 #define ADC_AWD2_EVENT (ADC_FLAG_AWD2) /*!< ADC Analog watchdog 2 event (additional analog watchdog, not present on all STM32 series) */ 707 #define ADC_AWD3_EVENT (ADC_FLAG_AWD3) /*!< ADC Analog watchdog 3 event (additional analog watchdog, not present on all STM32 series) */ 708 #define ADC_OVR_EVENT (ADC_FLAG_OVR) /*!< ADC overrun event */ 709 #define ADC_JQOVF_EVENT (ADC_FLAG_JQOVF) /*!< ADC Injected Context Queue Overflow event */ 710 /** 711 * @} 712 */ 713 #define ADC_AWD_EVENT ADC_AWD1_EVENT /*!< ADC Analog watchdog 1 event: Naming for compatibility with other STM32 devices having only one analog watchdog */ 714 715 /** @defgroup ADC_interrupts_definition ADC interrupts definition 716 * @{ 717 */ 718 #define ADC_IT_RDY ADC_IER_ADRDYIE /*!< ADC Ready interrupt source */ 719 #define ADC_IT_EOSMP ADC_IER_EOSMPIE /*!< ADC End of sampling interrupt source */ 720 #define ADC_IT_EOC ADC_IER_EOCIE /*!< ADC End of regular conversion interrupt source */ 721 #define ADC_IT_EOS ADC_IER_EOSIE /*!< ADC End of regular sequence of conversions interrupt source */ 722 #define ADC_IT_OVR ADC_IER_OVRIE /*!< ADC overrun interrupt source */ 723 #define ADC_IT_JEOC ADC_IER_JEOCIE /*!< ADC End of injected conversion interrupt source */ 724 #define ADC_IT_JEOS ADC_IER_JEOSIE /*!< ADC End of injected sequence of conversions interrupt source */ 725 #define ADC_IT_AWD1 ADC_IER_AWD1IE /*!< ADC Analog watchdog 1 interrupt source (main analog watchdog) */ 726 #define ADC_IT_AWD2 ADC_IER_AWD2IE /*!< ADC Analog watchdog 2 interrupt source (additional analog watchdog) */ 727 #define ADC_IT_AWD3 ADC_IER_AWD3IE /*!< ADC Analog watchdog 3 interrupt source (additional analog watchdog) */ 728 #define ADC_IT_JQOVF ADC_IER_JQOVFIE /*!< ADC Injected Context Queue Overflow interrupt source */ 729 730 #define ADC_IT_AWD ADC_IT_AWD1 /*!< ADC Analog watchdog 1 interrupt source: naming for compatibility with other STM32 devices having only one analog watchdog */ 731 732 /** 733 * @} 734 */ 735 736 /** @defgroup ADC_flags_definition ADC flags definition 737 * @{ 738 */ 739 #define ADC_FLAG_RDY ADC_ISR_ADRDY /*!< ADC Ready flag */ 740 #define ADC_FLAG_EOSMP ADC_ISR_EOSMP /*!< ADC End of Sampling flag */ 741 #define ADC_FLAG_EOC ADC_ISR_EOC /*!< ADC End of Regular Conversion flag */ 742 #define ADC_FLAG_EOS ADC_ISR_EOS /*!< ADC End of Regular sequence of Conversions flag */ 743 #define ADC_FLAG_OVR ADC_ISR_OVR /*!< ADC overrun flag */ 744 #define ADC_FLAG_JEOC ADC_ISR_JEOC /*!< ADC End of Injected Conversion flag */ 745 #define ADC_FLAG_JEOS ADC_ISR_JEOS /*!< ADC End of Injected sequence of Conversions flag */ 746 #define ADC_FLAG_AWD1 ADC_ISR_AWD1 /*!< ADC Analog watchdog 1 flag (main analog watchdog) */ 747 #define ADC_FLAG_AWD2 ADC_ISR_AWD2 /*!< ADC Analog watchdog 2 flag (additional analog watchdog) */ 748 #define ADC_FLAG_AWD3 ADC_ISR_AWD3 /*!< ADC Analog watchdog 3 flag (additional analog watchdog) */ 749 #define ADC_FLAG_JQOVF ADC_ISR_JQOVF /*!< ADC Injected Context Queue Overflow flag */ 750 751 #define ADC_FLAG_AWD ADC_FLAG_AWD1 /*!< ADC Analog watchdog 1 flag: Naming for compatibility with other STM32 devices having only one analog watchdog */ 752 753 #define ADC_FLAG_ALL (ADC_FLAG_RDY | ADC_FLAG_EOSMP | ADC_FLAG_EOC | ADC_FLAG_EOS | \ 754 ADC_FLAG_JEOC | ADC_FLAG_JEOS | ADC_FLAG_OVR | ADC_FLAG_AWD1 | \ 755 ADC_FLAG_AWD2 | ADC_FLAG_AWD3 | ADC_FLAG_JQOVF) /*!< ADC all flags */ 756 757 /* Combination of all post-conversion flags bits: EOC/EOS, JEOC/JEOS, OVR, AWDx, JQOVF */ 758 #define ADC_FLAG_POSTCONV_ALL (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_JEOC | ADC_FLAG_JEOS | \ 759 ADC_FLAG_OVR | ADC_FLAG_AWD1 | ADC_FLAG_AWD2 | ADC_FLAG_AWD3 | \ 760 ADC_FLAG_JQOVF) /*!< ADC post-conversion all flags */ 761 762 /** 763 * @} 764 */ 765 766 /** 767 * @} 768 */ 769 770 /* Private macro -------------------------------------------------------------*/ 771 772 /** @defgroup ADC_Private_Macros ADC Private Macros 773 * @{ 774 */ 775 /* Macro reserved for internal HAL driver usage, not intended to be used in */ 776 /* code of final user. */ 777 778 /** 779 * @brief Return resolution bits in CFGR register RES[1:0] field. 780 * @param __HANDLE__ ADC handle 781 * @retval Value of bitfield RES in CFGR register. 782 */ 783 #define ADC_GET_RESOLUTION(__HANDLE__) \ 784 (LL_ADC_GetResolution((__HANDLE__)->Instance)) 785 786 /** 787 * @brief Clear ADC error code (set it to no error code "HAL_ADC_ERROR_NONE"). 788 * @param __HANDLE__ ADC handle 789 * @retval None 790 */ 791 #define ADC_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE) 792 793 /** 794 * @brief Verification of ADC state: enabled or disabled. 795 * @param __HANDLE__ ADC handle 796 * @retval SET (ADC enabled) or RESET (ADC disabled) 797 */ 798 #define ADC_IS_ENABLE(__HANDLE__) \ 799 ((((((__HANDLE__)->Instance->CR) & (ADC_CR_ADEN | ADC_CR_ADDIS)) == ADC_CR_ADEN) && \ 800 ((((__HANDLE__)->Instance->ISR) & ADC_FLAG_RDY) == ADC_FLAG_RDY) \ 801 ) ? SET : RESET) 802 803 /** 804 * @brief Check if conversion is on going on regular group. 805 * @param __HANDLE__ ADC handle 806 * @retval Value "0" (no conversion is on going) or value "1" (conversion is on going) 807 */ 808 #define ADC_IS_CONVERSION_ONGOING_REGULAR(__HANDLE__) \ 809 (LL_ADC_REG_IsConversionOngoing((__HANDLE__)->Instance)) 810 811 /** 812 * @brief Simultaneously clear and set specific bits of the handle State. 813 * @note ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(), 814 * the first parameter is the ADC handle State, the second parameter is the 815 * bit field to clear, the third and last parameter is the bit field to set. 816 * @retval None 817 */ 818 #define ADC_STATE_CLR_SET MODIFY_REG 819 820 /** 821 * @brief Verify that a given value is aligned with the ADC resolution range. 822 * @param __RESOLUTION__ ADC resolution (12, 10, 8 or 6 bits). 823 * @param __ADC_VALUE__ value checked against the resolution. 824 * @retval SET (__ADC_VALUE__ in line with __RESOLUTION__) or RESET (__ADC_VALUE__ not in line with __RESOLUTION__) 825 */ 826 #define IS_ADC_RANGE(__RESOLUTION__, __ADC_VALUE__) \ 827 ((__ADC_VALUE__) <= __LL_ADC_DIGITAL_SCALE(__RESOLUTION__)) 828 829 /** 830 * @brief Verify the length of the scheduled regular conversions group. 831 * @param __LENGTH__ number of programmed conversions. 832 * @retval SET (__LENGTH__ is within the maximum number of possible programmable regular conversions) or RESET (__LENGTH__ is null or too large) 833 */ 834 #define IS_ADC_REGULAR_NB_CONV(__LENGTH__) (((__LENGTH__) >= (1UL)) && ((__LENGTH__) <= (16UL))) 835 836 837 /** 838 * @brief Verify the number of scheduled regular conversions in discontinuous mode. 839 * @param NUMBER number of scheduled regular conversions in discontinuous mode. 840 * @retval SET (NUMBER is within the maximum number of regular conversions in discontinuous mode) or RESET (NUMBER is null or too large) 841 */ 842 #define IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= (1UL)) && ((NUMBER) <= (8UL))) 843 844 845 /** 846 * @brief Verify the ADC clock setting. 847 * @param __ADC_CLOCK__ programmed ADC clock. 848 * @retval SET (__ADC_CLOCK__ is a valid value) or RESET (__ADC_CLOCK__ is invalid) 849 */ 850 #define IS_ADC_CLOCKPRESCALER(__ADC_CLOCK__) (((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV1) || \ 851 ((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV2) || \ 852 ((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV4) || \ 853 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV1) || \ 854 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV2) || \ 855 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV4) || \ 856 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV6) || \ 857 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV8) || \ 858 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV10) || \ 859 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV12) || \ 860 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV16) || \ 861 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV32) || \ 862 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV64) || \ 863 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV128) || \ 864 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV256) ) 865 866 /** 867 * @brief Verify the ADC resolution setting. 868 * @param __RESOLUTION__ programmed ADC resolution. 869 * @retval SET (__RESOLUTION__ is a valid value) or RESET (__RESOLUTION__ is invalid) 870 */ 871 #define IS_ADC_RESOLUTION(__RESOLUTION__) (((__RESOLUTION__) == ADC_RESOLUTION_12B) || \ 872 ((__RESOLUTION__) == ADC_RESOLUTION_10B) || \ 873 ((__RESOLUTION__) == ADC_RESOLUTION_8B) || \ 874 ((__RESOLUTION__) == ADC_RESOLUTION_6B) ) 875 876 /** 877 * @brief Verify the ADC resolution setting when limited to 6 or 8 bits. 878 * @param __RESOLUTION__ programmed ADC resolution when limited to 6 or 8 bits. 879 * @retval SET (__RESOLUTION__ is a valid value) or RESET (__RESOLUTION__ is invalid) 880 */ 881 #define IS_ADC_RESOLUTION_8_6_BITS(__RESOLUTION__) (((__RESOLUTION__) == ADC_RESOLUTION_8B) || \ 882 ((__RESOLUTION__) == ADC_RESOLUTION_6B) ) 883 884 /** 885 * @brief Verify the ADC converted data alignment. 886 * @param __ALIGN__ programmed ADC converted data alignment. 887 * @retval SET (__ALIGN__ is a valid value) or RESET (__ALIGN__ is invalid) 888 */ 889 #define IS_ADC_DATA_ALIGN(__ALIGN__) (((__ALIGN__) == ADC_DATAALIGN_RIGHT) || \ 890 ((__ALIGN__) == ADC_DATAALIGN_LEFT) ) 891 892 /** 893 * @brief Verify the ADC scan mode. 894 * @param __SCAN_MODE__ programmed ADC scan mode. 895 * @retval SET (__SCAN_MODE__ is valid) or RESET (__SCAN_MODE__ is invalid) 896 */ 897 #define IS_ADC_SCAN_MODE(__SCAN_MODE__) (((__SCAN_MODE__) == ADC_SCAN_DISABLE) || \ 898 ((__SCAN_MODE__) == ADC_SCAN_ENABLE) ) 899 900 /** 901 * @brief Verify the ADC edge trigger setting for regular group. 902 * @param __EDGE__ programmed ADC edge trigger setting. 903 * @retval SET (__EDGE__ is a valid value) or RESET (__EDGE__ is invalid) 904 */ 905 #define IS_ADC_EXTTRIG_EDGE(__EDGE__) (((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \ 906 ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_RISING) || \ 907 ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || \ 908 ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING) ) 909 910 /** 911 * @brief Verify the ADC regular conversions external trigger. 912 * @param __HANDLE__ ADC handle 913 * @param __REGTRIG__ programmed ADC regular conversions external trigger. 914 * @retval SET (__REGTRIG__ is a valid value) or RESET (__REGTRIG__ is invalid) 915 */ 916 #define IS_ADC_EXTTRIG(__HANDLE__, __REGTRIG__) (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC1) || \ 917 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC2) || \ 918 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC3) || \ 919 ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC2) || \ 920 ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_TRGO) || \ 921 ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC4) || \ 922 ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT11) || \ 923 ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO) || \ 924 ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO2) || \ 925 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO) || \ 926 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO2) || \ 927 ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_TRGO) || \ 928 ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_TRGO) || \ 929 ((__REGTRIG__) == ADC_EXTERNALTRIG_T6_TRGO) || \ 930 ((__REGTRIG__) == ADC_EXTERNALTRIG_T15_TRGO) || \ 931 ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC4) || \ 932 ((__REGTRIG__) == ADC_SOFTWARE_START) ) 933 934 /** 935 * @brief Verify the ADC regular conversions check for converted data availability. 936 * @param __EOC_SELECTION__ converted data availability check. 937 * @retval SET (__EOC_SELECTION__ is a valid value) or RESET (__EOC_SELECTION__ is invalid) 938 */ 939 #define IS_ADC_EOC_SELECTION(__EOC_SELECTION__) (((__EOC_SELECTION__) == ADC_EOC_SINGLE_CONV) || \ 940 ((__EOC_SELECTION__) == ADC_EOC_SEQ_CONV) ) 941 942 /** 943 * @brief Verify the ADC regular conversions overrun handling. 944 * @param __OVR__ ADC regular conversions overrun handling. 945 * @retval SET (__OVR__ is a valid value) or RESET (__OVR__ is invalid) 946 */ 947 #define IS_ADC_OVERRUN(__OVR__) (((__OVR__) == ADC_OVR_DATA_PRESERVED) || \ 948 ((__OVR__) == ADC_OVR_DATA_OVERWRITTEN) ) 949 950 /** 951 * @brief Verify the ADC conversions sampling time. 952 * @param __TIME__ ADC conversions sampling time. 953 * @retval SET (__TIME__ is a valid value) or RESET (__TIME__ is invalid) 954 */ 955 #if defined(ADC_SMPR1_SMPPLUS) 956 #define IS_ADC_SAMPLE_TIME(__TIME__) (((__TIME__) == ADC_SAMPLETIME_2CYCLES_5) || \ 957 ((__TIME__) == ADC_SAMPLETIME_3CYCLES_5) || \ 958 ((__TIME__) == ADC_SAMPLETIME_6CYCLES_5) || \ 959 ((__TIME__) == ADC_SAMPLETIME_12CYCLES_5) || \ 960 ((__TIME__) == ADC_SAMPLETIME_24CYCLES_5) || \ 961 ((__TIME__) == ADC_SAMPLETIME_47CYCLES_5) || \ 962 ((__TIME__) == ADC_SAMPLETIME_92CYCLES_5) || \ 963 ((__TIME__) == ADC_SAMPLETIME_247CYCLES_5) || \ 964 ((__TIME__) == ADC_SAMPLETIME_640CYCLES_5) ) 965 #else 966 #define IS_ADC_SAMPLE_TIME(__TIME__) (((__TIME__) == ADC_SAMPLETIME_2CYCLES_5) || \ 967 ((__TIME__) == ADC_SAMPLETIME_6CYCLES_5) || \ 968 ((__TIME__) == ADC_SAMPLETIME_12CYCLES_5) || \ 969 ((__TIME__) == ADC_SAMPLETIME_24CYCLES_5) || \ 970 ((__TIME__) == ADC_SAMPLETIME_47CYCLES_5) || \ 971 ((__TIME__) == ADC_SAMPLETIME_92CYCLES_5) || \ 972 ((__TIME__) == ADC_SAMPLETIME_247CYCLES_5) || \ 973 ((__TIME__) == ADC_SAMPLETIME_640CYCLES_5) ) 974 #endif /* ADC_SMPR1_SMPPLUS */ 975 976 /** 977 * @brief Verify the ADC regular channel setting. 978 * @param __CHANNEL__ programmed ADC regular channel. 979 * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid) 980 */ 981 #define IS_ADC_REGULAR_RANK(__CHANNEL__) (((__CHANNEL__) == ADC_REGULAR_RANK_1 ) || \ 982 ((__CHANNEL__) == ADC_REGULAR_RANK_2 ) || \ 983 ((__CHANNEL__) == ADC_REGULAR_RANK_3 ) || \ 984 ((__CHANNEL__) == ADC_REGULAR_RANK_4 ) || \ 985 ((__CHANNEL__) == ADC_REGULAR_RANK_5 ) || \ 986 ((__CHANNEL__) == ADC_REGULAR_RANK_6 ) || \ 987 ((__CHANNEL__) == ADC_REGULAR_RANK_7 ) || \ 988 ((__CHANNEL__) == ADC_REGULAR_RANK_8 ) || \ 989 ((__CHANNEL__) == ADC_REGULAR_RANK_9 ) || \ 990 ((__CHANNEL__) == ADC_REGULAR_RANK_10) || \ 991 ((__CHANNEL__) == ADC_REGULAR_RANK_11) || \ 992 ((__CHANNEL__) == ADC_REGULAR_RANK_12) || \ 993 ((__CHANNEL__) == ADC_REGULAR_RANK_13) || \ 994 ((__CHANNEL__) == ADC_REGULAR_RANK_14) || \ 995 ((__CHANNEL__) == ADC_REGULAR_RANK_15) || \ 996 ((__CHANNEL__) == ADC_REGULAR_RANK_16) ) 997 998 /** 999 * @} 1000 */ 1001 1002 1003 /* Private constants ---------------------------------------------------------*/ 1004 1005 /** @defgroup ADC_Private_Constants ADC Private Constants 1006 * @{ 1007 */ 1008 1009 /* Fixed timeout values for ADC conversion (including sampling time) */ 1010 /* Maximum sampling time is 640.5 ADC clock cycle (SMPx[2:0] = 0b111 */ 1011 /* Maximum conversion time is 12.5 + Maximum sampling time */ 1012 /* or 12.5 + 640.5 = 653 ADC clock cycles */ 1013 /* Minimum ADC Clock frequency is 0.14 MHz */ 1014 /* Maximum conversion time is */ 1015 /* 653 / 0.14 MHz = 4.66 ms */ 1016 #define ADC_STOP_CONVERSION_TIMEOUT ( 5UL) /*!< ADC stop time-out value */ 1017 1018 /* Delay for temperature sensor stabilization time. */ 1019 /* Maximum delay is 120us (refer device datasheet, parameter tSTART). */ 1020 /* Unit: us */ 1021 #define ADC_TEMPSENSOR_DELAY_US (LL_ADC_DELAY_TEMPSENSOR_STAB_US) 1022 1023 /** 1024 * @} 1025 */ 1026 1027 /* Exported macro ------------------------------------------------------------*/ 1028 1029 /** @defgroup ADC_Exported_Macros ADC Exported Macros 1030 * @{ 1031 */ 1032 /* Macro for internal HAL driver usage, and possibly can be used into code of */ 1033 /* final user. */ 1034 1035 /** @defgroup ADC_HAL_EM_HANDLE_IT_FLAG HAL ADC macro to manage HAL ADC handle, IT and flags. 1036 * @{ 1037 */ 1038 1039 /** @brief Reset ADC handle state. 1040 * @param __HANDLE__ ADC handle 1041 * @retval None 1042 */ 1043 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 1044 #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \ 1045 do{ \ 1046 (__HANDLE__)->State = HAL_ADC_STATE_RESET; \ 1047 (__HANDLE__)->MspInitCallback = NULL; \ 1048 (__HANDLE__)->MspDeInitCallback = NULL; \ 1049 } while(0) 1050 #else 1051 #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \ 1052 ((__HANDLE__)->State = HAL_ADC_STATE_RESET) 1053 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 1054 1055 /** 1056 * @brief Enable ADC interrupt. 1057 * @param __HANDLE__ ADC handle 1058 * @param __INTERRUPT__ ADC Interrupt 1059 * This parameter can be one of the following values: 1060 * @arg @ref ADC_IT_RDY ADC Ready interrupt source 1061 * @arg @ref ADC_IT_EOSMP ADC End of Sampling interrupt source 1062 * @arg @ref ADC_IT_EOC ADC End of Regular Conversion interrupt source 1063 * @arg @ref ADC_IT_EOS ADC End of Regular sequence of Conversions interrupt source 1064 * @arg @ref ADC_IT_OVR ADC overrun interrupt source 1065 * @arg @ref ADC_IT_JEOC ADC End of Injected Conversion interrupt source 1066 * @arg @ref ADC_IT_JEOS ADC End of Injected sequence of Conversions interrupt source 1067 * @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog) 1068 * @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog) 1069 * @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog) 1070 * @arg @ref ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source. 1071 * @retval None 1072 */ 1073 #define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \ 1074 (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__)) 1075 1076 /** 1077 * @brief Disable ADC interrupt. 1078 * @param __HANDLE__ ADC handle 1079 * @param __INTERRUPT__ ADC Interrupt 1080 * This parameter can be one of the following values: 1081 * @arg @ref ADC_IT_RDY ADC Ready interrupt source 1082 * @arg @ref ADC_IT_EOSMP ADC End of Sampling interrupt source 1083 * @arg @ref ADC_IT_EOC ADC End of Regular Conversion interrupt source 1084 * @arg @ref ADC_IT_EOS ADC End of Regular sequence of Conversions interrupt source 1085 * @arg @ref ADC_IT_OVR ADC overrun interrupt source 1086 * @arg @ref ADC_IT_JEOC ADC End of Injected Conversion interrupt source 1087 * @arg @ref ADC_IT_JEOS ADC End of Injected sequence of Conversions interrupt source 1088 * @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog) 1089 * @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog) 1090 * @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog) 1091 * @arg @ref ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source. 1092 * @retval None 1093 */ 1094 #define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \ 1095 (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__)) 1096 1097 /** @brief Checks if the specified ADC interrupt source is enabled or disabled. 1098 * @param __HANDLE__ ADC handle 1099 * @param __INTERRUPT__ ADC interrupt source to check 1100 * This parameter can be one of the following values: 1101 * @arg @ref ADC_IT_RDY ADC Ready interrupt source 1102 * @arg @ref ADC_IT_EOSMP ADC End of Sampling interrupt source 1103 * @arg @ref ADC_IT_EOC ADC End of Regular Conversion interrupt source 1104 * @arg @ref ADC_IT_EOS ADC End of Regular sequence of Conversions interrupt source 1105 * @arg @ref ADC_IT_OVR ADC overrun interrupt source 1106 * @arg @ref ADC_IT_JEOC ADC End of Injected Conversion interrupt source 1107 * @arg @ref ADC_IT_JEOS ADC End of Injected sequence of Conversions interrupt source 1108 * @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog) 1109 * @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog) 1110 * @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog) 1111 * @arg @ref ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source. 1112 * @retval State of interruption (SET or RESET) 1113 */ 1114 #define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \ 1115 (((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) 1116 1117 /** 1118 * @brief Check whether the specified ADC flag is set or not. 1119 * @param __HANDLE__ ADC handle 1120 * @param __FLAG__ ADC flag 1121 * This parameter can be one of the following values: 1122 * @arg @ref ADC_FLAG_RDY ADC Ready flag 1123 * @arg @ref ADC_FLAG_EOSMP ADC End of Sampling flag 1124 * @arg @ref ADC_FLAG_EOC ADC End of Regular Conversion flag 1125 * @arg @ref ADC_FLAG_EOS ADC End of Regular sequence of Conversions flag 1126 * @arg @ref ADC_FLAG_OVR ADC overrun flag 1127 * @arg @ref ADC_FLAG_JEOC ADC End of Injected Conversion flag 1128 * @arg @ref ADC_FLAG_JEOS ADC End of Injected sequence of Conversions flag 1129 * @arg @ref ADC_FLAG_AWD1 ADC Analog watchdog 1 flag (main analog watchdog) 1130 * @arg @ref ADC_FLAG_AWD2 ADC Analog watchdog 2 flag (additional analog watchdog) 1131 * @arg @ref ADC_FLAG_AWD3 ADC Analog watchdog 3 flag (additional analog watchdog) 1132 * @arg @ref ADC_FLAG_JQOVF ADC Injected Context Queue Overflow flag. 1133 * @retval State of flag (TRUE or FALSE). 1134 */ 1135 #define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) \ 1136 ((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__)) 1137 1138 /** 1139 * @brief Clear the specified ADC flag. 1140 * @param __HANDLE__ ADC handle 1141 * @param __FLAG__ ADC flag 1142 * This parameter can be one of the following values: 1143 * @arg @ref ADC_FLAG_RDY ADC Ready flag 1144 * @arg @ref ADC_FLAG_EOSMP ADC End of Sampling flag 1145 * @arg @ref ADC_FLAG_EOC ADC End of Regular Conversion flag 1146 * @arg @ref ADC_FLAG_EOS ADC End of Regular sequence of Conversions flag 1147 * @arg @ref ADC_FLAG_OVR ADC overrun flag 1148 * @arg @ref ADC_FLAG_JEOC ADC End of Injected Conversion flag 1149 * @arg @ref ADC_FLAG_JEOS ADC End of Injected sequence of Conversions flag 1150 * @arg @ref ADC_FLAG_AWD1 ADC Analog watchdog 1 flag (main analog watchdog) 1151 * @arg @ref ADC_FLAG_AWD2 ADC Analog watchdog 2 flag (additional analog watchdog) 1152 * @arg @ref ADC_FLAG_AWD3 ADC Analog watchdog 3 flag (additional analog watchdog) 1153 * @arg @ref ADC_FLAG_JQOVF ADC Injected Context Queue Overflow flag. 1154 * @retval None 1155 */ 1156 /* Note: bit cleared bit by writing 1 (writing 0 has no effect on any bit of register ISR) */ 1157 #define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) \ 1158 (((__HANDLE__)->Instance->ISR) = (__FLAG__)) 1159 1160 /** 1161 * @} 1162 */ 1163 1164 /** @defgroup ADC_HAL_EM_HELPER_MACRO HAL ADC helper macro 1165 * @{ 1166 */ 1167 1168 /** 1169 * @brief Helper macro to get ADC channel number in decimal format 1170 * from literals ADC_CHANNEL_x. 1171 * @note Example: 1172 * __HAL_ADC_CHANNEL_TO_DECIMAL_NB(ADC_CHANNEL_4) 1173 * will return decimal number "4". 1174 * @note The input can be a value from functions where a channel 1175 * number is returned, either defined with number 1176 * or with bitfield (only one bit must be set). 1177 * @param __CHANNEL__ This parameter can be one of the following values: 1178 * @arg @ref ADC_CHANNEL_0 1179 * @arg @ref ADC_CHANNEL_1 (7) 1180 * @arg @ref ADC_CHANNEL_2 (7) 1181 * @arg @ref ADC_CHANNEL_3 (7) 1182 * @arg @ref ADC_CHANNEL_4 (7) 1183 * @arg @ref ADC_CHANNEL_5 (7) 1184 * @arg @ref ADC_CHANNEL_6 1185 * @arg @ref ADC_CHANNEL_7 1186 * @arg @ref ADC_CHANNEL_8 1187 * @arg @ref ADC_CHANNEL_9 1188 * @arg @ref ADC_CHANNEL_10 1189 * @arg @ref ADC_CHANNEL_11 1190 * @arg @ref ADC_CHANNEL_12 1191 * @arg @ref ADC_CHANNEL_13 1192 * @arg @ref ADC_CHANNEL_14 1193 * @arg @ref ADC_CHANNEL_15 1194 * @arg @ref ADC_CHANNEL_16 1195 * @arg @ref ADC_CHANNEL_17 1196 * @arg @ref ADC_CHANNEL_18 1197 * @arg @ref ADC_CHANNEL_VREFINT (1) 1198 * @arg @ref ADC_CHANNEL_TEMPSENSOR (4) 1199 * @arg @ref ADC_CHANNEL_VBAT (4) 1200 * @arg @ref ADC_CHANNEL_DAC1CH1 (5) 1201 * @arg @ref ADC_CHANNEL_DAC1CH2 (5) 1202 * @arg @ref ADC_CHANNEL_DAC1CH1_ADC2 (2)(6) 1203 * @arg @ref ADC_CHANNEL_DAC1CH2_ADC2 (2)(6) 1204 * @arg @ref ADC_CHANNEL_DAC1CH1_ADC3 (3)(6) 1205 * @arg @ref ADC_CHANNEL_DAC1CH2_ADC3 (3)(6) 1206 * 1207 * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n 1208 * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n 1209 * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n 1210 * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n 1211 * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n 1212 * (6) On STM32L4, parameter available on devices with several ADC instances.\n 1213 * (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). 1214 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)). 1215 * @retval Value between Min_Data=0 and Max_Data=18 1216 */ 1217 #define __HAL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \ 1218 __LL_ADC_CHANNEL_TO_DECIMAL_NB((__CHANNEL__)) 1219 1220 /** 1221 * @brief Helper macro to get ADC channel in literal format ADC_CHANNEL_x 1222 * from number in decimal format. 1223 * @note Example: 1224 * __HAL_ADC_DECIMAL_NB_TO_CHANNEL(4) 1225 * will return a data equivalent to "ADC_CHANNEL_4". 1226 * @param __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18 1227 * @retval Returned value can be one of the following values: 1228 * @arg @ref ADC_CHANNEL_0 1229 * @arg @ref ADC_CHANNEL_1 (7) 1230 * @arg @ref ADC_CHANNEL_2 (7) 1231 * @arg @ref ADC_CHANNEL_3 (7) 1232 * @arg @ref ADC_CHANNEL_4 (7) 1233 * @arg @ref ADC_CHANNEL_5 (7) 1234 * @arg @ref ADC_CHANNEL_6 1235 * @arg @ref ADC_CHANNEL_7 1236 * @arg @ref ADC_CHANNEL_8 1237 * @arg @ref ADC_CHANNEL_9 1238 * @arg @ref ADC_CHANNEL_10 1239 * @arg @ref ADC_CHANNEL_11 1240 * @arg @ref ADC_CHANNEL_12 1241 * @arg @ref ADC_CHANNEL_13 1242 * @arg @ref ADC_CHANNEL_14 1243 * @arg @ref ADC_CHANNEL_15 1244 * @arg @ref ADC_CHANNEL_16 1245 * @arg @ref ADC_CHANNEL_17 1246 * @arg @ref ADC_CHANNEL_18 1247 * @arg @ref ADC_CHANNEL_VREFINT (1) 1248 * @arg @ref ADC_CHANNEL_TEMPSENSOR (4) 1249 * @arg @ref ADC_CHANNEL_VBAT (4) 1250 * @arg @ref ADC_CHANNEL_DAC1CH1 (5) 1251 * @arg @ref ADC_CHANNEL_DAC1CH2 (5) 1252 * @arg @ref ADC_CHANNEL_DAC1CH1_ADC2 (2)(6) 1253 * @arg @ref ADC_CHANNEL_DAC1CH2_ADC2 (2)(6) 1254 * @arg @ref ADC_CHANNEL_DAC1CH1_ADC3 (3)(6) 1255 * @arg @ref ADC_CHANNEL_DAC1CH2_ADC3 (3)(6) 1256 * 1257 * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n 1258 * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n 1259 * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n 1260 * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n 1261 * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n 1262 * (6) On STM32L4, parameter available on devices with several ADC instances.\n 1263 * (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). 1264 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).\n 1265 * (1, 2, 3, 4) For ADC channel read back from ADC register, 1266 * comparison with internal channel parameter to be done 1267 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). 1268 */ 1269 #define __HAL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \ 1270 __LL_ADC_DECIMAL_NB_TO_CHANNEL((__DECIMAL_NB__)) 1271 1272 /** 1273 * @brief Helper macro to determine whether the selected channel 1274 * corresponds to literal definitions of driver. 1275 * @note The different literal definitions of ADC channels are: 1276 * - ADC internal channel: 1277 * ADC_CHANNEL_VREFINT, ADC_CHANNEL_TEMPSENSOR, ... 1278 * - ADC external channel (channel connected to a GPIO pin): 1279 * ADC_CHANNEL_1, ADC_CHANNEL_2, ... 1280 * @note The channel parameter must be a value defined from literal 1281 * definition of a ADC internal channel (ADC_CHANNEL_VREFINT, 1282 * ADC_CHANNEL_TEMPSENSOR, ...), 1283 * ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...), 1284 * must not be a value from functions where a channel number is 1285 * returned from ADC registers, 1286 * because internal and external channels share the same channel 1287 * number in ADC registers. The differentiation is made only with 1288 * parameters definitions of driver. 1289 * @param __CHANNEL__ This parameter can be one of the following values: 1290 * @arg @ref ADC_CHANNEL_0 1291 * @arg @ref ADC_CHANNEL_1 (7) 1292 * @arg @ref ADC_CHANNEL_2 (7) 1293 * @arg @ref ADC_CHANNEL_3 (7) 1294 * @arg @ref ADC_CHANNEL_4 (7) 1295 * @arg @ref ADC_CHANNEL_5 (7) 1296 * @arg @ref ADC_CHANNEL_6 1297 * @arg @ref ADC_CHANNEL_7 1298 * @arg @ref ADC_CHANNEL_8 1299 * @arg @ref ADC_CHANNEL_9 1300 * @arg @ref ADC_CHANNEL_10 1301 * @arg @ref ADC_CHANNEL_11 1302 * @arg @ref ADC_CHANNEL_12 1303 * @arg @ref ADC_CHANNEL_13 1304 * @arg @ref ADC_CHANNEL_14 1305 * @arg @ref ADC_CHANNEL_15 1306 * @arg @ref ADC_CHANNEL_16 1307 * @arg @ref ADC_CHANNEL_17 1308 * @arg @ref ADC_CHANNEL_18 1309 * @arg @ref ADC_CHANNEL_VREFINT (1) 1310 * @arg @ref ADC_CHANNEL_TEMPSENSOR (4) 1311 * @arg @ref ADC_CHANNEL_VBAT (4) 1312 * @arg @ref ADC_CHANNEL_DAC1CH1 (5) 1313 * @arg @ref ADC_CHANNEL_DAC1CH2 (5) 1314 * @arg @ref ADC_CHANNEL_DAC1CH1_ADC2 (2)(6) 1315 * @arg @ref ADC_CHANNEL_DAC1CH2_ADC2 (2)(6) 1316 * @arg @ref ADC_CHANNEL_DAC1CH1_ADC3 (3)(6) 1317 * @arg @ref ADC_CHANNEL_DAC1CH2_ADC3 (3)(6) 1318 * 1319 * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n 1320 * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n 1321 * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n 1322 * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n 1323 * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n 1324 * (6) On STM32L4, parameter available on devices with several ADC instances.\n 1325 * (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). 1326 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)). 1327 * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin). 1328 * Value "1" if the channel corresponds to a parameter definition of a ADC internal channel. 1329 */ 1330 #define __HAL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \ 1331 __LL_ADC_IS_CHANNEL_INTERNAL((__CHANNEL__)) 1332 1333 /** 1334 * @brief Helper macro to convert a channel defined from parameter 1335 * definition of a ADC internal channel (ADC_CHANNEL_VREFINT, 1336 * ADC_CHANNEL_TEMPSENSOR, ...), 1337 * to its equivalent parameter definition of a ADC external channel 1338 * (ADC_CHANNEL_1, ADC_CHANNEL_2, ...). 1339 * @note The channel parameter can be, additionally to a value 1340 * defined from parameter definition of a ADC internal channel 1341 * (ADC_CHANNEL_VREFINT, ADC_CHANNEL_TEMPSENSOR, ...), 1342 * a value defined from parameter definition of 1343 * ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...) 1344 * or a value from functions where a channel number is returned 1345 * from ADC registers. 1346 * @param __CHANNEL__ This parameter can be one of the following values: 1347 * @arg @ref ADC_CHANNEL_0 1348 * @arg @ref ADC_CHANNEL_1 (7) 1349 * @arg @ref ADC_CHANNEL_2 (7) 1350 * @arg @ref ADC_CHANNEL_3 (7) 1351 * @arg @ref ADC_CHANNEL_4 (7) 1352 * @arg @ref ADC_CHANNEL_5 (7) 1353 * @arg @ref ADC_CHANNEL_6 1354 * @arg @ref ADC_CHANNEL_7 1355 * @arg @ref ADC_CHANNEL_8 1356 * @arg @ref ADC_CHANNEL_9 1357 * @arg @ref ADC_CHANNEL_10 1358 * @arg @ref ADC_CHANNEL_11 1359 * @arg @ref ADC_CHANNEL_12 1360 * @arg @ref ADC_CHANNEL_13 1361 * @arg @ref ADC_CHANNEL_14 1362 * @arg @ref ADC_CHANNEL_15 1363 * @arg @ref ADC_CHANNEL_16 1364 * @arg @ref ADC_CHANNEL_17 1365 * @arg @ref ADC_CHANNEL_18 1366 * @arg @ref ADC_CHANNEL_VREFINT (1) 1367 * @arg @ref ADC_CHANNEL_TEMPSENSOR (4) 1368 * @arg @ref ADC_CHANNEL_VBAT (4) 1369 * @arg @ref ADC_CHANNEL_DAC1CH1 (5) 1370 * @arg @ref ADC_CHANNEL_DAC1CH2 (5) 1371 * @arg @ref ADC_CHANNEL_DAC1CH1_ADC2 (2)(6) 1372 * @arg @ref ADC_CHANNEL_DAC1CH2_ADC2 (2)(6) 1373 * @arg @ref ADC_CHANNEL_DAC1CH1_ADC3 (3)(6) 1374 * @arg @ref ADC_CHANNEL_DAC1CH2_ADC3 (3)(6) 1375 * 1376 * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n 1377 * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n 1378 * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n 1379 * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n 1380 * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n 1381 * (6) On STM32L4, parameter available on devices with several ADC instances.\n 1382 * (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). 1383 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)). 1384 * @retval Returned value can be one of the following values: 1385 * @arg @ref ADC_CHANNEL_0 1386 * @arg @ref ADC_CHANNEL_1 1387 * @arg @ref ADC_CHANNEL_2 1388 * @arg @ref ADC_CHANNEL_3 1389 * @arg @ref ADC_CHANNEL_4 1390 * @arg @ref ADC_CHANNEL_5 1391 * @arg @ref ADC_CHANNEL_6 1392 * @arg @ref ADC_CHANNEL_7 1393 * @arg @ref ADC_CHANNEL_8 1394 * @arg @ref ADC_CHANNEL_9 1395 * @arg @ref ADC_CHANNEL_10 1396 * @arg @ref ADC_CHANNEL_11 1397 * @arg @ref ADC_CHANNEL_12 1398 * @arg @ref ADC_CHANNEL_13 1399 * @arg @ref ADC_CHANNEL_14 1400 * @arg @ref ADC_CHANNEL_15 1401 * @arg @ref ADC_CHANNEL_16 1402 * @arg @ref ADC_CHANNEL_17 1403 * @arg @ref ADC_CHANNEL_18 1404 */ 1405 #define __HAL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) \ 1406 __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL((__CHANNEL__)) 1407 1408 /** 1409 * @brief Helper macro to determine whether the internal channel 1410 * selected is available on the ADC instance selected. 1411 * @note The channel parameter must be a value defined from parameter 1412 * definition of a ADC internal channel (ADC_CHANNEL_VREFINT, 1413 * ADC_CHANNEL_TEMPSENSOR, ...), 1414 * must not be a value defined from parameter definition of 1415 * ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...) 1416 * or a value from functions where a channel number is 1417 * returned from ADC registers, 1418 * because internal and external channels share the same channel 1419 * number in ADC registers. The differentiation is made only with 1420 * parameters definitions of driver. 1421 * @param __ADC_INSTANCE__ ADC instance 1422 * @param __CHANNEL__ This parameter can be one of the following values: 1423 * @arg @ref ADC_CHANNEL_VREFINT (1) 1424 * @arg @ref ADC_CHANNEL_TEMPSENSOR (4) 1425 * @arg @ref ADC_CHANNEL_VBAT (4) 1426 * @arg @ref ADC_CHANNEL_DAC1CH1 (5) 1427 * @arg @ref ADC_CHANNEL_DAC1CH2 (5) 1428 * @arg @ref ADC_CHANNEL_DAC1CH1_ADC2 (2)(6) 1429 * @arg @ref ADC_CHANNEL_DAC1CH2_ADC2 (2)(6) 1430 * @arg @ref ADC_CHANNEL_DAC1CH1_ADC3 (3)(6) 1431 * @arg @ref ADC_CHANNEL_DAC1CH2_ADC3 (3)(6) 1432 * 1433 * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n 1434 * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n 1435 * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n 1436 * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n 1437 * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n 1438 * (6) On STM32L4, parameter available on devices with several ADC instances. 1439 * @retval Value "0" if the internal channel selected is not available on the ADC instance selected. 1440 * Value "1" if the internal channel selected is available on the ADC instance selected. 1441 */ 1442 #define __HAL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \ 1443 __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE((__ADC_INSTANCE__), (__CHANNEL__)) 1444 1445 #if defined(ADC_MULTIMODE_SUPPORT) 1446 /** 1447 * @brief Helper macro to get the ADC multimode conversion data of ADC master 1448 * or ADC slave from raw value with both ADC conversion data concatenated. 1449 * @note This macro is intended to be used when multimode transfer by DMA 1450 * is enabled: refer to function @ref LL_ADC_SetMultiDMATransfer(). 1451 * In this case the transferred data need to processed with this macro 1452 * to separate the conversion data of ADC master and ADC slave. 1453 * @param __ADC_MULTI_MASTER_SLAVE__ This parameter can be one of the following values: 1454 * @arg @ref LL_ADC_MULTI_MASTER 1455 * @arg @ref LL_ADC_MULTI_SLAVE 1456 * @param __ADC_MULTI_CONV_DATA__ Value between Min_Data=0x000 and Max_Data=0xFFF 1457 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF 1458 */ 1459 #define __HAL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__) \ 1460 __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE((__ADC_MULTI_MASTER_SLAVE__), (__ADC_MULTI_CONV_DATA__)) 1461 #endif /* ADC_MULTIMODE_SUPPORT */ 1462 1463 /** 1464 * @brief Helper macro to select the ADC common instance 1465 * to which is belonging the selected ADC instance. 1466 * @note ADC common register instance can be used for: 1467 * - Set parameters common to several ADC instances 1468 * - Multimode (for devices with several ADC instances) 1469 * Refer to functions having argument "ADCxy_COMMON" as parameter. 1470 * @param __ADCx__ ADC instance 1471 * @retval ADC common register instance 1472 */ 1473 #define __HAL_ADC_COMMON_INSTANCE(__ADCx__) \ 1474 __LL_ADC_COMMON_INSTANCE((__ADCx__)) 1475 1476 /** 1477 * @brief Helper macro to check if all ADC instances sharing the same 1478 * ADC common instance are disabled. 1479 * @note This check is required by functions with setting conditioned to 1480 * ADC state: 1481 * All ADC instances of the ADC common group must be disabled. 1482 * Refer to functions having argument "ADCxy_COMMON" as parameter. 1483 * @note On devices with only 1 ADC common instance, parameter of this macro 1484 * is useless and can be ignored (parameter kept for compatibility 1485 * with devices featuring several ADC common instances). 1486 * @param __ADCXY_COMMON__ ADC common instance 1487 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 1488 * @retval Value "0" if all ADC instances sharing the same ADC common instance 1489 * are disabled. 1490 * Value "1" if at least one ADC instance sharing the same ADC common instance 1491 * is enabled. 1492 */ 1493 #define __HAL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \ 1494 __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE((__ADCXY_COMMON__)) 1495 1496 /** 1497 * @brief Helper macro to define the ADC conversion data full-scale digital 1498 * value corresponding to the selected ADC resolution. 1499 * @note ADC conversion data full-scale corresponds to voltage range 1500 * determined by analog voltage references Vref+ and Vref- 1501 * (refer to reference manual). 1502 * @param __ADC_RESOLUTION__ This parameter can be one of the following values: 1503 * @arg @ref ADC_RESOLUTION_12B 1504 * @arg @ref ADC_RESOLUTION_10B 1505 * @arg @ref ADC_RESOLUTION_8B 1506 * @arg @ref ADC_RESOLUTION_6B 1507 * @retval ADC conversion data full-scale digital value 1508 */ 1509 #define __HAL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \ 1510 __LL_ADC_DIGITAL_SCALE((__ADC_RESOLUTION__)) 1511 1512 /** 1513 * @brief Helper macro to convert the ADC conversion data from 1514 * a resolution to another resolution. 1515 * @param __DATA__ ADC conversion data to be converted 1516 * @param __ADC_RESOLUTION_CURRENT__ Resolution of to the data to be converted 1517 * This parameter can be one of the following values: 1518 * @arg @ref ADC_RESOLUTION_12B 1519 * @arg @ref ADC_RESOLUTION_10B 1520 * @arg @ref ADC_RESOLUTION_8B 1521 * @arg @ref ADC_RESOLUTION_6B 1522 * @param __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion 1523 * This parameter can be one of the following values: 1524 * @arg @ref ADC_RESOLUTION_12B 1525 * @arg @ref ADC_RESOLUTION_10B 1526 * @arg @ref ADC_RESOLUTION_8B 1527 * @arg @ref ADC_RESOLUTION_6B 1528 * @retval ADC conversion data to the requested resolution 1529 */ 1530 #define __HAL_ADC_CONVERT_DATA_RESOLUTION(__DATA__,\ 1531 __ADC_RESOLUTION_CURRENT__,\ 1532 __ADC_RESOLUTION_TARGET__) \ 1533 __LL_ADC_CONVERT_DATA_RESOLUTION((__DATA__),\ 1534 (__ADC_RESOLUTION_CURRENT__),\ 1535 (__ADC_RESOLUTION_TARGET__)) 1536 1537 /** 1538 * @brief Helper macro to calculate the voltage (unit: mVolt) 1539 * corresponding to a ADC conversion data (unit: digital value). 1540 * @note Analog reference voltage (Vref+) must be either known from 1541 * user board environment or can be calculated using ADC measurement 1542 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). 1543 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV) 1544 * @param __ADC_DATA__ ADC conversion data (resolution 12 bits) 1545 * (unit: digital value). 1546 * @param __ADC_RESOLUTION__ This parameter can be one of the following values: 1547 * @arg @ref ADC_RESOLUTION_12B 1548 * @arg @ref ADC_RESOLUTION_10B 1549 * @arg @ref ADC_RESOLUTION_8B 1550 * @arg @ref ADC_RESOLUTION_6B 1551 * @retval ADC conversion data equivalent voltage value (unit: mVolt) 1552 */ 1553 #define __HAL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\ 1554 __ADC_DATA__,\ 1555 __ADC_RESOLUTION__) \ 1556 __LL_ADC_CALC_DATA_TO_VOLTAGE((__VREFANALOG_VOLTAGE__),\ 1557 (__ADC_DATA__),\ 1558 (__ADC_RESOLUTION__)) 1559 1560 /** 1561 * @brief Helper macro to calculate analog reference voltage (Vref+) 1562 * (unit: mVolt) from ADC conversion data of internal voltage 1563 * reference VrefInt. 1564 * @note Computation is using VrefInt calibration value 1565 * stored in system memory for each device during production. 1566 * @note This voltage depends on user board environment: voltage level 1567 * connected to pin Vref+. 1568 * On devices with small package, the pin Vref+ is not present 1569 * and internally bonded to pin Vdda. 1570 * @note On this STM32 series, calibration data of internal voltage reference 1571 * VrefInt corresponds to a resolution of 12 bits, 1572 * this is the recommended ADC resolution to convert voltage of 1573 * internal voltage reference VrefInt. 1574 * Otherwise, this macro performs the processing to scale 1575 * ADC conversion data to 12 bits. 1576 * @param __VREFINT_ADC_DATA__ ADC conversion data (resolution 12 bits) 1577 * of internal voltage reference VrefInt (unit: digital value). 1578 * @param __ADC_RESOLUTION__ This parameter can be one of the following values: 1579 * @arg @ref ADC_RESOLUTION_12B 1580 * @arg @ref ADC_RESOLUTION_10B 1581 * @arg @ref ADC_RESOLUTION_8B 1582 * @arg @ref ADC_RESOLUTION_6B 1583 * @retval Analog reference voltage (unit: mV) 1584 */ 1585 #define __HAL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\ 1586 __ADC_RESOLUTION__) \ 1587 __LL_ADC_CALC_VREFANALOG_VOLTAGE((__VREFINT_ADC_DATA__),\ 1588 (__ADC_RESOLUTION__)) 1589 1590 /** 1591 * @brief Helper macro to calculate the temperature (unit: degree Celsius) 1592 * from ADC conversion data of internal temperature sensor. 1593 * @note Computation is using temperature sensor calibration values 1594 * stored in system memory for each device during production. 1595 * @note Calculation formula: 1596 * Temperature = ((TS_ADC_DATA - TS_CAL1) 1597 * * (TS_CAL2_TEMP - TS_CAL1_TEMP)) 1598 * / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP 1599 * with TS_ADC_DATA = temperature sensor raw data measured by ADC 1600 * Avg_Slope = (TS_CAL2 - TS_CAL1) 1601 * / (TS_CAL2_TEMP - TS_CAL1_TEMP) 1602 * TS_CAL1 = equivalent TS_ADC_DATA at temperature 1603 * TEMP_DEGC_CAL1 (calibrated in factory) 1604 * TS_CAL2 = equivalent TS_ADC_DATA at temperature 1605 * TEMP_DEGC_CAL2 (calibrated in factory) 1606 * Caution: Calculation relevancy under reserve that calibration 1607 * parameters are correct (address and data). 1608 * To calculate temperature using temperature sensor 1609 * datasheet typical values (generic values less, therefore 1610 * less accurate than calibrated values), 1611 * use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(). 1612 * @note As calculation input, the analog reference voltage (Vref+) must be 1613 * defined as it impacts the ADC LSB equivalent voltage. 1614 * @note Analog reference voltage (Vref+) must be either known from 1615 * user board environment or can be calculated using ADC measurement 1616 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). 1617 * @note On this STM32 series, calibration data of temperature sensor 1618 * corresponds to a resolution of 12 bits, 1619 * this is the recommended ADC resolution to convert voltage of 1620 * temperature sensor. 1621 * Otherwise, this macro performs the processing to scale 1622 * ADC conversion data to 12 bits. 1623 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV) 1624 * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal 1625 * temperature sensor (unit: digital value). 1626 * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature 1627 * sensor voltage has been measured. 1628 * This parameter can be one of the following values: 1629 * @arg @ref ADC_RESOLUTION_12B 1630 * @arg @ref ADC_RESOLUTION_10B 1631 * @arg @ref ADC_RESOLUTION_8B 1632 * @arg @ref ADC_RESOLUTION_6B 1633 * @retval Temperature (unit: degree Celsius) 1634 */ 1635 #define __HAL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\ 1636 __TEMPSENSOR_ADC_DATA__,\ 1637 __ADC_RESOLUTION__) \ 1638 __LL_ADC_CALC_TEMPERATURE((__VREFANALOG_VOLTAGE__),\ 1639 (__TEMPSENSOR_ADC_DATA__),\ 1640 (__ADC_RESOLUTION__)) 1641 1642 /** 1643 * @brief Helper macro to calculate the temperature (unit: degree Celsius) 1644 * from ADC conversion data of internal temperature sensor. 1645 * @note Computation is using temperature sensor typical values 1646 * (refer to device datasheet). 1647 * @note Calculation formula: 1648 * Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV) 1649 * / Avg_Slope + CALx_TEMP 1650 * with TS_ADC_DATA = temperature sensor raw data measured by ADC 1651 * (unit: digital value) 1652 * Avg_Slope = temperature sensor slope 1653 * (unit: uV/Degree Celsius) 1654 * TS_TYP_CALx_VOLT = temperature sensor digital value at 1655 * temperature CALx_TEMP (unit: mV) 1656 * Caution: Calculation relevancy under reserve the temperature sensor 1657 * of the current device has characteristics in line with 1658 * datasheet typical values. 1659 * If temperature sensor calibration values are available on 1660 * on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()), 1661 * temperature calculation will be more accurate using 1662 * helper macro @ref __LL_ADC_CALC_TEMPERATURE(). 1663 * @note As calculation input, the analog reference voltage (Vref+) must be 1664 * defined as it impacts the ADC LSB equivalent voltage. 1665 * @note Analog reference voltage (Vref+) must be either known from 1666 * user board environment or can be calculated using ADC measurement 1667 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). 1668 * @note ADC measurement data must correspond to a resolution of 12bits 1669 * (full scale digital value 4095). If not the case, the data must be 1670 * preliminarily rescaled to an equivalent resolution of 12 bits. 1671 * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature sensor slope typical value (unit: uV/DegCelsius). 1672 * On STM32L4, refer to device datasheet parameter "Avg_Slope". 1673 * @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data: Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit: mV). 1674 * On STM32L4, refer to device datasheet parameter "V30" (corresponding to TS_CAL1). 1675 * @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data: Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit: mV) 1676 * @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) voltage (unit: mV) 1677 * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit: digital value). 1678 * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured. 1679 * This parameter can be one of the following values: 1680 * @arg @ref ADC_RESOLUTION_12B 1681 * @arg @ref ADC_RESOLUTION_10B 1682 * @arg @ref ADC_RESOLUTION_8B 1683 * @arg @ref ADC_RESOLUTION_6B 1684 * @retval Temperature (unit: degree Celsius) 1685 */ 1686 #define __HAL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\ 1687 __TEMPSENSOR_TYP_CALX_V__,\ 1688 __TEMPSENSOR_CALX_TEMP__,\ 1689 __VREFANALOG_VOLTAGE__,\ 1690 __TEMPSENSOR_ADC_DATA__,\ 1691 __ADC_RESOLUTION__) \ 1692 __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS((__TEMPSENSOR_TYP_AVGSLOPE__),\ 1693 (__TEMPSENSOR_TYP_CALX_V__),\ 1694 (__TEMPSENSOR_CALX_TEMP__),\ 1695 (__VREFANALOG_VOLTAGE__),\ 1696 (__TEMPSENSOR_ADC_DATA__),\ 1697 (__ADC_RESOLUTION__)) 1698 1699 /** 1700 * @} 1701 */ 1702 1703 /** 1704 * @} 1705 */ 1706 1707 /* Include ADC HAL Extended module */ 1708 #include "stm32l4xx_hal_adc_ex.h" 1709 1710 /* Exported functions --------------------------------------------------------*/ 1711 /** @addtogroup ADC_Exported_Functions 1712 * @{ 1713 */ 1714 1715 /** @addtogroup ADC_Exported_Functions_Group1 1716 * @brief Initialization and Configuration functions 1717 * @{ 1718 */ 1719 /* Initialization and de-initialization functions ****************************/ 1720 HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc); 1721 HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc); 1722 void HAL_ADC_MspInit(ADC_HandleTypeDef *hadc); 1723 void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc); 1724 1725 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 1726 /* Callbacks Register/UnRegister functions ***********************************/ 1727 HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, 1728 pADC_CallbackTypeDef pCallback); 1729 HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID); 1730 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 1731 /** 1732 * @} 1733 */ 1734 1735 /** @addtogroup ADC_Exported_Functions_Group2 1736 * @brief IO operation functions 1737 * @{ 1738 */ 1739 /* IO operation functions *****************************************************/ 1740 1741 /* Blocking mode: Polling */ 1742 HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef *hadc); 1743 HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef *hadc); 1744 HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout); 1745 HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef *hadc, uint32_t EventType, uint32_t Timeout); 1746 1747 /* Non-blocking mode: Interruption */ 1748 HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef *hadc); 1749 HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef *hadc); 1750 1751 /* Non-blocking mode: DMA */ 1752 HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length); 1753 HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc); 1754 1755 /* ADC retrieve conversion value intended to be used with polling or interruption */ 1756 uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef *hadc); 1757 1758 /* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */ 1759 void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc); 1760 void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc); 1761 void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef *hadc); 1762 void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef *hadc); 1763 void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc); 1764 /** 1765 * @} 1766 */ 1767 1768 /** @addtogroup ADC_Exported_Functions_Group3 Peripheral Control functions 1769 * @brief Peripheral Control functions 1770 * @{ 1771 */ 1772 /* Peripheral Control functions ***********************************************/ 1773 HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *sConfig); 1774 HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDGConfTypeDef *AnalogWDGConfig); 1775 1776 /** 1777 * @} 1778 */ 1779 1780 /* Peripheral State functions *************************************************/ 1781 /** @addtogroup ADC_Exported_Functions_Group4 1782 * @{ 1783 */ 1784 uint32_t HAL_ADC_GetState(ADC_HandleTypeDef *hadc); 1785 uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc); 1786 1787 /** 1788 * @} 1789 */ 1790 1791 /** 1792 * @} 1793 */ 1794 1795 /* Private functions -----------------------------------------------------------*/ 1796 /** @addtogroup ADC_Private_Functions ADC Private Functions 1797 * @{ 1798 */ 1799 HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef *hadc, uint32_t ConversionGroup); 1800 HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc); 1801 HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef *hadc); 1802 void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma); 1803 void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma); 1804 void ADC_DMAError(DMA_HandleTypeDef *hdma); 1805 1806 /** 1807 * @} 1808 */ 1809 1810 /** 1811 * @} 1812 */ 1813 1814 /** 1815 * @} 1816 */ 1817 1818 #ifdef __cplusplus 1819 } 1820 #endif 1821 1822 1823 #endif /* STM32L4xx_HAL_ADC_H */ 1824
