1 /**
2 ******************************************************************************
3 * @file stm32l0xx_ll_utils.h
4 * @author MCD Application Team
5 * @brief Header file of UTILS LL module.
6 @verbatim
7 ==============================================================================
8 ##### How to use this driver #####
9 ==============================================================================
10 [..]
11 The LL UTILS driver contains a set of generic APIs that can be
12 used by user:
13 (+) Device electronic signature
14 (+) Timing functions
15 (+) PLL configuration functions
16
17 @endverbatim
18 ******************************************************************************
19 * @attention
20 *
21 * Copyright (c) 2016 STMicroelectronics.
22 * All rights reserved.
23 *
24 * This software is licensed under terms that can be found in the LICENSE file
25 * in the root directory of this software component.
26 * If no LICENSE file comes with this software, it is provided AS-IS.
27 *
28 ******************************************************************************
29 */
30
31 /* Define to prevent recursive inclusion -------------------------------------*/
32 #ifndef __STM32L0xx_LL_UTILS_H
33 #define __STM32L0xx_LL_UTILS_H
34
35 #ifdef __cplusplus
36 extern "C" {
37 #endif
38
39 /* Includes ------------------------------------------------------------------*/
40 #include "stm32l0xx.h"
41
42 /** @addtogroup STM32L0xx_LL_Driver
43 * @{
44 */
45
46 /** @defgroup UTILS_LL UTILS
47 * @{
48 */
49
50 /* Private types -------------------------------------------------------------*/
51 /* Private variables ---------------------------------------------------------*/
52
53 /* Private constants ---------------------------------------------------------*/
54 /** @defgroup UTILS_LL_Private_Constants UTILS Private Constants
55 * @{
56 */
57
58 /* Max delay can be used in LL_mDelay */
59 #define LL_MAX_DELAY 0xFFFFFFFFU
60
61 /**
62 * @brief Unique device ID register base address
63 */
64 #define UID_BASE_ADDRESS UID_BASE
65
66 /**
67 * @brief Flash size data register base address
68 */
69 #define FLASHSIZE_BASE_ADDRESS FLASHSIZE_BASE
70
71
72 /**
73 * @}
74 */
75
76 /* Private macros ------------------------------------------------------------*/
77 /** @defgroup UTILS_LL_Private_Macros UTILS Private Macros
78 * @{
79 */
80 /**
81 * @}
82 */
83 /* Exported types ------------------------------------------------------------*/
84 /** @defgroup UTILS_LL_ES_INIT UTILS Exported structures
85 * @{
86 */
87 /**
88 * @brief UTILS PLL structure definition
89 */
90 typedef struct
91 {
92 uint32_t PLLMul; /*!< Multiplication factor for PLL VCO input clock.
93 This parameter can be a value of @ref RCC_LL_EC_PLL_MUL
94
95 This feature can be modified afterwards using unitary function
96 @ref LL_RCC_PLL_ConfigDomain_SYS(). */
97
98 uint32_t PLLDiv; /*!< Division factor for PLL VCO output clock.
99 This parameter can be a value of @ref RCC_LL_EC_PLL_DIV
100
101 This feature can be modified afterwards using unitary function
102 @ref LL_RCC_PLL_ConfigDomain_SYS(). */
103 } LL_UTILS_PLLInitTypeDef;
104
105 /**
106 * @brief UTILS System, AHB and APB buses clock configuration structure definition
107 */
108 typedef struct
109 {
110 uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
111 This parameter can be a value of @ref RCC_LL_EC_SYSCLK_DIV
112
113 This feature can be modified afterwards using unitary function
114 @ref LL_RCC_SetAHBPrescaler(). */
115
116 uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
117 This parameter can be a value of @ref RCC_LL_EC_APB1_DIV
118
119 This feature can be modified afterwards using unitary function
120 @ref LL_RCC_SetAPB1Prescaler(). */
121
122 uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
123 This parameter can be a value of @ref RCC_LL_EC_APB2_DIV
124
125 This feature can be modified afterwards using unitary function
126 @ref LL_RCC_SetAPB2Prescaler(). */
127
128 } LL_UTILS_ClkInitTypeDef;
129
130 /**
131 * @}
132 */
133
134 /* Exported constants --------------------------------------------------------*/
135 /** @defgroup UTILS_LL_Exported_Constants UTILS Exported Constants
136 * @{
137 */
138
139 /** @defgroup UTILS_EC_HSE_BYPASS HSE Bypass activation
140 * @{
141 */
142 #define LL_UTILS_HSEBYPASS_OFF 0x00000000U /*!< HSE Bypass is not enabled */
143 #define LL_UTILS_HSEBYPASS_ON 0x00000001U /*!< HSE Bypass is enabled */
144 /**
145 * @}
146 */
147
148
149 /**
150 * @}
151 */
152
153 /* Exported macro ------------------------------------------------------------*/
154
155 /* Exported functions --------------------------------------------------------*/
156 /** @defgroup UTILS_LL_Exported_Functions UTILS Exported Functions
157 * @{
158 */
159
160 /** @defgroup UTILS_EF_DEVICE_ELECTRONIC_SIGNATURE DEVICE ELECTRONIC SIGNATURE
161 * @{
162 */
163
164 /**
165 * @brief Get Word0 of the unique device identifier (UID based on 96 bits)
166 * @retval UID[31:0]
167 */
LL_GetUID_Word0(void)168 __STATIC_INLINE uint32_t LL_GetUID_Word0(void)
169 {
170 return (uint32_t)(READ_REG(*((uint32_t *)UID_BASE_ADDRESS)));
171 }
172
173 /**
174 * @brief Get Word1 of the unique device identifier (UID based on 96 bits)
175 * @retval UID[63:32]
176 */
LL_GetUID_Word1(void)177 __STATIC_INLINE uint32_t LL_GetUID_Word1(void)
178 {
179 return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 0x04U))));
180 }
181
182 /**
183 * @brief Get Word2 of the unique device identifier (UID based on 96 bits)
184 * @retval UID[95:64]
185 */
LL_GetUID_Word2(void)186 __STATIC_INLINE uint32_t LL_GetUID_Word2(void)
187 {
188 return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 0x14U))));
189 }
190
191 /**
192 * @brief Get Flash memory size
193 * @note This bitfield indicates the size of the device Flash memory expressed in
194 * Kbytes. As an example, 0x040 corresponds to 64 Kbytes.
195 * @retval FLASH_SIZE[15:0]: Flash memory size
196 */
LL_GetFlashSize(void)197 __STATIC_INLINE uint32_t LL_GetFlashSize(void)
198 {
199 return (uint32_t)(READ_REG(*((uint32_t *)FLASHSIZE_BASE_ADDRESS)) & 0xFFFF);
200 }
201
202
203 /**
204 * @}
205 */
206
207 /** @defgroup UTILS_LL_EF_DELAY DELAY
208 * @{
209 */
210
211 /**
212 * @brief This function configures the Cortex-M SysTick source of the time base.
213 * @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
214 * @note When a RTOS is used, it is recommended to avoid changing the SysTick
215 * configuration by calling this function, for a delay use rather osDelay RTOS service.
216 * @param Ticks Number of ticks
217 * @retval None
218 */
LL_InitTick(uint32_t HCLKFrequency,uint32_t Ticks)219 __STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks)
220 {
221 /* Configure the SysTick to have interrupt in 1ms time base */
222 SysTick->LOAD = (uint32_t)((HCLKFrequency / Ticks) - 1UL); /* set reload register */
223 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
224 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
225 SysTick_CTRL_ENABLE_Msk; /* Enable the Systick Timer */
226 }
227
228 void LL_Init1msTick(uint32_t HCLKFrequency);
229 void LL_mDelay(uint32_t Delay);
230
231 /**
232 * @}
233 */
234
235 /** @defgroup UTILS_EF_SYSTEM SYSTEM
236 * @{
237 */
238
239 void LL_SetSystemCoreClock(uint32_t HCLKFrequency);
240 ErrorStatus LL_SetFlashLatency(uint32_t HCLKFrequency);
241 ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
242 LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
243 ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass,
244 LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
245 ErrorStatus LL_SetFlashLatency(uint32_t Frequency);
246
247 /**
248 * @}
249 */
250
251 /**
252 * @}
253 */
254
255 /**
256 * @}
257 */
258
259 /**
260 * @}
261 */
262
263 #ifdef __cplusplus
264 }
265 #endif
266
267 #endif /* __STM32L0xx_LL_UTILS_H */
268
