1 /**
2 ******************************************************************************
3 * @file stm32h7xx_hal_sdram.c
4 * @author MCD Application Team
5 * @brief SDRAM HAL module driver.
6 * This file provides a generic firmware to drive SDRAM memories mounted
7 * as external device.
8 *
9 ******************************************************************************
10 * @attention
11 *
12 * Copyright (c) 2017 STMicroelectronics.
13 * All rights reserved.
14 *
15 * This software is licensed under terms that can be found in the LICENSE file
16 * in the root directory of this software component.
17 * If no LICENSE file comes with this software, it is provided AS-IS.
18 *
19 ******************************************************************************
20 @verbatim
21 ==============================================================================
22 ##### How to use this driver #####
23 ==============================================================================
24 [..]
25 This driver is a generic layered driver which contains a set of APIs used to
26 control SDRAM memories. It uses the FMC layer functions to interface
27 with SDRAM devices.
28 The following sequence should be followed to configure the FMC to interface
29 with SDRAM memories:
30
31 (#) Declare a SDRAM_HandleTypeDef handle structure, for example:
32 SDRAM_HandleTypeDef hsdram
33
34 (++) Fill the SDRAM_HandleTypeDef handle "Init" field with the allowed
35 values of the structure member.
36
37 (++) Fill the SDRAM_HandleTypeDef handle "Instance" field with a predefined
38 base register instance for NOR or SDRAM device
39
40 (#) Declare a FMC_SDRAM_TimingTypeDef structure; for example:
41 FMC_SDRAM_TimingTypeDef Timing;
42 and fill its fields with the allowed values of the structure member.
43
44 (#) Initialize the SDRAM Controller by calling the function HAL_SDRAM_Init(). This function
45 performs the following sequence:
46
47 (##) MSP hardware layer configuration using the function HAL_SDRAM_MspInit()
48 (##) Control register configuration using the FMC SDRAM interface function
49 FMC_SDRAM_Init()
50 (##) Timing register configuration using the FMC SDRAM interface function
51 FMC_SDRAM_Timing_Init()
52 (##) Program the SDRAM external device by applying its initialization sequence
53 according to the device plugged in your hardware. This step is mandatory
54 for accessing the SDRAM device.
55
56 (#) At this stage you can perform read/write accesses from/to the memory connected
57 to the SDRAM Bank. You can perform either polling or DMA transfer using the
58 following APIs:
59 (++) HAL_SDRAM_Read()/HAL_SDRAM_Write() for polling read/write access
60 (++) HAL_SDRAM_Read_DMA()/HAL_SDRAM_Write_DMA() for DMA read/write transfer
61
62 (#) You can also control the SDRAM device by calling the control APIs HAL_SDRAM_WriteOperation_Enable()/
63 HAL_SDRAM_WriteOperation_Disable() to respectively enable/disable the SDRAM write operation or
64 the function HAL_SDRAM_SendCommand() to send a specified command to the SDRAM
65 device. The command to be sent must be configured with the FMC_SDRAM_CommandTypeDef
66 structure.
67
68 (#) You can continuously monitor the SDRAM device HAL state by calling the function
69 HAL_SDRAM_GetState()
70
71 *** Callback registration ***
72 =============================================
73 [..]
74 The compilation define USE_HAL_SDRAM_REGISTER_CALLBACKS when set to 1
75 allows the user to configure dynamically the driver callbacks.
76
77 Use Functions HAL_SDRAM_RegisterCallback() to register a user callback,
78 it allows to register following callbacks:
79 (+) MspInitCallback : SDRAM MspInit.
80 (+) MspDeInitCallback : SDRAM MspDeInit.
81 This function takes as parameters the HAL peripheral handle, the Callback ID
82 and a pointer to the user callback function.
83
84 Use function HAL_SDRAM_UnRegisterCallback() to reset a callback to the default
85 weak (surcharged) function. It allows to reset following callbacks:
86 (+) MspInitCallback : SDRAM MspInit.
87 (+) MspDeInitCallback : SDRAM MspDeInit.
88 This function) takes as parameters the HAL peripheral handle and the Callback ID.
89
90 By default, after the HAL_SDRAM_Init and if the state is HAL_SDRAM_STATE_RESET
91 all callbacks are reset to the corresponding legacy weak (surcharged) functions.
92 Exception done for MspInit and MspDeInit callbacks that are respectively
93 reset to the legacy weak (surcharged) functions in the HAL_SDRAM_Init
94 and HAL_SDRAM_DeInit only when these callbacks are null (not registered beforehand).
95 If not, MspInit or MspDeInit are not null, the HAL_SDRAM_Init and HAL_SDRAM_DeInit
96 keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
97
98 Callbacks can be registered/unregistered in READY state only.
99 Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
100 in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
101 during the Init/DeInit.
102 In that case first register the MspInit/MspDeInit user callbacks
103 using HAL_SDRAM_RegisterCallback before calling HAL_SDRAM_DeInit
104 or HAL_SDRAM_Init function.
105
106 When The compilation define USE_HAL_SDRAM_REGISTER_CALLBACKS is set to 0 or
107 not defined, the callback registering feature is not available
108 and weak (surcharged) callbacks are used.
109
110 @endverbatim
111 ******************************************************************************
112 */
113
114 /* Includes ------------------------------------------------------------------*/
115 #include "stm32h7xx_hal.h"
116
117
118 /** @addtogroup STM32H7xx_HAL_Driver
119 * @{
120 */
121
122 #ifdef HAL_SDRAM_MODULE_ENABLED
123
124 /** @defgroup SDRAM SDRAM
125 * @brief SDRAM driver modules
126 * @{
127 */
128
129 /* Private typedef -----------------------------------------------------------*/
130 /* Private define ------------------------------------------------------------*/
131 /* Private macro -------------------------------------------------------------*/
132 /* Private variables ---------------------------------------------------------*/
133 /* Private function prototypes -----------------------------------------------*/
134 /** @addtogroup SDRAM_Private_Functions SDRAM Private Functions
135 * @{
136 */
137 static void SDRAM_DMACplt(MDMA_HandleTypeDef *hmdma);
138 static void SDRAM_DMACpltProt(MDMA_HandleTypeDef *hmdma);
139 static void SDRAM_DMAError(MDMA_HandleTypeDef *hmdma);
140 /**
141 * @}
142 */
143
144 /* Exported functions --------------------------------------------------------*/
145 /** @defgroup SDRAM_Exported_Functions SDRAM Exported Functions
146 * @{
147 */
148
149 /** @defgroup SDRAM_Exported_Functions_Group1 Initialization and de-initialization functions
150 * @brief Initialization and Configuration functions
151 *
152 @verbatim
153 ==============================================================================
154 ##### SDRAM Initialization and de_initialization functions #####
155 ==============================================================================
156 [..]
157 This section provides functions allowing to initialize/de-initialize
158 the SDRAM memory
159
160 @endverbatim
161 * @{
162 */
163
164 /**
165 * @brief Performs the SDRAM device initialization sequence.
166 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
167 * the configuration information for SDRAM module.
168 * @param Timing Pointer to SDRAM control timing structure
169 * @retval HAL status
170 */
HAL_SDRAM_Init(SDRAM_HandleTypeDef * hsdram,FMC_SDRAM_TimingTypeDef * Timing)171 HAL_StatusTypeDef HAL_SDRAM_Init(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTypeDef *Timing)
172 {
173 /* Check the SDRAM handle parameter */
174 if (hsdram == NULL)
175 {
176 return HAL_ERROR;
177 }
178
179 if (hsdram->State == HAL_SDRAM_STATE_RESET)
180 {
181 /* Allocate lock resource and initialize it */
182 hsdram->Lock = HAL_UNLOCKED;
183 #if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
184 if (hsdram->MspInitCallback == NULL)
185 {
186 hsdram->MspInitCallback = HAL_SDRAM_MspInit;
187 }
188 hsdram->RefreshErrorCallback = HAL_SDRAM_RefreshErrorCallback;
189 hsdram->DmaXferCpltCallback = HAL_SDRAM_DMA_XferCpltCallback;
190 hsdram->DmaXferErrorCallback = HAL_SDRAM_DMA_XferErrorCallback;
191
192 /* Init the low level hardware */
193 hsdram->MspInitCallback(hsdram);
194 #else
195 /* Initialize the low level hardware (MSP) */
196 HAL_SDRAM_MspInit(hsdram);
197 #endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */
198 }
199
200 /* Initialize the SDRAM controller state */
201 hsdram->State = HAL_SDRAM_STATE_BUSY;
202
203 /* Initialize SDRAM control Interface */
204 (void)FMC_SDRAM_Init(hsdram->Instance, &(hsdram->Init));
205
206 /* Initialize SDRAM timing Interface */
207 (void)FMC_SDRAM_Timing_Init(hsdram->Instance, Timing, hsdram->Init.SDBank);
208
209 /* Enable FMC Peripheral */
210 __FMC_ENABLE();
211 /* Update the SDRAM controller state */
212 hsdram->State = HAL_SDRAM_STATE_READY;
213
214 return HAL_OK;
215 }
216
217 /**
218 * @brief Perform the SDRAM device initialization sequence.
219 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
220 * the configuration information for SDRAM module.
221 * @retval HAL status
222 */
HAL_SDRAM_DeInit(SDRAM_HandleTypeDef * hsdram)223 HAL_StatusTypeDef HAL_SDRAM_DeInit(SDRAM_HandleTypeDef *hsdram)
224 {
225 #if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
226 if (hsdram->MspDeInitCallback == NULL)
227 {
228 hsdram->MspDeInitCallback = HAL_SDRAM_MspDeInit;
229 }
230
231 /* DeInit the low level hardware */
232 hsdram->MspDeInitCallback(hsdram);
233 #else
234 /* Initialize the low level hardware (MSP) */
235 HAL_SDRAM_MspDeInit(hsdram);
236 #endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */
237
238 /* Configure the SDRAM registers with their reset values */
239 (void)FMC_SDRAM_DeInit(hsdram->Instance, hsdram->Init.SDBank);
240
241 /* Reset the SDRAM controller state */
242 hsdram->State = HAL_SDRAM_STATE_RESET;
243
244 /* Release Lock */
245 __HAL_UNLOCK(hsdram);
246
247 return HAL_OK;
248 }
249
250 /**
251 * @brief SDRAM MSP Init.
252 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
253 * the configuration information for SDRAM module.
254 * @retval None
255 */
HAL_SDRAM_MspInit(SDRAM_HandleTypeDef * hsdram)256 __weak void HAL_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram)
257 {
258 /* Prevent unused argument(s) compilation warning */
259 UNUSED(hsdram);
260
261 /* NOTE: This function Should not be modified, when the callback is needed,
262 the HAL_SDRAM_MspInit could be implemented in the user file
263 */
264 }
265
266 /**
267 * @brief SDRAM MSP DeInit.
268 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
269 * the configuration information for SDRAM module.
270 * @retval None
271 */
HAL_SDRAM_MspDeInit(SDRAM_HandleTypeDef * hsdram)272 __weak void HAL_SDRAM_MspDeInit(SDRAM_HandleTypeDef *hsdram)
273 {
274 /* Prevent unused argument(s) compilation warning */
275 UNUSED(hsdram);
276
277 /* NOTE: This function Should not be modified, when the callback is needed,
278 the HAL_SDRAM_MspDeInit could be implemented in the user file
279 */
280 }
281
282 /**
283 * @brief This function handles SDRAM refresh error interrupt request.
284 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
285 * the configuration information for SDRAM module.
286 * @retval HAL status
287 */
HAL_SDRAM_IRQHandler(SDRAM_HandleTypeDef * hsdram)288 void HAL_SDRAM_IRQHandler(SDRAM_HandleTypeDef *hsdram)
289 {
290 /* Check SDRAM interrupt Rising edge flag */
291 if (__FMC_SDRAM_GET_FLAG(hsdram->Instance, FMC_SDRAM_FLAG_REFRESH_IT))
292 {
293 /* SDRAM refresh error interrupt callback */
294 #if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
295 hsdram->RefreshErrorCallback(hsdram);
296 #else
297 HAL_SDRAM_RefreshErrorCallback(hsdram);
298 #endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */
299
300 /* Clear SDRAM refresh error interrupt pending bit */
301 __FMC_SDRAM_CLEAR_FLAG(hsdram->Instance, FMC_SDRAM_FLAG_REFRESH_ERROR);
302 }
303 }
304
305 /**
306 * @brief SDRAM Refresh error callback.
307 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
308 * the configuration information for SDRAM module.
309 * @retval None
310 */
HAL_SDRAM_RefreshErrorCallback(SDRAM_HandleTypeDef * hsdram)311 __weak void HAL_SDRAM_RefreshErrorCallback(SDRAM_HandleTypeDef *hsdram)
312 {
313 /* Prevent unused argument(s) compilation warning */
314 UNUSED(hsdram);
315
316 /* NOTE: This function Should not be modified, when the callback is needed,
317 the HAL_SDRAM_RefreshErrorCallback could be implemented in the user file
318 */
319 }
320
321 /**
322 * @brief DMA transfer complete callback.
323 * @param hmdma pointer to a DMA_HandleTypeDef structure that contains
324 * the configuration information for the specified DMA module.
325 * @retval None
326 */
HAL_SDRAM_DMA_XferCpltCallback(MDMA_HandleTypeDef * hmdma)327 __weak void HAL_SDRAM_DMA_XferCpltCallback(MDMA_HandleTypeDef *hmdma)
328 {
329 /* Prevent unused argument(s) compilation warning */
330 UNUSED(hmdma);
331
332 /* NOTE: This function Should not be modified, when the callback is needed,
333 the HAL_SDRAM_DMA_XferCpltCallback could be implemented in the user file
334 */
335 }
336
337 /**
338 * @brief DMA transfer complete error callback.
339 * @param hmdma DMA handle
340 * @retval None
341 */
HAL_SDRAM_DMA_XferErrorCallback(MDMA_HandleTypeDef * hmdma)342 __weak void HAL_SDRAM_DMA_XferErrorCallback(MDMA_HandleTypeDef *hmdma)
343 {
344 /* Prevent unused argument(s) compilation warning */
345 UNUSED(hmdma);
346
347 /* NOTE: This function Should not be modified, when the callback is needed,
348 the HAL_SDRAM_DMA_XferErrorCallback could be implemented in the user file
349 */
350 }
351
352 /**
353 * @}
354 */
355
356 /** @defgroup SDRAM_Exported_Functions_Group2 Input and Output functions
357 * @brief Input Output and memory control functions
358 *
359 @verbatim
360 ==============================================================================
361 ##### SDRAM Input and Output functions #####
362 ==============================================================================
363 [..]
364 This section provides functions allowing to use and control the SDRAM memory
365
366 @endverbatim
367 * @{
368 */
369
370 /**
371 * @brief Reads 8-bit data buffer from the SDRAM memory.
372 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
373 * the configuration information for SDRAM module.
374 * @param pAddress Pointer to read start address
375 * @param pDstBuffer Pointer to destination buffer
376 * @param BufferSize Size of the buffer to read from memory
377 * @retval HAL status
378 */
HAL_SDRAM_Read_8b(SDRAM_HandleTypeDef * hsdram,uint32_t * pAddress,uint8_t * pDstBuffer,uint32_t BufferSize)379 HAL_StatusTypeDef HAL_SDRAM_Read_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pDstBuffer,
380 uint32_t BufferSize)
381 {
382 uint32_t size;
383 __IO uint8_t *pSdramAddress = (uint8_t *)pAddress;
384 uint8_t *pdestbuff = pDstBuffer;
385 HAL_SDRAM_StateTypeDef state = hsdram->State;
386
387 /* Check the SDRAM controller state */
388 if (state == HAL_SDRAM_STATE_BUSY)
389 {
390 return HAL_BUSY;
391 }
392 else if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED))
393 {
394 /* Process Locked */
395 __HAL_LOCK(hsdram);
396
397 /* Update the SDRAM controller state */
398 hsdram->State = HAL_SDRAM_STATE_BUSY;
399
400 /* Read data from source */
401 for (size = BufferSize; size != 0U; size--)
402 {
403 *pdestbuff = *(__IO uint8_t *)pSdramAddress;
404 pdestbuff++;
405 pSdramAddress++;
406 }
407
408 /* Update the SDRAM controller state */
409 hsdram->State = state;
410
411 /* Process Unlocked */
412 __HAL_UNLOCK(hsdram);
413 }
414 else
415 {
416 return HAL_ERROR;
417 }
418
419 return HAL_OK;
420 }
421
422 /**
423 * @brief Writes 8-bit data buffer to SDRAM memory.
424 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
425 * the configuration information for SDRAM module.
426 * @param pAddress Pointer to write start address
427 * @param pSrcBuffer Pointer to source buffer to write
428 * @param BufferSize Size of the buffer to write to memory
429 * @retval HAL status
430 */
HAL_SDRAM_Write_8b(SDRAM_HandleTypeDef * hsdram,uint32_t * pAddress,uint8_t * pSrcBuffer,uint32_t BufferSize)431 HAL_StatusTypeDef HAL_SDRAM_Write_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pSrcBuffer,
432 uint32_t BufferSize)
433 {
434 uint32_t size;
435 __IO uint8_t *pSdramAddress = (uint8_t *)pAddress;
436 uint8_t *psrcbuff = pSrcBuffer;
437
438 /* Check the SDRAM controller state */
439 if (hsdram->State == HAL_SDRAM_STATE_BUSY)
440 {
441 return HAL_BUSY;
442 }
443 else if (hsdram->State == HAL_SDRAM_STATE_READY)
444 {
445 /* Process Locked */
446 __HAL_LOCK(hsdram);
447
448 /* Update the SDRAM controller state */
449 hsdram->State = HAL_SDRAM_STATE_BUSY;
450
451 /* Write data to memory */
452 for (size = BufferSize; size != 0U; size--)
453 {
454 *(__IO uint8_t *)pSdramAddress = *psrcbuff;
455 psrcbuff++;
456 pSdramAddress++;
457 }
458
459 /* Update the SDRAM controller state */
460 hsdram->State = HAL_SDRAM_STATE_READY;
461
462 /* Process Unlocked */
463 __HAL_UNLOCK(hsdram);
464 }
465 else
466 {
467 return HAL_ERROR;
468 }
469
470 return HAL_OK;
471 }
472
473 /**
474 * @brief Reads 16-bit data buffer from the SDRAM memory.
475 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
476 * the configuration information for SDRAM module.
477 * @param pAddress Pointer to read start address
478 * @param pDstBuffer Pointer to destination buffer
479 * @param BufferSize Size of the buffer to read from memory
480 * @retval HAL status
481 */
HAL_SDRAM_Read_16b(SDRAM_HandleTypeDef * hsdram,uint32_t * pAddress,uint16_t * pDstBuffer,uint32_t BufferSize)482 HAL_StatusTypeDef HAL_SDRAM_Read_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pDstBuffer,
483 uint32_t BufferSize)
484 {
485 uint32_t size;
486 __IO uint32_t *pSdramAddress = pAddress;
487 uint16_t *pdestbuff = pDstBuffer;
488 HAL_SDRAM_StateTypeDef state = hsdram->State;
489
490 /* Check the SDRAM controller state */
491 if (state == HAL_SDRAM_STATE_BUSY)
492 {
493 return HAL_BUSY;
494 }
495 else if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED))
496 {
497 /* Process Locked */
498 __HAL_LOCK(hsdram);
499
500 /* Update the SDRAM controller state */
501 hsdram->State = HAL_SDRAM_STATE_BUSY;
502
503 /* Read data from memory */
504 for (size = BufferSize; size >= 2U ; size -= 2U)
505 {
506 *pdestbuff = (uint16_t)((*pSdramAddress) & 0x0000FFFFU);
507 pdestbuff++;
508 *pdestbuff = (uint16_t)(((*pSdramAddress) & 0xFFFF0000U) >> 16U);
509 pdestbuff++;
510 pSdramAddress++;
511 }
512
513 /* Read last 16-bits if size is not 32-bits multiple */
514 if ((BufferSize % 2U) != 0U)
515 {
516 *pdestbuff = (uint16_t)((*pSdramAddress) & 0x0000FFFFU);
517 }
518
519 /* Update the SDRAM controller state */
520 hsdram->State = state;
521
522 /* Process Unlocked */
523 __HAL_UNLOCK(hsdram);
524 }
525 else
526 {
527 return HAL_ERROR;
528 }
529
530 return HAL_OK;
531 }
532
533 /**
534 * @brief Writes 16-bit data buffer to SDRAM memory.
535 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
536 * the configuration information for SDRAM module.
537 * @param pAddress Pointer to write start address
538 * @param pSrcBuffer Pointer to source buffer to write
539 * @param BufferSize Size of the buffer to write to memory
540 * @retval HAL status
541 */
HAL_SDRAM_Write_16b(SDRAM_HandleTypeDef * hsdram,uint32_t * pAddress,uint16_t * pSrcBuffer,uint32_t BufferSize)542 HAL_StatusTypeDef HAL_SDRAM_Write_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pSrcBuffer,
543 uint32_t BufferSize)
544 {
545 uint32_t size;
546 __IO uint32_t *psdramaddress = pAddress;
547 uint16_t *psrcbuff = pSrcBuffer;
548
549 /* Check the SDRAM controller state */
550 if (hsdram->State == HAL_SDRAM_STATE_BUSY)
551 {
552 return HAL_BUSY;
553 }
554 else if (hsdram->State == HAL_SDRAM_STATE_READY)
555 {
556 /* Process Locked */
557 __HAL_LOCK(hsdram);
558
559 /* Update the SDRAM controller state */
560 hsdram->State = HAL_SDRAM_STATE_BUSY;
561
562 /* Write data to memory */
563 for (size = BufferSize; size >= 2U ; size -= 2U)
564 {
565 *psdramaddress = (uint32_t)(*psrcbuff);
566 psrcbuff++;
567 *psdramaddress |= ((uint32_t)(*psrcbuff) << 16U);
568 psrcbuff++;
569 psdramaddress++;
570 }
571
572 /* Write last 16-bits if size is not 32-bits multiple */
573 if ((BufferSize % 2U) != 0U)
574 {
575 *psdramaddress = ((uint32_t)(*psrcbuff) & 0x0000FFFFU) | ((*psdramaddress) & 0xFFFF0000U);
576 }
577
578 /* Update the SDRAM controller state */
579 hsdram->State = HAL_SDRAM_STATE_READY;
580
581 /* Process Unlocked */
582 __HAL_UNLOCK(hsdram);
583 }
584 else
585 {
586 return HAL_ERROR;
587 }
588
589 return HAL_OK;
590 }
591
592 /**
593 * @brief Reads 32-bit data buffer from the SDRAM memory.
594 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
595 * the configuration information for SDRAM module.
596 * @param pAddress Pointer to read start address
597 * @param pDstBuffer Pointer to destination buffer
598 * @param BufferSize Size of the buffer to read from memory
599 * @retval HAL status
600 */
HAL_SDRAM_Read_32b(SDRAM_HandleTypeDef * hsdram,uint32_t * pAddress,uint32_t * pDstBuffer,uint32_t BufferSize)601 HAL_StatusTypeDef HAL_SDRAM_Read_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer,
602 uint32_t BufferSize)
603 {
604 uint32_t size;
605 __IO uint32_t *pSdramAddress = (uint32_t *)pAddress;
606 uint32_t *pdestbuff = pDstBuffer;
607 HAL_SDRAM_StateTypeDef state = hsdram->State;
608
609 /* Check the SDRAM controller state */
610 if (state == HAL_SDRAM_STATE_BUSY)
611 {
612 return HAL_BUSY;
613 }
614 else if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED))
615 {
616 /* Process Locked */
617 __HAL_LOCK(hsdram);
618
619 /* Update the SDRAM controller state */
620 hsdram->State = HAL_SDRAM_STATE_BUSY;
621
622 /* Read data from source */
623 for (size = BufferSize; size != 0U; size--)
624 {
625 *pdestbuff = *(__IO uint32_t *)pSdramAddress;
626 pdestbuff++;
627 pSdramAddress++;
628 }
629
630 /* Update the SDRAM controller state */
631 hsdram->State = state;
632
633 /* Process Unlocked */
634 __HAL_UNLOCK(hsdram);
635 }
636 else
637 {
638 return HAL_ERROR;
639 }
640
641 return HAL_OK;
642 }
643
644 /**
645 * @brief Writes 32-bit data buffer to SDRAM memory.
646 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
647 * the configuration information for SDRAM module.
648 * @param pAddress Pointer to write start address
649 * @param pSrcBuffer Pointer to source buffer to write
650 * @param BufferSize Size of the buffer to write to memory
651 * @retval HAL status
652 */
HAL_SDRAM_Write_32b(SDRAM_HandleTypeDef * hsdram,uint32_t * pAddress,uint32_t * pSrcBuffer,uint32_t BufferSize)653 HAL_StatusTypeDef HAL_SDRAM_Write_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer,
654 uint32_t BufferSize)
655 {
656 uint32_t size;
657 __IO uint32_t *pSdramAddress = pAddress;
658 uint32_t *psrcbuff = pSrcBuffer;
659
660 /* Check the SDRAM controller state */
661 if (hsdram->State == HAL_SDRAM_STATE_BUSY)
662 {
663 return HAL_BUSY;
664 }
665 else if (hsdram->State == HAL_SDRAM_STATE_READY)
666 {
667 /* Process Locked */
668 __HAL_LOCK(hsdram);
669
670 /* Update the SDRAM controller state */
671 hsdram->State = HAL_SDRAM_STATE_BUSY;
672
673 /* Write data to memory */
674 for (size = BufferSize; size != 0U; size--)
675 {
676 *pSdramAddress = *psrcbuff;
677 psrcbuff++;
678 pSdramAddress++;
679 }
680
681 /* Update the SDRAM controller state */
682 hsdram->State = HAL_SDRAM_STATE_READY;
683
684 /* Process Unlocked */
685 __HAL_UNLOCK(hsdram);
686 }
687 else
688 {
689 return HAL_ERROR;
690 }
691
692 return HAL_OK;
693 }
694
695 /**
696 * @brief Reads a Words data from the SDRAM memory using DMA transfer.
697 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
698 * the configuration information for SDRAM module.
699 * @param pAddress Pointer to read start address
700 * @param pDstBuffer Pointer to destination buffer
701 * @param BufferSize Size of the buffer to read from memory
702 * @retval HAL status
703 */
HAL_SDRAM_Read_DMA(SDRAM_HandleTypeDef * hsdram,uint32_t * pAddress,uint32_t * pDstBuffer,uint32_t BufferSize)704 HAL_StatusTypeDef HAL_SDRAM_Read_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer,
705 uint32_t BufferSize)
706 {
707 HAL_StatusTypeDef status;
708 HAL_SDRAM_StateTypeDef state = hsdram->State;
709
710 /* Check the SDRAM controller state */
711 if (state == HAL_SDRAM_STATE_BUSY)
712 {
713 status = HAL_BUSY;
714 }
715 else if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED))
716 {
717 /* Process Locked */
718 __HAL_LOCK(hsdram);
719
720 /* Update the SDRAM controller state */
721 hsdram->State = HAL_SDRAM_STATE_BUSY;
722
723 /* Configure DMA user callbacks */
724 if (state == HAL_SDRAM_STATE_READY)
725 {
726 hsdram->hmdma->XferCpltCallback = SDRAM_DMACplt;
727 }
728 else
729 {
730 hsdram->hmdma->XferCpltCallback = SDRAM_DMACpltProt;
731 }
732 hsdram->hmdma->XferErrorCallback = SDRAM_DMAError;
733
734 /* Enable the DMA Stream */
735 status = HAL_MDMA_Start_IT(hsdram->hmdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, (uint32_t)(BufferSize * 4U), 1);
736
737 /* Process Unlocked */
738 __HAL_UNLOCK(hsdram);
739 }
740 else
741 {
742 status = HAL_ERROR;
743 }
744
745 return status;
746 }
747
748 /**
749 * @brief Writes a Words data buffer to SDRAM memory using DMA transfer.
750 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
751 * the configuration information for SDRAM module.
752 * @param pAddress Pointer to write start address
753 * @param pSrcBuffer Pointer to source buffer to write
754 * @param BufferSize Size of the buffer to write to memory
755 * @retval HAL status
756 */
HAL_SDRAM_Write_DMA(SDRAM_HandleTypeDef * hsdram,uint32_t * pAddress,uint32_t * pSrcBuffer,uint32_t BufferSize)757 HAL_StatusTypeDef HAL_SDRAM_Write_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer,
758 uint32_t BufferSize)
759 {
760 HAL_StatusTypeDef status;
761
762 /* Check the SDRAM controller state */
763 if (hsdram->State == HAL_SDRAM_STATE_BUSY)
764 {
765 status = HAL_BUSY;
766 }
767 else if (hsdram->State == HAL_SDRAM_STATE_READY)
768 {
769 /* Process Locked */
770 __HAL_LOCK(hsdram);
771
772 /* Update the SDRAM controller state */
773 hsdram->State = HAL_SDRAM_STATE_BUSY;
774
775 /* Configure DMA user callbacks */
776 hsdram->hmdma->XferCpltCallback = SDRAM_DMACplt;
777 hsdram->hmdma->XferErrorCallback = SDRAM_DMAError;
778
779 /* Enable the DMA Stream */
780 status = HAL_MDMA_Start_IT(hsdram->hmdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, (uint32_t)(BufferSize * 4U), 1);
781
782 /* Process Unlocked */
783 __HAL_UNLOCK(hsdram);
784 }
785 else
786 {
787 status = HAL_ERROR;
788 }
789
790 return status;
791 }
792
793 #if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
794 /**
795 * @brief Register a User SDRAM Callback
796 * To be used instead of the weak (surcharged) predefined callback
797 * @param hsdram : SDRAM handle
798 * @param CallbackId : ID of the callback to be registered
799 * This parameter can be one of the following values:
800 * @arg @ref HAL_SDRAM_MSP_INIT_CB_ID SDRAM MspInit callback ID
801 * @arg @ref HAL_SDRAM_MSP_DEINIT_CB_ID SDRAM MspDeInit callback ID
802 * @arg @ref HAL_SDRAM_REFRESH_ERR_CB_ID SDRAM Refresh Error callback ID
803 * @param pCallback : pointer to the Callback function
804 * @retval status
805 */
HAL_SDRAM_RegisterCallback(SDRAM_HandleTypeDef * hsdram,HAL_SDRAM_CallbackIDTypeDef CallbackId,pSDRAM_CallbackTypeDef pCallback)806 HAL_StatusTypeDef HAL_SDRAM_RegisterCallback(SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId,
807 pSDRAM_CallbackTypeDef pCallback)
808 {
809 HAL_StatusTypeDef status = HAL_OK;
810 HAL_SDRAM_StateTypeDef state;
811
812 if (pCallback == NULL)
813 {
814 return HAL_ERROR;
815 }
816
817 /* Process locked */
818 __HAL_LOCK(hsdram);
819
820 state = hsdram->State;
821 if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED))
822 {
823 switch (CallbackId)
824 {
825 case HAL_SDRAM_MSP_INIT_CB_ID :
826 hsdram->MspInitCallback = pCallback;
827 break;
828 case HAL_SDRAM_MSP_DEINIT_CB_ID :
829 hsdram->MspDeInitCallback = pCallback;
830 break;
831 case HAL_SDRAM_REFRESH_ERR_CB_ID :
832 hsdram->RefreshErrorCallback = pCallback;
833 break;
834 default :
835 /* update return status */
836 status = HAL_ERROR;
837 break;
838 }
839 }
840 else if (hsdram->State == HAL_SDRAM_STATE_RESET)
841 {
842 switch (CallbackId)
843 {
844 case HAL_SDRAM_MSP_INIT_CB_ID :
845 hsdram->MspInitCallback = pCallback;
846 break;
847 case HAL_SDRAM_MSP_DEINIT_CB_ID :
848 hsdram->MspDeInitCallback = pCallback;
849 break;
850 default :
851 /* update return status */
852 status = HAL_ERROR;
853 break;
854 }
855 }
856 else
857 {
858 /* update return status */
859 status = HAL_ERROR;
860 }
861
862 /* Release Lock */
863 __HAL_UNLOCK(hsdram);
864 return status;
865 }
866
867 /**
868 * @brief Unregister a User SDRAM Callback
869 * SDRAM Callback is redirected to the weak (surcharged) predefined callback
870 * @param hsdram : SDRAM handle
871 * @param CallbackId : ID of the callback to be unregistered
872 * This parameter can be one of the following values:
873 * @arg @ref HAL_SDRAM_MSP_INIT_CB_ID SDRAM MspInit callback ID
874 * @arg @ref HAL_SDRAM_MSP_DEINIT_CB_ID SDRAM MspDeInit callback ID
875 * @arg @ref HAL_SDRAM_REFRESH_ERR_CB_ID SDRAM Refresh Error callback ID
876 * @arg @ref HAL_SDRAM_DMA_XFER_CPLT_CB_ID SDRAM DMA Xfer Complete callback ID
877 * @arg @ref HAL_SDRAM_DMA_XFER_ERR_CB_ID SDRAM DMA Xfer Error callback ID
878 * @retval status
879 */
HAL_SDRAM_UnRegisterCallback(SDRAM_HandleTypeDef * hsdram,HAL_SDRAM_CallbackIDTypeDef CallbackId)880 HAL_StatusTypeDef HAL_SDRAM_UnRegisterCallback(SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId)
881 {
882 HAL_StatusTypeDef status = HAL_OK;
883 HAL_SDRAM_StateTypeDef state;
884
885 /* Process locked */
886 __HAL_LOCK(hsdram);
887
888 state = hsdram->State;
889 if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED))
890 {
891 switch (CallbackId)
892 {
893 case HAL_SDRAM_MSP_INIT_CB_ID :
894 hsdram->MspInitCallback = HAL_SDRAM_MspInit;
895 break;
896 case HAL_SDRAM_MSP_DEINIT_CB_ID :
897 hsdram->MspDeInitCallback = HAL_SDRAM_MspDeInit;
898 break;
899 case HAL_SDRAM_REFRESH_ERR_CB_ID :
900 hsdram->RefreshErrorCallback = HAL_SDRAM_RefreshErrorCallback;
901 break;
902 case HAL_SDRAM_DMA_XFER_CPLT_CB_ID :
903 hsdram->DmaXferCpltCallback = HAL_SDRAM_DMA_XferCpltCallback;
904 break;
905 case HAL_SDRAM_DMA_XFER_ERR_CB_ID :
906 hsdram->DmaXferErrorCallback = HAL_SDRAM_DMA_XferErrorCallback;
907 break;
908 default :
909 /* update return status */
910 status = HAL_ERROR;
911 break;
912 }
913 }
914 else if (hsdram->State == HAL_SDRAM_STATE_RESET)
915 {
916 switch (CallbackId)
917 {
918 case HAL_SDRAM_MSP_INIT_CB_ID :
919 hsdram->MspInitCallback = HAL_SDRAM_MspInit;
920 break;
921 case HAL_SDRAM_MSP_DEINIT_CB_ID :
922 hsdram->MspDeInitCallback = HAL_SDRAM_MspDeInit;
923 break;
924 default :
925 /* update return status */
926 status = HAL_ERROR;
927 break;
928 }
929 }
930 else
931 {
932 /* update return status */
933 status = HAL_ERROR;
934 }
935
936 /* Release Lock */
937 __HAL_UNLOCK(hsdram);
938 return status;
939 }
940
941 /**
942 * @brief Register a User SDRAM Callback for DMA transfers
943 * To be used instead of the weak (surcharged) predefined callback
944 * @param hsdram : SDRAM handle
945 * @param CallbackId : ID of the callback to be registered
946 * This parameter can be one of the following values:
947 * @arg @ref HAL_SDRAM_DMA_XFER_CPLT_CB_ID SDRAM DMA Xfer Complete callback ID
948 * @arg @ref HAL_SDRAM_DMA_XFER_ERR_CB_ID SDRAM DMA Xfer Error callback ID
949 * @param pCallback : pointer to the Callback function
950 * @retval status
951 */
HAL_SDRAM_RegisterDmaCallback(SDRAM_HandleTypeDef * hsdram,HAL_SDRAM_CallbackIDTypeDef CallbackId,pSDRAM_DmaCallbackTypeDef pCallback)952 HAL_StatusTypeDef HAL_SDRAM_RegisterDmaCallback(SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId,
953 pSDRAM_DmaCallbackTypeDef pCallback)
954 {
955 HAL_StatusTypeDef status = HAL_OK;
956 HAL_SDRAM_StateTypeDef state;
957
958 if (pCallback == NULL)
959 {
960 return HAL_ERROR;
961 }
962
963 /* Process locked */
964 __HAL_LOCK(hsdram);
965
966 state = hsdram->State;
967 if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED))
968 {
969 switch (CallbackId)
970 {
971 case HAL_SDRAM_DMA_XFER_CPLT_CB_ID :
972 hsdram->DmaXferCpltCallback = pCallback;
973 break;
974 case HAL_SDRAM_DMA_XFER_ERR_CB_ID :
975 hsdram->DmaXferErrorCallback = pCallback;
976 break;
977 default :
978 /* update return status */
979 status = HAL_ERROR;
980 break;
981 }
982 }
983 else
984 {
985 /* update return status */
986 status = HAL_ERROR;
987 }
988
989 /* Release Lock */
990 __HAL_UNLOCK(hsdram);
991 return status;
992 }
993 #endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */
994
995 /**
996 * @}
997 */
998
999 /** @defgroup SDRAM_Exported_Functions_Group3 Control functions
1000 * @brief management functions
1001 *
1002 @verbatim
1003 ==============================================================================
1004 ##### SDRAM Control functions #####
1005 ==============================================================================
1006 [..]
1007 This subsection provides a set of functions allowing to control dynamically
1008 the SDRAM interface.
1009
1010 @endverbatim
1011 * @{
1012 */
1013
1014 /**
1015 * @brief Enables dynamically SDRAM write protection.
1016 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
1017 * the configuration information for SDRAM module.
1018 * @retval HAL status
1019 */
HAL_SDRAM_WriteProtection_Enable(SDRAM_HandleTypeDef * hsdram)1020 HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Enable(SDRAM_HandleTypeDef *hsdram)
1021 {
1022 /* Check the SDRAM controller state */
1023 if (hsdram->State == HAL_SDRAM_STATE_BUSY)
1024 {
1025 return HAL_BUSY;
1026 }
1027 else if (hsdram->State == HAL_SDRAM_STATE_READY)
1028 {
1029 /* Update the SDRAM state */
1030 hsdram->State = HAL_SDRAM_STATE_BUSY;
1031
1032 /* Enable write protection */
1033 (void)FMC_SDRAM_WriteProtection_Enable(hsdram->Instance, hsdram->Init.SDBank);
1034
1035 /* Update the SDRAM state */
1036 hsdram->State = HAL_SDRAM_STATE_WRITE_PROTECTED;
1037 }
1038 else
1039 {
1040 return HAL_ERROR;
1041 }
1042
1043 return HAL_OK;
1044 }
1045
1046 /**
1047 * @brief Disables dynamically SDRAM write protection.
1048 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
1049 * the configuration information for SDRAM module.
1050 * @retval HAL status
1051 */
HAL_SDRAM_WriteProtection_Disable(SDRAM_HandleTypeDef * hsdram)1052 HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Disable(SDRAM_HandleTypeDef *hsdram)
1053 {
1054 HAL_SDRAM_StateTypeDef state = hsdram->State;
1055
1056 /* Check the SDRAM controller state */
1057 if (state == HAL_SDRAM_STATE_BUSY)
1058 {
1059 return HAL_BUSY;
1060 }
1061 else if (state == HAL_SDRAM_STATE_WRITE_PROTECTED)
1062 {
1063 /* Update the SDRAM state */
1064 hsdram->State = HAL_SDRAM_STATE_BUSY;
1065
1066 /* Disable write protection */
1067 (void)FMC_SDRAM_WriteProtection_Disable(hsdram->Instance, hsdram->Init.SDBank);
1068
1069 /* Update the SDRAM state */
1070 hsdram->State = HAL_SDRAM_STATE_READY;
1071 }
1072 else
1073 {
1074 return HAL_ERROR;
1075 }
1076
1077 return HAL_OK;
1078 }
1079
1080 /**
1081 * @brief Sends Command to the SDRAM bank.
1082 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
1083 * the configuration information for SDRAM module.
1084 * @param Command SDRAM command structure
1085 * @param Timeout Timeout duration
1086 * @retval HAL status
1087 */
HAL_SDRAM_SendCommand(SDRAM_HandleTypeDef * hsdram,FMC_SDRAM_CommandTypeDef * Command,uint32_t Timeout)1088 HAL_StatusTypeDef HAL_SDRAM_SendCommand(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command,
1089 uint32_t Timeout)
1090 {
1091 HAL_SDRAM_StateTypeDef state = hsdram->State;
1092
1093 /* Check the SDRAM controller state */
1094 if (state == HAL_SDRAM_STATE_BUSY)
1095 {
1096 return HAL_BUSY;
1097 }
1098 else if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_PRECHARGED))
1099 {
1100 /* Update the SDRAM state */
1101 hsdram->State = HAL_SDRAM_STATE_BUSY;
1102
1103 /* Send SDRAM command */
1104 (void)FMC_SDRAM_SendCommand(hsdram->Instance, Command, Timeout);
1105
1106 /* Update the SDRAM controller state state */
1107 if (Command->CommandMode == FMC_SDRAM_CMD_PALL)
1108 {
1109 hsdram->State = HAL_SDRAM_STATE_PRECHARGED;
1110 }
1111 else
1112 {
1113 hsdram->State = HAL_SDRAM_STATE_READY;
1114 }
1115 }
1116 else
1117 {
1118 return HAL_ERROR;
1119 }
1120
1121 return HAL_OK;
1122 }
1123
1124 /**
1125 * @brief Programs the SDRAM Memory Refresh rate.
1126 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
1127 * the configuration information for SDRAM module.
1128 * @param RefreshRate The SDRAM refresh rate value
1129 * @retval HAL status
1130 */
HAL_SDRAM_ProgramRefreshRate(SDRAM_HandleTypeDef * hsdram,uint32_t RefreshRate)1131 HAL_StatusTypeDef HAL_SDRAM_ProgramRefreshRate(SDRAM_HandleTypeDef *hsdram, uint32_t RefreshRate)
1132 {
1133 /* Check the SDRAM controller state */
1134 if (hsdram->State == HAL_SDRAM_STATE_BUSY)
1135 {
1136 return HAL_BUSY;
1137 }
1138 else if (hsdram->State == HAL_SDRAM_STATE_READY)
1139 {
1140 /* Update the SDRAM state */
1141 hsdram->State = HAL_SDRAM_STATE_BUSY;
1142
1143 /* Program the refresh rate */
1144 (void)FMC_SDRAM_ProgramRefreshRate(hsdram->Instance, RefreshRate);
1145
1146 /* Update the SDRAM state */
1147 hsdram->State = HAL_SDRAM_STATE_READY;
1148 }
1149 else
1150 {
1151 return HAL_ERROR;
1152 }
1153
1154 return HAL_OK;
1155 }
1156
1157 /**
1158 * @brief Sets the Number of consecutive SDRAM Memory auto Refresh commands.
1159 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
1160 * the configuration information for SDRAM module.
1161 * @param AutoRefreshNumber The SDRAM auto Refresh number
1162 * @retval HAL status
1163 */
HAL_SDRAM_SetAutoRefreshNumber(SDRAM_HandleTypeDef * hsdram,uint32_t AutoRefreshNumber)1164 HAL_StatusTypeDef HAL_SDRAM_SetAutoRefreshNumber(SDRAM_HandleTypeDef *hsdram, uint32_t AutoRefreshNumber)
1165 {
1166 /* Check the SDRAM controller state */
1167 if (hsdram->State == HAL_SDRAM_STATE_BUSY)
1168 {
1169 return HAL_BUSY;
1170 }
1171 else if (hsdram->State == HAL_SDRAM_STATE_READY)
1172 {
1173 /* Update the SDRAM state */
1174 hsdram->State = HAL_SDRAM_STATE_BUSY;
1175
1176 /* Set the Auto-Refresh number */
1177 (void)FMC_SDRAM_SetAutoRefreshNumber(hsdram->Instance, AutoRefreshNumber);
1178
1179 /* Update the SDRAM state */
1180 hsdram->State = HAL_SDRAM_STATE_READY;
1181 }
1182 else
1183 {
1184 return HAL_ERROR;
1185 }
1186
1187 return HAL_OK;
1188 }
1189
1190 /**
1191 * @brief Returns the SDRAM memory current mode.
1192 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
1193 * the configuration information for SDRAM module.
1194 * @retval The SDRAM memory mode.
1195 */
HAL_SDRAM_GetModeStatus(SDRAM_HandleTypeDef * hsdram)1196 uint32_t HAL_SDRAM_GetModeStatus(SDRAM_HandleTypeDef *hsdram)
1197 {
1198 /* Return the SDRAM memory current mode */
1199 return (FMC_SDRAM_GetModeStatus(hsdram->Instance, hsdram->Init.SDBank));
1200 }
1201
1202 /**
1203 * @}
1204 */
1205
1206 /** @defgroup SDRAM_Exported_Functions_Group4 State functions
1207 * @brief Peripheral State functions
1208 *
1209 @verbatim
1210 ==============================================================================
1211 ##### SDRAM State functions #####
1212 ==============================================================================
1213 [..]
1214 This subsection permits to get in run-time the status of the SDRAM controller
1215 and the data flow.
1216
1217 @endverbatim
1218 * @{
1219 */
1220
1221 /**
1222 * @brief Returns the SDRAM state.
1223 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
1224 * the configuration information for SDRAM module.
1225 * @retval HAL state
1226 */
HAL_SDRAM_GetState(SDRAM_HandleTypeDef * hsdram)1227 HAL_SDRAM_StateTypeDef HAL_SDRAM_GetState(SDRAM_HandleTypeDef *hsdram)
1228 {
1229 return hsdram->State;
1230 }
1231
1232 /**
1233 * @}
1234 */
1235
1236 /**
1237 * @}
1238 */
1239
1240 /** @addtogroup SDRAM_Private_Functions SDRAM Private Functions
1241 * @{
1242 */
1243 /**
1244 * @brief MDMA SDRAM process complete callback.
1245 * @param hmdma : MDMA handle
1246 * @retval None
1247 */
SDRAM_DMACplt(MDMA_HandleTypeDef * hmdma)1248 static void SDRAM_DMACplt(MDMA_HandleTypeDef *hmdma)
1249 {
1250 SDRAM_HandleTypeDef *hsdram = (SDRAM_HandleTypeDef *)(hmdma->Parent);
1251
1252 /* Disable the MDMA channel */
1253 __HAL_MDMA_DISABLE(hmdma);
1254
1255 /* Update the SDRAM controller state */
1256 hsdram->State = HAL_SDRAM_STATE_READY;
1257
1258 #if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
1259 hsdram->DmaXferCpltCallback(hmdma);
1260 #else
1261 HAL_SDRAM_DMA_XferCpltCallback(hmdma);
1262 #endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */
1263 }
1264
1265 /**
1266 * @brief MDMA SRAM process complete callback.
1267 * @param hmdma : MDMA handle
1268 * @retval None
1269 */
SDRAM_DMACpltProt(MDMA_HandleTypeDef * hmdma)1270 static void SDRAM_DMACpltProt(MDMA_HandleTypeDef *hmdma)
1271 {
1272 SDRAM_HandleTypeDef *hsdram = (SDRAM_HandleTypeDef *)(hmdma->Parent);
1273
1274 /* Disable the MDMA channel */
1275 __HAL_MDMA_DISABLE(hmdma);
1276
1277 /* Update the SDRAM controller state */
1278 hsdram->State = HAL_SDRAM_STATE_WRITE_PROTECTED;
1279
1280 #if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
1281 hsdram->DmaXferCpltCallback(hmdma);
1282 #else
1283 HAL_SDRAM_DMA_XferCpltCallback(hmdma);
1284 #endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */
1285 }
1286
1287 /**
1288 * @brief MDMA SDRAM error callback.
1289 * @param hmdma : MDMA handle
1290 * @retval None
1291 */
SDRAM_DMAError(MDMA_HandleTypeDef * hmdma)1292 static void SDRAM_DMAError(MDMA_HandleTypeDef *hmdma)
1293 {
1294 SDRAM_HandleTypeDef *hsdram = (SDRAM_HandleTypeDef *)(hmdma->Parent);
1295
1296 /* Disable the MDMA channel */
1297 __HAL_MDMA_DISABLE(hmdma);
1298
1299 /* Update the SDRAM controller state */
1300 hsdram->State = HAL_SDRAM_STATE_ERROR;
1301
1302 #if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
1303 hsdram->DmaXferErrorCallback(hmdma);
1304 #else
1305 HAL_SDRAM_DMA_XferErrorCallback(hmdma);
1306 #endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */
1307 }
1308
1309 /**
1310 * @}
1311 */
1312 /**
1313 * @}
1314 */
1315
1316 #endif /* HAL_SDRAM_MODULE_ENABLED */
1317
1318 /**
1319 * @}
1320 */
1321
1322
