1 /** 2 ****************************************************************************** 3 * @file stm32h7xx_hal_eth_legacy.h 4 * @author MCD Application Team 5 * @brief Header file of ETH HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2017 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32H7xx_HAL_ETH_LEGACY_H 21 #define STM32H7xx_HAL_ETH_LEGACY_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 28 /* Includes ------------------------------------------------------------------*/ 29 #include "stm32h7xx_hal_def.h" 30 31 #if defined(ETH) 32 33 /** @addtogroup STM32H7xx_HAL_Driver 34 * @{ 35 */ 36 37 /** @addtogroup ETH 38 * @{ 39 */ 40 41 /* Exported types ------------------------------------------------------------*/ 42 #ifndef ETH_TX_DESC_CNT 43 #define ETH_TX_DESC_CNT 4U 44 #endif 45 46 #ifndef ETH_RX_DESC_CNT 47 #define ETH_RX_DESC_CNT 4U 48 #endif 49 50 /*********************** Descriptors struct def section ************************/ 51 /** @defgroup ETH_Exported_Types ETH Exported Types 52 * @{ 53 */ 54 55 /** 56 * @brief ETH DMA Descriptor structure definition 57 */ 58 typedef struct 59 { 60 __IO uint32_t DESC0; 61 __IO uint32_t DESC1; 62 __IO uint32_t DESC2; 63 __IO uint32_t DESC3; 64 uint32_t BackupAddr0; /* used to store rx buffer 1 address */ 65 uint32_t BackupAddr1; /* used to store rx buffer 2 address */ 66 }ETH_DMADescTypeDef; 67 /** 68 * 69 */ 70 71 /** 72 * @brief ETH Buffers List structure definition 73 */ 74 typedef struct __ETH_BufferTypeDef 75 { 76 uint8_t *buffer; /*<! buffer address */ 77 78 uint32_t len; /*<! buffer length */ 79 80 struct __ETH_BufferTypeDef *next; /*<! Pointer to the next buffer in the list */ 81 }ETH_BufferTypeDef; 82 /** 83 * 84 */ 85 86 /** 87 * @brief DMA Transmit Descriptors Wrapper structure definition 88 */ 89 typedef struct 90 { 91 uint32_t TxDesc[ETH_TX_DESC_CNT]; /*<! Tx DMA descriptors addresses */ 92 93 uint32_t CurTxDesc; /*<! Current Tx descriptor index for packet transmission */ 94 95 uint32_t* PacketAddress[ETH_TX_DESC_CNT]; /*<! Ethernet packet addresses array */ 96 97 uint32_t* CurrentPacketAddress; /*<! Current transmit NX_PACKET addresses */ 98 99 uint32_t BuffersInUse; /*<! Buffers in Use */ 100 }ETH_TxDescListTypeDef; 101 /** 102 * 103 */ 104 105 /** 106 * @brief Transmit Packet Configuration structure definition 107 */ 108 typedef struct 109 { 110 uint32_t Attributes; /*!< Tx packet HW features capabilities. 111 This parameter can be a combination of @ref ETH_Tx_Packet_Attributes*/ 112 113 uint32_t Length; /*!< Total packet length */ 114 115 ETH_BufferTypeDef *TxBuffer; /*!< Tx buffers pointers */ 116 117 uint32_t SrcAddrCtrl; /*!< Specifies the source address insertion control. 118 This parameter can be a value of @ref ETH_Tx_Packet_Source_Addr_Control */ 119 120 uint32_t CRCPadCtrl; /*!< Specifies the CRC and Pad insertion and replacement control. 121 This parameter can be a value of @ref ETH_Tx_Packet_CRC_Pad_Control */ 122 123 uint32_t ChecksumCtrl; /*!< Specifies the checksum insertion control. 124 This parameter can be a value of @ref ETH_Tx_Packet_Checksum_Control */ 125 126 uint32_t MaxSegmentSize; /*!< Sets TCP maximum segment size only when TCP segmentation is enabled. 127 This parameter can be a value from 0x0 to 0x3FFF */ 128 129 uint32_t PayloadLen; /*!< Sets Total payload length only when TCP segmentation is enabled. 130 This parameter can be a value from 0x0 to 0x3FFFF */ 131 132 uint32_t TCPHeaderLen; /*!< Sets TCP header length only when TCP segmentation is enabled. 133 This parameter can be a value from 0x5 to 0xF */ 134 135 uint32_t VlanTag; /*!< Sets VLAN Tag only when VLAN is enabled. 136 This parameter can be a value from 0x0 to 0xFFFF*/ 137 138 uint32_t VlanCtrl; /*!< Specifies VLAN Tag insertion control only when VLAN is enabled. 139 This parameter can be a value of @ref ETH_Tx_Packet_VLAN_Control */ 140 141 uint32_t InnerVlanTag; /*!< Sets Inner VLAN Tag only when Inner VLAN is enabled. 142 This parameter can be a value from 0x0 to 0x3FFFF */ 143 144 uint32_t InnerVlanCtrl; /*!< Specifies Inner VLAN Tag insertion control only when Inner VLAN is enabled. 145 This parameter can be a value of @ref ETH_Tx_Packet_Inner_VLAN_Control */ 146 147 }ETH_TxPacketConfig; 148 /** 149 * 150 */ 151 152 /** 153 * @brief DMA Receive Descriptors Wrapper structure definition 154 */ 155 typedef struct 156 { 157 uint32_t RxDesc[ETH_RX_DESC_CNT]; /*<! Rx DMA descriptors addresses. */ 158 159 uint32_t CurRxDesc; /*<! Current Rx descriptor, ready for next reception. */ 160 161 uint32_t FirstAppDesc; /*<! First descriptor of last received packet. */ 162 163 uint32_t AppDescNbr; /*<! Number of descriptors of last received packet. */ 164 165 uint32_t AppContextDesc; /*<! If 1 a context descriptor is present in last received packet. 166 If 0 no context descriptor is present in last received packet. */ 167 168 uint32_t ItMode; /*<! If 1, DMA will generate the Rx complete interrupt. 169 If 0, DMA will not generate the Rx complete interrupt. */ 170 }ETH_RxDescListTypeDef; 171 /** 172 * 173 */ 174 175 /** 176 * @brief Received Packet Information structure definition 177 */ 178 typedef struct 179 { 180 uint32_t SegmentCnt; /*<! Number of Rx Descriptors */ 181 182 uint32_t VlanTag; /*<! Vlan Tag value */ 183 184 uint32_t InnerVlanTag; /*<! Inner Vlan Tag value */ 185 186 uint32_t Checksum; /*<! Rx Checksum status. 187 This parameter can be a value of @ref ETH_Rx_Checksum_Status */ 188 189 uint32_t HeaderType; /*<! IP header type. 190 This parameter can be a value of @ref ETH_Rx_IP_Header_Type */ 191 192 uint32_t PayloadType; /*<! Payload type. 193 This parameter can be a value of @ref ETH_Rx_Payload_Type */ 194 195 uint32_t MacFilterStatus; /*<! MAC filter status. 196 This parameter can be a value of @ref ETH_Rx_MAC_Filter_Status */ 197 198 uint32_t L3FilterStatus; /*<! L3 filter status 199 This parameter can be a value of @ref ETH_Rx_L3_Filter_Status */ 200 201 uint32_t L4FilterStatus; /*<! L4 filter status 202 This parameter can be a value of @ref ETH_Rx_L4_Filter_Status */ 203 204 uint32_t ErrorCode; /*<! Rx error code 205 This parameter can be a combination of @ref ETH_Rx_Error_Code */ 206 207 } ETH_RxPacketInfo; 208 /** 209 * 210 */ 211 212 /** 213 * @brief ETH MAC Configuration Structure definition 214 */ 215 typedef struct 216 { 217 uint32_t SourceAddrControl; /*!< Selects the Source Address Insertion or Replacement Control. 218 This parameter can be a value of @ref ETH_Source_Addr_Control */ 219 220 FunctionalState ChecksumOffload; /*!< Enables or Disable the checksum checking for received packet payloads TCP, UDP or ICMP headers */ 221 222 uint32_t InterPacketGapVal; /*!< Sets the minimum IPG between Packet during transmission. 223 This parameter can be a value of @ref ETH_Inter_Packet_Gap */ 224 225 FunctionalState GiantPacketSizeLimitControl; /*!< Enables or disables the Giant Packet Size Limit Control. */ 226 227 FunctionalState Support2KPacket; /*!< Enables or disables the IEEE 802.3as Support for 2K length Packets */ 228 229 FunctionalState CRCStripTypePacket; /*!< Enables or disables the CRC stripping for Type packets.*/ 230 231 FunctionalState AutomaticPadCRCStrip; /*!< Enables or disables the Automatic MAC Pad/CRC Stripping.*/ 232 233 FunctionalState Watchdog; /*!< Enables or disables the Watchdog timer on Rx path 234 When enabled, the MAC allows no more then 2048 bytes to be received. 235 When disabled, the MAC can receive up to 16384 bytes. */ 236 237 FunctionalState Jabber; /*!< Enables or disables Jabber timer on Tx path 238 When enabled, the MAC allows no more then 2048 bytes to be sent. 239 When disabled, the MAC can send up to 16384 bytes. */ 240 241 FunctionalState JumboPacket; /*!< Enables or disables receiving Jumbo Packet 242 When enabled, the MAC allows jumbo packets of 9,018 bytes 243 without reporting a giant packet error */ 244 245 uint32_t Speed; /*!< Sets the Ethernet speed: 10/100 Mbps. 246 This parameter can be a value of @ref ETH_Speed */ 247 248 uint32_t DuplexMode; /*!< Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode 249 This parameter can be a value of @ref ETH_Duplex_Mode */ 250 251 FunctionalState LoopbackMode; /*!< Enables or disables the loopback mode */ 252 253 FunctionalState CarrierSenseBeforeTransmit; /*!< Enables or disables the Carrier Sense Before Transmission in Full Duplex Mode. */ 254 255 FunctionalState ReceiveOwn; /*!< Enables or disables the Receive Own in Half Duplex mode. */ 256 257 FunctionalState CarrierSenseDuringTransmit; /*!< Enables or disables the Carrier Sense During Transmission in the Half Duplex mode */ 258 259 FunctionalState RetryTransmission; /*!< Enables or disables the MAC retry transmission, when a collision occurs in Half Duplex mode.*/ 260 261 uint32_t BackOffLimit; /*!< Selects the BackOff limit value. 262 This parameter can be a value of @ref ETH_Back_Off_Limit */ 263 264 FunctionalState DeferralCheck; /*!< Enables or disables the deferral check function in Half Duplex mode. */ 265 266 uint32_t PreambleLength; /*!< Selects or not the Preamble Length for Transmit packets (Full Duplex mode). 267 This parameter can be a value of @ref ETH_Preamble_Length */ 268 269 FunctionalState UnicastSlowProtocolPacketDetect; /*!< Enable or disables the Detection of Slow Protocol Packets with unicast address. */ 270 271 FunctionalState SlowProtocolDetect; /*!< Enable or disables the Slow Protocol Detection. */ 272 273 FunctionalState CRCCheckingRxPackets; /*!< Enable or disables the CRC Checking for Received Packets. */ 274 275 uint32_t GiantPacketSizeLimit; /*!< Specifies the packet size that the MAC will declare it as Giant, If it's size is 276 greater than the value programmed in this field in units of bytes 277 This parameter must be a number between Min_Data = 0x618 (1518 byte) and Max_Data = 0x3FFF (32 Kbyte)*/ 278 279 FunctionalState ExtendedInterPacketGap; /*!< Enable or disables the extended inter packet gap. */ 280 281 uint32_t ExtendedInterPacketGapVal; /*!< Sets the Extended IPG between Packet during transmission. 282 This parameter can be a value from 0x0 to 0xFF */ 283 284 FunctionalState ProgrammableWatchdog; /*!< Enable or disables the Programmable Watchdog.*/ 285 286 uint32_t WatchdogTimeout; /*!< This field is used as watchdog timeout for a received packet 287 This parameter can be a value of @ref ETH_Watchdog_Timeout */ 288 289 uint32_t PauseTime; /*!< This field holds the value to be used in the Pause Time field in the transmit control packet. 290 This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFF */ 291 292 FunctionalState ZeroQuantaPause; /*!< Enable or disables the automatic generation of Zero Quanta Pause Control packets.*/ 293 294 uint32_t PauseLowThreshold; /*!< This field configures the threshold of the PAUSE to be checked for automatic retransmission of PAUSE Packet. 295 This parameter can be a value of @ref ETH_Pause_Low_Threshold */ 296 297 FunctionalState TransmitFlowControl; /*!< Enables or disables the MAC to transmit Pause packets in Full Duplex mode 298 or the MAC back pressure operation in Half Duplex mode */ 299 300 FunctionalState UnicastPausePacketDetect; /*!< Enables or disables the MAC to detect Pause packets with unicast address of the station */ 301 302 FunctionalState ReceiveFlowControl; /*!< Enables or disables the MAC to decodes the received Pause packet 303 and disables its transmitter for a specified (Pause) time */ 304 305 uint32_t TransmitQueueMode; /*!< Specifies the Transmit Queue operating mode. 306 This parameter can be a value of @ref ETH_Transmit_Mode */ 307 308 uint32_t ReceiveQueueMode; /*!< Specifies the Receive Queue operating mode. 309 This parameter can be a value of @ref ETH_Receive_Mode */ 310 311 FunctionalState DropTCPIPChecksumErrorPacket; /*!< Enables or disables Dropping of TCPIP Checksum Error Packets. */ 312 313 FunctionalState ForwardRxErrorPacket; /*!< Enables or disables forwarding Error Packets. */ 314 315 FunctionalState ForwardRxUndersizedGoodPacket; /*!< Enables or disables forwarding Undersized Good Packets.*/ 316 } ETH_MACConfigTypeDef; 317 /** 318 * 319 */ 320 321 /** 322 * @brief ETH DMA Configuration Structure definition 323 */ 324 typedef struct 325 { 326 uint32_t DMAArbitration; /*!< Sets the arbitration scheme between DMA Tx and Rx 327 This parameter can be a value of @ref ETH_DMA_Arbitration */ 328 329 FunctionalState AddressAlignedBeats; /*!< Enables or disables the AHB Master interface address aligned 330 burst transfers on Read and Write channels */ 331 332 uint32_t BurstMode; /*!< Sets the AHB Master interface burst transfers. 333 This parameter can be a value of @ref ETH_Burst_Mode */ 334 335 FunctionalState RebuildINCRxBurst; /*!< Enables or disables the AHB Master to rebuild the pending beats 336 of any initiated burst transfer with INCRx and SINGLE transfers. */ 337 338 FunctionalState PBLx8Mode; /*!< Enables or disables the PBL multiplication by eight. */ 339 340 uint32_t TxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Tx DMA transaction. 341 This parameter can be a value of @ref ETH_Tx_DMA_Burst_Length */ 342 343 FunctionalState SecondPacketOperate; /*!< Enables or disables the Operate on second Packet mode, which allows the DMA to process a second 344 Packet of Transmit data even before obtaining the status for the first one. */ 345 346 uint32_t RxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Rx DMA transaction. 347 This parameter can be a value of @ref ETH_Rx_DMA_Burst_Length */ 348 349 FunctionalState FlushRxPacket; /*!< Enables or disables the Rx Packet Flush */ 350 351 FunctionalState TCPSegmentation; /*!< Enables or disables the TCP Segmentation */ 352 353 uint32_t MaximumSegmentSize; /*!< Sets the maximum segment size that should be used while segmenting the packet 354 This parameter can be a value from 0x40 to 0x3FFF */ 355 } ETH_DMAConfigTypeDef; 356 /** 357 * 358 */ 359 360 /** 361 * @brief HAL ETH Media Interfaces enum definition 362 */ 363 typedef enum 364 { 365 HAL_ETH_MII_MODE = 0x00U, /*!< Media Independent Interface */ 366 HAL_ETH_RMII_MODE = 0x01U /*!< Reduced Media Independent Interface */ 367 }ETH_MediaInterfaceTypeDef; 368 /** 369 * 370 */ 371 372 /** 373 * @brief ETH Init Structure definition 374 */ 375 typedef struct 376 { 377 378 uint8_t *MACAddr; /*!< MAC Address of used Hardware: must be pointer on an array of 6 bytes */ 379 380 ETH_MediaInterfaceTypeDef MediaInterface; /*!< Selects the MII interface or the RMII interface. */ 381 382 ETH_DMADescTypeDef *TxDesc; /*!< Provides the address of the first DMA Tx descriptor in the list */ 383 384 ETH_DMADescTypeDef *RxDesc; /*!< Provides the address of the first DMA Rx descriptor in the list */ 385 386 uint32_t RxBuffLen; /*!< Provides the length of Rx buffers size */ 387 388 }ETH_InitTypeDef; 389 /** 390 * 391 */ 392 393 /** 394 * @brief HAL State structures definition 395 */ 396 typedef uint32_t HAL_ETH_StateTypeDef; 397 /** 398 * 399 */ 400 401 /** 402 * @brief ETH Handle Structure definition 403 */ 404 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) 405 typedef struct __ETH_HandleTypeDef 406 #else 407 typedef struct 408 #endif 409 { 410 ETH_TypeDef *Instance; /*!< Register base address */ 411 412 ETH_InitTypeDef Init; /*!< Ethernet Init Configuration */ 413 414 ETH_TxDescListTypeDef TxDescList; /*!< Tx descriptor wrapper: holds all Tx descriptors list 415 addresses and current descriptor index */ 416 417 ETH_RxDescListTypeDef RxDescList; /*!< Rx descriptor wrapper: holds all Rx descriptors list 418 addresses and current descriptor index */ 419 420 HAL_LockTypeDef Lock; /*!< Locking object */ 421 422 __IO HAL_ETH_StateTypeDef gState; /*!< ETH state information related to global Handle management 423 and also related to Tx operations. 424 This parameter can be a value of @ref HAL_ETH_StateTypeDef */ 425 426 __IO HAL_ETH_StateTypeDef RxState; /*!< ETH state information related to Rx operations. 427 This parameter can be a value of @ref HAL_ETH_StateTypeDef */ 428 429 __IO uint32_t ErrorCode; /*!< Holds the global Error code of the ETH HAL status machine 430 This parameter can be a value of of @ref ETH_Error_Code */ 431 432 __IO uint32_t DMAErrorCode; /*!< Holds the DMA Rx Tx Error code when a DMA AIS interrupt occurs 433 This parameter can be a combination of @ref ETH_DMA_Status_Flags */ 434 435 __IO uint32_t MACErrorCode; /*!< Holds the MAC Rx Tx Error code when a MAC Rx or Tx status interrupt occurs 436 This parameter can be a combination of @ref ETH_MAC_Rx_Tx_Status */ 437 438 __IO uint32_t MACWakeUpEvent; /*!< Holds the Wake Up event when the MAC exit the power down mode 439 This parameter can be a value of @ref ETH_MAC_Wake_Up_Event */ 440 441 __IO uint32_t MACLPIEvent; /*!< Holds the LPI event when the an LPI status interrupt occurs. 442 This parameter can be a value of @ref ETHEx_LPI_Event */ 443 444 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) 445 446 void (* TxCpltCallback) ( struct __ETH_HandleTypeDef * heth); /*!< ETH Tx Complete Callback */ 447 void (* RxCpltCallback) ( struct __ETH_HandleTypeDef * heth); /*!< ETH Rx Complete Callback */ 448 void (* DMAErrorCallback) ( struct __ETH_HandleTypeDef * heth); /*!< ETH DMA Error Callback */ 449 void (* MACErrorCallback) ( struct __ETH_HandleTypeDef * heth); /*!< ETH MAC Error Callback */ 450 void (* PMTCallback) ( struct __ETH_HandleTypeDef * heth); /*!< ETH Power Management Callback */ 451 void (* EEECallback) ( struct __ETH_HandleTypeDef * heth); /*!< ETH EEE Callback */ 452 void (* WakeUpCallback) ( struct __ETH_HandleTypeDef * heth); /*!< ETH Wake UP Callback */ 453 454 void (* MspInitCallback) ( struct __ETH_HandleTypeDef * heth); /*!< ETH Msp Init callback */ 455 void (* MspDeInitCallback) ( struct __ETH_HandleTypeDef * heth); /*!< ETH Msp DeInit callback */ 456 457 #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ 458 459 } ETH_HandleTypeDef; 460 /** 461 * 462 */ 463 464 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) 465 /** 466 * @brief HAL ETH Callback ID enumeration definition 467 */ 468 typedef enum 469 { 470 HAL_ETH_MSPINIT_CB_ID = 0x00U, /*!< ETH MspInit callback ID */ 471 HAL_ETH_MSPDEINIT_CB_ID = 0x01U, /*!< ETH MspDeInit callback ID */ 472 473 HAL_ETH_TX_COMPLETE_CB_ID = 0x02U, /*!< ETH Tx Complete Callback ID */ 474 HAL_ETH_RX_COMPLETE_CB_ID = 0x03U, /*!< ETH Rx Complete Callback ID */ 475 HAL_ETH_DMA_ERROR_CB_ID = 0x04U, /*!< ETH DMA Error Callback ID */ 476 HAL_ETH_MAC_ERROR_CB_ID = 0x05U, /*!< ETH MAC Error Callback ID */ 477 HAL_ETH_PMT_CB_ID = 0x06U, /*!< ETH Power Management Callback ID */ 478 HAL_ETH_EEE_CB_ID = 0x07U, /*!< ETH EEE Callback ID */ 479 HAL_ETH_WAKEUP_CB_ID = 0x08U /*!< ETH Wake UP Callback ID */ 480 481 482 }HAL_ETH_CallbackIDTypeDef; 483 484 /** 485 * @brief HAL ETH Callback pointer definition 486 */ 487 typedef void (*pETH_CallbackTypeDef)(ETH_HandleTypeDef * heth); /*!< pointer to an ETH callback function */ 488 489 #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ 490 491 /** 492 * @brief ETH MAC filter structure definition 493 */ 494 typedef struct{ 495 FunctionalState PromiscuousMode; /*!< Enable or Disable Promiscuous Mode */ 496 497 FunctionalState ReceiveAllMode; /*!< Enable or Disable Receive All Mode */ 498 499 FunctionalState HachOrPerfectFilter; /*!< Enable or Disable Perfect filtering in addition to Hash filtering */ 500 501 FunctionalState HashUnicast; /*!< Enable or Disable Hash filtering on unicast packets */ 502 503 FunctionalState HashMulticast; /*!< Enable or Disable Hash filtering on multicast packets */ 504 505 FunctionalState PassAllMulticast; /*!< Enable or Disable passing all multicast packets */ 506 507 FunctionalState SrcAddrFiltering; /*!< Enable or Disable source address filtering module */ 508 509 FunctionalState SrcAddrInverseFiltering; /*!< Enable or Disable source address inverse filtering */ 510 511 FunctionalState DestAddrInverseFiltering; /*!< Enable or Disable destination address inverse filtering */ 512 513 FunctionalState BroadcastFilter; /*!< Enable or Disable broadcast filter */ 514 515 uint32_t ControlPacketsFilter; /*!< Set the control packets filter 516 This parameter can be a value of @ref ETH_Control_Packets_Filter */ 517 }ETH_MACFilterConfigTypeDef; 518 /** 519 * 520 */ 521 522 /** 523 * @brief ETH Power Down structure definition 524 */ 525 typedef struct{ 526 FunctionalState WakeUpPacket; /*!< Enable or Disable Wake up packet detection in power down mode */ 527 528 FunctionalState MagicPacket; /*!< Enable or Disable Magic packet detection in power down mode */ 529 530 FunctionalState GlobalUnicast; /*!< Enable or Disable Global unicast packet detection in power down mode */ 531 532 FunctionalState WakeUpForward; /*!< Enable or Disable Forwarding Wake up packets */ 533 534 }ETH_PowerDownConfigTypeDef; 535 /** 536 * 537 */ 538 539 /** 540 * @} 541 */ 542 543 /* Exported constants --------------------------------------------------------*/ 544 /** @defgroup ETH_Exported_Constants ETH Exported Constants 545 * @{ 546 */ 547 548 /** @defgroup ETH_DMA_Tx_Descriptor_Bit_Definition ETH DMA Tx Descriptor Bit Definition 549 * @{ 550 */ 551 552 /* 553 DMA Tx Normal Descriptor Read Format 554 ----------------------------------------------------------------------------------------------- 555 TDES0 | Buffer1 or Header Address [31:0] | 556 ----------------------------------------------------------------------------------------------- 557 TDES1 | Buffer2 Address [31:0] / Next Descriptor Address [31:0] | 558 ----------------------------------------------------------------------------------------------- 559 TDES2 | IOC(31) | TTSE(30) | Buff2 Length[29:16] | VTIR[15:14] | Header or Buff1 Length[13:0] | 560 ----------------------------------------------------------------------------------------------- 561 TDES3 | OWN(31) | CTRL[30:26] | Reserved[25:24] | CTRL[23:20] | Reserved[19:17] | Status[16:0] | 562 ----------------------------------------------------------------------------------------------- 563 */ 564 565 /** 566 * @brief Bit definition of TDES0 RF register 567 */ 568 #define ETH_DMATXNDESCRF_B1AP ((uint32_t)0xFFFFFFFFU) /*!< Transmit Packet Timestamp Low */ 569 570 /** 571 * @brief Bit definition of TDES1 RF register 572 */ 573 #define ETH_DMATXNDESCRF_B2AP ((uint32_t)0xFFFFFFFFU) /*!< Transmit Packet Timestamp High */ 574 575 /** 576 * @brief Bit definition of TDES2 RF register 577 */ 578 #define ETH_DMATXNDESCRF_IOC ((uint32_t)0x80000000U) /*!< Interrupt on Completion */ 579 #define ETH_DMATXNDESCRF_TTSE ((uint32_t)0x40000000U) /*!< Transmit Timestamp Enable */ 580 #define ETH_DMATXNDESCRF_B2L ((uint32_t)0x3FFF0000U) /*!< Buffer 2 Length */ 581 #define ETH_DMATXNDESCRF_VTIR ((uint32_t)0x0000C000U) /*!< VLAN Tag Insertion or Replacement mask */ 582 #define ETH_DMATXNDESCRF_VTIR_DISABLE ((uint32_t)0x00000000U) /*!< Do not add a VLAN tag. */ 583 #define ETH_DMATXNDESCRF_VTIR_REMOVE ((uint32_t)0x00004000U) /*!< Remove the VLAN tag from the packets before transmission. */ 584 #define ETH_DMATXNDESCRF_VTIR_INSERT ((uint32_t)0x00008000U) /*!< Insert a VLAN tag. */ 585 #define ETH_DMATXNDESCRF_VTIR_REPLACE ((uint32_t)0x0000C000U) /*!< Replace the VLAN tag. */ 586 #define ETH_DMATXNDESCRF_B1L ((uint32_t)0x00003FFFU) /*!< Buffer 1 Length */ 587 #define ETH_DMATXNDESCRF_HL ((uint32_t)0x000003FFU) /*!< Header Length */ 588 589 /** 590 * @brief Bit definition of TDES3 RF register 591 */ 592 #define ETH_DMATXNDESCRF_OWN ((uint32_t)0x80000000U) /*!< OWN bit: descriptor is owned by DMA engine */ 593 #define ETH_DMATXNDESCRF_CTXT ((uint32_t)0x40000000U) /*!< Context Type */ 594 #define ETH_DMATXNDESCRF_FD ((uint32_t)0x20000000U) /*!< First Descriptor */ 595 #define ETH_DMATXNDESCRF_LD ((uint32_t)0x10000000U) /*!< Last Descriptor */ 596 #define ETH_DMATXNDESCRF_CPC ((uint32_t)0x0C000000U) /*!< CRC Pad Control mask */ 597 #define ETH_DMATXNDESCRF_CPC_CRCPAD_INSERT ((uint32_t)0x00000000U) /*!< CRC Pad Control: CRC and Pad Insertion */ 598 #define ETH_DMATXNDESCRF_CPC_CRC_INSERT ((uint32_t)0x04000000U) /*!< CRC Pad Control: CRC Insertion (Disable Pad Insertion) */ 599 #define ETH_DMATXNDESCRF_CPC_DISABLE ((uint32_t)0x08000000U) /*!< CRC Pad Control: Disable CRC Insertion */ 600 #define ETH_DMATXNDESCRF_CPC_CRC_REPLACE ((uint32_t)0x0C000000U) /*!< CRC Pad Control: CRC Replacement */ 601 #define ETH_DMATXNDESCRF_SAIC ((uint32_t)0x03800000U) /*!< SA Insertion Control mask*/ 602 #define ETH_DMATXNDESCRF_SAIC_DISABLE ((uint32_t)0x00000000U) /*!< SA Insertion Control: Do not include the source address */ 603 #define ETH_DMATXNDESCRF_SAIC_INSERT ((uint32_t)0x00800000U) /*!< SA Insertion Control: Include or insert the source address */ 604 #define ETH_DMATXNDESCRF_SAIC_REPLACE ((uint32_t)0x01000000U) /*!< SA Insertion Control: Replace the source address */ 605 #define ETH_DMATXNDESCRF_THL ((uint32_t)0x00780000U) /*!< TCP Header Length */ 606 #define ETH_DMATXNDESCRF_TSE ((uint32_t)0x00040000U) /*!< TCP segmentation enable */ 607 #define ETH_DMATXNDESCRF_CIC ((uint32_t)0x00030000U) /*!< Checksum Insertion Control: 4 cases */ 608 #define ETH_DMATXNDESCRF_CIC_DISABLE ((uint32_t)0x00000000U) /*!< Do Nothing: Checksum Engine is disabled */ 609 #define ETH_DMATXNDESCRF_CIC_IPHDR_INSERT ((uint32_t)0x00010000U) /*!< Only IP header checksum calculation and insertion are enabled. */ 610 #define ETH_DMATXNDESCRF_CIC_IPHDR_PAYLOAD_INSERT ((uint32_t)0x00020000U) /*!< IP header checksum and payload checksum calculation and insertion are 611 enabled, but pseudo header checksum is not calculated in hardware */ 612 #define ETH_DMATXNDESCRF_CIC_IPHDR_PAYLOAD_INSERT_PHDR_CALC ((uint32_t)0x00030000U) /*!< IP Header checksum and payload checksum calculation and insertion are 613 enabled, and pseudo header checksum is calculated in hardware. */ 614 #define ETH_DMATXNDESCRF_TPL ((uint32_t)0x0003FFFFU) /*!< TCP Payload Length */ 615 #define ETH_DMATXNDESCRF_FL ((uint32_t)0x00007FFFU) /*!< Transmit End of Ring */ 616 617 /* 618 DMA Tx Normal Descriptor Write Back Format 619 ----------------------------------------------------------------------------------------------- 620 TDES0 | Timestamp Low | 621 ----------------------------------------------------------------------------------------------- 622 TDES1 | Timestamp High | 623 ----------------------------------------------------------------------------------------------- 624 TDES2 | Reserved[31:0] | 625 ----------------------------------------------------------------------------------------------- 626 TDES3 | OWN(31) | Status[30:0] | 627 ----------------------------------------------------------------------------------------------- 628 */ 629 630 /** 631 * @brief Bit definition of TDES0 WBF register 632 */ 633 #define ETH_DMATXNDESCWBF_TTSL ((uint32_t)0xFFFFFFFFU) /*!< Buffer1 Address Pointer or TSO Header Address Pointer */ 634 635 /** 636 * @brief Bit definition of TDES1 WBF register 637 */ 638 #define ETH_DMATXNDESCWBF_TTSH ((uint32_t)0xFFFFFFFFU) /*!< Buffer2 Address Pointer */ 639 640 /** 641 * @brief Bit definition of TDES3 WBF register 642 */ 643 #define ETH_DMATXNDESCWBF_OWN ((uint32_t)0x80000000U) /*!< OWN bit: descriptor is owned by DMA engine */ 644 #define ETH_DMATXNDESCWBF_CTXT ((uint32_t)0x40000000U) /*!< Context Type */ 645 #define ETH_DMATXNDESCWBF_FD ((uint32_t)0x20000000U) /*!< First Descriptor */ 646 #define ETH_DMATXNDESCWBF_LD ((uint32_t)0x10000000U) /*!< Last Descriptor */ 647 #define ETH_DMATXNDESCWBF_TTSS ((uint32_t)0x00020000U) /*!< Tx Timestamp Status */ 648 #define ETH_DMATXNDESCWBF_DP ((uint32_t)0x04000000U) /*!< Disable Padding */ 649 #define ETH_DMATXNDESCWBF_TTSE ((uint32_t)0x02000000U) /*!< Transmit Timestamp Enable */ 650 #define ETH_DMATXNDESCWBF_ES ((uint32_t)0x00008000U) /*!< Error summary: OR of the following bits: IHE || UF || ED || EC || LCO || PCE || NC || LCA || FF || JT */ 651 #define ETH_DMATXNDESCWBF_JT ((uint32_t)0x00004000U) /*!< Jabber Timeout */ 652 #define ETH_DMATXNDESCWBF_FF ((uint32_t)0x00002000U) /*!< Packet Flushed: DMA/MTL flushed the packet due to SW flush */ 653 #define ETH_DMATXNDESCWBF_PCE ((uint32_t)0x00001000U) /*!< Payload Checksum Error */ 654 #define ETH_DMATXNDESCWBF_LCA ((uint32_t)0x00000800U) /*!< Loss of Carrier: carrier lost during transmission */ 655 #define ETH_DMATXNDESCWBF_NC ((uint32_t)0x00000400U) /*!< No Carrier: no carrier signal from the transceiver */ 656 #define ETH_DMATXNDESCWBF_LCO ((uint32_t)0x00000200U) /*!< Late Collision: transmission aborted due to collision */ 657 #define ETH_DMATXNDESCWBF_EC ((uint32_t)0x00000100U) /*!< Excessive Collision: transmission aborted after 16 collisions */ 658 #define ETH_DMATXNDESCWBF_CC ((uint32_t)0x000000F0U) /*!< Collision Count */ 659 #define ETH_DMATXNDESCWBF_ED ((uint32_t)0x00000008U) /*!< Excessive Deferral */ 660 #define ETH_DMATXNDESCWBF_UF ((uint32_t)0x00000004U) /*!< Underflow Error: late data arrival from the memory */ 661 #define ETH_DMATXNDESCWBF_DB ((uint32_t)0x00000002U) /*!< Deferred Bit */ 662 #define ETH_DMATXNDESCWBF_IHE ((uint32_t)0x00000004U) /*!< IP Header Error */ 663 664 665 /* 666 DMA Tx Context Descriptor 667 ----------------------------------------------------------------------------------------------- 668 TDES0 | Timestamp Low | 669 ----------------------------------------------------------------------------------------------- 670 TDES1 | Timestamp High | 671 ----------------------------------------------------------------------------------------------- 672 TDES2 | Inner VLAN Tag[31:16] | Reserved(15) | Maximum Segment Size [14:0] | 673 ----------------------------------------------------------------------------------------------- 674 TDES3 | OWN(31) | Status[30:0] | 675 ----------------------------------------------------------------------------------------------- 676 */ 677 678 /** 679 * @brief Bit definition of Tx context descriptor register 0 680 */ 681 #define ETH_DMATXCDESC_TTSL ((uint32_t)0xFFFFFFFFU) /*!< Transmit Packet Timestamp Low */ 682 683 /** 684 * @brief Bit definition of Tx context descriptor register 1 685 */ 686 #define ETH_DMATXCDESC_TTSH ((uint32_t)0xFFFFFFFFU) /*!< Transmit Packet Timestamp High */ 687 688 /** 689 * @brief Bit definition of Tx context descriptor register 2 690 */ 691 #define ETH_DMATXCDESC_IVT ((uint32_t)0xFFFF0000U) /*!< Inner VLAN Tag */ 692 #define ETH_DMATXCDESC_MSS ((uint32_t)0x00003FFFU) /*!< Maximum Segment Size */ 693 694 /** 695 * @brief Bit definition of Tx context descriptor register 3 696 */ 697 #define ETH_DMATXCDESC_OWN ((uint32_t)0x80000000U) /*!< OWN bit: descriptor is owned by DMA engine */ 698 #define ETH_DMATXCDESC_CTXT ((uint32_t)0x40000000U) /*!< Context Type */ 699 #define ETH_DMATXCDESC_OSTC ((uint32_t)0x08000000U) /*!< One-Step Timestamp Correction Enable */ 700 #define ETH_DMATXCDESC_TCMSSV ((uint32_t)0x04000000U) /*!< One-Step Timestamp Correction Input or MSS Valid */ 701 #define ETH_DMATXCDESC_CDE ((uint32_t)0x00800000U) /*!< Context Descriptor Error */ 702 #define ETH_DMATXCDESC_IVTIR ((uint32_t)0x000C0000U) /*!< Inner VLAN Tag Insert or Replace Mask */ 703 #define ETH_DMATXCDESC_IVTIR_DISABLE ((uint32_t)0x00000000U) /*!< Do not add the inner VLAN tag. */ 704 #define ETH_DMATXCDESC_IVTIR_REMOVE ((uint32_t)0x00040000U) /*!< Remove the inner VLAN tag from the packets before transmission. */ 705 #define ETH_DMATXCDESC_IVTIR_INSERT ((uint32_t)0x00080000U) /*!< Insert the inner VLAN tag. */ 706 #define ETH_DMATXCDESC_IVTIR_REPLACE ((uint32_t)0x000C0000U) /*!< Replace the inner VLAN tag. */ 707 #define ETH_DMATXCDESC_IVLTV ((uint32_t)0x00020000U) /*!< Inner VLAN Tag Valid */ 708 #define ETH_DMATXCDESC_VLTV ((uint32_t)0x00010000U) /*!< VLAN Tag Valid */ 709 #define ETH_DMATXCDESC_VT ((uint32_t)0x0000FFFFU) /*!< VLAN Tag */ 710 711 /** 712 * @} 713 */ 714 715 716 /** @defgroup ETH_DMA_Rx_Descriptor_Bit_Definition ETH DMA Rx Descriptor Bit Definition 717 * @{ 718 */ 719 720 /* 721 DMA Rx Normal Descriptor read format 722 ----------------------------------------------------------------------------------------------------------- 723 RDES0 | Buffer1 or Header Address [31:0] | 724 ----------------------------------------------------------------------------------------------------------- 725 RDES1 | Reserved | 726 ----------------------------------------------------------------------------------------------------------- 727 RDES2 | Payload or Buffer2 Address[31:0] | 728 ----------------------------------------------------------------------------------------------------------- 729 RDES3 | OWN(31) | IOC(30) | Reserved [29:26] | BUF2V(25) | BUF1V(24) | Reserved [23:0] | 730 ----------------------------------------------------------------------------------------------------------- 731 */ 732 733 /** 734 * @brief Bit definition of Rx normal descriptor register 0 read format 735 */ 736 #define ETH_DMARXNDESCRF_BUF1AP ((uint32_t)0xFFFFFFFFU) /*!< Header or Buffer 1 Address Pointer */ 737 738 /** 739 * @brief Bit definition of Rx normal descriptor register 2 read format 740 */ 741 #define ETH_DMARXNDESCRF_BUF2AP ((uint32_t)0xFFFFFFFFU) /*!< Buffer 2 Address Pointer */ 742 743 /** 744 * @brief Bit definition of Rx normal descriptor register 3 read format 745 */ 746 #define ETH_DMARXNDESCRF_OWN ((uint32_t)0x80000000U) /*!< OWN bit: descriptor is owned by DMA engine */ 747 #define ETH_DMARXNDESCRF_IOC ((uint32_t)0x40000000U) /*!< Interrupt Enabled on Completion */ 748 #define ETH_DMARXNDESCRF_BUF2V ((uint32_t)0x02000000U) /*!< Buffer 2 Address Valid */ 749 #define ETH_DMARXNDESCRF_BUF1V ((uint32_t)0x01000000U) /*!< Buffer 1 Address Valid */ 750 751 /* 752 DMA Rx Normal Descriptor write back format 753 --------------------------------------------------------------------------------------------------------------------- 754 RDES0 | Inner VLAN Tag[31:16] | Outer VLAN Tag[15:0] | 755 --------------------------------------------------------------------------------------------------------------------- 756 RDES1 | OAM code, or MAC Control Opcode [31:16] | Extended Status | 757 --------------------------------------------------------------------------------------------------------------------- 758 RDES2 | MAC Filter Status[31:16] | VF(15) | Reserved [14:12] | ARP Status [11:10] | Header Length [9:0] | 759 --------------------------------------------------------------------------------------------------------------------- 760 RDES3 | OWN(31) | CTXT(30) | FD(29) | LD(28) | Status[27:16] | ES(15) | Packet Length[14:0] | 761 --------------------------------------------------------------------------------------------------------------------- 762 */ 763 764 /** 765 * @brief Bit definition of Rx normal descriptor register 0 write back format 766 */ 767 #define ETH_DMARXNDESCWBF_IVT ((uint32_t)0xFFFF0000U) /*!< Inner VLAN Tag */ 768 #define ETH_DMARXNDESCWBF_OVT ((uint32_t)0x0000FFFFU) /*!< Outer VLAN Tag */ 769 770 /** 771 * @brief Bit definition of Rx normal descriptor register 1 write back format 772 */ 773 #define ETH_DMARXNDESCWBF_OPC ((uint32_t)0xFFFF0000U) /*!< OAM Sub-Type Code, or MAC Control Packet opcode */ 774 #define ETH_DMARXNDESCWBF_TD ((uint32_t)0x00008000U) /*!< Timestamp Dropped */ 775 #define ETH_DMARXNDESCWBF_TSA ((uint32_t)0x00004000U) /*!< Timestamp Available */ 776 #define ETH_DMARXNDESCWBF_PV ((uint32_t)0x00002000U) /*!< PTP Version */ 777 #define ETH_DMARXNDESCWBF_PFT ((uint32_t)0x00001000U) /*!< PTP Packet Type */ 778 #define ETH_DMARXNDESCWBF_PMT_NO ((uint32_t)0x00000000U) /*!< PTP Message Type: No PTP message received */ 779 #define ETH_DMARXNDESCWBF_PMT_SYNC ((uint32_t)0x00000100U) /*!< PTP Message Type: SYNC (all clock types) */ 780 #define ETH_DMARXNDESCWBF_PMT_FUP ((uint32_t)0x00000200U) /*!< PTP Message Type: Follow_Up (all clock types) */ 781 #define ETH_DMARXNDESCWBF_PMT_DREQ ((uint32_t)0x00000300U) /*!< PTP Message Type: Delay_Req (all clock types) */ 782 #define ETH_DMARXNDESCWBF_PMT_DRESP ((uint32_t)0x00000400U) /*!< PTP Message Type: Delay_Resp (all clock types) */ 783 #define ETH_DMARXNDESCWBF_PMT_PDREQ ((uint32_t)0x00000500U) /*!< PTP Message Type: Pdelay_Req (in peer-to-peer transparent clock) */ 784 #define ETH_DMARXNDESCWBF_PMT_PDRESP ((uint32_t)0x00000600U) /*!< PTP Message Type: Pdelay_Resp (in peer-to-peer transparent clock) */ 785 #define ETH_DMARXNDESCWBF_PMT_PDRESPFUP ((uint32_t)0x00000700U) /*!< PTP Message Type: Pdelay_Resp_Follow_Up (in peer-to-peer transparent clock) */ 786 #define ETH_DMARXNDESCWBF_PMT_ANNOUNCE ((uint32_t)0x00000800U) /*!< PTP Message Type: Announce */ 787 #define ETH_DMARXNDESCWBF_PMT_MANAG ((uint32_t)0x00000900U) /*!< PTP Message Type: Management */ 788 #define ETH_DMARXNDESCWBF_PMT_SIGN ((uint32_t)0x00000A00U) /*!< PTP Message Type: Signaling */ 789 #define ETH_DMARXNDESCWBF_PMT_RESERVED ((uint32_t)0x00000F00U) /*!< PTP Message Type: PTP packet with Reserved message type */ 790 #define ETH_DMARXNDESCWBF_IPCE ((uint32_t)0x00000080U) /*!< IP Payload Error */ 791 #define ETH_DMARXNDESCWBF_IPCB ((uint32_t)0x00000040U) /*!< IP Checksum Bypassed */ 792 #define ETH_DMARXNDESCWBF_IPV6 ((uint32_t)0x00000020U) /*!< IPv6 header Present */ 793 #define ETH_DMARXNDESCWBF_IPV4 ((uint32_t)0x00000010U) /*!< IPv4 header Present */ 794 #define ETH_DMARXNDESCWBF_IPHE ((uint32_t)0x00000008U) /*!< IP Header Error */ 795 #define ETH_DMARXNDESCWBF_PT ((uint32_t)0x00000003U) /*!< Payload Type mask */ 796 #define ETH_DMARXNDESCWBF_PT_UNKNOWN ((uint32_t)0x00000000U) /*!< Payload Type: Unknown type or IP/AV payload not processed */ 797 #define ETH_DMARXNDESCWBF_PT_UDP ((uint32_t)0x00000001U) /*!< Payload Type: UDP */ 798 #define ETH_DMARXNDESCWBF_PT_TCP ((uint32_t)0x00000002U) /*!< Payload Type: TCP */ 799 #define ETH_DMARXNDESCWBF_PT_ICMP ((uint32_t)0x00000003U) /*!< Payload Type: ICMP */ 800 801 /** 802 * @brief Bit definition of Rx normal descriptor register 2 write back format 803 */ 804 #define ETH_DMARXNDESCWBF_L3L4FM ((uint32_t)0x20000000U) /*!< L3 and L4 Filter Number Matched: if reset filter 0 is matched , if set filter 1 is matched */ 805 #define ETH_DMARXNDESCWBF_L4FM ((uint32_t)0x10000000U) /*!< Layer 4 Filter Match */ 806 #define ETH_DMARXNDESCWBF_L3FM ((uint32_t)0x08000000U) /*!< Layer 3 Filter Match */ 807 #define ETH_DMARXNDESCWBF_MADRM ((uint32_t)0x07F80000U) /*!< MAC Address Match or Hash Value */ 808 #define ETH_DMARXNDESCWBF_HF ((uint32_t)0x00040000U) /*!< Hash Filter Status */ 809 #define ETH_DMARXNDESCWBF_DAF ((uint32_t)0x00020000U) /*!< Destination Address Filter Fail */ 810 #define ETH_DMARXNDESCWBF_SAF ((uint32_t)0x00010000U) /*!< SA Address Filter Fail */ 811 #define ETH_DMARXNDESCWBF_VF ((uint32_t)0x00008000U) /*!< VLAN Filter Status */ 812 #define ETH_DMARXNDESCWBF_ARPNR ((uint32_t)0x00000400U) /*!< ARP Reply Not Generated */ 813 814 815 /** 816 * @brief Bit definition of Rx normal descriptor register 3 write back format 817 */ 818 #define ETH_DMARXNDESCWBF_OWN ((uint32_t)0x80000000U) /*!< Own Bit */ 819 #define ETH_DMARXNDESCWBF_CTXT ((uint32_t)0x40000000U) /*!< Receive Context Descriptor */ 820 #define ETH_DMARXNDESCWBF_FD ((uint32_t)0x20000000U) /*!< First Descriptor */ 821 #define ETH_DMARXNDESCWBF_LD ((uint32_t)0x10000000U) /*!< Last Descriptor */ 822 #define ETH_DMARXNDESCWBF_RS2V ((uint32_t)0x08000000U) /*!< Receive Status RDES2 Valid */ 823 #define ETH_DMARXNDESCWBF_RS1V ((uint32_t)0x04000000U) /*!< Receive Status RDES1 Valid */ 824 #define ETH_DMARXNDESCWBF_RS0V ((uint32_t)0x02000000U) /*!< Receive Status RDES0 Valid */ 825 #define ETH_DMARXNDESCWBF_CE ((uint32_t)0x01000000U) /*!< CRC Error */ 826 #define ETH_DMARXNDESCWBF_GP ((uint32_t)0x00800000U) /*!< Giant Packet */ 827 #define ETH_DMARXNDESCWBF_RWT ((uint32_t)0x00400000U) /*!< Receive Watchdog Timeout */ 828 #define ETH_DMARXNDESCWBF_OE ((uint32_t)0x00200000U) /*!< Overflow Error */ 829 #define ETH_DMARXNDESCWBF_RE ((uint32_t)0x00100000U) /*!< Receive Error */ 830 #define ETH_DMARXNDESCWBF_DE ((uint32_t)0x00080000U) /*!< Dribble Bit Error */ 831 #define ETH_DMARXNDESCWBF_LT ((uint32_t)0x00070000U) /*!< Length/Type Field */ 832 #define ETH_DMARXNDESCWBF_LT_LP ((uint32_t)0x00000000U) /*!< The packet is a length packet */ 833 #define ETH_DMARXNDESCWBF_LT_TP ((uint32_t)0x00010000U) /*!< The packet is a type packet */ 834 #define ETH_DMARXNDESCWBF_LT_ARP ((uint32_t)0x00030000U) /*!< The packet is a ARP Request packet type */ 835 #define ETH_DMARXNDESCWBF_LT_VLAN ((uint32_t)0x00040000U) /*!< The packet is a type packet with VLAN Tag */ 836 #define ETH_DMARXNDESCWBF_LT_DVLAN ((uint32_t)0x00050000U) /*!< The packet is a type packet with Double VLAN Tag */ 837 #define ETH_DMARXNDESCWBF_LT_MAC ((uint32_t)0x00060000U) /*!< The packet is a MAC Control packet type */ 838 #define ETH_DMARXNDESCWBF_LT_OAM ((uint32_t)0x00070000U) /*!< The packet is a OAM packet type */ 839 #define ETH_DMARXNDESCWBF_ES ((uint32_t)0x00008000U) /*!< Error Summary */ 840 #define ETH_DMARXNDESCWBF_PL ((uint32_t)0x00007FFFU) /*!< Packet Length */ 841 842 /* 843 DMA Rx context Descriptor 844 --------------------------------------------------------------------------------------------------------------------- 845 RDES0 | Timestamp Low[31:0] | 846 --------------------------------------------------------------------------------------------------------------------- 847 RDES1 | Timestamp High[31:0] | 848 --------------------------------------------------------------------------------------------------------------------- 849 RDES2 | Reserved | 850 --------------------------------------------------------------------------------------------------------------------- 851 RDES3 | OWN(31) | CTXT(30) | Reserved[29:0] | 852 --------------------------------------------------------------------------------------------------------------------- 853 */ 854 855 /** 856 * @brief Bit definition of Rx context descriptor register 0 857 */ 858 #define ETH_DMARXCDESC_RTSL ((uint32_t)0xFFFFFFFFU) /*!< Receive Packet Timestamp Low */ 859 860 /** 861 * @brief Bit definition of Rx context descriptor register 1 862 */ 863 #define ETH_DMARXCDESC_RTSH ((uint32_t)0xFFFFFFFFU) /*!< Receive Packet Timestamp High */ 864 865 /** 866 * @brief Bit definition of Rx context descriptor register 3 867 */ 868 #define ETH_DMARXCDESC_OWN ((uint32_t)0x80000000U) /*!< Own Bit */ 869 #define ETH_DMARXCDESC_CTXT ((uint32_t)0x40000000U) /*!< Receive Context Descriptor */ 870 871 /** 872 * @} 873 */ 874 875 /** @defgroup ETH_Frame_settings ETH frame settings 876 * @{ 877 */ 878 #define ETH_MAX_PACKET_SIZE ((uint32_t)1528U) /*!< ETH_HEADER + 2*VLAN_TAG + MAX_ETH_PAYLOAD + ETH_CRC */ 879 #define ETH_HEADER ((uint32_t)14U) /*!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */ 880 #define ETH_CRC ((uint32_t)4U) /*!< Ethernet CRC */ 881 #define ETH_VLAN_TAG ((uint32_t)4U) /*!< optional 802.1q VLAN Tag */ 882 #define ETH_MIN_PAYLOAD ((uint32_t)46U) /*!< Minimum Ethernet payload size */ 883 #define ETH_MAX_PAYLOAD ((uint32_t)1500U) /*!< Maximum Ethernet payload size */ 884 #define ETH_JUMBO_FRAME_PAYLOAD ((uint32_t)9000U) /*!< Jumbo frame payload size */ 885 /** 886 * @} 887 */ 888 889 /** @defgroup ETH_Error_Code ETH Error Code 890 * @{ 891 */ 892 #define HAL_ETH_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ 893 #define HAL_ETH_ERROR_PARAM ((uint32_t)0x00000001U) /*!< Busy error */ 894 #define HAL_ETH_ERROR_BUSY ((uint32_t)0x00000002U) /*!< Parameter error */ 895 #define HAL_ETH_ERROR_TIMEOUT ((uint32_t)0x00000004U) /*!< Timeout error */ 896 #define HAL_ETH_ERROR_DMA ((uint32_t)0x00000008U) /*!< DMA transfer error */ 897 #define HAL_ETH_ERROR_MAC ((uint32_t)0x00000010U) /*!< MAC transfer error */ 898 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) 899 #define HAL_ETH_ERROR_INVALID_CALLBACK ((uint32_t)0x00000020U) /*!< Invalid Callback error */ 900 #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ 901 /** 902 * @} 903 */ 904 905 /** @defgroup ETH_Tx_Packet_Attributes ETH Tx Packet Attributes 906 * @{ 907 */ 908 #define ETH_TX_PACKETS_FEATURES_CSUM ((uint32_t)0x00000001U) 909 #define ETH_TX_PACKETS_FEATURES_SAIC ((uint32_t)0x00000002U) 910 #define ETH_TX_PACKETS_FEATURES_VLANTAG ((uint32_t)0x00000004U) 911 #define ETH_TX_PACKETS_FEATURES_INNERVLANTAG ((uint32_t)0x00000008U) 912 #define ETH_TX_PACKETS_FEATURES_TSO ((uint32_t)0x00000010U) 913 #define ETH_TX_PACKETS_FEATURES_CRCPAD ((uint32_t)0x00000020U) 914 /** 915 * @} 916 */ 917 918 /** @defgroup ETH_Tx_Packet_Source_Addr_Control ETH Tx Packet Source Addr Control 919 * @{ 920 */ 921 #define ETH_SRC_ADDR_CONTROL_DISABLE ETH_DMATXNDESCRF_SAIC_DISABLE 922 #define ETH_SRC_ADDR_INSERT ETH_DMATXNDESCRF_SAIC_INSERT 923 #define ETH_SRC_ADDR_REPLACE ETH_DMATXNDESCRF_SAIC_REPLACE 924 /** 925 * @} 926 */ 927 928 /** @defgroup ETH_Tx_Packet_CRC_Pad_Control ETH Tx Packet CRC Pad Control 929 * @{ 930 */ 931 #define ETH_CRC_PAD_DISABLE ETH_DMATXNDESCRF_CPC_DISABLE 932 #define ETH_CRC_PAD_INSERT ETH_DMATXNDESCRF_CPC_CRCPAD_INSERT 933 #define ETH_CRC_INSERT ETH_DMATXNDESCRF_CPC_CRC_INSERT 934 #define ETH_CRC_REPLACE ETH_DMATXNDESCRF_CPC_CRC_REPLACE 935 /** 936 * @} 937 */ 938 939 /** @defgroup ETH_Tx_Packet_Checksum_Control ETH Tx Packet Checksum Control 940 * @{ 941 */ 942 #define ETH_CHECKSUM_DISABLE ETH_DMATXNDESCRF_CIC_DISABLE 943 #define ETH_CHECKSUM_IPHDR_INSERT ETH_DMATXNDESCRF_CIC_IPHDR_INSERT 944 #define ETH_CHECKSUM_IPHDR_PAYLOAD_INSERT ETH_DMATXNDESCRF_CIC_IPHDR_PAYLOAD_INSERT 945 #define ETH_CHECKSUM_IPHDR_PAYLOAD_INSERT_PHDR_CALC ETH_DMATXNDESCRF_CIC_IPHDR_PAYLOAD_INSERT_PHDR_CALC 946 /** 947 * @} 948 */ 949 950 /** @defgroup ETH_Tx_Packet_VLAN_Control ETH Tx Packet VLAN Control 951 * @{ 952 */ 953 #define ETH_VLAN_DISABLE ETH_DMATXNDESCRF_VTIR_DISABLE 954 #define ETH_VLAN_REMOVE ETH_DMATXNDESCRF_VTIR_REMOVE 955 #define ETH_VLAN_INSERT ETH_DMATXNDESCRF_VTIR_INSERT 956 #define ETH_VLAN_REPLACE ETH_DMATXNDESCRF_VTIR_REPLACE 957 /** 958 * @} 959 */ 960 961 /** @defgroup ETH_Tx_Packet_Inner_VLAN_Control ETH Tx Packet Inner VLAN Control 962 * @{ 963 */ 964 #define ETH_INNER_VLAN_DISABLE ETH_DMATXCDESC_IVTIR_DISABLE 965 #define ETH_INNER_VLAN_REMOVE ETH_DMATXCDESC_IVTIR_REMOVE 966 #define ETH_INNER_VLAN_INSERT ETH_DMATXCDESC_IVTIR_INSERT 967 #define ETH_INNER_VLAN_REPLACE ETH_DMATXCDESC_IVTIR_REPLACE 968 /** 969 * @} 970 */ 971 972 /** @defgroup ETH_Rx_Checksum_Status ETH Rx Checksum Status 973 * @{ 974 */ 975 #define ETH_CHECKSUM_BYPASSED ETH_DMARXNDESCWBF_IPCB 976 #define ETH_CHECKSUM_IP_HEADER_ERROR ETH_DMARXNDESCWBF_IPHE 977 #define ETH_CHECKSUM_IP_PAYLOAD_ERROR ETH_DMARXNDESCWBF_IPCE 978 /** 979 * @} 980 */ 981 982 /** @defgroup ETH_Rx_IP_Header_Type ETH Rx IP Header Type 983 * @{ 984 */ 985 #define ETH_IP_HEADER_IPV4 ETH_DMARXNDESCWBF_IPV4 986 #define ETH_IP_HEADER_IPV6 ETH_DMARXNDESCWBF_IPV6 987 /** 988 * @} 989 */ 990 991 /** @defgroup ETH_Rx_Payload_Type ETH Rx Payload Type 992 * @{ 993 */ 994 #define ETH_IP_PAYLOAD_UNKNOWN ETH_DMARXNDESCWBF_PT_UNKNOWN 995 #define ETH_IP_PAYLOAD_UDP ETH_DMARXNDESCWBF_PT_UDP 996 #define ETH_IP_PAYLOAD_TCP ETH_DMARXNDESCWBF_PT_TCP 997 #define ETH_IP_PAYLOAD_ICMPN ETH_DMARXNDESCWBF_PT_ICMP 998 /** 999 * @} 1000 */ 1001 1002 /** @defgroup ETH_Rx_MAC_Filter_Status ETH Rx MAC Filter Status 1003 * @{ 1004 */ 1005 #define ETH_HASH_FILTER_PASS ETH_DMARXNDESCWBF_HF 1006 #define ETH_VLAN_FILTER_PASS ETH_DMARXNDESCWBF_VF 1007 #define ETH_DEST_ADDRESS_FAIL ETH_DMARXNDESCWBF_DAF 1008 #define ETH_SOURCE_ADDRESS_FAIL ETH_DMARXNDESCWBF_SAF 1009 /** 1010 * @} 1011 */ 1012 1013 /** @defgroup ETH_Rx_L3_Filter_Status ETH Rx L3 Filter Status 1014 * @{ 1015 */ 1016 #define ETH_L3_FILTER0_MATCH ETH_DMARXNDESCWBF_L3FM 1017 #define ETH_L3_FILTER1_MATCH (ETH_DMARXNDESCWBF_L3FM | ETH_DMARXNDESCWBF_L3L4FM) 1018 /** 1019 * @} 1020 */ 1021 1022 /** @defgroup ETH_Rx_L4_Filter_Status ETH Rx L4 Filter Status 1023 * @{ 1024 */ 1025 #define ETH_L4_FILTER0_MATCH ETH_DMARXNDESCWBF_L4FM 1026 #define ETH_L4_FILTER1_MATCH (ETH_DMARXNDESCWBF_L4FM | ETH_DMARXNDESCWBF_L3L4FM) 1027 /** 1028 * @} 1029 */ 1030 1031 /** @defgroup ETH_Rx_Error_Code ETH Rx Error Code 1032 * @{ 1033 */ 1034 #define ETH_DRIBBLE_BIT_ERROR ETH_DMARXNDESCWBF_DE 1035 #define ETH_RECEIVE_ERROR ETH_DMARXNDESCWBF_RE 1036 #define ETH_RECEIVE_OVERFLOW ETH_DMARXNDESCWBF_OE 1037 #define ETH_WATCHDOG_TIMEOUT ETH_DMARXNDESCWBF_RWT 1038 #define ETH_GIANT_PACKET ETH_DMARXNDESCWBF_GP 1039 #define ETH_CRC_ERROR ETH_DMARXNDESCWBF_CE 1040 /** 1041 * @} 1042 */ 1043 1044 /** @defgroup ETH_DMA_Arbitration ETH DMA Arbitration 1045 * @{ 1046 */ 1047 #define ETH_DMAARBITRATION_RX ETH_DMAMR_DA 1048 #define ETH_DMAARBITRATION_RX1_TX1 ((uint32_t)0x00000000U) 1049 #define ETH_DMAARBITRATION_RX2_TX1 ETH_DMAMR_PR_2_1 1050 #define ETH_DMAARBITRATION_RX3_TX1 ETH_DMAMR_PR_3_1 1051 #define ETH_DMAARBITRATION_RX4_TX1 ETH_DMAMR_PR_4_1 1052 #define ETH_DMAARBITRATION_RX5_TX1 ETH_DMAMR_PR_5_1 1053 #define ETH_DMAARBITRATION_RX6_TX1 ETH_DMAMR_PR_6_1 1054 #define ETH_DMAARBITRATION_RX7_TX1 ETH_DMAMR_PR_7_1 1055 #define ETH_DMAARBITRATION_RX8_TX1 ETH_DMAMR_PR_8_1 1056 #define ETH_DMAARBITRATION_TX (ETH_DMAMR_TXPR | ETH_DMAMR_DA) 1057 #define ETH_DMAARBITRATION_TX1_RX1 ((uint32_t)0x00000000U) 1058 #define ETH_DMAARBITRATION_TX2_RX1 (ETH_DMAMR_TXPR | ETH_DMAMR_PR_2_1) 1059 #define ETH_DMAARBITRATION_TX3_RX1 (ETH_DMAMR_TXPR | ETH_DMAMR_PR_3_1) 1060 #define ETH_DMAARBITRATION_TX4_RX1 (ETH_DMAMR_TXPR | ETH_DMAMR_PR_4_1) 1061 #define ETH_DMAARBITRATION_TX5_RX1 (ETH_DMAMR_TXPR | ETH_DMAMR_PR_5_1) 1062 #define ETH_DMAARBITRATION_TX6_RX1 (ETH_DMAMR_TXPR | ETH_DMAMR_PR_6_1) 1063 #define ETH_DMAARBITRATION_TX7_RX1 (ETH_DMAMR_TXPR | ETH_DMAMR_PR_7_1) 1064 #define ETH_DMAARBITRATION_TX8_RX1 (ETH_DMAMR_TXPR | ETH_DMAMR_PR_8_1) 1065 /** 1066 * @} 1067 */ 1068 1069 /** @defgroup ETH_Burst_Mode ETH Burst Mode 1070 * @{ 1071 */ 1072 #define ETH_BURSTLENGTH_FIXED ETH_DMASBMR_FB 1073 #define ETH_BURSTLENGTH_MIXED ETH_DMASBMR_MB 1074 #define ETH_BURSTLENGTH_UNSPECIFIED ((uint32_t)0x00000000U) 1075 /** 1076 * @} 1077 */ 1078 1079 /** @defgroup ETH_Tx_DMA_Burst_Length ETH Tx DMA Burst Length 1080 * @{ 1081 */ 1082 #define ETH_TXDMABURSTLENGTH_1BEAT ETH_DMACTCR_TPBL_1PBL 1083 #define ETH_TXDMABURSTLENGTH_2BEAT ETH_DMACTCR_TPBL_2PBL 1084 #define ETH_TXDMABURSTLENGTH_4BEAT ETH_DMACTCR_TPBL_4PBL 1085 #define ETH_TXDMABURSTLENGTH_8BEAT ETH_DMACTCR_TPBL_8PBL 1086 #define ETH_TXDMABURSTLENGTH_16BEAT ETH_DMACTCR_TPBL_16PBL 1087 #define ETH_TXDMABURSTLENGTH_32BEAT ETH_DMACTCR_TPBL_32PBL 1088 /** 1089 * @} 1090 */ 1091 1092 /** @defgroup ETH_Rx_DMA_Burst_Length ETH Rx DMA Burst Length 1093 * @{ 1094 */ 1095 #define ETH_RXDMABURSTLENGTH_1BEAT ETH_DMACRCR_RPBL_1PBL 1096 #define ETH_RXDMABURSTLENGTH_2BEAT ETH_DMACRCR_RPBL_2PBL 1097 #define ETH_RXDMABURSTLENGTH_4BEAT ETH_DMACRCR_RPBL_4PBL 1098 #define ETH_RXDMABURSTLENGTH_8BEAT ETH_DMACRCR_RPBL_8PBL 1099 #define ETH_RXDMABURSTLENGTH_16BEAT ETH_DMACRCR_RPBL_16PBL 1100 #define ETH_RXDMABURSTLENGTH_32BEAT ETH_DMACRCR_RPBL_32PBL 1101 /** 1102 * @} 1103 */ 1104 1105 /** @defgroup ETH_DMA_Interrupts ETH DMA Interrupts 1106 * @{ 1107 */ 1108 #define ETH_DMA_NORMAL_IT ETH_DMACIER_NIE 1109 #define ETH_DMA_ABNORMAL_IT ETH_DMACIER_AIE 1110 #define ETH_DMA_CONTEXT_DESC_ERROR_IT ETH_DMACIER_CDEE 1111 #define ETH_DMA_FATAL_BUS_ERROR_IT ETH_DMACIER_FBEE 1112 #define ETH_DMA_EARLY_RX_IT ETH_DMACIER_ERIE 1113 #define ETH_DMA_EARLY_TX_IT ETH_DMACIER_ETIE 1114 #define ETH_DMA_RX_WATCHDOG_TIMEOUT_IT ETH_DMACIER_RWTE 1115 #define ETH_DMA_RX_PROCESS_STOPPED_IT ETH_DMACIER_RSE 1116 #define ETH_DMA_RX_BUFFER_UNAVAILABLE_IT ETH_DMACIER_RBUE 1117 #define ETH_DMA_RX_IT ETH_DMACIER_RIE 1118 #define ETH_DMA_TX_BUFFER_UNAVAILABLE_IT ETH_DMACIER_TBUE 1119 #define ETH_DMA_TX_PROCESS_STOPPED_IT ETH_DMACIER_TXSE 1120 #define ETH_DMA_TX_IT ETH_DMACIER_TIE 1121 /** 1122 * @} 1123 */ 1124 1125 /** @defgroup ETH_DMA_Status_Flags ETH DMA Status Flags 1126 * @{ 1127 */ 1128 #define ETH_DMA_RX_NO_ERROR_FLAG ((uint32_t)0x00000000U) 1129 #define ETH_DMA_RX_DESC_READ_ERROR_FLAG (ETH_DMACSR_REB_BIT_2 | ETH_DMACSR_REB_BIT_1 | ETH_DMACSR_REB_BIT_0) 1130 #define ETH_DMA_RX_DESC_WRITE_ERROR_FLAG (ETH_DMACSR_REB_BIT_2 | ETH_DMACSR_REB_BIT_1) 1131 #define ETH_DMA_RX_BUFFER_READ_ERROR_FLAG (ETH_DMACSR_REB_BIT_2 | ETH_DMACSR_REB_BIT_0) 1132 #define ETH_DMA_RX_BUFFER_WRITE_ERROR_FLAG ETH_DMACSR_REB_BIT_2 1133 #define ETH_DMA_TX_NO_ERROR_FLAG ((uint32_t)0x00000000U) 1134 #define ETH_DMA_TX_DESC_READ_ERROR_FLAG (ETH_DMACSR_TEB_BIT_2 | ETH_DMACSR_TEB_BIT_1 | ETH_DMACSR_TEB_BIT_0) 1135 #define ETH_DMA_TX_DESC_WRITE_ERROR_FLAG (ETH_DMACSR_TEB_BIT_2 | ETH_DMACSR_TEB_BIT_1) 1136 #define ETH_DMA_TX_BUFFER_READ_ERROR_FLAG (ETH_DMACSR_TEB_BIT_2 | ETH_DMACSR_TEB_BIT_0) 1137 #define ETH_DMA_TX_BUFFER_WRITE_ERROR_FLAG ETH_DMACSR_TEB_BIT_2 1138 #define ETH_DMA_CONTEXT_DESC_ERROR_FLAG ETH_DMACSR_CDE 1139 #define ETH_DMA_FATAL_BUS_ERROR_FLAG ETH_DMACSR_FBE 1140 #define ETH_DMA_EARLY_TX_IT_FLAG ETH_DMACSR_ERI 1141 #define ETH_DMA_RX_WATCHDOG_TIMEOUT_FLAG ETH_DMACSR_RWT 1142 #define ETH_DMA_RX_PROCESS_STOPPED_FLAG ETH_DMACSR_RPS 1143 #define ETH_DMA_RX_BUFFER_UNAVAILABLE_FLAG ETH_DMACSR_RBU 1144 #define ETH_DMA_TX_PROCESS_STOPPED_FLAG ETH_DMACSR_TPS 1145 /** 1146 * @} 1147 */ 1148 1149 /** @defgroup ETH_Transmit_Mode ETH Transmit Mode 1150 * @{ 1151 */ 1152 #define ETH_TRANSMITSTOREFORWARD ETH_MTLTQOMR_TSF 1153 #define ETH_TRANSMITTHRESHOLD_32 ETH_MTLTQOMR_TTC_32BITS 1154 #define ETH_TRANSMITTHRESHOLD_64 ETH_MTLTQOMR_TTC_64BITS 1155 #define ETH_TRANSMITTHRESHOLD_96 ETH_MTLTQOMR_TTC_96BITS 1156 #define ETH_TRANSMITTHRESHOLD_128 ETH_MTLTQOMR_TTC_128BITS 1157 #define ETH_TRANSMITTHRESHOLD_192 ETH_MTLTQOMR_TTC_192BITS 1158 #define ETH_TRANSMITTHRESHOLD_256 ETH_MTLTQOMR_TTC_256BITS 1159 #define ETH_TRANSMITTHRESHOLD_384 ETH_MTLTQOMR_TTC_384BITS 1160 #define ETH_TRANSMITTHRESHOLD_512 ETH_MTLTQOMR_TTC_512BITS 1161 /** 1162 * @} 1163 */ 1164 1165 /** @defgroup ETH_Receive_Mode ETH Receive Mode 1166 * @{ 1167 */ 1168 #define ETH_RECEIVESTOREFORWARD ETH_MTLRQOMR_RSF 1169 #define ETH_RECEIVETHRESHOLD8_64 ETH_MTLRQOMR_RTC_64BITS 1170 #define ETH_RECEIVETHRESHOLD8_32 ETH_MTLRQOMR_RTC_32BITS 1171 #define ETH_RECEIVETHRESHOLD8_96 ETH_MTLRQOMR_RTC_96BITS 1172 #define ETH_RECEIVETHRESHOLD8_128 ETH_MTLRQOMR_RTC_128BITS 1173 /** 1174 * @} 1175 */ 1176 1177 /** @defgroup ETH_Pause_Low_Threshold ETH Pause Low Threshold 1178 * @{ 1179 */ 1180 #define ETH_PAUSELOWTHRESHOLD_MINUS_4 ETH_MACTFCR_PLT_MINUS4 1181 #define ETH_PAUSELOWTHRESHOLD_MINUS_28 ETH_MACTFCR_PLT_MINUS28 1182 #define ETH_PAUSELOWTHRESHOLD_MINUS_36 ETH_MACTFCR_PLT_MINUS36 1183 #define ETH_PAUSELOWTHRESHOLD_MINUS_144 ETH_MACTFCR_PLT_MINUS144 1184 #define ETH_PAUSELOWTHRESHOLD_MINUS_256 ETH_MACTFCR_PLT_MINUS256 1185 #define ETH_PAUSELOWTHRESHOLD_MINUS_512 ETH_MACTFCR_PLT_MINUS512 1186 /** 1187 * @} 1188 */ 1189 1190 /** @defgroup ETH_Watchdog_Timeout ETH Watchdog Timeout 1191 * @{ 1192 */ 1193 #define ETH_WATCHDOGTIMEOUT_2KB ETH_MACWTR_WTO_2KB 1194 #define ETH_WATCHDOGTIMEOUT_3KB ETH_MACWTR_WTO_3KB 1195 #define ETH_WATCHDOGTIMEOUT_4KB ETH_MACWTR_WTO_4KB 1196 #define ETH_WATCHDOGTIMEOUT_5KB ETH_MACWTR_WTO_5KB 1197 #define ETH_WATCHDOGTIMEOUT_6KB ETH_MACWTR_WTO_6KB 1198 #define ETH_WATCHDOGTIMEOUT_7KB ETH_MACWTR_WTO_7KB 1199 #define ETH_WATCHDOGTIMEOUT_8KB ETH_MACWTR_WTO_8KB 1200 #define ETH_WATCHDOGTIMEOUT_9KB ETH_MACWTR_WTO_9KB 1201 #define ETH_WATCHDOGTIMEOUT_10KB ETH_MACWTR_WTO_10KB 1202 #define ETH_WATCHDOGTIMEOUT_11KB ETH_MACWTR_WTO_12KB 1203 #define ETH_WATCHDOGTIMEOUT_12KB ETH_MACWTR_WTO_12KB 1204 #define ETH_WATCHDOGTIMEOUT_13KB ETH_MACWTR_WTO_13KB 1205 #define ETH_WATCHDOGTIMEOUT_14KB ETH_MACWTR_WTO_14KB 1206 #define ETH_WATCHDOGTIMEOUT_15KB ETH_MACWTR_WTO_15KB 1207 #define ETH_WATCHDOGTIMEOUT_16KB ETH_MACWTR_WTO_16KB 1208 /** 1209 * @} 1210 */ 1211 1212 /** @defgroup ETH_Inter_Packet_Gap ETH Inter Packet Gap 1213 * @{ 1214 */ 1215 #define ETH_INTERPACKETGAP_96BIT ETH_MACCR_IPG_96BIT 1216 #define ETH_INTERPACKETGAP_88BIT ETH_MACCR_IPG_88BIT 1217 #define ETH_INTERPACKETGAP_80BIT ETH_MACCR_IPG_80BIT 1218 #define ETH_INTERPACKETGAP_72BIT ETH_MACCR_IPG_72BIT 1219 #define ETH_INTERPACKETGAP_64BIT ETH_MACCR_IPG_64BIT 1220 #define ETH_INTERPACKETGAP_56BIT ETH_MACCR_IPG_56BIT 1221 #define ETH_INTERPACKETGAP_48BIT ETH_MACCR_IPG_48BIT 1222 #define ETH_INTERPACKETGAP_40BIT ETH_MACCR_IPG_40BIT 1223 /** 1224 * @} 1225 */ 1226 1227 /** @defgroup ETH_Speed ETH Speed 1228 * @{ 1229 */ 1230 #define ETH_SPEED_10M ((uint32_t)0x00000000U) 1231 #define ETH_SPEED_100M ETH_MACCR_FES 1232 /** 1233 * @} 1234 */ 1235 1236 /** @defgroup ETH_Duplex_Mode ETH Duplex Mode 1237 * @{ 1238 */ 1239 #define ETH_FULLDUPLEX_MODE ETH_MACCR_DM 1240 #define ETH_HALFDUPLEX_MODE ((uint32_t)0x00000000U) 1241 /** 1242 * @} 1243 */ 1244 1245 /** @defgroup ETH_Back_Off_Limit ETH Back Off Limit 1246 * @{ 1247 */ 1248 #define ETH_BACKOFFLIMIT_10 ETH_MACCR_BL_10 1249 #define ETH_BACKOFFLIMIT_8 ETH_MACCR_BL_8 1250 #define ETH_BACKOFFLIMIT_4 ETH_MACCR_BL_4 1251 #define ETH_BACKOFFLIMIT_1 ETH_MACCR_BL_1 1252 /** 1253 * @} 1254 */ 1255 1256 /** @defgroup ETH_Preamble_Length ETH Preamble Length 1257 * @{ 1258 */ 1259 #define ETH_PREAMBLELENGTH_7 ETH_MACCR_PRELEN_7 1260 #define ETH_PREAMBLELENGTH_5 ETH_MACCR_PRELEN_5 1261 #define ETH_PREAMBLELENGTH_3 ETH_MACCR_PRELEN_3 1262 /** 1263 * @} 1264 */ 1265 1266 /** @defgroup ETH_Source_Addr_Control ETH Source Addr Control 1267 * @{ 1268 */ 1269 #define ETH_SOURCEADDRESS_DISABLE ((uint32_t)0x00000000U) 1270 #define ETH_SOURCEADDRESS_INSERT_ADDR0 ETH_MACCR_SARC_INSADDR0 1271 #define ETH_SOURCEADDRESS_INSERT_ADDR1 ETH_MACCR_SARC_INSADDR1 1272 #define ETH_SOURCEADDRESS_REPLACE_ADDR0 ETH_MACCR_SARC_REPADDR0 1273 #define ETH_SOURCEADDRESS_REPLACE_ADDR1 ETH_MACCR_SARC_REPADDR1 1274 /** 1275 * @} 1276 */ 1277 1278 /** @defgroup ETH_Control_Packets_Filter ETH Control Packets Filter 1279 * @{ 1280 */ 1281 #define ETH_CTRLPACKETS_BLOCK_ALL ETH_MACPFR_PCF_BLOCKALL 1282 #define ETH_CTRLPACKETS_FORWARD_ALL_EXCEPT_PA ETH_MACPFR_PCF_FORWARDALLEXCEPTPA 1283 #define ETH_CTRLPACKETS_FORWARD_ALL ETH_MACPFR_PCF_FORWARDALL 1284 #define ETH_CTRLPACKETS_FORWARD_PASSED_ADDR_FILTER ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER 1285 /** 1286 * @} 1287 */ 1288 1289 /** @defgroup ETH_VLAN_Tag_Comparison ETH VLAN Tag Comparison 1290 * @{ 1291 */ 1292 #define ETH_VLANTAGCOMPARISON_16BIT ((uint32_t)0x00000000U) 1293 #define ETH_VLANTAGCOMPARISON_12BIT ETH_MACVTR_ETV 1294 /** 1295 * @} 1296 */ 1297 1298 /** @defgroup ETH_MAC_addresses ETH MAC addresses 1299 * @{ 1300 */ 1301 #define ETH_MAC_ADDRESS0 ((uint32_t)0x00000000U) 1302 #define ETH_MAC_ADDRESS1 ((uint32_t)0x00000008U) 1303 #define ETH_MAC_ADDRESS2 ((uint32_t)0x00000010U) 1304 #define ETH_MAC_ADDRESS3 ((uint32_t)0x00000018U) 1305 /** 1306 * @} 1307 */ 1308 1309 /** @defgroup ETH_MAC_Interrupts ETH MAC Interrupts 1310 * @{ 1311 */ 1312 #define ETH_MAC_RX_STATUS_IT ETH_MACIER_RXSTSIE 1313 #define ETH_MAC_TX_STATUS_IT ETH_MACIER_TXSTSIE 1314 #define ETH_MAC_TIMESTAMP_IT ETH_MACIER_TSIE 1315 #define ETH_MAC_LPI_IT ETH_MACIER_LPIIE 1316 #define ETH_MAC_PMT_IT ETH_MACIER_PMTIE 1317 #define ETH_MAC_PHY_IT ETH_MACIER_PHYIE 1318 /** 1319 * @} 1320 */ 1321 1322 /** @defgroup ETH_MAC_Wake_Up_Event ETH MAC Wake Up Event 1323 * @{ 1324 */ 1325 #define ETH_WAKEUP_PACKET_RECIEVED ETH_MACPCSR_RWKPRCVD 1326 #define ETH_MAGIC_PACKET_RECIEVED ETH_MACPCSR_MGKPRCVD 1327 /** 1328 * @} 1329 */ 1330 1331 /** @defgroup ETH_MAC_Rx_Tx_Status ETH MAC Rx Tx Status 1332 * @{ 1333 */ 1334 #define ETH_RECEIVE_WATCHDOG_TIMEOUT ETH_MACRXTXSR_RWT 1335 #define ETH_EXECESSIVE_COLLISIONS ETH_MACRXTXSR_EXCOL 1336 #define ETH_LATE_COLLISIONS ETH_MACRXTXSR_LCOL 1337 #define ETH_EXECESSIVE_DEFERRAL ETH_MACRXTXSR_EXDEF 1338 #define ETH_LOSS_OF_CARRIER ETH_MACRXTXSR_LCARR 1339 #define ETH_NO_CARRIER ETH_MACRXTXSR_NCARR 1340 #define ETH_TRANSMIT_JABBR_TIMEOUT ETH_MACRXTXSR_TJT 1341 /** 1342 * @} 1343 */ 1344 1345 /** @defgroup HAL_ETH_StateTypeDef ETH States 1346 * @{ 1347 */ 1348 #define HAL_ETH_STATE_RESET ((uint32_t)0x00000000U) /*!< Peripheral not yet Initialized or disabled */ 1349 #define HAL_ETH_STATE_READY ((uint32_t)0x00000010U) /*!< Peripheral Communication started */ 1350 #define HAL_ETH_STATE_BUSY ((uint32_t)0x00000023U) /*!< an internal process is ongoing */ 1351 #define HAL_ETH_STATE_BUSY_TX ((uint32_t)0x00000021U) /*!< Transmission process is ongoing */ 1352 #define HAL_ETH_STATE_BUSY_RX ((uint32_t)0x00000022U) /*!< Reception process is ongoing */ 1353 #define HAL_ETH_STATE_ERROR ((uint32_t)0x000000E0U) /*!< Error State */ 1354 /** 1355 * @} 1356 */ 1357 /** 1358 * @} 1359 */ 1360 1361 /* Exported macro ------------------------------------------------------------*/ 1362 /** @defgroup ETH_Exported_Macros ETH Exported Macros 1363 * @{ 1364 */ 1365 1366 /** @brief Reset ETH handle state 1367 * @param __HANDLE__: specifies the ETH handle. 1368 * @retval None 1369 */ 1370 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) 1371 #define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__) do{ \ 1372 (__HANDLE__)->gState = HAL_ETH_STATE_RESET; \ 1373 (__HANDLE__)->RxState = HAL_ETH_STATE_RESET; \ 1374 (__HANDLE__)->MspInitCallback = NULL; \ 1375 (__HANDLE__)->MspDeInitCallback = NULL; \ 1376 } while(0) 1377 #else 1378 #define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__) do{ \ 1379 (__HANDLE__)->gState = HAL_ETH_STATE_RESET; \ 1380 (__HANDLE__)->RxState = HAL_ETH_STATE_RESET; \ 1381 } while(0) 1382 #endif /*USE_HAL_ETH_REGISTER_CALLBACKS */ 1383 1384 /** 1385 * @brief Enables the specified ETHERNET DMA interrupts. 1386 * @param __HANDLE__ : ETH Handle 1387 * @param __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be 1388 * enabled @ref ETH_DMA_Interrupts 1389 * @retval None 1390 */ 1391 #define __HAL_ETH_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMACIER |= (__INTERRUPT__)) 1392 1393 /** 1394 * @brief Disables the specified ETHERNET DMA interrupts. 1395 * @param __HANDLE__ : ETH Handle 1396 * @param __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be 1397 * disabled. @ref ETH_DMA_Interrupts 1398 * @retval None 1399 */ 1400 #define __HAL_ETH_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMACIER &= ~(__INTERRUPT__)) 1401 1402 /** 1403 * @brief Gets the ETHERNET DMA IT source enabled or disabled. 1404 * @param __HANDLE__ : ETH Handle 1405 * @param __INTERRUPT__: specifies the interrupt source to get . @ref ETH_DMA_Interrupts 1406 * @retval The ETH DMA IT Source enabled or disabled 1407 */ 1408 #define __HAL_ETH_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->DMACIER & (__INTERRUPT__)) == (__INTERRUPT__)) 1409 1410 /** 1411 * @brief Gets the ETHERNET DMA IT pending bit. 1412 * @param __HANDLE__ : ETH Handle 1413 * @param __INTERRUPT__: specifies the interrupt source to get . @ref ETH_DMA_Interrupts 1414 * @retval The state of ETH DMA IT (SET or RESET) 1415 */ 1416 #define __HAL_ETH_DMA_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->DMACSR & (__INTERRUPT__)) == (__INTERRUPT__)) 1417 1418 /** 1419 * @brief Clears the ETHERNET DMA IT pending bit. 1420 * @param __HANDLE__ : ETH Handle 1421 * @param __INTERRUPT__: specifies the interrupt pending bit to clear. @ref ETH_DMA_Interrupts 1422 * @retval None 1423 */ 1424 #define __HAL_ETH_DMA_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMACSR = (__INTERRUPT__)) 1425 1426 /** 1427 * @brief Checks whether the specified ETHERNET DMA flag is set or not. 1428 * @param __HANDLE__: ETH Handle 1429 * @param __FLAG__: specifies the flag to check. @ref ETH_DMA_Status_Flags 1430 * @retval The state of ETH DMA FLAG (SET or RESET). 1431 */ 1432 #define __HAL_ETH_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->DMACSR &( __FLAG__)) == ( __FLAG__)) 1433 1434 /** 1435 * @brief Clears the specified ETHERNET DMA flag. 1436 * @param __HANDLE__: ETH Handle 1437 * @param __FLAG__: specifies the flag to check. @ref ETH_DMA_Status_Flags 1438 * @retval The state of ETH DMA FLAG (SET or RESET). 1439 */ 1440 #define __HAL_ETH_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->DMACSR = ( __FLAG__)) 1441 1442 /** 1443 * @brief Enables the specified ETHERNET MAC interrupts. 1444 * @param __HANDLE__ : ETH Handle 1445 * @param __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be 1446 * enabled @ref ETH_MAC_Interrupts 1447 * @retval None 1448 */ 1449 #define __HAL_ETH_MAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIER |= (__INTERRUPT__)) 1450 1451 /** 1452 * @brief Disables the specified ETHERNET MAC interrupts. 1453 * @param __HANDLE__ : ETH Handle 1454 * @param __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be 1455 * enabled @ref ETH_MAC_Interrupts 1456 * @retval None 1457 */ 1458 #define __HAL_ETH_MAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIER &= ~(__INTERRUPT__)) 1459 1460 /** 1461 * @brief Checks whether the specified ETHERNET MAC flag is set or not. 1462 * @param __HANDLE__: ETH Handle 1463 * @param __INTERRUPT__: specifies the flag to check. @ref ETH_MAC_Interrupts 1464 * @retval The state of ETH MAC IT (SET or RESET). 1465 */ 1466 #define __HAL_ETH_MAC_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->MACISR &( __INTERRUPT__)) == ( __INTERRUPT__)) 1467 1468 /*!< External interrupt line 86 Connected to the ETH wakeup EXTI Line */ 1469 #define ETH_WAKEUP_EXTI_LINE ((uint32_t)0x00400000U) /* !< 86 - 64 = 22 */ 1470 1471 /** 1472 * @brief Enable the ETH WAKEUP Exti Line. 1473 * @param __EXTI_LINE__: specifies the ETH WAKEUP Exti sources to be enabled. 1474 * @arg ETH_WAKEUP_EXTI_LINE 1475 * @retval None. 1476 */ 1477 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_IT(__EXTI_LINE__) (EXTI_D1->IMR3 |= (__EXTI_LINE__)) 1478 1479 /** 1480 * @brief checks whether the specified ETH WAKEUP Exti interrupt flag is set or not. 1481 * @param __EXTI_LINE__: specifies the ETH WAKEUP Exti sources to be cleared. 1482 * @arg ETH_WAKEUP_EXTI_LINE 1483 * @retval EXTI ETH WAKEUP Line Status. 1484 */ 1485 #define __HAL_ETH_WAKEUP_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI_D1->PR3 & (__EXTI_LINE__)) 1486 1487 /** 1488 * @brief Clear the ETH WAKEUP Exti flag. 1489 * @param __EXTI_LINE__: specifies the ETH WAKEUP Exti sources to be cleared. 1490 * @arg ETH_WAKEUP_EXTI_LINE 1491 * @retval None. 1492 */ 1493 #define __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI_D1->PR3 = (__EXTI_LINE__)) 1494 1495 #if defined(DUAL_CORE) 1496 /** 1497 * @brief Enable the ETH WAKEUP Exti Line by Core2. 1498 * @param __EXTI_LINE__: specifies the ETH WAKEUP Exti sources to be enabled. 1499 * @arg ETH_WAKEUP_EXTI_LINE 1500 * @retval None. 1501 */ 1502 #define __HAL_ETH_WAKEUP_EXTID2_ENABLE_IT(__EXTI_LINE__) (EXTI_D2->IMR3 |= (__EXTI_LINE__)) 1503 1504 /** 1505 * @brief checks whether the specified ETH WAKEUP Exti interrupt flag is set or not. 1506 * @param __EXTI_LINE__: specifies the ETH WAKEUP Exti sources to be cleared. 1507 * @arg ETH_WAKEUP_EXTI_LINE 1508 * @retval EXTI ETH WAKEUP Line Status. 1509 */ 1510 #define __HAL_ETH_WAKEUP_EXTID2_GET_FLAG(__EXTI_LINE__) (EXTI_D2->PR3 & (__EXTI_LINE__)) 1511 1512 /** 1513 * @brief Clear the ETH WAKEUP Exti flag. 1514 * @param __EXTI_LINE__: specifies the ETH WAKEUP Exti sources to be cleared. 1515 * @arg ETH_WAKEUP_EXTI_LINE 1516 * @retval None. 1517 */ 1518 #define __HAL_ETH_WAKEUP_EXTID2_CLEAR_FLAG(__EXTI_LINE__) (EXTI_D2->PR3 = (__EXTI_LINE__)) 1519 #endif 1520 1521 /** 1522 * @brief enable rising edge interrupt on selected EXTI line. 1523 * @param __EXTI_LINE__: specifies the ETH WAKEUP EXTI sources to be disabled. 1524 * @arg ETH_WAKEUP_EXTI_LINE 1525 * @retval None 1526 */ 1527 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE(__EXTI_LINE__) (EXTI->FTSR3 &= ~(__EXTI_LINE__)); \ 1528 (EXTI->RTSR3 |= (__EXTI_LINE__)) 1529 1530 /** 1531 * @brief enable falling edge interrupt on selected EXTI line. 1532 * @param __EXTI_LINE__: specifies the ETH WAKEUP EXTI sources to be disabled. 1533 * @arg ETH_WAKEUP_EXTI_LINE 1534 * @retval None 1535 */ 1536 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE(__EXTI_LINE__) (EXTI->RTSR3 &= ~(__EXTI_LINE__));\ 1537 (EXTI->FTSR3 |= (__EXTI_LINE__)) 1538 1539 /** 1540 * @brief enable falling edge interrupt on selected EXTI line. 1541 * @param __EXTI_LINE__: specifies the ETH WAKEUP EXTI sources to be disabled. 1542 * @arg ETH_WAKEUP_EXTI_LINE 1543 * @retval None 1544 */ 1545 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE(__EXTI_LINE__) (EXTI->RTSR3 |= (__EXTI_LINE__));\ 1546 (EXTI->FTSR3 |= (__EXTI_LINE__)) 1547 1548 /** 1549 * @brief Generates a Software interrupt on selected EXTI line. 1550 * @param __EXTI_LINE__: specifies the ETH WAKEUP EXTI sources to be disabled. 1551 * @arg ETH_WAKEUP_EXTI_LINE 1552 * @retval None 1553 */ 1554 #define __HAL_ETH_WAKEUP_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER3 |= (__EXTI_LINE__)) 1555 1556 /** 1557 * @} 1558 */ 1559 1560 /* Include ETH HAL Extension module */ 1561 #include "stm32h7xx_hal_eth_ex_legacy.h" 1562 1563 /* Exported functions --------------------------------------------------------*/ 1564 1565 /** @addtogroup ETH_Exported_Functions 1566 * @{ 1567 */ 1568 1569 /** @addtogroup ETH_Exported_Functions_Group1 1570 * @{ 1571 */ 1572 /* Initialization and de initialization functions **********************************/ 1573 HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth); 1574 HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth); 1575 void HAL_ETH_MspInit(ETH_HandleTypeDef *heth); 1576 void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth); 1577 HAL_StatusTypeDef HAL_ETH_DescAssignMemory(ETH_HandleTypeDef *heth, uint32_t Index, uint8_t *pBuffer1,uint8_t *pBuffer2); 1578 1579 /* Callbacks Register/UnRegister functions ***********************************/ 1580 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) 1581 HAL_StatusTypeDef HAL_ETH_RegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID, pETH_CallbackTypeDef pCallback); 1582 HAL_StatusTypeDef HAL_ETH_UnRegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID); 1583 #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ 1584 1585 /** 1586 * @} 1587 */ 1588 1589 /** @addtogroup ETH_Exported_Functions_Group2 1590 * @{ 1591 */ 1592 /* IO operation functions *******************************************************/ 1593 HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth); 1594 HAL_StatusTypeDef HAL_ETH_Start_IT(ETH_HandleTypeDef *heth); 1595 HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth); 1596 HAL_StatusTypeDef HAL_ETH_Stop_IT(ETH_HandleTypeDef *heth); 1597 1598 uint8_t HAL_ETH_IsRxDataAvailable(ETH_HandleTypeDef *heth); 1599 HAL_StatusTypeDef HAL_ETH_GetRxDataBuffer(ETH_HandleTypeDef *heth, ETH_BufferTypeDef *RxBuffer); 1600 HAL_StatusTypeDef HAL_ETH_GetRxDataLength(ETH_HandleTypeDef *heth, uint32_t *Length); 1601 HAL_StatusTypeDef HAL_ETH_GetRxDataInfo(ETH_HandleTypeDef *heth, ETH_RxPacketInfo *RxPacketInfo); 1602 HAL_StatusTypeDef HAL_ETH_BuildRxDescriptors(ETH_HandleTypeDef *heth); 1603 1604 HAL_StatusTypeDef HAL_ETH_Transmit(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig, uint32_t Timeout); 1605 HAL_StatusTypeDef HAL_ETH_Transmit_IT(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig); 1606 1607 HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg, uint32_t RegValue); 1608 HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg, uint32_t *pRegValue); 1609 1610 void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth); 1611 void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth); 1612 void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth); 1613 void HAL_ETH_DMAErrorCallback(ETH_HandleTypeDef *heth); 1614 void HAL_ETH_MACErrorCallback(ETH_HandleTypeDef *heth); 1615 void HAL_ETH_PMTCallback(ETH_HandleTypeDef *heth); 1616 void HAL_ETH_EEECallback(ETH_HandleTypeDef *heth); 1617 void HAL_ETH_WakeUpCallback(ETH_HandleTypeDef *heth); 1618 /** 1619 * @} 1620 */ 1621 1622 /** @addtogroup ETH_Exported_Functions_Group3 1623 * @{ 1624 */ 1625 /* Peripheral Control functions **********************************************/ 1626 /* MAC & DMA Configuration APIs **********************************************/ 1627 HAL_StatusTypeDef HAL_ETH_GetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf); 1628 HAL_StatusTypeDef HAL_ETH_GetDMAConfig(ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf); 1629 HAL_StatusTypeDef HAL_ETH_SetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf); 1630 HAL_StatusTypeDef HAL_ETH_SetDMAConfig(ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf); 1631 void HAL_ETH_SetMDIOClockRange(ETH_HandleTypeDef *heth); 1632 1633 /* MAC VLAN Processing APIs ************************************************/ 1634 void HAL_ETH_SetRxVLANIdentifier(ETH_HandleTypeDef *heth, uint32_t ComparisonBits, uint32_t VLANIdentifier); 1635 1636 /* MAC L2 Packet Filtering APIs **********************************************/ 1637 HAL_StatusTypeDef HAL_ETH_GetMACFilterConfig(ETH_HandleTypeDef *heth, ETH_MACFilterConfigTypeDef *pFilterConfig); 1638 HAL_StatusTypeDef HAL_ETH_SetMACFilterConfig(ETH_HandleTypeDef *heth, ETH_MACFilterConfigTypeDef *pFilterConfig); 1639 HAL_StatusTypeDef HAL_ETH_SetHashTable(ETH_HandleTypeDef *heth, uint32_t *pHashTable); 1640 HAL_StatusTypeDef HAL_ETH_SetSourceMACAddrMatch(ETH_HandleTypeDef *heth, uint32_t AddrNbr, uint8_t *pMACAddr); 1641 1642 /* MAC Power Down APIs *****************************************************/ 1643 void HAL_ETH_EnterPowerDownMode(ETH_HandleTypeDef *heth, ETH_PowerDownConfigTypeDef *pPowerDownConfig); 1644 void HAL_ETH_ExitPowerDownMode(ETH_HandleTypeDef *heth); 1645 HAL_StatusTypeDef HAL_ETH_SetWakeUpFilter(ETH_HandleTypeDef *heth, uint32_t *pFilter, uint32_t Count); 1646 1647 /** 1648 * @} 1649 */ 1650 1651 /** @addtogroup ETH_Exported_Functions_Group4 1652 * @{ 1653 */ 1654 /* Peripheral State functions **************************************************/ 1655 HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth); 1656 uint32_t HAL_ETH_GetError(ETH_HandleTypeDef *heth); 1657 uint32_t HAL_ETH_GetDMAError(ETH_HandleTypeDef *heth); 1658 uint32_t HAL_ETH_GetMACError(ETH_HandleTypeDef *heth); 1659 uint32_t HAL_ETH_GetMACWakeUpSource(ETH_HandleTypeDef *heth); 1660 /** 1661 * @} 1662 */ 1663 1664 /** 1665 * @} 1666 */ 1667 1668 /** 1669 * @} 1670 */ 1671 1672 /** 1673 * @} 1674 */ 1675 1676 #endif /* ETH */ 1677 1678 #ifdef __cplusplus 1679 } 1680 #endif 1681 1682 #endif /* STM32H7xx_HAL_ETH_LEGACY_H */ 1683
