1 /**
2 ******************************************************************************
3 * @file partition_stm32h563xx.h
4 * @author MCD Application Team
5 * @brief CMSIS STM32H563xx Device Header File for Initial Setup for Secure /
6 * Non-Secure Zones for ARMCM33 based on CMSIS CORE partition_ARMCM33.h
7 * Template.
8 *
9 * This file contains:
10 * - Initialize Security Attribution Unit (SAU) CTRL register
11 * - Setup behavior of Sleep and Exception Handling
12 * - Setup behavior of Floating Point Unit
13 * - Setup Interrupt Target
14 *
15 ******************************************************************************
16 * @attention
17 *
18 * Copyright (c) 2022 STMicroelectronics.
19 * All rights reserved.
20 *
21 * This software is licensed under terms that can be found in the LICENSE file
22 * in the root directory of this software component.
23 * If no LICENSE file comes with this software, it is provided AS-IS.
24 *
25 ******************************************************************************
26 */
27
28 #ifndef PARTITION_STM32H563XX_H
29 #define PARTITION_STM32H563XX_H
30
31 /*
32 //-------- <<< Use Configuration Wizard in Context Menu >>> -----------------
33 */
34
35 /*
36 // <e>Initialize Security Attribution Unit (SAU) CTRL register
37 */
38 #define SAU_INIT_CTRL 1
39
40 /*
41 // <q> Enable SAU
42 // <i> Value for SAU->CTRL register bit ENABLE
43 */
44 #define SAU_INIT_CTRL_ENABLE 0
45
46 /*
47 // <o> When SAU is disabled
48 // <0=> All Memory is Secure
49 // <1=> All Memory is Non-Secure
50 // <i> Value for SAU->CTRL register bit ALLNS
51 // <i> When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration.
52 */
53 #define SAU_INIT_CTRL_ALLNS 1
54
55 /*
56 // </e>
57 */
58
59 /*
60 // <h>Initialize Security Attribution Unit (SAU) Address Regions
61 // <i>SAU configuration specifies regions to be one of:
62 // <i> - Secure and Non-Secure Callable
63 // <i> - Non-Secure
64 // <i>Note: All memory regions not configured by SAU are Secure
65 */
66 #define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */
67
68 /*
69 // <e>Initialize SAU Region 0
70 // <i> Setup SAU Region 0 memory attributes
71 */
72 #define SAU_INIT_REGION0 0
73
74 /*
75 // <o>Start Address <0-0xFFFFFFE0>
76 */
77 #define SAU_INIT_START0 0x0C0FE000 /* start address of SAU region 0 */
78
79 /*
80 // <o>End Address <0x1F-0xFFFFFFFF>
81 */
82 #define SAU_INIT_END0 0x0C0FFFFF /* end address of SAU region 0 */
83
84 /*
85 // <o>Region is
86 // <0=>Non-Secure
87 // <1=>Secure, Non-Secure Callable
88 */
89 #define SAU_INIT_NSC0 1
90 /*
91 // </e>
92 */
93
94 /*
95 // <e>Initialize SAU Region 1
96 // <i> Setup SAU Region 1 memory attributes
97 */
98 #define SAU_INIT_REGION1 0
99
100 /*
101 // <o>Start Address <0-0xFFFFFFE0>
102 */
103 #define SAU_INIT_START1 0x08100000 /* start address of SAU region 1 */
104
105 /*
106 // <o>End Address <0x1F-0xFFFFFFFF>
107 */
108 #define SAU_INIT_END1 0x081FFFFF /* end address of SAU region 1 */
109
110 /*
111 // <o>Region is
112 // <0=>Non-Secure
113 // <1=>Secure, Non-Secure Callable
114 */
115 #define SAU_INIT_NSC1 0
116 /*
117 // </e>
118 */
119
120 /*
121 // <e>Initialize SAU Region 2
122 // <i> Setup SAU Region 2 memory attributes
123 */
124 #define SAU_INIT_REGION2 0
125
126 /*
127 // <o>Start Address <0-0xFFFFFFE0>
128 */
129 #define SAU_INIT_START2 0x20050000 /* start address of SAU region 2 */
130
131 /*
132 // <o>End Address <0x1F-0xFFFFFFFF>
133 */
134 #define SAU_INIT_END2 0x2009FFFF /* end address of SAU region 2 */
135
136 /*
137 // <o>Region is
138 // <0=>Non-Secure
139 // <1=>Secure, Non-Secure Callable
140 */
141 #define SAU_INIT_NSC2 0
142 /*
143 // </e>
144 */
145
146 /*
147 // <e>Initialize SAU Region 3
148 // <i> Setup SAU Region 3 memory attributes
149 */
150 #define SAU_INIT_REGION3 0
151
152 /*
153 // <o>Start Address <0-0xFFFFFFE0>
154 */
155 #define SAU_INIT_START3 0x40000000 /* start address of SAU region 3 */
156
157 /*
158 // <o>End Address <0x1F-0xFFFFFFFF>
159 */
160 #define SAU_INIT_END3 0x4FFFFFFF /* end address of SAU region 3 */
161
162 /*
163 // <o>Region is
164 // <0=>Non-Secure
165 // <1=>Secure, Non-Secure Callable
166 */
167 #define SAU_INIT_NSC3 0
168 /*
169 // </e>
170 */
171
172 /*
173 // <e>Initialize SAU Region 4
174 // <i> Setup SAU Region 4 memory attributes
175 */
176 #define SAU_INIT_REGION4 0
177
178 /*
179 // <o>Start Address <0-0xFFFFFFE0>
180 */
181 #define SAU_INIT_START4 0x60000000 /* start address of SAU region 4 */
182
183 /*
184 // <o>End Address <0x1F-0xFFFFFFFF>
185 */
186 #define SAU_INIT_END4 0x9FFFFFFF /* end address of SAU region 4 */
187
188 /*
189 // <o>Region is
190 // <0=>Non-Secure
191 // <1=>Secure, Non-Secure Callable
192 */
193 #define SAU_INIT_NSC4 0
194 /*
195 // </e>
196 */
197
198 /*
199 // <e>Initialize SAU Region 5
200 // <i> Setup SAU Region 5 memory attributes
201 */
202 #define SAU_INIT_REGION5 0
203
204 /*
205 // <o>Start Address <0-0xFFFFFFE0>
206 */
207 #define SAU_INIT_START5 0x0BF90000 /* start address of SAU region 5 */
208
209 /*
210 // <o>End Address <0x1F-0xFFFFFFFF>
211 */
212 #define SAU_INIT_END5 0x0BFA8FFF /* end address of SAU region 5 */
213
214 /*
215 // <o>Region is
216 // <0=>Non-Secure
217 // <1=>Secure, Non-Secure Callable
218 */
219 #define SAU_INIT_NSC5 0
220 /*
221 // </e>
222 */
223
224 /*
225 // <e>Initialize SAU Region 6
226 // <i> Setup SAU Region 6 memory attributes
227 */
228 #define SAU_INIT_REGION6 0
229
230 /*
231 // <o>Start Address <0-0xFFFFFFE0>
232 */
233 #define SAU_INIT_START6 0x00000000 /* start address of SAU region 6 */
234
235 /*
236 // <o>End Address <0x1F-0xFFFFFFFF>
237 */
238 #define SAU_INIT_END6 0x00000000 /* end address of SAU region 6 */
239
240 /*
241 // <o>Region is
242 // <0=>Non-Secure
243 // <1=>Secure, Non-Secure Callable
244 */
245 #define SAU_INIT_NSC6 0
246 /*
247 // </e>
248 */
249
250 /*
251 // <e>Initialize SAU Region 7
252 // <i> Setup SAU Region 7 memory attributes
253 */
254 #define SAU_INIT_REGION7 0
255
256 /*
257 // <o>Start Address <0-0xFFFFFFE0>
258 */
259 #define SAU_INIT_START7 0x00000000 /* start address of SAU region 7 */
260
261 /*
262 // <o>End Address <0x1F-0xFFFFFFFF>
263 */
264 #define SAU_INIT_END7 0x00000000 /* end address of SAU region 7 */
265
266 /*
267 // <o>Region is
268 // <0=>Non-Secure
269 // <1=>Secure, Non-Secure Callable
270 */
271 #define SAU_INIT_NSC7 0
272 /*
273 // </e>
274 */
275
276 /*
277 // </h>
278 */
279
280 /*
281 // <e>Setup behaviour of Sleep and Exception Handling
282 */
283 #define SCB_CSR_AIRCR_INIT 0
284
285 /*
286 // <o> Deep Sleep can be enabled by
287 // <0=>Secure and Non-Secure state
288 // <1=>Secure state only
289 // <i> Value for SCB->CSR register bit DEEPSLEEPS
290 */
291 #define SCB_CSR_DEEPSLEEPS_VAL 0
292
293 /*
294 // <o>System reset request accessible from
295 // <0=> Secure and Non-Secure state
296 // <1=> Secure state only
297 // <i> Value for SCB->AIRCR register bit SYSRESETREQS
298 */
299 #define SCB_AIRCR_SYSRESETREQS_VAL 0
300
301 /*
302 // <o>Priority of Non-Secure exceptions is
303 // <0=> Not altered
304 // <1=> Lowered to 0x04-0x07
305 // <i> Value for SCB->AIRCR register bit PRIS
306 */
307 #define SCB_AIRCR_PRIS_VAL 0
308
309 /*
310 // <o>BusFault, HardFault, and NMI target
311 // <0=> Secure state
312 // <1=> Non-Secure state
313 // <i> Value for SCB->AIRCR register bit BFHFNMINS
314 */
315 #define SCB_AIRCR_BFHFNMINS_VAL 0
316
317 /*
318 // </e>
319 */
320
321 /*
322 // <e>Setup behaviour of Floating Point Unit
323 */
324 #define TZ_FPU_NS_USAGE 1
325
326 /*
327 // <o>Floating Point Unit usage
328 // <0=> Secure state only
329 // <3=> Secure and Non-Secure state
330 // <i> Value for SCB->NSACR register bits CP10, CP11
331 */
332 #define SCB_NSACR_CP10_11_VAL 3
333
334 /*
335 // <o>Treat floating-point registers as Secure
336 // <0=> Disabled
337 // <1=> Enabled
338 // <i> Value for FPU->FPCCR register bit TS
339 */
340 #define FPU_FPCCR_TS_VAL 0
341
342 /*
343 // <o>Clear on return (CLRONRET) accessibility
344 // <0=> Secure and Non-Secure state
345 // <1=> Secure state only
346 // <i> Value for FPU->FPCCR register bit CLRONRETS
347 */
348 #define FPU_FPCCR_CLRONRETS_VAL 0
349
350 /*
351 // <o>Clear floating-point caller saved registers on exception return
352 // <0=> Disabled
353 // <1=> Enabled
354 // <i> Value for FPU->FPCCR register bit CLRONRET
355 */
356 #define FPU_FPCCR_CLRONRET_VAL 1
357
358 /*
359 // </e>
360 */
361
362 /*
363 // <h>Setup Interrupt Target
364 */
365
366 /*
367 // <e>Initialize ITNS 0 (Interrupts 0..31)
368 */
369 #define NVIC_INIT_ITNS0 1
370
371 /*
372 // Interrupts 0..31
373 // <o.0> WWDG_IRQn <0=> Secure state <1=> Non-Secure state
374 // <o.1> PVD_AVD_IRQn <0=> Secure state <1=> Non-Secure state
375 // <o.2> RTC_IRQn <0=> Secure state <1=> Non-Secure state
376 // <o.3> RTC_S_IRQn <0=> Secure state <1=> Non-Secure state
377 // <o.4> TAMP_IRQn <0=> Secure state <1=> Non-Secure state
378 // <o.5> RAMCFG_IRQn <0=> Secure state <1=> Non-Secure state
379 // <o.6> FLASH_IRQn <0=> Secure state <1=> Non-Secure state
380 // <o.7> FLASH_S_IRQn <0=> Secure state <1=> Non-Secure state
381 // <o.8> GTZC_IRQn <0=> Secure state <1=> Non-Secure state
382 // <o.9> RCC_IRQn <0=> Secure state <1=> Non-Secure state
383 // <o.10> RCC_S_IRQn <0=> Secure state <1=> Non-Secure state
384 // <o.11> EXTI0_IRQn <0=> Secure state <1=> Non-Secure state
385 // <o.12> EXTI1_IRQn <0=> Secure state <1=> Non-Secure state
386 // <o.13> EXTI2_IRQn <0=> Secure state <1=> Non-Secure state
387 // <o.14> EXTI3_IRQn <0=> Secure state <1=> Non-Secure state
388 // <o.15> EXTI4_IRQn <0=> Secure state <1=> Non-Secure state
389 // <o.16> EXTI5_IRQn <0=> Secure state <1=> Non-Secure state
390 // <o.17> EXTI6_IRQn <0=> Secure state <1=> Non-Secure state
391 // <o.18> EXTI7_IRQn <0=> Secure state <1=> Non-Secure state
392 // <o.19> EXTI8_IRQn <0=> Secure state <1=> Non-Secure state
393 // <o.20> EXTI9_IRQn <0=> Secure state <1=> Non-Secure state
394 // <o.21> EXTI10_IRQn <0=> Secure state <1=> Non-Secure state
395 // <o.22> EXTI11_IRQn <0=> Secure state <1=> Non-Secure state
396 // <o.23> EXTI12_IRQn <0=> Secure state <1=> Non-Secure state
397 // <o.24> EXTI13_IRQn <0=> Secure state <1=> Non-Secure state
398 // <o.25> EXTI14_IRQn <0=> Secure state <1=> Non-Secure state
399 // <o.26> EXTI15_IRQn <0=> Secure state <1=> Non-Secure state
400 // <o.27> GPDMA1_Channel0_IRQn <0=> Secure state <1=> Non-Secure state
401 // <o.28> GPDMA1_Channel1_IRQn <0=> Secure state <1=> Non-Secure state
402 // <o.29> GPDMA1_Channel2_IRQn <0=> Secure state <1=> Non-Secure state
403 // <o.30> GPDMA1_Channel3_IRQn <0=> Secure state <1=> Non-Secure state
404 // <o.31> GPDMA1_Channel4_IRQn <0=> Secure state <1=> Non-Secure state
405 */
406 #define NVIC_INIT_ITNS0_VAL 0x00000000
407
408 /*
409 // </e>
410 */
411
412 /*
413 // <e>Initialize ITNS 1 (Interrupts 32..63)
414 */
415 #define NVIC_INIT_ITNS1 1
416
417 /*
418 // Interrupts 32..63
419 // <o.0> GPDMA1_Channel5_IRQn <0=> Secure state <1=> Non-Secure state
420 // <o.1> GPDMA1_Channel6_IRQn <0=> Secure state <1=> Non-Secure state
421 // <o.2> GPDMA1_Channel7_IRQn <0=> Secure state <1=> Non-Secure state
422 // <o.3> IWDG_IRQn <0=> Secure state <1=> Non-Secure state
423 // <o.4> ADC1_IRQn <0=> Secure state <1=> Non-Secure state
424 // <o.5> DAC1_IRQn <0=> Secure state <1=> Non-Secure state
425 // <o.6> FDCAN1_IT0_IRQn <0=> Secure state <1=> Non-Secure state
426 // <o.7> FDCAN1_IT1_IRQn <0=> Secure state <1=> Non-Secure state
427 // <o.8> TIM1_BRK_IRQn <0=> Secure state <1=> Non-Secure state
428 // <o.9> TIM1_UP_IRQn <0=> Secure state <1=> Non-Secure state
429 // <o.10> TIM1_TRG_COM_IRQn <0=> Secure state <1=> Non-Secure state
430 // <o.11> TIM1_CC_IRQn <0=> Secure state <1=> Non-Secure state
431 // <o.12> TIM2_IRQn <0=> Secure state <1=> Non-Secure state
432 // <o.13> TIM3_IRQn <0=> Secure state <1=> Non-Secure state
433 // <o.14> TIM4_IRQn <0=> Secure state <1=> Non-Secure state
434 // <o.15> TIM5_IRQn <0=> Secure state <1=> Non-Secure state
435 // <o.16> TIM6_IRQn <0=> Secure state <1=> Non-Secure state
436 // <o.17> TIM7_IRQn <0=> Secure state <1=> Non-Secure state
437 // <o.18> I2C1_EV_IRQn <0=> Secure state <1=> Non-Secure state
438 // <o.19> I2C1_ER_IRQn <0=> Secure state <1=> Non-Secure state
439 // <o.20> I2C2_EV_IRQn <0=> Secure state <1=> Non-Secure state
440 // <o.21> I2C2_ER_IRQn <0=> Secure state <1=> Non-Secure state
441 // <o.22> SPI1_IRQn <0=> Secure state <1=> Non-Secure state
442 // <o.23> SPI2_IRQn <0=> Secure state <1=> Non-Secure state
443 // <o.24> SPI3_IRQn <0=> Secure state <1=> Non-Secure state
444 // <o.25> USART1_IRQn <0=> Secure state <1=> Non-Secure state
445 // <o.26> USART2_IRQn <0=> Secure state <1=> Non-Secure state
446 // <o.27> USART3_IRQn <0=> Secure state <1=> Non-Secure state
447 // <o.28> UART4_IRQn <0=> Secure state <1=> Non-Secure state
448 // <o.29> UART5_IRQn <0=> Secure state <1=> Non-Secure state
449 // <o.30> LPUART1_IRQn <0=> Secure state <1=> Non-Secure state
450 // <o.31> LPTIM1_IRQn <0=> Secure state <1=> Non-Secure state
451 */
452 #define NVIC_INIT_ITNS1_VAL 0x00000000
453
454 /*
455 // </e>
456 */
457
458 /*
459 // <e>Initialize ITNS 2 (Interrupts 64..95)
460 */
461 #define NVIC_INIT_ITNS2 1
462
463 /*
464 // Interrupts 64..95
465 // <o.0> TIM8_BRK_IRQn <0=> Secure state <1=> Non-Secure state
466 // <o.1> TIM8_UP_IRQn <0=> Secure state <1=> Non-Secure state
467 // <o.2> TIM8_TRG_COM_IRQn <0=> Secure state <1=> Non-Secure state
468 // <o.3> TIM8_CC_IRQn <0=> Secure state <1=> Non-Secure state
469 // <o.4> ADC2_IRQn <0=> Secure state <1=> Non-Secure state
470 // <o.5> LPTIM2_IRQn <0=> Secure state <1=> Non-Secure state
471 // <o.6> TIM15_IRQn <0=> Secure state <1=> Non-Secure state
472 // <o.7> TIM16_IRQn <0=> Secure state <1=> Non-Secure state
473 // <o.8> TIM17_IRQn <0=> Secure state <1=> Non-Secure state
474 // <o.9> USB_DRD_FS_IRQn <0=> Secure state <1=> Non-Secure state
475 // <o.10> CRS_IRQn <0=> Secure state <1=> Non-Secure state
476 // <o.11> UCPD1_IRQn <0=> Secure state <1=> Non-Secure state
477 // <o.12> FMC_IRQn <0=> Secure state <1=> Non-Secure state
478 // <o.13> OCTOSPI1_IRQn <0=> Secure state <1=> Non-Secure state
479 // <o.14> SDMMC1_IRQn <0=> Secure state <1=> Non-Secure state
480 // <o.15> I2C3_EV_IRQn <0=> Secure state <1=> Non-Secure state
481 // <o.16> I2C3_ER_IRQn <0=> Secure state <1=> Non-Secure state
482 // <o.17> SPI4_IRQn <0=> Secure state <1=> Non-Secure state
483 // <o.18> SPI5_IRQn <0=> Secure state <1=> Non-Secure state
484 // <o.19> SPI6_IRQn <0=> Secure state <1=> Non-Secure state
485 // <o.20> USART6_IRQn <0=> Secure state <1=> Non-Secure state
486 // <o.21> USART10_IRQn <0=> Secure state <1=> Non-Secure state
487 // <o.22> USART11_IRQn <0=> Secure state <1=> Non-Secure state
488 // <o.23> SAI1_IRQn <0=> Secure state <1=> Non-Secure state
489 // <o.24> SAI2_IRQn <0=> Secure state <1=> Non-Secure state
490 // <o.25> GPDMA2_Channel0_IRQn <0=> Secure state <1=> Non-Secure state
491 // <o.26> GPDMA2_Channel1_IRQn <0=> Secure state <1=> Non-Secure state
492 // <o.27> GPDMA2_Channel2_IRQn <0=> Secure state <1=> Non-Secure state
493 // <o.28> GPDMA2_Channel3_IRQn <0=> Secure state <1=> Non-Secure state
494 // <o.29> GPDMA2_Channel4_IRQn <0=> Secure state <1=> Non-Secure state
495 // <o.30> GPDMA2_Channel5_IRQn <0=> Secure state <1=> Non-Secure state
496 // <o.31> GPDMA2_Channel6_IRQn <0=> Secure state <1=> Non-Secure state
497 */
498 #define NVIC_INIT_ITNS2_VAL 0x00000000
499
500 /*
501 // </e>
502 */
503
504 /*
505 // <e>Initialize ITNS 3 (Interrupts 96..126)
506 */
507 #define NVIC_INIT_ITNS3 1
508
509 /*
510 // Interrupts 96..126
511 // <o.0> GPDMA2_Channel7_IRQn <0=> Secure state <1=> Non-Secure state
512 // <o.1> UART7_IRQn <0=> Secure state <1=> Non-Secure state
513 // <o.2> UART8_IRQn <0=> Secure state <1=> Non-Secure state
514 // <o.3> UART9_IRQn <0=> Secure state <1=> Non-Secure state
515 // <o.4> UART12_IRQn <0=> Secure state <1=> Non-Secure state
516 // <o.5> SDMMC2_IRQn <0=> Secure state <1=> Non-Secure state
517 // <o.6> FPU_IRQn <0=> Secure state <1=> Non-Secure state
518 // <o.7> ICACHE_IRQn <0=> Secure state <1=> Non-Secure state
519 // <o.8> DCACHE_IRQn <0=> Secure state <1=> Non-Secure state
520 // <o.9> ETH_IRQn <0=> Secure state <1=> Non-Secure state
521 // <o.10> ETH_WKUP_IRQn <0=> Secure state <1=> Non-Secure state
522 // <o.11> DCMI_PSSI_IRQn <0=> Secure state <1=> Non-Secure state
523 // <o.12> FDCAN2_IT0_IRQn <0=> Secure state <1=> Non-Secure state
524 // <o.13> FDCAN2_IT1_IRQn <0=> Secure state <1=> Non-Secure state
525 // <o.14> CORDIC_IRQn <0=> Secure state <1=> Non-Secure state
526 // <o.15> FMAC_IRQn <0=> Secure state <1=> Non-Secure state
527 // <o.16> DTS_IRQn <0=> Secure state <1=> Non-Secure state
528 // <o.17> RNG_IRQn <0=> Secure state <1=> Non-Secure state
529 // <o.18> HASH_IRQn <0=> Secure state <1=> Non-Secure state
530 // <o.19> CEC_IRQn <0=> Secure state <1=> Non-Secure state
531 // <o.20> TIM12_IRQn <0=> Secure state <1=> Non-Secure state
532 // <o.21> TIM13_IRQn <0=> Secure state <1=> Non-Secure state
533 // <o.22> TIM14_IRQn <0=> Secure state <1=> Non-Secure state
534 // <o.23> I3C1_EV_IRQn <0=> Secure state <1=> Non-Secure state
535 // <o.24> I3C1_ER_IRQn <0=> Secure state <1=> Non-Secure state
536 // <o.25> I2C4_EV_IRQn <0=> Secure state <1=> Non-Secure state
537 // <o.26> I2C4_ER_IRQn <0=> Secure state <1=> Non-Secure state
538 // <o.27> LPTIM3_IRQn <0=> Secure state <1=> Non-Secure state
539 // <o.28> LPTIM4_IRQn <0=> Secure state <1=> Non-Secure state
540 // <o.29> LPTIM5_IRQn <0=> Secure state <1=> Non-Secure state
541 // <o.30> LPTIM6_IRQn <0=> Secure state <1=> Non-Secure state
542 */
543 #define NVIC_INIT_ITNS3_VAL 0x00000000
544
545 /*
546 // </h>
547 */
548
549 /*
550 max 8 SAU regions.
551 SAU regions are defined in partition.h
552 */
553
554 #define SAU_INIT_REGION(n) \
555 SAU->RNR = (n & SAU_RNR_REGION_Msk); \
556 SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \
557 SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \
558 ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U
559
560 /**
561 \brief Setup a SAU Region
562 \details Writes the region information contained in SAU_Region to the
563 registers SAU_RNR, SAU_RBAR, and SAU_RLAR
564 */
TZ_SAU_Setup(void)565 __STATIC_INLINE void TZ_SAU_Setup (void)
566 {
567
568 #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
569
570 #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U)
571 SAU_INIT_REGION(0);
572 #endif
573
574 #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U)
575 SAU_INIT_REGION(1);
576 #endif
577
578 #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U)
579 SAU_INIT_REGION(2);
580 #endif
581
582 #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U)
583 SAU_INIT_REGION(3);
584 #endif
585
586 #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U)
587 SAU_INIT_REGION(4);
588 #endif
589
590 #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U)
591 SAU_INIT_REGION(5);
592 #endif
593
594 #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U)
595 SAU_INIT_REGION(6);
596 #endif
597
598 #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U)
599 SAU_INIT_REGION(7);
600 #endif
601
602 /* repeat this for all possible SAU regions */
603
604 #endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
605
606
607 #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U)
608 SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) |
609 ((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ;
610 #endif
611
612 #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U)
613 SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) |
614 ((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk);
615
616 SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk |
617 SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk) ) |
618 ((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) |
619 ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) |
620 ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) |
621 ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk);
622 #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */
623
624 #if defined (__FPU_USED) && (__FPU_USED == 1U) && \
625 defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U)
626
627 SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) |
628 ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk));
629
630 FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) |
631 ((FPU_FPCCR_TS_VAL << FPU_FPCCR_TS_Pos ) & FPU_FPCCR_TS_Msk ) |
632 ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) |
633 ((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk );
634 #endif
635
636 #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U)
637 NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL;
638 #endif
639
640 #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U)
641 NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL;
642 #endif
643
644 #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U)
645 NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL;
646 #endif
647
648 #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U)
649 NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL;
650 #endif
651
652 }
653
654 #endif /* PARTITION_STM32H563XX_H */
655
