1 /**
2 ******************************************************************************
3 * @file stm32h5xx_hal_gtzc.c
4 * @author MCD Application Team
5 * @brief GTZC HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of GTZC peripheral:
8 * + TZSC Initialization and Configuration functions
9 * + TZSC-MPCWM Initialization and Configuration functions
10 * + MPCBB Initialization and Configuration functions
11 * + TZSC, TZSC-MPCWM and MPCBB Lock functions
12 * + TZIC Initialization and Configuration functions
13 *
14 ******************************************************************************
15 * @attention
16 *
17 * Copyright (c) 2022 STMicroelectronics.
18 * All rights reserved.
19 *
20 * This software is licensed under terms that can be found in the LICENSE file
21 * in the root directory of this software component.
22 * If no LICENSE file comes with this software, it is provided AS-IS.
23 *
24 ******************************************************************************
25 @verbatim
26 ==============================================================================
27 ##### GTZC main features #####
28 ==============================================================================
29 [..]
30 (+) Global TrustZone Controller (GTZC) composed of three sub-blocks:
31 (++) TZSC: TrustZone security controller
32 This sub-block defines the secure/privileged state of master and slave
33 peripherals. It also controls the secure/privileged state of subregions
34 for the watermark memory peripheral controller (MPCWM).
35 (++) MPCBB: Block-Based memory protection controller
36 This sub-block defines the secure/privileged state of all blocks
37 (512-byte pages) of the associated SRAM.
38 (++) TZIC: TrustZone illegal access controller
39 This sub-block gathers all illegal access events in the system and
40 generates a secure interrupt towards NVIC.
41
42 (+) These sub-blocks are used to configure TrustZone system security in
43 a product having bus agents with programmable-security and privileged
44 attributes (securable) such as:
45 (++) on-chip RAM with programmable secure and/or privilege blocks (pages)
46 (++) AHB and APB peripherals with programmable security and/or privilege access
47 (++) AHB master granted as secure and/or privilege
48 (++) off-chip memories with secure and/or privilege areas
49
50 [..]
51 (+) TZIC accessible only with secure privileged transactions.
52 (+) Secure and non-secure access supported for privileged and unprivileged
53 part of TZSC and MPCBB
54 (+) Set of registers to define product security settings:
55 (++) Secure and privilege blocks for internal memories
56 (++) Secure and privilege regions for external memories
57 (++) Secure and privileged access mode for securable peripherals
58
59 ==============================================================================
60 ##### How to use this driver #####
61 ==============================================================================
62 [..]
63 The GTZC HAL driver can be used as follows:
64
65 (#) Configure or get back securable peripherals attributes using
66 HAL_GTZC_TZSC_ConfigPeriphAttributes() / HAL_GTZC_TZSC_GetConfigPeriphAttributes()
67
68 (#) Configure or get back MPCWM memories attributes using
69 HAL_GTZC_TZSC_MPCWM_ConfigMemAttributes() / HAL_GTZC_TZSC_MPCWM_GetConfigMemAttributes()
70
71 (#) Lock TZSC sub-block or get lock status using HAL_GTZC_TZSC_Lock() /
72 HAL_GTZC_TZSC_GetLock()
73
74 (#) Configure or get back MPCBB memories complete configuration using
75 HAL_GTZC_MPCBB_ConfigMem() / HAL_GTZC_MPCBB_GetConfigMem()
76
77 (#) Configure or get back MPCBB memories attributes using
78 HAL_GTZC_MPCBB_ConfigMemAttributes() / HAL_GTZC_MPCBB_GetConfigMemAttributes()
79
80 (#) Lock MPCBB configuration or get lock status using HAL_GTZC_MPCBB_Lock() /
81 HAL_GTZC_MPCBB_GetLock()
82
83 (#) Lock MPCBB super-blocks or get lock status using HAL_GTZC_MPCBB_LockConfig() /
84 HAL_GTZC_MPCBB_GetLockConfig()
85
86 (#) Illegal access detection can be configured through TZIC sub-block using
87 following functions: HAL_GTZC_TZIC_DisableIT() / HAL_GTZC_TZIC_EnableIT()
88
89 (#) Illegal access flags can be retrieved through HAL_GTZC_TZIC_GetFlag() and
90 HAL_GTZC_TZIC_ClearFlag() functions
91
92 (#) Illegal access interrupt service routines are served by HAL_GTZC_IRQHandler()
93 and user can add his own code using HAL_GTZC_TZIC_Callback()
94
95 @endverbatim
96 ******************************************************************************
97 */
98
99 /* Includes ------------------------------------------------------------------*/
100 #include "stm32h5xx_hal.h"
101
102 /** @addtogroup STM32H5xx_HAL_Driver
103 * @{
104 */
105
106 /** @defgroup GTZC GTZC
107 * @brief GTZC HAL module driver
108 * @{
109 */
110
111 #ifdef HAL_GTZC_MODULE_ENABLED
112
113 /* Private typedef -----------------------------------------------------------*/
114 /* Private constants ---------------------------------------------------------*/
115
116 /** @defgroup GTZC_Private_Constants GTZC Private Constants
117 * @{
118 */
119
120 /* Definitions for GTZC_TZSC_MPCWM */
121 #if defined (OCTOSPI1)
122 #define GTZC_TZSC_MPCWM1_MEM_SIZE 0x10000000U /* 256MB max size */
123 #endif /* defined (OCTOSPI1) */
124 #if defined (FMC_BANK1)
125 #define GTZC_TZSC_MPCWM2_MEM_SIZE 0x10000000U /* 256MB max size */
126 #endif /* defined (FMC_BANK1) */
127 #if defined (FMC_BANK3) || defined(FMC_SDRAM_BANK_1)
128 #define GTZC_TZSC_MPCWM3_MEM_SIZE 0x10000000U /* 256MB max size */
129 #endif /* defined (FMC_BANK3) || defined(FMC_SDRAM_BANK_1) */
130 #if defined(BKPSRAM_BASE)
131 #define GTZC_TZSC_MPCWM4_MEM_SIZE BKPSRAM_SIZE
132 #endif /* defined (BKPSRAM_BASE) */
133 #if defined(FMC_SDRAM_BANK_2)
134 #define GTZC_TZSC_MPCWM4_SDRAM_MEM_SIZE 0x10000000U /* 256MB max size */
135 #endif /* defined(FMC_SDRAM_BANK_2) */
136
137 /* Definitions for GTZC TZSC & TZIC ALL register values */
138 #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
139 #define TZSC1_SECCFGR1_ALL (0xFFFFFFFFUL)
140 #define TZSC1_SECCFGR2_ALL (0xFF0FFF07UL)
141 #define TZSC1_SECCFGR3_ALL (0x05FFFF03UL)
142 #endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
143
144 #if defined (GTZC_TZIC1)
145 #define TZSC1_PRIVCFGR1_ALL (0xFFFFFFFFUL)
146 #define TZSC1_PRIVCFGR2_ALL (0xFF0FFF07UL)
147 #define TZSC1_PRIVCFGR3_ALL (0x05FFFF03UL)
148 #else
149 #define TZSC1_PRIVCFGR1_ALL (0xC21E7E33UL)
150 #define TZSC1_PRIVCFGR2_ALL (0x12080B19UL)
151 #define TZSC1_PRIVCFGR3_ALL (0x04065106UL)
152 #endif /* defined (GTZC_TZIC1) */
153
154 #if defined (GTZC_TZIC1)
155 #define TZIC1_IER1_ALL (0xFFFFFFFFUL)
156 #define TZIC1_IER2_ALL (0xFF0FFF07UL)
157 #define TZIC1_IER3_ALL (0x05FFFF03UL)
158 #define TZIC1_IER4_ALL (0x3F3F0FFFUL)
159
160 #define TZIC1_FCR1_ALL (0xFFFFFFFFUL)
161 #define TZIC1_FCR2_ALL (0xFF0FFF07UL)
162 #define TZIC1_FCR3_ALL (0x05FFFF03UL)
163 #define TZIC1_FCR4_ALL (0x3F3F0FFFUL)
164 #endif /* defined (GTZC_TZIC1) */
165 /**
166 * @}
167 */
168
169 /* Private macros ------------------------------------------------------------*/
170
171 /** @defgroup GTZC_Private_Macros GTZC Private Macros
172 * @{
173 */
174
175 #define IS_ADDRESS_IN(mem, address)\
176 ( ( ( (uint32_t)(address) >= (uint32_t)GTZC_BASE_ADDRESS_NS(mem) ) \
177 && ( (uint32_t)(address) < ((uint32_t)GTZC_BASE_ADDRESS_NS(mem) + (uint32_t)GTZC_MEM_SIZE(mem) ) ) ) \
178 || ( ( (uint32_t)(address) >= (uint32_t)GTZC_BASE_ADDRESS_S(mem) ) \
179 && ( (uint32_t)(address) < ((uint32_t)GTZC_BASE_ADDRESS_S(mem) + (uint32_t)GTZC_MEM_SIZE(mem) ) ) ) )
180
181 #define IS_ADDRESS_IN_S(mem, address)\
182 ( ( (uint32_t)(address) >= (uint32_t)GTZC_BASE_ADDRESS_S(mem) ) \
183 && ( (uint32_t)(address) < ((uint32_t)GTZC_BASE_ADDRESS_S(mem) + (uint32_t)GTZC_MEM_SIZE(mem) ) ) )
184
185 #define IS_ADDRESS_IN_NS(mem, address)\
186 ( ( (uint32_t)(address) >= (uint32_t)GTZC_BASE_ADDRESS_NS(mem) ) \
187 && ( (uint32_t)(address) < ((uint32_t)GTZC_BASE_ADDRESS_NS(mem) + (uint32_t)GTZC_MEM_SIZE(mem) ) ) )
188
189 #define GTZC_BASE_ADDRESS(mem)\
190 ( mem ## _BASE )
191
192 /**
193 * @}
194 */
195
196 /* Private variables ---------------------------------------------------------*/
197 /* Private function prototypes -----------------------------------------------*/
198 /* Exported functions --------------------------------------------------------*/
199
200 /** @defgroup GTZC_Exported_Functions GTZC Exported Functions
201 * @{
202 */
203
204 /** @defgroup GTZC_Exported_Functions_Group1 TZSC Configuration functions
205 * @brief TZSC Configuration functions
206 *
207 @verbatim
208 ==============================================================================
209 ##### TZSC Configuration functions #####
210 ==============================================================================
211 [..]
212 This section provides functions allowing to configure TZSC
213 TZSC: TrustZone Security Controller
214 @endverbatim
215 * @{
216 */
217
218 /**
219 * @brief Configure TZSC on a single peripheral or on all peripherals.
220 * @note Secure and non-secure attributes can only be set from the secure
221 * state when the system implements the security (TZEN=1).
222 * @note Privilege and non-privilege attributes can only be set from the
223 * privilege state when TZEN=0 or TZEN=1
224 * @note Security and privilege attributes can be set independently.
225 * @note Default state is non-secure and unprivileged access allowed.
226 * @param PeriphId Peripheral identifier
227 * This parameter can be a value of @ref GTZC_TZSC_TZIC_PeriphId.
228 * Use GTZC_PERIPH_ALL to select all peripherals.
229 * @param PeriphAttributes Peripheral attributes, see @ref GTZC_TZSC_PeriphAttributes.
230 * @retval HAL status.
231 */
HAL_GTZC_TZSC_ConfigPeriphAttributes(uint32_t PeriphId,uint32_t PeriphAttributes)232 HAL_StatusTypeDef HAL_GTZC_TZSC_ConfigPeriphAttributes(uint32_t PeriphId,
233 uint32_t PeriphAttributes)
234 {
235 uint32_t register_address;
236
237 /* check entry parameters */
238 #if defined (GTZC_TZIC1)
239 if ((PeriphAttributes > (GTZC_TZSC_PERIPH_SEC | GTZC_TZSC_PERIPH_PRIV))
240 || (HAL_GTZC_GET_ARRAY_INDEX(PeriphId) >= GTZC_TZSC_PERIPH_NUMBER)
241 || (((PeriphId & GTZC_PERIPH_ALL) != 0U)
242 && (HAL_GTZC_GET_ARRAY_INDEX(PeriphId) != 0U)))
243 #else
244 if ((PeriphAttributes > GTZC_TZSC_PERIPH_PRIV)
245 || (HAL_GTZC_GET_ARRAY_INDEX(PeriphId) >= GTZC_TZSC_PERIPH_NUMBER)
246 || (((PeriphId & GTZC_PERIPH_ALL) != 0U)
247 && (HAL_GTZC_GET_ARRAY_INDEX(PeriphId) != 0U)))
248 #endif /* defined (GTZC_TZIC1) */
249 {
250 return HAL_ERROR;
251 }
252
253 if ((PeriphId & GTZC_PERIPH_ALL) != 0U)
254 {
255 /* special case where same attributes are applied to all peripherals */
256
257 #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
258 /* secure configuration */
259 if ((PeriphAttributes & GTZC_TZSC_PERIPH_SEC) == GTZC_TZSC_PERIPH_SEC)
260 {
261 SET_BIT(GTZC_TZSC1->SECCFGR1, TZSC1_SECCFGR1_ALL);
262 SET_BIT(GTZC_TZSC1->SECCFGR2, TZSC1_SECCFGR2_ALL);
263 SET_BIT(GTZC_TZSC1->SECCFGR3, TZSC1_SECCFGR3_ALL);
264 }
265 else if ((PeriphAttributes & GTZC_TZSC_PERIPH_NSEC) == GTZC_TZSC_PERIPH_NSEC)
266 {
267 CLEAR_BIT(GTZC_TZSC1->SECCFGR1, TZSC1_SECCFGR1_ALL);
268 CLEAR_BIT(GTZC_TZSC1->SECCFGR2, TZSC1_SECCFGR2_ALL);
269 CLEAR_BIT(GTZC_TZSC1->SECCFGR3, TZSC1_SECCFGR3_ALL);
270 }
271 else
272 {
273 /* do nothing */
274 }
275 #endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
276
277 /* privilege configuration */
278 if ((PeriphAttributes & GTZC_TZSC_PERIPH_PRIV) == GTZC_TZSC_PERIPH_PRIV)
279 {
280 SET_BIT(GTZC_TZSC1->PRIVCFGR1, TZSC1_PRIVCFGR1_ALL);
281 SET_BIT(GTZC_TZSC1->PRIVCFGR2, TZSC1_PRIVCFGR2_ALL);
282 SET_BIT(GTZC_TZSC1->PRIVCFGR3, TZSC1_PRIVCFGR3_ALL);
283 }
284 else if ((PeriphAttributes & GTZC_TZSC_PERIPH_NPRIV) == GTZC_TZSC_PERIPH_NPRIV)
285 {
286 CLEAR_BIT(GTZC_TZSC1->PRIVCFGR1, TZSC1_PRIVCFGR1_ALL);
287 CLEAR_BIT(GTZC_TZSC1->PRIVCFGR2, TZSC1_PRIVCFGR2_ALL);
288 CLEAR_BIT(GTZC_TZSC1->PRIVCFGR3, TZSC1_PRIVCFGR3_ALL);
289 }
290 else
291 {
292 /* do nothing */
293 }
294 }
295 else
296 {
297 /* common case where only one peripheral is configured */
298
299 #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
300 /* secure configuration */
301 register_address = (uint32_t) &(GTZC_TZSC1->SECCFGR1)
302 + (4U * GTZC_GET_REG_INDEX(PeriphId));
303 if ((PeriphAttributes & GTZC_TZSC_PERIPH_SEC) == GTZC_TZSC_PERIPH_SEC)
304 {
305 SET_BIT(*(__IO uint32_t *)register_address, 1UL << GTZC_GET_PERIPH_POS(PeriphId));
306 }
307 else if ((PeriphAttributes & GTZC_TZSC_PERIPH_NSEC) == GTZC_TZSC_PERIPH_NSEC)
308 {
309 CLEAR_BIT(*(__IO uint32_t *)register_address, 1UL << GTZC_GET_PERIPH_POS(PeriphId));
310 }
311 else
312 {
313 /* do nothing */
314 }
315 #endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
316
317 /* privilege configuration */
318 register_address = (uint32_t) &(GTZC_TZSC1->PRIVCFGR1)
319 + (4U * GTZC_GET_REG_INDEX(PeriphId));
320 if ((PeriphAttributes & GTZC_TZSC_PERIPH_PRIV) == GTZC_TZSC_PERIPH_PRIV)
321 {
322 SET_BIT(*(__IO uint32_t *)register_address, 1UL << GTZC_GET_PERIPH_POS(PeriphId));
323 }
324 else if ((PeriphAttributes & GTZC_TZSC_PERIPH_NPRIV) == GTZC_TZSC_PERIPH_NPRIV)
325 {
326 CLEAR_BIT(*(__IO uint32_t *)register_address, 1UL << GTZC_GET_PERIPH_POS(PeriphId));
327 }
328 else
329 {
330 /* do nothing */
331 }
332 }
333 return HAL_OK;
334 }
335
336 /**
337 * @brief Get TZSC configuration on a single peripheral or on all peripherals.
338 * @param PeriphId Peripheral identifier.
339 * This parameter can be a value of @ref GTZC_TZSC_TZIC_PeriphId.
340 * Use GTZC_PERIPH_ALL to select all peripherals.
341 * @param PeriphAttributes Peripheral attribute pointer.
342 * This parameter can be a value of @ref GTZC_TZSC_PeriphAttributes.
343 * If PeriphId target a single peripheral, pointer on a single element.
344 * If all peripherals selected (GTZC_PERIPH_ALL), pointer to an array of
345 * GTZC_TZSC_PERIPH_NUMBER elements is to be provided.
346 * @retval HAL status.
347 */
HAL_GTZC_TZSC_GetConfigPeriphAttributes(uint32_t PeriphId,uint32_t * PeriphAttributes)348 HAL_StatusTypeDef HAL_GTZC_TZSC_GetConfigPeriphAttributes(uint32_t PeriphId,
349 uint32_t *PeriphAttributes)
350 {
351 uint32_t i;
352 uint32_t reg_value;
353 uint32_t register_address;
354
355 /* check entry parameters */
356 if ((PeriphAttributes == NULL)
357 || (HAL_GTZC_GET_ARRAY_INDEX(PeriphId) >= GTZC_TZSC_PERIPH_NUMBER)
358 || (((PeriphId & GTZC_PERIPH_ALL) != 0U)
359 && (HAL_GTZC_GET_ARRAY_INDEX(PeriphId) != 0U)))
360 {
361 return HAL_ERROR;
362 }
363
364 if ((PeriphId & GTZC_PERIPH_ALL) != 0U)
365 {
366 #if defined (GTZC_TZIC1)
367 /* get secure configuration: read each register and deploy each bit value
368 * of corresponding index in the destination array
369 */
370 reg_value = READ_REG(GTZC_TZSC1->SECCFGR1);
371 for (i = 0U; i < 32U; i++)
372 {
373 if (((reg_value & (1UL << i)) >> i) != 0U)
374 {
375 PeriphAttributes[i] = GTZC_TZSC_PERIPH_SEC;
376 }
377 else
378 {
379 PeriphAttributes[i] = GTZC_TZSC_PERIPH_NSEC;
380 }
381 }
382
383 reg_value = READ_REG(GTZC_TZSC1->SECCFGR2);
384 for (i = 32U; i < 64U; i++)
385 {
386 if (((reg_value & (1UL << (i - 32U))) >> (i - 32U)) != 0U)
387 {
388 PeriphAttributes[i] = GTZC_TZSC_PERIPH_SEC;
389 }
390 else
391 {
392 PeriphAttributes[i] = GTZC_TZSC_PERIPH_NSEC;
393 }
394 }
395
396 reg_value = READ_REG(GTZC_TZSC1->SECCFGR3);
397 for (i = 64U; i < GTZC_TZSC_PERIPH_NUMBER; i++)
398 {
399 if (((reg_value & (1UL << (i - 64U))) >> (i - 64U)) != 0U)
400 {
401 PeriphAttributes[i] = GTZC_TZSC_PERIPH_SEC;
402 }
403 else
404 {
405 PeriphAttributes[i] = GTZC_TZSC_PERIPH_NSEC;
406 }
407 }
408 #endif /* defined (GTZC_TZIC1) */
409
410 /* get privilege configuration: read each register and deploy each bit value
411 * of corresponding index in the destination array
412 */
413 reg_value = READ_REG(GTZC_TZSC1->PRIVCFGR1);
414 for (i = 0U; i < 32U; i++)
415 {
416 if (((reg_value & (1UL << i)) >> i) != 0U)
417 {
418 PeriphAttributes[i] |= GTZC_TZSC_PERIPH_PRIV;
419 }
420 else
421 {
422 PeriphAttributes[i] |= GTZC_TZSC_PERIPH_NPRIV;
423 }
424 }
425
426 reg_value = READ_REG(GTZC_TZSC1->PRIVCFGR2);
427 for (i = 32U; i < 64U; i++)
428 {
429 if (((reg_value & (1UL << (i - 32U))) >> (i - 32U)) != 0U)
430 {
431 PeriphAttributes[i] |= GTZC_TZSC_PERIPH_PRIV;
432 }
433 else
434 {
435 PeriphAttributes[i] |= GTZC_TZSC_PERIPH_NPRIV;
436 }
437 }
438
439 reg_value = READ_REG(GTZC_TZSC1->PRIVCFGR3);
440 for (i = 64U; i < GTZC_TZSC_PERIPH_NUMBER; i++)
441 {
442 if (((reg_value & (1UL << (i - 64U))) >> (i - 64U)) != 0U)
443 {
444 PeriphAttributes[i] |= GTZC_TZSC_PERIPH_PRIV;
445 }
446 else
447 {
448 PeriphAttributes[i] |= GTZC_TZSC_PERIPH_NPRIV;
449 }
450 }
451 }
452 else
453 {
454 /* common case where only one peripheral is configured */
455 #if defined (GTZC_TZIC1)
456 /* secure configuration */
457 register_address = (uint32_t) &(GTZC_TZSC1->SECCFGR1)
458 + (4U * GTZC_GET_REG_INDEX(PeriphId));
459
460 if (((READ_BIT(*(__IO uint32_t *)register_address,
461 1UL << GTZC_GET_PERIPH_POS(PeriphId))) >> GTZC_GET_PERIPH_POS(PeriphId))
462 != 0U)
463 {
464 *PeriphAttributes = GTZC_TZSC_PERIPH_SEC;
465 }
466 else
467 {
468 *PeriphAttributes = GTZC_TZSC_PERIPH_NSEC;
469 }
470 #endif /* defined (GTZC_TZIC1) */
471
472 /* privilege configuration */
473 register_address = (uint32_t) &(GTZC_TZSC1->PRIVCFGR1)
474 + (4U * GTZC_GET_REG_INDEX(PeriphId));
475
476 if (((READ_BIT(*(__IO uint32_t *)register_address,
477 1UL << GTZC_GET_PERIPH_POS(PeriphId))) >> GTZC_GET_PERIPH_POS(PeriphId))
478 != 0U)
479 {
480 *PeriphAttributes |= GTZC_TZSC_PERIPH_PRIV;
481 }
482 else
483 {
484 *PeriphAttributes |= GTZC_TZSC_PERIPH_NPRIV;
485 }
486 }
487 return HAL_OK;
488 }
489
490 /**
491 * @}
492 */
493
494
495 /** @defgroup GTZC_Exported_Functions_Group2 MPCWM Configuration functions
496 * @brief MPCWM Configuration functions
497 *
498 @verbatim
499 ==============================================================================
500 ##### MPCWM Configuration functions #####
501 ==============================================================================
502 [..]
503 This section provides functions allowing to configure MPCWM
504 MPCWM is Memory Protection Controller WaterMark
505 @endverbatim
506 * @{
507 */
508
509 /**
510 * @brief Configure a TZSC-MPCWM area.
511 * @param MemBaseAddress WM identifier.
512 * @param pMPCWM_Desc TZSC-MPCWM descriptor pointer.
513 * The structure description is available in @ref GTZC_Exported_Types.
514 * @retval HAL status.
515 */
HAL_GTZC_TZSC_MPCWM_ConfigMemAttributes(uint32_t MemBaseAddress,const MPCWM_ConfigTypeDef * pMPCWM_Desc)516 HAL_StatusTypeDef HAL_GTZC_TZSC_MPCWM_ConfigMemAttributes(uint32_t MemBaseAddress,
517 const MPCWM_ConfigTypeDef *pMPCWM_Desc)
518 {
519 uint32_t register_address;
520 uint32_t reg_value;
521 uint32_t size;
522 /* granularity value depends on selected memory */
523 uint32_t granularity = (MemBaseAddress == BKPSRAM_BASE) ? \
524 GTZC_TZSC_MPCWM_GRANULARITY_2 : GTZC_TZSC_MPCWM_GRANULARITY_1;
525
526 /* check entry parameters */
527 if ((pMPCWM_Desc->AreaId > GTZC_TZSC_MPCWM_ID2)
528 #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
529 || (((MemBaseAddress == FMC_BANK3) || (MemBaseAddress == BKPSRAM_BASE) || \
530 (MemBaseAddress == FMC_SDRAM_BANK_1) || (MemBaseAddress == FMC_SDRAM_BANK_2))
531 #else
532 || ((MemBaseAddress == BKPSRAM_BASE)
533 #endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
534 && (pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID2))
535 || ((pMPCWM_Desc->Offset % granularity) != 0U)
536 || ((pMPCWM_Desc->Length % granularity) != 0U))
537 {
538 return HAL_ERROR;
539 }
540
541 /* check descriptor content vs. memory capacity */
542 switch (MemBaseAddress)
543 {
544 #if defined(OCTOSPI1)
545 case OCTOSPI1_BASE:
546 size = GTZC_TZSC_MPCWM1_MEM_SIZE;
547 if (pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID1)
548 {
549 register_address = (uint32_t) &(GTZC_TZSC1->MPCWM1AR);
550 }
551 else
552 {
553 /* Here pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID2
554 * (Parameter already checked)
555 */
556 register_address = (uint32_t) &(GTZC_TZSC1->MPCWM1BR);
557 }
558 break;
559 #endif /* (OCTOSPI1) */
560 #if defined(FMC_BANK1)
561 case FMC_BANK1:
562 size = GTZC_TZSC_MPCWM2_MEM_SIZE;
563 if (pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID1)
564 {
565 register_address = (uint32_t) &(GTZC_TZSC1->MPCWM2AR);
566 }
567 else
568 {
569 /* Here pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID2
570 * (Parameter already checked)
571 */
572 register_address = (uint32_t) &(GTZC_TZSC1->MPCWM2BR);
573 }
574 break;
575 #endif /* defined(FMC_BANK1) */
576 #if defined(FMC_BANK3)
577 case FMC_BANK3:
578 /* Here pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID1
579 * (Parameter already checked)
580 */
581 size = GTZC_TZSC_MPCWM3_MEM_SIZE;
582 register_address = (uint32_t) &(GTZC_TZSC1->MPCWM3AR);
583 break;
584 #endif /* defined(FMC_BANK3) */
585 #if defined(FMC_SDRAM_BANK_1)
586 case FMC_SDRAM_BANK_1:
587 /* Here pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID1
588 * (Parameter already checked)
589 */
590 size = GTZC_TZSC_MPCWM3_MEM_SIZE;
591 register_address = (uint32_t) &(GTZC_TZSC1->MPCWM3AR);
592 break;
593 #endif /* (FMC_SDRAM_BANK_1) */
594 #if defined(BKPSRAM_BASE)
595 case BKPSRAM_BASE:
596 /* Here pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID1
597 * (Parameter already checked)
598 */
599 size = GTZC_TZSC_MPCWM4_MEM_SIZE;
600 register_address = (uint32_t) &(GTZC_TZSC1->MPCWM4AR);
601 break;
602 #endif /* (BKPSRAM_BASE) */
603 #if defined(FMC_SDRAM_BANK_2)
604 case FMC_SDRAM_BANK_2:
605 /* Here pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID1
606 * (Parameter already checked)
607 */
608 size = GTZC_TZSC_MPCWM4_SDRAM_MEM_SIZE ;
609 register_address = (uint32_t) &(GTZC_TZSC1->MPCWM4AR);
610 break;
611 #endif /* (FMC_SDRAM_BANK_2) */
612 default:
613 return HAL_ERROR;
614 break;
615 }
616
617 if ((pMPCWM_Desc->Offset > size)
618 || ((pMPCWM_Desc->Offset
619 + pMPCWM_Desc->Length)
620 > size))
621 {
622 return HAL_ERROR;
623 }
624
625 /* Write watermark start and length value */
626 reg_value = ((pMPCWM_Desc->Offset / granularity)
627 << GTZC_TZSC_MPCWMR_SUBZ_START_Pos) & GTZC_TZSC_MPCWMR_SUBZ_START_Msk;
628 reg_value |= ((pMPCWM_Desc->Length / granularity)
629 << GTZC_TZSC_MPCWMR_SUBZ_LENGTH_Pos) & GTZC_TZSC_MPCWMR_SUBZ_LENGTH_Msk;
630 MODIFY_REG(*(__IO uint32_t *)register_address, GTZC_TZSC_MPCWMR_SUBZ_START_Msk | \
631 GTZC_TZSC_MPCWMR_SUBZ_LENGTH_Msk, reg_value);
632
633 #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
634 /* Write watermark configuration value */
635 reg_value = (pMPCWM_Desc->Attribute << GTZC_TZSC_MPCWM_CFGR_SEC_Pos) | \
636 pMPCWM_Desc->Lock | \
637 pMPCWM_Desc->AreaStatus;
638 MODIFY_REG(*(__IO uint32_t *)(register_address - 4U), (GTZC_TZSC_MPCWM_CFGR_PRIV | GTZC_TZSC_MPCWM_CFGR_SEC | \
639 GTZC_TZSC_MPCWM_CFGR_SRLOCK | GTZC_TZSC_MPCWM_CFGR_SREN), \
640 reg_value);
641 #else
642 /* Write watermark configuration value */
643 reg_value = (pMPCWM_Desc->Attribute << (GTZC_TZSC_MPCWM_CFGR_PRIV_Pos - 1U)) | \
644 pMPCWM_Desc->Lock | \
645 pMPCWM_Desc->AreaStatus;
646 MODIFY_REG(*(__IO uint32_t *)(register_address - 4U), (GTZC_TZSC_MPCWM_CFGR_PRIV | GTZC_TZSC_MPCWM_CFGR_SRLOCK | \
647 GTZC_TZSC_MPCWM_CFGR_SREN), reg_value);
648 #endif /* (__ARM_FEATURE_CMSE) */
649
650 return HAL_OK;
651 }
652
653 /**
654 * @brief Get a TZSC-MPCWM area configuration.
655 * @param MemBaseAddress WM identifier.
656 * @param pMPCWM_Desc pointer to a TZSC-MPCWM descriptor.
657 * When the WaterMark memory supports two sub-regions A and B. pMPCWM_Desc argument must point to an array of
658 * two MPCWM_ConfigTypeDef structures.
659 * The structure description is available in @ref GTZC_Exported_Types.
660 * @retval HAL status.
661 */
HAL_GTZC_TZSC_MPCWM_GetConfigMemAttributes(uint32_t MemBaseAddress,MPCWM_ConfigTypeDef * pMPCWM_Desc)662 HAL_StatusTypeDef HAL_GTZC_TZSC_MPCWM_GetConfigMemAttributes(uint32_t MemBaseAddress, MPCWM_ConfigTypeDef *pMPCWM_Desc)
663 {
664 uint32_t register_address;
665 uint32_t reg_value;
666 uint32_t granularity = (MemBaseAddress == BKPSRAM_BASE) ? \
667 GTZC_TZSC_MPCWM_GRANULARITY_2 : GTZC_TZSC_MPCWM_GRANULARITY_1;
668
669 /* firstly take care of the first area, present on all MPCWM sub-blocks */
670 switch (MemBaseAddress)
671 {
672 #if defined(OCTOSPI1)
673 case OCTOSPI1_BASE:
674 register_address = (uint32_t) &(GTZC_TZSC1->MPCWM1AR);
675 break;
676 #endif /* (OCTOSPI1) */
677 #if defined(FMC_BANK1)
678 case FMC_BANK1:
679 register_address = (uint32_t) &(GTZC_TZSC1->MPCWM2AR);
680 break;
681 #endif /* defined(FMC_BANK1) */
682 #if defined(FMC_BANK3)
683 case FMC_BANK3:
684 register_address = (uint32_t) &(GTZC_TZSC1->MPCWM3AR);
685 break;
686 #endif /* defined(FMC_BANK3) */
687 #if defined(FMC_SDRAM_BANK_1)
688 case FMC_SDRAM_BANK_1:
689 register_address = (uint32_t) &(GTZC_TZSC1->MPCWM3AR);
690 break;
691 #endif /* (FMC_SDRAM_BANK_1) */
692 #if defined(BKPSRAM_BASE)
693 case BKPSRAM_BASE:
694 register_address = (uint32_t) &(GTZC_TZSC1->MPCWM4AR);
695 break;
696 #endif /* (BKPSRAM_BASE) */
697 #if defined(FMC_SDRAM_BANK_2)
698 case FMC_SDRAM_BANK_2:
699 register_address = (uint32_t) &(GTZC_TZSC1->MPCWM4AR);
700 break;
701 #endif /* (FMC_SDRAM_BANK_2) */
702 default:
703 return HAL_ERROR;
704 break;
705 }
706
707 /* read register and update the descriptor for first area*/
708 reg_value = READ_REG(*(__IO uint32_t *)register_address);
709 pMPCWM_Desc[0].AreaId = GTZC_TZSC_MPCWM_ID1;
710 pMPCWM_Desc[0].Offset = ((reg_value & GTZC_TZSC_MPCWMR_SUBZ_START_Msk)
711 >> GTZC_TZSC_MPCWMR_SUBZ_START_Pos) * granularity;
712 pMPCWM_Desc[0].Length = ((reg_value & GTZC_TZSC_MPCWMR_SUBZ_LENGTH_Msk)
713 >> GTZC_TZSC_MPCWMR_SUBZ_LENGTH_Pos) * granularity;
714
715 /* read configuration register and update the descriptor for first area*/
716 reg_value = READ_REG(*(__IO uint32_t *)(register_address - 4U));
717 #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
718 pMPCWM_Desc[0].Attribute = (reg_value & (GTZC_TZSC_MPCWM_CFGR_PRIV | \
719 GTZC_TZSC_MPCWM_CFGR_SEC)) >> GTZC_TZSC_MPCWM_CFGR_SEC_Pos;
720 #else
721 pMPCWM_Desc[0].Attribute = (reg_value & GTZC_TZSC_MPCWM_CFGR_PRIV) >> (GTZC_TZSC_MPCWM_CFGR_PRIV_Pos - 1U);
722 #endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
723 pMPCWM_Desc[0].Lock = reg_value & GTZC_TZSC_MPCWM_CFGR_SRLOCK;
724 pMPCWM_Desc[0].AreaStatus = reg_value & GTZC_TZSC_MPCWM_CFGR_SREN;
725
726 #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
727 if ((MemBaseAddress == OCTOSPI1_BASE) || (MemBaseAddress == FMC_BANK1))
728 {
729 if (MemBaseAddress == OCTOSPI1_BASE)
730 {
731 register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM1BR);
732 }
733 else
734 {
735 register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM2BR);
736 }
737
738 /* read register and update the descriptor for second area*/
739 reg_value = READ_REG(*(__IO uint32_t *)register_address);
740 pMPCWM_Desc[1].AreaId = GTZC_TZSC_MPCWM_ID2;
741 pMPCWM_Desc[1].Offset = ((reg_value & GTZC_TZSC_MPCWMR_SUBZ_START_Msk)
742 >> GTZC_TZSC_MPCWMR_SUBZ_START_Pos) * granularity;
743 pMPCWM_Desc[1].Length = ((reg_value & GTZC_TZSC_MPCWMR_SUBZ_LENGTH_Msk)
744 >> GTZC_TZSC_MPCWMR_SUBZ_LENGTH_Pos) * granularity;
745
746 /* read configuration register and update the descriptor for second area*/
747 reg_value = READ_REG(*(__IO uint32_t *)(register_address - 4U));
748 pMPCWM_Desc[1].Attribute = (reg_value & (GTZC_TZSC_MPCWM_CFGR_PRIV | \
749 GTZC_TZSC_MPCWM_CFGR_SEC)) >> GTZC_TZSC_MPCWM_CFGR_SEC_Pos;
750 pMPCWM_Desc[1].Lock = reg_value & GTZC_TZSC_MPCWM_CFGR_SRLOCK;
751 pMPCWM_Desc[1].AreaStatus = reg_value & GTZC_TZSC_MPCWM_CFGR_SREN;
752 }
753 #endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
754
755 return HAL_OK;
756 }
757
758 #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
759 /**
760 * @}
761 */
762
763 /** @defgroup GTZC_Exported_Functions_Group3 TZSC Lock functions
764 * @brief TZSC Lock functions
765 *
766 @verbatim
767 ==============================================================================
768 ##### TZSC Lock functions #####
769 ==============================================================================
770 [..]
771 This section provides functions allowing to manage the TZSC (TrustZone
772 Security Controller) lock. It includes lock enable, and current value read.
773 @endverbatim
774 * @{
775 */
776
777 /**
778 * @brief Lock TZSC configuration.
779 * @note This function locks the configuration of TZSC_SECCFGRx and TZSC_PRIVCFGRx
780 * registers until next reset
781 * @param TZSC_Instance TZSC sub-block instance.
782 */
HAL_GTZC_TZSC_Lock(GTZC_TZSC_TypeDef * TZSC_Instance)783 void HAL_GTZC_TZSC_Lock(GTZC_TZSC_TypeDef *TZSC_Instance)
784 {
785 SET_BIT(TZSC_Instance->CR, GTZC_TZSC_CR_LCK_Msk);
786 }
787
788 /**
789 * @brief Get TZSC configuration lock state.
790 * @param TZSC_Instance TZSC sub-block instance.
791 * @retval Lock State (GTZC_TZSC_LOCK_OFF or GTZC_TZSC_LOCK_ON)
792 */
HAL_GTZC_TZSC_GetLock(const GTZC_TZSC_TypeDef * TZSC_Instance)793 uint32_t HAL_GTZC_TZSC_GetLock(const GTZC_TZSC_TypeDef *TZSC_Instance)
794 {
795 return READ_BIT(TZSC_Instance->CR, GTZC_TZSC_CR_LCK_Msk);
796 }
797
798 /**
799 * @}
800 */
801 #endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
802
803 /** @defgroup GTZC_Exported_Functions_Group4 MPCBB Configuration functions
804 * @brief MPCBB Configuration functions
805 *
806 @verbatim
807 ==============================================================================
808 ##### MPCBB Configuration functions #####
809 ==============================================================================
810 [..]
811 This section provides functions allowing to configure MPCBB
812 MPCBB is Memory Protection Controller Block Base
813 @endverbatim
814 * @{
815 */
816
817 /**
818 * @brief Set a complete MPCBB configuration on the SRAM passed as parameter.
819 * @param MemBaseAddress MPCBB identifier.
820 * @param pMPCBB_desc pointer to MPCBB descriptor.
821 * The structure description is available in @ref GTZC_Exported_Types.
822 * @retval HAL status.
823 */
HAL_GTZC_MPCBB_ConfigMem(uint32_t MemBaseAddress,const MPCBB_ConfigTypeDef * pMPCBB_desc)824 HAL_StatusTypeDef HAL_GTZC_MPCBB_ConfigMem(uint32_t MemBaseAddress,
825 const MPCBB_ConfigTypeDef *pMPCBB_desc)
826 {
827 GTZC_MPCBB_TypeDef *mpcbb_ptr;
828 uint32_t mem_size;
829 uint32_t size_in_superblocks;
830 uint32_t i;
831
832 #if defined (GTZC_MPCBB3)
833 /* check entry parameters */
834 if ((!(IS_GTZC_BASE_ADDRESS(SRAM1, MemBaseAddress))
835 && !(IS_GTZC_BASE_ADDRESS(SRAM2, MemBaseAddress))
836 && !(IS_GTZC_BASE_ADDRESS(SRAM3, MemBaseAddress)))
837 || ((pMPCBB_desc->SecureRWIllegalMode != GTZC_MPCBB_SRWILADIS_ENABLE)
838 && (pMPCBB_desc->SecureRWIllegalMode != GTZC_MPCBB_SRWILADIS_DISABLE))
839 || ((pMPCBB_desc->InvertSecureState != GTZC_MPCBB_INVSECSTATE_NOT_INVERTED)
840 && (pMPCBB_desc->InvertSecureState != GTZC_MPCBB_INVSECSTATE_INVERTED)))
841 #else
842 if ((!(IS_GTZC_BASE_ADDRESS(SRAM1, MemBaseAddress))
843 && !(IS_GTZC_BASE_ADDRESS(SRAM2, MemBaseAddress)))
844 || ((pMPCBB_desc->SecureRWIllegalMode != GTZC_MPCBB_SRWILADIS_ENABLE)
845 && (pMPCBB_desc->SecureRWIllegalMode != GTZC_MPCBB_SRWILADIS_DISABLE))
846 || ((pMPCBB_desc->InvertSecureState != GTZC_MPCBB_INVSECSTATE_NOT_INVERTED)
847 && (pMPCBB_desc->InvertSecureState != GTZC_MPCBB_INVSECSTATE_INVERTED)))
848 #endif /* defined (GTZC_MPCBB3) */
849 {
850 return HAL_ERROR;
851 }
852
853 if (IS_GTZC_BASE_ADDRESS(SRAM1, MemBaseAddress))
854 {
855 mpcbb_ptr = GTZC_MPCBB1;
856 mem_size = GTZC_MEM_SIZE(SRAM1);
857 }
858 #if defined (GTZC_MPCBB3)
859 else if (IS_GTZC_BASE_ADDRESS(SRAM2, MemBaseAddress))
860 {
861 mpcbb_ptr = GTZC_MPCBB2;
862 mem_size = GTZC_MEM_SIZE(SRAM2);
863 }
864 else
865 {
866 mpcbb_ptr = GTZC_MPCBB3;
867 mem_size = GTZC_MEM_SIZE(SRAM3);
868 }
869 #else
870 else
871 {
872 mpcbb_ptr = GTZC_MPCBB2;
873 mem_size = GTZC_MEM_SIZE(SRAM2);
874 }
875 #endif /* defined (GTZC_MPCBB3) */
876
877 /* translate mem_size in number of super-blocks */
878 size_in_superblocks = (mem_size / GTZC_MPCBB_SUPERBLOCK_SIZE);
879
880 /* write PRIVCFGR register information */
881 for (i = 0U; i < size_in_superblocks; i++)
882 {
883 WRITE_REG(mpcbb_ptr->PRIVCFGR[i],
884 pMPCBB_desc->AttributeConfig.MPCBB_PrivConfig_array[i]);
885 }
886
887 #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
888 uint32_t size_mask;
889 uint32_t reg_value;
890
891 /* write InvertSecureState and SecureRWIllegalMode properties */
892 reg_value = pMPCBB_desc->InvertSecureState;
893 reg_value |= pMPCBB_desc->SecureRWIllegalMode;
894
895 /* write SECCFGR register information */
896 for (i = 0U; i < size_in_superblocks; i++)
897 {
898 WRITE_REG(mpcbb_ptr->SECCFGR[i],
899 pMPCBB_desc->AttributeConfig.MPCBB_SecConfig_array[i]);
900 }
901
902 if (size_in_superblocks == 32U)
903 {
904 size_mask = 0xFFFFFFFFU;
905 }
906 else
907 {
908 size_mask = (1UL << size_in_superblocks) - 1U;
909 }
910 /* limitation: code not portable with memory > 512K */
911 MODIFY_REG(mpcbb_ptr->CFGLOCKR1, size_mask, pMPCBB_desc->AttributeConfig.MPCBB_LockConfig_array[0]);
912
913 /* write configuration and lock register information */
914 MODIFY_REG(mpcbb_ptr->CR,
915 GTZC_MPCBB_CR_INVSECSTATE_Msk | GTZC_MPCBB_CR_SRWILADIS_Msk, reg_value);
916
917 #endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
918
919 return HAL_OK;
920 }
921
922 /**
923 * @brief Get a complete MPCBB configuration on the SRAM passed as parameter.
924 * @param MemBaseAddress MPCBB identifier.
925 * @param pMPCBB_desc pointer to a MPCBB descriptor.
926 * The structure description is available in @ref GTZC_Exported_Types.
927 * @retval HAL status.
928 */
HAL_GTZC_MPCBB_GetConfigMem(uint32_t MemBaseAddress,MPCBB_ConfigTypeDef * pMPCBB_desc)929 HAL_StatusTypeDef HAL_GTZC_MPCBB_GetConfigMem(uint32_t MemBaseAddress,
930 MPCBB_ConfigTypeDef *pMPCBB_desc)
931 {
932 GTZC_MPCBB_TypeDef *mpcbb_ptr;
933 uint32_t mem_size;
934 uint32_t size_in_superblocks;
935 uint32_t i;
936
937 /* check entry parameters */
938 #if defined (GTZC_MPCBB3)
939 if (!(IS_GTZC_BASE_ADDRESS(SRAM1, MemBaseAddress))
940 && !(IS_GTZC_BASE_ADDRESS(SRAM2, MemBaseAddress))
941 && !(IS_GTZC_BASE_ADDRESS(SRAM3, MemBaseAddress)))
942 #else
943 if (!(IS_GTZC_BASE_ADDRESS(SRAM1, MemBaseAddress))
944 && !(IS_GTZC_BASE_ADDRESS(SRAM2, MemBaseAddress)))
945 #endif /* defined (GTZC_MPCBB3) */
946 {
947 return HAL_ERROR;
948 }
949
950 /* read InvertSecureState and SecureRWIllegalMode properties */
951 /* assume their Position/Mask is identical for all sub-blocks */
952 if (IS_GTZC_BASE_ADDRESS(SRAM1, MemBaseAddress))
953 {
954 mpcbb_ptr = GTZC_MPCBB1;
955 mem_size = GTZC_MEM_SIZE(SRAM1);
956 }
957 #if defined (GTZC_MPCBB3)
958 else if (IS_GTZC_BASE_ADDRESS(SRAM2, MemBaseAddress))
959 {
960 mpcbb_ptr = GTZC_MPCBB2;
961 mem_size = GTZC_MEM_SIZE(SRAM2);
962 }
963 else
964 {
965 mpcbb_ptr = GTZC_MPCBB3;
966 mem_size = GTZC_MEM_SIZE(SRAM3);
967 }
968 #else
969 else
970 {
971 mpcbb_ptr = GTZC_MPCBB2;
972 mem_size = GTZC_MEM_SIZE(SRAM2);
973 }
974 #endif /* */
975
976 /* translate mem_size in number of super-blocks */
977 size_in_superblocks = (mem_size / GTZC_MPCBB_SUPERBLOCK_SIZE);
978
979 #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
980 uint32_t reg_value;
981 uint32_t size_mask;
982
983 /* read configuration and lock register information */
984 reg_value = READ_REG(mpcbb_ptr->CR);
985 pMPCBB_desc->InvertSecureState = (reg_value & GTZC_MPCBB_CR_INVSECSTATE_Msk);
986 pMPCBB_desc->SecureRWIllegalMode = (reg_value & GTZC_MPCBB_CR_SRWILADIS_Msk);
987 if (size_in_superblocks == 32U)
988 {
989 size_mask = 0xFFFFFFFFU;
990 }
991 else
992 {
993 size_mask = (1UL << size_in_superblocks) - 1U;
994 }
995 /* limitation: code not portable with memory > 512K */
996 pMPCBB_desc->AttributeConfig.MPCBB_LockConfig_array[0] = READ_REG(mpcbb_ptr->CFGLOCKR1)
997 & size_mask;
998 #endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
999
1000 /* read SECCFGR / PRIVCFGR registers information */
1001 for (i = 0U; i < size_in_superblocks; i++)
1002 {
1003 #if defined (GTZC_TZIC1)
1004 pMPCBB_desc->AttributeConfig.MPCBB_SecConfig_array[i] = mpcbb_ptr->SECCFGR[i];
1005 #endif /* defined (GTZC_TZIC1) */
1006 pMPCBB_desc->AttributeConfig.MPCBB_PrivConfig_array[i] = mpcbb_ptr->PRIVCFGR[i];
1007 }
1008
1009 return HAL_OK;
1010 }
1011
1012 /**
1013 * @brief Set a MPCBB attribute configuration on the SRAM passed as parameter
1014 * for a number of blocks.
1015 * @param MemAddress MPCBB identifier, and start block to configure
1016 * (must be 512 Bytes aligned).
1017 * @param NbBlocks Number of blocks to configure
1018 * (Block size is 512 Bytes).
1019 * @param pMemAttributes pointer to an array (containing "NbBlocks" elements),
1020 * with each element must be GTZC_MCPBB_BLOCK_NSEC or GTZC_MCPBB_BLOCK_SEC,
1021 * and GTZC_MCPBB_BLOCK_NPRIV or GTZC_MCPBB_BLOCK_PRIV.
1022 * @retval HAL status.
1023 */
HAL_GTZC_MPCBB_ConfigMemAttributes(uint32_t MemAddress,uint32_t NbBlocks,const uint32_t * pMemAttributes)1024 HAL_StatusTypeDef HAL_GTZC_MPCBB_ConfigMemAttributes(uint32_t MemAddress,
1025 uint32_t NbBlocks,
1026 const uint32_t *pMemAttributes)
1027 {
1028 GTZC_MPCBB_TypeDef *mpcbb_ptr;
1029 uint32_t base_address;
1030 uint32_t end_address;
1031 uint32_t block_start;
1032 uint32_t offset_reg_start;
1033 uint32_t offset_bit_start;
1034 uint32_t i;
1035 uint32_t do_attr_change;
1036
1037 /* firstly check that MemAddress is well 512 Bytes aligned */
1038 if ((MemAddress % GTZC_MPCBB_BLOCK_SIZE) != 0U)
1039 {
1040 return HAL_ERROR;
1041 }
1042
1043 /* check entry parameters and deduce physical base address */
1044 end_address = MemAddress + (NbBlocks * GTZC_MPCBB_BLOCK_SIZE) - 1U;
1045 if (((IS_ADDRESS_IN_NS(SRAM1, MemAddress))
1046 && (IS_ADDRESS_IN_NS(SRAM1, end_address))) != 0U)
1047 {
1048 mpcbb_ptr = GTZC_MPCBB1;
1049 base_address = SRAM1_BASE_NS;
1050 }
1051 #if defined (GTZC_TZIC1)
1052 else if (((IS_ADDRESS_IN_S(SRAM1, MemAddress))
1053 && (IS_ADDRESS_IN_S(SRAM1, end_address))) != 0U)
1054 {
1055 mpcbb_ptr = GTZC_MPCBB1;
1056 base_address = SRAM1_BASE_S;
1057 }
1058 #endif /* defined (GTZC_TZIC1) */
1059 else if (((IS_ADDRESS_IN_NS(SRAM2, MemAddress))
1060 && (IS_ADDRESS_IN_NS(SRAM2, end_address))) != 0U)
1061 {
1062 mpcbb_ptr = GTZC_MPCBB2;
1063 base_address = SRAM2_BASE_NS;
1064 }
1065 #if defined (GTZC_TZIC1)
1066 else if (((IS_ADDRESS_IN_S(SRAM2, MemAddress))
1067 && (IS_ADDRESS_IN_S(SRAM2, end_address))) != 0U)
1068 {
1069 mpcbb_ptr = GTZC_MPCBB2;
1070 base_address = SRAM2_BASE_S;
1071 }
1072 #endif /* defined (GTZC_TZIC1) */
1073 #if defined (GTZC_MPCBB3)
1074 else if (((IS_ADDRESS_IN_NS(SRAM3, MemAddress))
1075 && (IS_ADDRESS_IN_NS(SRAM3, end_address))) != 0U)
1076 {
1077 mpcbb_ptr = GTZC_MPCBB3;
1078 base_address = SRAM3_BASE_NS;
1079 }
1080 else if (((IS_ADDRESS_IN_S(SRAM3, MemAddress))
1081 && (IS_ADDRESS_IN_S(SRAM3, end_address))) != 0U)
1082 {
1083 mpcbb_ptr = GTZC_MPCBB3;
1084 base_address = SRAM3_BASE_S;
1085 }
1086 #endif /* defined (GTZC_MPCBB3) */
1087 else
1088 {
1089 return HAL_ERROR;
1090 }
1091
1092 /* get start coordinates of the configuration */
1093 block_start = (MemAddress - base_address) / GTZC_MPCBB_BLOCK_SIZE;
1094 offset_reg_start = block_start / 32U;
1095 offset_bit_start = block_start % 32U;
1096
1097 for (i = 0U; i < NbBlocks; i++)
1098 {
1099 /* Indicate change done for protection attributes */
1100 do_attr_change = 0U;
1101
1102 #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
1103 /* secure configuration */
1104 if ((pMemAttributes[i] & GTZC_MCPBB_BLOCK_SEC) == GTZC_MCPBB_BLOCK_SEC)
1105 {
1106 SET_BIT(mpcbb_ptr->SECCFGR[offset_reg_start],
1107 1UL << (offset_bit_start % 32U));
1108 do_attr_change = 1U;
1109 }
1110 else if ((pMemAttributes[i] & GTZC_MCPBB_BLOCK_NSEC) == GTZC_MCPBB_BLOCK_NSEC)
1111 {
1112 CLEAR_BIT(mpcbb_ptr->SECCFGR[offset_reg_start],
1113 1UL << (offset_bit_start % 32U));
1114 do_attr_change = 1U;
1115 }
1116 else
1117 {
1118 /* nothing to do */
1119 }
1120 #endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
1121
1122 /* privilege configuration */
1123 if ((pMemAttributes[i] & GTZC_MCPBB_BLOCK_PRIV) == GTZC_MCPBB_BLOCK_PRIV)
1124 {
1125 SET_BIT(mpcbb_ptr->PRIVCFGR[offset_reg_start],
1126 1UL << (offset_bit_start % 32U));
1127 }
1128 else if ((pMemAttributes[i] & GTZC_MCPBB_BLOCK_NPRIV) == GTZC_MCPBB_BLOCK_NPRIV)
1129 {
1130 CLEAR_BIT(mpcbb_ptr->PRIVCFGR[offset_reg_start],
1131 1UL << (offset_bit_start % 32U));
1132 }
1133 else
1134 {
1135 /* if no change is done for security and privilege attributes: break the loop */
1136 if (do_attr_change == 0U)
1137 {
1138 break;
1139 }
1140 }
1141
1142 offset_bit_start++;
1143 if (offset_bit_start == 32U)
1144 {
1145 offset_bit_start = 0U;
1146 offset_reg_start++;
1147 }
1148 }
1149
1150 /* an unexpected value in pMemAttributes array leads to error status */
1151 if (i != NbBlocks)
1152 {
1153 return HAL_ERROR;
1154 }
1155
1156 return HAL_OK;
1157 }
1158
1159 /**
1160 * @brief Get a MPCBB attribute configuration on the SRAM passed as parameter
1161 * for a number of blocks.
1162 * @param MemAddress MPCBB identifier, and start block to get configuration
1163 * (must be 512 Bytes aligned).
1164 * @param NbBlocks Number of blocks to get configuration.
1165 * @param pMemAttributes pointer to an array (containing "NbBlocks" elements),
1166 * with each element will be GTZC_MCPBB_BLOCK_NSEC or GTZC_MCPBB_BLOCK_SEC,
1167 * and GTZC_MCPBB_BLOCK_NPRIV or GTZC_MCPBB_BLOCK_PRIV.
1168 * @retval HAL status.
1169 */
HAL_GTZC_MPCBB_GetConfigMemAttributes(uint32_t MemAddress,uint32_t NbBlocks,uint32_t * pMemAttributes)1170 HAL_StatusTypeDef HAL_GTZC_MPCBB_GetConfigMemAttributes(uint32_t MemAddress,
1171 uint32_t NbBlocks,
1172 uint32_t *pMemAttributes)
1173 {
1174 GTZC_MPCBB_TypeDef *mpcbb_ptr;
1175 uint32_t base_address;
1176 uint32_t end_address;
1177 uint32_t block_start;
1178 uint32_t offset_reg_start;
1179 uint32_t offset_bit_start;
1180 uint32_t i;
1181
1182 /* firstly check that MemAddress is well 512 Bytes aligned */
1183 if ((MemAddress % GTZC_MPCBB_BLOCK_SIZE) != 0U)
1184 {
1185 return HAL_ERROR;
1186 }
1187
1188 /* check entry parameters and deduce physical base address */
1189 end_address = MemAddress + (NbBlocks * GTZC_MPCBB_BLOCK_SIZE) - 1U;
1190 if ((IS_ADDRESS_IN_NS(SRAM1, MemAddress))
1191 && (IS_ADDRESS_IN_NS(SRAM1, end_address)))
1192 {
1193 mpcbb_ptr = GTZC_MPCBB1_NS;
1194 base_address = SRAM1_BASE_NS;
1195 }
1196 #if defined (GTZC_TZIC1)
1197 else if ((IS_ADDRESS_IN_S(SRAM1, MemAddress))
1198 && (IS_ADDRESS_IN_S(SRAM1, end_address)))
1199 {
1200 mpcbb_ptr = GTZC_MPCBB1_S;
1201 base_address = SRAM1_BASE_S;
1202 }
1203 #endif /* defined (GTZC_TZIC1) */
1204 else if ((IS_ADDRESS_IN_NS(SRAM2, MemAddress))
1205 && (IS_ADDRESS_IN_NS(SRAM2, end_address)))
1206 {
1207 mpcbb_ptr = GTZC_MPCBB2_NS;
1208 base_address = SRAM2_BASE_NS;
1209 }
1210 #if defined (GTZC_TZIC1)
1211 else if ((IS_ADDRESS_IN_S(SRAM2, MemAddress))
1212 && (IS_ADDRESS_IN_S(SRAM2, end_address)))
1213 {
1214 mpcbb_ptr = GTZC_MPCBB2_S;
1215 base_address = SRAM2_BASE_S;
1216 }
1217 #endif /* defined (GTZC_TZIC1) */
1218 #if defined (GTZC_MPCBB3)
1219 else if ((IS_ADDRESS_IN_NS(SRAM3, MemAddress))
1220 && (IS_ADDRESS_IN_NS(SRAM3, end_address)))
1221 {
1222 mpcbb_ptr = GTZC_MPCBB3_NS;
1223 base_address = SRAM3_BASE_NS;
1224 }
1225 else if ((IS_ADDRESS_IN_S(SRAM3, MemAddress))
1226 && (IS_ADDRESS_IN_S(SRAM3, end_address)))
1227 {
1228 mpcbb_ptr = GTZC_MPCBB3_S;
1229 base_address = SRAM3_BASE_S;
1230 }
1231 #endif /* defined (GTZC_MPCBB3) */
1232 else
1233 {
1234 return HAL_ERROR;
1235 }
1236
1237 /* get start coordinates of the configuration */
1238 block_start = (MemAddress - base_address) / GTZC_MPCBB_BLOCK_SIZE;
1239 offset_reg_start = block_start / 32U;
1240 offset_bit_start = block_start % 32U;
1241
1242 for (i = 0U; i < NbBlocks; i++)
1243 {
1244 #if defined (GTZC_TZIC1)
1245 pMemAttributes[i] = (READ_BIT(mpcbb_ptr->SECCFGR[offset_reg_start],
1246 1UL << (offset_bit_start % 32U))
1247 >> (offset_bit_start % 32U)) | GTZC_ATTR_SEC_MASK;
1248 #endif /* defined (GTZC_TZIC1) */
1249 pMemAttributes[i] |= ((READ_BIT(mpcbb_ptr->PRIVCFGR[offset_reg_start],
1250 1UL << (offset_bit_start % 32U))
1251 >> (offset_bit_start % 32U)) << 1U) | GTZC_ATTR_PRIV_MASK;
1252
1253 offset_bit_start++;
1254 if (offset_bit_start == 32U)
1255 {
1256 offset_bit_start = 0U;
1257 offset_reg_start++;
1258 }
1259 }
1260
1261 return HAL_OK;
1262 }
1263
1264 #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
1265 /**
1266 * @brief Lock MPCBB super-blocks on the SRAM passed as parameter.
1267 * @param MemAddress MPCBB start-address of super-block to configure
1268 * (must be 16KBytes aligned).
1269 * @param NbSuperBlocks Number of super-blocks to configure.
1270 * @param pLockAttributes pointer to an array (containing "NbSuperBlocks" elements),
1271 * with for each element:
1272 * value 0 super-block is unlocked, value 1 super-block is locked
1273 * (corresponds to GTZC_MCPBB_SUPERBLOCK_UNLOCKED and
1274 * GTZC_MCPBB_SUPERBLOCK_LOCKED values).
1275 * @retval HAL status.
1276 */
HAL_GTZC_MPCBB_LockConfig(uint32_t MemAddress,uint32_t NbSuperBlocks,const uint32_t * pLockAttributes)1277 HAL_StatusTypeDef HAL_GTZC_MPCBB_LockConfig(uint32_t MemAddress,
1278 uint32_t NbSuperBlocks,
1279 const uint32_t *pLockAttributes)
1280 {
1281 __IO uint32_t *reg_mpcbb;
1282 uint32_t base_address;
1283 uint32_t superblock_start;
1284 uint32_t offset_bit_start;
1285 uint32_t i;
1286
1287 /* firstly check that MemAddress is well 16KBytes aligned */
1288 if ((MemAddress % GTZC_MPCBB_SUPERBLOCK_SIZE) != 0U)
1289 {
1290 return HAL_ERROR;
1291 }
1292
1293 /* check entry parameters */
1294 if ((IS_ADDRESS_IN(SRAM1, MemAddress))
1295 && (IS_ADDRESS_IN(SRAM1, (MemAddress
1296 + (NbSuperBlocks * GTZC_MPCBB_SUPERBLOCK_SIZE)
1297 - 1U))))
1298 {
1299 base_address = GTZC_BASE_ADDRESS(SRAM1);
1300 /* limitation: code not portable with memory > 512K */
1301 reg_mpcbb = (__IO uint32_t *)>ZC_MPCBB1_S->CFGLOCKR1;
1302 }
1303 else if ((IS_ADDRESS_IN(SRAM2, MemAddress))
1304 && (IS_ADDRESS_IN(SRAM2, (MemAddress
1305 + (NbSuperBlocks * GTZC_MPCBB_SUPERBLOCK_SIZE)
1306 - 1U))))
1307 {
1308 base_address = GTZC_BASE_ADDRESS(SRAM2);
1309 /* limitation: code not portable with memory > 256K */
1310 reg_mpcbb = (__IO uint32_t *)>ZC_MPCBB2_S->CFGLOCKR1;
1311 }
1312 else if ((IS_ADDRESS_IN(SRAM3, MemAddress))
1313 && (IS_ADDRESS_IN(SRAM3, (MemAddress
1314 + (NbSuperBlocks * GTZC_MPCBB_SUPERBLOCK_SIZE)
1315 - 1U))))
1316 {
1317 base_address = GTZC_BASE_ADDRESS(SRAM3);
1318 /* limitation: code not portable with memory > 512K */
1319 reg_mpcbb = (__IO uint32_t *)>ZC_MPCBB3_S->CFGLOCKR1;
1320 }
1321
1322 else
1323 {
1324 return HAL_ERROR;
1325 }
1326
1327 /* get start coordinates of the configuration */
1328 superblock_start = (MemAddress - base_address) / GTZC_MPCBB_SUPERBLOCK_SIZE;
1329 offset_bit_start = superblock_start % 32U;
1330
1331 for (i = 0U; i < NbSuperBlocks; i++)
1332 {
1333 if (pLockAttributes[i] == GTZC_MCPBB_SUPERBLOCK_LOCKED)
1334 {
1335 SET_BIT(*reg_mpcbb, 1UL << (offset_bit_start % 32U));
1336 }
1337 else if (pLockAttributes[i] == GTZC_MCPBB_SUPERBLOCK_UNLOCKED)
1338 {
1339 CLEAR_BIT(*reg_mpcbb, 1UL << (offset_bit_start % 32U));
1340 }
1341 else
1342 {
1343 break;
1344 }
1345
1346 offset_bit_start++;
1347 }
1348
1349 /* an unexpected value in pLockAttributes array leads to an error status */
1350 if (i != NbSuperBlocks)
1351 {
1352 return HAL_ERROR;
1353 }
1354
1355 return HAL_OK;
1356 }
1357
1358 /**
1359 * @brief Get MPCBB super-blocks lock configuration on the SRAM passed as parameter.
1360 * @param MemAddress MPCBB start-address of super-block to get configuration
1361 * (must be 16KBytes aligned).
1362 * @param NbSuperBlocks Number of super-blocks to get configuration.
1363 * @param pLockAttributes pointer to an array (containing "NbSuperBlocks" elements),
1364 * with for each element:
1365 * value 0 super-block is unlocked, value 1 super-block is locked
1366 * (corresponds to GTZC_MCPBB_SUPERBLOCK_UNLOCKED and
1367 * GTZC_MCPBB_SUPERBLOCK_LOCKED values).
1368 * @retval HAL status.
1369 */
HAL_GTZC_MPCBB_GetLockConfig(uint32_t MemAddress,uint32_t NbSuperBlocks,uint32_t * pLockAttributes)1370 HAL_StatusTypeDef HAL_GTZC_MPCBB_GetLockConfig(uint32_t MemAddress,
1371 uint32_t NbSuperBlocks,
1372 uint32_t *pLockAttributes)
1373 {
1374 uint32_t reg_mpcbb;
1375 uint32_t base_address;
1376 uint32_t superblock_start;
1377 uint32_t offset_bit_start;
1378 uint32_t i;
1379
1380 /* firstly check that MemAddress is well 16KBytes aligned */
1381 if ((MemAddress % GTZC_MPCBB_SUPERBLOCK_SIZE) != 0U)
1382 {
1383 return HAL_ERROR;
1384 }
1385
1386 /* check entry parameters */
1387 if ((IS_ADDRESS_IN(SRAM1, MemAddress))
1388 && (IS_ADDRESS_IN(SRAM1, (MemAddress
1389 + (NbSuperBlocks * GTZC_MPCBB_SUPERBLOCK_SIZE)
1390 - 1U))))
1391 {
1392 base_address = GTZC_BASE_ADDRESS(SRAM1);
1393 /* limitation: code not portable with memory > 512K */
1394 reg_mpcbb = GTZC_MPCBB1_S->CFGLOCKR1;
1395 }
1396 else if ((IS_ADDRESS_IN(SRAM2, MemAddress))
1397 && (IS_ADDRESS_IN(SRAM2, (MemAddress
1398 + (NbSuperBlocks
1399 * GTZC_MPCBB_SUPERBLOCK_SIZE)
1400 - 1U))))
1401 {
1402 base_address = GTZC_BASE_ADDRESS(SRAM2);
1403 /* limitation: code not portable with memory > 512K */
1404 reg_mpcbb = GTZC_MPCBB2_S->CFGLOCKR1;
1405 }
1406 else if ((IS_ADDRESS_IN(SRAM3, MemAddress))
1407 && (IS_ADDRESS_IN(SRAM3, (MemAddress
1408 + (NbSuperBlocks
1409 * GTZC_MPCBB_SUPERBLOCK_SIZE)
1410 - 1U))))
1411 {
1412 base_address = GTZC_BASE_ADDRESS(SRAM3);
1413 /* limitation: code not portable with memory > 512K */
1414 reg_mpcbb = GTZC_MPCBB3_S->CFGLOCKR1;
1415 }
1416 else
1417 {
1418 return HAL_ERROR;
1419 }
1420
1421 /* get start coordinates of the configuration */
1422 superblock_start = (MemAddress - base_address) / GTZC_MPCBB_SUPERBLOCK_SIZE;
1423 offset_bit_start = superblock_start % 32U;
1424
1425 for (i = 0U; i < NbSuperBlocks; i++)
1426 {
1427 pLockAttributes[i] = (reg_mpcbb & (1UL << (offset_bit_start % 32U)))
1428 >> (offset_bit_start % 32U);
1429 offset_bit_start++;
1430 }
1431
1432 return HAL_OK;
1433 }
1434
1435 /**
1436 * @brief Lock a MPCBB configuration on the SRAM base address passed as parameter.
1437 * @note This functions locks the control register of the MPCBB until next reset.
1438 * @param MemBaseAddress MPCBB identifier.
1439 * @retval HAL status.
1440 */
HAL_GTZC_MPCBB_Lock(uint32_t MemBaseAddress)1441 HAL_StatusTypeDef HAL_GTZC_MPCBB_Lock(uint32_t MemBaseAddress)
1442 {
1443 /* check entry parameters */
1444 if (IS_GTZC_BASE_ADDRESS(SRAM1, MemBaseAddress))
1445 {
1446 SET_BIT(GTZC_MPCBB1_S->CR, GTZC_MPCBB_CR_GLOCK_Msk);
1447 }
1448 else if (IS_GTZC_BASE_ADDRESS(SRAM2, MemBaseAddress))
1449 {
1450 SET_BIT(GTZC_MPCBB2_S->CR, GTZC_MPCBB_CR_GLOCK_Msk);
1451 }
1452 else if (IS_GTZC_BASE_ADDRESS(SRAM3, MemBaseAddress))
1453 {
1454 SET_BIT(GTZC_MPCBB3_S->CR, GTZC_MPCBB_CR_GLOCK_Msk);
1455 }
1456 else
1457 {
1458 return HAL_ERROR;
1459 }
1460
1461 return HAL_OK;
1462 }
1463
1464 /**
1465 * @brief Get MPCBB configuration lock state on the SRAM base address passed as parameter.
1466 * @param MemBaseAddress MPCBB identifier.
1467 * @param pLockState pointer to Lock State (GTZC_MCPBB_LOCK_OFF or GTZC_MCPBB_LOCK_ON).
1468 * @retval HAL status.
1469 */
HAL_GTZC_MPCBB_GetLock(uint32_t MemBaseAddress,uint32_t * pLockState)1470 HAL_StatusTypeDef HAL_GTZC_MPCBB_GetLock(uint32_t MemBaseAddress,
1471 uint32_t *pLockState)
1472 {
1473 /* check entry parameters */
1474 if (IS_GTZC_BASE_ADDRESS(SRAM1, MemBaseAddress))
1475 {
1476 *pLockState = READ_BIT(GTZC_MPCBB1_S->CR, GTZC_MPCBB_CR_GLOCK_Msk);
1477 }
1478 else if (IS_GTZC_BASE_ADDRESS(SRAM2, MemBaseAddress))
1479 {
1480 *pLockState = READ_BIT(GTZC_MPCBB2_S->CR, GTZC_MPCBB_CR_GLOCK_Msk);
1481 }
1482 else if (IS_GTZC_BASE_ADDRESS(SRAM3, MemBaseAddress))
1483 {
1484 *pLockState = READ_BIT(GTZC_MPCBB3_S->CR, GTZC_MPCBB_CR_GLOCK_Msk);
1485 }
1486 else
1487 {
1488 return HAL_ERROR;
1489 }
1490
1491 return HAL_OK;
1492 }
1493
1494 /**
1495 * @}
1496 */
1497
1498 /** @defgroup GTZC_Exported_Functions_Group5 TZIC Configuration and Control functions
1499 * @brief TZIC Configuration and Control functions
1500 *
1501 @verbatim
1502 ==============================================================================
1503 ##### TZIC Configuration and Control functions #####
1504 ==============================================================================
1505 [..]
1506 This section provides functions allowing to configure and control TZIC
1507 TZIC is Trust Zone Interrupt Controller
1508 @endverbatim
1509 * @{
1510 */
1511
1512 /**
1513 * @brief Disable the interrupt associated to a single TZIC peripheral or on all peripherals.
1514 * @param PeriphId Peripheral identifier.
1515 * This parameter can be a value of @ref GTZC_TZSC_TZIC_PeriphId.
1516 * Use GTZC_PERIPH_ALL to select all peripherals.
1517 * @retval HAL status.
1518 */
HAL_GTZC_TZIC_DisableIT(uint32_t PeriphId)1519 HAL_StatusTypeDef HAL_GTZC_TZIC_DisableIT(uint32_t PeriphId)
1520 {
1521 uint32_t register_address;
1522
1523 /* check entry parameters */
1524 if ((HAL_GTZC_GET_ARRAY_INDEX(PeriphId) >= GTZC_TZIC_PERIPH_NUMBER)
1525 || (((PeriphId & GTZC_PERIPH_ALL) != 0U)
1526 && (HAL_GTZC_GET_ARRAY_INDEX(PeriphId) != 0U)))
1527 {
1528 return HAL_ERROR;
1529 }
1530
1531 if ((PeriphId & GTZC_PERIPH_ALL) != 0U)
1532 {
1533 /* same configuration is applied to all peripherals */
1534 WRITE_REG(GTZC_TZIC1->IER1, 0U);
1535 WRITE_REG(GTZC_TZIC1->IER2, 0U);
1536 WRITE_REG(GTZC_TZIC1->IER3, 0U);
1537 WRITE_REG(GTZC_TZIC1->IER4, 0U);
1538 }
1539 else
1540 {
1541 /* common case where only one peripheral is configured */
1542 register_address = (uint32_t) &(GTZC_TZIC1->IER1)
1543 + (4U * GTZC_GET_REG_INDEX(PeriphId));
1544 CLEAR_BIT(*(__IO uint32_t *)register_address, 1UL << GTZC_GET_PERIPH_POS(PeriphId));
1545 }
1546
1547 return HAL_OK;
1548 }
1549
1550 /**
1551 * @brief Enable the interrupt associated to a single TZIC peripheral or on all peripherals.
1552 * @param PeriphId Peripheral identifier.
1553 * This parameter can be a value of @ref GTZC_TZSC_TZIC_PeriphId.
1554 * Use GTZC_PERIPH_ALL to select all peripherals.
1555 * @retval HAL status.
1556 */
HAL_GTZC_TZIC_EnableIT(uint32_t PeriphId)1557 HAL_StatusTypeDef HAL_GTZC_TZIC_EnableIT(uint32_t PeriphId)
1558 {
1559 uint32_t register_address;
1560
1561 /* check entry parameters */
1562 if ((HAL_GTZC_GET_ARRAY_INDEX(PeriphId) >= GTZC_TZIC_PERIPH_NUMBER)
1563 || (((PeriphId & GTZC_PERIPH_ALL) != 0U)
1564 && (HAL_GTZC_GET_ARRAY_INDEX(PeriphId) != 0U)))
1565 {
1566 return HAL_ERROR;
1567 }
1568
1569 if ((PeriphId & GTZC_PERIPH_ALL) != 0U)
1570 {
1571 /* same configuration is applied to all peripherals */
1572 WRITE_REG(GTZC_TZIC1->IER1, TZIC1_IER1_ALL);
1573 WRITE_REG(GTZC_TZIC1->IER2, TZIC1_IER2_ALL);
1574 WRITE_REG(GTZC_TZIC1->IER3, TZIC1_IER3_ALL);
1575 WRITE_REG(GTZC_TZIC1->IER4, TZIC1_IER4_ALL);
1576 }
1577 else
1578 {
1579 /* common case where only one peripheral is configured */
1580 register_address = (uint32_t) &(GTZC_TZIC1->IER1)
1581 + (4U * GTZC_GET_REG_INDEX(PeriphId));
1582 SET_BIT(*(__IO uint32_t *)register_address, 1UL << GTZC_GET_PERIPH_POS(PeriphId));
1583 }
1584
1585 return HAL_OK;
1586 }
1587
1588 /**
1589 * @brief Get TZIC flag on a single TZIC peripheral or on all peripherals.
1590 * @param PeriphId Peripheral identifier.
1591 * This parameter can be a value of @ref GTZC_TZSC_TZIC_PeriphId.
1592 * Use GTZC_PERIPH_ALL to select all peripherals.
1593 * @param pFlag Pointer to the flags.
1594 * If PeriphId target a single peripheral, pointer on a single element.
1595 * If all peripherals selected (GTZC_PERIPH_ALL), pointer to an array
1596 * of GTZC_TZIC_PERIPH_NUMBER elements.
1597 * Element content is either GTZC_TZIC_NO_ILA_EVENT
1598 * or GTZC_TZSC_ILA_EVENT_PENDING.
1599 * @retval HAL status
1600 */
HAL_GTZC_TZIC_GetFlag(uint32_t PeriphId,uint32_t * pFlag)1601 HAL_StatusTypeDef HAL_GTZC_TZIC_GetFlag(uint32_t PeriphId, uint32_t *pFlag)
1602 {
1603 uint32_t i;
1604 uint32_t reg_value;
1605 uint32_t register_address;
1606
1607 /* check entry parameters */
1608 if ((HAL_GTZC_GET_ARRAY_INDEX(PeriphId) >= GTZC_TZIC_PERIPH_NUMBER)
1609 || (((PeriphId & GTZC_PERIPH_ALL) != 0U)
1610 && (HAL_GTZC_GET_ARRAY_INDEX(PeriphId) != 0U)))
1611 {
1612 return HAL_ERROR;
1613 }
1614
1615 if ((PeriphId & GTZC_PERIPH_ALL) != 0U)
1616 {
1617 /* special case where it is applied to all peripherals */
1618 reg_value = READ_REG(GTZC_TZIC1->SR1);
1619 for (i = 0U; i < 32U; i++)
1620 {
1621 pFlag[i] = (reg_value & (1UL << i)) >> i;
1622 }
1623
1624 reg_value = READ_REG(GTZC_TZIC1->SR2);
1625 for (i = 32U; i < 64U; i++)
1626 {
1627 pFlag[i] = (reg_value & (1UL << (i - 32U))) >> (i - 32U);
1628 }
1629
1630 reg_value = READ_REG(GTZC_TZIC1->SR3);
1631 for (i = 64U; i < 96U; i++)
1632 {
1633 pFlag[i] = (reg_value & (1UL << (i - 64U))) >> (i - 64U);
1634 }
1635
1636 reg_value = READ_REG(GTZC_TZIC1->SR4);
1637 for (i = 96U; i < 128U; i++)
1638 {
1639 pFlag[i] = (reg_value & (1UL << (i - 96U))) >> (i - 96U);
1640 }
1641 }
1642 else
1643 {
1644 /* common case where only one peripheral is concerned */
1645 register_address = (uint32_t) &(GTZC_TZIC1->SR1)
1646 + (4U * GTZC_GET_REG_INDEX(PeriphId));
1647 *pFlag = READ_BIT(*(__IO uint32_t *)register_address,
1648 1UL << GTZC_GET_PERIPH_POS(PeriphId)) >> GTZC_GET_PERIPH_POS(PeriphId);
1649 }
1650
1651 return HAL_OK;
1652 }
1653
1654 /**
1655 * @brief Clear TZIC flag on a single TZIC peripheral or on all peripherals.
1656 * @param PeriphId Peripheral identifier.
1657 * This parameter can be a value of @ref GTZC_TZSC_TZIC_PeriphId.
1658 * Use GTZC_PERIPH_ALL to select all peripherals.
1659 * @retval HAL status.
1660 */
HAL_GTZC_TZIC_ClearFlag(uint32_t PeriphId)1661 HAL_StatusTypeDef HAL_GTZC_TZIC_ClearFlag(uint32_t PeriphId)
1662 {
1663 uint32_t register_address;
1664
1665 /* check entry parameters */
1666 if ((HAL_GTZC_GET_ARRAY_INDEX(PeriphId) >= GTZC_TZIC_PERIPH_NUMBER)
1667 || (((PeriphId & GTZC_PERIPH_ALL) != 0U)
1668 && (HAL_GTZC_GET_ARRAY_INDEX(PeriphId) != 0U)))
1669 {
1670 return HAL_ERROR;
1671 }
1672
1673 if ((PeriphId & GTZC_PERIPH_ALL) != 0U)
1674 {
1675 /* same configuration is applied to all peripherals */
1676 WRITE_REG(GTZC_TZIC1->FCR1, TZIC1_FCR1_ALL);
1677 WRITE_REG(GTZC_TZIC1->FCR2, TZIC1_FCR2_ALL);
1678 WRITE_REG(GTZC_TZIC1->FCR3, TZIC1_FCR3_ALL);
1679 WRITE_REG(GTZC_TZIC1->FCR4, TZIC1_FCR4_ALL);
1680 }
1681 else
1682 {
1683 /* common case where only one peripheral is configured */
1684 register_address = (uint32_t) &(GTZC_TZIC1->FCR1)
1685 + (4U * GTZC_GET_REG_INDEX(PeriphId));
1686 SET_BIT(*(__IO uint32_t *)register_address, 1UL << GTZC_GET_PERIPH_POS(PeriphId));
1687 }
1688
1689 return HAL_OK;
1690 }
1691
1692 /**
1693 * @}
1694 */
1695
1696 /** @defgroup GTZC_Exported_Functions_Group6 IRQ related functions
1697 * @brief IRQ related functions
1698 *
1699 @verbatim
1700 ==============================================================================
1701 ##### TZIC IRQ Handler and Callback functions #####
1702 ==============================================================================
1703 [..]
1704 This section provides functions allowing to treat ISR and provide user callback
1705 @endverbatim
1706 * @{
1707 */
1708
1709 /**
1710 * @brief This function handles GTZC TZIC interrupt request.
1711 * @retval None.
1712 */
HAL_GTZC_IRQHandler(void)1713 void HAL_GTZC_IRQHandler(void)
1714 {
1715 uint32_t position;
1716 uint32_t flag;
1717 uint32_t ier_itsources;
1718 uint32_t sr_flags;
1719
1720 /* Get current IT Flags and IT sources value on 1st register of TZIC1 */
1721 ier_itsources = READ_REG(GTZC_TZIC1_S->IER1);
1722 sr_flags = READ_REG(GTZC_TZIC1_S->SR1);
1723
1724 /* Get Mask interrupt and then clear them */
1725 flag = ier_itsources & sr_flags;
1726 if (flag != 0U)
1727 {
1728 WRITE_REG(GTZC_TZIC1_S->FCR1, flag);
1729
1730 /* Loop on flag to check, which ones have been raised */
1731 position = 0U;
1732 while ((flag >> position) != 0U)
1733 {
1734 if ((flag & (1UL << position)) != 0U)
1735 {
1736 HAL_GTZC_TZIC_Callback(GTZC1_PERIPH_REG1 | position);
1737 }
1738
1739 /* Position bit to be updated */
1740 position++;
1741 }
1742 }
1743
1744 /* Get current IT Flags and IT sources value on 2nd register of TZIC1 */
1745 ier_itsources = READ_REG(GTZC_TZIC1_S->IER2);
1746 sr_flags = READ_REG(GTZC_TZIC1_S->SR2);
1747
1748 /* Get Mask interrupt and then clear them */
1749 flag = ier_itsources & sr_flags;
1750 if (flag != 0U)
1751 {
1752 WRITE_REG(GTZC_TZIC1_S->FCR2, flag);
1753
1754 /* Loop on flag to check, which ones have been raised */
1755 position = 0U;
1756 while ((flag >> position) != 0U)
1757 {
1758 if ((flag & (1UL << position)) != 0U)
1759 {
1760 HAL_GTZC_TZIC_Callback(GTZC1_PERIPH_REG2 | position);
1761 }
1762
1763 /* Position bit to be updated */
1764 position++;
1765 }
1766 }
1767
1768 /* Get current IT Flags and IT sources value on 3rd register of TZIC1 */
1769 ier_itsources = READ_REG(GTZC_TZIC1_S->IER3);
1770 sr_flags = READ_REG(GTZC_TZIC1_S->SR3);
1771
1772 /* Get Mask interrupt and then clear them */
1773 flag = ier_itsources & sr_flags;
1774 if (flag != 0U)
1775 {
1776 WRITE_REG(GTZC_TZIC1_S->FCR3, flag);
1777
1778 /* Loop on flag to check, which ones have been raised */
1779 position = 0U;
1780 while ((flag >> position) != 0U)
1781 {
1782 if ((flag & (1UL << position)) != 0U)
1783 {
1784 HAL_GTZC_TZIC_Callback(GTZC1_PERIPH_REG3 | position);
1785 }
1786
1787 /* Position bit to be updated */
1788 position++;
1789 }
1790 }
1791
1792 /* Get current IT Flags and IT sources value on 4th register of TZIC1 */
1793 ier_itsources = READ_REG(GTZC_TZIC1_S->IER4);
1794 sr_flags = READ_REG(GTZC_TZIC1_S->SR4);
1795
1796 /* Get Mask interrupt and then clear them */
1797 flag = ier_itsources & sr_flags;
1798 if (flag != 0U)
1799 {
1800 WRITE_REG(GTZC_TZIC1->FCR4, flag);
1801
1802 /* Loop on flag to check, which ones have been raised */
1803 position = 0U;
1804 while ((flag >> position) != 0U)
1805 {
1806 if ((flag & (1UL << position)) != 0U)
1807 {
1808 HAL_GTZC_TZIC_Callback(GTZC1_PERIPH_REG4 | position);
1809 }
1810
1811 /* Position bit to be updated */
1812 position++;
1813 }
1814 }
1815 }
1816
1817 /**
1818 * @brief GTZC TZIC sub-block interrupt callback.
1819 * @param PeriphId Peripheral identifier triggering the illegal access.
1820 * This parameter can be a value of @ref GTZC_TZSC_TZIC_PeriphId
1821 * @retval None.
1822 */
HAL_GTZC_TZIC_Callback(uint32_t PeriphId)1823 __weak void HAL_GTZC_TZIC_Callback(uint32_t PeriphId)
1824 {
1825 /* Prevent unused argument(s) compilation warning */
1826 UNUSED(PeriphId);
1827
1828 /* NOTE: This function should not be modified. When the callback is needed,
1829 * the HAL_GTZC_TZIC_Callback is to be implemented in the user file
1830 */
1831 }
1832
1833 /**
1834 * @}
1835 */
1836
1837 #endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
1838
1839 /**
1840 * @}
1841 */
1842
1843 #endif /*HAL_GTZC_MODULE_ENABLED*/
1844
1845 /**
1846 * @}
1847 */
1848
1849 /**
1850 * @}
1851 */
1852
