1 /** 2 ****************************************************************************** 3 * @file stm32g4xx_hal_fdcan.h 4 * @author MCD Application Team 5 * @brief Header file of FDCAN HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2019 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 /* Define to prevent recursive inclusion -------------------------------------*/ 20 #ifndef STM32G4xx_HAL_FDCAN_H 21 #define STM32G4xx_HAL_FDCAN_H 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* Includes ------------------------------------------------------------------*/ 28 #include "stm32g4xx_hal_def.h" 29 30 #if defined(FDCAN1) 31 32 /** @addtogroup STM32G4xx_HAL_Driver 33 * @{ 34 */ 35 36 /** @addtogroup FDCAN 37 * @{ 38 */ 39 40 /* Exported types ------------------------------------------------------------*/ 41 /** @defgroup FDCAN_Exported_Types FDCAN Exported Types 42 * @{ 43 */ 44 45 /** 46 * @brief HAL State structures definition 47 */ 48 typedef enum 49 { 50 HAL_FDCAN_STATE_RESET = 0x00U, /*!< FDCAN not yet initialized or disabled */ 51 HAL_FDCAN_STATE_READY = 0x01U, /*!< FDCAN initialized and ready for use */ 52 HAL_FDCAN_STATE_BUSY = 0x02U, /*!< FDCAN process is ongoing */ 53 HAL_FDCAN_STATE_ERROR = 0x03U /*!< FDCAN error state */ 54 } HAL_FDCAN_StateTypeDef; 55 56 /** 57 * @brief FDCAN Init structure definition 58 */ 59 typedef struct 60 { 61 uint32_t ClockDivider; /*!< Specifies the FDCAN kernel clock divider. 62 The clock is common to all FDCAN instances. 63 This parameter is applied only at initialisation of 64 first FDCAN instance. 65 This parameter can be a value of @ref FDCAN_clock_divider. */ 66 67 uint32_t FrameFormat; /*!< Specifies the FDCAN frame format. 68 This parameter can be a value of @ref FDCAN_frame_format */ 69 70 uint32_t Mode; /*!< Specifies the FDCAN mode. 71 This parameter can be a value of @ref FDCAN_operating_mode */ 72 73 FunctionalState AutoRetransmission; /*!< Enable or disable the automatic retransmission mode. 74 This parameter can be set to ENABLE or DISABLE */ 75 76 FunctionalState TransmitPause; /*!< Enable or disable the Transmit Pause feature. 77 This parameter can be set to ENABLE or DISABLE */ 78 79 FunctionalState ProtocolException; /*!< Enable or disable the Protocol Exception Handling. 80 This parameter can be set to ENABLE or DISABLE */ 81 82 uint32_t NominalPrescaler; /*!< Specifies the value by which the oscillator frequency is 83 divided for generating the nominal bit time quanta. 84 This parameter must be a number between 1 and 512 */ 85 86 uint32_t NominalSyncJumpWidth; /*!< Specifies the maximum number of time quanta the FDCAN 87 hardware is allowed to lengthen or shorten a bit to perform 88 resynchronization. 89 This parameter must be a number between 1 and 128 */ 90 91 uint32_t NominalTimeSeg1; /*!< Specifies the number of time quanta in Bit Segment 1. 92 This parameter must be a number between 2 and 256 */ 93 94 uint32_t NominalTimeSeg2; /*!< Specifies the number of time quanta in Bit Segment 2. 95 This parameter must be a number between 2 and 128 */ 96 97 uint32_t DataPrescaler; /*!< Specifies the value by which the oscillator frequency is 98 divided for generating the data bit time quanta. 99 This parameter must be a number between 1 and 32 */ 100 101 uint32_t DataSyncJumpWidth; /*!< Specifies the maximum number of time quanta the FDCAN 102 hardware is allowed to lengthen or shorten a data bit to 103 perform resynchronization. 104 This parameter must be a number between 1 and 16 */ 105 106 uint32_t DataTimeSeg1; /*!< Specifies the number of time quanta in Data Bit Segment 1. 107 This parameter must be a number between 1 and 32 */ 108 109 uint32_t DataTimeSeg2; /*!< Specifies the number of time quanta in Data Bit Segment 2. 110 This parameter must be a number between 1 and 16 */ 111 112 uint32_t StdFiltersNbr; /*!< Specifies the number of standard Message ID filters. 113 This parameter must be a number between 0 and 28 */ 114 115 uint32_t ExtFiltersNbr; /*!< Specifies the number of extended Message ID filters. 116 This parameter must be a number between 0 and 8 */ 117 118 uint32_t TxFifoQueueMode; /*!< Tx FIFO/Queue Mode selection. 119 This parameter can be a value of @ref FDCAN_txFifoQueue_Mode */ 120 121 } FDCAN_InitTypeDef; 122 123 /** 124 * @brief FDCAN filter structure definition 125 */ 126 typedef struct 127 { 128 uint32_t IdType; /*!< Specifies the identifier type. 129 This parameter can be a value of @ref FDCAN_id_type */ 130 131 uint32_t FilterIndex; /*!< Specifies the filter which will be initialized. 132 This parameter must be a number between: 133 - 0 and (SRAMCAN_FLS_NBR-1), if IdType is FDCAN_STANDARD_ID 134 - 0 and (SRAMCAN_FLE_NBR-1), if IdType is FDCAN_EXTENDED_ID */ 135 136 uint32_t FilterType; /*!< Specifies the filter type. 137 This parameter can be a value of @ref FDCAN_filter_type. 138 The value FDCAN_FILTER_RANGE_NO_EIDM is permitted 139 only when IdType is FDCAN_EXTENDED_ID. */ 140 141 uint32_t FilterConfig; /*!< Specifies the filter configuration. 142 This parameter can be a value of @ref FDCAN_filter_config */ 143 144 uint32_t FilterID1; /*!< Specifies the filter identification 1. 145 This parameter must be a number between: 146 - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID 147 - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID */ 148 149 uint32_t FilterID2; /*!< Specifies the filter identification 2. 150 This parameter must be a number between: 151 - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID 152 - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID */ 153 154 } FDCAN_FilterTypeDef; 155 156 /** 157 * @brief FDCAN Tx header structure definition 158 */ 159 typedef struct 160 { 161 uint32_t Identifier; /*!< Specifies the identifier. 162 This parameter must be a number between: 163 - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID 164 - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID */ 165 166 uint32_t IdType; /*!< Specifies the identifier type for the message that will be 167 transmitted. 168 This parameter can be a value of @ref FDCAN_id_type */ 169 170 uint32_t TxFrameType; /*!< Specifies the frame type of the message that will be transmitted. 171 This parameter can be a value of @ref FDCAN_frame_type */ 172 173 uint32_t DataLength; /*!< Specifies the length of the frame that will be transmitted. 174 This parameter can be a value of @ref FDCAN_data_length_code */ 175 176 uint32_t ErrorStateIndicator; /*!< Specifies the error state indicator. 177 This parameter can be a value of @ref FDCAN_error_state_indicator */ 178 179 uint32_t BitRateSwitch; /*!< Specifies whether the Tx frame will be transmitted with or without 180 bit rate switching. 181 This parameter can be a value of @ref FDCAN_bit_rate_switching */ 182 183 uint32_t FDFormat; /*!< Specifies whether the Tx frame will be transmitted in classic or 184 FD format. 185 This parameter can be a value of @ref FDCAN_format */ 186 187 uint32_t TxEventFifoControl; /*!< Specifies the event FIFO control. 188 This parameter can be a value of @ref FDCAN_EFC */ 189 190 uint32_t MessageMarker; /*!< Specifies the message marker to be copied into Tx Event FIFO 191 element for identification of Tx message status. 192 This parameter must be a number between 0 and 0xFF */ 193 194 } FDCAN_TxHeaderTypeDef; 195 196 /** 197 * @brief FDCAN Rx header structure definition 198 */ 199 typedef struct 200 { 201 uint32_t Identifier; /*!< Specifies the identifier. 202 This parameter must be a number between: 203 - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID 204 - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID */ 205 206 uint32_t IdType; /*!< Specifies the identifier type of the received message. 207 This parameter can be a value of @ref FDCAN_id_type */ 208 209 uint32_t RxFrameType; /*!< Specifies the the received message frame type. 210 This parameter can be a value of @ref FDCAN_frame_type */ 211 212 uint32_t DataLength; /*!< Specifies the received frame length. 213 This parameter can be a value of @ref FDCAN_data_length_code */ 214 215 uint32_t ErrorStateIndicator; /*!< Specifies the error state indicator. 216 This parameter can be a value of @ref FDCAN_error_state_indicator */ 217 218 uint32_t BitRateSwitch; /*!< Specifies whether the Rx frame is received with or without bit 219 rate switching. 220 This parameter can be a value of @ref FDCAN_bit_rate_switching */ 221 222 uint32_t FDFormat; /*!< Specifies whether the Rx frame is received in classic or FD 223 format. 224 This parameter can be a value of @ref FDCAN_format */ 225 226 uint32_t RxTimestamp; /*!< Specifies the timestamp counter value captured on start of frame 227 reception. 228 This parameter must be a number between 0 and 0xFFFF */ 229 230 uint32_t FilterIndex; /*!< Specifies the index of matching Rx acceptance filter element. 231 This parameter must be a number between: 232 - 0 and (SRAMCAN_FLS_NBR-1), if IdType is FDCAN_STANDARD_ID 233 - 0 and (SRAMCAN_FLE_NBR-1), if IdType is FDCAN_EXTENDED_ID */ 234 235 uint32_t IsFilterMatchingFrame; /*!< Specifies whether the accepted frame did not match any Rx filter. 236 Acceptance of non-matching frames may be enabled via 237 HAL_FDCAN_ConfigGlobalFilter(). 238 This parameter can be 0 or 1 */ 239 240 } FDCAN_RxHeaderTypeDef; 241 242 /** 243 * @brief FDCAN Tx event FIFO structure definition 244 */ 245 typedef struct 246 { 247 uint32_t Identifier; /*!< Specifies the identifier. 248 This parameter must be a number between: 249 - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID 250 - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID */ 251 252 uint32_t IdType; /*!< Specifies the identifier type for the transmitted message. 253 This parameter can be a value of @ref FDCAN_id_type */ 254 255 uint32_t TxFrameType; /*!< Specifies the frame type of the transmitted message. 256 This parameter can be a value of @ref FDCAN_frame_type */ 257 258 uint32_t DataLength; /*!< Specifies the length of the transmitted frame. 259 This parameter can be a value of @ref FDCAN_data_length_code */ 260 261 uint32_t ErrorStateIndicator; /*!< Specifies the error state indicator. 262 This parameter can be a value of @ref FDCAN_error_state_indicator */ 263 264 uint32_t BitRateSwitch; /*!< Specifies whether the Tx frame is transmitted with or without bit 265 rate switching. 266 This parameter can be a value of @ref FDCAN_bit_rate_switching */ 267 268 uint32_t FDFormat; /*!< Specifies whether the Tx frame is transmitted in classic or FD 269 format. 270 This parameter can be a value of @ref FDCAN_format */ 271 272 uint32_t TxTimestamp; /*!< Specifies the timestamp counter value captured on start of frame 273 transmission. 274 This parameter must be a number between 0 and 0xFFFF */ 275 276 uint32_t MessageMarker; /*!< Specifies the message marker copied into Tx Event FIFO element 277 for identification of Tx message status. 278 This parameter must be a number between 0 and 0xFF */ 279 280 uint32_t EventType; /*!< Specifies the event type. 281 This parameter can be a value of @ref FDCAN_event_type */ 282 283 } FDCAN_TxEventFifoTypeDef; 284 285 /** 286 * @brief FDCAN High Priority Message Status structure definition 287 */ 288 typedef struct 289 { 290 uint32_t FilterList; /*!< Specifies the filter list of the matching filter element. 291 This parameter can be: 292 - 0 : Standard Filter List 293 - 1 : Extended Filter List */ 294 295 uint32_t FilterIndex; /*!< Specifies the index of matching filter element. 296 This parameter can be a number between: 297 - 0 and (SRAMCAN_FLS_NBR-1), if FilterList is 0 (Standard) 298 - 0 and (SRAMCAN_FLE_NBR-1), if FilterList is 1 (Extended) */ 299 300 uint32_t MessageStorage; /*!< Specifies the HP Message Storage. 301 This parameter can be a value of @ref FDCAN_hp_msg_storage */ 302 303 uint32_t MessageIndex; /*!< Specifies the Index of Rx FIFO element to which the 304 message was stored. 305 This parameter is valid only when MessageStorage is: 306 FDCAN_HP_STORAGE_RXFIFO0 307 or 308 FDCAN_HP_STORAGE_RXFIFO1 */ 309 310 } FDCAN_HpMsgStatusTypeDef; 311 312 /** 313 * @brief FDCAN Protocol Status structure definition 314 */ 315 typedef struct 316 { 317 uint32_t LastErrorCode; /*!< Specifies the type of the last error that occurred on the FDCAN bus. 318 This parameter can be a value of @ref FDCAN_protocol_error_code */ 319 320 uint32_t DataLastErrorCode; /*!< Specifies the type of the last error that occurred in the data phase 321 of a CAN FD format frame with its BRS flag set. 322 This parameter can be a value of @ref FDCAN_protocol_error_code */ 323 324 uint32_t Activity; /*!< Specifies the FDCAN module communication state. 325 This parameter can be a value of @ref FDCAN_communication_state */ 326 327 uint32_t ErrorPassive; /*!< Specifies the FDCAN module error status. 328 This parameter can be: 329 - 0 : The FDCAN is in Error_Active state 330 - 1 : The FDCAN is in Error_Passive state */ 331 332 uint32_t Warning; /*!< Specifies the FDCAN module warning status. 333 This parameter can be: 334 - 0 : error counters (RxErrorCnt and TxErrorCnt) 335 are below the Error_Warning limit of 96 336 - 1 : at least one of error counters has reached the Error_Warning limit of 96 */ 337 338 uint32_t BusOff; /*!< Specifies the FDCAN module Bus_Off status. 339 This parameter can be: 340 - 0 : The FDCAN is not in Bus_Off state 341 - 1 : The FDCAN is in Bus_Off state */ 342 343 uint32_t RxESIflag; /*!< Specifies ESI flag of last received CAN FD message. 344 This parameter can be: 345 - 0 : Last received CAN FD message did not have its ESI flag set 346 - 1 : Last received CAN FD message had its ESI flag set */ 347 348 uint32_t RxBRSflag; /*!< Specifies BRS flag of last received CAN FD message. 349 This parameter can be: 350 - 0 : Last received CAN FD message did not have its BRS flag set 351 - 1 : Last received CAN FD message had its BRS flag set */ 352 353 uint32_t RxFDFflag; /*!< Specifies if CAN FD message (FDF flag set) has been received 354 since last protocol status.This parameter can be: 355 - 0 : No CAN FD message received 356 - 1 : CAN FD message received */ 357 358 uint32_t ProtocolException; /*!< Specifies the FDCAN module Protocol Exception status. 359 This parameter can be: 360 - 0 : No protocol exception event occurred since last read access 361 - 1 : Protocol exception event occurred */ 362 363 uint32_t TDCvalue; /*!< Specifies the Transmitter Delay Compensation Value. 364 This parameter can be a number between 0 and 127 */ 365 366 } FDCAN_ProtocolStatusTypeDef; 367 368 /** 369 * @brief FDCAN Error Counters structure definition 370 */ 371 typedef struct 372 { 373 uint32_t TxErrorCnt; /*!< Specifies the Transmit Error Counter Value. 374 This parameter can be a number between 0 and 255 */ 375 376 uint32_t RxErrorCnt; /*!< Specifies the Receive Error Counter Value. 377 This parameter can be a number between 0 and 127 */ 378 379 uint32_t RxErrorPassive; /*!< Specifies the Receive Error Passive status. 380 This parameter can be: 381 - 0 : The Receive Error Counter (RxErrorCnt) is below the error passive level of 128 382 - 1 : The Receive Error Counter (RxErrorCnt) 383 has reached the error passive level of 128 */ 384 385 uint32_t ErrorLogging; /*!< Specifies the Transmit/Receive error logging counter value. 386 This parameter can be a number between 0 and 255. 387 This counter is incremented each time when a FDCAN protocol error causes the TxErrorCnt 388 or the RxErrorCnt to be incremented. The counter stops at 255; the next increment of 389 TxErrorCnt or RxErrorCnt sets interrupt flag FDCAN_FLAG_ERROR_LOGGING_OVERFLOW */ 390 391 } FDCAN_ErrorCountersTypeDef; 392 393 /** 394 * @brief FDCAN Message RAM blocks 395 */ 396 typedef struct 397 { 398 uint32_t StandardFilterSA; /*!< Specifies the Standard Filter List Start Address. 399 This parameter must be a 32-bit word address */ 400 401 uint32_t ExtendedFilterSA; /*!< Specifies the Extended Filter List Start Address. 402 This parameter must be a 32-bit word address */ 403 404 uint32_t RxFIFO0SA; /*!< Specifies the Rx FIFO 0 Start Address. 405 This parameter must be a 32-bit word address */ 406 407 uint32_t RxFIFO1SA; /*!< Specifies the Rx FIFO 1 Start Address. 408 This parameter must be a 32-bit word address */ 409 410 uint32_t TxEventFIFOSA; /*!< Specifies the Tx Event FIFO Start Address. 411 This parameter must be a 32-bit word address */ 412 413 uint32_t TxFIFOQSA; /*!< Specifies the Tx FIFO/Queue Start Address. 414 This parameter must be a 32-bit word address */ 415 416 } FDCAN_MsgRamAddressTypeDef; 417 418 /** 419 * @brief FDCAN handle structure definition 420 */ 421 #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 422 typedef struct __FDCAN_HandleTypeDef 423 #else 424 typedef struct 425 #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ 426 { 427 FDCAN_GlobalTypeDef *Instance; /*!< Register base address */ 428 429 FDCAN_InitTypeDef Init; /*!< FDCAN required parameters */ 430 431 FDCAN_MsgRamAddressTypeDef msgRam; /*!< FDCAN Message RAM blocks */ 432 433 uint32_t LatestTxFifoQRequest; /*!< FDCAN Tx buffer index 434 of latest Tx FIFO/Queue request */ 435 436 __IO HAL_FDCAN_StateTypeDef State; /*!< FDCAN communication state */ 437 438 HAL_LockTypeDef Lock; /*!< FDCAN locking object */ 439 440 __IO uint32_t ErrorCode; /*!< FDCAN Error code */ 441 442 #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 443 void (* TxEventFifoCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t TxEventFifoITs); /*!< FDCAN Tx Event Fifo callback */ 444 void (* RxFifo0Callback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo0ITs); /*!< FDCAN Rx Fifo 0 callback */ 445 void (* RxFifo1Callback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo1ITs); /*!< FDCAN Rx Fifo 1 callback */ 446 void (* TxFifoEmptyCallback)(struct __FDCAN_HandleTypeDef *hfdcan); /*!< FDCAN Tx Fifo Empty callback */ 447 void (* TxBufferCompleteCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes); /*!< FDCAN Tx Buffer complete callback */ 448 void (* TxBufferAbortCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes); /*!< FDCAN Tx Buffer abort callback */ 449 void (* HighPriorityMessageCallback)(struct __FDCAN_HandleTypeDef *hfdcan); /*!< FDCAN High priority message callback */ 450 void (* TimestampWraparoundCallback)(struct __FDCAN_HandleTypeDef *hfdcan); /*!< FDCAN Timestamp wraparound callback */ 451 void (* TimeoutOccurredCallback)(struct __FDCAN_HandleTypeDef *hfdcan); /*!< FDCAN Timeout occurred callback */ 452 void (* ErrorCallback)(struct __FDCAN_HandleTypeDef *hfdcan); /*!< FDCAN Error callback */ 453 void (* ErrorStatusCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t ErrorStatusITs); /*!< FDCAN Error status callback */ 454 455 void (* MspInitCallback)(struct __FDCAN_HandleTypeDef *hfdcan); /*!< FDCAN Msp Init callback */ 456 void (* MspDeInitCallback)(struct __FDCAN_HandleTypeDef *hfdcan); /*!< FDCAN Msp DeInit callback */ 457 458 #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ 459 460 } FDCAN_HandleTypeDef; 461 462 #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 463 /** 464 * @brief HAL FDCAN common Callback ID enumeration definition 465 */ 466 typedef enum 467 { 468 HAL_FDCAN_TX_FIFO_EMPTY_CB_ID = 0x00U, /*!< FDCAN Tx Fifo Empty callback ID */ 469 HAL_FDCAN_HIGH_PRIO_MESSAGE_CB_ID = 0x01U, /*!< FDCAN High priority message callback ID */ 470 HAL_FDCAN_TIMESTAMP_WRAPAROUND_CB_ID = 0x02U, /*!< FDCAN Timestamp wraparound callback ID */ 471 HAL_FDCAN_TIMEOUT_OCCURRED_CB_ID = 0x03U, /*!< FDCAN Timeout occurred callback ID */ 472 HAL_FDCAN_ERROR_CALLBACK_CB_ID = 0x04U, /*!< FDCAN Error callback ID */ 473 474 HAL_FDCAN_MSPINIT_CB_ID = 0x05U, /*!< FDCAN MspInit callback ID */ 475 HAL_FDCAN_MSPDEINIT_CB_ID = 0x06U, /*!< FDCAN MspDeInit callback ID */ 476 477 } HAL_FDCAN_CallbackIDTypeDef; 478 479 /** 480 * @brief HAL FDCAN Callback pointer definition 481 */ 482 typedef void (*pFDCAN_CallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan); /*!< pointer to a common FDCAN callback function */ 483 typedef void (*pFDCAN_TxEventFifoCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t TxEventFifoITs); /*!< pointer to Tx event Fifo FDCAN callback function */ 484 typedef void (*pFDCAN_RxFifo0CallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo0ITs); /*!< pointer to Rx Fifo 0 FDCAN callback function */ 485 typedef void (*pFDCAN_RxFifo1CallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo1ITs); /*!< pointer to Rx Fifo 1 FDCAN callback function */ 486 typedef void (*pFDCAN_TxBufferCompleteCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes); /*!< pointer to Tx Buffer complete FDCAN callback function */ 487 typedef void (*pFDCAN_TxBufferAbortCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes); /*!< pointer to Tx Buffer abort FDCAN callback function */ 488 typedef void (*pFDCAN_ErrorStatusCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t ErrorStatusITs); /*!< pointer to Error Status callback function */ 489 490 #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ 491 492 /** 493 * @} 494 */ 495 496 /* Exported constants --------------------------------------------------------*/ 497 /** @defgroup FDCAN_Exported_Constants FDCAN Exported Constants 498 * @{ 499 */ 500 501 /** @defgroup HAL_FDCAN_Error_Code HAL FDCAN Error Code 502 * @{ 503 */ 504 #define HAL_FDCAN_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ 505 #define HAL_FDCAN_ERROR_TIMEOUT ((uint32_t)0x00000001U) /*!< Timeout error */ 506 #define HAL_FDCAN_ERROR_NOT_INITIALIZED ((uint32_t)0x00000002U) /*!< Peripheral not initialized */ 507 #define HAL_FDCAN_ERROR_NOT_READY ((uint32_t)0x00000004U) /*!< Peripheral not ready */ 508 #define HAL_FDCAN_ERROR_NOT_STARTED ((uint32_t)0x00000008U) /*!< Peripheral not started */ 509 #define HAL_FDCAN_ERROR_NOT_SUPPORTED ((uint32_t)0x00000010U) /*!< Mode not supported */ 510 #define HAL_FDCAN_ERROR_PARAM ((uint32_t)0x00000020U) /*!< Parameter error */ 511 #define HAL_FDCAN_ERROR_PENDING ((uint32_t)0x00000040U) /*!< Pending operation */ 512 #define HAL_FDCAN_ERROR_RAM_ACCESS ((uint32_t)0x00000080U) /*!< Message RAM Access Failure */ 513 #define HAL_FDCAN_ERROR_FIFO_EMPTY ((uint32_t)0x00000100U) /*!< Put element in full FIFO */ 514 #define HAL_FDCAN_ERROR_FIFO_FULL ((uint32_t)0x00000200U) /*!< Get element from empty FIFO */ 515 #define HAL_FDCAN_ERROR_LOG_OVERFLOW FDCAN_IR_ELO /*!< Overflow of CAN Error Logging Counter */ 516 #define HAL_FDCAN_ERROR_RAM_WDG FDCAN_IR_WDI /*!< Message RAM Watchdog event occurred */ 517 #define HAL_FDCAN_ERROR_PROTOCOL_ARBT FDCAN_IR_PEA /*!< Protocol Error in Arbitration Phase (Nominal Bit Time is used) */ 518 #define HAL_FDCAN_ERROR_PROTOCOL_DATA FDCAN_IR_PED /*!< Protocol Error in Data Phase (Data Bit Time is used) */ 519 #define HAL_FDCAN_ERROR_RESERVED_AREA FDCAN_IR_ARA /*!< Access to Reserved Address */ 520 521 #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 522 #define HAL_FDCAN_ERROR_INVALID_CALLBACK ((uint32_t)0x00000100U) /*!< Invalid Callback error */ 523 #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ 524 /** 525 * @} 526 */ 527 528 /** @defgroup FDCAN_frame_format FDCAN Frame Format 529 * @{ 530 */ 531 #define FDCAN_FRAME_CLASSIC ((uint32_t)0x00000000U) /*!< Classic mode */ 532 #define FDCAN_FRAME_FD_NO_BRS ((uint32_t)FDCAN_CCCR_FDOE) /*!< FD mode without BitRate Switching */ 533 #define FDCAN_FRAME_FD_BRS ((uint32_t)(FDCAN_CCCR_FDOE | FDCAN_CCCR_BRSE)) /*!< FD mode with BitRate Switching */ 534 /** 535 * @} 536 */ 537 538 /** @defgroup FDCAN_operating_mode FDCAN Operating Mode 539 * @{ 540 */ 541 #define FDCAN_MODE_NORMAL ((uint32_t)0x00000000U) /*!< Normal mode */ 542 #define FDCAN_MODE_RESTRICTED_OPERATION ((uint32_t)0x00000001U) /*!< Restricted Operation mode */ 543 #define FDCAN_MODE_BUS_MONITORING ((uint32_t)0x00000002U) /*!< Bus Monitoring mode */ 544 #define FDCAN_MODE_INTERNAL_LOOPBACK ((uint32_t)0x00000003U) /*!< Internal LoopBack mode */ 545 #define FDCAN_MODE_EXTERNAL_LOOPBACK ((uint32_t)0x00000004U) /*!< External LoopBack mode */ 546 /** 547 * @} 548 */ 549 550 /** @defgroup FDCAN_clock_divider FDCAN Clock Divider 551 * @{ 552 */ 553 #define FDCAN_CLOCK_DIV1 ((uint32_t)0x00000000U) /*!< Divide kernel clock by 1 */ 554 #define FDCAN_CLOCK_DIV2 ((uint32_t)0x00000001U) /*!< Divide kernel clock by 2 */ 555 #define FDCAN_CLOCK_DIV4 ((uint32_t)0x00000002U) /*!< Divide kernel clock by 4 */ 556 #define FDCAN_CLOCK_DIV6 ((uint32_t)0x00000003U) /*!< Divide kernel clock by 6 */ 557 #define FDCAN_CLOCK_DIV8 ((uint32_t)0x00000004U) /*!< Divide kernel clock by 8 */ 558 #define FDCAN_CLOCK_DIV10 ((uint32_t)0x00000005U) /*!< Divide kernel clock by 10 */ 559 #define FDCAN_CLOCK_DIV12 ((uint32_t)0x00000006U) /*!< Divide kernel clock by 12 */ 560 #define FDCAN_CLOCK_DIV14 ((uint32_t)0x00000007U) /*!< Divide kernel clock by 14 */ 561 #define FDCAN_CLOCK_DIV16 ((uint32_t)0x00000008U) /*!< Divide kernel clock by 16 */ 562 #define FDCAN_CLOCK_DIV18 ((uint32_t)0x00000009U) /*!< Divide kernel clock by 18 */ 563 #define FDCAN_CLOCK_DIV20 ((uint32_t)0x0000000AU) /*!< Divide kernel clock by 20 */ 564 #define FDCAN_CLOCK_DIV22 ((uint32_t)0x0000000BU) /*!< Divide kernel clock by 22 */ 565 #define FDCAN_CLOCK_DIV24 ((uint32_t)0x0000000CU) /*!< Divide kernel clock by 24 */ 566 #define FDCAN_CLOCK_DIV26 ((uint32_t)0x0000000DU) /*!< Divide kernel clock by 26 */ 567 #define FDCAN_CLOCK_DIV28 ((uint32_t)0x0000000EU) /*!< Divide kernel clock by 28 */ 568 #define FDCAN_CLOCK_DIV30 ((uint32_t)0x0000000FU) /*!< Divide kernel clock by 30 */ 569 /** 570 * @} 571 */ 572 573 /** @defgroup FDCAN_txFifoQueue_Mode FDCAN Tx FIFO/Queue Mode 574 * @{ 575 */ 576 #define FDCAN_TX_FIFO_OPERATION ((uint32_t)0x00000000U) /*!< FIFO mode */ 577 #define FDCAN_TX_QUEUE_OPERATION ((uint32_t)FDCAN_TXBC_TFQM) /*!< Queue mode */ 578 /** 579 * @} 580 */ 581 582 /** @defgroup FDCAN_id_type FDCAN ID Type 583 * @{ 584 */ 585 #define FDCAN_STANDARD_ID ((uint32_t)0x00000000U) /*!< Standard ID element */ 586 #define FDCAN_EXTENDED_ID ((uint32_t)0x40000000U) /*!< Extended ID element */ 587 /** 588 * @} 589 */ 590 591 /** @defgroup FDCAN_frame_type FDCAN Frame Type 592 * @{ 593 */ 594 #define FDCAN_DATA_FRAME ((uint32_t)0x00000000U) /*!< Data frame */ 595 #define FDCAN_REMOTE_FRAME ((uint32_t)0x20000000U) /*!< Remote frame */ 596 /** 597 * @} 598 */ 599 600 /** @defgroup FDCAN_data_length_code FDCAN Data Length Code 601 * @{ 602 */ 603 #define FDCAN_DLC_BYTES_0 ((uint32_t)0x00000000U) /*!< 0 bytes data field */ 604 #define FDCAN_DLC_BYTES_1 ((uint32_t)0x00010000U) /*!< 1 bytes data field */ 605 #define FDCAN_DLC_BYTES_2 ((uint32_t)0x00020000U) /*!< 2 bytes data field */ 606 #define FDCAN_DLC_BYTES_3 ((uint32_t)0x00030000U) /*!< 3 bytes data field */ 607 #define FDCAN_DLC_BYTES_4 ((uint32_t)0x00040000U) /*!< 4 bytes data field */ 608 #define FDCAN_DLC_BYTES_5 ((uint32_t)0x00050000U) /*!< 5 bytes data field */ 609 #define FDCAN_DLC_BYTES_6 ((uint32_t)0x00060000U) /*!< 6 bytes data field */ 610 #define FDCAN_DLC_BYTES_7 ((uint32_t)0x00070000U) /*!< 7 bytes data field */ 611 #define FDCAN_DLC_BYTES_8 ((uint32_t)0x00080000U) /*!< 8 bytes data field */ 612 #define FDCAN_DLC_BYTES_12 ((uint32_t)0x00090000U) /*!< 12 bytes data field */ 613 #define FDCAN_DLC_BYTES_16 ((uint32_t)0x000A0000U) /*!< 16 bytes data field */ 614 #define FDCAN_DLC_BYTES_20 ((uint32_t)0x000B0000U) /*!< 20 bytes data field */ 615 #define FDCAN_DLC_BYTES_24 ((uint32_t)0x000C0000U) /*!< 24 bytes data field */ 616 #define FDCAN_DLC_BYTES_32 ((uint32_t)0x000D0000U) /*!< 32 bytes data field */ 617 #define FDCAN_DLC_BYTES_48 ((uint32_t)0x000E0000U) /*!< 48 bytes data field */ 618 #define FDCAN_DLC_BYTES_64 ((uint32_t)0x000F0000U) /*!< 64 bytes data field */ 619 /** 620 * @} 621 */ 622 623 /** @defgroup FDCAN_error_state_indicator FDCAN Error State Indicator 624 * @{ 625 */ 626 #define FDCAN_ESI_ACTIVE ((uint32_t)0x00000000U) /*!< Transmitting node is error active */ 627 #define FDCAN_ESI_PASSIVE ((uint32_t)0x80000000U) /*!< Transmitting node is error passive */ 628 /** 629 * @} 630 */ 631 632 /** @defgroup FDCAN_bit_rate_switching FDCAN Bit Rate Switching 633 * @{ 634 */ 635 #define FDCAN_BRS_OFF ((uint32_t)0x00000000U) /*!< FDCAN frames transmitted/received without bit rate switching */ 636 #define FDCAN_BRS_ON ((uint32_t)0x00100000U) /*!< FDCAN frames transmitted/received with bit rate switching */ 637 /** 638 * @} 639 */ 640 641 /** @defgroup FDCAN_format FDCAN format 642 * @{ 643 */ 644 #define FDCAN_CLASSIC_CAN ((uint32_t)0x00000000U) /*!< Frame transmitted/received in Classic CAN format */ 645 #define FDCAN_FD_CAN ((uint32_t)0x00200000U) /*!< Frame transmitted/received in FDCAN format */ 646 /** 647 * @} 648 */ 649 650 /** @defgroup FDCAN_EFC FDCAN Event FIFO control 651 * @{ 652 */ 653 #define FDCAN_NO_TX_EVENTS ((uint32_t)0x00000000U) /*!< Do not store Tx events */ 654 #define FDCAN_STORE_TX_EVENTS ((uint32_t)0x00800000U) /*!< Store Tx events */ 655 /** 656 * @} 657 */ 658 659 /** @defgroup FDCAN_filter_type FDCAN Filter Type 660 * @{ 661 */ 662 #define FDCAN_FILTER_RANGE ((uint32_t)0x00000000U) /*!< Range filter from FilterID1 to FilterID2 */ 663 #define FDCAN_FILTER_DUAL ((uint32_t)0x00000001U) /*!< Dual ID filter for FilterID1 or FilterID2 */ 664 #define FDCAN_FILTER_MASK ((uint32_t)0x00000002U) /*!< Classic filter: FilterID1 = filter, FilterID2 = mask */ 665 #define FDCAN_FILTER_RANGE_NO_EIDM ((uint32_t)0x00000003U) /*!< Range filter from FilterID1 to FilterID2, EIDM mask not applied */ 666 /** 667 * @} 668 */ 669 670 /** @defgroup FDCAN_filter_config FDCAN Filter Configuration 671 * @{ 672 */ 673 #define FDCAN_FILTER_DISABLE ((uint32_t)0x00000000U) /*!< Disable filter element */ 674 #define FDCAN_FILTER_TO_RXFIFO0 ((uint32_t)0x00000001U) /*!< Store in Rx FIFO 0 if filter matches */ 675 #define FDCAN_FILTER_TO_RXFIFO1 ((uint32_t)0x00000002U) /*!< Store in Rx FIFO 1 if filter matches */ 676 #define FDCAN_FILTER_REJECT ((uint32_t)0x00000003U) /*!< Reject ID if filter matches */ 677 #define FDCAN_FILTER_HP ((uint32_t)0x00000004U) /*!< Set high priority if filter matches */ 678 #define FDCAN_FILTER_TO_RXFIFO0_HP ((uint32_t)0x00000005U) /*!< Set high priority and store in FIFO 0 if filter matches */ 679 #define FDCAN_FILTER_TO_RXFIFO1_HP ((uint32_t)0x00000006U) /*!< Set high priority and store in FIFO 1 if filter matches */ 680 /** 681 * @} 682 */ 683 684 /** @defgroup FDCAN_Tx_location FDCAN Tx Location 685 * @{ 686 */ 687 #define FDCAN_TX_BUFFER0 ((uint32_t)0x00000001U) /*!< Add message to Tx Buffer 0 */ 688 #define FDCAN_TX_BUFFER1 ((uint32_t)0x00000002U) /*!< Add message to Tx Buffer 1 */ 689 #define FDCAN_TX_BUFFER2 ((uint32_t)0x00000004U) /*!< Add message to Tx Buffer 2 */ 690 /** 691 * @} 692 */ 693 694 /** @defgroup FDCAN_Rx_location FDCAN Rx Location 695 * @{ 696 */ 697 #define FDCAN_RX_FIFO0 ((uint32_t)0x00000040U) /*!< Get received message from Rx FIFO 0 */ 698 #define FDCAN_RX_FIFO1 ((uint32_t)0x00000041U) /*!< Get received message from Rx FIFO 1 */ 699 /** 700 * @} 701 */ 702 703 /** @defgroup FDCAN_event_type FDCAN Event Type 704 * @{ 705 */ 706 #define FDCAN_TX_EVENT ((uint32_t)0x00400000U) /*!< Tx event */ 707 #define FDCAN_TX_IN_SPITE_OF_ABORT ((uint32_t)0x00800000U) /*!< Transmission in spite of cancellation */ 708 /** 709 * @} 710 */ 711 712 /** @defgroup FDCAN_hp_msg_storage FDCAN High Priority Message Storage 713 * @{ 714 */ 715 #define FDCAN_HP_STORAGE_NO_FIFO ((uint32_t)0x00000000U) /*!< No FIFO selected */ 716 #define FDCAN_HP_STORAGE_MSG_LOST ((uint32_t)0x00000040U) /*!< FIFO message lost */ 717 #define FDCAN_HP_STORAGE_RXFIFO0 ((uint32_t)0x00000080U) /*!< Message stored in FIFO 0 */ 718 #define FDCAN_HP_STORAGE_RXFIFO1 ((uint32_t)0x000000C0U) /*!< Message stored in FIFO 1 */ 719 /** 720 * @} 721 */ 722 723 /** @defgroup FDCAN_protocol_error_code FDCAN protocol error code 724 * @{ 725 */ 726 #define FDCAN_PROTOCOL_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error occurred */ 727 #define FDCAN_PROTOCOL_ERROR_STUFF ((uint32_t)0x00000001U) /*!< Stuff error */ 728 #define FDCAN_PROTOCOL_ERROR_FORM ((uint32_t)0x00000002U) /*!< Form error */ 729 #define FDCAN_PROTOCOL_ERROR_ACK ((uint32_t)0x00000003U) /*!< Acknowledge error */ 730 #define FDCAN_PROTOCOL_ERROR_BIT1 ((uint32_t)0x00000004U) /*!< Bit 1 (recessive) error */ 731 #define FDCAN_PROTOCOL_ERROR_BIT0 ((uint32_t)0x00000005U) /*!< Bit 0 (dominant) error */ 732 #define FDCAN_PROTOCOL_ERROR_CRC ((uint32_t)0x00000006U) /*!< CRC check sum error */ 733 #define FDCAN_PROTOCOL_ERROR_NO_CHANGE ((uint32_t)0x00000007U) /*!< No change since last read */ 734 /** 735 * @} 736 */ 737 738 /** @defgroup FDCAN_communication_state FDCAN communication state 739 * @{ 740 */ 741 #define FDCAN_COM_STATE_SYNC ((uint32_t)0x00000000U) /*!< Node is synchronizing on CAN communication */ 742 #define FDCAN_COM_STATE_IDLE ((uint32_t)0x00000008U) /*!< Node is neither receiver nor transmitter */ 743 #define FDCAN_COM_STATE_RX ((uint32_t)0x00000010U) /*!< Node is operating as receiver */ 744 #define FDCAN_COM_STATE_TX ((uint32_t)0x00000018U) /*!< Node is operating as transmitter */ 745 /** 746 * @} 747 */ 748 749 /** @defgroup FDCAN_Rx_FIFO_operation_mode FDCAN FIFO operation mode 750 * @{ 751 */ 752 #define FDCAN_RX_FIFO_BLOCKING ((uint32_t)0x00000000U) /*!< Rx FIFO blocking mode */ 753 #define FDCAN_RX_FIFO_OVERWRITE ((uint32_t)0x00000001U) /*!< Rx FIFO overwrite mode */ 754 /** 755 * @} 756 */ 757 758 /** @defgroup FDCAN_Non_Matching_Frames FDCAN non-matching frames 759 * @{ 760 */ 761 #define FDCAN_ACCEPT_IN_RX_FIFO0 ((uint32_t)0x00000000U) /*!< Accept in Rx FIFO 0 */ 762 #define FDCAN_ACCEPT_IN_RX_FIFO1 ((uint32_t)0x00000001U) /*!< Accept in Rx FIFO 1 */ 763 #define FDCAN_REJECT ((uint32_t)0x00000002U) /*!< Reject */ 764 /** 765 * @} 766 */ 767 768 /** @defgroup FDCAN_Reject_Remote_Frames FDCAN reject remote frames 769 * @{ 770 */ 771 #define FDCAN_FILTER_REMOTE ((uint32_t)0x00000000U) /*!< Filter remote frames */ 772 #define FDCAN_REJECT_REMOTE ((uint32_t)0x00000001U) /*!< Reject all remote frames */ 773 /** 774 * @} 775 */ 776 777 /** @defgroup FDCAN_Interrupt_Line FDCAN interrupt line 778 * @{ 779 */ 780 #define FDCAN_INTERRUPT_LINE0 ((uint32_t)0x00000001U) /*!< Interrupt Line 0 */ 781 #define FDCAN_INTERRUPT_LINE1 ((uint32_t)0x00000002U) /*!< Interrupt Line 1 */ 782 /** 783 * @} 784 */ 785 786 /** @defgroup FDCAN_Timestamp FDCAN timestamp 787 * @{ 788 */ 789 #define FDCAN_TIMESTAMP_INTERNAL ((uint32_t)0x00000001U) /*!< Timestamp counter value incremented according to TCP */ 790 #define FDCAN_TIMESTAMP_EXTERNAL ((uint32_t)0x00000002U) /*!< External timestamp counter value used */ 791 /** 792 * @} 793 */ 794 795 /** @defgroup FDCAN_Timestamp_Prescaler FDCAN timestamp prescaler 796 * @{ 797 */ 798 #define FDCAN_TIMESTAMP_PRESC_1 ((uint32_t)0x00000000U) /*!< Timestamp counter time unit in equal to CAN bit time */ 799 #define FDCAN_TIMESTAMP_PRESC_2 ((uint32_t)0x00010000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 2 */ 800 #define FDCAN_TIMESTAMP_PRESC_3 ((uint32_t)0x00020000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 3 */ 801 #define FDCAN_TIMESTAMP_PRESC_4 ((uint32_t)0x00030000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 4 */ 802 #define FDCAN_TIMESTAMP_PRESC_5 ((uint32_t)0x00040000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 5 */ 803 #define FDCAN_TIMESTAMP_PRESC_6 ((uint32_t)0x00050000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 6 */ 804 #define FDCAN_TIMESTAMP_PRESC_7 ((uint32_t)0x00060000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 7 */ 805 #define FDCAN_TIMESTAMP_PRESC_8 ((uint32_t)0x00070000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 8 */ 806 #define FDCAN_TIMESTAMP_PRESC_9 ((uint32_t)0x00080000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 9 */ 807 #define FDCAN_TIMESTAMP_PRESC_10 ((uint32_t)0x00090000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 10 */ 808 #define FDCAN_TIMESTAMP_PRESC_11 ((uint32_t)0x000A0000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 11 */ 809 #define FDCAN_TIMESTAMP_PRESC_12 ((uint32_t)0x000B0000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 12 */ 810 #define FDCAN_TIMESTAMP_PRESC_13 ((uint32_t)0x000C0000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 13 */ 811 #define FDCAN_TIMESTAMP_PRESC_14 ((uint32_t)0x000D0000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 14 */ 812 #define FDCAN_TIMESTAMP_PRESC_15 ((uint32_t)0x000E0000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 15 */ 813 #define FDCAN_TIMESTAMP_PRESC_16 ((uint32_t)0x000F0000U) /*!< Timestamp counter time unit in equal to CAN bit time multiplied by 16 */ 814 /** 815 * @} 816 */ 817 818 /** @defgroup FDCAN_Timeout_Operation FDCAN timeout operation 819 * @{ 820 */ 821 #define FDCAN_TIMEOUT_CONTINUOUS ((uint32_t)0x00000000U) /*!< Timeout continuous operation */ 822 #define FDCAN_TIMEOUT_TX_EVENT_FIFO ((uint32_t)0x00000002U) /*!< Timeout controlled by Tx Event FIFO */ 823 #define FDCAN_TIMEOUT_RX_FIFO0 ((uint32_t)0x00000004U) /*!< Timeout controlled by Rx FIFO 0 */ 824 #define FDCAN_TIMEOUT_RX_FIFO1 ((uint32_t)0x00000006U) /*!< Timeout controlled by Rx FIFO 1 */ 825 /** 826 * @} 827 */ 828 829 /** @defgroup Interrupt_Masks Interrupt masks 830 * @{ 831 */ 832 #define FDCAN_IR_MASK ((uint32_t)0x00FFFFFFU) /*!< FDCAN interrupts mask */ 833 #define FDCAN_ILS_MASK ((uint32_t)0x0000007FU) /*!< FDCAN interrupts group mask */ 834 /** 835 * @} 836 */ 837 838 /** @defgroup FDCAN_flags FDCAN Flags 839 * @{ 840 */ 841 #define FDCAN_FLAG_TX_COMPLETE FDCAN_IR_TC /*!< Transmission Completed */ 842 #define FDCAN_FLAG_TX_ABORT_COMPLETE FDCAN_IR_TCF /*!< Transmission Cancellation Finished */ 843 #define FDCAN_FLAG_TX_FIFO_EMPTY FDCAN_IR_TFE /*!< Tx FIFO Empty */ 844 #define FDCAN_FLAG_RX_HIGH_PRIORITY_MSG FDCAN_IR_HPM /*!< High priority message received */ 845 #define FDCAN_FLAG_TX_EVT_FIFO_ELT_LOST FDCAN_IR_TEFL /*!< Tx Event FIFO element lost */ 846 #define FDCAN_FLAG_TX_EVT_FIFO_FULL FDCAN_IR_TEFF /*!< Tx Event FIFO full */ 847 #define FDCAN_FLAG_TX_EVT_FIFO_NEW_DATA FDCAN_IR_TEFN /*!< Tx Handler wrote Tx Event FIFO element */ 848 #define FDCAN_FLAG_RX_FIFO0_MESSAGE_LOST FDCAN_IR_RF0L /*!< Rx FIFO 0 message lost */ 849 #define FDCAN_FLAG_RX_FIFO0_FULL FDCAN_IR_RF0F /*!< Rx FIFO 0 full */ 850 #define FDCAN_FLAG_RX_FIFO0_NEW_MESSAGE FDCAN_IR_RF0N /*!< New message written to Rx FIFO 0 */ 851 #define FDCAN_FLAG_RX_FIFO1_MESSAGE_LOST FDCAN_IR_RF1L /*!< Rx FIFO 1 message lost */ 852 #define FDCAN_FLAG_RX_FIFO1_FULL FDCAN_IR_RF1F /*!< Rx FIFO 1 full */ 853 #define FDCAN_FLAG_RX_FIFO1_NEW_MESSAGE FDCAN_IR_RF1N /*!< New message written to Rx FIFO 1 */ 854 #define FDCAN_FLAG_RAM_ACCESS_FAILURE FDCAN_IR_MRAF /*!< Message RAM access failure occurred */ 855 #define FDCAN_FLAG_ERROR_LOGGING_OVERFLOW FDCAN_IR_ELO /*!< Overflow of FDCAN Error Logging Counter occurred */ 856 #define FDCAN_FLAG_ERROR_PASSIVE FDCAN_IR_EP /*!< Error_Passive status changed */ 857 #define FDCAN_FLAG_ERROR_WARNING FDCAN_IR_EW /*!< Error_Warning status changed */ 858 #define FDCAN_FLAG_BUS_OFF FDCAN_IR_BO /*!< Bus_Off status changed */ 859 #define FDCAN_FLAG_RAM_WATCHDOG FDCAN_IR_WDI /*!< Message RAM Watchdog event due to missing READY */ 860 #define FDCAN_FLAG_ARB_PROTOCOL_ERROR FDCAN_IR_PEA /*!< Protocol error in arbitration phase detected */ 861 #define FDCAN_FLAG_DATA_PROTOCOL_ERROR FDCAN_IR_PED /*!< Protocol error in data phase detected */ 862 #define FDCAN_FLAG_RESERVED_ADDRESS_ACCESS FDCAN_IR_ARA /*!< Access to reserved address occurred */ 863 #define FDCAN_FLAG_TIMESTAMP_WRAPAROUND FDCAN_IR_TSW /*!< Timestamp counter wrapped around */ 864 #define FDCAN_FLAG_TIMEOUT_OCCURRED FDCAN_IR_TOO /*!< Timeout reached */ 865 /** 866 * @} 867 */ 868 869 /** @defgroup FDCAN_Interrupts FDCAN Interrupts 870 * @{ 871 */ 872 873 /** @defgroup FDCAN_Tx_Interrupts FDCAN Tx Interrupts 874 * @{ 875 */ 876 #define FDCAN_IT_TX_COMPLETE FDCAN_IE_TCE /*!< Transmission Completed */ 877 #define FDCAN_IT_TX_ABORT_COMPLETE FDCAN_IE_TCFE /*!< Transmission Cancellation Finished */ 878 #define FDCAN_IT_TX_FIFO_EMPTY FDCAN_IE_TFEE /*!< Tx FIFO Empty */ 879 /** 880 * @} 881 */ 882 883 /** @defgroup FDCAN_Rx_Interrupts FDCAN Rx Interrupts 884 * @{ 885 */ 886 #define FDCAN_IT_RX_HIGH_PRIORITY_MSG FDCAN_IE_HPME /*!< High priority message received */ 887 /** 888 * @} 889 */ 890 891 /** @defgroup FDCAN_Counter_Interrupts FDCAN Counter Interrupts 892 * @{ 893 */ 894 #define FDCAN_IT_TIMESTAMP_WRAPAROUND FDCAN_IE_TSWE /*!< Timestamp counter wrapped around */ 895 #define FDCAN_IT_TIMEOUT_OCCURRED FDCAN_IE_TOOE /*!< Timeout reached */ 896 /** 897 * @} 898 */ 899 900 /** @defgroup FDCAN_Tx_Event_Fifo_Interrupts FDCAN Tx Event FIFO Interrupts 901 * @{ 902 */ 903 #define FDCAN_IT_TX_EVT_FIFO_ELT_LOST FDCAN_IE_TEFLE /*!< Tx Event FIFO element lost */ 904 #define FDCAN_IT_TX_EVT_FIFO_FULL FDCAN_IE_TEFFE /*!< Tx Event FIFO full */ 905 #define FDCAN_IT_TX_EVT_FIFO_NEW_DATA FDCAN_IE_TEFNE /*!< Tx Handler wrote Tx Event FIFO element */ 906 /** 907 * @} 908 */ 909 910 /** @defgroup FDCAN_Rx_Fifo0_Interrupts FDCAN Rx FIFO 0 Interrupts 911 * @{ 912 */ 913 #define FDCAN_IT_RX_FIFO0_MESSAGE_LOST FDCAN_IE_RF0LE /*!< Rx FIFO 0 message lost */ 914 #define FDCAN_IT_RX_FIFO0_FULL FDCAN_IE_RF0FE /*!< Rx FIFO 0 full */ 915 #define FDCAN_IT_RX_FIFO0_NEW_MESSAGE FDCAN_IE_RF0NE /*!< New message written to Rx FIFO 0 */ 916 /** 917 * @} 918 */ 919 920 /** @defgroup FDCAN_Rx_Fifo1_Interrupts FDCAN Rx FIFO 1 Interrupts 921 * @{ 922 */ 923 #define FDCAN_IT_RX_FIFO1_MESSAGE_LOST FDCAN_IE_RF1LE /*!< Rx FIFO 1 message lost */ 924 #define FDCAN_IT_RX_FIFO1_FULL FDCAN_IE_RF1FE /*!< Rx FIFO 1 full */ 925 #define FDCAN_IT_RX_FIFO1_NEW_MESSAGE FDCAN_IE_RF1NE /*!< New message written to Rx FIFO 1 */ 926 /** 927 * @} 928 */ 929 930 /** @defgroup FDCAN_Error_Interrupts FDCAN Error Interrupts 931 * @{ 932 */ 933 #define FDCAN_IT_RAM_ACCESS_FAILURE FDCAN_IE_MRAFE /*!< Message RAM access failure occurred */ 934 #define FDCAN_IT_ERROR_LOGGING_OVERFLOW FDCAN_IE_ELOE /*!< Overflow of FDCAN Error Logging Counter occurred */ 935 #define FDCAN_IT_RAM_WATCHDOG FDCAN_IE_WDIE /*!< Message RAM Watchdog event due to missing READY */ 936 #define FDCAN_IT_ARB_PROTOCOL_ERROR FDCAN_IE_PEAE /*!< Protocol error in arbitration phase detected */ 937 #define FDCAN_IT_DATA_PROTOCOL_ERROR FDCAN_IE_PEDE /*!< Protocol error in data phase detected */ 938 #define FDCAN_IT_RESERVED_ADDRESS_ACCESS FDCAN_IE_ARAE /*!< Access to reserved address occurred */ 939 /** 940 * @} 941 */ 942 943 /** @defgroup FDCAN_Error_Status_Interrupts FDCAN Error Status Interrupts 944 * @{ 945 */ 946 #define FDCAN_IT_ERROR_PASSIVE FDCAN_IE_EPE /*!< Error_Passive status changed */ 947 #define FDCAN_IT_ERROR_WARNING FDCAN_IE_EWE /*!< Error_Warning status changed */ 948 #define FDCAN_IT_BUS_OFF FDCAN_IE_BOE /*!< Bus_Off status changed */ 949 /** 950 * @} 951 */ 952 953 /** 954 * @} 955 */ 956 957 /** @defgroup FDCAN_Interrupts_List FDCAN Interrupts List 958 * @{ 959 */ 960 #define FDCAN_IT_LIST_RX_FIFO0 (FDCAN_IT_RX_FIFO0_MESSAGE_LOST | \ 961 FDCAN_IT_RX_FIFO0_FULL | \ 962 FDCAN_IT_RX_FIFO0_NEW_MESSAGE) /*!< RX FIFO 0 Interrupts List */ 963 #define FDCAN_IT_LIST_RX_FIFO1 (FDCAN_IT_RX_FIFO1_MESSAGE_LOST | \ 964 FDCAN_IT_RX_FIFO1_FULL | \ 965 FDCAN_IT_RX_FIFO1_NEW_MESSAGE) /*!< RX FIFO 1 Interrupts List */ 966 #define FDCAN_IT_LIST_SMSG (FDCAN_IT_TX_ABORT_COMPLETE | \ 967 FDCAN_IT_TX_COMPLETE | \ 968 FDCAN_IT_RX_HIGH_PRIORITY_MSG) /*!< Status Message Interrupts List */ 969 #define FDCAN_IT_LIST_TX_FIFO_ERROR (FDCAN_IT_TX_EVT_FIFO_ELT_LOST | \ 970 FDCAN_IT_TX_EVT_FIFO_FULL | \ 971 FDCAN_IT_TX_EVT_FIFO_NEW_DATA | \ 972 FDCAN_IT_TX_FIFO_EMPTY) /*!< TX FIFO Error Interrupts List */ 973 #define FDCAN_IT_LIST_MISC (FDCAN_IT_TIMEOUT_OCCURRED | \ 974 FDCAN_IT_RAM_ACCESS_FAILURE | \ 975 FDCAN_IT_TIMESTAMP_WRAPAROUND) /*!< Misc. Interrupts List */ 976 #define FDCAN_IT_LIST_BIT_LINE_ERROR (FDCAN_IT_ERROR_PASSIVE | \ 977 FDCAN_IT_ERROR_LOGGING_OVERFLOW) /*!< Bit and Line Error Interrupts List */ 978 #define FDCAN_IT_LIST_PROTOCOL_ERROR (FDCAN_IT_RESERVED_ADDRESS_ACCESS | \ 979 FDCAN_IT_DATA_PROTOCOL_ERROR | \ 980 FDCAN_IT_ARB_PROTOCOL_ERROR | \ 981 FDCAN_IT_RAM_WATCHDOG | \ 982 FDCAN_IT_BUS_OFF | \ 983 FDCAN_IT_ERROR_WARNING) /*!< Protocol Error Interrupts List */ 984 /** 985 * @} 986 */ 987 988 /** @defgroup FDCAN_Interrupts_Group FDCAN Interrupts Group 989 * @{ 990 */ 991 #define FDCAN_IT_GROUP_RX_FIFO0 FDCAN_ILS_RXFIFO0 /*!< RX FIFO 0 Interrupts Group: 992 RF0LL: Rx FIFO 0 Message Lost 993 RF0FL: Rx FIFO 0 is Full 994 RF0NL: Rx FIFO 0 Has New Message */ 995 #define FDCAN_IT_GROUP_RX_FIFO1 FDCAN_ILS_RXFIFO1 /*!< RX FIFO 1 Interrupts Group: 996 RF1LL: Rx FIFO 1 Message Lost 997 RF1FL: Rx FIFO 1 is Full 998 RF1NL: Rx FIFO 1 Has New Message */ 999 #define FDCAN_IT_GROUP_SMSG FDCAN_ILS_SMSG /*!< Status Message Interrupts Group: 1000 TCFL: Transmission Cancellation Finished 1001 TCL: Transmission Completed 1002 HPML: High Priority Message */ 1003 #define FDCAN_IT_GROUP_TX_FIFO_ERROR FDCAN_ILS_TFERR /*!< TX FIFO Error Interrupts Group: 1004 TEFLL: Tx Event FIFO Element Lost 1005 TEFFL: Tx Event FIFO Full 1006 TEFNL: Tx Event FIFO New Entry 1007 TFEL: Tx FIFO Empty Interrupt Line */ 1008 #define FDCAN_IT_GROUP_MISC FDCAN_ILS_MISC /*!< Misc. Interrupts Group: 1009 TOOL: Timeout Occurred 1010 MRAFL: Message RAM Access Failure 1011 TSWL: Timestamp Wraparound */ 1012 #define FDCAN_IT_GROUP_BIT_LINE_ERROR FDCAN_ILS_BERR /*!< Bit and Line Error Interrupts Group: 1013 EPL: Error Passive 1014 ELOL: Error Logging Overflow */ 1015 #define FDCAN_IT_GROUP_PROTOCOL_ERROR FDCAN_ILS_PERR /*!< Protocol Error Group: 1016 ARAL: Access to Reserved Address Line 1017 PEDL: Protocol Error in Data Phase Line 1018 PEAL: Protocol Error in Arbitration Phase Line 1019 WDIL: Watchdog Interrupt Line 1020 BOL: Bus_Off Status 1021 EWL: Warning Status */ 1022 /** 1023 * @} 1024 */ 1025 1026 /** 1027 * @} 1028 */ 1029 1030 /* Exported macro ------------------------------------------------------------*/ 1031 /** @defgroup FDCAN_Exported_Macros FDCAN Exported Macros 1032 * @{ 1033 */ 1034 1035 /** @brief Reset FDCAN handle state. 1036 * @param __HANDLE__ FDCAN handle. 1037 * @retval None 1038 */ 1039 #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 1040 #define __HAL_FDCAN_RESET_HANDLE_STATE(__HANDLE__) do{ \ 1041 (__HANDLE__)->State = HAL_FDCAN_STATE_RESET; \ 1042 (__HANDLE__)->MspInitCallback = NULL; \ 1043 (__HANDLE__)->MspDeInitCallback = NULL; \ 1044 } while(0) 1045 #else 1046 #define __HAL_FDCAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_FDCAN_STATE_RESET) 1047 #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ 1048 1049 /** 1050 * @brief Enable the specified FDCAN interrupts. 1051 * @param __HANDLE__ FDCAN handle. 1052 * @param __INTERRUPT__ FDCAN interrupt. 1053 * This parameter can be any combination of @arg FDCAN_Interrupts 1054 * @retval None 1055 */ 1056 #define __HAL_FDCAN_ENABLE_IT(__HANDLE__, __INTERRUPT__) \ 1057 (__HANDLE__)->Instance->IE |= (__INTERRUPT__) 1058 1059 /** 1060 * @brief Disable the specified FDCAN interrupts. 1061 * @param __HANDLE__ FDCAN handle. 1062 * @param __INTERRUPT__ FDCAN interrupt. 1063 * This parameter can be any combination of @arg FDCAN_Interrupts 1064 * @retval None 1065 */ 1066 #define __HAL_FDCAN_DISABLE_IT(__HANDLE__, __INTERRUPT__) \ 1067 ((__HANDLE__)->Instance->IE) &= ~(__INTERRUPT__) 1068 1069 /** 1070 * @brief Check whether the specified FDCAN interrupt is set or not. 1071 * @param __HANDLE__ FDCAN handle. 1072 * @param __INTERRUPT__ FDCAN interrupt. 1073 * This parameter can be one of @arg FDCAN_Interrupts 1074 * @retval ITStatus 1075 */ 1076 #define __HAL_FDCAN_GET_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IR & (__INTERRUPT__)) 1077 1078 /** 1079 * @brief Clear the specified FDCAN interrupts. 1080 * @param __HANDLE__ FDCAN handle. 1081 * @param __INTERRUPT__ specifies the interrupts to clear. 1082 * This parameter can be any combination of @arg FDCAN_Interrupts 1083 * @retval None 1084 */ 1085 #define __HAL_FDCAN_CLEAR_IT(__HANDLE__, __INTERRUPT__) \ 1086 ((__HANDLE__)->Instance->IR) = (__INTERRUPT__) 1087 1088 /** 1089 * @brief Check whether the specified FDCAN flag is set or not. 1090 * @param __HANDLE__ FDCAN handle. 1091 * @param __FLAG__ FDCAN flag. 1092 * This parameter can be one of @arg FDCAN_flags 1093 * @retval FlagStatus 1094 */ 1095 #define __HAL_FDCAN_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->IR & (__FLAG__)) 1096 1097 /** 1098 * @brief Clear the specified FDCAN flags. 1099 * @param __HANDLE__ FDCAN handle. 1100 * @param __FLAG__ specifies the flags to clear. 1101 * This parameter can be any combination of @arg FDCAN_flags 1102 * @retval None 1103 */ 1104 #define __HAL_FDCAN_CLEAR_FLAG(__HANDLE__, __FLAG__) \ 1105 ((__HANDLE__)->Instance->IR) = (__FLAG__) 1106 1107 /** @brief Check if the specified FDCAN interrupt source is enabled or disabled. 1108 * @param __HANDLE__ FDCAN handle. 1109 * @param __INTERRUPT__ specifies the FDCAN interrupt source to check. 1110 * This parameter can be a value of @arg FDCAN_Interrupts 1111 * @retval ITStatus 1112 */ 1113 #define __HAL_FDCAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IE & (__INTERRUPT__)) 1114 1115 /** 1116 * @} 1117 */ 1118 1119 /* Exported functions --------------------------------------------------------*/ 1120 /** @addtogroup FDCAN_Exported_Functions 1121 * @{ 1122 */ 1123 1124 /** @addtogroup FDCAN_Exported_Functions_Group1 1125 * @{ 1126 */ 1127 /* Initialization and de-initialization functions *****************************/ 1128 HAL_StatusTypeDef HAL_FDCAN_Init(FDCAN_HandleTypeDef *hfdcan); 1129 HAL_StatusTypeDef HAL_FDCAN_DeInit(FDCAN_HandleTypeDef *hfdcan); 1130 void HAL_FDCAN_MspInit(FDCAN_HandleTypeDef *hfdcan); 1131 void HAL_FDCAN_MspDeInit(FDCAN_HandleTypeDef *hfdcan); 1132 HAL_StatusTypeDef HAL_FDCAN_EnterPowerDownMode(FDCAN_HandleTypeDef *hfdcan); 1133 HAL_StatusTypeDef HAL_FDCAN_ExitPowerDownMode(FDCAN_HandleTypeDef *hfdcan); 1134 1135 #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1 1136 /* Callbacks Register/UnRegister functions ***********************************/ 1137 HAL_StatusTypeDef HAL_FDCAN_RegisterCallback(FDCAN_HandleTypeDef *hfdcan, HAL_FDCAN_CallbackIDTypeDef CallbackID, 1138 pFDCAN_CallbackTypeDef pCallback); 1139 HAL_StatusTypeDef HAL_FDCAN_UnRegisterCallback(FDCAN_HandleTypeDef *hfdcan, HAL_FDCAN_CallbackIDTypeDef CallbackID); 1140 HAL_StatusTypeDef HAL_FDCAN_RegisterTxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan, 1141 pFDCAN_TxEventFifoCallbackTypeDef pCallback); 1142 HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan); 1143 HAL_StatusTypeDef HAL_FDCAN_RegisterRxFifo0Callback(FDCAN_HandleTypeDef *hfdcan, 1144 pFDCAN_RxFifo0CallbackTypeDef pCallback); 1145 HAL_StatusTypeDef HAL_FDCAN_UnRegisterRxFifo0Callback(FDCAN_HandleTypeDef *hfdcan); 1146 HAL_StatusTypeDef HAL_FDCAN_RegisterRxFifo1Callback(FDCAN_HandleTypeDef *hfdcan, 1147 pFDCAN_RxFifo1CallbackTypeDef pCallback); 1148 HAL_StatusTypeDef HAL_FDCAN_UnRegisterRxFifo1Callback(FDCAN_HandleTypeDef *hfdcan); 1149 HAL_StatusTypeDef HAL_FDCAN_RegisterTxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan, 1150 pFDCAN_TxBufferCompleteCallbackTypeDef pCallback); 1151 HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan); 1152 HAL_StatusTypeDef HAL_FDCAN_RegisterTxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan, 1153 pFDCAN_TxBufferAbortCallbackTypeDef pCallback); 1154 HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan); 1155 HAL_StatusTypeDef HAL_FDCAN_RegisterErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan, 1156 pFDCAN_ErrorStatusCallbackTypeDef pCallback); 1157 HAL_StatusTypeDef HAL_FDCAN_UnRegisterErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan); 1158 #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */ 1159 /** 1160 * @} 1161 */ 1162 1163 /** @addtogroup FDCAN_Exported_Functions_Group2 1164 * @{ 1165 */ 1166 /* Configuration functions ****************************************************/ 1167 HAL_StatusTypeDef HAL_FDCAN_ConfigFilter(FDCAN_HandleTypeDef *hfdcan, FDCAN_FilterTypeDef *sFilterConfig); 1168 HAL_StatusTypeDef HAL_FDCAN_ConfigGlobalFilter(FDCAN_HandleTypeDef *hfdcan, uint32_t NonMatchingStd, 1169 uint32_t NonMatchingExt, uint32_t RejectRemoteStd, 1170 uint32_t RejectRemoteExt); 1171 HAL_StatusTypeDef HAL_FDCAN_ConfigExtendedIdMask(FDCAN_HandleTypeDef *hfdcan, uint32_t Mask); 1172 HAL_StatusTypeDef HAL_FDCAN_ConfigRxFifoOverwrite(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo, uint32_t OperationMode); 1173 HAL_StatusTypeDef HAL_FDCAN_ConfigRamWatchdog(FDCAN_HandleTypeDef *hfdcan, uint32_t CounterStartValue); 1174 HAL_StatusTypeDef HAL_FDCAN_ConfigTimestampCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimestampPrescaler); 1175 HAL_StatusTypeDef HAL_FDCAN_EnableTimestampCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimestampOperation); 1176 HAL_StatusTypeDef HAL_FDCAN_DisableTimestampCounter(FDCAN_HandleTypeDef *hfdcan); 1177 uint16_t HAL_FDCAN_GetTimestampCounter(FDCAN_HandleTypeDef *hfdcan); 1178 HAL_StatusTypeDef HAL_FDCAN_ResetTimestampCounter(FDCAN_HandleTypeDef *hfdcan); 1179 HAL_StatusTypeDef HAL_FDCAN_ConfigTimeoutCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimeoutOperation, 1180 uint32_t TimeoutPeriod); 1181 HAL_StatusTypeDef HAL_FDCAN_EnableTimeoutCounter(FDCAN_HandleTypeDef *hfdcan); 1182 HAL_StatusTypeDef HAL_FDCAN_DisableTimeoutCounter(FDCAN_HandleTypeDef *hfdcan); 1183 uint16_t HAL_FDCAN_GetTimeoutCounter(FDCAN_HandleTypeDef *hfdcan); 1184 HAL_StatusTypeDef HAL_FDCAN_ResetTimeoutCounter(FDCAN_HandleTypeDef *hfdcan); 1185 HAL_StatusTypeDef HAL_FDCAN_ConfigTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan, uint32_t TdcOffset, 1186 uint32_t TdcFilter); 1187 HAL_StatusTypeDef HAL_FDCAN_EnableTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan); 1188 HAL_StatusTypeDef HAL_FDCAN_DisableTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan); 1189 HAL_StatusTypeDef HAL_FDCAN_EnableISOMode(FDCAN_HandleTypeDef *hfdcan); 1190 HAL_StatusTypeDef HAL_FDCAN_DisableISOMode(FDCAN_HandleTypeDef *hfdcan); 1191 HAL_StatusTypeDef HAL_FDCAN_EnableEdgeFiltering(FDCAN_HandleTypeDef *hfdcan); 1192 HAL_StatusTypeDef HAL_FDCAN_DisableEdgeFiltering(FDCAN_HandleTypeDef *hfdcan); 1193 /** 1194 * @} 1195 */ 1196 1197 /** @addtogroup FDCAN_Exported_Functions_Group3 1198 * @{ 1199 */ 1200 /* Control functions **********************************************************/ 1201 HAL_StatusTypeDef HAL_FDCAN_Start(FDCAN_HandleTypeDef *hfdcan); 1202 HAL_StatusTypeDef HAL_FDCAN_Stop(FDCAN_HandleTypeDef *hfdcan); 1203 HAL_StatusTypeDef HAL_FDCAN_AddMessageToTxFifoQ(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, 1204 uint8_t *pTxData); 1205 uint32_t HAL_FDCAN_GetLatestTxFifoQRequestBuffer(FDCAN_HandleTypeDef *hfdcan); 1206 HAL_StatusTypeDef HAL_FDCAN_AbortTxRequest(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndex); 1207 HAL_StatusTypeDef HAL_FDCAN_GetRxMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t RxLocation, 1208 FDCAN_RxHeaderTypeDef *pRxHeader, uint8_t *pRxData); 1209 HAL_StatusTypeDef HAL_FDCAN_GetTxEvent(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxEventFifoTypeDef *pTxEvent); 1210 HAL_StatusTypeDef HAL_FDCAN_GetHighPriorityMessageStatus(FDCAN_HandleTypeDef *hfdcan, 1211 FDCAN_HpMsgStatusTypeDef *HpMsgStatus); 1212 HAL_StatusTypeDef HAL_FDCAN_GetProtocolStatus(FDCAN_HandleTypeDef *hfdcan, FDCAN_ProtocolStatusTypeDef *ProtocolStatus); 1213 HAL_StatusTypeDef HAL_FDCAN_GetErrorCounters(FDCAN_HandleTypeDef *hfdcan, FDCAN_ErrorCountersTypeDef *ErrorCounters); 1214 uint32_t HAL_FDCAN_IsTxBufferMessagePending(FDCAN_HandleTypeDef *hfdcan, uint32_t TxBufferIndex); 1215 uint32_t HAL_FDCAN_GetRxFifoFillLevel(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo); 1216 uint32_t HAL_FDCAN_GetTxFifoFreeLevel(FDCAN_HandleTypeDef *hfdcan); 1217 uint32_t HAL_FDCAN_IsRestrictedOperationMode(FDCAN_HandleTypeDef *hfdcan); 1218 HAL_StatusTypeDef HAL_FDCAN_ExitRestrictedOperationMode(FDCAN_HandleTypeDef *hfdcan); 1219 /** 1220 * @} 1221 */ 1222 1223 /** @addtogroup FDCAN_Exported_Functions_Group4 1224 * @{ 1225 */ 1226 /* Interrupts management ******************************************************/ 1227 HAL_StatusTypeDef HAL_FDCAN_ConfigInterruptLines(FDCAN_HandleTypeDef *hfdcan, uint32_t ITList, uint32_t InterruptLine); 1228 HAL_StatusTypeDef HAL_FDCAN_ActivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t ActiveITs, 1229 uint32_t BufferIndexes); 1230 HAL_StatusTypeDef HAL_FDCAN_DeactivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t InactiveITs); 1231 void HAL_FDCAN_IRQHandler(FDCAN_HandleTypeDef *hfdcan); 1232 /** 1233 * @} 1234 */ 1235 1236 /** @addtogroup FDCAN_Exported_Functions_Group5 1237 * @{ 1238 */ 1239 /* Callback functions *********************************************************/ 1240 void HAL_FDCAN_TxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TxEventFifoITs); 1241 void HAL_FDCAN_RxFifo0Callback(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo0ITs); 1242 void HAL_FDCAN_RxFifo1Callback(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo1ITs); 1243 void HAL_FDCAN_TxFifoEmptyCallback(FDCAN_HandleTypeDef *hfdcan); 1244 void HAL_FDCAN_TxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes); 1245 void HAL_FDCAN_TxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes); 1246 void HAL_FDCAN_HighPriorityMessageCallback(FDCAN_HandleTypeDef *hfdcan); 1247 void HAL_FDCAN_TimestampWraparoundCallback(FDCAN_HandleTypeDef *hfdcan); 1248 void HAL_FDCAN_TimeoutOccurredCallback(FDCAN_HandleTypeDef *hfdcan); 1249 void HAL_FDCAN_ErrorCallback(FDCAN_HandleTypeDef *hfdcan); 1250 void HAL_FDCAN_ErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t ErrorStatusITs); 1251 /** 1252 * @} 1253 */ 1254 1255 /** @addtogroup FDCAN_Exported_Functions_Group6 1256 * @{ 1257 */ 1258 /* Peripheral State functions *************************************************/ 1259 uint32_t HAL_FDCAN_GetError(FDCAN_HandleTypeDef *hfdcan); 1260 HAL_FDCAN_StateTypeDef HAL_FDCAN_GetState(FDCAN_HandleTypeDef *hfdcan); 1261 /** 1262 * @} 1263 */ 1264 1265 /** 1266 * @} 1267 */ 1268 1269 /* Private types -------------------------------------------------------------*/ 1270 /* Private variables ---------------------------------------------------------*/ 1271 /** @defgroup FDCAN_Private_Variables FDCAN Private Variables 1272 * @{ 1273 */ 1274 1275 /** 1276 * @} 1277 */ 1278 1279 /* Private constants ---------------------------------------------------------*/ 1280 /** @defgroup FDCAN_Private_Constants FDCAN Private Constants 1281 * @{ 1282 */ 1283 1284 /** 1285 * @} 1286 */ 1287 1288 /* Private macros ------------------------------------------------------------*/ 1289 /** @defgroup FDCAN_Private_Macros FDCAN Private Macros 1290 * @{ 1291 */ 1292 #define IS_FDCAN_FRAME_FORMAT(FORMAT) (((FORMAT) == FDCAN_FRAME_CLASSIC ) || \ 1293 ((FORMAT) == FDCAN_FRAME_FD_NO_BRS) || \ 1294 ((FORMAT) == FDCAN_FRAME_FD_BRS )) 1295 #define IS_FDCAN_MODE(MODE) (((MODE) == FDCAN_MODE_NORMAL ) || \ 1296 ((MODE) == FDCAN_MODE_RESTRICTED_OPERATION) || \ 1297 ((MODE) == FDCAN_MODE_BUS_MONITORING ) || \ 1298 ((MODE) == FDCAN_MODE_INTERNAL_LOOPBACK ) || \ 1299 ((MODE) == FDCAN_MODE_EXTERNAL_LOOPBACK )) 1300 #define IS_FDCAN_CKDIV(CKDIV) (((CKDIV) == FDCAN_CLOCK_DIV1 ) || \ 1301 ((CKDIV) == FDCAN_CLOCK_DIV2 ) || \ 1302 ((CKDIV) == FDCAN_CLOCK_DIV4 ) || \ 1303 ((CKDIV) == FDCAN_CLOCK_DIV6 ) || \ 1304 ((CKDIV) == FDCAN_CLOCK_DIV8 ) || \ 1305 ((CKDIV) == FDCAN_CLOCK_DIV10) || \ 1306 ((CKDIV) == FDCAN_CLOCK_DIV12) || \ 1307 ((CKDIV) == FDCAN_CLOCK_DIV14) || \ 1308 ((CKDIV) == FDCAN_CLOCK_DIV16) || \ 1309 ((CKDIV) == FDCAN_CLOCK_DIV18) || \ 1310 ((CKDIV) == FDCAN_CLOCK_DIV20) || \ 1311 ((CKDIV) == FDCAN_CLOCK_DIV22) || \ 1312 ((CKDIV) == FDCAN_CLOCK_DIV24) || \ 1313 ((CKDIV) == FDCAN_CLOCK_DIV26) || \ 1314 ((CKDIV) == FDCAN_CLOCK_DIV28) || \ 1315 ((CKDIV) == FDCAN_CLOCK_DIV30)) 1316 #define IS_FDCAN_NOMINAL_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 512U)) 1317 #define IS_FDCAN_NOMINAL_SJW(SJW) (((SJW) >= 1U) && ((SJW) <= 128U)) 1318 #define IS_FDCAN_NOMINAL_TSEG1(TSEG1) (((TSEG1) >= 1U) && ((TSEG1) <= 256U)) 1319 #define IS_FDCAN_NOMINAL_TSEG2(TSEG2) (((TSEG2) >= 1U) && ((TSEG2) <= 128U)) 1320 #define IS_FDCAN_DATA_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 32U)) 1321 #define IS_FDCAN_DATA_SJW(SJW) (((SJW) >= 1U) && ((SJW) <= 16U)) 1322 #define IS_FDCAN_DATA_TSEG1(TSEG1) (((TSEG1) >= 1U) && ((TSEG1) <= 32U)) 1323 #define IS_FDCAN_DATA_TSEG2(TSEG2) (((TSEG2) >= 1U) && ((TSEG2) <= 16U)) 1324 #define IS_FDCAN_MAX_VALUE(VALUE, _MAX_) ((VALUE) <= (_MAX_)) 1325 #define IS_FDCAN_MIN_VALUE(VALUE, _MIN_) ((VALUE) >= (_MIN_)) 1326 #define IS_FDCAN_TX_FIFO_QUEUE_MODE(MODE) (((MODE) == FDCAN_TX_FIFO_OPERATION ) || \ 1327 ((MODE) == FDCAN_TX_QUEUE_OPERATION)) 1328 #define IS_FDCAN_ID_TYPE(ID_TYPE) (((ID_TYPE) == FDCAN_STANDARD_ID) || \ 1329 ((ID_TYPE) == FDCAN_EXTENDED_ID)) 1330 #define IS_FDCAN_FILTER_CFG(CONFIG) (((CONFIG) == FDCAN_FILTER_DISABLE ) || \ 1331 ((CONFIG) == FDCAN_FILTER_TO_RXFIFO0 ) || \ 1332 ((CONFIG) == FDCAN_FILTER_TO_RXFIFO1 ) || \ 1333 ((CONFIG) == FDCAN_FILTER_REJECT ) || \ 1334 ((CONFIG) == FDCAN_FILTER_HP ) || \ 1335 ((CONFIG) == FDCAN_FILTER_TO_RXFIFO0_HP) || \ 1336 ((CONFIG) == FDCAN_FILTER_TO_RXFIFO1_HP)) 1337 #define IS_FDCAN_TX_LOCATION(LOCATION) (((LOCATION) == FDCAN_TX_BUFFER0 ) || ((LOCATION) == FDCAN_TX_BUFFER1 ) || \ 1338 ((LOCATION) == FDCAN_TX_BUFFER2 )) 1339 #define IS_FDCAN_TX_LOCATION_LIST(LOCATION) (((LOCATION) >= FDCAN_TX_BUFFER0) && \ 1340 ((LOCATION) <= (FDCAN_TX_BUFFER0 | FDCAN_TX_BUFFER1 | FDCAN_TX_BUFFER2))) 1341 #define IS_FDCAN_RX_FIFO(FIFO) (((FIFO) == FDCAN_RX_FIFO0) || \ 1342 ((FIFO) == FDCAN_RX_FIFO1)) 1343 #define IS_FDCAN_RX_FIFO_MODE(MODE) (((MODE) == FDCAN_RX_FIFO_BLOCKING ) || \ 1344 ((MODE) == FDCAN_RX_FIFO_OVERWRITE)) 1345 #define IS_FDCAN_STD_FILTER_TYPE(TYPE) (((TYPE) == FDCAN_FILTER_RANGE) || \ 1346 ((TYPE) == FDCAN_FILTER_DUAL ) || \ 1347 ((TYPE) == FDCAN_FILTER_MASK )) 1348 #define IS_FDCAN_EXT_FILTER_TYPE(TYPE) (((TYPE) == FDCAN_FILTER_RANGE ) || \ 1349 ((TYPE) == FDCAN_FILTER_DUAL ) || \ 1350 ((TYPE) == FDCAN_FILTER_MASK ) || \ 1351 ((TYPE) == FDCAN_FILTER_RANGE_NO_EIDM)) 1352 #define IS_FDCAN_FRAME_TYPE(TYPE) (((TYPE) == FDCAN_DATA_FRAME ) || \ 1353 ((TYPE) == FDCAN_REMOTE_FRAME)) 1354 #define IS_FDCAN_DLC(DLC) (((DLC) == FDCAN_DLC_BYTES_0 ) || \ 1355 ((DLC) == FDCAN_DLC_BYTES_1 ) || \ 1356 ((DLC) == FDCAN_DLC_BYTES_2 ) || \ 1357 ((DLC) == FDCAN_DLC_BYTES_3 ) || \ 1358 ((DLC) == FDCAN_DLC_BYTES_4 ) || \ 1359 ((DLC) == FDCAN_DLC_BYTES_5 ) || \ 1360 ((DLC) == FDCAN_DLC_BYTES_6 ) || \ 1361 ((DLC) == FDCAN_DLC_BYTES_7 ) || \ 1362 ((DLC) == FDCAN_DLC_BYTES_8 ) || \ 1363 ((DLC) == FDCAN_DLC_BYTES_12) || \ 1364 ((DLC) == FDCAN_DLC_BYTES_16) || \ 1365 ((DLC) == FDCAN_DLC_BYTES_20) || \ 1366 ((DLC) == FDCAN_DLC_BYTES_24) || \ 1367 ((DLC) == FDCAN_DLC_BYTES_32) || \ 1368 ((DLC) == FDCAN_DLC_BYTES_48) || \ 1369 ((DLC) == FDCAN_DLC_BYTES_64)) 1370 #define IS_FDCAN_ESI(ESI) (((ESI) == FDCAN_ESI_ACTIVE ) || \ 1371 ((ESI) == FDCAN_ESI_PASSIVE)) 1372 #define IS_FDCAN_BRS(BRS) (((BRS) == FDCAN_BRS_OFF) || \ 1373 ((BRS) == FDCAN_BRS_ON )) 1374 #define IS_FDCAN_FDF(FDF) (((FDF) == FDCAN_CLASSIC_CAN) || \ 1375 ((FDF) == FDCAN_FD_CAN )) 1376 #define IS_FDCAN_EFC(EFC) (((EFC) == FDCAN_NO_TX_EVENTS ) || \ 1377 ((EFC) == FDCAN_STORE_TX_EVENTS)) 1378 #define IS_FDCAN_IT(IT) (((IT) & ~(FDCAN_IR_MASK)) == 0U) 1379 #define IS_FDCAN_IT_GROUP(IT_GROUP) (((IT_GROUP) & ~(FDCAN_ILS_MASK)) == 0U) 1380 #define IS_FDCAN_NON_MATCHING(DESTINATION) (((DESTINATION) == FDCAN_ACCEPT_IN_RX_FIFO0) || \ 1381 ((DESTINATION) == FDCAN_ACCEPT_IN_RX_FIFO1) || \ 1382 ((DESTINATION) == FDCAN_REJECT )) 1383 #define IS_FDCAN_REJECT_REMOTE(DESTINATION) (((DESTINATION) == FDCAN_FILTER_REMOTE) || \ 1384 ((DESTINATION) == FDCAN_REJECT_REMOTE)) 1385 #define IS_FDCAN_IT_LINE(IT_LINE) (((IT_LINE) == FDCAN_INTERRUPT_LINE0) || \ 1386 ((IT_LINE) == FDCAN_INTERRUPT_LINE1)) 1387 #define IS_FDCAN_TIMESTAMP(OPERATION) (((OPERATION) == FDCAN_TIMESTAMP_INTERNAL) || \ 1388 ((OPERATION) == FDCAN_TIMESTAMP_EXTERNAL)) 1389 #define IS_FDCAN_TIMESTAMP_PRESCALER(PRESCALER) (((PRESCALER) == FDCAN_TIMESTAMP_PRESC_1 ) || \ 1390 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_2 ) || \ 1391 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_3 ) || \ 1392 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_4 ) || \ 1393 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_5 ) || \ 1394 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_6 ) || \ 1395 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_7 ) || \ 1396 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_8 ) || \ 1397 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_9 ) || \ 1398 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_10) || \ 1399 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_11) || \ 1400 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_12) || \ 1401 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_13) || \ 1402 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_14) || \ 1403 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_15) || \ 1404 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_16)) 1405 #define IS_FDCAN_TIMEOUT(OPERATION) (((OPERATION) == FDCAN_TIMEOUT_CONTINUOUS ) || \ 1406 ((OPERATION) == FDCAN_TIMEOUT_TX_EVENT_FIFO) || \ 1407 ((OPERATION) == FDCAN_TIMEOUT_RX_FIFO0 ) || \ 1408 ((OPERATION) == FDCAN_TIMEOUT_RX_FIFO1 )) 1409 /** 1410 * @} 1411 */ 1412 1413 /* Private functions prototypes ----------------------------------------------*/ 1414 /* Private functions ---------------------------------------------------------*/ 1415 1416 /** 1417 * @} 1418 */ 1419 1420 /** 1421 * @} 1422 */ 1423 #endif /* FDCAN1 */ 1424 1425 #ifdef __cplusplus 1426 } 1427 #endif 1428 1429 #endif /* STM32G4xx_HAL_FDCAN_H */ 1430
