1 /**
2 ******************************************************************************
3 * @file stm32f4xx_ll_rcc.c
4 * @author MCD Application Team
5 * @brief RCC LL module driver.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file in
13 * the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 ******************************************************************************
16 */
17 #if defined(USE_FULL_LL_DRIVER)
18
19 /* Includes ------------------------------------------------------------------*/
20 #include "stm32f4xx_ll_rcc.h"
21 #ifdef USE_FULL_ASSERT
22 #include "stm32_assert.h"
23 #else
24 #define assert_param(expr) ((void)0U)
25 #endif
26 /** @addtogroup STM32F4xx_LL_Driver
27 * @{
28 */
29
30 #if defined(RCC)
31
32 /** @addtogroup RCC_LL
33 * @{
34 */
35
36 /* Private types -------------------------------------------------------------*/
37 /* Private variables ---------------------------------------------------------*/
38 /* Private constants ---------------------------------------------------------*/
39 /* Private macros ------------------------------------------------------------*/
40 /** @addtogroup RCC_LL_Private_Macros
41 * @{
42 */
43 #if defined(FMPI2C1)
44 #define IS_LL_RCC_FMPI2C_CLKSOURCE(__VALUE__) ((__VALUE__) == LL_RCC_FMPI2C1_CLKSOURCE)
45 #endif /* FMPI2C1 */
46
47 #if defined(LPTIM1)
48 #define IS_LL_RCC_LPTIM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_LPTIM1_CLKSOURCE))
49 #endif /* LPTIM1 */
50
51 #if defined(SAI1)
52 #if defined(RCC_DCKCFGR_SAI1SRC)
53 #define IS_LL_RCC_SAI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SAI1_CLKSOURCE) \
54 || ((__VALUE__) == LL_RCC_SAI2_CLKSOURCE))
55 #elif defined(RCC_DCKCFGR_SAI1ASRC)
56 #define IS_LL_RCC_SAI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SAI1_A_CLKSOURCE) \
57 || ((__VALUE__) == LL_RCC_SAI1_B_CLKSOURCE))
58 #endif /* RCC_DCKCFGR_SAI1SRC */
59 #endif /* SAI1 */
60
61 #if defined(SDIO)
62 #define IS_LL_RCC_SDIO_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SDIO_CLKSOURCE))
63 #endif /* SDIO */
64
65 #if defined(RNG)
66 #define IS_LL_RCC_RNG_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_RNG_CLKSOURCE))
67 #endif /* RNG */
68
69 #if defined(USB_OTG_FS) || defined(USB_OTG_HS)
70 #define IS_LL_RCC_USB_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_USB_CLKSOURCE))
71 #endif /* USB_OTG_FS || USB_OTG_HS */
72
73 #if defined(DFSDM2_Channel0)
74 #define IS_LL_RCC_DFSDM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_DFSDM1_CLKSOURCE))
75
76 #define IS_LL_RCC_DFSDM_AUDIO_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_DFSDM1_AUDIO_CLKSOURCE) \
77 || ((__VALUE__) == LL_RCC_DFSDM2_AUDIO_CLKSOURCE))
78 #elif defined(DFSDM1_Channel0)
79 #define IS_LL_RCC_DFSDM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_DFSDM1_CLKSOURCE))
80
81 #define IS_LL_RCC_DFSDM_AUDIO_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_DFSDM1_AUDIO_CLKSOURCE))
82 #endif /* DFSDM2_Channel0 */
83
84 #if defined(RCC_DCKCFGR_I2S2SRC)
85 #define IS_LL_RCC_I2S_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2S1_CLKSOURCE) \
86 || ((__VALUE__) == LL_RCC_I2S2_CLKSOURCE))
87 #else
88 #define IS_LL_RCC_I2S_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_I2S1_CLKSOURCE))
89 #endif /* RCC_DCKCFGR_I2S2SRC */
90
91 #if defined(CEC)
92 #define IS_LL_RCC_CEC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_CEC_CLKSOURCE))
93 #endif /* CEC */
94
95 #if defined(DSI)
96 #define IS_LL_RCC_DSI_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_DSI_CLKSOURCE))
97 #endif /* DSI */
98
99 #if defined(LTDC)
100 #define IS_LL_RCC_LTDC_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_LTDC_CLKSOURCE))
101 #endif /* LTDC */
102
103 #if defined(SPDIFRX)
104 #define IS_LL_RCC_SPDIFRX_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_SPDIFRX1_CLKSOURCE))
105 #endif /* SPDIFRX */
106 /**
107 * @}
108 */
109
110 /* Private function prototypes -----------------------------------------------*/
111 /** @defgroup RCC_LL_Private_Functions RCC Private functions
112 * @{
113 */
114 uint32_t RCC_GetSystemClockFreq(void);
115 uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency);
116 uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency);
117 uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency);
118 uint32_t RCC_PLL_GetFreqDomain_SYS(uint32_t SYSCLK_Source);
119 uint32_t RCC_PLL_GetFreqDomain_48M(void);
120 #if defined(RCC_DCKCFGR_I2SSRC) || defined(RCC_DCKCFGR_I2S1SRC)
121 uint32_t RCC_PLL_GetFreqDomain_I2S(void);
122 #endif /* RCC_DCKCFGR_I2SSRC || RCC_DCKCFGR_I2S1SRC */
123 #if defined(SPDIFRX)
124 uint32_t RCC_PLL_GetFreqDomain_SPDIFRX(void);
125 #endif /* SPDIFRX */
126 #if defined(RCC_PLLCFGR_PLLR)
127 #if defined(SAI1)
128 uint32_t RCC_PLL_GetFreqDomain_SAI(void);
129 #endif /* SAI1 */
130 #endif /* RCC_PLLCFGR_PLLR */
131 #if defined(DSI)
132 uint32_t RCC_PLL_GetFreqDomain_DSI(void);
133 #endif /* DSI */
134 #if defined(RCC_PLLSAI_SUPPORT)
135 uint32_t RCC_PLLSAI_GetFreqDomain_SAI(void);
136 #if defined(RCC_PLLSAICFGR_PLLSAIP)
137 uint32_t RCC_PLLSAI_GetFreqDomain_48M(void);
138 #endif /* RCC_PLLSAICFGR_PLLSAIP */
139 #if defined(LTDC)
140 uint32_t RCC_PLLSAI_GetFreqDomain_LTDC(void);
141 #endif /* LTDC */
142 #endif /* RCC_PLLSAI_SUPPORT */
143 #if defined(RCC_PLLI2S_SUPPORT)
144 uint32_t RCC_PLLI2S_GetFreqDomain_I2S(void);
145 #if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ)
146 uint32_t RCC_PLLI2S_GetFreqDomain_48M(void);
147 #endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */
148 #if defined(SAI1)
149 uint32_t RCC_PLLI2S_GetFreqDomain_SAI(void);
150 #endif /* SAI1 */
151 #if defined(SPDIFRX)
152 uint32_t RCC_PLLI2S_GetFreqDomain_SPDIFRX(void);
153 #endif /* SPDIFRX */
154 #endif /* RCC_PLLI2S_SUPPORT */
155 /**
156 * @}
157 */
158
159
160 /* Exported functions --------------------------------------------------------*/
161 /** @addtogroup RCC_LL_Exported_Functions
162 * @{
163 */
164
165 /** @addtogroup RCC_LL_EF_Init
166 * @{
167 */
168
169 /**
170 * @brief Reset the RCC clock configuration to the default reset state.
171 * @note The default reset state of the clock configuration is given below:
172 * - HSI ON and used as system clock source
173 * - HSE and PLL OFF
174 * - AHB, APB1 and APB2 prescaler set to 1.
175 * - CSS, MCO OFF
176 * - All interrupts disabled
177 * @note This function doesn't modify the configuration of the
178 * - Peripheral clocks
179 * - LSI, LSE and RTC clocks
180 * @retval An ErrorStatus enumeration value:
181 * - SUCCESS: RCC registers are de-initialized
182 * - ERROR: not applicable
183 */
LL_RCC_DeInit(void)184 ErrorStatus LL_RCC_DeInit(void)
185 {
186 __IO uint32_t vl_mask;
187
188 /* Set HSION bit */
189 LL_RCC_HSI_Enable();
190
191 /* Wait for HSI READY bit */
192 while(LL_RCC_HSI_IsReady() != 1U)
193 {}
194
195 /* Reset CFGR register */
196 LL_RCC_WriteReg(CFGR, 0x00000000U);
197
198 /* Read CR register */
199 vl_mask = LL_RCC_ReadReg(CR);
200
201 /* Reset HSEON, HSEBYP, PLLON, CSSON bits */
202 CLEAR_BIT(vl_mask,
203 (RCC_CR_HSEON | RCC_CR_HSEBYP | RCC_CR_PLLON | RCC_CR_CSSON));
204
205 #if defined(RCC_PLLSAI_SUPPORT)
206 /* Reset PLLSAION bit */
207 CLEAR_BIT(vl_mask, RCC_CR_PLLSAION);
208 #endif /* RCC_PLLSAI_SUPPORT */
209
210 #if defined(RCC_PLLI2S_SUPPORT)
211 /* Reset PLLI2SON bit */
212 CLEAR_BIT(vl_mask, RCC_CR_PLLI2SON);
213 #endif /* RCC_PLLI2S_SUPPORT */
214
215 /* Write new value in CR register */
216 LL_RCC_WriteReg(CR, vl_mask);
217
218 /* Set HSITRIM bits to the reset value*/
219 LL_RCC_HSI_SetCalibTrimming(0x10U);
220
221 /* Wait for PLL READY bit to be reset */
222 while(LL_RCC_PLL_IsReady() != 0U)
223 {}
224
225 /* Reset PLLCFGR register */
226 LL_RCC_WriteReg(PLLCFGR, RCC_PLLCFGR_RST_VALUE);
227
228 #if defined(RCC_PLLI2S_SUPPORT)
229 /* Reset PLLI2SCFGR register */
230 LL_RCC_WriteReg(PLLI2SCFGR, RCC_PLLI2SCFGR_RST_VALUE);
231 #endif /* RCC_PLLI2S_SUPPORT */
232
233 #if defined(RCC_PLLSAI_SUPPORT)
234 /* Reset PLLSAICFGR register */
235 LL_RCC_WriteReg(PLLSAICFGR, RCC_PLLSAICFGR_RST_VALUE);
236 #endif /* RCC_PLLSAI_SUPPORT */
237
238 /* Disable all interrupts */
239 CLEAR_BIT(RCC->CIR, RCC_CIR_LSIRDYIE | RCC_CIR_LSERDYIE | RCC_CIR_HSIRDYIE | RCC_CIR_HSERDYIE | RCC_CIR_PLLRDYIE);
240
241 #if defined(RCC_CIR_PLLI2SRDYIE)
242 CLEAR_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYIE);
243 #endif /* RCC_CIR_PLLI2SRDYIE */
244
245 #if defined(RCC_CIR_PLLSAIRDYIE)
246 CLEAR_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYIE);
247 #endif /* RCC_CIR_PLLSAIRDYIE */
248
249 /* Clear all interrupt flags */
250 SET_BIT(RCC->CIR, RCC_CIR_LSIRDYC | RCC_CIR_LSERDYC | RCC_CIR_HSIRDYC | RCC_CIR_HSERDYC | RCC_CIR_PLLRDYC | RCC_CIR_CSSC);
251
252 #if defined(RCC_CIR_PLLI2SRDYC)
253 SET_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYC);
254 #endif /* RCC_CIR_PLLI2SRDYC */
255
256 #if defined(RCC_CIR_PLLSAIRDYC)
257 SET_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYC);
258 #endif /* RCC_CIR_PLLSAIRDYC */
259
260 /* Clear LSION bit */
261 CLEAR_BIT(RCC->CSR, RCC_CSR_LSION);
262
263 /* Reset all CSR flags */
264 SET_BIT(RCC->CSR, RCC_CSR_RMVF);
265
266 return SUCCESS;
267 }
268
269 /**
270 * @}
271 */
272
273 /** @addtogroup RCC_LL_EF_Get_Freq
274 * @brief Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks
275 * and different peripheral clocks available on the device.
276 * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(**)
277 * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(***)
278 * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(***)
279 * or HSI_VALUE(**) multiplied/divided by the PLL factors.
280 * @note (**) HSI_VALUE is a constant defined in this file (default value
281 * 16 MHz) but the real value may vary depending on the variations
282 * in voltage and temperature.
283 * @note (***) HSE_VALUE is a constant defined in this file (default value
284 * 25 MHz), user has to ensure that HSE_VALUE is same as the real
285 * frequency of the crystal used. Otherwise, this function may
286 * have wrong result.
287 * @note The result of this function could be incorrect when using fractional
288 * value for HSE crystal.
289 * @note This function can be used by the user application to compute the
290 * baud-rate for the communication peripherals or configure other parameters.
291 * @{
292 */
293
294 /**
295 * @brief Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks
296 * @note Each time SYSCLK, HCLK, PCLK1 and/or PCLK2 clock changes, this function
297 * must be called to update structure fields. Otherwise, any
298 * configuration based on this function will be incorrect.
299 * @param RCC_Clocks pointer to a @ref LL_RCC_ClocksTypeDef structure which will hold the clocks frequencies
300 * @retval None
301 */
LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef * RCC_Clocks)302 void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks)
303 {
304 /* Get SYSCLK frequency */
305 RCC_Clocks->SYSCLK_Frequency = RCC_GetSystemClockFreq();
306
307 /* HCLK clock frequency */
308 RCC_Clocks->HCLK_Frequency = RCC_GetHCLKClockFreq(RCC_Clocks->SYSCLK_Frequency);
309
310 /* PCLK1 clock frequency */
311 RCC_Clocks->PCLK1_Frequency = RCC_GetPCLK1ClockFreq(RCC_Clocks->HCLK_Frequency);
312
313 /* PCLK2 clock frequency */
314 RCC_Clocks->PCLK2_Frequency = RCC_GetPCLK2ClockFreq(RCC_Clocks->HCLK_Frequency);
315 }
316
317 #if defined(FMPI2C1)
318 /**
319 * @brief Return FMPI2Cx clock frequency
320 * @param FMPI2CxSource This parameter can be one of the following values:
321 * @arg @ref LL_RCC_FMPI2C1_CLKSOURCE
322 * @retval FMPI2C clock frequency (in Hz)
323 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that HSI oscillator is not ready
324 */
LL_RCC_GetFMPI2CClockFreq(uint32_t FMPI2CxSource)325 uint32_t LL_RCC_GetFMPI2CClockFreq(uint32_t FMPI2CxSource)
326 {
327 uint32_t FMPI2C_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
328
329 /* Check parameter */
330 assert_param(IS_LL_RCC_FMPI2C_CLKSOURCE(FMPI2CxSource));
331
332 if (FMPI2CxSource == LL_RCC_FMPI2C1_CLKSOURCE)
333 {
334 /* FMPI2C1 CLK clock frequency */
335 switch (LL_RCC_GetFMPI2CClockSource(FMPI2CxSource))
336 {
337 case LL_RCC_FMPI2C1_CLKSOURCE_SYSCLK: /* FMPI2C1 Clock is System Clock */
338 FMPI2C_frequency = RCC_GetSystemClockFreq();
339 break;
340
341 case LL_RCC_FMPI2C1_CLKSOURCE_HSI: /* FMPI2C1 Clock is HSI Osc. */
342 if (LL_RCC_HSI_IsReady())
343 {
344 FMPI2C_frequency = HSI_VALUE;
345 }
346 break;
347
348 case LL_RCC_FMPI2C1_CLKSOURCE_PCLK1: /* FMPI2C1 Clock is PCLK1 */
349 default:
350 FMPI2C_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
351 break;
352 }
353 }
354
355 return FMPI2C_frequency;
356 }
357 #endif /* FMPI2C1 */
358
359 /**
360 * @brief Return I2Sx clock frequency
361 * @param I2SxSource This parameter can be one of the following values:
362 * @arg @ref LL_RCC_I2S1_CLKSOURCE
363 * @arg @ref LL_RCC_I2S2_CLKSOURCE (*)
364 *
365 * (*) value not defined in all devices.
366 * @retval I2S clock frequency (in Hz)
367 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
368 */
LL_RCC_GetI2SClockFreq(uint32_t I2SxSource)369 uint32_t LL_RCC_GetI2SClockFreq(uint32_t I2SxSource)
370 {
371 uint32_t i2s_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
372
373 /* Check parameter */
374 assert_param(IS_LL_RCC_I2S_CLKSOURCE(I2SxSource));
375
376 if (I2SxSource == LL_RCC_I2S1_CLKSOURCE)
377 {
378 /* I2S1 CLK clock frequency */
379 switch (LL_RCC_GetI2SClockSource(I2SxSource))
380 {
381 #if defined(RCC_PLLI2S_SUPPORT)
382 case LL_RCC_I2S1_CLKSOURCE_PLLI2S: /* I2S1 Clock is PLLI2S */
383 if (LL_RCC_PLLI2S_IsReady())
384 {
385 i2s_frequency = RCC_PLLI2S_GetFreqDomain_I2S();
386 }
387 break;
388 #endif /* RCC_PLLI2S_SUPPORT */
389
390 #if defined(RCC_DCKCFGR_I2SSRC) || defined(RCC_DCKCFGR_I2S1SRC)
391 case LL_RCC_I2S1_CLKSOURCE_PLL: /* I2S1 Clock is PLL */
392 if (LL_RCC_PLL_IsReady())
393 {
394 i2s_frequency = RCC_PLL_GetFreqDomain_I2S();
395 }
396 break;
397
398 case LL_RCC_I2S1_CLKSOURCE_PLLSRC: /* I2S1 Clock is PLL Main source */
399 switch (LL_RCC_PLL_GetMainSource())
400 {
401 case LL_RCC_PLLSOURCE_HSE: /* I2S1 Clock is HSE Osc. */
402 if (LL_RCC_HSE_IsReady())
403 {
404 i2s_frequency = HSE_VALUE;
405 }
406 break;
407
408 case LL_RCC_PLLSOURCE_HSI: /* I2S1 Clock is HSI Osc. */
409 default:
410 if (LL_RCC_HSI_IsReady())
411 {
412 i2s_frequency = HSI_VALUE;
413 }
414 break;
415 }
416 break;
417 #endif /* RCC_DCKCFGR_I2SSRC || RCC_DCKCFGR_I2S1SRC */
418
419 case LL_RCC_I2S1_CLKSOURCE_PIN: /* I2S1 Clock is External clock */
420 default:
421 i2s_frequency = EXTERNAL_CLOCK_VALUE;
422 break;
423 }
424 }
425 #if defined(RCC_DCKCFGR_I2S2SRC)
426 else
427 {
428 /* I2S2 CLK clock frequency */
429 switch (LL_RCC_GetI2SClockSource(I2SxSource))
430 {
431 case LL_RCC_I2S2_CLKSOURCE_PLLI2S: /* I2S2 Clock is PLLI2S */
432 if (LL_RCC_PLLI2S_IsReady())
433 {
434 i2s_frequency = RCC_PLLI2S_GetFreqDomain_I2S();
435 }
436 break;
437
438 case LL_RCC_I2S2_CLKSOURCE_PLL: /* I2S2 Clock is PLL */
439 if (LL_RCC_PLL_IsReady())
440 {
441 i2s_frequency = RCC_PLL_GetFreqDomain_I2S();
442 }
443 break;
444
445 case LL_RCC_I2S2_CLKSOURCE_PLLSRC: /* I2S2 Clock is PLL Main source */
446 switch (LL_RCC_PLL_GetMainSource())
447 {
448 case LL_RCC_PLLSOURCE_HSE: /* I2S2 Clock is HSE Osc. */
449 if (LL_RCC_HSE_IsReady())
450 {
451 i2s_frequency = HSE_VALUE;
452 }
453 break;
454
455 case LL_RCC_PLLSOURCE_HSI: /* I2S2 Clock is HSI Osc. */
456 default:
457 if (LL_RCC_HSI_IsReady())
458 {
459 i2s_frequency = HSI_VALUE;
460 }
461 break;
462 }
463 break;
464
465 case LL_RCC_I2S2_CLKSOURCE_PIN: /* I2S2 Clock is External clock */
466 default:
467 i2s_frequency = EXTERNAL_CLOCK_VALUE;
468 break;
469 }
470 }
471 #endif /* RCC_DCKCFGR_I2S2SRC */
472
473 return i2s_frequency;
474 }
475
476 #if defined(LPTIM1)
477 /**
478 * @brief Return LPTIMx clock frequency
479 * @param LPTIMxSource This parameter can be one of the following values:
480 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE
481 * @retval LPTIM clock frequency (in Hz)
482 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI, LSI or LSE) is not ready
483 */
LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource)484 uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource)
485 {
486 uint32_t lptim_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
487
488 /* Check parameter */
489 assert_param(IS_LL_RCC_LPTIM_CLKSOURCE(LPTIMxSource));
490
491 if (LPTIMxSource == LL_RCC_LPTIM1_CLKSOURCE)
492 {
493 /* LPTIM1CLK clock frequency */
494 switch (LL_RCC_GetLPTIMClockSource(LPTIMxSource))
495 {
496 case LL_RCC_LPTIM1_CLKSOURCE_LSI: /* LPTIM1 Clock is LSI Osc. */
497 if (LL_RCC_LSI_IsReady())
498 {
499 lptim_frequency = LSI_VALUE;
500 }
501 break;
502
503 case LL_RCC_LPTIM1_CLKSOURCE_HSI: /* LPTIM1 Clock is HSI Osc. */
504 if (LL_RCC_HSI_IsReady())
505 {
506 lptim_frequency = HSI_VALUE;
507 }
508 break;
509
510 case LL_RCC_LPTIM1_CLKSOURCE_LSE: /* LPTIM1 Clock is LSE Osc. */
511 if (LL_RCC_LSE_IsReady())
512 {
513 lptim_frequency = LSE_VALUE;
514 }
515 break;
516
517 case LL_RCC_LPTIM1_CLKSOURCE_PCLK1: /* LPTIM1 Clock is PCLK1 */
518 default:
519 lptim_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
520 break;
521 }
522 }
523
524 return lptim_frequency;
525 }
526 #endif /* LPTIM1 */
527
528 #if defined(SAI1)
529 /**
530 * @brief Return SAIx clock frequency
531 * @param SAIxSource This parameter can be one of the following values:
532 * @arg @ref LL_RCC_SAI1_CLKSOURCE (*)
533 * @arg @ref LL_RCC_SAI2_CLKSOURCE (*)
534 * @arg @ref LL_RCC_SAI1_A_CLKSOURCE (*)
535 * @arg @ref LL_RCC_SAI1_B_CLKSOURCE (*)
536 *
537 * (*) value not defined in all devices.
538 * @retval SAI clock frequency (in Hz)
539 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
540 */
LL_RCC_GetSAIClockFreq(uint32_t SAIxSource)541 uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource)
542 {
543 uint32_t sai_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
544
545 /* Check parameter */
546 assert_param(IS_LL_RCC_SAI_CLKSOURCE(SAIxSource));
547
548 #if defined(RCC_DCKCFGR_SAI1SRC)
549 if ((SAIxSource == LL_RCC_SAI1_CLKSOURCE) || (SAIxSource == LL_RCC_SAI2_CLKSOURCE))
550 {
551 /* SAI1CLK clock frequency */
552 switch (LL_RCC_GetSAIClockSource(SAIxSource))
553 {
554 case LL_RCC_SAI1_CLKSOURCE_PLLSAI: /* PLLSAI clock used as SAI1 clock source */
555 case LL_RCC_SAI2_CLKSOURCE_PLLSAI: /* PLLSAI clock used as SAI2 clock source */
556 if (LL_RCC_PLLSAI_IsReady())
557 {
558 sai_frequency = RCC_PLLSAI_GetFreqDomain_SAI();
559 }
560 break;
561
562 case LL_RCC_SAI1_CLKSOURCE_PLLI2S: /* PLLI2S clock used as SAI1 clock source */
563 case LL_RCC_SAI2_CLKSOURCE_PLLI2S: /* PLLI2S clock used as SAI2 clock source */
564 if (LL_RCC_PLLI2S_IsReady())
565 {
566 sai_frequency = RCC_PLLI2S_GetFreqDomain_SAI();
567 }
568 break;
569
570 case LL_RCC_SAI1_CLKSOURCE_PLL: /* PLL clock used as SAI1 clock source */
571 case LL_RCC_SAI2_CLKSOURCE_PLL: /* PLL clock used as SAI2 clock source */
572 if (LL_RCC_PLL_IsReady())
573 {
574 sai_frequency = RCC_PLL_GetFreqDomain_SAI();
575 }
576 break;
577
578 case LL_RCC_SAI2_CLKSOURCE_PLLSRC:
579 switch (LL_RCC_PLL_GetMainSource())
580 {
581 case LL_RCC_PLLSOURCE_HSE: /* HSE clock used as SAI2 clock source */
582 if (LL_RCC_HSE_IsReady())
583 {
584 sai_frequency = HSE_VALUE;
585 }
586 break;
587
588 case LL_RCC_PLLSOURCE_HSI: /* HSI clock used as SAI2 clock source */
589 default:
590 if (LL_RCC_HSI_IsReady())
591 {
592 sai_frequency = HSI_VALUE;
593 }
594 break;
595 }
596 break;
597
598 case LL_RCC_SAI1_CLKSOURCE_PIN: /* External input clock used as SAI1 clock source */
599 default:
600 sai_frequency = EXTERNAL_CLOCK_VALUE;
601 break;
602 }
603 }
604 #endif /* RCC_DCKCFGR_SAI1SRC */
605 #if defined(RCC_DCKCFGR_SAI1ASRC)
606 if ((SAIxSource == LL_RCC_SAI1_A_CLKSOURCE) || (SAIxSource == LL_RCC_SAI1_B_CLKSOURCE))
607 {
608 /* SAI1CLK clock frequency */
609 switch (LL_RCC_GetSAIClockSource(SAIxSource))
610 {
611 #if defined(RCC_PLLSAI_SUPPORT)
612 case LL_RCC_SAI1_A_CLKSOURCE_PLLSAI: /* PLLSAI clock used as SAI1 Block A clock source */
613 case LL_RCC_SAI1_B_CLKSOURCE_PLLSAI: /* PLLSAI clock used as SAI1 Block B clock source */
614 if (LL_RCC_PLLSAI_IsReady())
615 {
616 sai_frequency = RCC_PLLSAI_GetFreqDomain_SAI();
617 }
618 break;
619 #endif /* RCC_PLLSAI_SUPPORT */
620
621 case LL_RCC_SAI1_A_CLKSOURCE_PLLI2S: /* PLLI2S clock used as SAI1 Block A clock source */
622 case LL_RCC_SAI1_B_CLKSOURCE_PLLI2S: /* PLLI2S clock used as SAI1 Block B clock source */
623 if (LL_RCC_PLLI2S_IsReady())
624 {
625 sai_frequency = RCC_PLLI2S_GetFreqDomain_SAI();
626 }
627 break;
628
629 #if defined(RCC_SAI1A_PLLSOURCE_SUPPORT)
630 case LL_RCC_SAI1_A_CLKSOURCE_PLL: /* PLL clock used as SAI1 Block A clock source */
631 case LL_RCC_SAI1_B_CLKSOURCE_PLL: /* PLL clock used as SAI1 Block B clock source */
632 if (LL_RCC_PLL_IsReady())
633 {
634 sai_frequency = RCC_PLL_GetFreqDomain_SAI();
635 }
636 break;
637
638 case LL_RCC_SAI1_A_CLKSOURCE_PLLSRC:
639 case LL_RCC_SAI1_B_CLKSOURCE_PLLSRC:
640 switch (LL_RCC_PLL_GetMainSource())
641 {
642 case LL_RCC_PLLSOURCE_HSE: /* HSE clock used as SAI1 Block A or B clock source */
643 if (LL_RCC_HSE_IsReady())
644 {
645 sai_frequency = HSE_VALUE;
646 }
647 break;
648
649 case LL_RCC_PLLSOURCE_HSI: /* HSI clock used as SAI1 Block A or B clock source */
650 default:
651 if (LL_RCC_HSI_IsReady())
652 {
653 sai_frequency = HSI_VALUE;
654 }
655 break;
656 }
657 break;
658 #endif /* RCC_SAI1A_PLLSOURCE_SUPPORT */
659
660 case LL_RCC_SAI1_A_CLKSOURCE_PIN: /* External input clock used as SAI1 Block A clock source */
661 case LL_RCC_SAI1_B_CLKSOURCE_PIN: /* External input clock used as SAI1 Block B clock source */
662 default:
663 sai_frequency = EXTERNAL_CLOCK_VALUE;
664 break;
665 }
666 }
667 #endif /* RCC_DCKCFGR_SAI1ASRC */
668
669 return sai_frequency;
670 }
671 #endif /* SAI1 */
672
673 #if defined(SDIO)
674 /**
675 * @brief Return SDIOx clock frequency
676 * @param SDIOxSource This parameter can be one of the following values:
677 * @arg @ref LL_RCC_SDIO_CLKSOURCE
678 * @retval SDIO clock frequency (in Hz)
679 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
680 */
LL_RCC_GetSDIOClockFreq(uint32_t SDIOxSource)681 uint32_t LL_RCC_GetSDIOClockFreq(uint32_t SDIOxSource)
682 {
683 uint32_t SDIO_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
684
685 /* Check parameter */
686 assert_param(IS_LL_RCC_SDIO_CLKSOURCE(SDIOxSource));
687
688 if (SDIOxSource == LL_RCC_SDIO_CLKSOURCE)
689 {
690 #if defined(RCC_DCKCFGR_SDIOSEL) || defined(RCC_DCKCFGR2_SDIOSEL)
691 /* SDIOCLK clock frequency */
692 switch (LL_RCC_GetSDIOClockSource(SDIOxSource))
693 {
694 case LL_RCC_SDIO_CLKSOURCE_PLL48CLK: /* PLL48M clock used as SDIO clock source */
695 switch (LL_RCC_GetCK48MClockSource(LL_RCC_CK48M_CLKSOURCE))
696 {
697 case LL_RCC_CK48M_CLKSOURCE_PLL: /* PLL clock used as 48Mhz domain clock */
698 if (LL_RCC_PLL_IsReady())
699 {
700 SDIO_frequency = RCC_PLL_GetFreqDomain_48M();
701 }
702 break;
703
704 #if defined(RCC_PLLSAI_SUPPORT)
705 case LL_RCC_CK48M_CLKSOURCE_PLLSAI: /* PLLSAI clock used as 48Mhz domain clock */
706 default:
707 if (LL_RCC_PLLSAI_IsReady())
708 {
709 SDIO_frequency = RCC_PLLSAI_GetFreqDomain_48M();
710 }
711 break;
712 #endif /* RCC_PLLSAI_SUPPORT */
713
714 #if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ)
715 case LL_RCC_CK48M_CLKSOURCE_PLLI2S: /* PLLI2S clock used as 48Mhz domain clock */
716 default:
717 if (LL_RCC_PLLI2S_IsReady())
718 {
719 SDIO_frequency = RCC_PLLI2S_GetFreqDomain_48M();
720 }
721 break;
722 #endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */
723 }
724 break;
725
726 case LL_RCC_SDIO_CLKSOURCE_SYSCLK: /* PLL clock used as SDIO clock source */
727 default:
728 SDIO_frequency = RCC_GetSystemClockFreq();
729 break;
730 }
731 #else
732 /* PLL clock used as 48Mhz domain clock */
733 if (LL_RCC_PLL_IsReady())
734 {
735 SDIO_frequency = RCC_PLL_GetFreqDomain_48M();
736 }
737 #endif /* RCC_DCKCFGR_SDIOSEL || RCC_DCKCFGR2_SDIOSEL */
738 }
739
740 return SDIO_frequency;
741 }
742 #endif /* SDIO */
743
744 #if defined(RNG)
745 /**
746 * @brief Return RNGx clock frequency
747 * @param RNGxSource This parameter can be one of the following values:
748 * @arg @ref LL_RCC_RNG_CLKSOURCE
749 * @retval RNG clock frequency (in Hz)
750 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
751 */
LL_RCC_GetRNGClockFreq(uint32_t RNGxSource)752 uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource)
753 {
754 uint32_t rng_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
755
756 /* Check parameter */
757 assert_param(IS_LL_RCC_RNG_CLKSOURCE(RNGxSource));
758
759 #if defined(RCC_DCKCFGR_CK48MSEL) || defined(RCC_DCKCFGR2_CK48MSEL)
760 /* RNGCLK clock frequency */
761 switch (LL_RCC_GetRNGClockSource(RNGxSource))
762 {
763 #if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ)
764 case LL_RCC_RNG_CLKSOURCE_PLLI2S: /* PLLI2S clock used as RNG clock source */
765 if (LL_RCC_PLLI2S_IsReady())
766 {
767 rng_frequency = RCC_PLLI2S_GetFreqDomain_48M();
768 }
769 break;
770 #endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */
771
772 #if defined(RCC_PLLSAI_SUPPORT)
773 case LL_RCC_RNG_CLKSOURCE_PLLSAI: /* PLLSAI clock used as RNG clock source */
774 if (LL_RCC_PLLSAI_IsReady())
775 {
776 rng_frequency = RCC_PLLSAI_GetFreqDomain_48M();
777 }
778 break;
779 #endif /* RCC_PLLSAI_SUPPORT */
780
781 case LL_RCC_RNG_CLKSOURCE_PLL: /* PLL clock used as RNG clock source */
782 default:
783 if (LL_RCC_PLL_IsReady())
784 {
785 rng_frequency = RCC_PLL_GetFreqDomain_48M();
786 }
787 break;
788 }
789 #else
790 /* PLL clock used as RNG clock source */
791 if (LL_RCC_PLL_IsReady())
792 {
793 rng_frequency = RCC_PLL_GetFreqDomain_48M();
794 }
795 #endif /* RCC_DCKCFGR_CK48MSEL || RCC_DCKCFGR2_CK48MSEL */
796
797 return rng_frequency;
798 }
799 #endif /* RNG */
800
801 #if defined(CEC)
802 /**
803 * @brief Return CEC clock frequency
804 * @param CECxSource This parameter can be one of the following values:
805 * @arg @ref LL_RCC_CEC_CLKSOURCE
806 * @retval CEC clock frequency (in Hz)
807 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSI or LSE) is not ready
808 */
LL_RCC_GetCECClockFreq(uint32_t CECxSource)809 uint32_t LL_RCC_GetCECClockFreq(uint32_t CECxSource)
810 {
811 uint32_t cec_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
812
813 /* Check parameter */
814 assert_param(IS_LL_RCC_CEC_CLKSOURCE(CECxSource));
815
816 /* CECCLK clock frequency */
817 switch (LL_RCC_GetCECClockSource(CECxSource))
818 {
819 case LL_RCC_CEC_CLKSOURCE_LSE: /* CEC Clock is LSE Osc. */
820 if (LL_RCC_LSE_IsReady())
821 {
822 cec_frequency = LSE_VALUE;
823 }
824 break;
825
826 case LL_RCC_CEC_CLKSOURCE_HSI_DIV488: /* CEC Clock is HSI Osc. */
827 default:
828 if (LL_RCC_HSI_IsReady())
829 {
830 cec_frequency = HSI_VALUE/488U;
831 }
832 break;
833 }
834
835 return cec_frequency;
836 }
837 #endif /* CEC */
838
839 #if defined(USB_OTG_FS) || defined(USB_OTG_HS)
840 /**
841 * @brief Return USBx clock frequency
842 * @param USBxSource This parameter can be one of the following values:
843 * @arg @ref LL_RCC_USB_CLKSOURCE
844 * @retval USB clock frequency (in Hz)
845 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
846 */
LL_RCC_GetUSBClockFreq(uint32_t USBxSource)847 uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource)
848 {
849 uint32_t usb_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
850
851 /* Check parameter */
852 assert_param(IS_LL_RCC_USB_CLKSOURCE(USBxSource));
853
854 #if defined(RCC_DCKCFGR_CK48MSEL) || defined(RCC_DCKCFGR2_CK48MSEL)
855 /* USBCLK clock frequency */
856 switch (LL_RCC_GetUSBClockSource(USBxSource))
857 {
858 #if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ)
859 case LL_RCC_USB_CLKSOURCE_PLLI2S: /* PLLI2S clock used as USB clock source */
860 if (LL_RCC_PLLI2S_IsReady())
861 {
862 usb_frequency = RCC_PLLI2S_GetFreqDomain_48M();
863 }
864 break;
865
866 #endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */
867
868 #if defined(RCC_PLLSAI_SUPPORT)
869 case LL_RCC_USB_CLKSOURCE_PLLSAI: /* PLLSAI clock used as USB clock source */
870 if (LL_RCC_PLLSAI_IsReady())
871 {
872 usb_frequency = RCC_PLLSAI_GetFreqDomain_48M();
873 }
874 break;
875 #endif /* RCC_PLLSAI_SUPPORT */
876
877 case LL_RCC_USB_CLKSOURCE_PLL: /* PLL clock used as USB clock source */
878 default:
879 if (LL_RCC_PLL_IsReady())
880 {
881 usb_frequency = RCC_PLL_GetFreqDomain_48M();
882 }
883 break;
884 }
885 #else
886 /* PLL clock used as USB clock source */
887 if (LL_RCC_PLL_IsReady())
888 {
889 usb_frequency = RCC_PLL_GetFreqDomain_48M();
890 }
891 #endif /* RCC_DCKCFGR_CK48MSEL || RCC_DCKCFGR2_CK48MSEL */
892
893 return usb_frequency;
894 }
895 #endif /* USB_OTG_FS || USB_OTG_HS */
896
897 #if defined(DFSDM1_Channel0)
898 /**
899 * @brief Return DFSDMx clock frequency
900 * @param DFSDMxSource This parameter can be one of the following values:
901 * @arg @ref LL_RCC_DFSDM1_CLKSOURCE
902 * @arg @ref LL_RCC_DFSDM2_CLKSOURCE (*)
903 *
904 * (*) value not defined in all devices.
905 * @retval DFSDM clock frequency (in Hz)
906 */
LL_RCC_GetDFSDMClockFreq(uint32_t DFSDMxSource)907 uint32_t LL_RCC_GetDFSDMClockFreq(uint32_t DFSDMxSource)
908 {
909 uint32_t dfsdm_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
910
911 /* Check parameter */
912 assert_param(IS_LL_RCC_DFSDM_CLKSOURCE(DFSDMxSource));
913
914 if (DFSDMxSource == LL_RCC_DFSDM1_CLKSOURCE)
915 {
916 /* DFSDM1CLK clock frequency */
917 switch (LL_RCC_GetDFSDMClockSource(DFSDMxSource))
918 {
919 case LL_RCC_DFSDM1_CLKSOURCE_SYSCLK: /* DFSDM1 Clock is SYSCLK */
920 dfsdm_frequency = RCC_GetSystemClockFreq();
921 break;
922
923 case LL_RCC_DFSDM1_CLKSOURCE_PCLK2: /* DFSDM1 Clock is PCLK2 */
924 default:
925 dfsdm_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
926 break;
927 }
928 }
929 #if defined(DFSDM2_Channel0)
930 else
931 {
932 /* DFSDM2CLK clock frequency */
933 switch (LL_RCC_GetDFSDMClockSource(DFSDMxSource))
934 {
935 case LL_RCC_DFSDM2_CLKSOURCE_SYSCLK: /* DFSDM2 Clock is SYSCLK */
936 dfsdm_frequency = RCC_GetSystemClockFreq();
937 break;
938
939 case LL_RCC_DFSDM2_CLKSOURCE_PCLK2: /* DFSDM2 Clock is PCLK2 */
940 default:
941 dfsdm_frequency = RCC_GetPCLK2ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq()));
942 break;
943 }
944 }
945 #endif /* DFSDM2_Channel0 */
946
947 return dfsdm_frequency;
948 }
949
950 /**
951 * @brief Return DFSDMx Audio clock frequency
952 * @param DFSDMxSource This parameter can be one of the following values:
953 * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE
954 * @arg @ref LL_RCC_DFSDM2_AUDIO_CLKSOURCE (*)
955 *
956 * (*) value not defined in all devices.
957 * @retval DFSDM clock frequency (in Hz)
958 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
959 */
LL_RCC_GetDFSDMAudioClockFreq(uint32_t DFSDMxSource)960 uint32_t LL_RCC_GetDFSDMAudioClockFreq(uint32_t DFSDMxSource)
961 {
962 uint32_t dfsdm_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
963
964 /* Check parameter */
965 assert_param(IS_LL_RCC_DFSDM_AUDIO_CLKSOURCE(DFSDMxSource));
966
967 if (DFSDMxSource == LL_RCC_DFSDM1_AUDIO_CLKSOURCE)
968 {
969 /* DFSDM1CLK clock frequency */
970 switch (LL_RCC_GetDFSDMAudioClockSource(DFSDMxSource))
971 {
972 case LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S1: /* I2S1 clock used as DFSDM1 clock */
973 dfsdm_frequency = LL_RCC_GetI2SClockFreq(LL_RCC_I2S1_CLKSOURCE);
974 break;
975
976 case LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S2: /* I2S2 clock used as DFSDM1 clock */
977 default:
978 dfsdm_frequency = LL_RCC_GetI2SClockFreq(LL_RCC_I2S2_CLKSOURCE);
979 break;
980 }
981 }
982 #if defined(DFSDM2_Channel0)
983 else
984 {
985 /* DFSDM2CLK clock frequency */
986 switch (LL_RCC_GetDFSDMAudioClockSource(DFSDMxSource))
987 {
988 case LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S1: /* I2S1 clock used as DFSDM2 clock */
989 dfsdm_frequency = LL_RCC_GetI2SClockFreq(LL_RCC_I2S1_CLKSOURCE);
990 break;
991
992 case LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S2: /* I2S2 clock used as DFSDM2 clock */
993 default:
994 dfsdm_frequency = LL_RCC_GetI2SClockFreq(LL_RCC_I2S2_CLKSOURCE);
995 break;
996 }
997 }
998 #endif /* DFSDM2_Channel0 */
999
1000 return dfsdm_frequency;
1001 }
1002 #endif /* DFSDM1_Channel0 */
1003
1004 #if defined(DSI)
1005 /**
1006 * @brief Return DSI clock frequency
1007 * @param DSIxSource This parameter can be one of the following values:
1008 * @arg @ref LL_RCC_DSI_CLKSOURCE
1009 * @retval DSI clock frequency (in Hz)
1010 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
1011 * - @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that external clock is used
1012 */
LL_RCC_GetDSIClockFreq(uint32_t DSIxSource)1013 uint32_t LL_RCC_GetDSIClockFreq(uint32_t DSIxSource)
1014 {
1015 uint32_t dsi_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1016
1017 /* Check parameter */
1018 assert_param(IS_LL_RCC_DSI_CLKSOURCE(DSIxSource));
1019
1020 /* DSICLK clock frequency */
1021 switch (LL_RCC_GetDSIClockSource(DSIxSource))
1022 {
1023 case LL_RCC_DSI_CLKSOURCE_PLL: /* DSI Clock is PLL Osc. */
1024 if (LL_RCC_PLL_IsReady())
1025 {
1026 dsi_frequency = RCC_PLL_GetFreqDomain_DSI();
1027 }
1028 break;
1029
1030 case LL_RCC_DSI_CLKSOURCE_PHY: /* DSI Clock is DSI physical clock. */
1031 default:
1032 dsi_frequency = LL_RCC_PERIPH_FREQUENCY_NA;
1033 break;
1034 }
1035
1036 return dsi_frequency;
1037 }
1038 #endif /* DSI */
1039
1040 #if defined(LTDC)
1041 /**
1042 * @brief Return LTDC clock frequency
1043 * @param LTDCxSource This parameter can be one of the following values:
1044 * @arg @ref LL_RCC_LTDC_CLKSOURCE
1045 * @retval LTDC clock frequency (in Hz)
1046 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator PLLSAI is not ready
1047 */
LL_RCC_GetLTDCClockFreq(uint32_t LTDCxSource)1048 uint32_t LL_RCC_GetLTDCClockFreq(uint32_t LTDCxSource)
1049 {
1050 uint32_t ltdc_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1051
1052 /* Check parameter */
1053 assert_param(IS_LL_RCC_LTDC_CLKSOURCE(LTDCxSource));
1054
1055 if (LL_RCC_PLLSAI_IsReady())
1056 {
1057 ltdc_frequency = RCC_PLLSAI_GetFreqDomain_LTDC();
1058 }
1059
1060 return ltdc_frequency;
1061 }
1062 #endif /* LTDC */
1063
1064 #if defined(SPDIFRX)
1065 /**
1066 * @brief Return SPDIFRX clock frequency
1067 * @param SPDIFRXxSource This parameter can be one of the following values:
1068 * @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE
1069 * @retval SPDIFRX clock frequency (in Hz)
1070 * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator is not ready
1071 */
LL_RCC_GetSPDIFRXClockFreq(uint32_t SPDIFRXxSource)1072 uint32_t LL_RCC_GetSPDIFRXClockFreq(uint32_t SPDIFRXxSource)
1073 {
1074 uint32_t spdifrx_frequency = LL_RCC_PERIPH_FREQUENCY_NO;
1075
1076 /* Check parameter */
1077 assert_param(IS_LL_RCC_SPDIFRX_CLKSOURCE(SPDIFRXxSource));
1078
1079 /* SPDIFRX1CLK clock frequency */
1080 switch (LL_RCC_GetSPDIFRXClockSource(SPDIFRXxSource))
1081 {
1082 case LL_RCC_SPDIFRX1_CLKSOURCE_PLLI2S: /* SPDIFRX Clock is PLLI2S Osc. */
1083 if (LL_RCC_PLLI2S_IsReady())
1084 {
1085 spdifrx_frequency = RCC_PLLI2S_GetFreqDomain_SPDIFRX();
1086 }
1087 break;
1088
1089 case LL_RCC_SPDIFRX1_CLKSOURCE_PLL: /* SPDIFRX Clock is PLL Osc. */
1090 default:
1091 if (LL_RCC_PLL_IsReady())
1092 {
1093 spdifrx_frequency = RCC_PLL_GetFreqDomain_SPDIFRX();
1094 }
1095 break;
1096 }
1097
1098 return spdifrx_frequency;
1099 }
1100 #endif /* SPDIFRX */
1101
1102 /**
1103 * @}
1104 */
1105
1106 /**
1107 * @}
1108 */
1109
1110 /** @addtogroup RCC_LL_Private_Functions
1111 * @{
1112 */
1113
1114 /**
1115 * @brief Return SYSTEM clock frequency
1116 * @retval SYSTEM clock frequency (in Hz)
1117 */
RCC_GetSystemClockFreq(void)1118 uint32_t RCC_GetSystemClockFreq(void)
1119 {
1120 uint32_t frequency = 0U;
1121
1122 /* Get SYSCLK source -------------------------------------------------------*/
1123 switch (LL_RCC_GetSysClkSource())
1124 {
1125 case LL_RCC_SYS_CLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
1126 frequency = HSI_VALUE;
1127 break;
1128
1129 case LL_RCC_SYS_CLKSOURCE_STATUS_HSE: /* HSE used as system clock source */
1130 frequency = HSE_VALUE;
1131 break;
1132
1133 case LL_RCC_SYS_CLKSOURCE_STATUS_PLL: /* PLL used as system clock source */
1134 frequency = RCC_PLL_GetFreqDomain_SYS(LL_RCC_SYS_CLKSOURCE_STATUS_PLL);
1135 break;
1136
1137 #if defined(RCC_PLLR_SYSCLK_SUPPORT)
1138 case LL_RCC_SYS_CLKSOURCE_STATUS_PLLR: /* PLLR used as system clock source */
1139 frequency = RCC_PLL_GetFreqDomain_SYS(LL_RCC_SYS_CLKSOURCE_STATUS_PLLR);
1140 break;
1141 #endif /* RCC_PLLR_SYSCLK_SUPPORT */
1142
1143 default:
1144 frequency = HSI_VALUE;
1145 break;
1146 }
1147
1148 return frequency;
1149 }
1150
1151 /**
1152 * @brief Return HCLK clock frequency
1153 * @param SYSCLK_Frequency SYSCLK clock frequency
1154 * @retval HCLK clock frequency (in Hz)
1155 */
RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency)1156 uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency)
1157 {
1158 /* HCLK clock frequency */
1159 return __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, LL_RCC_GetAHBPrescaler());
1160 }
1161
1162 /**
1163 * @brief Return PCLK1 clock frequency
1164 * @param HCLK_Frequency HCLK clock frequency
1165 * @retval PCLK1 clock frequency (in Hz)
1166 */
RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency)1167 uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency)
1168 {
1169 /* PCLK1 clock frequency */
1170 return __LL_RCC_CALC_PCLK1_FREQ(HCLK_Frequency, LL_RCC_GetAPB1Prescaler());
1171 }
1172
1173 /**
1174 * @brief Return PCLK2 clock frequency
1175 * @param HCLK_Frequency HCLK clock frequency
1176 * @retval PCLK2 clock frequency (in Hz)
1177 */
RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency)1178 uint32_t RCC_GetPCLK2ClockFreq(uint32_t HCLK_Frequency)
1179 {
1180 /* PCLK2 clock frequency */
1181 return __LL_RCC_CALC_PCLK2_FREQ(HCLK_Frequency, LL_RCC_GetAPB2Prescaler());
1182 }
1183
1184 /**
1185 * @brief Return PLL clock frequency used for system domain
1186 * @param SYSCLK_Source System clock source
1187 * @retval PLL clock frequency (in Hz)
1188 */
RCC_PLL_GetFreqDomain_SYS(uint32_t SYSCLK_Source)1189 uint32_t RCC_PLL_GetFreqDomain_SYS(uint32_t SYSCLK_Source)
1190 {
1191 uint32_t pllinputfreq = 0U, pllsource = 0U, plloutputfreq = 0U;
1192
1193 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
1194 SYSCLK = PLL_VCO / (PLLP or PLLR)
1195 */
1196 pllsource = LL_RCC_PLL_GetMainSource();
1197
1198 switch (pllsource)
1199 {
1200 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
1201 pllinputfreq = HSI_VALUE;
1202 break;
1203
1204 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
1205 pllinputfreq = HSE_VALUE;
1206 break;
1207
1208 default:
1209 pllinputfreq = HSI_VALUE;
1210 break;
1211 }
1212
1213 if (SYSCLK_Source == LL_RCC_SYS_CLKSOURCE_STATUS_PLL)
1214 {
1215 plloutputfreq = __LL_RCC_CALC_PLLCLK_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
1216 LL_RCC_PLL_GetN(), LL_RCC_PLL_GetP());
1217 }
1218 #if defined(RCC_PLLR_SYSCLK_SUPPORT)
1219 else
1220 {
1221 plloutputfreq = __LL_RCC_CALC_PLLRCLK_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
1222 LL_RCC_PLL_GetN(), LL_RCC_PLL_GetR());
1223 }
1224 #endif /* RCC_PLLR_SYSCLK_SUPPORT */
1225
1226 return plloutputfreq;
1227 }
1228
1229 /**
1230 * @brief Return PLL clock frequency used for 48 MHz domain
1231 * @retval PLL clock frequency (in Hz)
1232 */
RCC_PLL_GetFreqDomain_48M(void)1233 uint32_t RCC_PLL_GetFreqDomain_48M(void)
1234 {
1235 uint32_t pllinputfreq = 0U, pllsource = 0U;
1236
1237 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM ) * PLLN
1238 48M Domain clock = PLL_VCO / PLLQ
1239 */
1240 pllsource = LL_RCC_PLL_GetMainSource();
1241
1242 switch (pllsource)
1243 {
1244 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
1245 pllinputfreq = HSI_VALUE;
1246 break;
1247
1248 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
1249 pllinputfreq = HSE_VALUE;
1250 break;
1251
1252 default:
1253 pllinputfreq = HSI_VALUE;
1254 break;
1255 }
1256 return __LL_RCC_CALC_PLLCLK_48M_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
1257 LL_RCC_PLL_GetN(), LL_RCC_PLL_GetQ());
1258 }
1259
1260 #if defined(DSI)
1261 /**
1262 * @brief Return PLL clock frequency used for DSI clock
1263 * @retval PLL clock frequency (in Hz)
1264 */
RCC_PLL_GetFreqDomain_DSI(void)1265 uint32_t RCC_PLL_GetFreqDomain_DSI(void)
1266 {
1267 uint32_t pllinputfreq = 0U, pllsource = 0U;
1268
1269 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
1270 DSICLK = PLL_VCO / PLLR
1271 */
1272 pllsource = LL_RCC_PLL_GetMainSource();
1273
1274 switch (pllsource)
1275 {
1276 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
1277 pllinputfreq = HSE_VALUE;
1278 break;
1279
1280 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
1281 default:
1282 pllinputfreq = HSI_VALUE;
1283 break;
1284 }
1285 return __LL_RCC_CALC_PLLCLK_DSI_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
1286 LL_RCC_PLL_GetN(), LL_RCC_PLL_GetR());
1287 }
1288 #endif /* DSI */
1289
1290 #if defined(RCC_DCKCFGR_I2SSRC) || defined(RCC_DCKCFGR_I2S1SRC)
1291 /**
1292 * @brief Return PLL clock frequency used for I2S clock
1293 * @retval PLL clock frequency (in Hz)
1294 */
RCC_PLL_GetFreqDomain_I2S(void)1295 uint32_t RCC_PLL_GetFreqDomain_I2S(void)
1296 {
1297 uint32_t pllinputfreq = 0U, pllsource = 0U;
1298
1299 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
1300 I2SCLK = PLL_VCO / PLLR
1301 */
1302 pllsource = LL_RCC_PLL_GetMainSource();
1303
1304 switch (pllsource)
1305 {
1306 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
1307 pllinputfreq = HSE_VALUE;
1308 break;
1309
1310 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
1311 default:
1312 pllinputfreq = HSI_VALUE;
1313 break;
1314 }
1315 return __LL_RCC_CALC_PLLCLK_I2S_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
1316 LL_RCC_PLL_GetN(), LL_RCC_PLL_GetR());
1317 }
1318 #endif /* RCC_DCKCFGR_I2SSRC || RCC_DCKCFGR_I2S1SRC */
1319
1320 #if defined(SPDIFRX)
1321 /**
1322 * @brief Return PLL clock frequency used for SPDIFRX clock
1323 * @retval PLL clock frequency (in Hz)
1324 */
RCC_PLL_GetFreqDomain_SPDIFRX(void)1325 uint32_t RCC_PLL_GetFreqDomain_SPDIFRX(void)
1326 {
1327 uint32_t pllinputfreq = 0U, pllsource = 0U;
1328
1329 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
1330 SPDIFRXCLK = PLL_VCO / PLLR
1331 */
1332 pllsource = LL_RCC_PLL_GetMainSource();
1333
1334 switch (pllsource)
1335 {
1336 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
1337 pllinputfreq = HSE_VALUE;
1338 break;
1339
1340 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
1341 default:
1342 pllinputfreq = HSI_VALUE;
1343 break;
1344 }
1345 return __LL_RCC_CALC_PLLCLK_SPDIFRX_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
1346 LL_RCC_PLL_GetN(), LL_RCC_PLL_GetR());
1347 }
1348 #endif /* SPDIFRX */
1349
1350 #if defined(RCC_PLLCFGR_PLLR)
1351 #if defined(SAI1)
1352 /**
1353 * @brief Return PLL clock frequency used for SAI clock
1354 * @retval PLL clock frequency (in Hz)
1355 */
RCC_PLL_GetFreqDomain_SAI(void)1356 uint32_t RCC_PLL_GetFreqDomain_SAI(void)
1357 {
1358 uint32_t pllinputfreq = 0U, pllsource = 0U, plloutputfreq = 0U;
1359
1360 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
1361 SAICLK = (PLL_VCO / PLLR) / PLLDIVR
1362 or
1363 SAICLK = PLL_VCO / PLLR
1364 */
1365 pllsource = LL_RCC_PLL_GetMainSource();
1366
1367 switch (pllsource)
1368 {
1369 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
1370 pllinputfreq = HSE_VALUE;
1371 break;
1372
1373 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
1374 default:
1375 pllinputfreq = HSI_VALUE;
1376 break;
1377 }
1378
1379 #if defined(RCC_DCKCFGR_PLLDIVR)
1380 plloutputfreq = __LL_RCC_CALC_PLLCLK_SAI_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
1381 LL_RCC_PLL_GetN(), LL_RCC_PLL_GetR(), LL_RCC_PLL_GetDIVR());
1382 #else
1383 plloutputfreq = __LL_RCC_CALC_PLLCLK_SAI_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
1384 LL_RCC_PLL_GetN(), LL_RCC_PLL_GetR());
1385 #endif /* RCC_DCKCFGR_PLLDIVR */
1386
1387 return plloutputfreq;
1388 }
1389 #endif /* SAI1 */
1390 #endif /* RCC_PLLCFGR_PLLR */
1391
1392 #if defined(RCC_PLLSAI_SUPPORT)
1393 /**
1394 * @brief Return PLLSAI clock frequency used for SAI domain
1395 * @retval PLLSAI clock frequency (in Hz)
1396 */
RCC_PLLSAI_GetFreqDomain_SAI(void)1397 uint32_t RCC_PLLSAI_GetFreqDomain_SAI(void)
1398 {
1399 uint32_t pllinputfreq = 0U, pllsource = 0U;
1400
1401 /* PLLSAI_VCO = (HSE_VALUE or HSI_VALUE / PLLSAIM) * PLLSAIN
1402 SAI domain clock = (PLLSAI_VCO / PLLSAIQ) / PLLSAIDIVQ
1403 */
1404 pllsource = LL_RCC_PLL_GetMainSource();
1405
1406 switch (pllsource)
1407 {
1408 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLSAI clock source */
1409 pllinputfreq = HSI_VALUE;
1410 break;
1411
1412 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLSAI clock source */
1413 pllinputfreq = HSE_VALUE;
1414 break;
1415
1416 default:
1417 pllinputfreq = HSI_VALUE;
1418 break;
1419 }
1420 return __LL_RCC_CALC_PLLSAI_SAI_FREQ(pllinputfreq, LL_RCC_PLLSAI_GetDivider(),
1421 LL_RCC_PLLSAI_GetN(), LL_RCC_PLLSAI_GetQ(), LL_RCC_PLLSAI_GetDIVQ());
1422 }
1423
1424 #if defined(RCC_PLLSAICFGR_PLLSAIP)
1425 /**
1426 * @brief Return PLLSAI clock frequency used for 48Mhz domain
1427 * @retval PLLSAI clock frequency (in Hz)
1428 */
RCC_PLLSAI_GetFreqDomain_48M(void)1429 uint32_t RCC_PLLSAI_GetFreqDomain_48M(void)
1430 {
1431 uint32_t pllinputfreq = 0U, pllsource = 0U;
1432
1433 /* PLLSAI_VCO = (HSE_VALUE or HSI_VALUE / PLLSAIM) * PLLSAIN
1434 48M Domain clock = PLLSAI_VCO / PLLSAIP
1435 */
1436 pllsource = LL_RCC_PLL_GetMainSource();
1437
1438 switch (pllsource)
1439 {
1440 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLSAI clock source */
1441 pllinputfreq = HSI_VALUE;
1442 break;
1443
1444 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLSAI clock source */
1445 pllinputfreq = HSE_VALUE;
1446 break;
1447
1448 default:
1449 pllinputfreq = HSI_VALUE;
1450 break;
1451 }
1452 return __LL_RCC_CALC_PLLSAI_48M_FREQ(pllinputfreq, LL_RCC_PLLSAI_GetDivider(),
1453 LL_RCC_PLLSAI_GetN(), LL_RCC_PLLSAI_GetP());
1454 }
1455 #endif /* RCC_PLLSAICFGR_PLLSAIP */
1456
1457 #if defined(LTDC)
1458 /**
1459 * @brief Return PLLSAI clock frequency used for LTDC domain
1460 * @retval PLLSAI clock frequency (in Hz)
1461 */
RCC_PLLSAI_GetFreqDomain_LTDC(void)1462 uint32_t RCC_PLLSAI_GetFreqDomain_LTDC(void)
1463 {
1464 uint32_t pllinputfreq = 0U, pllsource = 0U;
1465
1466 /* PLLSAI_VCO = (HSE_VALUE or HSI_VALUE / PLLSAIM) * PLLSAIN
1467 LTDC Domain clock = (PLLSAI_VCO / PLLSAIR) / PLLSAIDIVR
1468 */
1469 pllsource = LL_RCC_PLL_GetMainSource();
1470
1471 switch (pllsource)
1472 {
1473 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLSAI clock source */
1474 pllinputfreq = HSI_VALUE;
1475 break;
1476
1477 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLSAI clock source */
1478 pllinputfreq = HSE_VALUE;
1479 break;
1480
1481 default:
1482 pllinputfreq = HSI_VALUE;
1483 break;
1484 }
1485 return __LL_RCC_CALC_PLLSAI_LTDC_FREQ(pllinputfreq, LL_RCC_PLLSAI_GetDivider(),
1486 LL_RCC_PLLSAI_GetN(), LL_RCC_PLLSAI_GetR(), LL_RCC_PLLSAI_GetDIVR());
1487 }
1488 #endif /* LTDC */
1489 #endif /* RCC_PLLSAI_SUPPORT */
1490
1491 #if defined(RCC_PLLI2S_SUPPORT)
1492 #if defined(SAI1)
1493 /**
1494 * @brief Return PLLI2S clock frequency used for SAI domains
1495 * @retval PLLI2S clock frequency (in Hz)
1496 */
RCC_PLLI2S_GetFreqDomain_SAI(void)1497 uint32_t RCC_PLLI2S_GetFreqDomain_SAI(void)
1498 {
1499 uint32_t plli2sinputfreq = 0U, plli2ssource = 0U, plli2soutputfreq = 0U;
1500
1501 /* PLLI2S_VCO = (HSE_VALUE or HSI_VALUE / PLLI2SM) * PLLI2SN
1502 SAI domain clock = (PLLI2S_VCO / PLLI2SQ) / PLLI2SDIVQ
1503 or
1504 SAI domain clock = (PLLI2S_VCO / PLLI2SR) / PLLI2SDIVR
1505 */
1506 plli2ssource = LL_RCC_PLLI2S_GetMainSource();
1507
1508 switch (plli2ssource)
1509 {
1510 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLI2S clock source */
1511 plli2sinputfreq = HSE_VALUE;
1512 break;
1513
1514 #if defined(RCC_PLLI2SCFGR_PLLI2SSRC)
1515 case LL_RCC_PLLI2SSOURCE_PIN: /* External pin input clock used as PLLI2S clock source */
1516 plli2sinputfreq = EXTERNAL_CLOCK_VALUE;
1517 break;
1518 #endif /* RCC_PLLI2SCFGR_PLLI2SSRC */
1519
1520 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLI2S clock source */
1521 default:
1522 plli2sinputfreq = HSI_VALUE;
1523 break;
1524 }
1525
1526 #if defined(RCC_DCKCFGR_PLLI2SDIVQ)
1527 plli2soutputfreq = __LL_RCC_CALC_PLLI2S_SAI_FREQ(plli2sinputfreq, LL_RCC_PLLI2S_GetDivider(),
1528 LL_RCC_PLLI2S_GetN(), LL_RCC_PLLI2S_GetQ(), LL_RCC_PLLI2S_GetDIVQ());
1529 #else
1530 plli2soutputfreq = __LL_RCC_CALC_PLLI2S_SAI_FREQ(plli2sinputfreq, LL_RCC_PLLI2S_GetDivider(),
1531 LL_RCC_PLLI2S_GetN(), LL_RCC_PLLI2S_GetR(), LL_RCC_PLLI2S_GetDIVR());
1532 #endif /* RCC_DCKCFGR_PLLI2SDIVQ */
1533
1534 return plli2soutputfreq;
1535 }
1536 #endif /* SAI1 */
1537
1538 #if defined(SPDIFRX)
1539 /**
1540 * @brief Return PLLI2S clock frequency used for SPDIFRX domain
1541 * @retval PLLI2S clock frequency (in Hz)
1542 */
RCC_PLLI2S_GetFreqDomain_SPDIFRX(void)1543 uint32_t RCC_PLLI2S_GetFreqDomain_SPDIFRX(void)
1544 {
1545 uint32_t pllinputfreq = 0U, pllsource = 0U;
1546
1547 /* PLLI2S_VCO = (HSE_VALUE or HSI_VALUE / PLLI2SM) * PLLI2SN
1548 SPDIFRX Domain clock = PLLI2S_VCO / PLLI2SP
1549 */
1550 pllsource = LL_RCC_PLLI2S_GetMainSource();
1551
1552 switch (pllsource)
1553 {
1554 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLI2S clock source */
1555 pllinputfreq = HSE_VALUE;
1556 break;
1557
1558 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLI2S clock source */
1559 default:
1560 pllinputfreq = HSI_VALUE;
1561 break;
1562 }
1563
1564 return __LL_RCC_CALC_PLLI2S_SPDIFRX_FREQ(pllinputfreq, LL_RCC_PLLI2S_GetDivider(),
1565 LL_RCC_PLLI2S_GetN(), LL_RCC_PLLI2S_GetP());
1566 }
1567 #endif /* SPDIFRX */
1568
1569 /**
1570 * @brief Return PLLI2S clock frequency used for I2S domain
1571 * @retval PLLI2S clock frequency (in Hz)
1572 */
RCC_PLLI2S_GetFreqDomain_I2S(void)1573 uint32_t RCC_PLLI2S_GetFreqDomain_I2S(void)
1574 {
1575 uint32_t plli2sinputfreq = 0U, plli2ssource = 0U, plli2soutputfreq = 0U;
1576
1577 /* PLLI2S_VCO = (HSE_VALUE or HSI_VALUE / PLLI2SM) * PLLI2SN
1578 I2S Domain clock = PLLI2S_VCO / PLLI2SR
1579 */
1580 plli2ssource = LL_RCC_PLLI2S_GetMainSource();
1581
1582 switch (plli2ssource)
1583 {
1584 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLI2S clock source */
1585 plli2sinputfreq = HSE_VALUE;
1586 break;
1587
1588 #if defined(RCC_PLLI2SCFGR_PLLI2SSRC)
1589 case LL_RCC_PLLI2SSOURCE_PIN: /* External pin input clock used as PLLI2S clock source */
1590 plli2sinputfreq = EXTERNAL_CLOCK_VALUE;
1591 break;
1592 #endif /* RCC_PLLI2SCFGR_PLLI2SSRC */
1593
1594 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLI2S clock source */
1595 default:
1596 plli2sinputfreq = HSI_VALUE;
1597 break;
1598 }
1599
1600 plli2soutputfreq = __LL_RCC_CALC_PLLI2S_I2S_FREQ(plli2sinputfreq, LL_RCC_PLLI2S_GetDivider(),
1601 LL_RCC_PLLI2S_GetN(), LL_RCC_PLLI2S_GetR());
1602
1603 return plli2soutputfreq;
1604 }
1605
1606 #if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ)
1607 /**
1608 * @brief Return PLLI2S clock frequency used for 48Mhz domain
1609 * @retval PLLI2S clock frequency (in Hz)
1610 */
RCC_PLLI2S_GetFreqDomain_48M(void)1611 uint32_t RCC_PLLI2S_GetFreqDomain_48M(void)
1612 {
1613 uint32_t plli2sinputfreq = 0U, plli2ssource = 0U, plli2soutputfreq = 0U;
1614
1615 /* PLL48M_VCO = (HSE_VALUE or HSI_VALUE / PLLI2SM) * PLLI2SN
1616 48M Domain clock = PLLI2S_VCO / PLLI2SQ
1617 */
1618 plli2ssource = LL_RCC_PLLI2S_GetMainSource();
1619
1620 switch (plli2ssource)
1621 {
1622 case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLI2S clock source */
1623 plli2sinputfreq = HSE_VALUE;
1624 break;
1625
1626 #if defined(RCC_PLLI2SCFGR_PLLI2SSRC)
1627 case LL_RCC_PLLI2SSOURCE_PIN: /* External pin input clock used as PLLI2S clock source */
1628 plli2sinputfreq = EXTERNAL_CLOCK_VALUE;
1629 break;
1630 #endif /* RCC_PLLI2SCFGR_PLLI2SSRC */
1631
1632 case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLLI2S clock source */
1633 default:
1634 plli2sinputfreq = HSI_VALUE;
1635 break;
1636 }
1637
1638 plli2soutputfreq = __LL_RCC_CALC_PLLI2S_48M_FREQ(plli2sinputfreq, LL_RCC_PLLI2S_GetDivider(),
1639 LL_RCC_PLLI2S_GetN(), LL_RCC_PLLI2S_GetQ());
1640
1641 return plli2soutputfreq;
1642 }
1643 #endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */
1644 #endif /* RCC_PLLI2S_SUPPORT */
1645 /**
1646 * @}
1647 */
1648
1649 /**
1650 * @}
1651 */
1652
1653 #endif /* defined(RCC) */
1654
1655 /**
1656 * @}
1657 */
1658
1659 #endif /* USE_FULL_LL_DRIVER */
1660
1661
