1 /**
2 ******************************************************************************
3 * @file stm32c0xx_ll_system.h
4 * @author MCD Application Team
5 * @brief Header file of SYSTEM LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2022 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 @verbatim
18 ==============================================================================
19 ##### How to use this driver #####
20 ==============================================================================
21 [..]
22 The LL SYSTEM driver contains a set of generic APIs that can be
23 used by user:
24 (+) Some of the FLASH features need to be handled in the SYSTEM file.
25 (+) Access to DBGCMU registers
26 (+) Access to SYSCFG registers
27 @endverbatim
28 ******************************************************************************
29 */
30
31 /* Define to prevent recursive inclusion -------------------------------------*/
32 #ifndef STM32C0xx_LL_SYSTEM_H
33 #define STM32C0xx_LL_SYSTEM_H
34
35 #ifdef __cplusplus
36 extern "C" {
37 #endif
38
39 /* Includes ------------------------------------------------------------------*/
40 #include "stm32c0xx.h"
41
42 /** @addtogroup STM32C0xx_LL_Driver
43 * @{
44 */
45
46 #if defined (FLASH) || defined (SYSCFG) || defined (DBG)
47
48 /** @defgroup SYSTEM_LL SYSTEM
49 * @{
50 */
51
52 /* Private types -------------------------------------------------------------*/
53 /* Private variables ---------------------------------------------------------*/
54
55 /* Private constants ---------------------------------------------------------*/
56 /** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants
57 * @{
58 */
59
60 /**
61 * @}
62 */
63
64 /* Private macros ------------------------------------------------------------*/
65
66 /* Exported types ------------------------------------------------------------*/
67 /* Exported constants --------------------------------------------------------*/
68 /** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants
69 * @{
70 */
71
72 /** @defgroup SYSTEM_LL_EC_REMAP SYSCFG REMAP
73 * @{
74 */
75 #define LL_SYSCFG_REMAP_FLASH 0x00000000U /*!< Main Flash memory mapped at 0x00000000 */
76 #define LL_SYSCFG_REMAP_SYSTEMFLASH SYSCFG_CFGR1_MEM_MODE_0 /*!< System Flash memory mapped at 0x00000000 */
77 #define LL_SYSCFG_REMAP_SRAM (SYSCFG_CFGR1_MEM_MODE_1 | SYSCFG_CFGR1_MEM_MODE_0) /*!< Embedded SRAM mapped at 0x00000000 */
78 /**
79 * @}
80 */
81
82 /** @defgroup SYSTEM_LL_EC_PIN_RMP SYSCFG PIN RMP
83 * @{
84 */
85 #define LL_SYSCFG_PIN_RMP_PA11 SYSCFG_CFGR1_PA11_RMP /*!< PA11 pad behaves as PA9 pin */
86 #define LL_SYSCFG_PIN_RMP_PA12 SYSCFG_CFGR1_PA12_RMP /*!< PA12 pad behaves as PA10 pin */
87 /**
88 * @}
89 */
90
91 /** @defgroup SYSTEM_LL_EC_IR_MOD SYSCFG IR Modulation
92 * @{
93 */
94 #define LL_SYSCFG_IR_MOD_TIM16 (SYSCFG_CFGR1_IR_MOD_0 & SYSCFG_CFGR1_IR_MOD_1) /*!< 00: Timer16 is selected as IRDA Modulation envelope source */
95 #define LL_SYSCFG_IR_MOD_USART1 (SYSCFG_CFGR1_IR_MOD_0) /*!< 01: USART1 is selected as IRDA Modulation envelope source */
96 #define LL_SYSCFG_IR_MOD_USART2 (SYSCFG_CFGR1_IR_MOD_1) /*!< 10: USART2 is selected as IRDA Modulation envelope source */
97
98 /**
99 * @}
100 */
101 /** @defgroup SYSTEM_LL_EC_IR_POL SYSCFG IR Polarity
102 * @{
103 */
104 #define LL_SYSCFG_IR_POL_NOT_INVERTED 0x00000000U /*!< 0: Output of IRDA (IROut) not inverted */
105 #define LL_SYSCFG_IR_POL_INVERTED (SYSCFG_CFGR1_IR_POL) /*!< 1: Output of IRDA (IROut) inverted */
106 /**
107 * @}
108 */
109
110 /** @defgroup SYSTEM_LL_EC_BOOSTEN SYSCFG I/O analog switch voltage booster enable
111 * @{
112 */
113 #define LL_SYSCFG_CFGR1_BOOSTEN SYSCFG_CFGR1_BOOSTEN /*!< I/O analog switch voltage booster enable */
114 /**
115 * @}
116 */
117
118 /** @defgroup SYSTEM_LL_EC_I2C_FASTMODEPLUS SYSCFG I2C FASTMODEPLUS
119 * @{
120 */
121 #define LL_SYSCFG_I2C_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP /*!< I2C PB6 Fast mode plus */
122 #define LL_SYSCFG_I2C_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP /*!< I2C PB7 Fast mode plus */
123 #define LL_SYSCFG_I2C_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP /*!< I2C PB8 Fast mode plus */
124 #define LL_SYSCFG_I2C_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP /*!< I2C PB9 Fast mode plus */
125 #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C1_FMP /*!< Enable I2C1 Fast mode Plus */
126 #define LL_SYSCFG_I2C_FASTMODEPLUS_PA9 SYSCFG_CFGR1_I2C_PA9_FMP /*!< Enable Fast Mode Plus on PA9 */
127 #define LL_SYSCFG_I2C_FASTMODEPLUS_PA10 SYSCFG_CFGR1_I2C_PA10_FMP /*!< Enable Fast Mode Plus on PA10 */
128 #define LL_SYSCFG_I2C_FASTMODEPLUS_PC14 SYSCFG_CFGR1_I2C_PC14_FMP /*!< Enable Fast Mode Plus on PC14 */
129 /**
130 * @}
131 */
132
133 /** @defgroup SYSTEM_LL_EC_TIMBREAK SYSCFG TIMER BREAK
134 * @{
135 */
136 #define LL_SYSCFG_TIMBREAK_LOCKUP SYSCFG_CFGR2_CLL /*!< Enables and locks the LOCKUP (Hardfault) output of
137 CortexM0 with Break Input of TIM1/16/17 */
138 /**
139 * @}
140 */
141
142 /** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP
143 * @{
144 */
145 #define LL_DBGMCU_APB1_GRP1_TIM3_STOP DBG_APB_FZ1_DBG_TIM3_STOP /*!< TIM3 counter stopped when core is halted */
146 #define LL_DBGMCU_APB1_GRP1_RTC_STOP DBG_APB_FZ1_DBG_RTC_STOP /*!< RTC Calendar frozen when core is halted */
147 #define LL_DBGMCU_APB1_GRP1_WWDG_STOP DBG_APB_FZ1_DBG_WWDG_STOP /*!< Debug Window Watchdog stopped when Core is halted */
148 #define LL_DBGMCU_APB1_GRP1_IWDG_STOP DBG_APB_FZ1_DBG_IWDG_STOP /*!< Debug Independent Watchdog stopped when Core is halted */
149 #define LL_DBGMCU_APB1_GRP1_I2C1_STOP DBG_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_STOP /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
150
151 /**
152 * @}
153 */
154
155 /** @defgroup SYSTEM_LL_EC_APB2_GRP1_STOP_IP DBGMCU APB2 GRP1 STOP IP
156 * @{
157 */
158 #define LL_DBGMCU_APB2_GRP1_TIM1_STOP DBG_APB_FZ2_DBG_TIM1_STOP /*!< TIM1 counter stopped when core is halted */
159 #if defined(DBG_APB_FZ2_DBG_TIM14_STOP)
160 #define LL_DBGMCU_APB2_GRP1_TIM14_STOP DBG_APB_FZ2_DBG_TIM14_STOP /*!< TIM14 counter stopped when core is halted */
161 #endif /* DBG_APB_FZ2_DBG_TIM14_STOP */
162 #define LL_DBGMCU_APB2_GRP1_TIM16_STOP DBG_APB_FZ2_DBG_TIM16_STOP /*!< TIM16 counter stopped when core is halted */
163 #define LL_DBGMCU_APB2_GRP1_TIM17_STOP DBG_APB_FZ2_DBG_TIM17_STOP /*!< TIM17 counter stopped when core is halted */
164 /**
165 * @}
166 */
167
168 /** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY
169 * @{
170 */
171 #define LL_FLASH_LATENCY_0 0x00000000U /*!< FLASH Zero Latency cycle */
172 #define LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY_0 /*!< FLASH One Latency cycle */
173
174 /**
175 * @}
176 */
177
178 /** @defgroup SYSTEM_LL_PINMUX_CFG PINMUX Config
179 * @{
180 */
181 #if (DEV_ID == 0x443UL)
182 #define LL_PINMUX_SO8_PIN1_PB7 (((SYSCFG_CFGR3_PINMUX0_0 | SYSCFG_CFGR3_PINMUX0_1) << 16U) | 0x00000000U) /*!< STM32C011 SO8 package, Pin1 assigned to GPIO PB7 */
183 #define LL_PINMUX_SO8_PIN1_PC14 (((SYSCFG_CFGR3_PINMUX0_0 | SYSCFG_CFGR3_PINMUX0_1) << 16U) | SYSCFG_CFGR3_PINMUX0_0) /*!< STM32C011 SO8 package, Pin1 assigned to GPIO PC14 */
184 #define LL_PINMUX_SO8_PIN4_PF2 (((SYSCFG_CFGR3_PINMUX1_0 | SYSCFG_CFGR3_PINMUX1_1) << 16U) | 0x00000000U) /*!< STM32C011 SO8 package, Pin4 assigned to GPIO PF2 */
185 #define LL_PINMUX_SO8_PIN4_PA0 (((SYSCFG_CFGR3_PINMUX1_0 | SYSCFG_CFGR3_PINMUX1_1) << 16U) | SYSCFG_CFGR3_PINMUX1_0) /*!< STM32C011 SO8 package, Pin4 assigned to GPIO PA0 */
186 #define LL_PINMUX_SO8_PIN4_PA1 (((SYSCFG_CFGR3_PINMUX1_0 | SYSCFG_CFGR3_PINMUX1_1) << 16U) | SYSCFG_CFGR3_PINMUX1_1) /*!< STM32C011 SO8 package, Pin4 assigned to GPIO PA1 */
187 #define LL_PINMUX_SO8_PIN4_PA2 (((SYSCFG_CFGR3_PINMUX1_0 | SYSCFG_CFGR3_PINMUX1_1) << 16U) | SYSCFG_CFGR3_PINMUX1_0 | SYSCFG_CFGR3_PINMUX1_1) /*!< STM32C011 SO8 package, Pin4 assigned to GPIO PA2 */
188 #define LL_PINMUX_SO8_PIN5_PA8 (((SYSCFG_CFGR3_PINMUX2_0 | SYSCFG_CFGR3_PINMUX2_1) << 16U) | 0x00000000U) /*!< STM32C011 SO8 package, Pin5 assigned to GPIO PA8 */
189 #define LL_PINMUX_SO8_PIN5_PA11 (((SYSCFG_CFGR3_PINMUX2_0 | SYSCFG_CFGR3_PINMUX2_1) << 16U) | SYSCFG_CFGR3_PINMUX2_0) /*!< STM32C011 SO8 package, Pin5 assigned to GPIO PA11 */
190 #define LL_PINMUX_SO8_PIN8_PA14 (((SYSCFG_CFGR3_PINMUX3_0 | SYSCFG_CFGR3_PINMUX3_1) << 16U) | 0x00000000U) /*!< STM32C011 SO8 package, Pin8 assigned to GPIO PA14 */
191 #define LL_PINMUX_SO8_PIN8_PB6 (((SYSCFG_CFGR3_PINMUX3_0 | SYSCFG_CFGR3_PINMUX3_1) << 16U) | SYSCFG_CFGR3_PINMUX3_0) /*!< STM32C011 SO8 package, Pin8 assigned to GPIO PB6 */
192 #define LL_PINMUX_SO8_PIN8_PC15 (((SYSCFG_CFGR3_PINMUX3_0 | SYSCFG_CFGR3_PINMUX3_1) << 16U) | SYSCFG_CFGR3_PINMUX3_1) /*!< STM32C011 SO8 package, Pin8 assigned to GPIO PC15 */
193 #define LL_PINMUX_WLCSP12_PINE2_PA7 (((SYSCFG_CFGR3_PINMUX4_0 | SYSCFG_CFGR3_PINMUX4_1) << 16U) | 0x00000000U) /*!< STM32C011 WLCSP12 package, PinE2 assigned to GPIO PA7 */
194 #define LL_PINMUX_WLCSP12_PINE2_PA12 (((SYSCFG_CFGR3_PINMUX4_0 | SYSCFG_CFGR3_PINMUX4_1) << 16U) | SYSCFG_CFGR3_PINMUX4_0) /*!< STM32C011 WLCSP12 package, PinE2 assigned to GPIO PA12 */
195 #define LL_PINMUX_WLCSP12_PINF1_PA3 (((SYSCFG_CFGR3_PINMUX5_0 | SYSCFG_CFGR3_PINMUX5_1) << 16U) | 0x00000000U) /*!< STM32C011 WLCSP12 package, PinF1 assigned to GPIO PA3*/
196 #define LL_PINMUX_WLCSP12_PINF1_PA4 (((SYSCFG_CFGR3_PINMUX5_0 | SYSCFG_CFGR3_PINMUX5_1) << 16U) | SYSCFG_CFGR3_PINMUX5_0) /*!< STM32C011 WLCSP12 package, PinF1 assigned to GPIO PA4 */
197 #define LL_PINMUX_WLCSP12_PINF1_PA5 (((SYSCFG_CFGR3_PINMUX5_0 | SYSCFG_CFGR3_PINMUX5_1) << 16U) | SYSCFG_CFGR3_PINMUX5_1) /*!< STM32C011 WLCSP12 package, PinF1 assigned to GPIO PA5 */
198 #define LL_PINMUX_WLCSP12_PINF1_PA6 (((SYSCFG_CFGR3_PINMUX5_0 | SYSCFG_CFGR3_PINMUX5_1) << 16U) | SYSCFG_CFGR3_PINMUX5_0 | SYSCFG_CFGR3_PINMUX5_1) /*!< STM32C011 WLCSP12 package, PinF1 assigned to GPIO PA6 */
199
200 #elif (DEV_ID == 0x453UL)
201 #define LL_PINMUX_WLCSP14_PINF2_PA1 (((SYSCFG_CFGR3_PINMUX0_0 | SYSCFG_CFGR3_PINMUX0_1) << 16U) | 0x00000000U) /*!< STM32C031 WLCSP14 package, PinF2 assigned to GPIO PA1 */
202 #define LL_PINMUX_WLCSP14_PINF2_PA2 (((SYSCFG_CFGR3_PINMUX0_0 | SYSCFG_CFGR3_PINMUX0_1) << 16U) | SYSCFG_CFGR3_PINMUX0_0) /*!< STM32C031 WLCSP14 package, PinF2 assigned to GPIO PA2 */
203 #define LL_PINMUX_WLCSP14_PING3_PF2 (((SYSCFG_CFGR3_PINMUX1_0 | SYSCFG_CFGR3_PINMUX1_1) << 16U) | 0x00000000U) /*!< STM32C031 WLCSP14 package, PinG3 assigned to GPIO PF2 */
204 #define LL_PINMUX_WLCSP14_PING3_PA0 (((SYSCFG_CFGR3_PINMUX1_0 | SYSCFG_CFGR3_PINMUX1_1) << 16U) | SYSCFG_CFGR3_PINMUX1_0) /*!< STM32C031 WLCSP14 package, PinG3 assigned to GPIO PA0 */
205 #define LL_PINMUX_WLCSP14_PINJ1_PA8 (((SYSCFG_CFGR3_PINMUX2_0 | SYSCFG_CFGR3_PINMUX2_1) << 16U) | 0x00000000U) /*!< STM32C031 WLCSP14 package, PinJ1 assigned to GPIO PA8 */
206 #define LL_PINMUX_WLCSP14_PINJ1_PA11 (((SYSCFG_CFGR3_PINMUX2_0 | SYSCFG_CFGR3_PINMUX2_1) << 16U) | SYSCFG_CFGR3_PINMUX2_0) /*!< STM32C031 WLCSP14 package, PinJ1 assigned to GPIO PA11 */
207 #define LL_PINMUX_WLCSP14_PINH2_PA5 (((SYSCFG_CFGR3_PINMUX3_0 | SYSCFG_CFGR3_PINMUX3_1) << 16U) | 0x00000000U) /*!< STM32C031 WLCSP14 package, PinH2 assigned to GPIO PA5 */
208 #define LL_PINMUX_WLCSP14_PINH2_PA6 (((SYSCFG_CFGR3_PINMUX3_0 | SYSCFG_CFGR3_PINMUX3_1) << 16U) | SYSCFG_CFGR3_PINMUX3_0) /*!< STM32C031 WLCSP14 package, PinH2 assigned to GPIO PA6 */
209 #define LL_PINMUX_WLCSP14_PING1_PA7 (((SYSCFG_CFGR3_PINMUX4_0 | SYSCFG_CFGR3_PINMUX4_1) << 16U) | 0x00000000U) /*!< STM32C031 WLCSP14 package, PinG1 assigned to GPIO PA7 */
210 #define LL_PINMUX_WLCSP14_PING1_PA12 (((SYSCFG_CFGR3_PINMUX4_0 | SYSCFG_CFGR3_PINMUX4_1) << 16U) | SYSCFG_CFGR3_PINMUX4_0) /*!< STM32C031 WLCSP14 package, PinG1 assigned to GPIO PA12 */
211 #define LL_PINMUX_WLCSP14_PINJ3_PA3 (((SYSCFG_CFGR3_PINMUX5_0 | SYSCFG_CFGR3_PINMUX5_1) << 16U) | 0x00000000U) /*!< STM32C031 WLCSP14 package, PinJ3 assigned to GPIO PA3 */
212 #define LL_PINMUX_WLCSP14_PINJ3_PA4 (((SYSCFG_CFGR3_PINMUX5_0 | SYSCFG_CFGR3_PINMUX5_1) << 16U) | SYSCFG_CFGR3_PINMUX5_0) /*!< STM32C031 WLCSP14 package, PinJ3 assigned to GPIO PA4 */
213 #endif /* DEV_ID == 0x443UL */
214 /**
215 * @}
216 */
217
218 /** @defgroup SYSTEM_LL_PINMUX_SOURCE PINMUX Config Source
219 * @{
220 */
221 #if (DEV_ID == 0x443UL)
222 #define LL_PINMUX_SO8_PIN1 (SYSCFG_CFGR3_PINMUX0_0 | SYSCFG_CFGR3_PINMUX0_1) /*!< STM32C011 SO8 package, GPIO Pin1 multiplexer */
223 #define LL_PINMUX_SO8_PIN4 (SYSCFG_CFGR3_PINMUX1_0 | SYSCFG_CFGR3_PINMUX1_1) /*!< STM32C011 SO8 package, GPIO Pin4 multiplexer */
224 #define LL_PINMUX_SO8_PIN5 (SYSCFG_CFGR3_PINMUX2_0 | SYSCFG_CFGR3_PINMUX2_1) /*!< STM32C011 SO8 package, GPIO Pin5 multiplexer */
225 #define LL_PINMUX_SO8_PIN8 (SYSCFG_CFGR3_PINMUX3_0 | SYSCFG_CFGR3_PINMUX3_1) /*!< STM32C011 SO8 package, GPIO Pin8 multiplexer */
226 #define LL_PINMUX_WLCSP12_PINE2 (SYSCFG_CFGR3_PINMUX4_0 | SYSCFG_CFGR3_PINMUX4_1) /*!< STM32C011 WLCSP12 package, GPIO PinE2 multiplexer */
227 #define LL_PINMUX_WLCSP12_PINF1 (SYSCFG_CFGR3_PINMUX5_0 | SYSCFG_CFGR3_PINMUX5_1) /*!< STM32C011 WLCSP12 package, GPIO PinF1 multiplexer */
228 #elif (DEV_ID == 0x453UL)
229 #define LL_PINMUX_WLCSP14_PINF2 (SYSCFG_CFGR3_PINMUX0_0 | SYSCFG_CFGR3_PINMUX0_1) /*!< STM32C031 WLCSP14 package, GPIO PinF2 multiplexer */
230 #define LL_PINMUX_WLCSP14_PING3 (SYSCFG_CFGR3_PINMUX1_0 | SYSCFG_CFGR3_PINMUX1_1) /*!< STM32C031 WLCSP14 package, GPIO PinG3 multiplexer */
231 #define LL_PINMUX_WLCSP14_PINJ1 (SYSCFG_CFGR3_PINMUX2_0 | SYSCFG_CFGR3_PINMUX2_1) /*!< STM32C031 WLCSP14 package, GPIO PinJ1 multiplexer */
232 #define LL_PINMUX_WLCSP14_PINH2 (SYSCFG_CFGR3_PINMUX3_0 | SYSCFG_CFGR3_PINMUX3_1) /*!< STM32C031 WLCSP14 package, GPIO PinH2 multiplexer */
233 #define LL_PINMUX_WLCSP14_PING1 (SYSCFG_CFGR3_PINMUX4_0 | SYSCFG_CFGR3_PINMUX4_1) /*!< STM32C031 WLCSP14 package, GPIO PinG1 multiplexer */
234 #define LL_PINMUX_WLCSP14_PINJ3 (SYSCFG_CFGR3_PINMUX5_0 | SYSCFG_CFGR3_PINMUX5_1) /*!< STM32C031 WLCSP14 package, GPIO PinJ3 multiplexer */
235 #endif /* DEV_ID == 0x443UL */
236 /**
237 * @}
238 */
239
240 /**
241 * @}
242 */
243
244 /* Exported macro ------------------------------------------------------------*/
245
246 /* Exported functions --------------------------------------------------------*/
247 /** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions
248 * @{
249 */
250
251 /** @defgroup SYSTEM_LL_EF_SYSCFG SYSCFG
252 * @{
253 */
254
255 /**
256 * @brief Set memory mapping at address 0x00000000
257 * @rmtoll SYSCFG_CFGR1 MEM_MODE LL_SYSCFG_SetRemapMemory
258 * @param Memory This parameter can be one of the following values:
259 * @arg @ref LL_SYSCFG_REMAP_FLASH
260 * @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH
261 * @arg @ref LL_SYSCFG_REMAP_SRAM
262 * @retval None
263 */
LL_SYSCFG_SetRemapMemory(uint32_t Memory)264 __STATIC_INLINE void LL_SYSCFG_SetRemapMemory(uint32_t Memory)
265 {
266 MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE, Memory);
267 }
268
269 /**
270 * @brief Get memory mapping at address 0x00000000
271 * @rmtoll SYSCFG_CFGR1 MEM_MODE LL_SYSCFG_GetRemapMemory
272 * @retval Returned value can be one of the following values:
273 * @arg @ref LL_SYSCFG_REMAP_FLASH
274 * @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH
275 * @arg @ref LL_SYSCFG_REMAP_SRAM
276 */
LL_SYSCFG_GetRemapMemory(void)277 __STATIC_INLINE uint32_t LL_SYSCFG_GetRemapMemory(void)
278 {
279 return (uint32_t)(READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE));
280 }
281
282 /**
283 * @brief Enable remap of a pin on different pad
284 * @rmtoll SYSCFG_CFGR1 PA11_RMP LL_SYSCFG_EnablePinRemap\n
285 * SYSCFG_CFGR1 PA12_RMP LL_SYSCFG_EnablePinRemap\n
286 * @param PinRemap This parameter can be a combination of the following values:
287 * @arg @ref LL_SYSCFG_PIN_RMP_PA11
288 * @arg @ref LL_SYSCFG_PIN_RMP_PA12
289 * @retval None
290 */
LL_SYSCFG_EnablePinRemap(uint32_t PinRemap)291 __STATIC_INLINE void LL_SYSCFG_EnablePinRemap(uint32_t PinRemap)
292 {
293 SET_BIT(SYSCFG->CFGR1, PinRemap);
294 }
295
296 /**
297 * @brief Enable remap of a pin on different pad
298 * @rmtoll SYSCFG_CFGR1 PA11_RMP LL_SYSCFG_DisablePinRemap\n
299 * SYSCFG_CFGR1 PA12_RMP LL_SYSCFG_DisablePinRemap\n
300 * @param PinRemap This parameter can be a combination of the following values:
301 * @arg @ref LL_SYSCFG_PIN_RMP_PA11
302 * @arg @ref LL_SYSCFG_PIN_RMP_PA12
303 * @retval None
304 */
LL_SYSCFG_DisablePinRemap(uint32_t PinRemap)305 __STATIC_INLINE void LL_SYSCFG_DisablePinRemap(uint32_t PinRemap)
306 {
307 CLEAR_BIT(SYSCFG->CFGR1, PinRemap);
308 }
309
310 /**
311 * @brief Set IR Modulation Envelope signal source.
312 * @rmtoll SYSCFG_CFGR1 IR_MOD LL_SYSCFG_SetIRModEnvelopeSignal
313 * @param Source This parameter can be one of the following values:
314 * @arg @ref LL_SYSCFG_IR_MOD_TIM16
315 * @arg @ref LL_SYSCFG_IR_MOD_USART1
316 * @arg @ref LL_SYSCFG_IR_MOD_USART2
317 * @retval None
318 */
LL_SYSCFG_SetIRModEnvelopeSignal(uint32_t Source)319 __STATIC_INLINE void LL_SYSCFG_SetIRModEnvelopeSignal(uint32_t Source)
320 {
321 MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_IR_MOD, Source);
322 }
323
324 /**
325 * @brief Get IR Modulation Envelope signal source.
326 * @rmtoll SYSCFG_CFGR1 IR_MOD LL_SYSCFG_GetIRModEnvelopeSignal
327 * @retval Returned value can be one of the following values:
328 * @arg @ref LL_SYSCFG_IR_MOD_TIM16
329 * @arg @ref LL_SYSCFG_IR_MOD_USART1
330 * @arg @ref LL_SYSCFG_IR_MOD_USART2
331 */
LL_SYSCFG_GetIRModEnvelopeSignal(void)332 __STATIC_INLINE uint32_t LL_SYSCFG_GetIRModEnvelopeSignal(void)
333 {
334 return (uint32_t)(READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_IR_MOD));
335 }
336
337 /**
338 * @brief Set IR Output polarity.
339 * @rmtoll SYSCFG_CFGR1 IR_POL LL_SYSCFG_SetIRPolarity
340 * @param Polarity This parameter can be one of the following values:
341 * @arg @ref LL_SYSCFG_IR_POL_INVERTED
342 * @arg @ref LL_SYSCFG_IR_POL_NOT_INVERTED
343 * @retval None
344 */
LL_SYSCFG_SetIRPolarity(uint32_t Polarity)345 __STATIC_INLINE void LL_SYSCFG_SetIRPolarity(uint32_t Polarity)
346 {
347 MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_IR_POL, Polarity);
348 }
349
350 /**
351 * @brief Get IR Output polarity.
352 * @rmtoll SYSCFG_CFGR1 IR_POL LL_SYSCFG_GetIRPolarity
353 * @retval Returned value can be one of the following values:
354 * @arg @ref LL_SYSCFG_IR_POL_INVERTED
355 * @arg @ref LL_SYSCFG_IR_POL_NOT_INVERTED
356 */
LL_SYSCFG_GetIRPolarity(void)357 __STATIC_INLINE uint32_t LL_SYSCFG_GetIRPolarity(void)
358 {
359 return (uint32_t)(READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_IR_POL));
360 }
361
362
363 /**
364 * @brief Enable the I2C fast mode plus driving capability.
365 * @rmtoll SYSCFG_CFGR1 I2C_FMP_PB6 LL_SYSCFG_EnableFastModePlus\n
366 * SYSCFG_CFGR1 I2C_FMP_PB7 LL_SYSCFG_EnableFastModePlus\n
367 * SYSCFG_CFGR1 I2C_FMP_PB8 LL_SYSCFG_EnableFastModePlus\n
368 * SYSCFG_CFGR1 I2C_FMP_PB9 LL_SYSCFG_EnableFastModePlus\n
369 * SYSCFG_CFGR1 I2C_FMP_I2C1 LL_SYSCFG_EnableFastModePlus\n
370 * SYSCFG_CFGR1 I2C_FMP_PA9 LL_SYSCFG_EnableFastModePlus\n
371 * SYSCFG_CFGR1 I2C_FMP_PA10 LL_SYSCFG_EnableFastModePlus
372 * SYSCFG_CFGR1 I2C_FMP_PC14 LL_SYSCFG_EnableFastModePlus
373 * @param ConfigFastModePlus This parameter can be a combination of the following values:
374 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6
375 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7
376 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8
377 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9
378 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1
379 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PA9
380 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PA10
381 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PC14
382 *
383 * @retval None
384 */
LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus)385 __STATIC_INLINE void LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus)
386 {
387 SET_BIT(SYSCFG->CFGR1, ConfigFastModePlus);
388 }
389
390 /**
391 * @brief Disable the I2C fast mode plus driving capability.
392 * @rmtoll SYSCFG_CFGR1 I2C_FMP_PB6 LL_SYSCFG_DisableFastModePlus\n
393 * SYSCFG_CFGR1 I2C_FMP_PB7 LL_SYSCFG_DisableFastModePlus\n
394 * SYSCFG_CFGR1 I2C_FMP_PB8 LL_SYSCFG_DisableFastModePlus\n
395 * SYSCFG_CFGR1 I2C_FMP_PB9 LL_SYSCFG_DisableFastModePlus\n
396 * SYSCFG_CFGR1 I2C_FMP_I2C1 LL_SYSCFG_DisableFastModePlus\n
397 * SYSCFG_CFGR1 I2C_FMP_PA9 LL_SYSCFG_DisableFastModePlus\n
398 * SYSCFG_CFGR1 I2C_FMP_PA10 LL_SYSCFG_DisableFastModePlus
399 * SYSCFG_CFGR1 I2C_FMP_PC14 LL_SYSCFG_EnableFastModePlus
400 * @param ConfigFastModePlus This parameter can be a combination of the following values:
401 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6
402 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7
403 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8
404 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9
405 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1
406 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PA9
407 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PA10
408 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PC14
409 *
410 * @retval None
411 */
LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus)412 __STATIC_INLINE void LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus)
413 {
414 CLEAR_BIT(SYSCFG->CFGR1, ConfigFastModePlus);
415 }
416
417 /**
418 * @brief Set connections to TIM1/16/17 Break inputs
419 * @rmtoll SYSCFG_CFGR2 CLL LL_SYSCFG_SetTIMBreakInputs\n
420 * @param Break This parameter can be a combination of the following values:
421 * @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP
422 * @retval None
423 */
LL_SYSCFG_SetTIMBreakInputs(uint32_t Break)424 __STATIC_INLINE void LL_SYSCFG_SetTIMBreakInputs(uint32_t Break)
425 {
426 MODIFY_REG(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL, Break);
427 }
428
429 /**
430 * @brief Get connections to TIM1/16/17 Break inputs
431 * @rmtoll SYSCFG_CFGR2 CLL LL_SYSCFG_GetTIMBreakInputs\n
432 * @retval Returned value can be can be a combination of the following values:
433 * @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP
434 */
LL_SYSCFG_GetTIMBreakInputs(void)435 __STATIC_INLINE uint32_t LL_SYSCFG_GetTIMBreakInputs(void)
436 {
437 return (uint32_t)(READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL));
438 }
439
440 /**
441 * @brief Config PinMux
442 * @rmtoll SYSCFG_CFGR3 CLL LL_SYSCFG_ConfigPinMux\n
443 * @param mux_cfg This parameter can be a value of @ref SYSTEM_LL_PINMUX_CFG
444 * @retval None
445 */
LL_SYSCFG_ConfigPinMux(uint32_t mux_cfg)446 __STATIC_INLINE void LL_SYSCFG_ConfigPinMux(uint32_t mux_cfg)
447 {
448 MODIFY_REG(SYSCFG->CFGR3, (mux_cfg >> 16U), (mux_cfg & 0x0000FFFFU));
449 }
450
451 /**
452 * @brief Get PinMux configuration
453 * @rmtoll SYSCFG_CFGR3 CLL LL_SYSCFG_GetConfigPinMux\n
454 * @param LL_PINMUX_PACKx_PINy This parameter can be a value of @ref SYSTEM_LL_PINMUX_SOURCE
455 * @retval Returned value can be one of SYSTEM_LL_PINMUX_CFG defines
456 */
LL_SYSCFG_GetConfigPinMux(uint32_t LL_PINMUX_PACKx_PINy)457 __STATIC_INLINE uint32_t LL_SYSCFG_GetConfigPinMux(uint32_t LL_PINMUX_PACKx_PINy)
458 {
459 return (uint32_t)(READ_BIT(SYSCFG->CFGR3, LL_PINMUX_PACKx_PINy) | (LL_PINMUX_PACKx_PINy << 16U));
460 }
461
462 #if defined(SYSCFG_ITLINE0_SR_EWDG)
463 /**
464 * @brief Check if Window watchdog interrupt occurred or not.
465 * @rmtoll SYSCFG_ITLINE0 SR_EWDG LL_SYSCFG_IsActiveFlag_WWDG
466 * @retval State of bit (1 or 0).
467 */
LL_SYSCFG_IsActiveFlag_WWDG(void)468 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_WWDG(void)
469 {
470 return ((READ_BIT(SYSCFG->IT_LINE_SR[0], SYSCFG_ITLINE0_SR_EWDG) == (SYSCFG_ITLINE0_SR_EWDG)) ? 1UL : 0UL);
471 }
472 #endif /* SYSCFG_ITLINE0_SR_EWDG */
473
474 #if defined(SYSCFG_ITLINE2_SR_RTC)
475 /**
476 * @brief Check if RTC interrupt occurred or not (EXTI line 19).
477 * @rmtoll SYSCFG_ITLINE2 SR_RTC LL_SYSCFG_IsActiveFlag_RTC
478 * @retval State of bit (1 or 0).
479 */
LL_SYSCFG_IsActiveFlag_RTC(void)480 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_RTC(void)
481 {
482 return ((READ_BIT(SYSCFG->IT_LINE_SR[2], SYSCFG_ITLINE2_SR_RTC) == (SYSCFG_ITLINE2_SR_RTC)) ? 1UL : 0UL);
483 }
484 #endif /* SYSCFG_ITLINE2_SR_RTC */
485
486 #if defined(SYSCFG_ITLINE3_SR_FLASH_ITF)
487 /**
488 * @brief Check if Flash interface interrupt occurred or not.
489 * @rmtoll SYSCFG_ITLINE3 SR_FLASH_ITF LL_SYSCFG_IsActiveFlag_FLASH_ITF
490 * @retval State of bit (1 or 0).
491 */
LL_SYSCFG_IsActiveFlag_FLASH_ITF(void)492 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_FLASH_ITF(void)
493 {
494 return ((READ_BIT(SYSCFG->IT_LINE_SR[3], SYSCFG_ITLINE3_SR_FLASH_ITF) == (SYSCFG_ITLINE3_SR_FLASH_ITF)) ? 1UL : 0UL);
495 }
496 #endif /* SYSCFG_ITLINE3_SR_FLASH_ITF */
497
498
499 #if defined(SYSCFG_ITLINE4_SR_CLK_CTRL)
500 /**
501 * @brief Check if Reset and clock control interrupt occurred or not.
502 * @rmtoll SYSCFG_ITLINE4 SR_CLK_CTRL LL_SYSCFG_IsActiveFlag_CLK_CTRL
503 * @retval State of bit (1 or 0).
504 */
LL_SYSCFG_IsActiveFlag_CLK_CTRL(void)505 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_CLK_CTRL(void)
506 {
507 return ((READ_BIT(SYSCFG->IT_LINE_SR[4], SYSCFG_ITLINE4_SR_CLK_CTRL) == (SYSCFG_ITLINE4_SR_CLK_CTRL)) ? 1UL : 0UL);
508 }
509 #endif /* SYSCFG_ITLINE4_SR_CLK_CTRL */
510
511 #if defined(SYSCFG_ITLINE5_SR_EXTI0)
512 /**
513 * @brief Check if EXTI line 0 interrupt occurred or not.
514 * @rmtoll SYSCFG_ITLINE5 SR_EXTI0 LL_SYSCFG_IsActiveFlag_EXTI0
515 * @retval State of bit (1 or 0).
516 */
LL_SYSCFG_IsActiveFlag_EXTI0(void)517 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI0(void)
518 {
519 return ((READ_BIT(SYSCFG->IT_LINE_SR[5], SYSCFG_ITLINE5_SR_EXTI0) == (SYSCFG_ITLINE5_SR_EXTI0)) ? 1UL : 0UL);
520 }
521 #endif /* SYSCFG_ITLINE5_SR_EXTI0 */
522
523 #if defined(SYSCFG_ITLINE5_SR_EXTI1)
524 /**
525 * @brief Check if EXTI line 1 interrupt occurred or not.
526 * @rmtoll SYSCFG_ITLINE5 SR_EXTI1 LL_SYSCFG_IsActiveFlag_EXTI1
527 * @retval State of bit (1 or 0).
528 */
LL_SYSCFG_IsActiveFlag_EXTI1(void)529 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI1(void)
530 {
531 return ((READ_BIT(SYSCFG->IT_LINE_SR[5], SYSCFG_ITLINE5_SR_EXTI1) == (SYSCFG_ITLINE5_SR_EXTI1)) ? 1UL : 0UL);
532 }
533 #endif /* SYSCFG_ITLINE5_SR_EXTI1 */
534
535 #if defined(SYSCFG_ITLINE6_SR_EXTI2)
536 /**
537 * @brief Check if EXTI line 2 interrupt occurred or not.
538 * @rmtoll SYSCFG_ITLINE6 SR_EXTI2 LL_SYSCFG_IsActiveFlag_EXTI2
539 * @retval State of bit (1 or 0).
540 */
LL_SYSCFG_IsActiveFlag_EXTI2(void)541 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI2(void)
542 {
543 return ((READ_BIT(SYSCFG->IT_LINE_SR[6], SYSCFG_ITLINE6_SR_EXTI2) == (SYSCFG_ITLINE6_SR_EXTI2)) ? 1UL : 0UL);
544 }
545 #endif /* SYSCFG_ITLINE6_SR_EXTI2 */
546
547 #if defined(SYSCFG_ITLINE6_SR_EXTI3)
548 /**
549 * @brief Check if EXTI line 3 interrupt occurred or not.
550 * @rmtoll SYSCFG_ITLINE6 SR_EXTI3 LL_SYSCFG_IsActiveFlag_EXTI3
551 * @retval State of bit (1 or 0).
552 */
LL_SYSCFG_IsActiveFlag_EXTI3(void)553 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI3(void)
554 {
555 return ((READ_BIT(SYSCFG->IT_LINE_SR[6], SYSCFG_ITLINE6_SR_EXTI3) == (SYSCFG_ITLINE6_SR_EXTI3)) ? 1UL : 0UL);
556 }
557 #endif /* SYSCFG_ITLINE6_SR_EXTI3 */
558
559 #if defined(SYSCFG_ITLINE7_SR_EXTI4)
560 /**
561 * @brief Check if EXTI line 4 interrupt occurred or not.
562 * @rmtoll SYSCFG_ITLINE7 SR_EXTI4 LL_SYSCFG_IsActiveFlag_EXTI4
563 * @retval State of bit (1 or 0).
564 */
LL_SYSCFG_IsActiveFlag_EXTI4(void)565 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI4(void)
566 {
567 return ((READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI4) == (SYSCFG_ITLINE7_SR_EXTI4)) ? 1UL : 0UL);
568 }
569 #endif /* SYSCFG_ITLINE7_SR_EXTI4 */
570
571 #if defined(SYSCFG_ITLINE7_SR_EXTI5)
572 /**
573 * @brief Check if EXTI line 5 interrupt occurred or not.
574 * @rmtoll SYSCFG_ITLINE7 SR_EXTI5 LL_SYSCFG_IsActiveFlag_EXTI5
575 * @retval State of bit (1 or 0).
576 */
LL_SYSCFG_IsActiveFlag_EXTI5(void)577 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI5(void)
578 {
579 return ((READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI5) == (SYSCFG_ITLINE7_SR_EXTI5)) ? 1UL : 0UL);
580 }
581 #endif /* SYSCFG_ITLINE7_SR_EXTI5 */
582
583 #if defined(SYSCFG_ITLINE7_SR_EXTI6)
584 /**
585 * @brief Check if EXTI line 6 interrupt occurred or not.
586 * @rmtoll SYSCFG_ITLINE7 SR_EXTI6 LL_SYSCFG_IsActiveFlag_EXTI6
587 * @retval State of bit (1 or 0).
588 */
LL_SYSCFG_IsActiveFlag_EXTI6(void)589 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI6(void)
590 {
591 return ((READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI6) == (SYSCFG_ITLINE7_SR_EXTI6)) ? 1UL : 0UL);
592 }
593 #endif /* SYSCFG_ITLINE7_SR_EXTI6 */
594
595 #if defined(SYSCFG_ITLINE7_SR_EXTI7)
596 /**
597 * @brief Check if EXTI line 7 interrupt occurred or not.
598 * @rmtoll SYSCFG_ITLINE7 SR_EXTI7 LL_SYSCFG_IsActiveFlag_EXTI7
599 * @retval State of bit (1 or 0).
600 */
LL_SYSCFG_IsActiveFlag_EXTI7(void)601 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI7(void)
602 {
603 return ((READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI7) == (SYSCFG_ITLINE7_SR_EXTI7)) ? 1UL : 0UL);
604 }
605 #endif /* SYSCFG_ITLINE7_SR_EXTI7 */
606
607 #if defined(SYSCFG_ITLINE7_SR_EXTI8)
608 /**
609 * @brief Check if EXTI line 8 interrupt occurred or not.
610 * @rmtoll SYSCFG_ITLINE7 SR_EXTI8 LL_SYSCFG_IsActiveFlag_EXTI8
611 * @retval State of bit (1 or 0).
612 */
LL_SYSCFG_IsActiveFlag_EXTI8(void)613 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI8(void)
614 {
615 return ((READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI8) == (SYSCFG_ITLINE7_SR_EXTI8)) ? 1UL : 0UL);
616 }
617 #endif /* SYSCFG_ITLINE7_SR_EXTI8 */
618
619 #if defined(SYSCFG_ITLINE7_SR_EXTI9)
620 /**
621 * @brief Check if EXTI line 9 interrupt occurred or not.
622 * @rmtoll SYSCFG_ITLINE7 SR_EXTI9 LL_SYSCFG_IsActiveFlag_EXTI9
623 * @retval State of bit (1 or 0).
624 */
LL_SYSCFG_IsActiveFlag_EXTI9(void)625 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI9(void)
626 {
627 return ((READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI9) == (SYSCFG_ITLINE7_SR_EXTI9)) ? 1UL : 0UL);
628 }
629 #endif /* SYSCFG_ITLINE7_SR_EXTI9 */
630
631 #if defined(SYSCFG_ITLINE7_SR_EXTI10)
632 /**
633 * @brief Check if EXTI line 10 interrupt occurred or not.
634 * @rmtoll SYSCFG_ITLINE7 SR_EXTI10 LL_SYSCFG_IsActiveFlag_EXTI10
635 * @retval State of bit (1 or 0).
636 */
LL_SYSCFG_IsActiveFlag_EXTI10(void)637 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI10(void)
638 {
639 return ((READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI10) == (SYSCFG_ITLINE7_SR_EXTI10)) ? 1UL : 0UL);
640 }
641 #endif /* SYSCFG_ITLINE7_SR_EXTI10 */
642
643 #if defined(SYSCFG_ITLINE7_SR_EXTI11)
644 /**
645 * @brief Check if EXTI line 11 interrupt occurred or not.
646 * @rmtoll SYSCFG_ITLINE7 SR_EXTI11 LL_SYSCFG_IsActiveFlag_EXTI11
647 * @retval State of bit (1 or 0).
648 */
LL_SYSCFG_IsActiveFlag_EXTI11(void)649 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI11(void)
650 {
651 return ((READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI11) == (SYSCFG_ITLINE7_SR_EXTI11)) ? 1UL : 0UL);
652 }
653 #endif /* SYSCFG_ITLINE7_SR_EXTI11 */
654
655 #if defined(SYSCFG_ITLINE7_SR_EXTI12)
656 /**
657 * @brief Check if EXTI line 12 interrupt occurred or not.
658 * @rmtoll SYSCFG_ITLINE7 SR_EXTI12 LL_SYSCFG_IsActiveFlag_EXTI12
659 * @retval State of bit (1 or 0).
660 */
LL_SYSCFG_IsActiveFlag_EXTI12(void)661 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI12(void)
662 {
663 return ((READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI12) == (SYSCFG_ITLINE7_SR_EXTI12)) ? 1UL : 0UL);
664 }
665 #endif /* SYSCFG_ITLINE7_SR_EXTI12 */
666
667 #if defined(SYSCFG_ITLINE7_SR_EXTI13)
668 /**
669 * @brief Check if EXTI line 13 interrupt occurred or not.
670 * @rmtoll SYSCFG_ITLINE7 SR_EXTI13 LL_SYSCFG_IsActiveFlag_EXTI13
671 * @retval State of bit (1 or 0).
672 */
LL_SYSCFG_IsActiveFlag_EXTI13(void)673 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI13(void)
674 {
675 return ((READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI13) == (SYSCFG_ITLINE7_SR_EXTI13)) ? 1UL : 0UL);
676 }
677 #endif /* SYSCFG_ITLINE7_SR_EXTI13 */
678
679 #if defined(SYSCFG_ITLINE7_SR_EXTI14)
680 /**
681 * @brief Check if EXTI line 14 interrupt occurred or not.
682 * @rmtoll SYSCFG_ITLINE7 SR_EXTI14 LL_SYSCFG_IsActiveFlag_EXTI14
683 * @retval State of bit (1 or 0).
684 */
LL_SYSCFG_IsActiveFlag_EXTI14(void)685 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI14(void)
686 {
687 return ((READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI14) == (SYSCFG_ITLINE7_SR_EXTI14)) ? 1UL : 0UL);
688 }
689 #endif /* SYSCFG_ITLINE7_SR_EXTI14 */
690
691 #if defined(SYSCFG_ITLINE7_SR_EXTI15)
692 /**
693 * @brief Check if EXTI line 15 interrupt occurred or not.
694 * @rmtoll SYSCFG_ITLINE7 SR_EXTI15 LL_SYSCFG_IsActiveFlag_EXTI15
695 * @retval State of bit (1 or 0).
696 */
LL_SYSCFG_IsActiveFlag_EXTI15(void)697 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_EXTI15(void)
698 {
699 return ((READ_BIT(SYSCFG->IT_LINE_SR[7], SYSCFG_ITLINE7_SR_EXTI15) == (SYSCFG_ITLINE7_SR_EXTI15)) ? 1UL : 0UL);
700 }
701 #endif /* SYSCFG_ITLINE7_SR_EXTI15 */
702
703
704 #if defined(SYSCFG_ITLINE9_SR_DMA1_CH1)
705 /**
706 * @brief Check if DMA1 channel 1 interrupt occurred or not.
707 * @rmtoll SYSCFG_ITLINE9 SR_DMA1_CH1 LL_SYSCFG_IsActiveFlag_DMA1_CH1
708 * @retval State of bit (1 or 0).
709 */
LL_SYSCFG_IsActiveFlag_DMA1_CH1(void)710 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA1_CH1(void)
711 {
712 return ((READ_BIT(SYSCFG->IT_LINE_SR[9], SYSCFG_ITLINE9_SR_DMA1_CH1) == (SYSCFG_ITLINE9_SR_DMA1_CH1)) ? 1UL : 0UL);
713 }
714 #endif /* SYSCFG_ITLINE9_SR_DMA1_CH1 */
715
716 #if defined(SYSCFG_ITLINE10_SR_DMA1_CH2)
717 /**
718 * @brief Check if DMA1 channel 2 interrupt occurred or not.
719 * @rmtoll SYSCFG_ITLINE10 SR_DMA1_CH2 LL_SYSCFG_IsActiveFlag_DMA1_CH2
720 * @retval State of bit (1 or 0).
721 */
LL_SYSCFG_IsActiveFlag_DMA1_CH2(void)722 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA1_CH2(void)
723 {
724 return ((READ_BIT(SYSCFG->IT_LINE_SR[10], SYSCFG_ITLINE10_SR_DMA1_CH2) == (SYSCFG_ITLINE10_SR_DMA1_CH2)) ? 1UL : 0UL);
725 }
726 #endif /* SYSCFG_ITLINE10_SR_DMA1_CH2 */
727
728 #if defined(SYSCFG_ITLINE10_SR_DMA1_CH3)
729 /**
730 * @brief Check if DMA1 channel 3 interrupt occurred or not.
731 * @rmtoll SYSCFG_ITLINE10 SR_DMA1_CH3 LL_SYSCFG_IsActiveFlag_DMA1_CH3
732 * @retval State of bit (1 or 0).
733 */
LL_SYSCFG_IsActiveFlag_DMA1_CH3(void)734 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMA1_CH3(void)
735 {
736 return ((READ_BIT(SYSCFG->IT_LINE_SR[10], SYSCFG_ITLINE10_SR_DMA1_CH3) == (SYSCFG_ITLINE10_SR_DMA1_CH3)) ? 1UL : 0UL);
737 }
738 #endif /* SYSCFG_ITLINE10_SR_DMA1_CH3 */
739
740
741 #if defined(SYSCFG_ITLINE11_SR_DMAMUX1)
742 /**
743 * @brief Check if DMAMUX interrupt occurred or not.
744 * @rmtoll SYSCFG_ITLINE11 SR_DMAMUX1 LL_SYSCFG_IsActiveFlag_DMAMUX
745 * @retval State of bit (1 or 0).
746 */
LL_SYSCFG_IsActiveFlag_DMAMUX(void)747 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_DMAMUX(void)
748 {
749 return ((READ_BIT(SYSCFG->IT_LINE_SR[11], SYSCFG_ITLINE11_SR_DMAMUX1) == (SYSCFG_ITLINE11_SR_DMAMUX1)) ? 1UL : 0UL);
750 }
751 #endif /* SYSCFG_ITLINE11_SR_DMAMUX */
752
753 #if defined(SYSCFG_ITLINE12_SR_ADC)
754 /**
755 * @brief Check if ADC interrupt occurred or not.
756 * @rmtoll SYSCFG_ITLINE12 SR_ADC LL_SYSCFG_IsActiveFlag_ADC
757 * @retval State of bit (1 or 0).
758 */
LL_SYSCFG_IsActiveFlag_ADC(void)759 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_ADC(void)
760 {
761 return ((READ_BIT(SYSCFG->IT_LINE_SR[12], SYSCFG_ITLINE12_SR_ADC) == (SYSCFG_ITLINE12_SR_ADC)) ? 1UL : 0UL);
762 }
763 #endif /* SYSCFG_ITLINE12_SR_ADC */
764
765 #if defined(SYSCFG_ITLINE13_SR_TIM1_BRK)
766 /**
767 * @brief Check if Timer 1 break interrupt occurred or not.
768 * @rmtoll SYSCFG_ITLINE13 SR_TIM1_BRK LL_SYSCFG_IsActiveFlag_TIM1_BRK
769 * @retval State of bit (1 or 0).
770 */
LL_SYSCFG_IsActiveFlag_TIM1_BRK(void)771 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM1_BRK(void)
772 {
773 return ((READ_BIT(SYSCFG->IT_LINE_SR[13], SYSCFG_ITLINE13_SR_TIM1_BRK) == (SYSCFG_ITLINE13_SR_TIM1_BRK)) ? 1UL : 0UL);
774 }
775 #endif /* SYSCFG_ITLINE13_SR_TIM1_BRK */
776
777 #if defined(SYSCFG_ITLINE13_SR_TIM1_UPD)
778 /**
779 * @brief Check if Timer 1 update interrupt occurred or not.
780 * @rmtoll SYSCFG_ITLINE13 SR_TIM1_UPD LL_SYSCFG_IsActiveFlag_TIM1_UPD
781 * @retval State of bit (1 or 0).
782 */
LL_SYSCFG_IsActiveFlag_TIM1_UPD(void)783 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM1_UPD(void)
784 {
785 return ((READ_BIT(SYSCFG->IT_LINE_SR[13], SYSCFG_ITLINE13_SR_TIM1_UPD) == (SYSCFG_ITLINE13_SR_TIM1_UPD)) ? 1UL : 0UL);
786 }
787 #endif /* SYSCFG_ITLINE13_SR_TIM1_UPD */
788
789 #if defined(SYSCFG_ITLINE13_SR_TIM1_TRG)
790 /**
791 * @brief Check if Timer 1 trigger interrupt occurred or not.
792 * @rmtoll SYSCFG_ITLINE13 SR_TIM1_TRG LL_SYSCFG_IsActiveFlag_TIM1_TRG
793 * @retval State of bit (1 or 0).
794 */
LL_SYSCFG_IsActiveFlag_TIM1_TRG(void)795 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM1_TRG(void)
796 {
797 return ((READ_BIT(SYSCFG->IT_LINE_SR[13], SYSCFG_ITLINE13_SR_TIM1_TRG) == (SYSCFG_ITLINE13_SR_TIM1_TRG)) ? 1UL : 0UL);
798 }
799 #endif /* SYSCFG_ITLINE13_SR_TIM1_TRG */
800
801 #if defined(SYSCFG_ITLINE13_SR_TIM1_CCU)
802 /**
803 * @brief Check if Timer 1 commutation interrupt occurred or not.
804 * @rmtoll SYSCFG_ITLINE13 SR_TIM1_CCU LL_SYSCFG_IsActiveFlag_TIM1_CCU
805 * @retval State of bit (1 or 0).
806 */
LL_SYSCFG_IsActiveFlag_TIM1_CCU(void)807 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM1_CCU(void)
808 {
809 return ((READ_BIT(SYSCFG->IT_LINE_SR[13], SYSCFG_ITLINE13_SR_TIM1_CCU) == (SYSCFG_ITLINE13_SR_TIM1_CCU)) ? 1UL : 0UL);
810 }
811 #endif /* SYSCFG_ITLINE13_SR_TIM1_CCU */
812
813 #if defined(SYSCFG_ITLINE14_SR_TIM1_CC)
814 /**
815 * @brief Check if Timer 1 capture compare interrupt occurred or not.
816 * @rmtoll SYSCFG_ITLINE14 SR_TIM1_CC LL_SYSCFG_IsActiveFlag_TIM1_CC
817 * @retval State of bit (1 or 0).
818 */
LL_SYSCFG_IsActiveFlag_TIM1_CC(void)819 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM1_CC(void)
820 {
821 return ((READ_BIT(SYSCFG->IT_LINE_SR[14], SYSCFG_ITLINE14_SR_TIM1_CC) == (SYSCFG_ITLINE14_SR_TIM1_CC)) ? 1UL : 0UL);
822 }
823 #endif /* SYSCFG_ITLINE14_SR_TIM1_CC */
824
825
826 #if defined(SYSCFG_ITLINE16_SR_TIM3_GLB)
827 /**
828 * @brief Check if Timer 3 interrupt occurred or not.
829 * @rmtoll SYSCFG_ITLINE16 SR_TIM3_GLB LL_SYSCFG_IsActiveFlag_TIM3
830 * @retval State of bit (1 or 0).
831 */
LL_SYSCFG_IsActiveFlag_TIM3(void)832 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM3(void)
833 {
834 return ((READ_BIT(SYSCFG->IT_LINE_SR[16], SYSCFG_ITLINE16_SR_TIM3_GLB) == (SYSCFG_ITLINE16_SR_TIM3_GLB)) ? 1UL : 0UL);
835 }
836 #endif /* SYSCFG_ITLINE16_SR_TIM3_GLB */
837
838 #if defined(SYSCFG_ITLINE19_SR_TIM14_GLB)
839 /**
840 * @brief Check if Timer 14 interrupt occurred or not.
841 * @rmtoll SYSCFG_ITLINE19 SR_TIM14_GLB LL_SYSCFG_IsActiveFlag_TIM14
842 * @retval State of bit (1 or 0).
843 */
LL_SYSCFG_IsActiveFlag_TIM14(void)844 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM14(void)
845 {
846 return ((READ_BIT(SYSCFG->IT_LINE_SR[19], SYSCFG_ITLINE19_SR_TIM14_GLB) == (SYSCFG_ITLINE19_SR_TIM14_GLB)) ? 1UL : 0UL);
847 }
848 #endif /* SYSCFG_ITLINE19_SR_TIM14_GLB */
849
850 #if defined(SYSCFG_ITLINE21_SR_TIM16_GLB)
851 /**
852 * @brief Check if Timer 16 interrupt occurred or not.
853 * @rmtoll SYSCFG_ITLINE21 SR_TIM16_GLB LL_SYSCFG_IsActiveFlag_TIM16
854 * @retval State of bit (1 or 0).
855 */
LL_SYSCFG_IsActiveFlag_TIM16(void)856 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM16(void)
857 {
858 return ((READ_BIT(SYSCFG->IT_LINE_SR[21], SYSCFG_ITLINE21_SR_TIM16_GLB) == (SYSCFG_ITLINE21_SR_TIM16_GLB)) ? 1UL : 0UL);
859 }
860 #endif /* SYSCFG_ITLINE21_SR_TIM16_GLB */
861
862 #if defined(SYSCFG_ITLINE22_SR_TIM17_GLB)
863 /**
864 * @brief Check if Timer 17 interrupt occurred or not.
865 * @rmtoll SYSCFG_ITLINE22 SR_TIM17_GLB LL_SYSCFG_IsActiveFlag_TIM17
866 * @retval State of bit (1 or 0).
867 */
LL_SYSCFG_IsActiveFlag_TIM17(void)868 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_TIM17(void)
869 {
870 return ((READ_BIT(SYSCFG->IT_LINE_SR[22], SYSCFG_ITLINE22_SR_TIM17_GLB) == (SYSCFG_ITLINE22_SR_TIM17_GLB)) ? 1UL : 0UL);
871 }
872 #endif /* SYSCFG_ITLINE22_SR_TIM17_GLB */
873
874 #if defined(SYSCFG_ITLINE23_SR_I2C1_GLB)
875 /**
876 * @brief Check if I2C1 interrupt occurred or not, combined with EXTI line 23.
877 * @rmtoll SYSCFG_ITLINE23 SR_I2C1_GLB LL_SYSCFG_IsActiveFlag_I2C1
878 * @retval State of bit (1 or 0).
879 */
LL_SYSCFG_IsActiveFlag_I2C1(void)880 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_I2C1(void)
881 {
882 return ((READ_BIT(SYSCFG->IT_LINE_SR[23], SYSCFG_ITLINE23_SR_I2C1_GLB) == (SYSCFG_ITLINE23_SR_I2C1_GLB)) ? 1UL : 0UL);
883 }
884 #endif /* SYSCFG_ITLINE23_SR_I2C1_GLB */
885
886 #if defined(SYSCFG_ITLINE25_SR_SPI1)
887 /**
888 * @brief Check if SPI1 interrupt occurred or not.
889 * @rmtoll SYSCFG_ITLINE25 SR_SPI1 LL_SYSCFG_IsActiveFlag_SPI1
890 * @retval State of bit (1 or 0).
891 */
LL_SYSCFG_IsActiveFlag_SPI1(void)892 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_SPI1(void)
893 {
894 return ((READ_BIT(SYSCFG->IT_LINE_SR[25], SYSCFG_ITLINE25_SR_SPI1) == (SYSCFG_ITLINE25_SR_SPI1)) ? 1UL : 0UL);
895 }
896 #endif /* SYSCFG_ITLINE25_SR_SPI1 */
897
898
899 #if defined(SYSCFG_ITLINE27_SR_USART1_GLB)
900 /**
901 * @brief Check if USART1 interrupt occurred or not, combined with EXTI line 25.
902 * @rmtoll SYSCFG_ITLINE27 SR_USART1_GLB LL_SYSCFG_IsActiveFlag_USART1
903 * @retval State of bit (1 or 0).
904 */
LL_SYSCFG_IsActiveFlag_USART1(void)905 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USART1(void)
906 {
907 return ((READ_BIT(SYSCFG->IT_LINE_SR[27], SYSCFG_ITLINE27_SR_USART1_GLB) == (SYSCFG_ITLINE27_SR_USART1_GLB)) ? 1UL : 0UL);
908 }
909 #endif /* SYSCFG_ITLINE27_SR_USART1_GLB */
910
911 #if defined(SYSCFG_ITLINE28_SR_USART2_GLB)
912 /**
913 * @brief Check if USART2 interrupt occurred or not, combined with EXTI line 26.
914 * @rmtoll SYSCFG_ITLINE28 SR_USART2_GLB LL_SYSCFG_IsActiveFlag_USART2
915 * @retval State of bit (1 or 0).
916 */
LL_SYSCFG_IsActiveFlag_USART2(void)917 __STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_USART2(void)
918 {
919 return ((READ_BIT(SYSCFG->IT_LINE_SR[28], SYSCFG_ITLINE28_SR_USART2_GLB) == (SYSCFG_ITLINE28_SR_USART2_GLB)) ? 1UL : 0UL);
920 }
921 #endif /* SYSCFG_ITLINE28_SR_USART2_GLB */
922
923 /**
924 * @}
925 */
926
927 /** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU
928 * @{
929 */
930
931 /**
932 * @brief Return the device identifier
933 * @rmtoll DBG_IDCODE DEV_ID LL_DBGMCU_GetDeviceID
934 * @retval Values between Min_Data=0x00 and Max_Data=0xFFF
935 */
LL_DBGMCU_GetDeviceID(void)936 __STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void)
937 {
938 return (uint32_t)(READ_BIT(DBG->IDCODE, DBG_IDCODE_DEV_ID));
939 }
940
941 /**
942 * @brief Return the device revision identifier
943 * @note This field indicates the revision of the device.
944 * @rmtoll DBG_IDCODE REV_ID LL_DBGMCU_GetRevisionID
945 * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF
946 */
LL_DBGMCU_GetRevisionID(void)947 __STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void)
948 {
949 return (uint32_t)(READ_BIT(DBG->IDCODE, DBG_IDCODE_REV_ID) >> DBG_IDCODE_REV_ID_Pos);
950 }
951
952 /**
953 * @brief Enable the Debug Module during STOP mode
954 * @rmtoll DBG_CR DBG_STOP LL_DBGMCU_EnableDBGStopMode
955 * @retval None
956 */
LL_DBGMCU_EnableDBGStopMode(void)957 __STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void)
958 {
959 SET_BIT(DBG->CR, DBG_CR_DBG_STOP);
960 }
961
962 /**
963 * @brief Disable the Debug Module during STOP mode
964 * @rmtoll DBG_CR DBG_STOP LL_DBGMCU_DisableDBGStopMode
965 * @retval None
966 */
LL_DBGMCU_DisableDBGStopMode(void)967 __STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void)
968 {
969 CLEAR_BIT(DBG->CR, DBG_CR_DBG_STOP);
970 }
971
972 /**
973 * @brief Enable the Debug Module during STANDBY mode
974 * @rmtoll DBG_CR DBG_STANDBY LL_DBGMCU_EnableDBGStandbyMode
975 * @retval None
976 */
LL_DBGMCU_EnableDBGStandbyMode(void)977 __STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void)
978 {
979 SET_BIT(DBG->CR, DBG_CR_DBG_STANDBY);
980 }
981
982 /**
983 * @brief Disable the Debug Module during STANDBY mode
984 * @rmtoll DBG_CR DBG_STANDBY LL_DBGMCU_DisableDBGStandbyMode
985 * @retval None
986 */
LL_DBGMCU_DisableDBGStandbyMode(void)987 __STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void)
988 {
989 CLEAR_BIT(DBG->CR, DBG_CR_DBG_STANDBY);
990 }
991
992 /**
993 * @brief Freeze APB1 peripherals (group1 peripherals)
994 * @rmtoll DBG_APB_FZ1 DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
995 * DBG_APB_FZ1 DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
996 * DBG_APB_FZ1 DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
997 * DBG_APB_FZ1 DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
998 * DBG_APB_FZ1 DBG_I2C1_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
999 * @param Periphs This parameter can be a combination of the following values:
1000 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP
1001 * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
1002 * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
1003 * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
1004 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
1005 *
1006 * @retval None
1007 */
LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)1008 __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)
1009 {
1010 SET_BIT(DBG->APBFZ1, Periphs);
1011 }
1012
1013 /**
1014 * @brief Unfreeze APB1 peripherals (group1 peripherals)
1015 * @rmtoll DBG_APB_FZ1 DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1016 * DBG_APB_FZ1 DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1017 * DBG_APB_FZ1 DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1018 * DBG_APB_FZ1 DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1019 * DBG_APB_FZ1 DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
1020 * @param Periphs This parameter can be a combination of the following values:
1021 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP
1022 * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
1023 * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
1024 * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
1025 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
1026 *
1027 * (*) value not defined in all devices
1028 * @retval None
1029 */
LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)1030 __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)
1031 {
1032 CLEAR_BIT(DBG->APBFZ1, Periphs);
1033 }
1034
1035 /**
1036 * @brief Freeze APB2 peripherals
1037 * @rmtoll DBG_APB_FZ2 DBG_TIM1_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
1038 * DBG_APB_FZ2 DBG_TIM14_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
1039 * DBG_APB_FZ2 DBG_TIM16_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
1040 * DBG_APB_FZ2 DBG_TIM17_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph
1041 * @param Periphs This parameter can be a combination of the following values:
1042 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
1043 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM14_STOP
1044 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP
1045 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP
1046 *
1047 * @retval None
1048 */
LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs)1049 __STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs)
1050 {
1051 SET_BIT(DBG->APBFZ2, Periphs);
1052 }
1053
1054 /**
1055 * @brief Unfreeze APB2 peripherals
1056 * @rmtoll DBG_APB_FZ2 DBG_TIM1_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
1057 * DBG_APB_FZ2 DBG_TIM14_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
1058 * DBG_APB_FZ2 DBG_TIM16_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
1059 * DBG_APB_FZ2 DBG_TIM17_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph
1060 * @param Periphs This parameter can be a combination of the following values:
1061 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
1062 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM14_STOP
1063 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP
1064 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP
1065 *
1066 * @retval None
1067 */
LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs)1068 __STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs)
1069 {
1070 CLEAR_BIT(DBG->APBFZ2, Periphs);
1071 }
1072 /**
1073 * @}
1074 */
1075
1076
1077 /** @defgroup SYSTEM_LL_EF_FLASH FLASH
1078 * @{
1079 */
1080
1081 /**
1082 * @brief Set FLASH Latency
1083 * @rmtoll FLASH_ACR FLASH_ACR_LATENCY LL_FLASH_SetLatency
1084 * @param Latency This parameter can be one of the following values:
1085 * @arg @ref LL_FLASH_LATENCY_0
1086 * @arg @ref LL_FLASH_LATENCY_1
1087 * @retval None
1088 */
LL_FLASH_SetLatency(uint32_t Latency)1089 __STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency)
1090 {
1091 MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency);
1092 }
1093
1094 /**
1095 * @brief Get FLASH Latency
1096 * @rmtoll FLASH_ACR FLASH_ACR_LATENCY LL_FLASH_GetLatency
1097 * @retval Returned value can be one of the following values:
1098 * @arg @ref LL_FLASH_LATENCY_0
1099 * @arg @ref LL_FLASH_LATENCY_1
1100 */
LL_FLASH_GetLatency(void)1101 __STATIC_INLINE uint32_t LL_FLASH_GetLatency(void)
1102 {
1103 return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY));
1104 }
1105
1106 /**
1107 * @brief Enable Prefetch
1108 * @rmtoll FLASH_ACR FLASH_ACR_PRFTEN LL_FLASH_EnablePrefetch
1109 * @retval None
1110 */
LL_FLASH_EnablePrefetch(void)1111 __STATIC_INLINE void LL_FLASH_EnablePrefetch(void)
1112 {
1113 SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN);
1114 }
1115
1116 /**
1117 * @brief Disable Prefetch
1118 * @rmtoll FLASH_ACR FLASH_ACR_PRFTEN LL_FLASH_DisablePrefetch
1119 * @retval None
1120 */
LL_FLASH_DisablePrefetch(void)1121 __STATIC_INLINE void LL_FLASH_DisablePrefetch(void)
1122 {
1123 CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTEN);
1124 }
1125
1126 /**
1127 * @brief Check if Prefetch buffer is enabled
1128 * @rmtoll FLASH_ACR FLASH_ACR_PRFTEN LL_FLASH_IsPrefetchEnabled
1129 * @retval State of bit (1 or 0).
1130 */
LL_FLASH_IsPrefetchEnabled(void)1131 __STATIC_INLINE uint32_t LL_FLASH_IsPrefetchEnabled(void)
1132 {
1133 return ((READ_BIT(FLASH->ACR, FLASH_ACR_PRFTEN) == (FLASH_ACR_PRFTEN)) ? 1UL : 0UL);
1134 }
1135
1136 /**
1137 * @brief Enable Instruction cache
1138 * @rmtoll FLASH_ACR FLASH_ACR_ICEN LL_FLASH_EnableInstCache
1139 * @retval None
1140 */
LL_FLASH_EnableInstCache(void)1141 __STATIC_INLINE void LL_FLASH_EnableInstCache(void)
1142 {
1143 SET_BIT(FLASH->ACR, FLASH_ACR_ICEN);
1144 }
1145
1146 /**
1147 * @brief Disable Instruction cache
1148 * @rmtoll FLASH_ACR FLASH_ACR_ICEN LL_FLASH_DisableInstCache
1149 * @retval None
1150 */
LL_FLASH_DisableInstCache(void)1151 __STATIC_INLINE void LL_FLASH_DisableInstCache(void)
1152 {
1153 CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICEN);
1154 }
1155
1156 /**
1157 * @brief Enable Instruction cache reset
1158 * @note bit can be written only when the instruction cache is disabled
1159 * @rmtoll FLASH_ACR FLASH_ACR_ICRST LL_FLASH_EnableInstCacheReset
1160 * @retval None
1161 */
LL_FLASH_EnableInstCacheReset(void)1162 __STATIC_INLINE void LL_FLASH_EnableInstCacheReset(void)
1163 {
1164 SET_BIT(FLASH->ACR, FLASH_ACR_ICRST);
1165 }
1166
1167 /**
1168 * @brief Disable Instruction cache reset
1169 * @rmtoll FLASH_ACR FLASH_ACR_ICRST LL_FLASH_DisableInstCacheReset
1170 * @retval None
1171 */
LL_FLASH_DisableInstCacheReset(void)1172 __STATIC_INLINE void LL_FLASH_DisableInstCacheReset(void)
1173 {
1174 CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICRST);
1175 }
1176
1177 /**
1178 * @}
1179 */
1180
1181 /**
1182 * @}
1183 */
1184
1185 /**
1186 * @}
1187 */
1188
1189 #endif /* defined (FLASH) || defined (SYSCFG) || defined (DBG) */
1190
1191 /**
1192 * @}
1193 */
1194
1195 #ifdef __cplusplus
1196 }
1197 #endif
1198
1199 #endif /* STM32C0xx_LL_SYSTEM_H */
1200
