1 /** 2 ****************************************************************************** 3 * @file shci.h 4 * @author MCD Application Team 5 * @brief HCI command for the system channel 6 ****************************************************************************** 7 * @attention 8 * 9 * Copyright (c) 2018-2021 STMicroelectronics. 10 * All rights reserved. 11 * 12 * This software is licensed under terms that can be found in the LICENSE file 13 * in the root directory of this software component. 14 * If no LICENSE file comes with this software, it is provided AS-IS. 15 * 16 ****************************************************************************** 17 */ 18 19 20 /* Define to prevent recursive inclusion -------------------------------------*/ 21 #ifndef __SHCI_H 22 #define __SHCI_H 23 24 #ifdef __cplusplus 25 extern "C" { 26 #endif 27 28 /* Includes ------------------------------------------------------------------*/ 29 #include "mbox_def.h" /* Requested to expose the MB_WirelessFwInfoTable_t structure */ 30 31 /* Exported types ------------------------------------------------------------*/ 32 33 /* SYSTEM EVENT */ 34 typedef enum 35 { 36 WIRELESS_FW_RUNNING = 0x00, 37 FUS_FW_RUNNING = 0x01, 38 } SHCI_SysEvt_Ready_Rsp_t; 39 40 /* ERROR CODES 41 * 42 * These error codes are detected on CPU2 side and are send back to the CPU1 via a system 43 * notification message. It is up to the application running on CPU1 to manage these errors 44 * 45 * These errors can be generated by all layers (low level driver, stack, framework infrastructure, etc..) 46 */ 47 typedef enum 48 { 49 ERR_BLE_INIT = 0, /* This event is currently not reported by the CPU2 */ 50 ERR_THREAD_LLD_FATAL_ERROR = 125, /* The LLD driver used on 802_15_4 detected a fatal error */ 51 ERR_THREAD_UNKNOWN_CMD = 126, /* The command send by the CPU1 to control the Thread stack is unknown */ 52 ERR_ZIGBEE_UNKNOWN_CMD = 200, /* The command send by the CPU1 to control the Zigbee stack is unknown */ 53 } SCHI_SystemErrCode_t; 54 55 #define SHCI_EVTCODE ( 0xFF ) 56 #define SHCI_SUB_EVT_CODE_BASE ( 0x9200 ) 57 58 /** 59 * THE ORDER SHALL NOT BE CHANGED TO GUARANTEE COMPATIBILITY WITH THE CPU1 DEFINITION 60 */ 61 typedef enum 62 { 63 SHCI_SUB_EVT_CODE_READY = SHCI_SUB_EVT_CODE_BASE, 64 SHCI_SUB_EVT_ERROR_NOTIF, 65 SHCI_SUB_EVT_BLE_NVM_RAM_UPDATE, 66 SHCI_SUB_EVT_THREAD_NVM_RAM_UPDATE, 67 SHCI_SUB_EVT_NVM_START_WRITE, 68 SHCI_SUB_EVT_NVM_END_WRITE, 69 SHCI_SUB_EVT_NVM_START_ERASE, 70 SHCI_SUB_EVT_NVM_END_ERASE, 71 SHCI_SUB_EVT_CODE_CONCURRENT_802154_EVT, 72 } SHCI_SUB_EVT_CODE_t; 73 74 /** 75 * SHCI_SUB_EVT_CODE_READY 76 * This notifies the CPU1 that the CPU2 is now ready to receive commands 77 * It reports as well which firmware is running on CPU2 : The wireless stack of the FUS (previously named RSS) 78 */ 79 typedef PACKED_STRUCT{ 80 SHCI_SysEvt_Ready_Rsp_t sysevt_ready_rsp; 81 } SHCI_C2_Ready_Evt_t; 82 83 /** 84 * SHCI_SUB_EVT_ERROR_NOTIF 85 * This reports to the CPU1 some error form the CPU2 86 */ 87 typedef PACKED_STRUCT{ 88 SCHI_SystemErrCode_t errorCode; 89 } SHCI_C2_ErrorNotif_Evt_t; 90 91 /** 92 * SHCI_SUB_EVT_BLE_NVM_RAM_UPDATE 93 * This notifies the CPU1 which part of the BLE NVM RAM has been updated so that only the modified 94 * section could be written in Flash/NVM 95 * StartAddress : Start address of the section that has been modified 96 * Size : Size (in bytes) of the section that has been modified 97 */ 98 typedef PACKED_STRUCT{ 99 uint32_t StartAddress; 100 uint32_t Size; 101 } SHCI_C2_BleNvmRamUpdate_Evt_t; 102 103 /** 104 * SHCI_SUB_EVT_THREAD_NVM_RAM_UPDATE 105 * This notifies the CPU1 which part of the OT NVM RAM has been updated so that only the modified 106 * section could be written in Flash/NVM 107 * StartAddress : Start address of the section that has been modified 108 * Size : Size (in bytes) of the section that has been modified 109 */ 110 typedef PACKED_STRUCT{ 111 uint32_t StartAddress; 112 uint32_t Size; 113 } SHCI_C2_ThreadNvmRamUpdate_Evt_t; 114 115 /** 116 * SHCI_SUB_EVT_NVM_START_WRITE 117 * This notifies the CPU1 that the CPU2 has started a write procedure in Flash 118 * NumberOfWords : The number of 64bits data the CPU2 needs to write in Flash. 119 * For each 64bits data, the algorithm as described in AN5289 is executed. 120 * When this number is reported to 0, it means the Number of 64bits to be written 121 * was unknown when the procedure has started. 122 * When all data are written, the SHCI_SUB_EVT_NVM_END_WRITE event is reported 123 */ 124 typedef PACKED_STRUCT{ 125 uint32_t NumberOfWords; 126 } SHCI_C2_NvmStartWrite_Evt_t; 127 128 /** 129 * SHCI_SUB_EVT_NVM_END_WRITE 130 * This notifies the CPU1 that the CPU2 has written all expected data in Flash 131 */ 132 133 /** 134 * SHCI_SUB_EVT_NVM_START_ERASE 135 * This notifies the CPU1 that the CPU2 has started a erase procedure in Flash 136 * NumberOfSectors : The number of sectors the CPU2 needs to erase in Flash. 137 * For each sector, the algorithm as described in AN5289 is executed. 138 * When this number is reported to 0, it means the Number of sectors to be erased 139 * was unknown when the procedure has started. 140 * When all sectors are erased, the SHCI_SUB_EVT_NVM_END_ERASE event is reported 141 */ 142 typedef PACKED_STRUCT{ 143 uint32_t NumberOfSectors; 144 } SHCI_C2_NvmStartErase_Evt_t; 145 146 /** 147 * SHCI_SUB_EVT_NVM_END_ERASE 148 * This notifies the CPU1 that the CPU2 has erased all expected flash sectors 149 */ 150 151 /* SYSTEM COMMAND */ 152 typedef PACKED_STRUCT 153 { 154 /** 155 * MetaData holds : 156 * 2*32bits for chaining list 157 * 1*32bits with BLE header (type + Opcode + Length) 158 */ 159 uint32_t MetaData[3]; 160 } SHCI_Header_t; 161 162 typedef enum 163 { 164 SHCI_Success = 0x00, 165 SHCI_UNKNOWN_CMD = 0x01, 166 SHCI_MEMORY_CAPACITY_EXCEEDED_ERR_CODE= 0x07, 167 SHCI_ERR_UNSUPPORTED_FEATURE = 0x11, 168 SHCI_ERR_INVALID_HCI_CMD_PARAMS = 0x12, 169 SHCI_ERR_INVALID_PARAMS = 0x42, /* only used for release < v1.13.0 */ 170 SHCI_ERR_INVALID_PARAMS_V2 = 0x92, /* available for release >= v1.13.0 */ 171 SHCI_FUS_CMD_NOT_SUPPORTED = 0xFF, 172 } SHCI_CmdStatus_t; 173 174 typedef enum 175 { 176 SHCI_8BITS = 0x01, 177 SHCI_16BITS = 0x02, 178 SHCI_32BITS = 0x04, 179 } SHCI_Busw_t; 180 181 #define SHCI_OGF ( 0x3F ) 182 #define SHCI_OCF_BASE ( 0x50 ) 183 184 /** 185 * THE ORDER SHALL NOT BE CHANGED TO GUARANTEE COMPATIBILITY WITH THE CPU2 DEFINITION 186 */ 187 typedef enum 188 { 189 SHCI_OCF_C2_RESERVED1 = SHCI_OCF_BASE, 190 SHCI_OCF_C2_RESERVED2, 191 SHCI_OCF_C2_FUS_GET_STATE, 192 SHCI_OCF_C2_FUS_RESERVED1, 193 SHCI_OCF_C2_FUS_FW_UPGRADE, 194 SHCI_OCF_C2_FUS_FW_DELETE, 195 SHCI_OCF_C2_FUS_UPDATE_AUTH_KEY, 196 SHCI_OCF_C2_FUS_LOCK_AUTH_KEY, 197 SHCI_OCF_C2_FUS_STORE_USR_KEY, 198 SHCI_OCF_C2_FUS_LOAD_USR_KEY, 199 SHCI_OCF_C2_FUS_START_WS, 200 SHCI_OCF_C2_FUS_RESERVED2, 201 SHCI_OCF_C2_FUS_RESERVED3, 202 SHCI_OCF_C2_FUS_LOCK_USR_KEY, 203 SHCI_OCF_C2_FUS_UNLOAD_USR_KEY, 204 SHCI_OCF_C2_FUS_ACTIVATE_ANTIROLLBACK, 205 SHCI_OCF_C2_FUS_RESERVED7, 206 SHCI_OCF_C2_FUS_RESERVED8, 207 SHCI_OCF_C2_FUS_RESERVED9, 208 SHCI_OCF_C2_FUS_RESERVED10, 209 SHCI_OCF_C2_FUS_RESERVED11, 210 SHCI_OCF_C2_FUS_RESERVED12, 211 SHCI_OCF_C2_BLE_INIT, 212 SHCI_OCF_C2_THREAD_INIT, 213 SHCI_OCF_C2_DEBUG_INIT, 214 SHCI_OCF_C2_FLASH_ERASE_ACTIVITY, 215 SHCI_OCF_C2_CONCURRENT_SET_MODE, 216 SHCI_OCF_C2_FLASH_STORE_DATA, 217 SHCI_OCF_C2_FLASH_ERASE_DATA, 218 SHCI_OCF_C2_RADIO_ALLOW_LOW_POWER, 219 SHCI_OCF_C2_MAC_802_15_4_INIT, 220 SHCI_OCF_C2_REINIT, 221 SHCI_OCF_C2_ZIGBEE_INIT, 222 SHCI_OCF_C2_LLD_TESTS_INIT, 223 SHCI_OCF_C2_EXTPA_CONFIG, 224 SHCI_OCF_C2_SET_FLASH_ACTIVITY_CONTROL, 225 SHCI_OCF_C2_BLE_LLD_INIT, 226 SHCI_OCF_C2_CONFIG, 227 SHCI_OCF_C2_CONCURRENT_GET_NEXT_BLE_EVT_TIME, 228 SHCI_OCF_C2_CONCURRENT_ENABLE_NEXT_802154_EVT_NOTIFICATION, 229 SHCI_OCF_C2_802_15_4_DEINIT, 230 } SHCI_OCF_t; 231 232 #define SHCI_OPCODE_C2_FUS_GET_STATE (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_GET_STATE) 233 /** No command parameters */ 234 /** Response parameters*/ 235 /** It responds a 1 byte value holding FUS State error code when the FUS State value is 0xFF (FUS_STATE_VALUE_ERROR) */ 236 typedef enum 237 { 238 FUS_STATE_ERROR_NO_ERROR = 0x00, 239 FUS_STATE_ERROR_IMG_NOT_FOUND = 0x01, 240 FUS_STATE_ERROR_IMG_CORRUPT = 0x02, 241 FUS_STATE_ERROR_IMG_NOT_AUTHENTIC = 0x03, 242 FUS_STATE_ERROR_IMG_NOT_ENOUGH_SPACE = 0x04, 243 FUS_STATE_ERROR_IMAGE_USRABORT = 0x05, 244 FUS_STATE_ERROR_IMAGE_ERSERROR = 0x06, 245 FUS_STATE_ERROR_IMAGE_WRTERROR = 0x07, 246 FUS_STATE_ERROR_AUTH_TAG_ST_NOTFOUND = 0x08, 247 FUS_STATE_ERROR_AUTH_TAG_CUST_NOTFOUND = 0x09, 248 FUS_STATE_ERROR_AUTH_KEY_LOCKED = 0x0A, 249 FUS_STATE_ERROR_FW_ROLLBACK_ERROR = 0x11, 250 FUS_STATE_ERROR_STATE_NOT_RUNNING = 0xFE, 251 FUS_STATE_ERROR_ERR_UNKNOWN = 0xFF, 252 } SHCI_FUS_GetState_ErrorCode_t; 253 254 enum 255 { 256 FUS_STATE_VALUE_IDLE = 0x00, 257 FUS_STATE_VALUE_FW_UPGRD_ONGOING = 0x10, 258 FUS_STATE_VALUE_FW_UPGRD_ONGOING_END = 0x1F, /* All values between 0x10 and 0x1F has the same meaning */ 259 FUS_STATE_VALUE_FUS_UPGRD_ONGOING = 0x20, 260 FUS_STATE_VALUE_FUS_UPGRD_ONGOING_END = 0x2F, /* All values between 0x20 and 0x2F has the same meaning */ 261 FUS_STATE_VALUE_SERVICE_ONGOING = 0x30, 262 FUS_STATE_VALUE_SERVICE_ONGOING_END = 0x3F, /* All values between 0x30 and 0x3F has the same meaning */ 263 FUS_STATE_VALUE_ERROR = 0xFF, 264 }; 265 266 #define SHCI_OPCODE_C2_FUS_RESERVED1 (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_RESERVED1) 267 /** No command parameters */ 268 /** No response parameters*/ 269 270 #define SHCI_OPCODE_C2_FUS_FW_UPGRADE (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_FW_UPGRADE) 271 /** No structure for command parameters */ 272 /** No response parameters*/ 273 274 #define SHCI_OPCODE_C2_FUS_FW_DELETE (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_FW_DELETE) 275 /** No command parameters */ 276 /** No response parameters*/ 277 278 #define SHCI_OPCODE_C2_FUS_UPDATE_AUTH_KEY (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_UPDATE_AUTH_KEY) 279 typedef PACKED_STRUCT{ 280 uint8_t KeySize; 281 uint8_t KeyData[64]; 282 } SHCI_C2_FUS_UpdateAuthKey_Cmd_Param_t; 283 284 /** No response parameters*/ 285 286 #define SHCI_OPCODE_C2_FUS_LOCK_AUTH_KEY (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_LOCK_AUTH_KEY) 287 /** No command parameters */ 288 /** No response parameters*/ 289 290 #define SHCI_OPCODE_C2_FUS_STORE_USR_KEY (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_STORE_USR_KEY) 291 /** Command parameters */ 292 /* List of supported key type */ 293 enum 294 { 295 KEYTYPE_NONE = 0x00, 296 KEYTYPE_SIMPLE = 0x01, 297 KEYTYPE_MASTER = 0x02, 298 KEYTYPE_ENCRYPTED = 0x03, 299 }; 300 301 /* List of supported key size */ 302 enum 303 { 304 KEYSIZE_16 = 16, 305 KEYSIZE_32 = 32, 306 }; 307 308 typedef PACKED_STRUCT{ 309 uint8_t KeyType; 310 uint8_t KeySize; 311 uint8_t KeyData[32 + 12]; 312 } SHCI_C2_FUS_StoreUsrKey_Cmd_Param_t; 313 314 /** Response parameters*/ 315 /** It responds a 1 byte value holding the index given for the stored key */ 316 317 #define SHCI_OPCODE_C2_FUS_LOAD_USR_KEY (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_LOAD_USR_KEY) 318 /** Command parameters */ 319 /** 1 byte holding the key index value */ 320 321 /** No response parameters*/ 322 323 #define SHCI_OPCODE_C2_FUS_START_WS (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_START_WS) 324 /** No command parameters */ 325 /** No response parameters*/ 326 327 #define SHCI_OPCODE_C2_FUS_RESERVED2 (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_RESERVED2) 328 /** No command parameters */ 329 /** No response parameters*/ 330 331 #define SHCI_OPCODE_C2_FUS_RESERVED3 (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_RESERVED3) 332 /** No command parameters */ 333 /** No response parameters*/ 334 335 #define SHCI_OPCODE_C2_FUS_LOCK_USR_KEY (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_LOCK_USR_KEY) 336 /** Command parameters */ 337 /** 1 byte holding the key index value */ 338 339 /** No response parameters*/ 340 341 #define SHCI_OPCODE_C2_FUS_UNLOAD_USR_KEY (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_UNLOAD_USR_KEY) 342 /** No command parameters */ 343 /** 1 byte holding the key index value */ 344 345 #define SHCI_OPCODE_C2_FUS_ACTIVATE_ANTIROLLBACK (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_ACTIVATE_ANTIROLLBACK) 346 /** No command parameters */ 347 /** No response parameters*/ 348 349 #define SHCI_OPCODE_C2_FUS_RESERVED7 (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_RESERVED7) 350 /** No command parameters */ 351 /** No response parameters*/ 352 353 #define SHCI_OPCODE_C2_FUS_RESERVED8 (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_RESERVED8) 354 /** No command parameters */ 355 /** No response parameters*/ 356 357 #define SHCI_OPCODE_C2_FUS_RESERVED9 (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_RESERVED9) 358 /** No command parameters */ 359 /** No response parameters*/ 360 361 #define SHCI_OPCODE_C2_FUS_RESERVED10 (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_RESERVED10) 362 /** No command parameters */ 363 /** No response parameters*/ 364 365 #define SHCI_OPCODE_C2_FUS_RESERVED11 (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_RESERVED11) 366 /** No command parameters */ 367 /** No response parameters*/ 368 369 #define SHCI_OPCODE_C2_FUS_RESERVED12 (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_RESERVED12) 370 /** No command parameters */ 371 /** No response parameters*/ 372 373 #define SHCI_OPCODE_C2_BLE_INIT (( SHCI_OGF << 10) + SHCI_OCF_C2_BLE_INIT) 374 /** THE ORDER SHALL NOT BE CHANGED */ 375 typedef PACKED_STRUCT{ 376 uint8_t* pBleBufferAddress; /**< NOT USED - shall be set to 0 */ 377 uint32_t BleBufferSize; /**< NOT USED - shall be set to 0 */ 378 379 /** 380 * NumAttrRecord 381 * Maximum number of attribute records related to all the required characteristics (excluding the services) 382 * that can be stored in the GATT database, for the specific BLE user application. 383 * For each characteristic, the number of attribute records goes from two to five depending on the characteristic properties: 384 * - minimum of two (one for declaration and one for the value) 385 * - add one more record for each additional property: notify or indicate, broadcast, extended property. 386 * The total calculated value must be increased by 9, due to the records related to the standard attribute profile and 387 * GAP service characteristics, and automatically added when initializing GATT and GAP layers 388 * - Min value: <number of user attributes> + 9 389 * - Max value: depending on the GATT database defined by user application 390 */ 391 uint16_t NumAttrRecord; 392 393 /** 394 * NumAttrServ 395 * Defines the maximum number of services that can be stored in the GATT database. Note that the GAP and GATT services 396 * are automatically added at initialization so this parameter must be the number of user services increased by two. 397 * - Min value: <number of user service> + 2 398 * - Max value: depending GATT database defined by user application 399 */ 400 uint16_t NumAttrServ; 401 402 /** 403 * AttrValueArrSize 404 * NOTE: This parameter is ignored by the CPU2 when the parameter "Options" is set to "LL_only" ( see Options description in that structure ) 405 * 406 * Size of the storage area for the attribute values. 407 * Each characteristic contributes to the attrValueArrSize value as follows: 408 * - Characteristic value length plus: 409 * + 5 bytes if characteristic UUID is 16 bits 410 * + 19 bytes if characteristic UUID is 128 bits 411 * + 2 bytes if characteristic has a server configuration descriptor 412 * + 2 bytes * NumOfLinks if the characteristic has a client configuration descriptor 413 * + 2 bytes if the characteristic has extended properties 414 * Each descriptor contributes to the attrValueArrSize value as follows: 415 * - Descriptor length 416 */ 417 uint16_t AttrValueArrSize; 418 419 /** 420 * NumOfLinks 421 * Maximum number of BLE links supported 422 * - Min value: 1 423 * - Max value: 8 424 */ 425 uint8_t NumOfLinks; 426 427 /** 428 * ExtendedPacketLengthEnable 429 * Disable/enable the extended packet length BLE 5.0 feature 430 * - Disable: 0 431 * - Enable: 1 432 */ 433 uint8_t ExtendedPacketLengthEnable; 434 435 /** 436 * PrWriteListSize 437 * NOTE: This parameter is ignored by the CPU2 when the parameter "Options" is set to "LL_only" ( see Options description in that structure ) 438 * 439 * Maximum number of supported �prepare write request� 440 * - Min value: given by the macro DEFAULT_PREP_WRITE_LIST_SIZE 441 * - Max value: a value higher than the minimum required can be specified, but it is not recommended 442 */ 443 uint8_t PrWriteListSize; 444 445 /** 446 * MblockCount 447 * NOTE: This parameter is overwritten by the CPU2 with an hardcoded optimal value when the parameter "Options" is set to "LL_only" 448 * ( see Options description in that structure ) 449 * 450 * Number of allocated memory blocks for the BLE stack 451 * - Min value: given by the macro MBLOCKS_CALC 452 * - Max value: a higher value can improve data throughput performance, but uses more memory 453 */ 454 uint8_t MblockCount; 455 456 /** 457 * AttMtu 458 * NOTE: This parameter is ignored by the CPU2 when the parameter "Options" is set to "LL_only" ( see Options description in that structure ) 459 * 460 * Maximum ATT MTU size supported 461 * - Min value: 23 462 * - Max value: 512 463 */ 464 uint16_t AttMtu; 465 466 /** 467 * SlaveSca 468 * The sleep clock accuracy (ppm value) that used in BLE connected slave mode to calculate the window widening 469 * (in combination with the sleep clock accuracy sent by master in CONNECT_REQ PDU), 470 * refer to BLE 5.0 specifications - Vol 6 - Part B - chap 4.5.7 and 4.2.2 471 * - Min value: 0 472 * - Max value: 500 (worst possible admitted by specification) 473 */ 474 uint16_t SlaveSca; 475 476 /** 477 * MasterSca 478 * The sleep clock accuracy handled in master mode. It is used to determine the connection and advertising events timing. 479 * It is transmitted to the slave in CONNEC_REQ PDU used by the slave to calculate the window widening, 480 * see SlaveSca and Bluetooth Core Specification v5.0 Vol 6 - Part B - chap 4.5.7 and 4.2.2 481 * Possible values: 482 * - 251 ppm to 500 ppm: 0 483 * - 151 ppm to 250 ppm: 1 484 * - 101 ppm to 150 ppm: 2 485 * - 76 ppm to 100 ppm: 3 486 * - 51 ppm to 75 ppm: 4 487 * - 31 ppm to 50 ppm: 5 488 * - 21 ppm to 30 ppm: 6 489 * - 0 ppm to 20 ppm: 7 490 */ 491 uint8_t MasterSca; 492 493 /** 494 * LsSource 495 * Some information for Low speed clock mapped in bits field 496 * - bit 0: 1: Calibration for the RF system wakeup clock source 0: No calibration for the RF system wakeup clock source 497 * - bit 1: 1: STM32W5M Module device 0: Other devices as STM32WBxx SOC, STM32WB1M module 498 * - bit 2: 1: HSE/1024 Clock config 0: LSE Clock config 499 */ 500 uint8_t LsSource; 501 502 /** 503 * MaxConnEventLength 504 * This parameter determines the maximum duration of a slave connection event. When this duration is reached the slave closes 505 * the current connections event (whatever is the CE_length parameter specified by the master in HCI_CREATE_CONNECTION HCI command), 506 * expressed in units of 625/256 �s (~2.44 �s) 507 * - Min value: 0 (if 0 is specified, the master and slave perform only a single TX-RX exchange per connection event) 508 * - Max value: 1638400 (4000 ms). A higher value can be specified (max 0xFFFFFFFF) but results in a maximum connection time 509 * of 4000 ms as specified. In this case the parameter is not applied, and the predicted CE length calculated on slave is not shortened 510 */ 511 uint32_t MaxConnEventLength; 512 513 /** 514 * HsStartupTime 515 * Startup time of the high speed (16 or 32 MHz) crystal oscillator in units of 625/256 �s (~2.44 �s). 516 * - Min value: 0 517 * - Max value: 820 (~2 ms). A higher value can be specified, but the value that implemented in stack is forced to ~2 ms 518 */ 519 uint16_t HsStartupTime; 520 521 /** 522 * ViterbiEnable 523 * Viterbi implementation in BLE LL reception. 524 * - 0: Enable 525 * - 1: Disable 526 */ 527 uint8_t ViterbiEnable; 528 529 /** 530 * Options flags 531 * - bit 0: 1: LL only 0: LL + host 532 * - bit 1: 1: no service change desc. 0: with service change desc. 533 * - bit 2: 1: device name Read-Only 0: device name R/W 534 * - bit 3: 1: extended advertizing supported 0: extended advertizing not supported 535 * - bit 4: 1: CS Algo #2 supported 0: CS Algo #2 not supported 536 * - bit 5: 1: Reduced GATT database in NVM 0: Full GATT database in NVM 537 * - bit 6: 1: GATT caching is used 0: GATT caching is not used 538 * - bit 7: 1: LE Power Class 1 0: LE Power Class 2-3 539 * - other bits: complete with Options_extension flag 540 */ 541 uint8_t Options; 542 543 /** 544 * HwVersion 545 * Reserved for future use - shall be set to 0 546 */ 547 uint8_t HwVersion; 548 549 /** 550 * Maximum number of connection-oriented channels in initiator mode. 551 * Range: 0 .. 64 552 */ 553 uint8_t max_coc_initiator_nbr; 554 555 /** 556 * Minimum transmit power in dBm supported by the Controller. 557 * Range: -127 .. 20 558 */ 559 int8_t min_tx_power; 560 561 /** 562 * Maximum transmit power in dBm supported by the Controller. 563 * Range: -127 .. 20 564 */ 565 int8_t max_tx_power; 566 567 /** 568 * RX model configuration 569 * - bit 0: 1: agc_rssi model improved vs RF blockers 0: Legacy agc_rssi model 570 * - other bits: reserved ( shall be set to 0) 571 */ 572 uint8_t rx_model_config; 573 574 /* Maximum number of advertising sets. 575 * Range: 1 .. 8 with limitation: 576 * This parameter is linked to max_adv_data_len such as both compliant with allocated Total memory computed with BLE_EXT_ADV_BUFFER_SIZE based 577 * on Max Extended advertising configuration supported. 578 * This parameter is considered by the CPU2 when Options has SHCI_C2_BLE_INIT_OPTIONS_EXT_ADV flag set 579 */ 580 uint8_t max_adv_set_nbr; 581 582 /* Maximum advertising data length (in bytes) 583 * Range: 31 .. 1650 with limitation: 584 * This parameter is linked to max_adv_set_nbr such as both compliant with allocated Total memory computed with BLE_EXT_ADV_BUFFER_SIZE based 585 * on Max Extended advertising configuration supported. 586 * This parameter is considered by the CPU2 when Options has SHCI_C2_BLE_INIT_OPTIONS_EXT_ADV flag set 587 */ 588 uint16_t max_adv_data_len; 589 590 /* RF TX Path Compensation Value (16-bit signed integer). Units: 0.1 dB. 591 * Range: -1280 .. 1280 592 */ 593 int16_t tx_path_compens; 594 595 /* RF RX Path Compensation Value (16-bit signed integer). Units: 0.1 dB. 596 * Range: -1280 .. 1280 597 */ 598 int16_t rx_path_compens; 599 600 /* BLE core specification version (8-bit unsigned integer). 601 * values as: 11(5.2), 12(5.3) 602 */ 603 uint8_t ble_core_version; 604 605 /** 606 * Options flags extension 607 * - bit 0: 1: appearance Writable 0: appearance Read-Only 608 * - bit 1: 1: Enhanced ATT supported 0: Enhanced ATT not supported 609 * - other bits: reserved ( shall be set to 0) 610 */ 611 uint8_t Options_extension; 612 613 } SHCI_C2_Ble_Init_Cmd_Param_t; 614 615 typedef PACKED_STRUCT{ 616 SHCI_Header_t Header; /** Does not need to be initialized by the user */ 617 SHCI_C2_Ble_Init_Cmd_Param_t Param; 618 } SHCI_C2_Ble_Init_Cmd_Packet_t; 619 620 /** 621 * Options 622 * Each definition below may be added together to build the Options value 623 * WARNING : Only one definition per bit shall be added to build the Options value 624 */ 625 #define SHCI_C2_BLE_INIT_OPTIONS_LL_ONLY (1<<0) 626 #define SHCI_C2_BLE_INIT_OPTIONS_LL_HOST (0<<0) 627 628 #define SHCI_C2_BLE_INIT_OPTIONS_NO_SVC_CHANGE_DESC (1<<1) 629 #define SHCI_C2_BLE_INIT_OPTIONS_WITH_SVC_CHANGE_DESC (0<<1) 630 631 #define SHCI_C2_BLE_INIT_OPTIONS_DEVICE_NAME_RO (1<<2) 632 #define SHCI_C2_BLE_INIT_OPTIONS_DEVICE_NAME_RW (0<<2) 633 634 #define SHCI_C2_BLE_INIT_OPTIONS_EXT_ADV (1<<3) 635 #define SHCI_C2_BLE_INIT_OPTIONS_NO_EXT_ADV (0<<3) 636 637 #define SHCI_C2_BLE_INIT_OPTIONS_CS_ALGO2 (1<<4) 638 #define SHCI_C2_BLE_INIT_OPTIONS_NO_CS_ALGO2 (0<<4) 639 640 #define SHCI_C2_BLE_INIT_OPTIONS_REDUC_GATTDB_NVM (1<<5) 641 #define SHCI_C2_BLE_INIT_OPTIONS_FULL_GATTDB_NVM (0<<5) 642 643 #define SHCI_C2_BLE_INIT_OPTIONS_GATT_CACHING_USED (1<<6) 644 #define SHCI_C2_BLE_INIT_OPTIONS_GATT_CACHING_NOTUSED (0<<6) 645 646 #define SHCI_C2_BLE_INIT_OPTIONS_POWER_CLASS_1 (1<<7) 647 #define SHCI_C2_BLE_INIT_OPTIONS_POWER_CLASS_2_3 (0<<7) 648 649 /** 650 * Options extension 651 * Each definition below may be added together to build the Options value 652 * WARNING : Only one definition per bit shall be added to build the Options value 653 */ 654 #define SHCI_C2_BLE_INIT_OPTIONS_APPEARANCE_WRITABLE (1<<0) 655 #define SHCI_C2_BLE_INIT_OPTIONS_APPEARANCE_READONLY (0<<0) 656 657 #define SHCI_C2_BLE_INIT_OPTIONS_ENHANCED_ATT_SUPPORTED (1<<1) 658 #define SHCI_C2_BLE_INIT_OPTIONS_ENHANCED_ATT_NOTSUPPORTED (0<<1) 659 660 /** 661 * RX models configuration 662 */ 663 #define SHCI_C2_BLE_INIT_RX_MODEL_AGC_RSSI_LEGACY (0<<0) 664 #define SHCI_C2_BLE_INIT_RX_MODEL_AGC_RSSI_BLOCKER (1<<0) 665 666 /** 667 * BLE core version 668 */ 669 #define SHCI_C2_BLE_INIT_BLE_CORE_5_2 11 670 #define SHCI_C2_BLE_INIT_BLE_CORE_5_3 12 671 #define SHCI_C2_BLE_INIT_BLE_CORE_5_4 13 672 673 /** 674 * LsSource information 675 */ 676 #define SHCI_C2_BLE_INIT_CFG_BLE_LS_NOCALIB (0<<0) 677 #define SHCI_C2_BLE_INIT_CFG_BLE_LS_CALIB (1<<0) 678 #define SHCI_C2_BLE_INIT_CFG_BLE_LS_OTHER_DEV (0<<1) 679 #define SHCI_C2_BLE_INIT_CFG_BLE_LS_MOD5MM_DEV (1<<1) 680 #define SHCI_C2_BLE_INIT_CFG_BLE_LS_CLK_LSE (0<<2) 681 #define SHCI_C2_BLE_INIT_CFG_BLE_LS_CLK_HSE_1024 (1<<2) 682 683 #define SHCI_OPCODE_C2_THREAD_INIT (( SHCI_OGF << 10) + SHCI_OCF_C2_THREAD_INIT) 684 /** No command parameters */ 685 /** No response parameters*/ 686 687 #define SHCI_OPCODE_C2_DEBUG_INIT (( SHCI_OGF << 10) + SHCI_OCF_C2_DEBUG_INIT) 688 /** Command parameters */ 689 typedef PACKED_STRUCT 690 { 691 uint8_t thread_config; 692 uint8_t ble_config; 693 uint8_t mac_802_15_4_config; 694 uint8_t zigbee_config; 695 } SHCI_C2_DEBUG_TracesConfig_t; 696 697 typedef PACKED_STRUCT 698 { 699 uint8_t ble_dtb_cfg; 700 /** 701 * sys_dbg_cfg1 options flag 702 * - bit 0: 0: IP BLE core in LP mode 1: IP BLE core in run mode (no LP supported) 703 * - bit 1: 0: CPU2 STOP mode Enable 1: CPU2 STOP mode Disable 704 * - bit [2-7]: bits reserved ( shall be set to 0) 705 */ 706 uint8_t sys_dbg_cfg1; 707 uint8_t reserved[2]; 708 uint16_t STBY_DebugGpioaPinList; 709 uint16_t STBY_DebugGpiobPinList; 710 uint16_t STBY_DebugGpiocPinList; 711 uint16_t STBY_DtbGpioaPinList; 712 uint16_t STBY_DtbGpiobPinList; 713 } SHCI_C2_DEBUG_GeneralConfig_t; 714 715 typedef PACKED_STRUCT{ 716 uint8_t *pGpioConfig; 717 uint8_t *pTracesConfig; 718 uint8_t *pGeneralConfig; 719 uint8_t GpioConfigSize; 720 uint8_t TracesConfigSize; 721 uint8_t GeneralConfigSize; 722 } SHCI_C2_DEBUG_init_Cmd_Param_t; 723 724 typedef PACKED_STRUCT{ 725 SHCI_Header_t Header; /** Does not need to be initialized by the user */ 726 SHCI_C2_DEBUG_init_Cmd_Param_t Param; 727 } SHCI_C2_DEBUG_Init_Cmd_Packet_t; 728 /** No response parameters*/ 729 730 /** 731 * Options 732 * Each definition below may be added together to build the Options value 733 * WARNING : Only one definition per bit shall be added to build the Options value 734 */ 735 #define SHCI_C2_DEBUG_OPTIONS_IPCORE_LP (0<<0) 736 #define SHCI_C2_DEBUG_OPTIONS_IPCORE_NO_LP (1<<0) 737 738 #define SHCI_C2_DEBUG_OPTIONS_CPU2_STOP_EN (0<<1) 739 #define SHCI_C2_DEBUG_OPTIONS_CPU2_STOP_DIS (1<<1) 740 741 742 #define SHCI_OPCODE_C2_FLASH_ERASE_ACTIVITY (( SHCI_OGF << 10) + SHCI_OCF_C2_FLASH_ERASE_ACTIVITY) 743 /** Command parameters */ 744 typedef enum 745 { 746 ERASE_ACTIVITY_OFF = 0x00, 747 ERASE_ACTIVITY_ON = 0x01, 748 } SHCI_EraseActivity_t; 749 750 /** No response parameters*/ 751 752 #define SHCI_OPCODE_C2_CONCURRENT_SET_MODE (( SHCI_OGF << 10) + SHCI_OCF_C2_CONCURRENT_SET_MODE) 753 /** command parameters */ 754 typedef enum 755 { 756 BLE_ENABLE, 757 THREAD_ENABLE, 758 ZIGBEE_ENABLE, 759 MAC_ENABLE, 760 } SHCI_C2_CONCURRENT_Mode_Param_t; 761 /** No response parameters*/ 762 763 #define SHCI_OPCODE_C2_CONCURRENT_GET_NEXT_BLE_EVT_TIME (( SHCI_OGF << 10) + SHCI_OCF_C2_CONCURRENT_GET_NEXT_BLE_EVT_TIME) 764 /** command parameters */ 765 typedef PACKED_STRUCT 766 { 767 uint32_t relative_time; 768 } SHCI_C2_CONCURRENT_GetNextBleEvtTime_Param_t; 769 /** No response parameters*/ 770 771 #define SHCI_OPCODE_C2_CONCURRENT_ENABLE_NEXT_802154_EVT_NOTIFICATION (( SHCI_OGF << 10) + SHCI_OCF_C2_CONCURRENT_ENABLE_NEXT_802154_EVT_NOTIFICATION) 772 /** No command parameters */ 773 /** No response parameters*/ 774 775 #define SHCI_OPCODE_C2_FLASH_STORE_DATA (( SHCI_OGF << 10) + SHCI_OCF_C2_FLASH_STORE_DATA) 776 #define SHCI_OPCODE_C2_FLASH_ERASE_DATA (( SHCI_OGF << 10) + SHCI_OCF_C2_FLASH_ERASE_DATA) 777 /** command parameters */ 778 typedef enum 779 { 780 BLE_IP, 781 THREAD_IP, 782 ZIGBEE_IP, 783 } SHCI_C2_FLASH_Ip_t; 784 /** No response parameters*/ 785 786 #define SHCI_OPCODE_C2_RADIO_ALLOW_LOW_POWER (( SHCI_OGF << 10) + SHCI_OCF_C2_RADIO_ALLOW_LOW_POWER) 787 788 #define SHCI_OPCODE_C2_MAC_802_15_4_INIT (( SHCI_OGF << 10) + SHCI_OCF_C2_MAC_802_15_4_INIT) 789 790 #define SHCI_OPCODE_C2_REINIT (( SHCI_OGF << 10) + SHCI_OCF_C2_REINIT) 791 792 #define SHCI_OPCODE_C2_ZIGBEE_INIT (( SHCI_OGF << 10) + SHCI_OCF_C2_ZIGBEE_INIT) 793 794 #define SHCI_OPCODE_C2_LLD_TESTS_INIT (( SHCI_OGF << 10) + SHCI_OCF_C2_LLD_TESTS_INIT) 795 796 #define SHCI_OPCODE_C2_BLE_LLD_INIT (( SHCI_OGF << 10) + SHCI_OCF_C2_BLE_LLD_INIT) 797 798 #define SHCI_OPCODE_C2_EXTPA_CONFIG (( SHCI_OGF << 10) + SHCI_OCF_C2_EXTPA_CONFIG) 799 /** Command parameters */ 800 enum 801 { 802 EXT_PA_ENABLED_LOW, 803 EXT_PA_ENABLED_HIGH, 804 }/* gpio_polarity */; 805 806 enum 807 { 808 EXT_PA_DISABLED, 809 EXT_PA_ENABLED, 810 }/* gpio_status */; 811 812 typedef PACKED_STRUCT{ 813 uint32_t gpio_port; 814 uint16_t gpio_pin_number; 815 uint8_t gpio_polarity; 816 uint8_t gpio_status; 817 } SHCI_C2_EXTPA_CONFIG_Cmd_Param_t; 818 819 /** No response parameters*/ 820 821 #define SHCI_OPCODE_C2_SET_FLASH_ACTIVITY_CONTROL (( SHCI_OGF << 10) + SHCI_OCF_C2_SET_FLASH_ACTIVITY_CONTROL) 822 /** Command parameters */ 823 typedef enum 824 { 825 FLASH_ACTIVITY_CONTROL_PES, 826 FLASH_ACTIVITY_CONTROL_SEM7, 827 }SHCI_C2_SET_FLASH_ACTIVITY_CONTROL_Source_t; 828 829 /** No response parameters*/ 830 831 #define SHCI_OPCODE_C2_CONFIG (( SHCI_OGF << 10) + SHCI_OCF_C2_CONFIG) 832 /** Command parameters */ 833 typedef PACKED_STRUCT{ 834 uint8_t PayloadCmdSize; 835 uint8_t Config1; 836 uint8_t EvtMask1; 837 uint8_t Spare1; 838 uint32_t BleNvmRamAddress; 839 uint32_t ThreadNvmRamAddress; 840 uint16_t RevisionID; 841 uint16_t DeviceID; 842 } SHCI_C2_CONFIG_Cmd_Param_t; 843 844 #define SHCI_OPCODE_C2_802_15_4_DEINIT (( SHCI_OGF << 10) + SHCI_OCF_C2_802_15_4_DEINIT) 845 846 /** 847 * PayloadCmdSize 848 * Value that shall be used 849 */ 850 #define SHCI_C2_CONFIG_PAYLOAD_CMD_SIZE (sizeof(SHCI_C2_CONFIG_Cmd_Param_t) - 1) 851 852 /** 853 * Device revision ID 854 */ 855 #define SHCI_C2_CONFIG_CUT2_0 (0x2000) 856 #define SHCI_C2_CONFIG_CUT2_1 (0x2001) 857 #define SHCI_C2_CONFIG_CUT2_2 (0x2003) 858 859 /** 860 * Device ID 861 */ 862 #define SHCI_C2_CONFIG_STM32WB55xx (0x495) 863 #define SHCI_C2_CONFIG_STM32WB15xx (0x494) 864 865 /** 866 * Config1 867 * Each definition below may be added together to build the Config1 value 868 * WARNING : Only one definition per bit shall be added to build the Config1 value 869 */ 870 #define SHCI_C2_CONFIG_CONFIG1_BIT0_BLE_NVM_DATA_TO_INTERNAL_FLASH (0<<0) 871 #define SHCI_C2_CONFIG_CONFIG1_BIT0_BLE_NVM_DATA_TO_SRAM (1<<0) 872 #define SHCI_C2_CONFIG_CONFIG1_BIT1_THREAD_NVM_DATA_TO_INTERNAL_FLASH (0<<1) 873 #define SHCI_C2_CONFIG_CONFIG1_BIT1_THREAD_NVM_DATA_TO_SRAM (1<<1) 874 875 /** 876 * EvtMask1 877 * Each definition below may be added together to build the EvtMask1 value 878 */ 879 #define SHCI_C2_CONFIG_EVTMASK1_BIT0_ERROR_NOTIF_ENABLE (1<<0) 880 #define SHCI_C2_CONFIG_EVTMASK1_BIT1_BLE_NVM_RAM_UPDATE_ENABLE (1<<1) 881 #define SHCI_C2_CONFIG_EVTMASK1_BIT2_THREAD_NVM_RAM_UPDATE_ENABLE (1<<2) 882 #define SHCI_C2_CONFIG_EVTMASK1_BIT3_NVM_START_WRITE_ENABLE (1<<3) 883 #define SHCI_C2_CONFIG_EVTMASK1_BIT4_NVM_END_WRITE_ENABLE (1<<4) 884 #define SHCI_C2_CONFIG_EVTMASK1_BIT5_NVM_START_ERASE_ENABLE (1<<5) 885 #define SHCI_C2_CONFIG_EVTMASK1_BIT6_NVM_END_ERASE_ENABLE (1<<6) 886 887 /** 888 * BleNvmRamAddress 889 * The buffer shall have a size of BLE_NVM_SRAM_SIZE number of 32bits 890 * The buffer shall be allocated in SRAM2 891 */ 892 #define BLE_NVM_SRAM_SIZE (507) 893 894 /** 895 * ThreadNvmRamAddress 896 * The buffer shall have a size of THREAD_NVM_SRAM_SIZE number of 32bits 897 * The buffer shall be allocated in SRAM2 898 */ 899 #define THREAD_NVM_SRAM_SIZE (1016) 900 901 902 /** No response parameters*/ 903 904 /* Exported type --------------------------------------------------------*/ 905 #define FUS_DEVICE_INFO_TABLE_VALIDITY_KEYWORD (0xA94656B9) 906 907 /* 908 * At startup, the information relative to the wireless binary are stored in RAM through a structure defined by 909 * MB_WirelessFwInfoTable_t.This structure contains 4 fields (Version,MemorySize, Stack_info and a reserved part) 910 * each of those coded on 32 bits as shown on the table below: 911 * 912 * 913 * |7 |6 |5 |4 |3 |2 |1 |0 |7 |6 |5 |4 |3 |2 |1 |0 |7 |6 |5 |4 |3 |2 |1 |0 |7 |6 |5 |4 |3 |2 |1 |0 | 914 * ------------------------------------------------------------------------------------------------- 915 * Version | Major version | Minor version | Sub version | Branch |ReleaseType| 916 * ------------------------------------------------------------------------------------------------- 917 * MemorySize | SRAM2B (kB) | SRAM2A (kB) | SRAM1 (kB) | FLASH (4kb) | 918 * ------------------------------------------------------------------------------------------------- 919 * Info stack | Reserved | Reserved | Reserved | Type (MAC,Thread,BLE) | 920 * ------------------------------------------------------------------------------------------------- 921 * Reserved | Reserved | Reserved | Reserved | Reserved | 922 * ------------------------------------------------------------------------------------------------- 923 * 924 */ 925 926 /* Field Version */ 927 #define INFO_VERSION_MAJOR_OFFSET 24 928 #define INFO_VERSION_MAJOR_MASK 0xff000000 929 #define INFO_VERSION_MINOR_OFFSET 16 930 #define INFO_VERSION_MINOR_MASK 0x00ff0000 931 #define INFO_VERSION_SUB_OFFSET 8 932 #define INFO_VERSION_SUB_MASK 0x0000ff00 933 #define INFO_VERSION_BRANCH_OFFSET 4 934 #define INFO_VERSION_BRANCH_MASK 0x0000000f0 935 #define INFO_VERSION_TYPE_OFFSET 0 936 #define INFO_VERSION_TYPE_MASK 0x00000000f 937 938 #define INFO_VERSION_TYPE_RELEASE 1 939 940 /* Field Memory */ 941 #define INFO_SIZE_SRAM2B_OFFSET 24 942 #define INFO_SIZE_SRAM2B_MASK 0xff000000 943 #define INFO_SIZE_SRAM2A_OFFSET 16 944 #define INFO_SIZE_SRAM2A_MASK 0x00ff0000 945 #define INFO_SIZE_SRAM1_OFFSET 8 946 #define INFO_SIZE_SRAM1_MASK 0x0000ff00 947 #define INFO_SIZE_FLASH_OFFSET 0 948 #define INFO_SIZE_FLASH_MASK 0x000000ff 949 950 /* Field stack information */ 951 #define INFO_STACK_TYPE_OFFSET 0 952 #define INFO_STACK_TYPE_MASK 0x000000ff 953 #define INFO_STACK_TYPE_NONE 0 954 955 #define INFO_STACK_TYPE_BLE_FULL 0x01 956 #define INFO_STACK_TYPE_BLE_HCI 0x02 957 #define INFO_STACK_TYPE_BLE_LIGHT 0x03 958 #define INFO_STACK_TYPE_BLE_BEACON 0x04 959 #define INFO_STACK_TYPE_BLE_BASIC 0x05 960 #define INFO_STACK_TYPE_BLE_FULL_EXT_ADV 0x06 961 #define INFO_STACK_TYPE_BLE_HCI_EXT_ADV 0x07 962 #define INFO_STACK_TYPE_THREAD_FTD 0x10 963 #define INFO_STACK_TYPE_THREAD_MTD 0x11 964 #define INFO_STACK_TYPE_ZIGBEE_FFD 0x30 965 #define INFO_STACK_TYPE_ZIGBEE_RFD 0x31 966 #define INFO_STACK_TYPE_MAC 0x40 967 #define INFO_STACK_TYPE_BLE_THREAD_FTD_STATIC 0x50 968 #define INFO_STACK_TYPE_BLE_THREAD_FTD_DYAMIC 0x51 969 #define INFO_STACK_TYPE_802154_LLD_TESTS 0x60 970 #define INFO_STACK_TYPE_802154_PHY_VALID 0x61 971 #define INFO_STACK_TYPE_BLE_PHY_VALID 0x62 972 #define INFO_STACK_TYPE_BLE_LLD_TESTS 0x63 973 #define INFO_STACK_TYPE_BLE_RLV 0x64 974 #define INFO_STACK_TYPE_802154_RLV 0x65 975 #define INFO_STACK_TYPE_BLE_ZIGBEE_FFD_STATIC 0x70 976 #define INFO_STACK_TYPE_BLE_ZIGBEE_RFD_STATIC 0x71 977 #define INFO_STACK_TYPE_BLE_ZIGBEE_FFD_DYNAMIC 0x78 978 #define INFO_STACK_TYPE_BLE_ZIGBEE_RFD_DYNAMIC 0x79 979 #define INFO_STACK_TYPE_RLV 0x80 980 #define INFO_STACK_TYPE_BLE_MAC_STATIC 0x90 981 982 typedef struct { 983 /** 984 * Wireless Info 985 */ 986 uint8_t VersionMajor; 987 uint8_t VersionMinor; 988 uint8_t VersionSub; 989 uint8_t VersionBranch; 990 uint8_t VersionReleaseType; 991 uint8_t MemorySizeSram2B; /*< Multiple of 1K */ 992 uint8_t MemorySizeSram2A; /*< Multiple of 1K */ 993 uint8_t MemorySizeSram1; /*< Multiple of 1K */ 994 uint8_t MemorySizeFlash; /*< Multiple of 4K */ 995 uint8_t StackType; 996 /** 997 * Fus Info 998 */ 999 uint8_t FusVersionMajor; 1000 uint8_t FusVersionMinor; 1001 uint8_t FusVersionSub; 1002 uint8_t FusMemorySizeSram2B; /*< Multiple of 1K */ 1003 uint8_t FusMemorySizeSram2A; /*< Multiple of 1K */ 1004 uint8_t FusMemorySizeFlash; /*< Multiple of 4K */ 1005 }WirelessFwInfo_t; 1006 1007 1008 /* Exported functions ------------------------------------------------------- */ 1009 1010 /** 1011 * SHCI_C2_FUS_GetState 1012 * @brief Read the FUS State 1013 * If the user is not interested by the Error code response, a null value may 1014 * be passed as parameter 1015 * 1016 * Note: This command is fully supported only by the FUS. 1017 * When the wireless firmware receives that command, it responds SHCI_FUS_CMD_NOT_SUPPORTED the first time. 1018 * When the wireless firmware receives that command a second time, it reboots the full device with the FUS running on CPU2 1019 * 1020 * @param p_rsp : return the error code when the FUS State Value = 0xFF 1021 * @retval FUS State Values 1022 */ 1023 uint8_t SHCI_C2_FUS_GetState( SHCI_FUS_GetState_ErrorCode_t *p_rsp ); 1024 1025 /** 1026 * SHCI_C2_FUS_FwUpgrade 1027 * @brief Request the FUS to install the CPU2 firmware update 1028 * Note: This command is only supported by the FUS. 1029 * 1030 * @param fw_src_add: Address of the firmware image location 1031 * @param fw_dest_add: Address of the firmware destination 1032 * @retval Status 1033 */ 1034 SHCI_CmdStatus_t SHCI_C2_FUS_FwUpgrade( uint32_t fw_src_add, uint32_t fw_dest_add ); 1035 1036 /** 1037 * SHCI_C2_FUS_FwDelete 1038 * @brief Delete the wireless stack on CPU2 1039 * Note: This command is only supported by the FUS. 1040 * 1041 * @param None 1042 * @retval Status 1043 */ 1044 SHCI_CmdStatus_t SHCI_C2_FUS_FwDelete( void ); 1045 1046 /** 1047 * SHCI_C2_FUS_UpdateAuthKey 1048 * @brief Request the FUS to update the authentication key 1049 * Note: This command is only supported by the FUS. 1050 * 1051 * @param pCmdPacket 1052 * @retval Status 1053 */ 1054 SHCI_CmdStatus_t SHCI_C2_FUS_UpdateAuthKey( SHCI_C2_FUS_UpdateAuthKey_Cmd_Param_t *pParam ); 1055 1056 /** 1057 * SHCI_C2_FUS_LockAuthKey 1058 * @brief Request the FUS to prevent any future update of the authentication key 1059 * Note: This command is only supported by the FUS. 1060 * 1061 * @param None 1062 * @retval Status 1063 */ 1064 SHCI_CmdStatus_t SHCI_C2_FUS_LockAuthKey( void ); 1065 1066 /** 1067 * SHCI_C2_FUS_StoreUsrKey 1068 * @brief Request the FUS to store the user key 1069 * Note: This command is supported by both the FUS and the wireless stack. 1070 * 1071 * @param pParam : command parameter 1072 * @param p_key_index : Index allocated by the FUS to the stored key 1073 * 1074 * @retval Status 1075 */ 1076 SHCI_CmdStatus_t SHCI_C2_FUS_StoreUsrKey( SHCI_C2_FUS_StoreUsrKey_Cmd_Param_t *pParam, uint8_t *p_key_index ); 1077 1078 /** 1079 * SHCI_C2_FUS_LoadUsrKey 1080 * @brief Request the FUS to load the user key into the AES 1081 * Note: This command is supported by both the FUS and the wireless stack. 1082 * 1083 * @param key_index : index of the user key to load in AES1 1084 * @retval Status 1085 */ 1086 SHCI_CmdStatus_t SHCI_C2_FUS_LoadUsrKey( uint8_t key_index ); 1087 1088 /** 1089 * SHCI_C2_FUS_StartWs 1090 * @brief Request the FUS to reboot on the wireless stack 1091 * Note: This command is only supported by the FUS. 1092 * 1093 * @param None 1094 * @retval Status 1095 */ 1096 SHCI_CmdStatus_t SHCI_C2_FUS_StartWs( void ); 1097 1098 /** 1099 * SHCI_C2_FUS_LockUsrKey 1100 * @brief Request the FUS to lock the user key so that it cannot be updated later on 1101 * Note: This command is supported by both the FUS and the wireless stack. 1102 * 1103 * @param key_index : index of the user key to lock 1104 * @retval Status 1105 */ 1106 SHCI_CmdStatus_t SHCI_C2_FUS_LockUsrKey( uint8_t key_index ); 1107 1108 /** 1109 * SHCI_C2_FUS_UnloadUsrKey 1110 * @brief Request the FUS to Unload the user key so that the CPU1 may use the AES with another Key 1111 * Note: This command is supported by both the FUS and the wireless stack. 1112 * 1113 * @param key_index : index of the user key to unload 1114 * @retval Status 1115 */ 1116 SHCI_CmdStatus_t SHCI_C2_FUS_UnloadUsrKey( uint8_t key_index ); 1117 1118 /** 1119 * SHCI_C2_FUS_ActivateAntiRollback 1120 * @brief Request the FUS to enable the AntiRollback feature so that it is not possible to update the wireless firmware 1121 * with an older version than the current one. 1122 * Note: 1123 * - This command is only supported by the FUS. 1124 * - Once this feature is enabled, it is not possible anymore to disable it. 1125 * 1126 * @param None 1127 * @retval Status 1128 */ 1129 SHCI_CmdStatus_t SHCI_C2_FUS_ActivateAntiRollback( void ); 1130 1131 /** 1132 * SHCI_C2_BLE_Init 1133 * @brief Provides parameters and starts the BLE Stack 1134 * 1135 * @param pCmdPacket : Parameters are described SHCI_C2_Ble_Init_Cmd_Packet_t declaration 1136 * @retval Status 1137 */ 1138 SHCI_CmdStatus_t SHCI_C2_BLE_Init( SHCI_C2_Ble_Init_Cmd_Packet_t *pCmdPacket ); 1139 1140 /** 1141 * SHCI_C2_THREAD_Init 1142 * @brief Starts the THREAD Stack 1143 * 1144 * @param None 1145 * @retval Status 1146 */ 1147 SHCI_CmdStatus_t SHCI_C2_THREAD_Init( void ); 1148 1149 /** 1150 * SHCI_C2_LLDTESTS_Init 1151 * @brief Starts the LLD tests CLI 1152 * 1153 * @param param_size : Nb of bytes 1154 * @param p_param : pointer with data to give from M4 to M0 1155 * @retval Status 1156 */ 1157 SHCI_CmdStatus_t SHCI_C2_LLDTESTS_Init( uint8_t param_size, uint8_t * p_param ); 1158 1159 /** 1160 * SHCI_C2_BLE_LLD_Init 1161 * @brief Starts the LLD tests BLE 1162 * 1163 * @param param_size : Nb of bytes 1164 * @param p_param : pointer with data to give from M4 to M0 1165 * @retval Status 1166 */ 1167 SHCI_CmdStatus_t SHCI_C2_BLE_LLD_Init( uint8_t param_size, uint8_t * p_param ); 1168 1169 /** 1170 * SHCI_C2_ZIGBEE_Init 1171 * @brief Starts the Zigbee Stack 1172 * 1173 * @param None 1174 * @retval Status 1175 */ 1176 SHCI_CmdStatus_t SHCI_C2_ZIGBEE_Init( void ); 1177 1178 /** 1179 * SHCI_C2_DEBUG_Init 1180 * @brief Starts the Traces 1181 * 1182 * @param None 1183 * @retval Status 1184 */ 1185 SHCI_CmdStatus_t SHCI_C2_DEBUG_Init( SHCI_C2_DEBUG_Init_Cmd_Packet_t *pCmdPacket ); 1186 1187 /** 1188 * SHCI_C2_FLASH_EraseActivity 1189 * @brief Provides the information of the start and the end of a flash erase window on the CPU1 1190 * The protection will be active until next end of radio event. 1191 * 1192 * @param erase_activity: Start/End of erase activity 1193 * @retval Status 1194 */ 1195 SHCI_CmdStatus_t SHCI_C2_FLASH_EraseActivity( SHCI_EraseActivity_t erase_activity ); 1196 1197 /** 1198 * SHCI_C2_CONCURRENT_SetMode 1199 * @brief Enable/Disable Thread on CPU2 (M0+) 1200 * 1201 * @param Mode: BLE or Thread enable flag 1202 * @retval Status 1203 */ 1204 SHCI_CmdStatus_t SHCI_C2_CONCURRENT_SetMode( SHCI_C2_CONCURRENT_Mode_Param_t Mode ); 1205 1206 /** 1207 * SHCI_C2_CONCURRENT_GetNextBleEvtTime 1208 * @brief Get the next BLE event date (relative time) 1209 * 1210 * @param Command Packet 1211 * @retval None 1212 */ 1213 SHCI_CmdStatus_t SHCI_C2_CONCURRENT_GetNextBleEvtTime( SHCI_C2_CONCURRENT_GetNextBleEvtTime_Param_t *pParam ); 1214 1215 /** 1216 * SHCI_C2_CONCURRENT_EnableNext_802154_EvtNotification 1217 * @brief Activate the next 802.15.4 event notification (one shot) 1218 * 1219 * @param None 1220 * @retval None 1221 */ 1222 SHCI_CmdStatus_t SHCI_C2_CONCURRENT_EnableNext_802154_EvtNotification( void ); 1223 1224 /** 1225 * SHCI_C2_FLASH_StoreData 1226 * @brief Store Data in Flash 1227 * 1228 * @param Ip: BLE or THREAD 1229 * @retval Status 1230 */ 1231 SHCI_CmdStatus_t SHCI_C2_FLASH_StoreData( SHCI_C2_FLASH_Ip_t Ip ); 1232 1233 /** 1234 * SHCI_C2_FLASH_EraseData 1235 * @brief Erase Data in Flash 1236 * 1237 * @param Ip: BLE or THREAD 1238 * @retval Status 1239 */ 1240 SHCI_CmdStatus_t SHCI_C2_FLASH_EraseData( SHCI_C2_FLASH_Ip_t Ip ); 1241 1242 /** 1243 * SHCI_C2_RADIO_AllowLowPower 1244 * @brief Allow or forbid IP_radio (802_15_4 or BLE) to enter in low power mode. 1245 * 1246 * @param Ip: BLE or 802_15_5 1247 * @param FlagRadioLowPowerOn: True or false 1248 * @retval Status 1249 */ 1250 SHCI_CmdStatus_t SHCI_C2_RADIO_AllowLowPower( SHCI_C2_FLASH_Ip_t Ip,uint8_t FlagRadioLowPowerOn); 1251 1252 1253 /** 1254 * SHCI_C2_MAC_802_15_4_Init 1255 * @brief Starts the MAC 802.15.4 on M0 1256 * 1257 * @param None 1258 * @retval Status 1259 */ 1260 SHCI_CmdStatus_t SHCI_C2_MAC_802_15_4_Init( void ); 1261 1262 /** 1263 * SHCI_GetWirelessFwInfo 1264 * @brief This function read back the information relative to the wireless binary loaded. 1265 * Refer yourself to MB_WirelessFwInfoTable_t structure to get the significance 1266 * of the different parameters returned. 1267 * @param pWirelessInfo : Pointer to WirelessFwInfo_t. 1268 * 1269 * @retval SHCI_Success 1270 */ 1271 SHCI_CmdStatus_t SHCI_GetWirelessFwInfo( WirelessFwInfo_t* pWirelessInfo ); 1272 1273 /** 1274 * SHCI_C2_Reinit 1275 * @brief This is required to allow the CPU1 to fake a set C2BOOT when it has already been set. 1276 * In order to fake a C2BOOT, the CPU1 shall : 1277 * - Send SHCI_C2_Reinit() 1278 * - call SEV instruction 1279 * WARNING: 1280 * This function is intended to be used by the SBSFU 1281 * 1282 * @param None 1283 * @retval Status 1284 */ 1285 SHCI_CmdStatus_t SHCI_C2_Reinit( void ); 1286 1287 /** 1288 * SHCI_C2_ExtpaConfig 1289 * @brief Send the Ext PA configuration 1290 * When the CPU2 receives the command, it controls the Ext PA as requested by the configuration 1291 * This configures only which IO is used to enable/disable the ExtPA and the associated polarity 1292 * This command has no effect on the other IO that is used to control the mode of the Ext PA (Rx/Tx) 1293 * 1294 * @param gpio_port: GPIOx where x can be (A..F) to select the GPIO peripheral for STM32WBxx family 1295 * @param gpio_pin_number: This parameter can be one of GPIO_PIN_x (= LL_GPIO_PIN_x) where x can be (0..15). 1296 * @param gpio_polarity: This parameter can be either 1297 * - EXT_PA_ENABLED_LOW: ExtPA is enabled when GPIO is low 1298 * - EXT_PA_ENABLED_HIGH: ExtPA is enabled when GPIO is high 1299 * @param gpio_status: This parameter can be either 1300 * - EXT_PA_DISABLED: Stop driving the ExtPA 1301 * - EXT_PA_ENABLED: Drive the ExtPA according to radio activity 1302 * (ON before the Event and OFF at the end of the event) 1303 * @retval Status 1304 */ 1305 SHCI_CmdStatus_t SHCI_C2_ExtpaConfig(uint32_t gpio_port, uint16_t gpio_pin_number, uint8_t gpio_polarity, uint8_t gpio_status); 1306 1307 /** 1308 * SHCI_C2_SetFlashActivityControl 1309 * @brief Set the mechanism to be used on CPU2 to prevent the CPU1 to either write or erase in flash 1310 * 1311 * @param Source: It can be one of the following list 1312 * - FLASH_ACTIVITY_CONTROL_PES : The CPU2 set the PES bit to prevent the CPU1 to either read or write in flash 1313 * - FLASH_ACTIVITY_CONTROL_SEM7 : The CPU2 gets the semaphore 7 to prevent the CPU1 to either read or write in flash. 1314 * This requires the CPU1 to first get semaphore 7 before erasing or writing the flash. 1315 * 1316 * @retval Status 1317 */ 1318 SHCI_CmdStatus_t SHCI_C2_SetFlashActivityControl(SHCI_C2_SET_FLASH_ACTIVITY_CONTROL_Source_t Source); 1319 1320 /** 1321 * SHCI_C2_Config 1322 * @brief Send the system configuration to the CPU2 1323 * 1324 * @param pCmdPacket: address of the buffer holding following parameters 1325 * uint8_t PayloadCmdSize : Size of the payload - shall be SHCI_C2_CONFIG_PAYLOAD_CMD_SIZE 1326 * uint8_t Config1 : 1327 * - bit0 : 0 - BLE NVM Data data are flushed in internal secure flash 1328 * 1 - BLE NVM Data are written in SRAM cache pointed by BleNvmRamAddress 1329 * - bit1 : 0 - THREAD NVM Data data are flushed in internal secure flash 1330 * 1 - THREAD NVM Data are written in SRAM cache pointed by ThreadNvmRamAddress 1331 * - bit2 to bit7 : Unused, shall be set to 0 1332 * uint8_t EvtMask1 : 1333 * When a bit is set to 0, the event is not reported 1334 * bit0 : Asynchronous Event with Sub Evt Code 0x9201 (= SHCI_SUB_EVT_ERROR_NOTIF) 1335 * ... 1336 * bit31 : Asynchronous Event with Sub Evt Code 0x9220 1337 * uint8_t Spare1 : Unused, shall be set to 0 1338 * uint32_t BleNvmRamAddress : 1339 * Only considered when Config1.bit0 = 1 1340 * When set to 0, data are kept in internal SRAM on CPU2 1341 * Otherwise, data are copied in the cache pointed by BleNvmRamAddress 1342 * The size of the buffer shall be BLE_NVM_SRAM_SIZE (number of 32bits) 1343 * The buffer shall be allocated in SRAM2 1344 * uint32_t ThreadNvmRamAddress : 1345 * Only considered when Config1.bit1 = 1 1346 * When set to 0, data are kept in internal SRAM on CPU2 1347 * Otherwise, data are copied in the cache pointed by ThreadNvmRamAddress 1348 * The size of the buffer shall be THREAD_NVM_SRAM_SIZE (number of 32bits) 1349 * The buffer shall be allocated in SRAM1 1350 * 1351 * Please check macro definition to be used for this function 1352 * They are defined in this file next to the definition of SHCI_OPCODE_C2_CONFIG 1353 * 1354 * @retval Status 1355 */ 1356 SHCI_CmdStatus_t SHCI_C2_Config(SHCI_C2_CONFIG_Cmd_Param_t *pCmdPacket); 1357 1358 /** 1359 * SHCI_C2_802_15_4_DeInit 1360 * @brief Deinit 802.15.4 layer (to be used before entering StandBy mode) 1361 * 1362 * @param None 1363 * @retval Status 1364 */ 1365 SHCI_CmdStatus_t SHCI_C2_802_15_4_DeInit( void ); 1366 1367 #ifdef __cplusplus 1368 } 1369 #endif 1370 1371 #endif /*__SHCI_H */ 1372 1373
