1 /***************************************************************************//**
2 * @file
3 * @brief Direct memory access (LDMA) API
4 *******************************************************************************
5 * # License
6 * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b>
7 *******************************************************************************
8 *
9 * SPDX-License-Identifier: Zlib
10 *
11 * The licensor of this software is Silicon Laboratories Inc.
12 *
13 * This software is provided 'as-is', without any express or implied
14 * warranty. In no event will the authors be held liable for any damages
15 * arising from the use of this software.
16 *
17 * Permission is granted to anyone to use this software for any purpose,
18 * including commercial applications, and to alter it and redistribute it
19 * freely, subject to the following restrictions:
20 *
21 * 1. The origin of this software must not be misrepresented; you must not
22 * claim that you wrote the original software. If you use this software
23 * in a product, an acknowledgment in the product documentation would be
24 * appreciated but is not required.
25 * 2. Altered source versions must be plainly marked as such, and must not be
26 * misrepresented as being the original software.
27 * 3. This notice may not be removed or altered from any source distribution.
28 *
29 ******************************************************************************/
30
31 #ifndef EM_LDMA_H
32 #define EM_LDMA_H
33
34 #include "em_device.h"
35
36 #if defined(LDMA_PRESENT) && (LDMA_COUNT == 1)
37
38 #include <stdbool.h>
39
40 #ifdef __cplusplus
41 extern "C" {
42 #endif
43
44 /***************************************************************************//**
45 * @addtogroup ldma LDMA - Linked DMA
46 * @brief Linked Direct Memory Access (LDMA) Peripheral API
47 *
48 * @details
49 * LDMA API functions provide full support for the LDMA peripheral.
50 *
51 * LDMA supports these DMA transfer types:
52 *
53 * @li Memory to memory.
54 * @li Memory to peripheral.
55 * @li Peripheral to memory.
56 * @li Peripheral to peripheral.
57 * @li Constant value to memory.
58 *
59 * LDMA supports linked lists of DMA descriptors allowing:
60 *
61 * @li Circular and ping-pong buffer transfers.
62 * @li Scatter-gather transfers.
63 * @li Looped transfers.
64 *
65 * LDMA has some advanced features:
66 *
67 * @li Intra-channel synchronization (SYNC), allowing hardware events to
68 * pause and restart a DMA sequence.
69 * @li Immediate-write (WRI), allowing DMA to write a constant anywhere
70 * in the memory map.
71 * @li Complex flow control allowing if-else constructs.
72 *
73 * Basic understanding of LDMA controller is assumed. Please refer to
74 * the reference manual for further details. The LDMA examples described
75 * in the reference manual are particularly helpful in understanding LDMA
76 * operations.
77 *
78 * In order to use the DMA controller, the initialization function @ref
79 * LDMA_Init() must have been executed once (normally during system initialization).
80 *
81 * DMA transfers are initiated by a call to @ref LDMA_StartTransfer(),
82 * transfer properties are controlled by the contents of @ref LDMA_TransferCfg_t
83 * and @ref LDMA_Descriptor_t structure parameters.
84 * The LDMA_Descriptor_t structure parameter may be a
85 * pointer to an array of descriptors, descriptors in array should
86 * be linked together as needed.
87 *
88 * Transfer and descriptor initialization macros are provided for the most common
89 * transfer types. Due to the flexibility of LDMA peripheral, only a small
90 * subset of all possible initializer macros are provided, users should create
91 * new ones when needed.
92 *
93 * <b> Examples of LDMA usage: </b>
94 *
95 * A simple memory to memory transfer:
96 *
97 * @include em_ldma_single.c
98 *
99 * @n A linked list of three memory to memory transfers:
100 *
101 * @include em_ldma_link_memory.c
102 *
103 * @n DMA from serial port peripheral to memory:
104 *
105 * @include em_ldma_peripheral.c
106 *
107 * @n Ping-pong DMA from serial port peripheral to memory:
108 *
109 * @include em_ldma_pingpong.c
110 *
111 * @note LDMA module does not implement LDMA interrupt handler. A
112 * template for an LDMA IRQ handler is included here as an example.
113 *
114 * @include em_ldma_irq.c
115 *
116 * @{
117 ******************************************************************************/
118
119 /*******************************************************************************
120 ******************************** ENUMS ************************************
121 ******************************************************************************/
122
123 /**
124 * Controls the number of unit data transfers per arbitration
125 * cycle, providing a means to balance DMA channels' load on the controller.
126 */
127 typedef enum {
128 ldmaCtrlBlockSizeUnit1 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT1, /**< One transfer per arbitration. */
129 ldmaCtrlBlockSizeUnit2 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT2, /**< Two transfers per arbitration. */
130 ldmaCtrlBlockSizeUnit3 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT3, /**< Three transfers per arbitration. */
131 ldmaCtrlBlockSizeUnit4 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT4, /**< Four transfers per arbitration. */
132 ldmaCtrlBlockSizeUnit6 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT6, /**< Six transfers per arbitration. */
133 ldmaCtrlBlockSizeUnit8 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT8, /**< Eight transfers per arbitration. */
134 ldmaCtrlBlockSizeUnit16 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT16, /**< 16 transfers per arbitration. */
135 ldmaCtrlBlockSizeUnit32 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT32, /**< 32 transfers per arbitration. */
136 ldmaCtrlBlockSizeUnit64 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT64, /**< 64 transfers per arbitration. */
137 ldmaCtrlBlockSizeUnit128 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT128, /**< 128 transfers per arbitration. */
138 ldmaCtrlBlockSizeUnit256 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT256, /**< 256 transfers per arbitration. */
139 ldmaCtrlBlockSizeUnit512 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT512, /**< 512 transfers per arbitration. */
140 ldmaCtrlBlockSizeUnit1024 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT1024, /**< 1024 transfers per arbitration. */
141 ldmaCtrlBlockSizeAll = _LDMA_CH_CTRL_BLOCKSIZE_ALL /**< Lock arbitration during transfer. */
142 } LDMA_CtrlBlockSize_t;
143
144 /** DMA structure type. */
145 typedef enum {
146 ldmaCtrlStructTypeXfer = _LDMA_CH_CTRL_STRUCTTYPE_TRANSFER, /**< TRANSFER transfer type. */
147 ldmaCtrlStructTypeSync = _LDMA_CH_CTRL_STRUCTTYPE_SYNCHRONIZE, /**< SYNCHRONIZE transfer type. */
148 ldmaCtrlStructTypeWrite = _LDMA_CH_CTRL_STRUCTTYPE_WRITE /**< WRITE transfer type. */
149 } LDMA_CtrlStructType_t;
150
151 /** DMA transfer block or cycle selector. */
152 typedef enum {
153 ldmaCtrlReqModeBlock = _LDMA_CH_CTRL_REQMODE_BLOCK, /**< Each DMA request trigger transfer of one block. */
154 ldmaCtrlReqModeAll = _LDMA_CH_CTRL_REQMODE_ALL /**< A DMA request trigger transfer of a complete cycle. */
155 } LDMA_CtrlReqMode_t;
156
157 /** Source address increment unit size. */
158 typedef enum {
159 ldmaCtrlSrcIncOne = _LDMA_CH_CTRL_SRCINC_ONE, /**< Increment source address by one unit data size. */
160 ldmaCtrlSrcIncTwo = _LDMA_CH_CTRL_SRCINC_TWO, /**< Increment source address by two unit data sizes. */
161 ldmaCtrlSrcIncFour = _LDMA_CH_CTRL_SRCINC_FOUR, /**< Increment source address by four unit data sizes. */
162 ldmaCtrlSrcIncNone = _LDMA_CH_CTRL_SRCINC_NONE /**< Do not increment source address. */
163 } LDMA_CtrlSrcInc_t;
164
165 /** DMA transfer unit size. */
166 typedef enum {
167 ldmaCtrlSizeByte = _LDMA_CH_CTRL_SIZE_BYTE, /**< Each unit transfer is a byte. */
168 ldmaCtrlSizeHalf = _LDMA_CH_CTRL_SIZE_HALFWORD, /**< Each unit transfer is a half-word. */
169 ldmaCtrlSizeWord = _LDMA_CH_CTRL_SIZE_WORD /**< Each unit transfer is a word. */
170 } LDMA_CtrlSize_t;
171
172 /** Destination address increment unit size. */
173 typedef enum {
174 ldmaCtrlDstIncOne = _LDMA_CH_CTRL_DSTINC_ONE, /**< Increment destination address by one unit data size. */
175 ldmaCtrlDstIncTwo = _LDMA_CH_CTRL_DSTINC_TWO, /**< Increment destination address by two unit data sizes. */
176 ldmaCtrlDstIncFour = _LDMA_CH_CTRL_DSTINC_FOUR, /**< Increment destination address by four unit data sizes. */
177 ldmaCtrlDstIncNone = _LDMA_CH_CTRL_DSTINC_NONE /**< Do not increment destination address. */
178 } LDMA_CtrlDstInc_t;
179
180 /** Source addressing mode. */
181 typedef enum {
182 ldmaCtrlSrcAddrModeAbs = _LDMA_CH_CTRL_SRCMODE_ABSOLUTE, /**< Address fetched from a linked structure is absolute. */
183 ldmaCtrlSrcAddrModeRel = _LDMA_CH_CTRL_SRCMODE_RELATIVE /**< Address fetched from a linked structure is relative. */
184 } LDMA_CtrlSrcAddrMode_t;
185
186 /** Destination addressing mode. */
187 typedef enum {
188 ldmaCtrlDstAddrModeAbs = _LDMA_CH_CTRL_DSTMODE_ABSOLUTE, /**< Address fetched from a linked structure is absolute. */
189 ldmaCtrlDstAddrModeRel = _LDMA_CH_CTRL_DSTMODE_RELATIVE /**< Address fetched from a linked structure is relative. */
190 } LDMA_CtrlDstAddrMode_t;
191
192 /** DMA link load address mode. */
193 typedef enum {
194 ldmaLinkModeAbs = _LDMA_CH_LINK_LINKMODE_ABSOLUTE, /**< Link address is an absolute address value. */
195 ldmaLinkModeRel = _LDMA_CH_LINK_LINKMODE_RELATIVE /**< Link address is a two's complement relative address. */
196 } LDMA_LinkMode_t;
197
198 /** Insert extra arbitration slots to increase channel arbitration priority. */
199 typedef enum {
200 ldmaCfgArbSlotsAs1 = _LDMA_CH_CFG_ARBSLOTS_ONE, /**< One arbitration slot selected. */
201 ldmaCfgArbSlotsAs2 = _LDMA_CH_CFG_ARBSLOTS_TWO, /**< Two arbitration slots selected. */
202 ldmaCfgArbSlotsAs4 = _LDMA_CH_CFG_ARBSLOTS_FOUR, /**< Four arbitration slots selected. */
203 ldmaCfgArbSlotsAs8 = _LDMA_CH_CFG_ARBSLOTS_EIGHT /**< Eight arbitration slots selected. */
204 } LDMA_CfgArbSlots_t;
205
206 /** Source address increment sign. */
207 typedef enum {
208 ldmaCfgSrcIncSignPos = _LDMA_CH_CFG_SRCINCSIGN_POSITIVE, /**< Increment source address. */
209 ldmaCfgSrcIncSignNeg = _LDMA_CH_CFG_SRCINCSIGN_NEGATIVE /**< Decrement source address. */
210 } LDMA_CfgSrcIncSign_t;
211
212 /** Destination address increment sign. */
213 typedef enum {
214 ldmaCfgDstIncSignPos = _LDMA_CH_CFG_DSTINCSIGN_POSITIVE, /**< Increment destination address. */
215 ldmaCfgDstIncSignNeg = _LDMA_CH_CFG_DSTINCSIGN_NEGATIVE /**< Decrement destination address. */
216 } LDMA_CfgDstIncSign_t;
217
218 #if defined(_LDMA_CH_CFG_STRUCTBUSPORT_MASK)
219 /** Structure fetch operation bus port. */
220 typedef enum {
221 ldmaCfgStructBusPort0 = _LDMA_CH_CFG_STRUCTBUSPORT_AHBM0, /**< AHB Master 0 port. */
222 ldmaCfgStructBusPort1 = _LDMA_CH_CFG_STRUCTBUSPORT_AHBM1 /**< AHB Master 1 port. */
223 } LDMA_CfgStructBusPort_t;
224 #endif
225
226 #if defined(_LDMA_CH_CFG_SRCBUSPORT_MASK)
227 /** Source operation bus port. */
228 typedef enum {
229 ldmaCfgSrcBusPort0 = _LDMA_CH_CFG_SRCBUSPORT_AHBM0, /**< AHB Master 0 port. */
230 ldmaCfgSrcBusPort1 = _LDMA_CH_CFG_SRCBUSPORT_AHBM1 /**< AHB Master 1 port. */
231 } LDMA_CfgSrcBusPort_t;
232 #endif
233
234 #if defined(_LDMA_CH_CFG_DSTBUSPORT_MASK)
235 /** Destination operation bus port. */
236 typedef enum {
237 ldmaCfgDstBusPort0 = _LDMA_CH_CFG_DSTBUSPORT_AHBM0, /**< AHB Master 0 port. */
238 ldmaCfgDstBusPort1 = _LDMA_CH_CFG_DSTBUSPORT_AHBM1 /**< AHB Master 1 port. */
239 } LDMA_CfgDstBusPort_t;
240 #endif
241
242 #if defined(_LDMA_CH_CTRL_EXTEND_MASK)
243 /** Rules table mode (interleaving destination). */
244 typedef enum {
245 ldmaIlModeAbsolute = _LDMA_CH_XCTRL_ILMODE_ABSOLUTE, /**< Address by value in rules. Size of WORD */
246 ldmaIlModeRelative16 = _LDMA_CH_XCTRL_ILMODE_RELATIVE16, /**< Address by adding rules to DST. size of HALFWORD */
247 ldmaIlModeRelative8 = _LDMA_CH_XCTRL_ILMODE_RELATIVE8 /**< Address by adding rules to DST. size of BYTE */
248 } LDMA_RulesTblMode_t;
249 #endif
250
251 #if defined(LDMAXBAR_COUNT) && (LDMAXBAR_COUNT > 0)
252 /** Peripherals that can trigger LDMA transfers. */
253 typedef enum {
254 ldmaPeripheralSignal_NONE = LDMAXBAR_CH_REQSEL_SOURCESEL_NONE, ///< No peripheral selected for DMA triggering.
255 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_LDMAXBARPRSREQ0
256 ldmaPeripheralSignal_LDMAXBAR_PRSREQ0 = LDMAXBAR_CH_REQSEL_SIGSEL_LDMAXBARPRSREQ0 | LDMAXBAR_CH_REQSEL_SOURCESEL_LDMAXBAR, ///< Trigger on PRS REQ0.
257 #endif
258 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_LDMAXBARPRSREQ1
259 ldmaPeripheralSignal_LDMAXBAR_PRSREQ1 = LDMAXBAR_CH_REQSEL_SIGSEL_LDMAXBARPRSREQ1 | LDMAXBAR_CH_REQSEL_SOURCESEL_LDMAXBAR, ///< Trigger on PRS REQ1.
260 #endif
261 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC0
262 ldmaPeripheralSignal_TIMER0_CC0 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC0 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER0, ///< Trigger on TIMER0_CC0.
263 #endif
264 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC1
265 ldmaPeripheralSignal_TIMER0_CC1 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC1 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER0, ///< Trigger on TIMER0_CC1.
266 #endif
267 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC2
268 ldmaPeripheralSignal_TIMER0_CC2 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC2 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER0, ///< Trigger on TIMER0_CC2.
269 #endif
270 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0UFOF
271 ldmaPeripheralSignal_TIMER0_UFOF = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0UFOF | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER0, ///< Trigger on TIMER0_UFOF.
272 #endif
273 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC0
274 ldmaPeripheralSignal_TIMER1_CC0 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC0 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER1, ///< Trigger on TIMER1_CC0.
275 #endif
276 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC1
277 ldmaPeripheralSignal_TIMER1_CC1 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC1 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER1, ///< Trigger on TIMER1_CC1.
278 #endif
279 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC2
280 ldmaPeripheralSignal_TIMER1_CC2 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC2 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER1, ///< Trigger on TIMER1_CC2.
281 #endif
282 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1UFOF
283 ldmaPeripheralSignal_TIMER1_UFOF = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1UFOF | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER1, ///< Trigger on TIMER1_UFOF.
284 #endif
285 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART0RXDATAV
286 ldmaPeripheralSignal_USART0_RXDATAV = LDMAXBAR_CH_REQSEL_SIGSEL_USART0RXDATAV | LDMAXBAR_CH_REQSEL_SOURCESEL_USART0, ///< Trigger on USART0_RXDATAV.
287 #endif
288 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART0RXDATAVRIGHT
289 ldmaPeripheralSignal_USART0_RXDATAVRIGHT = LDMAXBAR_CH_REQSEL_SIGSEL_USART0RXDATAVRIGHT | LDMAXBAR_CH_REQSEL_SOURCESEL_USART0,///< Trigger on USART0_RXDATAVRIGHT.
290 #endif
291 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXBL
292 ldmaPeripheralSignal_USART0_TXBL = LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXBL | LDMAXBAR_CH_REQSEL_SOURCESEL_USART0, ///< Trigger on USART0_TXBL.
293 #endif
294 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXBLRIGHT
295 ldmaPeripheralSignal_USART0_TXBLRIGHT = LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXBLRIGHT | LDMAXBAR_CH_REQSEL_SOURCESEL_USART0, ///< Trigger on USART0_TXBLRIGHT.
296 #endif
297 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXEMPTY
298 ldmaPeripheralSignal_USART0_TXEMPTY = LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXEMPTY | LDMAXBAR_CH_REQSEL_SOURCESEL_USART0, ///< Trigger on USART0_TXEMPTY.
299 #endif
300 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART1RXDATAV
301 ldmaPeripheralSignal_USART1_RXDATAV = LDMAXBAR_CH_REQSEL_SIGSEL_USART1RXDATAV | LDMAXBAR_CH_REQSEL_SOURCESEL_USART1, ///< Trigger on USART1_RXDATAV.
302 #endif
303 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT
304 ldmaPeripheralSignal_USART1_RXDATAVRIGHT = LDMAXBAR_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT | LDMAXBAR_CH_REQSEL_SOURCESEL_USART1,///< Trigger on USART1_RXDATAVRIGHT.
305 #endif
306 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART1TXBL
307 ldmaPeripheralSignal_USART1_TXBL = LDMAXBAR_CH_REQSEL_SIGSEL_USART1TXBL | LDMAXBAR_CH_REQSEL_SOURCESEL_USART1, ///< Trigger on USART1_TXBL.
308 #endif
309 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART1TXBLRIGHT
310 ldmaPeripheralSignal_USART1_TXBLRIGHT = LDMAXBAR_CH_REQSEL_SIGSEL_USART1TXBLRIGHT | LDMAXBAR_CH_REQSEL_SOURCESEL_USART1, ///< Trigger on USART1_TXBLRIGHT.
311 #endif
312 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART1TXEMPTY
313 ldmaPeripheralSignal_USART1_TXEMPTY = LDMAXBAR_CH_REQSEL_SIGSEL_USART1TXEMPTY | LDMAXBAR_CH_REQSEL_SOURCESEL_USART1, ///< Trigger on USART1_TXEMPTY.
314 #endif
315 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART2RXDATAV
316 ldmaPeripheralSignal_USART2_RXDATAV = LDMAXBAR_CH_REQSEL_SIGSEL_USART2RXDATAV | LDMAXBAR_CH_REQSEL_SOURCESEL_USART2, ///< Trigger on USART2_RXDATAV.
317 #endif
318 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART2RXDATAVRIGHT
319 ldmaPeripheralSignal_USART2_RXDATAVRIGHT = LDMAXBAR_CH_REQSEL_SIGSEL_USART2RXDATAVRIGHT | LDMAXBAR_CH_REQSEL_SOURCESEL_USART2,///< Trigger on USART2_RXDATAVRIGHT.
320 #endif
321 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART2TXBL
322 ldmaPeripheralSignal_USART2_TXBL = LDMAXBAR_CH_REQSEL_SIGSEL_USART2TXBL | LDMAXBAR_CH_REQSEL_SOURCESEL_USART2, ///< Trigger on USART2_TXBL.
323 #endif
324 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART2TXBLRIGHT
325 ldmaPeripheralSignal_USART2_TXBLRIGHT = LDMAXBAR_CH_REQSEL_SIGSEL_USART2TXBLRIGHT | LDMAXBAR_CH_REQSEL_SOURCESEL_USART2, ///< Trigger on USART2_TXBLRIGHT.
326 #endif
327 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART2TXEMPTY
328 ldmaPeripheralSignal_USART2_TXEMPTY = LDMAXBAR_CH_REQSEL_SIGSEL_USART2TXEMPTY | LDMAXBAR_CH_REQSEL_SOURCESEL_USART2, ///< Trigger on USART2_TXEMPTY.
329 #endif
330 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_I2C0RXDATAV
331 ldmaPeripheralSignal_I2C0_RXDATAV = LDMAXBAR_CH_REQSEL_SIGSEL_I2C0RXDATAV | LDMAXBAR_CH_REQSEL_SOURCESEL_I2C0, ///< Trigger on I2C0_RXDATAV.
332 #endif
333 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_I2C0TXBL
334 ldmaPeripheralSignal_I2C0_TXBL = LDMAXBAR_CH_REQSEL_SIGSEL_I2C0TXBL | LDMAXBAR_CH_REQSEL_SOURCESEL_I2C0, ///< Trigger on I2C0_TXBL.
335 #endif
336 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_I2C1RXDATAV
337 ldmaPeripheralSignal_I2C1_RXDATAV = LDMAXBAR_CH_REQSEL_SIGSEL_I2C1RXDATAV | LDMAXBAR_CH_REQSEL_SOURCESEL_I2C1, ///< Trigger on I2C1_RXDATAV.
338 #endif
339 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_I2C1TXBL
340 ldmaPeripheralSignal_I2C1_TXBL = LDMAXBAR_CH_REQSEL_SIGSEL_I2C1TXBL | LDMAXBAR_CH_REQSEL_SOURCESEL_I2C1, ///< Trigger on I2C1_TXBL.
341 #endif
342 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_AGCRSSI
343 ldmaPeripheralSignal_AGC_RSSI = LDMAXBAR_CH_REQSEL_SIGSEL_AGCRSSI | LDMAXBAR_CH_REQSEL_SOURCESEL_AGC, ///< Trigger on AGC_RSSI.
344 #endif
345 #if defined(LDMAXBAR_CH_REQSEL_SIGSEL_PDMRXDATAV)
346 ldmaPeripheralSignal_PDM_RXDATAV = LDMAXBAR_CH_REQSEL_SIGSEL_PDMRXDATAV | LDMAXBAR_CH_REQSEL_SOURCESEL_PDM, ///< Trigger on PDM_RXDATAV.
347 #endif
348 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERBOF
349 ldmaPeripheralSignal_PROTIMER_BOF = LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERBOF | LDMAXBAR_CH_REQSEL_SOURCESEL_PROTIMER, ///< Trigger on PROTIMER_BOF.
350 #endif
351 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC0
352 ldmaPeripheralSignal_PROTIMER_CC0 = LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC0 | LDMAXBAR_CH_REQSEL_SOURCESEL_PROTIMER, ///< Trigger on PROTIMER_CC0.
353 #endif
354 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC1
355 ldmaPeripheralSignal_PROTIMER_CC1 = LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC1 | LDMAXBAR_CH_REQSEL_SOURCESEL_PROTIMER, ///< Trigger on PROTIMER_CC1.
356 #endif
357 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC2
358 ldmaPeripheralSignal_PROTIMER_CC2 = LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC2 | LDMAXBAR_CH_REQSEL_SOURCESEL_PROTIMER, ///< Trigger on PROTIMER_CC2.
359 #endif
360 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC3
361 ldmaPeripheralSignal_PROTIMER_CC3 = LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC3 | LDMAXBAR_CH_REQSEL_SOURCESEL_PROTIMER, ///< Trigger on PROTIMER_CC3.
362 #endif
363 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC4
364 ldmaPeripheralSignal_PROTIMER_CC4 = LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC4 | LDMAXBAR_CH_REQSEL_SOURCESEL_PROTIMER, ///< Trigger on PROTIMER_CC4.
365 #endif
366 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERPOF
367 ldmaPeripheralSignal_PROTIMER_POF = LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERPOF | LDMAXBAR_CH_REQSEL_SOURCESEL_PROTIMER, ///< Trigger on PROTIMER_POF.
368 #endif
369 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERWOF
370 ldmaPeripheralSignal_PROTIMER_WOF = LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERWOF | LDMAXBAR_CH_REQSEL_SOURCESEL_PROTIMER, ///< Trigger on PROTIMER_WOF.
371 #endif
372 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_MODEMDEBUG
373 ldmaPeripheralSignal_MODEM_DEBUG = LDMAXBAR_CH_REQSEL_SIGSEL_MODEMDEBUG | LDMAXBAR_CH_REQSEL_SOURCESEL_MODEM, ///< Trigger on MODEM_DEBUG.
374 #endif
375 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_IADC0IADC_SCAN
376 ldmaPeripheralSignal_IADC0_IADC_SCAN = LDMAXBAR_CH_REQSEL_SIGSEL_IADC0IADC_SCAN | LDMAXBAR_CH_REQSEL_SOURCESEL_IADC0, ///< Trigger on IADC0_IADC_SCAN.
377 #endif
378 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_IADC0IADC_SINGLE
379 ldmaPeripheralSignal_IADC0_IADC_SINGLE = LDMAXBAR_CH_REQSEL_SIGSEL_IADC0IADC_SINGLE | LDMAXBAR_CH_REQSEL_SOURCESEL_IADC0, ///< Trigger on IADC0_IADC_SINGLE.
380 #endif
381 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_MSCWDATA
382 ldmaPeripheralSignal_MSC_WDATA = LDMAXBAR_CH_REQSEL_SIGSEL_MSCWDATA | LDMAXBAR_CH_REQSEL_SOURCESEL_MSC, ///< Trigger on MSC_WDATA.
383 #endif
384 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC0
385 ldmaPeripheralSignal_TIMER2_CC0 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC0 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER2, ///< Trigger on TIMER2_CC0.
386 #endif
387 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC1
388 ldmaPeripheralSignal_TIMER2_CC1 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC1 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER2, ///< Trigger on TIMER2_CC1.
389 #endif
390 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC2
391 ldmaPeripheralSignal_TIMER2_CC2 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC2 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER2, ///< Trigger on TIMER2_CC2.
392 #endif
393 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2UFOF
394 ldmaPeripheralSignal_TIMER2_UFOF = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2UFOF | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER2, ///< Trigger on TIMER2_UFOF.
395 #endif
396 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC0
397 ldmaPeripheralSignal_TIMER3_CC0 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC0 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER3, ///< Trigger on TIMER3_CC0.
398 #endif
399 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC1
400 ldmaPeripheralSignal_TIMER3_CC1 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC1 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER3, ///< Trigger on TIMER3_CC1.
401 #endif
402 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC2
403 ldmaPeripheralSignal_TIMER3_CC2 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC2 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER3, ///< Trigger on TIMER3_CC2.
404 #endif
405 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3UFOF
406 ldmaPeripheralSignal_TIMER3_UFOF = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3UFOF | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER3, ///< Trigger on TIMER3_UFOF.
407 #endif
408 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER5CC0
409 ldmaPeripheralSignal_TIMER5_CC0 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER5CC0 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER5, ///< Trigger on TIMER5_CC0.
410 #endif
411 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER5CC1
412 ldmaPeripheralSignal_TIMER5_CC1 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER5CC1 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER5, ///< Trigger on TIMER5_CC1.
413 #endif
414 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER5CC2
415 ldmaPeripheralSignal_TIMER5_CC2 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER5CC2 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER5, ///< Trigger on TIMER5_CC2.
416 #endif
417 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER5UFOF
418 ldmaPeripheralSignal_TIMER5_UFOF = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER5UFOF | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER5, ///< Trigger on TIMER5_UFOF.
419 #endif
420 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER6CC0
421 ldmaPeripheralSignal_TIMER6_CC0 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER6CC0 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER6, ///< Trigger on TIMER6_CC0.
422 #endif
423 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER6CC1
424 ldmaPeripheralSignal_TIMER6_CC1 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER6CC1 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER6, ///< Trigger on TIMER6_CC1.
425 #endif
426 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER6CC2
427 ldmaPeripheralSignal_TIMER6_CC2 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER6CC2 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER6, ///< Trigger on TIMER6_CC2.
428 #endif
429 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER6UFOF
430 ldmaPeripheralSignal_TIMER6_UFOF = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER6UFOF | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER6, ///< Trigger on TIMER6_UFOF.
431 #endif
432 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER7CC0
433 ldmaPeripheralSignal_TIMER7_CC0 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER7CC0 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER7, ///< Trigger on TIMER7_CC0.
434 #endif
435 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER7CC1
436 ldmaPeripheralSignal_TIMER7_CC1 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER7CC1 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER7, ///< Trigger on TIMER7_CC1.
437 #endif
438 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER7CC2
439 ldmaPeripheralSignal_TIMER7_CC2 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER7CC2 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER7, ///< Trigger on TIMER7_CC2.
440 #endif
441 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER7UFOF
442 ldmaPeripheralSignal_TIMER7_UFOF = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER7UFOF | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER7, ///< Trigger on TIMER7_UFOF.
443 #endif
444 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_LCD
445 ldmaPeripheralSignal_LCD = LDMAXBAR_CH_REQSEL_SIGSEL_LCD | LDMAXBAR_CH_REQSEL_SOURCESEL_LCD,
446 #endif
447 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC0
448 ldmaPeripheralSignal_TIMER4_CC0 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC0 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER4, ///< Trigger on TIMER4_CC0.
449 #endif
450 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC1
451 ldmaPeripheralSignal_TIMER4_CC1 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC1 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER4, ///< Trigger on TIMER4_CC1.
452 #endif
453 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC2
454 ldmaPeripheralSignal_TIMER4_CC2 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC2 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER4, ///< Trigger on TIMER4_CC2.
455 #endif
456 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4UFOF
457 ldmaPeripheralSignal_TIMER4_UFOF = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4UFOF | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER4, ///< Trigger on TIMER4_UFOF.
458 #endif
459 #if defined(LDMAXBAR_CH_REQSEL_SIGSEL_VDAC0CH0_REQ)
460 ldmaPeripheralSignal_VDAC0CH0REQ = LDMAXBAR_CH_REQSEL_SIGSEL_VDAC0CH0_REQ | LDMAXBAR_CH_REQSEL_SOURCESEL_VDAC0, ///< Trigger on VDAC0_CH0REQ.
461 #endif
462 #if defined(LDMAXBAR_CH_REQSEL_SIGSEL_VDAC0CH1_REQ)
463 ldmaPeripheralSignal_VDAC0CH1REQ = LDMAXBAR_CH_REQSEL_SIGSEL_VDAC0CH1_REQ | LDMAXBAR_CH_REQSEL_SOURCESEL_VDAC0, ///< Trigger on VDAC0_CH1REQ.
464 #endif
465 #if defined(LDMAXBAR_CH_REQSEL_SIGSEL_VDAC1CH0_REQ)
466 ldmaPeripheralSignal_VDAC1CH0REQ = LDMAXBAR_CH_REQSEL_SIGSEL_VDAC1CH0_REQ | LDMAXBAR_CH_REQSEL_SOURCESEL_VDAC1, ///< Trigger on VDAC1_CH0REQ.
467 #endif
468 #if defined(LDMAXBAR_CH_REQSEL_SIGSEL_VDAC1CH1_REQ)
469 ldmaPeripheralSignal_VDAC1CH1REQ = LDMAXBAR_CH_REQSEL_SIGSEL_VDAC1CH1_REQ | LDMAXBAR_CH_REQSEL_SOURCESEL_VDAC1, ///< Trigger on VDAC1_CH1REQ.
470 #endif
471 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUART0RXFL
472 ldmaPeripheralSignal_EUART0_RXFL = LDMAXBAR_CH_REQSEL_SIGSEL_EUART0RXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUART0, ///< Trigger on EUART0_RXFL.
473 #endif
474 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUART0TXFL
475 ldmaPeripheralSignal_EUART0_TXFL = LDMAXBAR_CH_REQSEL_SIGSEL_EUART0TXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUART0, ///< Trigger on EUART0_TXFL.
476 #endif
477 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUSART0RXFL
478 ldmaPeripheralSignal_EUSART0_RXFL = LDMAXBAR_CH_REQSEL_SIGSEL_EUSART0RXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART0, ///< Trigger on EUSART0_RXFL.
479 #endif
480 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUSART0TXFL
481 ldmaPeripheralSignal_EUSART0_TXFL = LDMAXBAR_CH_REQSEL_SIGSEL_EUSART0TXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART0, ///< Trigger on EUSART0_TXFL.
482 #endif
483 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUSART1RXFL
484 ldmaPeripheralSignal_EUSART1_RXFL = LDMAXBAR_CH_REQSEL_SIGSEL_EUSART1RXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART1, ///< Trigger on EUSART1_RXFL.
485 #endif
486 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUSART1TXFL
487 ldmaPeripheralSignal_EUSART1_TXFL = LDMAXBAR_CH_REQSEL_SIGSEL_EUSART1TXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART1, ///< Trigger on EUSART1_TXFL.
488 #endif
489 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUSART2RXFL
490 ldmaPeripheralSignal_EUSART2_RXFL = LDMAXBAR_CH_REQSEL_SIGSEL_EUSART2RXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART2, ///< Trigger on EUSART2_RXFL.
491 #endif
492 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUSART2TXFL
493 ldmaPeripheralSignal_EUSART2_TXFL = LDMAXBAR_CH_REQSEL_SIGSEL_EUSART2TXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART2, ///< Trigger on EUSART2_TXFL.
494 #endif
495 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUSART3RXFL
496 ldmaPeripheralSignal_EUSART3_RXFL = LDMAXBAR_CH_REQSEL_SIGSEL_EUSART3RXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART3, ///< Trigger on EUSART3_RXFL.
497 #endif
498 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUSART3TXFL
499 ldmaPeripheralSignal_EUSART3_TXFL = LDMAXBAR_CH_REQSEL_SIGSEL_EUSART3TXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART3, ///< Trigger on EUSART3_TXFL.
500 #endif
501 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUSART4RXFL
502 ldmaPeripheralSignal_EUSART4_RXFL = LDMAXBAR_CH_REQSEL_SIGSEL_EUSART4RXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART4, ///< Trigger on EUSART4_RXFL.
503 #endif
504 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUSART4TXFL
505 ldmaPeripheralSignal_EUSART4_TXFL = LDMAXBAR_CH_REQSEL_SIGSEL_EUSART4TXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART4, ///< Trigger on EUSART4_TXFL.
506 #endif
507 #if defined(LDMAXBAR_CH_REQSEL_SIGSEL_LESENSEFIFO)
508 ldmaPeripheralSignal_LESENSE_BUFDATAV = LDMAXBAR_CH_REQSEL_SIGSEL_LESENSEFIFO | LDMAXBAR_CH_REQSEL_SOURCESEL_LESENSE, ///< Trigger on LESENSEFIFO.
509 #endif
510 } LDMA_PeripheralSignal_t;
511
512 #else
513 /** Peripherals that can trigger LDMA transfers. */
514 typedef enum {
515 ldmaPeripheralSignal_NONE = LDMA_CH_REQSEL_SOURCESEL_NONE, ///< No peripheral selected for DMA triggering.
516 #if defined(LDMA_CH_REQSEL_SIGSEL_ADC0SCAN)
517 ldmaPeripheralSignal_ADC0_SCAN = LDMA_CH_REQSEL_SIGSEL_ADC0SCAN | LDMA_CH_REQSEL_SOURCESEL_ADC0, ///< Trigger on ADC0_SCAN.
518 #endif
519 #if defined(LDMA_CH_REQSEL_SIGSEL_ADC0SINGLE)
520 ldmaPeripheralSignal_ADC0_SINGLE = LDMA_CH_REQSEL_SIGSEL_ADC0SINGLE | LDMA_CH_REQSEL_SOURCESEL_ADC0, ///< Trigger on ADC0_SINGLE.
521 #endif
522 #if defined(LDMA_CH_REQSEL_SIGSEL_ADC1SCAN)
523 ldmaPeripheralSignal_ADC1_SCAN = LDMA_CH_REQSEL_SIGSEL_ADC1SCAN | LDMA_CH_REQSEL_SOURCESEL_ADC1, ///< Trigger on ADC1_SCAN.
524 #endif
525 #if defined(LDMA_CH_REQSEL_SIGSEL_ADC1SINGLE)
526 ldmaPeripheralSignal_ADC1_SINGLE = LDMA_CH_REQSEL_SIGSEL_ADC1SINGLE | LDMA_CH_REQSEL_SOURCESEL_ADC1, ///< Trigger on ADC1_SINGLE.
527 #endif
528 #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0RD)
529 ldmaPeripheralSignal_CRYPTO_DATA0RD = LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0RD | LDMA_CH_REQSEL_SOURCESEL_CRYPTO, ///< Trigger on CRYPTO_DATA0RD.
530 #endif
531 #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0WR)
532 ldmaPeripheralSignal_CRYPTO_DATA0WR = LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0WR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO, ///< Trigger on CRYPTO_DATA0WR.
533 #endif
534 #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0XWR)
535 ldmaPeripheralSignal_CRYPTO_DATA0XWR = LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0XWR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO, ///< Trigger on CRYPTO_DATA0XWR.
536 #endif
537 #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTODATA1RD)
538 ldmaPeripheralSignal_CRYPTO_DATA1RD = LDMA_CH_REQSEL_SIGSEL_CRYPTODATA1RD | LDMA_CH_REQSEL_SOURCESEL_CRYPTO, ///< Trigger on CRYPTO_DATA1RD.
539 #endif
540 #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTODATA1WR)
541 ldmaPeripheralSignal_CRYPTO_DATA1WR = LDMA_CH_REQSEL_SIGSEL_CRYPTODATA1WR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO, ///< Trigger on CRYPTO_DATA1WR.
542 #endif
543 #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0RD)
544 ldmaPeripheralSignal_CRYPTO0_DATA0RD = LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0RD | LDMA_CH_REQSEL_SOURCESEL_CRYPTO0, ///< Trigger on CRYPTO0_DATA0RD.
545 #endif
546 #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0WR)
547 ldmaPeripheralSignal_CRYPTO0_DATA0WR = LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0WR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO0, ///< Trigger on CRYPTO0_DATA0WR.
548 #endif
549 #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0XWR)
550 ldmaPeripheralSignal_CRYPTO0_DATA0XWR = LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0XWR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO0, ///< Trigger on CRYPTO0_DATA0XWR.
551 #endif
552 #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1RD)
553 ldmaPeripheralSignal_CRYPTO0_DATA1RD = LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1RD | LDMA_CH_REQSEL_SOURCESEL_CRYPTO0, ///< Trigger on CRYPTO0_DATA1RD.
554 #endif
555 #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1WR)
556 ldmaPeripheralSignal_CRYPTO0_DATA1WR = LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1WR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO0, ///< Trigger on CRYPTO0_DATA1WR.
557 #endif
558 #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0RD)
559 ldmaPeripheralSignal_CRYPTO1_DATA0RD = LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0RD | LDMA_CH_REQSEL_SOURCESEL_CRYPTO1, ///< Trigger on CRYPTO1_DATA0RD.
560 #endif
561 #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0WR)
562 ldmaPeripheralSignal_CRYPTO1_DATA0WR = LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0WR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO1, ///< Trigger on CRYPTO1_DATA0WR.
563 #endif
564 #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0XWR)
565 ldmaPeripheralSignal_CRYPTO1_DATA0XWR = LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0XWR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO1, ///< Trigger on CRYPTO1_DATA0XWR.
566 #endif
567 #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA1RD)
568 ldmaPeripheralSignal_CRYPTO1_DATA1RD = LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA1RD | LDMA_CH_REQSEL_SOURCESEL_CRYPTO1, ///< Trigger on CRYPTO1_DATA1RD.
569 #endif
570 #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA1WR)
571 ldmaPeripheralSignal_CRYPTO1_DATA1WR = LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA1WR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO1, ///< Trigger on CRYPTO1_DATA1WR.
572 #endif
573 #if defined(LDMA_CH_REQSEL_SIGSEL_CSENBSLN)
574 ldmaPeripheralSignal_CSEN_BSLN = LDMA_CH_REQSEL_SIGSEL_CSENBSLN | LDMA_CH_REQSEL_SOURCESEL_CSEN, ///< Trigger on CSEN_BSLN.
575 #endif
576 #if defined(LDMA_CH_REQSEL_SIGSEL_CSENDATA)
577 ldmaPeripheralSignal_CSEN_DATA = LDMA_CH_REQSEL_SIGSEL_CSENDATA | LDMA_CH_REQSEL_SOURCESEL_CSEN, ///< Trigger on CSEN_DATA.
578 #endif
579 #if defined(LDMA_CH_REQSEL_SIGSEL_EBIPXL0EMPTY)
580 ldmaPeripheralSignal_EBI_PXL0EMPTY = LDMA_CH_REQSEL_SIGSEL_EBIPXL0EMPTY | LDMA_CH_REQSEL_SOURCESEL_EBI, ///< Trigger on EBI_PXL0EMPTY.
581 #endif
582 #if defined(LDMA_CH_REQSEL_SIGSEL_EBIPXL1EMPTY)
583 ldmaPeripheralSignal_EBI_PXL1EMPTY = LDMA_CH_REQSEL_SIGSEL_EBIPXL1EMPTY | LDMA_CH_REQSEL_SOURCESEL_EBI, ///< Trigger on EBI_PXL1EMPTY.
584 #endif
585 #if defined(LDMA_CH_REQSEL_SIGSEL_EBIPXLFULL)
586 ldmaPeripheralSignal_EBI_PXLFULL = LDMA_CH_REQSEL_SIGSEL_EBIPXLFULL | LDMA_CH_REQSEL_SOURCESEL_EBI, ///< Trigger on EBI_PXLFULL.
587 #endif
588 #if defined(LDMA_CH_REQSEL_SIGSEL_EBIDDEMPTY)
589 ldmaPeripheralSignal_EBI_DDEMPTY = LDMA_CH_REQSEL_SIGSEL_EBIDDEMPTY | LDMA_CH_REQSEL_SOURCESEL_EBI, ///< Trigger on EBI_DDEMPTY.
590 #endif
591 #if defined(LDMA_CH_REQSEL_SIGSEL_EBIVSYNC)
592 ldmaPeripheralSignal_EBI_VSYNC = LDMA_CH_REQSEL_SIGSEL_EBIVSYNC | LDMA_CH_REQSEL_SOURCESEL_EBI, ///< Trigger on EBI_VSYNC.
593 #endif
594 #if defined(LDMA_CH_REQSEL_SIGSEL_EBIHSYNC)
595 ldmaPeripheralSignal_EBI_HSYNC = LDMA_CH_REQSEL_SIGSEL_EBIHSYNC | LDMA_CH_REQSEL_SOURCESEL_EBI, ///< Trigger on EBI_HSYNC.
596 #endif
597 #if defined(LDMA_CH_REQSEL_SIGSEL_I2C0RXDATAV)
598 ldmaPeripheralSignal_I2C0_RXDATAV = LDMA_CH_REQSEL_SIGSEL_I2C0RXDATAV | LDMA_CH_REQSEL_SOURCESEL_I2C0, ///< Trigger on I2C0_RXDATAV.
599 #endif
600 #if defined(LDMA_CH_REQSEL_SIGSEL_I2C0TXBL)
601 ldmaPeripheralSignal_I2C0_TXBL = LDMA_CH_REQSEL_SIGSEL_I2C0TXBL | LDMA_CH_REQSEL_SOURCESEL_I2C0, ///< Trigger on I2C0_TXBL.
602 #endif
603 #if defined(LDMA_CH_REQSEL_SIGSEL_I2C1RXDATAV)
604 ldmaPeripheralSignal_I2C1_RXDATAV = LDMA_CH_REQSEL_SIGSEL_I2C1RXDATAV | LDMA_CH_REQSEL_SOURCESEL_I2C1, ///< Trigger on I2C1_RXDATAV.
605 #endif
606 #if defined(LDMA_CH_REQSEL_SIGSEL_I2C1TXBL)
607 ldmaPeripheralSignal_I2C1_TXBL = LDMA_CH_REQSEL_SIGSEL_I2C1TXBL | LDMA_CH_REQSEL_SOURCESEL_I2C1, ///< Trigger on I2C1_TXBL.
608 #endif
609 #if defined(LDMA_CH_REQSEL_SIGSEL_I2C2RXDATAV)
610 ldmaPeripheralSignal_I2C2_RXDATAV = LDMA_CH_REQSEL_SIGSEL_I2C2RXDATAV | LDMA_CH_REQSEL_SOURCESEL_I2C2, ///< Trigger on I2C2_RXDATAV.
611 #endif
612 #if defined(LDMA_CH_REQSEL_SIGSEL_I2C2TXBL)
613 ldmaPeripheralSignal_I2C2_TXBL = LDMA_CH_REQSEL_SIGSEL_I2C2TXBL | LDMA_CH_REQSEL_SOURCESEL_I2C2, ///< Trigger on I2C2_TXBL.
614 #endif
615 #if defined(LDMA_CH_REQSEL_SIGSEL_LESENSEBUFDATAV)
616 ldmaPeripheralSignal_LESENSE_BUFDATAV = LDMA_CH_REQSEL_SIGSEL_LESENSEBUFDATAV | LDMA_CH_REQSEL_SOURCESEL_LESENSE, ///< Trigger on LESENSE_BUFDATAV.
617 #endif
618 #if defined(LDMA_CH_REQSEL_SIGSEL_LEUART0RXDATAV)
619 ldmaPeripheralSignal_LEUART0_RXDATAV = LDMA_CH_REQSEL_SIGSEL_LEUART0RXDATAV | LDMA_CH_REQSEL_SOURCESEL_LEUART0, ///< Trigger on LEUART0_RXDATAV.
620 #endif
621 #if defined(LDMA_CH_REQSEL_SIGSEL_LEUART0TXBL)
622 ldmaPeripheralSignal_LEUART0_TXBL = LDMA_CH_REQSEL_SIGSEL_LEUART0TXBL | LDMA_CH_REQSEL_SOURCESEL_LEUART0, ///< Trigger on LEUART0_TXBL.
623 #endif
624 #if defined(LDMA_CH_REQSEL_SIGSEL_LEUART0TXEMPTY)
625 ldmaPeripheralSignal_LEUART0_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_LEUART0TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_LEUART0, ///< Trigger on LEUART0_TXEMPTY.
626 #endif
627 #if defined(LDMA_CH_REQSEL_SIGSEL_LEUART1RXDATAV)
628 ldmaPeripheralSignal_LEUART1_RXDATAV = LDMA_CH_REQSEL_SIGSEL_LEUART1RXDATAV | LDMA_CH_REQSEL_SOURCESEL_LEUART1, ///< Trigger on LEUART1_RXDATAV.
629 #endif
630 #if defined(LDMA_CH_REQSEL_SIGSEL_LEUART1TXBL)
631 ldmaPeripheralSignal_LEUART1_TXBL = LDMA_CH_REQSEL_SIGSEL_LEUART1TXBL | LDMA_CH_REQSEL_SOURCESEL_LEUART1, ///< Trigger on LEUART1_TXBL.
632 #endif
633 #if defined(LDMA_CH_REQSEL_SIGSEL_LEUART1TXEMPTY)
634 ldmaPeripheralSignal_LEUART1_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_LEUART1TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_LEUART1, ///< Trigger on LEUART1_TXEMPTY.
635 #endif
636 #if defined(LDMA_CH_REQSEL_SIGSEL_MSCWDATA)
637 ldmaPeripheralSignal_MSC_WDATA = LDMA_CH_REQSEL_SIGSEL_MSCWDATA | LDMA_CH_REQSEL_SOURCESEL_MSC, ///< Trigger on MSC_WDATA.
638 #endif
639 #if defined(LDMA_CH_REQSEL_SIGSEL_PDMRXDATAV)
640 ldmaPeripheralSignal_PDM_RXDATAV = LDMA_CH_REQSEL_SIGSEL_PDMRXDATAV | LDMA_CH_REQSEL_SOURCESEL_PDM, ///< Trigger on PDM_RXDATAV.
641 #endif
642 #if defined(LDMA_CH_REQSEL_SIGSEL_PRSREQ0)
643 ldmaPeripheralSignal_PRS_REQ0 = LDMA_CH_REQSEL_SIGSEL_PRSREQ0 | LDMA_CH_REQSEL_SOURCESEL_PRS, ///< Trigger on PRS_REQ0.
644 #endif
645 #if defined(LDMA_CH_REQSEL_SIGSEL_PRSREQ1)
646 ldmaPeripheralSignal_PRS_REQ1 = LDMA_CH_REQSEL_SIGSEL_PRSREQ1 | LDMA_CH_REQSEL_SOURCESEL_PRS, ///< Trigger on PRS_REQ1.
647 #endif
648 #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER0CC0)
649 ldmaPeripheralSignal_TIMER0_CC0 = LDMA_CH_REQSEL_SIGSEL_TIMER0CC0 | LDMA_CH_REQSEL_SOURCESEL_TIMER0, ///< Trigger on TIMER0_CC0.
650 #endif
651 #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER0CC1)
652 ldmaPeripheralSignal_TIMER0_CC1 = LDMA_CH_REQSEL_SIGSEL_TIMER0CC1 | LDMA_CH_REQSEL_SOURCESEL_TIMER0, ///< Trigger on TIMER0_CC1.
653 #endif
654 #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER0CC2)
655 ldmaPeripheralSignal_TIMER0_CC2 = LDMA_CH_REQSEL_SIGSEL_TIMER0CC2 | LDMA_CH_REQSEL_SOURCESEL_TIMER0, ///< Trigger on TIMER0_CC2.
656 #endif
657 #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER0UFOF)
658 ldmaPeripheralSignal_TIMER0_UFOF = LDMA_CH_REQSEL_SIGSEL_TIMER0UFOF | LDMA_CH_REQSEL_SOURCESEL_TIMER0, ///< Trigger on TIMER0_UFOF.
659 #endif
660 #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER1CC0)
661 ldmaPeripheralSignal_TIMER1_CC0 = LDMA_CH_REQSEL_SIGSEL_TIMER1CC0 | LDMA_CH_REQSEL_SOURCESEL_TIMER1, ///< Trigger on TIMER1_CC0.
662 #endif
663 #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER1CC1)
664 ldmaPeripheralSignal_TIMER1_CC1 = LDMA_CH_REQSEL_SIGSEL_TIMER1CC1 | LDMA_CH_REQSEL_SOURCESEL_TIMER1, ///< Trigger on TIMER1_CC1.
665 #endif
666 #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER1CC2)
667 ldmaPeripheralSignal_TIMER1_CC2 = LDMA_CH_REQSEL_SIGSEL_TIMER1CC2 | LDMA_CH_REQSEL_SOURCESEL_TIMER1, ///< Trigger on TIMER1_CC2.
668 #endif
669 #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER1CC3)
670 ldmaPeripheralSignal_TIMER1_CC3 = LDMA_CH_REQSEL_SIGSEL_TIMER1CC3 | LDMA_CH_REQSEL_SOURCESEL_TIMER1, ///< Trigger on TIMER1_CC3.
671 #endif
672 #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER1UFOF)
673 ldmaPeripheralSignal_TIMER1_UFOF = LDMA_CH_REQSEL_SIGSEL_TIMER1UFOF | LDMA_CH_REQSEL_SOURCESEL_TIMER1, ///< Trigger on TIMER1_UFOF.
674 #endif
675 #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER2CC0)
676 ldmaPeripheralSignal_TIMER2_CC0 = LDMA_CH_REQSEL_SIGSEL_TIMER2CC0 | LDMA_CH_REQSEL_SOURCESEL_TIMER2, ///< Trigger on TIMER2_CC0.
677 #endif
678 #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER2CC1)
679 ldmaPeripheralSignal_TIMER2_CC1 = LDMA_CH_REQSEL_SIGSEL_TIMER2CC1 | LDMA_CH_REQSEL_SOURCESEL_TIMER2, ///< Trigger on TIMER2_CC1.
680 #endif
681 #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER2CC2)
682 ldmaPeripheralSignal_TIMER2_CC2 = LDMA_CH_REQSEL_SIGSEL_TIMER2CC2 | LDMA_CH_REQSEL_SOURCESEL_TIMER2, ///< Trigger on TIMER2_CC2.
683 #endif
684 #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER2UFOF)
685 ldmaPeripheralSignal_TIMER2_UFOF = LDMA_CH_REQSEL_SIGSEL_TIMER2UFOF | LDMA_CH_REQSEL_SOURCESEL_TIMER2, ///< Trigger on TIMER2_UFOF.
686 #endif
687 #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER3CC0)
688 ldmaPeripheralSignal_TIMER3_CC0 = LDMA_CH_REQSEL_SIGSEL_TIMER3CC0 | LDMA_CH_REQSEL_SOURCESEL_TIMER3, ///< Trigger on TIMER3_CC0.
689 #endif
690 #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER3CC1)
691 ldmaPeripheralSignal_TIMER3_CC1 = LDMA_CH_REQSEL_SIGSEL_TIMER3CC1 | LDMA_CH_REQSEL_SOURCESEL_TIMER3, ///< Trigger on TIMER3_CC1.
692 #endif
693 #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER3CC2)
694 ldmaPeripheralSignal_TIMER3_CC2 = LDMA_CH_REQSEL_SIGSEL_TIMER3CC2 | LDMA_CH_REQSEL_SOURCESEL_TIMER3, ///< Trigger on TIMER3_CC2.
695 #endif
696 #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER3UFOF)
697 ldmaPeripheralSignal_TIMER3_UFOF = LDMA_CH_REQSEL_SIGSEL_TIMER3UFOF | LDMA_CH_REQSEL_SOURCESEL_TIMER3, ///< Trigger on TIMER3_UFOF.
698 #endif
699 #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER4CC0)
700 ldmaPeripheralSignal_TIMER4_CC0 = LDMA_CH_REQSEL_SIGSEL_TIMER4CC0 | LDMA_CH_REQSEL_SOURCESEL_TIMER4, ///< Trigger on TIMER4_CC0.
701 #endif
702 #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER4CC1)
703 ldmaPeripheralSignal_TIMER4_CC1 = LDMA_CH_REQSEL_SIGSEL_TIMER4CC1 | LDMA_CH_REQSEL_SOURCESEL_TIMER4, ///< Trigger on TIMER4_CC1.
704 #endif
705 #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER4CC2)
706 ldmaPeripheralSignal_TIMER4_CC2 = LDMA_CH_REQSEL_SIGSEL_TIMER4CC2 | LDMA_CH_REQSEL_SOURCESEL_TIMER4, ///< Trigger on TIMER4_CC2.
707 #endif
708 #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER4UFOF)
709 ldmaPeripheralSignal_TIMER4_UFOF = LDMA_CH_REQSEL_SIGSEL_TIMER4UFOF | LDMA_CH_REQSEL_SOURCESEL_TIMER4, ///< Trigger on TIMER4_UFOF.
710 #endif
711 #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER5CC0)
712 ldmaPeripheralSignal_TIMER5_CC0 = LDMA_CH_REQSEL_SIGSEL_TIMER5CC0 | LDMA_CH_REQSEL_SOURCESEL_TIMER5, ///< Trigger on TIMER5_CC0.
713 #endif
714 #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER5CC1)
715 ldmaPeripheralSignal_TIMER5_CC1 = LDMA_CH_REQSEL_SIGSEL_TIMER5CC1 | LDMA_CH_REQSEL_SOURCESEL_TIMER5, ///< Trigger on TIMER5_CC1.
716 #endif
717 #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER5CC2)
718 ldmaPeripheralSignal_TIMER5_CC2 = LDMA_CH_REQSEL_SIGSEL_TIMER5CC2 | LDMA_CH_REQSEL_SOURCESEL_TIMER5, ///< Trigger on TIMER5_CC2.
719 #endif
720 #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER5UFOF)
721 ldmaPeripheralSignal_TIMER5_UFOF = LDMA_CH_REQSEL_SIGSEL_TIMER5UFOF | LDMA_CH_REQSEL_SOURCESEL_TIMER5, ///< Trigger on TIMER5_UFOF.
722 #endif
723 #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER6CC0)
724 ldmaPeripheralSignal_TIMER6_CC0 = LDMA_CH_REQSEL_SIGSEL_TIMER6CC0 | LDMA_CH_REQSEL_SOURCESEL_TIMER6, ///< Trigger on TIMER6_CC0.
725 #endif
726 #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER6CC1)
727 ldmaPeripheralSignal_TIMER6_CC1 = LDMA_CH_REQSEL_SIGSEL_TIMER6CC1 | LDMA_CH_REQSEL_SOURCESEL_TIMER6, ///< Trigger on TIMER6_CC1.
728 #endif
729 #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER6CC2)
730 ldmaPeripheralSignal_TIMER6_CC2 = LDMA_CH_REQSEL_SIGSEL_TIMER6CC2 | LDMA_CH_REQSEL_SOURCESEL_TIMER6, ///< Trigger on TIMER6_CC2.
731 #endif
732 #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER6UFOF)
733 ldmaPeripheralSignal_TIMER6_UFOF = LDMA_CH_REQSEL_SIGSEL_TIMER6UFOF | LDMA_CH_REQSEL_SOURCESEL_TIMER6, ///< Trigger on TIMER6_UFOF.
734 #endif
735 #if defined(LDMA_CH_REQSEL_SIGSEL_UART0RXDATAV)
736 ldmaPeripheralSignal_UART0_RXDATAV = LDMA_CH_REQSEL_SIGSEL_UART0RXDATAV | LDMA_CH_REQSEL_SOURCESEL_UART0, ///< Trigger on UART0_RXDATAV.
737 #endif
738 #if defined(LDMA_CH_REQSEL_SIGSEL_UART0TXBL)
739 ldmaPeripheralSignal_UART0_TXBL = LDMA_CH_REQSEL_SIGSEL_UART0TXBL | LDMA_CH_REQSEL_SOURCESEL_UART0, ///< Trigger on UART0_TXBL.
740 #endif
741 #if defined(LDMA_CH_REQSEL_SIGSEL_UART0TXEMPTY)
742 ldmaPeripheralSignal_UART0_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_UART0TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_UART0, ///< Trigger on UART0_TXEMPTY.
743 #endif
744 #if defined(LDMA_CH_REQSEL_SIGSEL_UART1RXDATAV)
745 ldmaPeripheralSignal_UART1_RXDATAV = LDMA_CH_REQSEL_SIGSEL_UART1RXDATAV | LDMA_CH_REQSEL_SOURCESEL_UART1, ///< Trigger on UART1_RXDATAV.
746 #endif
747 #if defined(LDMA_CH_REQSEL_SIGSEL_UART1TXBL)
748 ldmaPeripheralSignal_UART1_TXBL = LDMA_CH_REQSEL_SIGSEL_UART1TXBL | LDMA_CH_REQSEL_SOURCESEL_UART1, ///< Trigger on UART1_TXBL.
749 #endif
750 #if defined(LDMA_CH_REQSEL_SIGSEL_UART1TXEMPTY)
751 ldmaPeripheralSignal_UART1_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_UART1TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_UART1, ///< Trigger on UART1_TXEMPTY.
752 #endif
753 #if defined(LDMA_CH_REQSEL_SIGSEL_USART0RXDATAV)
754 ldmaPeripheralSignal_USART0_RXDATAV = LDMA_CH_REQSEL_SIGSEL_USART0RXDATAV | LDMA_CH_REQSEL_SOURCESEL_USART0, ///< Trigger on USART0_RXDATAV.
755 #endif
756 #if defined(LDMA_CH_REQSEL_SIGSEL_USART0TXBL)
757 ldmaPeripheralSignal_USART0_TXBL = LDMA_CH_REQSEL_SIGSEL_USART0TXBL | LDMA_CH_REQSEL_SOURCESEL_USART0, ///< Trigger on USART0_TXBL.
758 #endif
759 #if defined(LDMA_CH_REQSEL_SIGSEL_USART0TXEMPTY)
760 ldmaPeripheralSignal_USART0_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_USART0TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_USART0, ///< Trigger on USART0_TXEMPTY.
761 #endif
762 #if defined(LDMA_CH_REQSEL_SIGSEL_USART1RXDATAV)
763 ldmaPeripheralSignal_USART1_RXDATAV = LDMA_CH_REQSEL_SIGSEL_USART1RXDATAV | LDMA_CH_REQSEL_SOURCESEL_USART1, ///< Trigger on USART1_RXDATAV.
764 #endif
765 #if defined(LDMA_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT)
766 ldmaPeripheralSignal_USART1_RXDATAVRIGHT = LDMA_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT | LDMA_CH_REQSEL_SOURCESEL_USART1, ///< Trigger on USART1_RXDATAVRIGHT.
767 #endif
768 #if defined(LDMA_CH_REQSEL_SIGSEL_USART1TXBL)
769 ldmaPeripheralSignal_USART1_TXBL = LDMA_CH_REQSEL_SIGSEL_USART1TXBL | LDMA_CH_REQSEL_SOURCESEL_USART1, ///< Trigger on USART1_TXBL.
770 #endif
771 #if defined(LDMA_CH_REQSEL_SIGSEL_USART1TXBLRIGHT)
772 ldmaPeripheralSignal_USART1_TXBLRIGHT = LDMA_CH_REQSEL_SIGSEL_USART1TXBLRIGHT | LDMA_CH_REQSEL_SOURCESEL_USART1, ///< Trigger on USART1_TXBLRIGHT.
773 #endif
774 #if defined(LDMA_CH_REQSEL_SIGSEL_USART1TXEMPTY)
775 ldmaPeripheralSignal_USART1_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_USART1TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_USART1, ///< Trigger on USART1_TXEMPTY.
776 #endif
777 #if defined(LDMA_CH_REQSEL_SIGSEL_USART2RXDATAV)
778 ldmaPeripheralSignal_USART2_RXDATAV = LDMA_CH_REQSEL_SIGSEL_USART2RXDATAV | LDMA_CH_REQSEL_SOURCESEL_USART2, ///< Trigger on USART2_RXDATAV.
779 #endif
780 #if defined(LDMA_CH_REQSEL_SIGSEL_USART2TXBL)
781 ldmaPeripheralSignal_USART2_TXBL = LDMA_CH_REQSEL_SIGSEL_USART2TXBL | LDMA_CH_REQSEL_SOURCESEL_USART2, ///< Trigger on USART2_TXBL.
782 #endif
783 #if defined(LDMA_CH_REQSEL_SIGSEL_USART2TXEMPTY)
784 ldmaPeripheralSignal_USART2_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_USART2TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_USART2, ///< Trigger on USART2_TXEMPTY.
785 #endif
786 #if defined(LDMA_CH_REQSEL_SIGSEL_USART3RXDATAV)
787 ldmaPeripheralSignal_USART3_RXDATAV = LDMA_CH_REQSEL_SIGSEL_USART3RXDATAV | LDMA_CH_REQSEL_SOURCESEL_USART3, ///< Trigger on USART3_RXDATAV.
788 #endif
789 #if defined(LDMA_CH_REQSEL_SIGSEL_USART3RXDATAVRIGHT)
790 ldmaPeripheralSignal_USART3_RXDATAVRIGHT = LDMA_CH_REQSEL_SIGSEL_USART3RXDATAVRIGHT | LDMA_CH_REQSEL_SOURCESEL_USART3, ///< Trigger on USART3_RXDATAVRIGHT.
791 #endif
792 #if defined(LDMA_CH_REQSEL_SIGSEL_USART3TXBL)
793 ldmaPeripheralSignal_USART3_TXBL = LDMA_CH_REQSEL_SIGSEL_USART3TXBL | LDMA_CH_REQSEL_SOURCESEL_USART3, ///< Trigger on USART3_TXBL.
794 #endif
795 #if defined(LDMA_CH_REQSEL_SIGSEL_USART3TXBLRIGHT)
796 ldmaPeripheralSignal_USART3_TXBLRIGHT = LDMA_CH_REQSEL_SIGSEL_USART3TXBLRIGHT | LDMA_CH_REQSEL_SOURCESEL_USART3, ///< Trigger on USART3_TXBLRIGHT.
797 #endif
798 #if defined(LDMA_CH_REQSEL_SIGSEL_USART3TXEMPTY)
799 ldmaPeripheralSignal_USART3_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_USART3TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_USART3, ///< Trigger on USART3_TXEMPTY.
800 #endif
801 #if defined(LDMA_CH_REQSEL_SIGSEL_USART4RXDATAV)
802 ldmaPeripheralSignal_USART4_RXDATAV = LDMA_CH_REQSEL_SIGSEL_USART4RXDATAV | LDMA_CH_REQSEL_SOURCESEL_USART4, ///< Trigger on USART4_RXDATAV.
803 #endif
804 #if defined(LDMA_CH_REQSEL_SIGSEL_USART4RXDATAVRIGHT)
805 ldmaPeripheralSignal_USART4_RXDATAVRIGHT = LDMA_CH_REQSEL_SIGSEL_USART4RXDATAVRIGHT | LDMA_CH_REQSEL_SOURCESEL_USART4, ///< Trigger on USART4_RXDATAVRIGHT.
806 #endif
807 #if defined(LDMA_CH_REQSEL_SIGSEL_USART4TXBL)
808 ldmaPeripheralSignal_USART4_TXBL = LDMA_CH_REQSEL_SIGSEL_USART4TXBL | LDMA_CH_REQSEL_SOURCESEL_USART4, ///< Trigger on USART4_TXBL.
809 #endif
810 #if defined(LDMA_CH_REQSEL_SIGSEL_USART4TXBLRIGHT)
811 ldmaPeripheralSignal_USART4_TXBLRIGHT = LDMA_CH_REQSEL_SIGSEL_USART4TXBLRIGHT | LDMA_CH_REQSEL_SOURCESEL_USART4, ///< Trigger on USART4_TXBLRIGHT.
812 #endif
813 #if defined(LDMA_CH_REQSEL_SIGSEL_USART4TXEMPTY)
814 ldmaPeripheralSignal_USART4_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_USART4TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_USART4, ///< Trigger on USART4_TXEMPTY.
815 #endif
816 #if defined(LDMA_CH_REQSEL_SIGSEL_USART5RXDATAV)
817 ldmaPeripheralSignal_USART5_RXDATAV = LDMA_CH_REQSEL_SIGSEL_USART5RXDATAV | LDMA_CH_REQSEL_SOURCESEL_USART5, ///< Trigger on USART5_RXDATAV.
818 #endif
819 #if defined(LDMA_CH_REQSEL_SIGSEL_USART5TXBL)
820 ldmaPeripheralSignal_USART5_TXBL = LDMA_CH_REQSEL_SIGSEL_USART5TXBL | LDMA_CH_REQSEL_SOURCESEL_USART5, ///< Trigger on USART5_TXBL.
821 #endif
822 #if defined(LDMA_CH_REQSEL_SIGSEL_USART5TXEMPTY)
823 ldmaPeripheralSignal_USART5_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_USART5TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_USART5, ///< Trigger on USART5_TXEMPTY.
824 #endif
825 #if defined(LDMA_CH_REQSEL_SIGSEL_VDAC0CH0)
826 ldmaPeripheralSignal_VDAC0_CH0 = LDMA_CH_REQSEL_SIGSEL_VDAC0CH0 | LDMA_CH_REQSEL_SOURCESEL_VDAC0, ///< Trigger on VDAC0_CH0.
827 #endif
828 #if defined(LDMA_CH_REQSEL_SIGSEL_VDAC0CH1)
829 ldmaPeripheralSignal_VDAC0_CH1 = LDMA_CH_REQSEL_SIGSEL_VDAC0CH1 | LDMA_CH_REQSEL_SOURCESEL_VDAC0, ///< Trigger on VDAC0_CH1.
830 #endif
831 #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER0CC0)
832 ldmaPeripheralSignal_WTIMER0_CC0 = LDMA_CH_REQSEL_SIGSEL_WTIMER0CC0 | LDMA_CH_REQSEL_SOURCESEL_WTIMER0, ///< Trigger on WTIMER0_CC0.
833 #endif
834 #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER0CC1)
835 ldmaPeripheralSignal_WTIMER0_CC1 = LDMA_CH_REQSEL_SIGSEL_WTIMER0CC1 | LDMA_CH_REQSEL_SOURCESEL_WTIMER0, ///< Trigger on WTIMER0_CC1.
836 #endif
837 #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER0CC2)
838 ldmaPeripheralSignal_WTIMER0_CC2 = LDMA_CH_REQSEL_SIGSEL_WTIMER0CC2 | LDMA_CH_REQSEL_SOURCESEL_WTIMER0, ///< Trigger on WTIMER0_CC2.
839 #endif
840 #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER0UFOF)
841 ldmaPeripheralSignal_WTIMER0_UFOF = LDMA_CH_REQSEL_SIGSEL_WTIMER0UFOF | LDMA_CH_REQSEL_SOURCESEL_WTIMER0, ///< Trigger on WTIMER0_UFOF.
842 #endif
843 #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER1CC0)
844 ldmaPeripheralSignal_WTIMER1_CC0 = LDMA_CH_REQSEL_SIGSEL_WTIMER1CC0 | LDMA_CH_REQSEL_SOURCESEL_WTIMER1, ///< Trigger on WTIMER1_CC0.
845 #endif
846 #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER1CC1)
847 ldmaPeripheralSignal_WTIMER1_CC1 = LDMA_CH_REQSEL_SIGSEL_WTIMER1CC1 | LDMA_CH_REQSEL_SOURCESEL_WTIMER1, ///< Trigger on WTIMER1_CC1.
848 #endif
849 #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER1CC2)
850 ldmaPeripheralSignal_WTIMER1_CC2 = LDMA_CH_REQSEL_SIGSEL_WTIMER1CC2 | LDMA_CH_REQSEL_SOURCESEL_WTIMER1, ///< Trigger on WTIMER1_CC2.
851 #endif
852 #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER1CC3)
853 ldmaPeripheralSignal_WTIMER1_CC3 = LDMA_CH_REQSEL_SIGSEL_WTIMER1CC3 | LDMA_CH_REQSEL_SOURCESEL_WTIMER1, ///< Trigger on WTIMER1_CC3.
854 #endif
855 #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER1UFOF)
856 ldmaPeripheralSignal_WTIMER1_UFOF = LDMA_CH_REQSEL_SIGSEL_WTIMER1UFOF | LDMA_CH_REQSEL_SOURCESEL_WTIMER1, ///< Trigger on WTIMER1_UFOF.
857 #endif
858 #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER2CC0)
859 ldmaPeripheralSignal_WTIMER2_CC0 = LDMA_CH_REQSEL_SIGSEL_WTIMER2CC0 | LDMA_CH_REQSEL_SOURCESEL_WTIMER2, ///< Trigger on WTIMER2_CC0.
860 #endif
861 #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER2CC1)
862 ldmaPeripheralSignal_WTIMER2_CC1 = LDMA_CH_REQSEL_SIGSEL_WTIMER2CC1 | LDMA_CH_REQSEL_SOURCESEL_WTIMER2, ///< Trigger on WTIMER2_CC1.
863 #endif
864 #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER2CC2)
865 ldmaPeripheralSignal_WTIMER2_CC2 = LDMA_CH_REQSEL_SIGSEL_WTIMER2CC2 | LDMA_CH_REQSEL_SOURCESEL_WTIMER2, ///< Trigger on WTIMER2_CC2.
866 #endif
867 #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER2UFOF)
868 ldmaPeripheralSignal_WTIMER2_UFOF = LDMA_CH_REQSEL_SIGSEL_WTIMER2UFOF | LDMA_CH_REQSEL_SOURCESEL_WTIMER2, ///< Trigger on WTIMER2_UFOF.
869 #endif
870 #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER3CC0)
871 ldmaPeripheralSignal_WTIMER3_CC0 = LDMA_CH_REQSEL_SIGSEL_WTIMER3CC0 | LDMA_CH_REQSEL_SOURCESEL_WTIMER3, ///< Trigger on WTIMER3_CC0.
872 #endif
873 #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER3CC1)
874 ldmaPeripheralSignal_WTIMER3_CC1 = LDMA_CH_REQSEL_SIGSEL_WTIMER3CC1 | LDMA_CH_REQSEL_SOURCESEL_WTIMER3, ///< Trigger on WTIMER3_CC1.
875 #endif
876 #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER3CC2)
877 ldmaPeripheralSignal_WTIMER3_CC2 = LDMA_CH_REQSEL_SIGSEL_WTIMER3CC2 | LDMA_CH_REQSEL_SOURCESEL_WTIMER3, ///< Trigger on WTIMER3_CC2.
878 #endif
879 #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER3UFOF)
880 ldmaPeripheralSignal_WTIMER3_UFOF = LDMA_CH_REQSEL_SIGSEL_WTIMER3UFOF | LDMA_CH_REQSEL_SOURCESEL_WTIMER3, ///< Trigger on WTIMER3_UFOF.
881 #endif
882 } LDMA_PeripheralSignal_t;
883 #endif
884
885 /*******************************************************************************
886 ******************************* STRUCTS ***********************************
887 ******************************************************************************/
888
889 /**
890 * @brief
891 * DMA descriptor.
892 * @details
893 * The LDMA DMA controller supports three different DMA descriptors. Each
894 * consists of four WORDs which map directly onto HW control registers for a
895 * given DMA channel. The three descriptor types are XFER, SYNC and WRI.
896 * Refer to the reference manual for further information.
897 */
898 typedef union {
899 /**
900 * TRANSFER DMA descriptor, this is the only descriptor type which can be
901 * used to start a DMA transfer.
902 */
903 struct {
904 uint32_t structType : 2; /**< Set to 0 to select XFER descriptor type. */
905 uint32_t reserved0 : 1; /**< Reserved. */
906 uint32_t structReq : 1; /**< DMA transfer trigger during LINKLOAD. */
907 uint32_t xferCnt : 11; /**< Transfer count minus one. */
908 uint32_t byteSwap : 1; /**< Enable byte swapping transfers. */
909 uint32_t blockSize : 4; /**< Number of unit transfers per arbitration cycle. */
910 uint32_t doneIfs : 1; /**< Generate interrupt when done. */
911 uint32_t reqMode : 1; /**< Block or cycle transfer selector. */
912 uint32_t decLoopCnt : 1; /**< Enable looped transfers. */
913 uint32_t ignoreSrec : 1; /**< Ignore single requests. */
914 uint32_t srcInc : 2; /**< Source address increment unit size. */
915 uint32_t size : 2; /**< DMA transfer unit size. */
916 uint32_t dstInc : 2; /**< Destination address increment unit size. */
917 uint32_t srcAddrMode : 1; /**< Source addressing mode. */
918 uint32_t dstAddrMode : 1; /**< Destination addressing mode. */
919
920 uint32_t srcAddr; /**< DMA source address. */
921 uint32_t dstAddr; /**< DMA destination address. */
922
923 uint32_t linkMode : 1; /**< Select absolute or relative link address. */
924 uint32_t link : 1; /**< Enable LINKLOAD when transfer is done. */
925 int32_t linkAddr : 30; /**< Address of next (linked) descriptor. */
926 } xfer;
927
928 /** SYNCHRONIZE DMA descriptor, used for intra channel transfer
929 * synchronization.
930 */
931 struct {
932 uint32_t structType : 2; /**< Set to 1 to select SYNC descriptor type. */
933 uint32_t reserved0 : 1; /**< Reserved. */
934 uint32_t structReq : 1; /**< DMA transfer trigger during LINKLOAD. */
935 uint32_t xferCnt : 11; /**< Transfer count minus one. */
936 uint32_t byteSwap : 1; /**< Enable byte swapping transfers. */
937 uint32_t blockSize : 4; /**< Number of unit transfers per arbitration cycle. */
938 uint32_t doneIfs : 1; /**< Generate interrupt when done. */
939 uint32_t reqMode : 1; /**< Block or cycle transfer selector. */
940 uint32_t decLoopCnt : 1; /**< Enable looped transfers. */
941 uint32_t ignoreSrec : 1; /**< Ignore single requests. */
942 uint32_t srcInc : 2; /**< Source address increment unit size. */
943 uint32_t size : 2; /**< DMA transfer unit size. */
944 uint32_t dstInc : 2; /**< Destination address increment unit size. */
945 uint32_t srcAddrMode : 1; /**< Source addressing mode. */
946 uint32_t dstAddrMode : 1; /**< Destination addressing mode. */
947
948 uint32_t syncSet : 8; /**< Set bits in LDMA_CTRL.SYNCTRIG register. */
949 uint32_t syncClr : 8; /**< Clear bits in LDMA_CTRL.SYNCTRIG register. */
950 uint32_t reserved1 : 16; /**< Reserved. */
951 #if defined(_LDMA_CH_CTRL_EXTEND_MASK)
952 uint32_t matchEn : 8; /**< Sync trigger match enable. */
953 uint32_t matchVal : 8; /**< Sync trigger match value. */
954 #else
955 uint32_t matchVal : 8; /**< Sync trigger match value. */
956 uint32_t matchEn : 8; /**< Sync trigger match enable. */
957 #endif
958 uint32_t reserved2 : 16; /**< Reserved. */
959
960 uint32_t linkMode : 1; /**< Select absolute or relative link address. */
961 uint32_t link : 1; /**< Enable LINKLOAD when transfer is done. */
962 int32_t linkAddr : 30; /**< Address of next (linked) descriptor. */
963 } sync;
964
965 /** WRITE DMA descriptor, used for write immediate operations. */
966 struct {
967 uint32_t structType : 2; /**< Set to 2 to select WRITE descriptor type. */
968 uint32_t reserved0 : 1; /**< Reserved. */
969 uint32_t structReq : 1; /**< DMA transfer trigger during LINKLOAD. */
970 uint32_t xferCnt : 11; /**< Transfer count minus one. */
971 uint32_t byteSwap : 1; /**< Enable byte swapping transfers. */
972 uint32_t blockSize : 4; /**< Number of unit transfers per arbitration cycle. */
973 uint32_t doneIfs : 1; /**< Generate interrupt when done. */
974 uint32_t reqMode : 1; /**< Block or cycle transfer selector. */
975 uint32_t decLoopCnt : 1; /**< Enable looped transfers. */
976 uint32_t ignoreSrec : 1; /**< Ignore single requests. */
977 uint32_t srcInc : 2; /**< Source address increment unit size. */
978 uint32_t size : 2; /**< DMA transfer unit size. */
979 uint32_t dstInc : 2; /**< Destination address increment unit size. */
980 uint32_t srcAddrMode : 1; /**< Source addressing mode. */
981 uint32_t dstAddrMode : 1; /**< Destination addressing mode. */
982
983 uint32_t immVal; /**< Data to be written at dstAddr. */
984 uint32_t dstAddr; /**< DMA write destination address. */
985
986 uint32_t linkMode : 1; /**< Select absolute or relative link address. */
987 uint32_t link : 1; /**< Enable LINKLOAD when transfer is done. */
988 int32_t linkAddr : 30; /**< Address of next (linked) descriptor. */
989 } wri;
990 } LDMA_Descriptor_t;
991
992 #if defined(_LDMA_CH_CTRL_EXTEND_MASK)
993 /**
994 * @brief
995 * DMA extended descriptor.
996 * @details
997 * The extended descriptor adds additional fields for the extended features
998 * available on the MMLDMA peripheral: destination interleaving and bufferable.
999 * The same three different DMA descriptors supported by the LDMA DMA controller
1000 * are available. Each consists of seven WORDs (instead of four in non-extended
1001 * descriptors) which map directly onto HW control registers for a given DMA
1002 * channel. The three descriptor types are XFER, SYNC and WRI. But the
1003 * extended fields are true only for XFER. The extended fields are the following:
1004 *
1005 * +- +- CTRL
1006 * | Original | SRC
1007 * | Structure | DST
1008 * Extended | +- LINK
1009 * Structure | XCTRL
1010 * | Reserved for future usage
1011 * +- ILSRC
1012 *
1013 * Refer to the reference manual for further information.
1014 */
1015 typedef struct {
1016 uint32_t structType : 2; /**< Set to 0 to select XFER descriptor type. */
1017 uint32_t extend : 1; /**< Extend data structure. */
1018 uint32_t structReq : 1; /**< DMA transfer trigger during LINKLOAD. */
1019 uint32_t xferCnt : 11; /**< Transfer count minus one. */
1020 uint32_t byteSwap : 1; /**< Enable byte swapping transfers. */
1021 uint32_t blockSize : 4; /**< Number of unit transfers per arbitration cycle. */
1022 uint32_t doneIfs : 1; /**< Generate interrupt when done. */
1023 uint32_t reqMode : 1; /**< Block or cycle transfer selector. */
1024 uint32_t decLoopCnt : 1; /**< Enable looped transfers. */
1025 uint32_t ignoreSrec : 1; /**< Ignore single requests. */
1026 uint32_t srcInc : 2; /**< Source address increment unit size. */
1027 uint32_t size : 2; /**< DMA transfer unit size. */
1028 uint32_t dstInc : 2; /**< Destination address increment unit size. */
1029 uint32_t srcAddrMode : 1; /**< Source addressing mode. */
1030 uint32_t dstAddrMode : 1; /**< Destination addressing mode. */
1031
1032 uint32_t srcAddr; /**< DMA source address. */
1033 uint32_t dstAddr; /**< DMA destination address. */
1034
1035 uint32_t linkMode : 1; /**< Select absolute or relative link address. */
1036 uint32_t link : 1; /**< Enable LINKLOAD when transfer is done. */
1037 int32_t linkAddr : 30; /**< Address of next (linked) descriptor. */
1038
1039 uint32_t reserved1 : 4; /**< Reserved */
1040 uint32_t dstIlEn : 1; /**< Destination interleave. */
1041 uint32_t IlMode : 2; /**< Interleave mode. */
1042 uint32_t bufferable : 1; /**< Allow AHB buffering. */
1043 uint32_t reserved2 : 24; /**< Reserved */
1044
1045 uint32_t reserved3; /**< Reserved */
1046 uint32_t IlSrc; /**< DMA rules table base address in memory. */
1047 } LDMA_DescriptorExtend_t;
1048 #endif
1049
1050 /** @brief LDMA initialization configuration structure. */
1051 typedef struct {
1052 uint8_t ldmaInitCtrlNumFixed; /**< Arbitration mode separator. */
1053 uint8_t ldmaInitCtrlSyncPrsClrEn; /**< PRS Synctrig clear enable. */
1054 uint8_t ldmaInitCtrlSyncPrsSetEn; /**< PRS Synctrig set enable. */
1055 uint8_t ldmaInitIrqPriority; /**< LDMA IRQ priority (0..7). */
1056 } LDMA_Init_t;
1057
1058 /**
1059 * @brief
1060 * DMA transfer configuration structure.
1061 * @details
1062 * This structure configures all aspects of a DMA transfer.
1063 */
1064 typedef struct {
1065 uint32_t ldmaReqSel; /**< Selects DMA trigger source. */
1066 uint8_t ldmaCtrlSyncPrsClrOff; /**< PRS Synctrig clear enables to clear. */
1067 uint8_t ldmaCtrlSyncPrsClrOn; /**< PRS Synctrig clear enables to set. */
1068 uint8_t ldmaCtrlSyncPrsSetOff; /**< PRS Synctrig set enables to clear. */
1069 uint8_t ldmaCtrlSyncPrsSetOn; /**< PRS Synctrig set enables to set. */
1070 bool ldmaReqDis; /**< Mask the PRS trigger input. */
1071 bool ldmaDbgHalt; /**< Dis. DMA trig when CPU is halted. */
1072 LDMA_CfgArbSlots_t ldmaCfgArbSlots; /**< Arbitration slot number. */
1073 LDMA_CfgSrcIncSign_t ldmaCfgSrcIncSign; /**< Source address increment sign. */
1074 LDMA_CfgDstIncSign_t ldmaCfgDstIncSign; /**< Destination address increment sign. */
1075 uint8_t ldmaLoopCnt; /**< Counter for looped transfers. */
1076 #if defined(_LDMA_CH_CFG_SRCBUSPORT_MASK)
1077 LDMA_CfgStructBusPort_t ldmaCfgStructBusPort; /**< Structure fetch operation bus port. */
1078 LDMA_CfgSrcBusPort_t ldmaCfgSrcBusPort; /**< Source operation bus port. */
1079 LDMA_CfgDstBusPort_t ldmaCfgDstBusPort; /**< Destination operation bus port. */
1080 #endif
1081 } LDMA_TransferCfg_t;
1082
1083 /*******************************************************************************
1084 ******************************** DEFINES **********************************
1085 ******************************************************************************/
1086
1087 /** @brief Size in words of a non-extended DMA descriptor. */
1088 #define LDMA_DESCRIPTOR_NON_EXTEND_SIZE_WORD 4
1089
1090 /** @brief Size in words of an extended DMA descriptor. */
1091 #define LDMA_DESCRIPTOR_EXTEND_SIZE_WORD 7
1092
1093 /** @brief Maximum transfer size possible per descriptor. */
1094 #define LDMA_DESCRIPTOR_MAX_XFER_SIZE (((_LDMA_CH_CTRL_XFERCNT_MASK >> _LDMA_CH_CTRL_XFERCNT_SHIFT) + 1))
1095
1096 /** @brief Converts a LDMA_Descriptor_t pointer to the value suitable to write to the linkAddr field of a LDMA_Descriptor_t. */
1097 #define LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR(addr) (int32_t) ((((uintptr_t)addr) & _LDMA_CH_LINK_LINKADDR_MASK) >> _LDMA_CH_LINK_LINKADDR_SHIFT)
1098
1099 /** @brief Converts a LDMA_Descriptor_t linkAddr field value back to a LDMA_Descriptor_t pointer. */
1100 #define LDMA_DESCRIPTOR_LINKABS_LINKADDR_TO_ADDR(linkAddr) (LDMA_Descriptor_t *) (linkAddr << _LDMA_CH_LINK_LINKADDR_SHIFT)
1101
1102 /*******************************************************************************
1103 ************************** STRUCT INITIALIZERS ****************************
1104 ******************************************************************************/
1105
1106 /** @brief Default DMA initialization structure. */
1107 #define LDMA_INIT_DEFAULT \
1108 { \
1109 .ldmaInitCtrlNumFixed = _LDMA_CTRL_NUMFIXED_DEFAULT,/* Fixed priority arbitration.*/ \
1110 .ldmaInitCtrlSyncPrsClrEn = 0, /* No PRS Synctrig clear enable*/ \
1111 .ldmaInitCtrlSyncPrsSetEn = 0, /* No PRS Synctrig set enable. */ \
1112 .ldmaInitIrqPriority = 3 /* IRQ priority level 3. */ \
1113 }
1114
1115 /**
1116 * @brief
1117 * Generic DMA transfer configuration for memory to memory transfers.
1118 */
1119 #if defined(_LDMA_CH_CFG_SRCBUSPORT_MASK)
1120 #define LDMA_TRANSFER_CFG_MEMORY() \
1121 { \
1122 0, 0, 0, 0, 0, \
1123 false, false, ldmaCfgArbSlotsAs1, \
1124 ldmaCfgSrcIncSignPos, ldmaCfgDstIncSignPos, 0, \
1125 ldmaCfgStructBusPort0, ldmaCfgSrcBusPort0, ldmaCfgDstBusPort0 \
1126 }
1127 #else
1128 #define LDMA_TRANSFER_CFG_MEMORY() \
1129 { \
1130 0, 0, 0, 0, 0, \
1131 false, false, ldmaCfgArbSlotsAs1, \
1132 ldmaCfgSrcIncSignPos, ldmaCfgDstIncSignPos, 0 \
1133 }
1134 #endif
1135
1136 /**
1137 * @brief
1138 * Generic DMA transfer configuration for looped memory to memory transfers.
1139 */
1140 #if defined(_LDMA_CH_CFG_SRCBUSPORT_MASK)
1141 #define LDMA_TRANSFER_CFG_MEMORY_LOOP(loopCnt) \
1142 { \
1143 0, 0, 0, 0, 0, \
1144 false, false, ldmaCfgArbSlotsAs1, \
1145 ldmaCfgSrcIncSignPos, ldmaCfgDstIncSignPos, \
1146 loopCnt, \
1147 ldmaCfgStructBusPort0, ldmaCfgSrcBusPort0, ldmaCfgDstBusPort0 \
1148 }
1149 #else
1150 #define LDMA_TRANSFER_CFG_MEMORY_LOOP(loopCnt) \
1151 { \
1152 0, 0, 0, 0, 0, \
1153 false, false, ldmaCfgArbSlotsAs1, \
1154 ldmaCfgSrcIncSignPos, ldmaCfgDstIncSignPos, \
1155 loopCnt \
1156 }
1157 #endif
1158
1159 /**
1160 * @brief
1161 * Generic DMA transfer configuration for memory to/from peripheral transfers.
1162 */
1163 #if defined(_LDMA_CH_CFG_SRCBUSPORT_MASK)
1164 #define LDMA_TRANSFER_CFG_PERIPHERAL(signal) \
1165 { \
1166 signal, 0, 0, 0, 0, \
1167 false, false, ldmaCfgArbSlotsAs1, \
1168 ldmaCfgSrcIncSignPos, ldmaCfgDstIncSignPos, 0, \
1169 ldmaCfgStructBusPort0, ldmaCfgSrcBusPort0, ldmaCfgDstBusPort0 \
1170 }
1171 #else
1172 #define LDMA_TRANSFER_CFG_PERIPHERAL(signal) \
1173 { \
1174 signal, 0, 0, 0, 0, \
1175 false, false, ldmaCfgArbSlotsAs1, \
1176 ldmaCfgSrcIncSignPos, ldmaCfgDstIncSignPos, 0 \
1177 }
1178 #endif
1179
1180 /**
1181 * @brief
1182 * Generic DMA transfer configuration for looped memory to/from peripheral transfers.
1183 */
1184 #if defined(_LDMA_CH_CFG_SRCBUSPORT_MASK)
1185 #define LDMA_TRANSFER_CFG_PERIPHERAL_LOOP(signal, loopCnt) \
1186 { \
1187 signal, 0, 0, 0, 0, \
1188 false, false, ldmaCfgArbSlotsAs1, \
1189 ldmaCfgSrcIncSignPos, ldmaCfgDstIncSignPos, loopCnt, \
1190 ldmaCfgStructBusPort0, ldmaCfgSrcBusPort0, ldmaCfgDstBusPort0 \
1191 }
1192 #else
1193 #define LDMA_TRANSFER_CFG_PERIPHERAL_LOOP(signal, loopCnt) \
1194 { \
1195 signal, 0, 0, 0, 0, \
1196 false, false, ldmaCfgArbSlotsAs1, \
1197 ldmaCfgSrcIncSignPos, ldmaCfgDstIncSignPos, loopCnt \
1198 }
1199 #endif
1200
1201 /**
1202 * @brief
1203 * DMA descriptor initializer for single memory to memory word transfer.
1204 * @param[in] src Source data address.
1205 * @param[in] dest Destination data address.
1206 * @param[in] count Number of words to transfer.
1207 */
1208 #define LDMA_DESCRIPTOR_SINGLE_M2M_WORD(src, dest, count) \
1209 { \
1210 .xfer = \
1211 { \
1212 .structType = ldmaCtrlStructTypeXfer, \
1213 .structReq = 1, \
1214 .xferCnt = (count) - 1, \
1215 .byteSwap = 0, \
1216 .blockSize = ldmaCtrlBlockSizeUnit1, \
1217 .doneIfs = 1, \
1218 .reqMode = ldmaCtrlReqModeAll, \
1219 .decLoopCnt = 0, \
1220 .ignoreSrec = 0, \
1221 .srcInc = ldmaCtrlSrcIncOne, \
1222 .size = ldmaCtrlSizeWord, \
1223 .dstInc = ldmaCtrlDstIncOne, \
1224 .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \
1225 .dstAddrMode = ldmaCtrlDstAddrModeAbs, \
1226 .srcAddr = (uint32_t)(src), \
1227 .dstAddr = (uint32_t)(dest), \
1228 .linkMode = 0, \
1229 .link = 0, \
1230 .linkAddr = 0 \
1231 } \
1232 }
1233
1234 #if defined(_LDMA_CH_CTRL_EXTEND_MASK)
1235 /**
1236 * @brief
1237 * DMA descriptor initializer for single memory to memory word transfer
1238 * using the extended descriptor fields.
1239 * @param[in] src Source data address.
1240 * @param[in] dest Destination data address.
1241 * @param[in] count Number of words to transfer.
1242 */
1243 #define LDMA_DESCRIPTOR_SINGLE_M2M_WORD_EXTEND(src, dest, count) \
1244 { \
1245 .structType = ldmaCtrlStructTypeXfer, \
1246 .extend = 1, \
1247 .structReq = 1, \
1248 .xferCnt = (count) - 1, \
1249 .byteSwap = 0, \
1250 .blockSize = ldmaCtrlBlockSizeUnit1, \
1251 .doneIfs = 1, \
1252 .reqMode = ldmaCtrlReqModeAll, \
1253 .decLoopCnt = 0, \
1254 .ignoreSrec = 0, \
1255 .srcInc = ldmaCtrlSrcIncOne, \
1256 .size = ldmaCtrlSizeWord, \
1257 .dstInc = ldmaCtrlDstIncNone, /* Ignored since destination addressing is non-sequential */ \
1258 .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \
1259 .dstAddrMode = ldmaCtrlDstAddrModeAbs, \
1260 .srcAddr = (uint32_t)(src), \
1261 .dstAddr = (uint32_t)(dest), \
1262 .linkMode = 0, \
1263 .link = 0, \
1264 .linkAddr = 0, \
1265 .dstIlEn = 0, \
1266 .IlMode = 0, \
1267 .bufferable = 0, \
1268 .IlSrc = 0 \
1269 }
1270 #endif
1271
1272 /**
1273 * @brief
1274 * DMA descriptor initializer for single memory to memory half-word transfer.
1275 * @param[in] src Source data address.
1276 * @param[in] dest Destination data address.
1277 * @param[in] count Number of half-words to transfer.
1278 */
1279 #define LDMA_DESCRIPTOR_SINGLE_M2M_HALF(src, dest, count) \
1280 { \
1281 .xfer = \
1282 { \
1283 .structType = ldmaCtrlStructTypeXfer, \
1284 .structReq = 1, \
1285 .xferCnt = (count) - 1, \
1286 .byteSwap = 0, \
1287 .blockSize = ldmaCtrlBlockSizeUnit1, \
1288 .doneIfs = 1, \
1289 .reqMode = ldmaCtrlReqModeAll, \
1290 .decLoopCnt = 0, \
1291 .ignoreSrec = 0, \
1292 .srcInc = ldmaCtrlSrcIncOne, \
1293 .size = ldmaCtrlSizeHalf, \
1294 .dstInc = ldmaCtrlDstIncOne, \
1295 .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \
1296 .dstAddrMode = ldmaCtrlDstAddrModeAbs, \
1297 .srcAddr = (uint32_t)(src), \
1298 .dstAddr = (uint32_t)(dest), \
1299 .linkMode = 0, \
1300 .link = 0, \
1301 .linkAddr = 0 \
1302 } \
1303 }
1304
1305 #if defined(_LDMA_CH_CTRL_EXTEND_MASK)
1306 /**
1307 * @brief
1308 * DMA descriptor initializer for single memory to memory half-word transfer
1309 * using the extended descriptor fields.
1310 * @param[in] src Source data address.
1311 * @param[in] dest Destination data address.
1312 * @param[in] count Number of half-words to transfer.
1313 */
1314 #define LDMA_DESCRIPTOR_SINGLE_M2M_HALF_EXTEND(src, dest, count) \
1315 { \
1316 .structType = ldmaCtrlStructTypeXfer, \
1317 .extend = 1, \
1318 .structReq = 1, \
1319 .xferCnt = (count) - 1, \
1320 .byteSwap = 0, \
1321 .blockSize = ldmaCtrlBlockSizeUnit1, \
1322 .doneIfs = 1, \
1323 .reqMode = ldmaCtrlReqModeAll, \
1324 .decLoopCnt = 0, \
1325 .ignoreSrec = 0, \
1326 .srcInc = ldmaCtrlSrcIncOne, \
1327 .size = ldmaCtrlSizeHalf, \
1328 .dstInc = ldmaCtrlDstIncNone, \
1329 .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \
1330 .dstAddrMode = ldmaCtrlDstAddrModeAbs, \
1331 .srcAddr = (uint32_t)(src), \
1332 .dstAddr = (uint32_t)(dest), \
1333 .linkMode = 0, \
1334 .link = 0, \
1335 .linkAddr = 0, \
1336 .dstIlEn = 0, \
1337 .IlMode = 0, \
1338 .bufferable = 0, \
1339 .IlSrc = 0 \
1340 }
1341 #endif
1342
1343 /**
1344 * @brief
1345 * DMA descriptor initializer for single memory to memory byte transfer.
1346 * @param[in] src Source data address.
1347 * @param[in] dest Destination data address.
1348 * @param[in] count Number of bytes to transfer.
1349 */
1350 #define LDMA_DESCRIPTOR_SINGLE_M2M_BYTE(src, dest, count) \
1351 { \
1352 .xfer = \
1353 { \
1354 .structType = ldmaCtrlStructTypeXfer, \
1355 .structReq = 1, \
1356 .xferCnt = (count) - 1, \
1357 .byteSwap = 0, \
1358 .blockSize = ldmaCtrlBlockSizeUnit1, \
1359 .doneIfs = 1, \
1360 .reqMode = ldmaCtrlReqModeAll, \
1361 .decLoopCnt = 0, \
1362 .ignoreSrec = 0, \
1363 .srcInc = ldmaCtrlSrcIncOne, \
1364 .size = ldmaCtrlSizeByte, \
1365 .dstInc = ldmaCtrlDstIncOne, \
1366 .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \
1367 .dstAddrMode = ldmaCtrlDstAddrModeAbs, \
1368 .srcAddr = (uint32_t)(src), \
1369 .dstAddr = (uint32_t)(dest), \
1370 .linkMode = 0, \
1371 .link = 0, \
1372 .linkAddr = 0 \
1373 } \
1374 }
1375
1376 #if defined(_LDMA_CH_CTRL_EXTEND_MASK)
1377 /**
1378 * @brief
1379 * DMA descriptor initializer for single memory to memory byte transfer
1380 * using the extended descriptor fields.
1381 * @param[in] src Source data address.
1382 * @param[in] dest Destination data address.
1383 * @param[in] count Number of bytes to transfer.
1384 */
1385 #define LDMA_DESCRIPTOR_SINGLE_M2M_BYTE_EXTEND(src, dest, count) \
1386 { \
1387 .structType = ldmaCtrlStructTypeXfer, \
1388 .extend = 1, \
1389 .structReq = 1, \
1390 .xferCnt = (count) - 1, \
1391 .byteSwap = 0, \
1392 .blockSize = ldmaCtrlBlockSizeUnit1, \
1393 .doneIfs = 1, \
1394 .reqMode = ldmaCtrlReqModeAll, \
1395 .decLoopCnt = 0, \
1396 .ignoreSrec = 0, \
1397 .srcInc = ldmaCtrlSrcIncOne, \
1398 .size = ldmaCtrlSizeByte, \
1399 .dstInc = ldmaCtrlDstIncNone, \
1400 .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \
1401 .dstAddrMode = ldmaCtrlDstAddrModeAbs, \
1402 .srcAddr = (uint32_t)(src), \
1403 .dstAddr = (uint32_t)(dest), \
1404 .linkMode = 0, \
1405 .link = 0, \
1406 .linkAddr = 0, \
1407 .dstIlEn = 0, \
1408 .IlMode = 0, \
1409 .bufferable = 0, \
1410 .IlSrc = 0 \
1411 }
1412 #endif
1413
1414 /**
1415 * @brief
1416 * DMA descriptor initializer for linked memory to memory word transfer.
1417 *
1418 * Link address must be an absolute address.
1419 * @note
1420 * The linkAddr member of the transfer descriptor is not initialized.
1421 * linkAddr must be initialized by using the proper bits right-shift
1422 * to get the correct bits from the absolute address.
1423 * LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR macro should be used for that operation:
1424 * @code
1425 desc.linkAddr = LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR(&next_desc);@endcode
1426 * The opposite bit shift (left) must be done with LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR
1427 * if linkAddr is read.
1428 * @param[in] src Source data address.
1429 * @param[in] dest Destination data address.
1430 * @param[in] count Number of words to transfer.
1431 */
1432 #define LDMA_DESCRIPTOR_LINKABS_M2M_WORD(src, dest, count) \
1433 { \
1434 .xfer = \
1435 { \
1436 .structType = ldmaCtrlStructTypeXfer, \
1437 .structReq = 1, \
1438 .xferCnt = (count) - 1, \
1439 .byteSwap = 0, \
1440 .blockSize = ldmaCtrlBlockSizeUnit1, \
1441 .doneIfs = 0, \
1442 .reqMode = ldmaCtrlReqModeAll, \
1443 .decLoopCnt = 0, \
1444 .ignoreSrec = 0, \
1445 .srcInc = ldmaCtrlSrcIncOne, \
1446 .size = ldmaCtrlSizeWord, \
1447 .dstInc = ldmaCtrlDstIncOne, \
1448 .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \
1449 .dstAddrMode = ldmaCtrlDstAddrModeAbs, \
1450 .srcAddr = (uint32_t)(src), \
1451 .dstAddr = (uint32_t)(dest), \
1452 .linkMode = ldmaLinkModeAbs, \
1453 .link = 1, \
1454 .linkAddr = 0 /* Must be set runtime ! */ \
1455 } \
1456 }
1457
1458 #if defined(_LDMA_CH_CTRL_EXTEND_MASK)
1459 /**
1460 * @brief
1461 * DMA descriptor initializer for linked memory to memory word transfer
1462 * using the extended descriptor fields.
1463 *
1464 * Link address must be an absolute address.
1465 * @note
1466 * The linkAddr member of the transfer descriptor is not initialized.
1467 * linkAddr must be initialized by using the proper bits right-shift
1468 * to get the correct bits from the absolute address.
1469 * LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR macro should be used for that operation:
1470 * @code
1471 desc.linkAddr = LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR(&next_desc);@endcode
1472 * The opposite bit shift (left) must be done with LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR
1473 * if linkAddr is read.
1474 * @param[in] src Source data address.
1475 * @param[in] dest Destination data address.
1476 * @param[in] count Number of words to transfer.
1477 */
1478 #define LDMA_DESCRIPTOR_LINKABS_M2M_WORD_EXTEND(src, dest, count) \
1479 { \
1480 .structType = ldmaCtrlStructTypeXfer, \
1481 .extend = 1, \
1482 .structReq = 1, \
1483 .xferCnt = (count) - 1, \
1484 .byteSwap = 0, \
1485 .blockSize = ldmaCtrlBlockSizeUnit1, \
1486 .doneIfs = 0, \
1487 .reqMode = ldmaCtrlReqModeAll, \
1488 .decLoopCnt = 0, \
1489 .ignoreSrec = 0, \
1490 .srcInc = ldmaCtrlSrcIncOne, \
1491 .size = ldmaCtrlSizeWord, \
1492 .dstInc = ldmaCtrlDstIncNone, \
1493 .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \
1494 .dstAddrMode = ldmaCtrlDstAddrModeAbs, \
1495 .srcAddr = (uint32_t)(src), \
1496 .dstAddr = (uint32_t)(dest), \
1497 .linkMode = ldmaLinkModeAbs, \
1498 .link = 1, \
1499 .linkAddr = 0, /* Must be set runtime ! */ \
1500 .dstIlEn = 0, \
1501 .IlMode = 0, \
1502 .bufferable = 0, \
1503 .IlSrc = 0 \
1504 }
1505 #endif
1506
1507 /**
1508 * @brief
1509 * DMA descriptor initializer for linked memory to memory half-word transfer.
1510 *
1511 * Link address must be an absolute address.
1512 * @note
1513 * The linkAddr member of the transfer descriptor is not initialized.
1514 * linkAddr must be initialized by using the proper bits right-shift
1515 * to get the correct bits from the absolute address.
1516 * LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR macro should be used for that operation:
1517 * @code
1518 desc.linkAddr = LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR(&next_desc);@endcode
1519 * The opposite bit shift (left) must be done with LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR
1520 * if linkAddr is read.
1521 * @param[in] src Source data address.
1522 * @param[in] dest Destination data address.
1523 * @param[in] count Number of half-words to transfer.
1524 */
1525 #define LDMA_DESCRIPTOR_LINKABS_M2M_HALF(src, dest, count) \
1526 { \
1527 .xfer = \
1528 { \
1529 .structType = ldmaCtrlStructTypeXfer, \
1530 .structReq = 1, \
1531 .xferCnt = (count) - 1, \
1532 .byteSwap = 0, \
1533 .blockSize = ldmaCtrlBlockSizeUnit1, \
1534 .doneIfs = 0, \
1535 .reqMode = ldmaCtrlReqModeAll, \
1536 .decLoopCnt = 0, \
1537 .ignoreSrec = 0, \
1538 .srcInc = ldmaCtrlSrcIncOne, \
1539 .size = ldmaCtrlSizeHalf, \
1540 .dstInc = ldmaCtrlDstIncOne, \
1541 .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \
1542 .dstAddrMode = ldmaCtrlDstAddrModeAbs, \
1543 .srcAddr = (uint32_t)(src), \
1544 .dstAddr = (uint32_t)(dest), \
1545 .linkMode = ldmaLinkModeAbs, \
1546 .link = 1, \
1547 .linkAddr = 0 /* Must be set runtime ! */ \
1548 } \
1549 }
1550
1551 #if defined(_LDMA_CH_CTRL_EXTEND_MASK)
1552 /**
1553 * @brief
1554 * DMA descriptor initializer for linked memory to memory half-word transfer
1555 * using the extended descriptor fields.
1556 *
1557 * Link address must be an absolute address.
1558 * @note
1559 * The linkAddr member of the transfer descriptor is not initialized.
1560 * linkAddr must be initialized by using the proper bits right-shift
1561 * to get the correct bits from the absolute address.
1562 * LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR macro should be used for that operation:
1563 * @code
1564 desc.linkAddr = LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR(&next_desc);@endcode
1565 * The opposite bit shift (left) must be done with LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR
1566 * if linkAddr is read.
1567 * @param[in] src Source data address.
1568 * @param[in] dest Destination data address.
1569 * @param[in] count Number of half-words to transfer.
1570 */
1571 #define LDMA_DESCRIPTOR_LINKABS_M2M_HALF_EXTEND(src, dest, count) \
1572 { \
1573 .structType = ldmaCtrlStructTypeXfer, \
1574 .extend = 1, \
1575 .structReq = 1, \
1576 .xferCnt = (count) - 1, \
1577 .byteSwap = 0, \
1578 .blockSize = ldmaCtrlBlockSizeUnit1, \
1579 .doneIfs = 0, \
1580 .reqMode = ldmaCtrlReqModeAll, \
1581 .decLoopCnt = 0, \
1582 .ignoreSrec = 0, \
1583 .srcInc = ldmaCtrlSrcIncOne, \
1584 .size = ldmaCtrlSizeHalf, \
1585 .dstInc = ldmaCtrlDstIncNone, \
1586 .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \
1587 .dstAddrMode = ldmaCtrlDstAddrModeAbs, \
1588 .srcAddr = (uint32_t)(src), \
1589 .dstAddr = (uint32_t)(dest), \
1590 .linkMode = ldmaLinkModeAbs, \
1591 .link = 1, \
1592 .linkAddr = 0, /* Must be set runtime ! */ \
1593 .dstIlEn = 0, \
1594 .IlMode = 0, \
1595 .bufferable = 0, \
1596 .IlSrc = 0 \
1597 }
1598 #endif
1599
1600 /**
1601 * @brief
1602 * DMA descriptor initializer for linked memory to memory byte transfer.
1603 *
1604 * Link address must be an absolute address.
1605 * @note
1606 * The linkAddr member of the transfer descriptor is not initialized.
1607 * linkAddr must be initialized by using the proper bits right-shift
1608 * to get the correct bits from the absolute address.
1609 * LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR macro should be used for that operation:
1610 * @code
1611 desc.linkAddr = LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR(&next_desc);@endcode
1612 * The opposite bit shift (left) must be done with LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR
1613 * if linkAddr is read.
1614 * @param[in] src Source data address.
1615 * @param[in] dest Destination data address.
1616 * @param[in] count Number of bytes to transfer.
1617 */
1618 #define LDMA_DESCRIPTOR_LINKABS_M2M_BYTE(src, dest, count) \
1619 { \
1620 .xfer = \
1621 { \
1622 .structType = ldmaCtrlStructTypeXfer, \
1623 .structReq = 1, \
1624 .xferCnt = (count) - 1, \
1625 .byteSwap = 0, \
1626 .blockSize = ldmaCtrlBlockSizeUnit1, \
1627 .doneIfs = 0, \
1628 .reqMode = ldmaCtrlReqModeAll, \
1629 .decLoopCnt = 0, \
1630 .ignoreSrec = 0, \
1631 .srcInc = ldmaCtrlSrcIncOne, \
1632 .size = ldmaCtrlSizeByte, \
1633 .dstInc = ldmaCtrlDstIncOne, \
1634 .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \
1635 .dstAddrMode = ldmaCtrlDstAddrModeAbs, \
1636 .srcAddr = (uint32_t)(src), \
1637 .dstAddr = (uint32_t)(dest), \
1638 .linkMode = ldmaLinkModeAbs, \
1639 .link = 1, \
1640 .linkAddr = 0 /* Must be set runtime ! */ \
1641 } \
1642 }
1643
1644 #if defined(_LDMA_CH_CTRL_EXTEND_MASK)
1645 /**
1646 * @brief
1647 * DMA descriptor initializer for linked memory to memory byte transfer
1648 * using the extended descriptor fields.
1649 *
1650 * Link address must be an absolute address.
1651 * @note
1652 * The linkAddr member of the transfer descriptor is not initialized.
1653 * linkAddr must be initialized by using the proper bits right-shift
1654 * to get the correct bits from the absolute address.
1655 * LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR macro should be used for that operation:
1656 * @code
1657 desc.linkAddr = LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR(&next_desc);@endcode
1658 * The opposite bit shift (left) must be done with LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR
1659 * if linkAddr is read.
1660 * @param[in] src Source data address.
1661 * @param[in] dest Destination data address.
1662 * @param[in] count Number of bytes to transfer.
1663 */
1664 #define LDMA_DESCRIPTOR_LINKABS_M2M_BYTE_EXTEND(src, dest, count) \
1665 { \
1666 .structType = ldmaCtrlStructTypeXfer, \
1667 .extend = 1, \
1668 .structReq = 1, \
1669 .xferCnt = (count) - 1, \
1670 .byteSwap = 0, \
1671 .blockSize = ldmaCtrlBlockSizeUnit1, \
1672 .doneIfs = 0, \
1673 .reqMode = ldmaCtrlReqModeAll, \
1674 .decLoopCnt = 0, \
1675 .ignoreSrec = 0, \
1676 .srcInc = ldmaCtrlSrcIncOne, \
1677 .size = ldmaCtrlSizeByte, \
1678 .dstInc = ldmaCtrlDstIncNone, \
1679 .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \
1680 .dstAddrMode = ldmaCtrlDstAddrModeAbs, \
1681 .srcAddr = (uint32_t)(src), \
1682 .dstAddr = (uint32_t)(dest), \
1683 .linkMode = ldmaLinkModeAbs, \
1684 .link = 1, \
1685 .linkAddr = 0, /* Must be set runtime ! */ \
1686 .dstIlEn = 0, \
1687 .IlMode = 0, \
1688 .bufferable = 0, \
1689 .IlSrc = 0 \
1690 }
1691 #endif
1692
1693 /**
1694 * @brief
1695 * DMA descriptor initializer for linked memory to memory word transfer.
1696 *
1697 * Link address is a relative address.
1698 * @note
1699 * The linkAddr member of the transfer descriptor is initialized to 4
1700 * (regular descriptor) or 7 (extended descriptor), assuming that
1701 * the next descriptor immediately follows this descriptor (in memory).
1702 * @param[in] src Source data address.
1703 * @param[in] dest Destination data address.
1704 * @param[in] count Number of words to transfer.
1705 * @param[in] linkjmp Address of descriptor to link to, expressed as a
1706 * signed number of descriptors from "here".
1707 * 1=one descriptor forward in memory,
1708 * 0=this descriptor,
1709 * -1=one descriptor back in memory.
1710 */
1711 #define LDMA_DESCRIPTOR_LINKREL_M2M_WORD(src, dest, count, linkjmp) \
1712 { \
1713 .xfer = \
1714 { \
1715 .structType = ldmaCtrlStructTypeXfer, \
1716 .structReq = 1, \
1717 .xferCnt = (count) - 1, \
1718 .byteSwap = 0, \
1719 .blockSize = ldmaCtrlBlockSizeUnit1, \
1720 .doneIfs = 0, \
1721 .reqMode = ldmaCtrlReqModeAll, \
1722 .decLoopCnt = 0, \
1723 .ignoreSrec = 0, \
1724 .srcInc = ldmaCtrlSrcIncOne, \
1725 .size = ldmaCtrlSizeWord, \
1726 .dstInc = ldmaCtrlDstIncOne, \
1727 .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \
1728 .dstAddrMode = ldmaCtrlDstAddrModeAbs, \
1729 .srcAddr = (uint32_t)(src), \
1730 .dstAddr = (uint32_t)(dest), \
1731 .linkMode = ldmaLinkModeRel, \
1732 .link = 1, \
1733 .linkAddr = (linkjmp) * LDMA_DESCRIPTOR_NON_EXTEND_SIZE_WORD \
1734 } \
1735 }
1736
1737 #if defined(_LDMA_CH_CTRL_EXTEND_MASK)
1738 /**
1739 * @brief
1740 * DMA descriptor initializer for linked memory to memory word transfer
1741 * using the extended descriptor fields.
1742 *
1743 * Link address is a relative address.
1744 * @note
1745 * The linkAddr member of the transfer descriptor is initialized to 4
1746 * (regular descriptor) or 7 (extended descriptor), assuming that
1747 * the next descriptor immediately follows this descriptor (in memory).
1748 * @param[in] src Source data address.
1749 * @param[in] dest Destination data address.
1750 * @param[in] count Number of words to transfer.
1751 * @param[in] linkjmp Address of descriptor to link to, expressed as a
1752 * signed number of descriptors from "here".
1753 * 1=one descriptor forward in memory,
1754 * 0=this descriptor,
1755 * -1=one descriptor back in memory.
1756 */
1757 #define LDMA_DESCRIPTOR_LINKREL_M2M_WORD_EXTEND(src, dest, count, linkjmp) \
1758 { \
1759 .structType = ldmaCtrlStructTypeXfer, \
1760 .extend = 1, \
1761 .structReq = 1, \
1762 .xferCnt = (count) - 1, \
1763 .byteSwap = 0, \
1764 .blockSize = ldmaCtrlBlockSizeUnit1, \
1765 .doneIfs = 0, \
1766 .reqMode = ldmaCtrlReqModeAll, \
1767 .decLoopCnt = 0, \
1768 .ignoreSrec = 0, \
1769 .srcInc = ldmaCtrlSrcIncOne, \
1770 .size = ldmaCtrlSizeWord, \
1771 .dstInc = ldmaCtrlDstIncNone, \
1772 .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \
1773 .dstAddrMode = ldmaCtrlDstAddrModeAbs, \
1774 .srcAddr = (uint32_t)(src), \
1775 .dstAddr = (uint32_t)(dest), \
1776 .linkMode = ldmaLinkModeRel, \
1777 .link = 1, \
1778 .linkAddr = (linkjmp) * LDMA_DESCRIPTOR_EXTEND_SIZE_WORD, \
1779 .dstIlEn = 0, \
1780 .IlMode = 0, \
1781 .bufferable = 0, \
1782 .IlSrc = 0 \
1783 }
1784 #endif
1785
1786 /**
1787 * @brief
1788 * DMA descriptor initializer for linked memory to memory half-word transfer.
1789 *
1790 * Link address is a relative address.
1791 * @note
1792 * The linkAddr member of the transfer descriptor is initialized to 4
1793 * (regular descriptor) or 7 (extended descriptor), assuming that
1794 * the next descriptor immediately follows this descriptor (in memory).
1795 * @param[in] src Source data address.
1796 * @param[in] dest Destination data address.
1797 * @param[in] count Number of half-words to transfer.
1798 * @param[in] linkjmp Address of descriptor to link to, expressed as a
1799 * signed number of descriptors from "here".
1800 * 1=one descriptor forward in memory,
1801 * 0=this descriptor,
1802 * -1=one descriptor back in memory.
1803 */
1804 #define LDMA_DESCRIPTOR_LINKREL_M2M_HALF(src, dest, count, linkjmp) \
1805 { \
1806 .xfer = \
1807 { \
1808 .structType = ldmaCtrlStructTypeXfer, \
1809 .structReq = 1, \
1810 .xferCnt = (count) - 1, \
1811 .byteSwap = 0, \
1812 .blockSize = ldmaCtrlBlockSizeUnit1, \
1813 .doneIfs = 0, \
1814 .reqMode = ldmaCtrlReqModeAll, \
1815 .decLoopCnt = 0, \
1816 .ignoreSrec = 0, \
1817 .srcInc = ldmaCtrlSrcIncOne, \
1818 .size = ldmaCtrlSizeHalf, \
1819 .dstInc = ldmaCtrlDstIncOne, \
1820 .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \
1821 .dstAddrMode = ldmaCtrlDstAddrModeAbs, \
1822 .srcAddr = (uint32_t)(src), \
1823 .dstAddr = (uint32_t)(dest), \
1824 .linkMode = ldmaLinkModeRel, \
1825 .link = 1, \
1826 .linkAddr = (linkjmp) * LDMA_DESCRIPTOR_NON_EXTEND_SIZE_WORD \
1827 } \
1828 }
1829
1830 #if defined(_LDMA_CH_CTRL_EXTEND_MASK)
1831 /**
1832 * @brief
1833 * DMA descriptor initializer for linked memory to memory half-word transfer
1834 * using the extended descriptor fields.
1835 *
1836 * Link address is a relative address.
1837 * @note
1838 * The linkAddr member of the transfer descriptor is initialized to 4
1839 * (regular descriptor) or 7 (extended descriptor), assuming that
1840 * the next descriptor immediately follows this descriptor (in memory).
1841 * @param[in] src Source data address.
1842 * @param[in] dest Destination data address.
1843 * @param[in] count Number of half-words to transfer.
1844 * @param[in] linkjmp Address of descriptor to link to, expressed as a
1845 * signed number of descriptors from "here".
1846 * 1=one descriptor forward in memory,
1847 * 0=this descriptor,
1848 * -1=one descriptor back in memory.
1849 */
1850 #define LDMA_DESCRIPTOR_LINKREL_M2M_HALF_EXTEND(src, dest, count, linkjmp) \
1851 { \
1852 .structType = ldmaCtrlStructTypeXfer, \
1853 .extend = 1, \
1854 .structReq = 1, \
1855 .xferCnt = (count) - 1, \
1856 .byteSwap = 0, \
1857 .blockSize = ldmaCtrlBlockSizeUnit1, \
1858 .doneIfs = 0, \
1859 .reqMode = ldmaCtrlReqModeAll, \
1860 .decLoopCnt = 0, \
1861 .ignoreSrec = 0, \
1862 .srcInc = ldmaCtrlSrcIncOne, \
1863 .size = ldmaCtrlSizeHalf, \
1864 .dstInc = ldmaCtrlDstIncNone, \
1865 .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \
1866 .dstAddrMode = ldmaCtrlDstAddrModeAbs, \
1867 .srcAddr = (uint32_t)(src), \
1868 .dstAddr = (uint32_t)(dest), \
1869 .linkMode = ldmaLinkModeRel, \
1870 .link = 1, \
1871 .linkAddr = (linkjmp) * LDMA_DESCRIPTOR_EXTEND_SIZE_WORD, \
1872 .dstIlEn = 0, \
1873 .IlMode = 0, \
1874 .bufferable = 0, \
1875 .IlSrc = 0 \
1876 }
1877 #endif
1878
1879 /**
1880 * @brief
1881 * DMA descriptor initializer for linked memory to memory byte transfer.
1882 *
1883 * Link address is a relative address.
1884 * @note
1885 * The linkAddr member of the transfer descriptor is initialized to 4
1886 * (regular descriptor) or 7 (extended descriptor), assuming that
1887 * the next descriptor immediately follows this descriptor (in memory).
1888 * @param[in] src Source data address.
1889 * @param[in] dest Destination data address.
1890 * @param[in] count Number of bytes to transfer.
1891 * @param[in] linkjmp Address of descriptor to link to, expressed as a
1892 * signed number of descriptors from "here".
1893 * 1=one descriptor forward in memory,
1894 * 0=this descriptor,
1895 * -1=one descriptor back in memory.
1896 */
1897 #define LDMA_DESCRIPTOR_LINKREL_M2M_BYTE(src, dest, count, linkjmp) \
1898 { \
1899 .xfer = \
1900 { \
1901 .structType = ldmaCtrlStructTypeXfer, \
1902 .structReq = 1, \
1903 .xferCnt = (count) - 1, \
1904 .byteSwap = 0, \
1905 .blockSize = ldmaCtrlBlockSizeUnit1, \
1906 .doneIfs = 0, \
1907 .reqMode = ldmaCtrlReqModeAll, \
1908 .decLoopCnt = 0, \
1909 .ignoreSrec = 0, \
1910 .srcInc = ldmaCtrlSrcIncOne, \
1911 .size = ldmaCtrlSizeByte, \
1912 .dstInc = ldmaCtrlDstIncOne, \
1913 .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \
1914 .dstAddrMode = ldmaCtrlDstAddrModeAbs, \
1915 .srcAddr = (uint32_t)(src), \
1916 .dstAddr = (uint32_t)(dest), \
1917 .linkMode = ldmaLinkModeRel, \
1918 .link = 1, \
1919 .linkAddr = (linkjmp) * LDMA_DESCRIPTOR_NON_EXTEND_SIZE_WORD \
1920 } \
1921 }
1922
1923 #if defined(_LDMA_CH_CTRL_EXTEND_MASK)
1924 /**
1925 * @brief
1926 * DMA descriptor initializer for linked memory to memory byte transfer
1927 * using the extended descriptor fields.
1928 *
1929 * Link address is a relative address.
1930 * @note
1931 * The linkAddr member of the transfer descriptor is initialized to 4
1932 * (regular descriptor) or 7 (extended descriptor), assuming that
1933 * the next descriptor immediately follows this descriptor (in memory).
1934 * @param[in] src Source data address.
1935 * @param[in] dest Destination data address.
1936 * @param[in] count Number of bytes to transfer.
1937 * @param[in] linkjmp Address of descriptor to link to, expressed as a
1938 * signed number of descriptors from "here".
1939 * 1=one descriptor forward in memory,
1940 * 0=this descriptor,
1941 * -1=one descriptor back in memory.
1942 */
1943 #define LDMA_DESCRIPTOR_LINKREL_M2M_BYTE_EXTEND(src, dest, count, linkjmp) \
1944 { \
1945 .structType = ldmaCtrlStructTypeXfer, \
1946 .extend = 1, \
1947 .structReq = 1, \
1948 .xferCnt = (count) - 1, \
1949 .byteSwap = 0, \
1950 .blockSize = ldmaCtrlBlockSizeUnit1, \
1951 .doneIfs = 0, \
1952 .reqMode = ldmaCtrlReqModeAll, \
1953 .decLoopCnt = 0, \
1954 .ignoreSrec = 0, \
1955 .srcInc = ldmaCtrlSrcIncOne, \
1956 .size = ldmaCtrlSizeByte, \
1957 .dstInc = ldmaCtrlDstIncNone, \
1958 .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \
1959 .dstAddrMode = ldmaCtrlDstAddrModeAbs, \
1960 .srcAddr = (uint32_t)(src), \
1961 .dstAddr = (uint32_t)(dest), \
1962 .linkMode = ldmaLinkModeRel, \
1963 .link = 1, \
1964 .linkAddr = (linkjmp) * LDMA_DESCRIPTOR_EXTEND_SIZE_WORD, \
1965 .dstIlEn = 0, \
1966 .IlMode = 0, \
1967 .bufferable = 0, \
1968 .IlSrc = 0 \
1969 }
1970 #endif
1971
1972 /**
1973 * @brief
1974 * DMA descriptor initializer for byte transfers from a peripheral to memory.
1975 * @param[in] src Peripheral data source register address.
1976 * @param[in] dest Destination data address.
1977 * @param[in] count Number of bytes to transfer.
1978 */
1979 #define LDMA_DESCRIPTOR_SINGLE_P2M_BYTE(src, dest, count) \
1980 { \
1981 .xfer = \
1982 { \
1983 .structType = ldmaCtrlStructTypeXfer, \
1984 .structReq = 0, \
1985 .xferCnt = (count) - 1, \
1986 .byteSwap = 0, \
1987 .blockSize = ldmaCtrlBlockSizeUnit1, \
1988 .doneIfs = 1, \
1989 .reqMode = ldmaCtrlReqModeBlock, \
1990 .decLoopCnt = 0, \
1991 .ignoreSrec = 0, \
1992 .srcInc = ldmaCtrlSrcIncNone, \
1993 .size = ldmaCtrlSizeByte, \
1994 .dstInc = ldmaCtrlDstIncOne, \
1995 .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \
1996 .dstAddrMode = ldmaCtrlDstAddrModeAbs, \
1997 .srcAddr = (uint32_t)(src), \
1998 .dstAddr = (uint32_t)(dest), \
1999 .linkMode = 0, \
2000 .link = 0, \
2001 .linkAddr = 0 \
2002 } \
2003 }
2004
2005 #if defined(_LDMA_CH_CTRL_EXTEND_MASK)
2006 /**
2007 * @brief
2008 * DMA descriptor initializer for byte transfers from a peripheral to memory
2009 * using the extended descriptor fields.
2010 * @param[in] src Peripheral data source register address.
2011 * @param[in] dest Destination data address.
2012 * @param[in] count Number of bytes to transfer.
2013 */
2014 #define LDMA_DESCRIPTOR_SINGLE_P2M_BYTE_EXTEND(src, dest, count) \
2015 { \
2016 .structType = ldmaCtrlStructTypeXfer, \
2017 .extend = 1, \
2018 .structReq = 0, \
2019 .xferCnt = (count) - 1, \
2020 .byteSwap = 0, \
2021 .blockSize = ldmaCtrlBlockSizeUnit1, \
2022 .doneIfs = 1, \
2023 .reqMode = ldmaCtrlReqModeBlock, \
2024 .decLoopCnt = 0, \
2025 .ignoreSrec = 0, \
2026 .srcInc = ldmaCtrlSrcIncNone, \
2027 .size = ldmaCtrlSizeByte, \
2028 .dstInc = ldmaCtrlDstIncNone, \
2029 .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \
2030 .dstAddrMode = ldmaCtrlDstAddrModeAbs, \
2031 .srcAddr = (uint32_t)(src), \
2032 .dstAddr = (uint32_t)(dest), \
2033 .linkMode = 0, \
2034 .link = 0, \
2035 .linkAddr = 0, \
2036 .dstIlEn = 0, \
2037 .IlMode = 0, \
2038 .bufferable = 0, \
2039 .IlSrc = 0 \
2040 }
2041 #endif
2042
2043 /**
2044 * @brief
2045 * DMA descriptor initializer for byte transfers from a peripheral to a peripheral.
2046 * @param[in] src Peripheral data source register address.
2047 * @param[in] dest Peripheral data destination register address.
2048 * @param[in] count Number of bytes to transfer.
2049 */
2050 #define LDMA_DESCRIPTOR_SINGLE_P2P_BYTE(src, dest, count) \
2051 { \
2052 .xfer = \
2053 { \
2054 .structType = ldmaCtrlStructTypeXfer, \
2055 .structReq = 0, \
2056 .xferCnt = (count) - 1, \
2057 .byteSwap = 0, \
2058 .blockSize = ldmaCtrlBlockSizeUnit1, \
2059 .doneIfs = 1, \
2060 .reqMode = ldmaCtrlReqModeBlock, \
2061 .decLoopCnt = 0, \
2062 .ignoreSrec = 0, \
2063 .srcInc = ldmaCtrlSrcIncNone, \
2064 .size = ldmaCtrlSizeByte, \
2065 .dstInc = ldmaCtrlDstIncNone, \
2066 .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \
2067 .dstAddrMode = ldmaCtrlDstAddrModeAbs, \
2068 .srcAddr = (uint32_t)(src), \
2069 .dstAddr = (uint32_t)(dest), \
2070 .linkMode = 0, \
2071 .link = 0, \
2072 .linkAddr = 0 \
2073 } \
2074 }
2075
2076 /**
2077 * @brief
2078 * DMA descriptor initializer for byte transfers from memory to a peripheral.
2079 * @param[in] src Source data address.
2080 * @param[in] dest Peripheral data register destination address.
2081 * @param[in] count Number of bytes to transfer.
2082 */
2083 #define LDMA_DESCRIPTOR_SINGLE_M2P_BYTE(src, dest, count) \
2084 { \
2085 .xfer = \
2086 { \
2087 .structType = ldmaCtrlStructTypeXfer, \
2088 .structReq = 0, \
2089 .xferCnt = (count) - 1, \
2090 .byteSwap = 0, \
2091 .blockSize = ldmaCtrlBlockSizeUnit1, \
2092 .doneIfs = 1, \
2093 .reqMode = ldmaCtrlReqModeBlock, \
2094 .decLoopCnt = 0, \
2095 .ignoreSrec = 0, \
2096 .srcInc = ldmaCtrlSrcIncOne, \
2097 .size = ldmaCtrlSizeByte, \
2098 .dstInc = ldmaCtrlDstIncNone, \
2099 .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \
2100 .dstAddrMode = ldmaCtrlDstAddrModeAbs, \
2101 .srcAddr = (uint32_t)(src), \
2102 .dstAddr = (uint32_t)(dest), \
2103 .linkMode = 0, \
2104 .link = 0, \
2105 .linkAddr = 0 \
2106 } \
2107 }
2108
2109 #if defined(_LDMA_CH_CTRL_EXTEND_MASK)
2110 /**
2111 * @brief
2112 * DMA descriptor initializer for byte transfers from memory to a peripheral
2113 * using the extended descriptor fields.
2114 * @note
2115 * For the extended descriptor, if IlMode uses the absolute addressing, the
2116 * rules are used directly as the destination addresses of the corresponding
2117 * data. Thus the argument 'dest' will be ignored by the DMA engine.
2118 * @param[in] src Source data address.
2119 * @param[in] dest Peripheral data register destination address.
2120 * @param[in] count Number of bytes to transfer.
2121 */
2122 #define LDMA_DESCRIPTOR_SINGLE_M2P_BYTE_EXTEND(src, dest, count) \
2123 { \
2124 .structType = ldmaCtrlStructTypeXfer, \
2125 .extend = 1, \
2126 .structReq = 0, \
2127 .xferCnt = (count) - 1, \
2128 .byteSwap = 0, \
2129 .blockSize = ldmaCtrlBlockSizeUnit1, \
2130 .doneIfs = 1, \
2131 .reqMode = ldmaCtrlReqModeBlock, \
2132 .decLoopCnt = 0, \
2133 .ignoreSrec = 0, \
2134 .srcInc = ldmaCtrlSrcIncOne, \
2135 .size = ldmaCtrlSizeByte, \
2136 .dstInc = ldmaCtrlDstIncNone, \
2137 .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \
2138 .dstAddrMode = ldmaCtrlDstAddrModeAbs, \
2139 .srcAddr = (uint32_t)(src), \
2140 .dstAddr = (uint32_t)(dest), \
2141 .linkMode = 0, \
2142 .link = 0, \
2143 .linkAddr = 0, \
2144 .dstIlEn = 0, \
2145 .IlMode = 0, \
2146 .bufferable = 0, \
2147 .IlSrc = 0 \
2148 }
2149 #endif
2150
2151 /**
2152 * @brief
2153 * DMA descriptor initializer for byte transfers from a peripheral to memory.
2154 * @param[in] src Peripheral data source register address.
2155 * @param[in] dest Destination data address.
2156 * @param[in] count Number of bytes to transfer.
2157 * @param[in] linkjmp Address of descriptor to link to, expressed as a
2158 * signed number of descriptors from "here".
2159 * 1=one descriptor forward in memory,
2160 * 0=this descriptor,
2161 * -1=one descriptor back in memory.
2162 */
2163 #define LDMA_DESCRIPTOR_LINKREL_P2M_BYTE(src, dest, count, linkjmp) \
2164 { \
2165 .xfer = \
2166 { \
2167 .structType = ldmaCtrlStructTypeXfer, \
2168 .structReq = 0, \
2169 .xferCnt = (count) - 1, \
2170 .byteSwap = 0, \
2171 .blockSize = ldmaCtrlBlockSizeUnit1, \
2172 .doneIfs = 1, \
2173 .reqMode = ldmaCtrlReqModeBlock, \
2174 .decLoopCnt = 0, \
2175 .ignoreSrec = 0, \
2176 .srcInc = ldmaCtrlSrcIncNone, \
2177 .size = ldmaCtrlSizeByte, \
2178 .dstInc = ldmaCtrlDstIncOne, \
2179 .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \
2180 .dstAddrMode = ldmaCtrlDstAddrModeAbs, \
2181 .srcAddr = (uint32_t)(src), \
2182 .dstAddr = (uint32_t)(dest), \
2183 .linkMode = ldmaLinkModeRel, \
2184 .link = 1, \
2185 .linkAddr = (linkjmp) * LDMA_DESCRIPTOR_NON_EXTEND_SIZE_WORD \
2186 } \
2187 }
2188
2189 #if defined(_LDMA_CH_CTRL_EXTEND_MASK)
2190 /**
2191 * @brief
2192 * DMA descriptor initializer for byte transfers from a peripheral to memory
2193 * using the extended descriptor fields.
2194 * @param[in] src Peripheral data source register address.
2195 * @param[in] dest Destination data address.
2196 * @param[in] count Number of bytes to transfer.
2197 * @param[in] linkjmp Address of descriptor to link to, expressed as a
2198 * signed number of descriptors from "here".
2199 * 1=one descriptor forward in memory,
2200 * 0=this descriptor,
2201 * -1=one descriptor back in memory.
2202 */
2203 #define LDMA_DESCRIPTOR_LINKREL_P2M_BYTE_EXTEND(src, dest, count, linkjmp) \
2204 { \
2205 .structType = ldmaCtrlStructTypeXfer, \
2206 .extend = 1, \
2207 .structReq = 0, \
2208 .xferCnt = (count) - 1, \
2209 .byteSwap = 0, \
2210 .blockSize = ldmaCtrlBlockSizeUnit1, \
2211 .doneIfs = 1, \
2212 .reqMode = ldmaCtrlReqModeBlock, \
2213 .decLoopCnt = 0, \
2214 .ignoreSrec = 0, \
2215 .srcInc = ldmaCtrlSrcIncNone, \
2216 .size = ldmaCtrlSizeByte, \
2217 .dstInc = ldmaCtrlDstIncNone, \
2218 .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \
2219 .dstAddrMode = ldmaCtrlDstAddrModeAbs, \
2220 .srcAddr = (uint32_t)(src), \
2221 .dstAddr = (uint32_t)(dest), \
2222 .linkMode = ldmaLinkModeRel, \
2223 .link = 1, \
2224 .linkAddr = (linkjmp) * LDMA_DESCRIPTOR_EXTEND_SIZE_WORD, \
2225 .dstIlEn = 0, \
2226 .IlMode = 0, \
2227 .bufferable = 0, \
2228 .IlSrc = 0 \
2229 }
2230 #endif
2231
2232 /**
2233 * @brief
2234 * DMA descriptor initializer for word transfers from a peripheral to memory.
2235 * @param[in] src Peripheral data source register address.
2236 * @param[in] dest Destination data address.
2237 * @param[in] count Number of words to transfer.
2238 * @param[in] linkjmp Address of descriptor to link to, expressed as a
2239 * signed number of descriptors from "here".
2240 * 1=one descriptor forward in memory,
2241 * 0=this descriptor,
2242 * -1=one descriptor back in memory.
2243 */
2244 #define LDMA_DESCRIPTOR_LINKREL_P2M_WORD(src, dest, count, linkjmp) \
2245 { \
2246 .xfer = \
2247 { \
2248 .structType = ldmaCtrlStructTypeXfer, \
2249 .structReq = 0, \
2250 .xferCnt = (count) - 1, \
2251 .byteSwap = 0, \
2252 .blockSize = ldmaCtrlBlockSizeUnit1, \
2253 .doneIfs = 1, \
2254 .reqMode = ldmaCtrlReqModeBlock, \
2255 .decLoopCnt = 0, \
2256 .ignoreSrec = 0, \
2257 .srcInc = ldmaCtrlSrcIncNone, \
2258 .size = ldmaCtrlSizeWord, \
2259 .dstInc = ldmaCtrlDstIncOne, \
2260 .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \
2261 .dstAddrMode = ldmaCtrlDstAddrModeAbs, \
2262 .srcAddr = (uint32_t)(src), \
2263 .dstAddr = (uint32_t)(dest), \
2264 .linkMode = ldmaLinkModeRel, \
2265 .link = 1, \
2266 .linkAddr = (linkjmp) * LDMA_DESCRIPTOR_NON_EXTEND_SIZE_WORD \
2267 } \
2268 }
2269
2270 #if defined(_LDMA_CH_CTRL_EXTEND_MASK)
2271 /**
2272 * @brief
2273 * DMA descriptor initializer for word transfers from a peripheral to memory
2274 * using the extended descriptor fields.
2275 * @param[in] src Peripheral data source register address.
2276 * @param[in] dest Destination data address.
2277 * @param[in] count Number of words to transfer.
2278 * @param[in] linkjmp Address of descriptor to link to, expressed as a
2279 * signed number of descriptors from "here".
2280 * 1=one descriptor forward in memory,
2281 * 0=this descriptor,
2282 * -1=one descriptor back in memory.
2283 */
2284 #define LDMA_DESCRIPTOR_LINKREL_P2M_WORD_EXTEND(src, dest, count, linkjmp) \
2285 { \
2286 .structType = ldmaCtrlStructTypeXfer, \
2287 .extend = 1, \
2288 .structReq = 0, \
2289 .xferCnt = (count) - 1, \
2290 .byteSwap = 0, \
2291 .blockSize = ldmaCtrlBlockSizeUnit1, \
2292 .doneIfs = 1, \
2293 .reqMode = ldmaCtrlReqModeBlock, \
2294 .decLoopCnt = 0, \
2295 .ignoreSrec = 0, \
2296 .srcInc = ldmaCtrlSrcIncNone, \
2297 .size = ldmaCtrlSizeWord, \
2298 .dstInc = ldmaCtrlDstIncNone, \
2299 .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \
2300 .dstAddrMode = ldmaCtrlDstAddrModeAbs, \
2301 .srcAddr = (uint32_t)(src), \
2302 .dstAddr = (uint32_t)(dest), \
2303 .linkMode = ldmaLinkModeRel, \
2304 .link = 1, \
2305 .linkAddr = (linkjmp) * LDMA_DESCRIPTOR_EXTEND_SIZE_WORD, \
2306 .dstIlEn = 0, \
2307 .IlMode = 0, \
2308 .bufferable = 0, \
2309 .IlSrc = 0 \
2310 }
2311 #endif
2312
2313 /**
2314 * @brief
2315 * DMA descriptor initializer for byte transfers from memory to a peripheral.
2316 * @param[in] src Source data address.
2317 * @param[in] dest Peripheral data register destination address.
2318 * @param[in] count Number of bytes to transfer.
2319 * @param[in] linkjmp Address of descriptor to link to, expressed as a
2320 * signed number of descriptors from "here".
2321 * 1=one descriptor forward in memory,
2322 * 0=this descriptor,
2323 * -1=one descriptor back in memory.
2324 */
2325 #define LDMA_DESCRIPTOR_LINKREL_M2P_BYTE(src, dest, count, linkjmp) \
2326 { \
2327 .xfer = \
2328 { \
2329 .structType = ldmaCtrlStructTypeXfer, \
2330 .structReq = 0, \
2331 .xferCnt = (count) - 1, \
2332 .byteSwap = 0, \
2333 .blockSize = ldmaCtrlBlockSizeUnit1, \
2334 .doneIfs = 1, \
2335 .reqMode = ldmaCtrlReqModeBlock, \
2336 .decLoopCnt = 0, \
2337 .ignoreSrec = 0, \
2338 .srcInc = ldmaCtrlSrcIncOne, \
2339 .size = ldmaCtrlSizeByte, \
2340 .dstInc = ldmaCtrlDstIncNone, \
2341 .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \
2342 .dstAddrMode = ldmaCtrlDstAddrModeAbs, \
2343 .srcAddr = (uint32_t)(src), \
2344 .dstAddr = (uint32_t)(dest), \
2345 .linkMode = ldmaLinkModeRel, \
2346 .link = 1, \
2347 .linkAddr = (linkjmp) * LDMA_DESCRIPTOR_NON_EXTEND_SIZE_WORD \
2348 } \
2349 }
2350
2351 #if defined(_LDMA_CH_CTRL_EXTEND_MASK)
2352 /**
2353 * @brief
2354 * DMA descriptor initializer for byte transfers from memory to a peripheral
2355 * using the extended descriptor fields.
2356 * @note
2357 * For the extended descriptor, if IlMode uses the absolute addressing, the
2358 * rules are used directly as the destination addresses of the corresponding
2359 * data. Thus the argument 'dest' will be ignored by the DMA engine.
2360 * @param[in] src Source data address.
2361 * @param[in] dest Peripheral data register destination address.
2362 * @param[in] count Number of bytes to transfer.
2363 * @param[in] linkjmp Address of descriptor to link to, expressed as a
2364 * signed number of descriptors from "here".
2365 * 1=one descriptor forward in memory,
2366 * 0=this descriptor,
2367 * -1=one descriptor back in memory.
2368 */
2369 #define LDMA_DESCRIPTOR_LINKREL_M2P_BYTE_EXTEND(src, dest, count, linkjmp) \
2370 { \
2371 .structType = ldmaCtrlStructTypeXfer, \
2372 .extend = 1, \
2373 .structReq = 0, \
2374 .xferCnt = (count) - 1, \
2375 .byteSwap = 0, \
2376 .blockSize = ldmaCtrlBlockSizeUnit1, \
2377 .doneIfs = 1, \
2378 .reqMode = ldmaCtrlReqModeBlock, \
2379 .decLoopCnt = 0, \
2380 .ignoreSrec = 0, \
2381 .srcInc = ldmaCtrlSrcIncOne, \
2382 .size = ldmaCtrlSizeByte, \
2383 .dstInc = ldmaCtrlDstIncNone, \
2384 .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \
2385 .dstAddrMode = ldmaCtrlDstAddrModeAbs, \
2386 .srcAddr = (uint32_t)(src), \
2387 .dstAddr = (uint32_t)(dest), \
2388 .linkMode = ldmaLinkModeRel, \
2389 .link = 1, \
2390 .linkAddr = (linkjmp) * LDMA_DESCRIPTOR_EXTEND_SIZE_WORD, \
2391 .dstIlEn = 0, \
2392 .IlMode = 0, \
2393 .bufferable = 0, \
2394 .IlSrc = 0 \
2395 }
2396 #endif
2397
2398 /**
2399 * @brief
2400 * DMA descriptor initializer for Immediate WRITE transfer
2401 * @param[in] value Immediate value to write.
2402 * @param[in] address Write address.
2403 */
2404 #define LDMA_DESCRIPTOR_SINGLE_WRITE(value, address) \
2405 { \
2406 .wri = \
2407 { \
2408 .structType = ldmaCtrlStructTypeWrite, \
2409 .structReq = 1, \
2410 .xferCnt = 0, \
2411 .byteSwap = 0, \
2412 .blockSize = 0, \
2413 .doneIfs = 1, \
2414 .reqMode = 0, \
2415 .decLoopCnt = 0, \
2416 .ignoreSrec = 0, \
2417 .srcInc = 0, \
2418 .size = 0, \
2419 .dstInc = 0, \
2420 .srcAddrMode = 0, \
2421 .dstAddrMode = 0, \
2422 .immVal = (value), \
2423 .dstAddr = (uint32_t)(address), \
2424 .linkMode = 0, \
2425 .link = 0, \
2426 .linkAddr = 0 \
2427 } \
2428 }
2429
2430 /**
2431 * @brief
2432 * DMA descriptor initializer for Immediate WRITE transfer
2433 *
2434 * Link address must be an absolute address.
2435 * @note
2436 * The linkAddr member of the transfer descriptor is not initialized.
2437 * linkAddr must be initialized by using the proper bits right-shift
2438 * to get the correct bits from the absolute address.
2439 * LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR should be used for that operation:
2440 * @code
2441 desc.linkAddr = LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR(&next_desc);@endcode
2442 * The opposite bit shift (left) must be done with LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR
2443 * if linkAddr is read.
2444 * @param[in] value Immediate value to write.
2445 * @param[in] address Write address.
2446 */
2447 #define LDMA_DESCRIPTOR_LINKABS_WRITE(value, address) \
2448 { \
2449 .wri = \
2450 { \
2451 .structType = ldmaCtrlStructTypeWrite, \
2452 .structReq = 1, \
2453 .xferCnt = 0, \
2454 .byteSwap = 0, \
2455 .blockSize = 0, \
2456 .doneIfs = 0, \
2457 .reqMode = 0, \
2458 .decLoopCnt = 0, \
2459 .ignoreSrec = 0, \
2460 .srcInc = 0, \
2461 .size = 0, \
2462 .dstInc = 0, \
2463 .srcAddrMode = 0, \
2464 .dstAddrMode = 0, \
2465 .immVal = (value), \
2466 .dstAddr = (uint32_t)(address), \
2467 .linkMode = ldmaLinkModeAbs, \
2468 .link = 1, \
2469 .linkAddr = 0 /* Must be set runtime ! */ \
2470 } \
2471 }
2472
2473 /**
2474 * @brief
2475 * DMA descriptor initializer for Immediate WRITE transfer
2476 * @param[in] value Immediate value to write.
2477 * @param[in] address Write address.
2478 * @param[in] linkjmp Address of descriptor to link to, expressed as a
2479 * signed number of descriptors from "here".
2480 * 1=one descriptor forward in memory,
2481 * 0=this descriptor,
2482 * -1=one descriptor back in memory.
2483 */
2484 #define LDMA_DESCRIPTOR_LINKREL_WRITE(value, address, linkjmp) \
2485 { \
2486 .wri = \
2487 { \
2488 .structType = ldmaCtrlStructTypeWrite, \
2489 .structReq = 1, \
2490 .xferCnt = 0, \
2491 .byteSwap = 0, \
2492 .blockSize = 0, \
2493 .doneIfs = 0, \
2494 .reqMode = 0, \
2495 .decLoopCnt = 0, \
2496 .ignoreSrec = 0, \
2497 .srcInc = 0, \
2498 .size = 0, \
2499 .dstInc = 0, \
2500 .srcAddrMode = 0, \
2501 .dstAddrMode = 0, \
2502 .immVal = (value), \
2503 .dstAddr = (uint32_t)(address), \
2504 .linkMode = ldmaLinkModeRel, \
2505 .link = 1, \
2506 .linkAddr = (linkjmp) * LDMA_DESCRIPTOR_NON_EXTEND_SIZE_WORD \
2507 } \
2508 }
2509
2510 /**
2511 * @brief
2512 * DMA descriptor initializer for SYNC transfer
2513 * @param[in] set Sync pattern bits to set.
2514 * @param[in] clr Sync pattern bits to clear.
2515 * @param[in] matchValue Sync pattern to match.
2516 * @param[in] matchEnable Sync pattern bits to enable for match.
2517 */
2518 #define LDMA_DESCRIPTOR_SINGLE_SYNC(set, clr, matchValue, matchEnable) \
2519 { \
2520 .sync = \
2521 { \
2522 .structType = ldmaCtrlStructTypeSync, \
2523 .structReq = 1, \
2524 .xferCnt = 0, \
2525 .byteSwap = 0, \
2526 .blockSize = 0, \
2527 .doneIfs = 1, \
2528 .reqMode = 0, \
2529 .decLoopCnt = 0, \
2530 .ignoreSrec = 0, \
2531 .srcInc = 0, \
2532 .size = 0, \
2533 .dstInc = 0, \
2534 .srcAddrMode = 0, \
2535 .dstAddrMode = 0, \
2536 .syncSet = (set), \
2537 .syncClr = (clr), \
2538 .matchVal = (matchValue), \
2539 .matchEn = (matchEnable), \
2540 .linkMode = 0, \
2541 .link = 0, \
2542 .linkAddr = 0 \
2543 } \
2544 }
2545
2546 /**
2547 * @brief
2548 * DMA descriptor initializer for SYNC transfer
2549 *
2550 * Link address must be an absolute address.
2551 * @note
2552 * The linkAddr member of the transfer descriptor is not initialized.
2553 * linkAddr must be initialized by using the proper bits right-shift
2554 * to get the correct bits from the absolute address.
2555 * LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR should be used for that operation:
2556 * @code
2557 desc.linkAddr = LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR(&next_desc);@endcode
2558 * The opposite bit shift (left) must be done with LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR
2559 * if linkAddr is read.
2560 * @param[in] set Sync pattern bits to set.
2561 * @param[in] clr Sync pattern bits to clear.
2562 * @param[in] matchValue Sync pattern to match.
2563 * @param[in] matchEnable Sync pattern bits to enable for match.
2564 */
2565 #define LDMA_DESCRIPTOR_LINKABS_SYNC(set, clr, matchValue, matchEnable) \
2566 { \
2567 .sync = \
2568 { \
2569 .structType = ldmaCtrlStructTypeSync, \
2570 .structReq = 1, \
2571 .xferCnt = 0, \
2572 .byteSwap = 0, \
2573 .blockSize = 0, \
2574 .doneIfs = 0, \
2575 .reqMode = 0, \
2576 .decLoopCnt = 0, \
2577 .ignoreSrec = 0, \
2578 .srcInc = 0, \
2579 .size = 0, \
2580 .dstInc = 0, \
2581 .srcAddrMode = 0, \
2582 .dstAddrMode = 0, \
2583 .syncSet = (set), \
2584 .syncClr = (clr), \
2585 .matchVal = (matchValue), \
2586 .matchEn = (matchEnable), \
2587 .linkMode = ldmaLinkModeAbs, \
2588 .link = 1, \
2589 .linkAddr = 0 /* Must be set runtime ! */ \
2590 } \
2591 }
2592
2593 /**
2594 * @brief
2595 * DMA descriptor initializer for SYNC transfer
2596 * @param[in] set Sync pattern bits to set.
2597 * @param[in] clr Sync pattern bits to clear.
2598 * @param[in] matchValue Sync pattern to match.
2599 * @param[in] matchEnable Sync pattern bits to enable for match.
2600 * @param[in] linkjmp Address of descriptor to link to, expressed as a
2601 * signed number of descriptors from "here".
2602 * 1=one descriptor forward in memory,
2603 * 0=this descriptor,
2604 * -1=one descriptor back in memory.
2605 */
2606 #define LDMA_DESCRIPTOR_LINKREL_SYNC(set, clr, matchValue, matchEnable, linkjmp) \
2607 { \
2608 .sync = \
2609 { \
2610 .structType = ldmaCtrlStructTypeSync, \
2611 .structReq = 1, \
2612 .xferCnt = 0, \
2613 .byteSwap = 0, \
2614 .blockSize = 0, \
2615 .doneIfs = 0, \
2616 .reqMode = 0, \
2617 .decLoopCnt = 0, \
2618 .ignoreSrec = 0, \
2619 .srcInc = 0, \
2620 .size = 0, \
2621 .dstInc = 0, \
2622 .srcAddrMode = 0, \
2623 .dstAddrMode = 0, \
2624 .syncSet = (set), \
2625 .syncClr = (clr), \
2626 .matchVal = (matchValue), \
2627 .matchEn = (matchEnable), \
2628 .linkMode = ldmaLinkModeRel, \
2629 .link = 1, \
2630 .linkAddr = (linkjmp) * LDMA_DESCRIPTOR_NON_EXTEND_SIZE_WORD \
2631 } \
2632 }
2633
2634 #if defined(_LDMA_CH_CTRL_EXTEND_MASK)
2635 /**
2636 * @brief
2637 * Initializer for the destination interleaving portion of the DMA extended descriptor.
2638 * @param[in] desc Transfer-type descriptor.
2639 * @param[in] ilmode Rules table addressing mode for interleaved data.
2640 * @param[in] ilsrc Base address for rules table in memory.
2641 */
2642 #define LDMA_DESCRIPTOR_EXTEND_DST_IL_CFG(desc, ilmode, ilsrc) \
2643 { \
2644 (desc).dstIlEn = true; \
2645 (desc).IlMode = (ilmode); \
2646 (desc).IlSrc = (uint32_t)(ilsrc); \
2647 }
2648 #endif
2649
2650 /*******************************************************************************
2651 ***************************** PROTOTYPES **********************************
2652 ******************************************************************************/
2653
2654 void LDMA_DeInit(void);
2655 void LDMA_EnableChannelRequest(int ch, bool enable);
2656 void LDMA_Init(const LDMA_Init_t *init);
2657 void LDMA_StartTransfer(int ch,
2658 const LDMA_TransferCfg_t *transfer,
2659 const LDMA_Descriptor_t *descriptor);
2660 #if defined(_LDMA_CH_CTRL_EXTEND_MASK)
2661 void LDMA_StartTransferExtend(int ch,
2662 const LDMA_TransferCfg_t *transfer,
2663 const LDMA_DescriptorExtend_t *descriptor_ext);
2664 #endif
2665 void LDMA_StopTransfer(int ch);
2666 bool LDMA_TransferDone(int ch);
2667 uint32_t LDMA_TransferRemainingCount(int ch);
2668
2669 #if defined(_LDMA_SWRST_MASK)
2670 /***************************************************************************//**
2671 * @brief
2672 * Reset the LDMA.
2673 ******************************************************************************/
LDMA_Reset(void)2674 __STATIC_INLINE void LDMA_Reset(void)
2675 {
2676 LDMA->SWRST_SET = LDMA_SWRST_SWRST;
2677
2678 /* Wait for reset to complete. */
2679 while (0UL != (LDMA->SWRST & _LDMA_SWRST_RESETTING_MASK)) {
2680 }
2681 }
2682 #endif
2683
2684 /***************************************************************************//**
2685 * @brief
2686 * Check if a certain channel is enabled.
2687 *
2688 * @param[in] ch
2689 * LDMA channel to check.
2690 *
2691 * @return
2692 * return true if the LDMA channel is enabled and false if the channel is not
2693 * enabled.
2694 ******************************************************************************/
LDMA_ChannelEnabled(int ch)2695 __STATIC_INLINE bool LDMA_ChannelEnabled(int ch)
2696 {
2697 if ((ch < 0) || (ch > 31)) {
2698 return false;
2699 }
2700 #if defined(_LDMA_CHSTATUS_MASK)
2701 return (0UL != (LDMA->CHSTATUS & (1UL << (uint8_t)ch)));
2702 #else
2703 // We've already confirmed ch is between 0 and 31,
2704 // so it's now safe to cast it to uint8_t
2705 return (0UL != (LDMA->CHEN & (1 << (uint8_t)ch)));
2706 #endif
2707 }
2708
2709 /***************************************************************************//**
2710 * @brief
2711 * Clear one or more pending LDMA interrupts.
2712 *
2713 * @param[in] flags
2714 * Pending LDMA interrupt sources to clear. Use one or more valid
2715 * interrupt flags for the LDMA module. The flags are LDMA_IFC_ERROR
2716 * and one done flag for each channel.
2717 ******************************************************************************/
LDMA_IntClear(uint32_t flags)2718 __STATIC_INLINE void LDMA_IntClear(uint32_t flags)
2719 {
2720 #if defined (LDMA_HAS_SET_CLEAR)
2721 LDMA->IF_CLR = flags;
2722 #else
2723 LDMA->IFC = flags;
2724 #endif
2725 }
2726
2727 /***************************************************************************//**
2728 * @brief
2729 * Disable one or more LDMA interrupts.
2730 *
2731 * @param[in] flags
2732 * LDMA interrupt sources to disable. Use one or more valid
2733 * interrupt flags for LDMA module. The flags are LDMA_IEN_ERROR
2734 * and one done flag for each channel.
2735 ******************************************************************************/
LDMA_IntDisable(uint32_t flags)2736 __STATIC_INLINE void LDMA_IntDisable(uint32_t flags)
2737 {
2738 LDMA->IEN &= ~flags;
2739 }
2740
2741 /***************************************************************************//**
2742 * @brief
2743 * Enable one or more LDMA interrupts.
2744 *
2745 * @note
2746 * Depending on the use, a pending interrupt may already be set prior to
2747 * enabling the interrupt. To ignore a pending interrupt, consider using
2748 * LDMA_IntClear() prior to enabling the interrupt.
2749 *
2750 * @param[in] flags
2751 * LDMA interrupt sources to enable. Use one or more valid
2752 * interrupt flags for LDMA module. The flags are LDMA_IEN_ERROR
2753 * and one done flag for each channel.
2754 ******************************************************************************/
LDMA_IntEnable(uint32_t flags)2755 __STATIC_INLINE void LDMA_IntEnable(uint32_t flags)
2756 {
2757 LDMA->IEN |= flags;
2758 }
2759
2760 /***************************************************************************//**
2761 * @brief
2762 * Get pending LDMA interrupt flags.
2763 *
2764 * @note
2765 * Event bits are not cleared by the use of this function.
2766 *
2767 * @return
2768 * LDMA interrupt sources pending. Returns one or more valid
2769 * interrupt flags for LDMA module. The flags are LDMA_IF_ERROR and
2770 * one flag for each LDMA channel.
2771 ******************************************************************************/
LDMA_IntGet(void)2772 __STATIC_INLINE uint32_t LDMA_IntGet(void)
2773 {
2774 return LDMA->IF;
2775 }
2776
2777 /***************************************************************************//**
2778 * @brief
2779 * Get enabled and pending LDMA interrupt flags.
2780 * Useful for handling more interrupt sources in the same interrupt handler.
2781 *
2782 * @note
2783 * Interrupt flags are not cleared by the use of this function.
2784 *
2785 * @return
2786 * Pending and enabled LDMA interrupt sources
2787 * Return value is the bitwise AND of
2788 * - the enabled interrupt sources in LDMA_IEN and
2789 * - the pending interrupt flags LDMA_IF
2790 ******************************************************************************/
LDMA_IntGetEnabled(void)2791 __STATIC_INLINE uint32_t LDMA_IntGetEnabled(void)
2792 {
2793 uint32_t ien;
2794
2795 ien = LDMA->IEN;
2796 return LDMA->IF & ien;
2797 }
2798
2799 /***************************************************************************//**
2800 * @brief
2801 * Set one or more pending LDMA interrupts
2802 *
2803 * @param[in] flags
2804 * LDMA interrupt sources to set to pending. Use one or more valid
2805 * interrupt flags for LDMA module. The flags are LDMA_IFS_ERROR and
2806 * one done flag for each LDMA channel.
2807 ******************************************************************************/
LDMA_IntSet(uint32_t flags)2808 __STATIC_INLINE void LDMA_IntSet(uint32_t flags)
2809 {
2810 #if defined (LDMA_HAS_SET_CLEAR)
2811 LDMA->IF_SET = flags;
2812 #else
2813 LDMA->IFS = flags;
2814 #endif
2815 }
2816
2817 /** @} (end addtogroup ldma) */
2818
2819 #ifdef __cplusplus
2820 }
2821 #endif
2822
2823 #endif /* defined( LDMA_PRESENT ) && ( LDMA_COUNT == 1 ) */
2824 #endif /* EM_LDMA_H */
2825
