1 //------------------------------------------------------------------------------
2 // Copyright 2012 (c) Silicon Laboratories Inc.
3 //
4 // SPDX-License-Identifier: Zlib
5 //
6 // This siHAL software is provided 'as-is', without any express or implied
7 // warranty. In no event will the authors be held liable for any damages
8 // arising from the use of this software.
9 //
10 // Permission is granted to anyone to use this software for any purpose,
11 // including commercial applications, and to alter it and redistribute it
12 // freely, subject to the following restrictions:
13 //
14 // 1. The origin of this software must not be misrepresented; you must not
15 //    claim that you wrote the original software. If you use this software
16 //    in a product, an acknowledgment in the product documentation would be
17 //    appreciated but is not required.
18 // 2. Altered source versions must be plainly marked as such, and must not be
19 //    misrepresented as being the original software.
20 // 3. This notice may not be removed or altered from any source distribution.
21 //------------------------------------------------------------------------------
22 //
23 // This file applies to the SIM3L1XX_SLEEPCTRL_A module
24 //
25 // Script: 0.56
26 // Version: 1
27 
28 #ifndef __SI32_SLEEPCTRL_A_REGISTERS_H__
29 #define __SI32_SLEEPCTRL_A_REGISTERS_H__
30 
31 #include <stdint.h>
32 
33 #ifdef __cplusplus
34 extern "C" {
35 #endif
36 
37 struct SI32_SLEEPCTRL_A_CONTROL_Struct
38 {
39    union
40    {
41       struct
42       {
43          // CLKDIV
44          volatile uint32_t CLKDIV: 2;
45          // CPMD
46          volatile uint32_t CPMD: 2;
47                   uint32_t reserved0: 28;
48       };
49       volatile uint32_t U32;
50    };
51 };
52 
53 #define SI32_SLEEPCTRL_A_CONTROL_CLKDIV_MASK  0x00000003
54 #define SI32_SLEEPCTRL_A_CONTROL_CLKDIV_SHIFT  0
55 // Undivided RTC clock
56 #define SI32_SLEEPCTRL_A_CONTROL_CLKDIV_DIV1_VALUE  0
57 #define SI32_SLEEPCTRL_A_CONTROL_CLKDIV_DIV1_U32 \
58    (SI32_SLEEPCTRL_A_CONTROL_CLKDIV_DIV1_VALUE << SI32_SLEEPCTRL_A_CONTROL_CLKDIV_SHIFT)
59 // RTC clock divided by 2
60 #define SI32_SLEEPCTRL_A_CONTROL_CLKDIV_DIV2_VALUE  1
61 #define SI32_SLEEPCTRL_A_CONTROL_CLKDIV_DIV2_U32 \
62    (SI32_SLEEPCTRL_A_CONTROL_CLKDIV_DIV2_VALUE << SI32_SLEEPCTRL_A_CONTROL_CLKDIV_SHIFT)
63 // RTC clock divided by 4
64 #define SI32_SLEEPCTRL_A_CONTROL_CLKDIV_DIV4_VALUE  2
65 #define SI32_SLEEPCTRL_A_CONTROL_CLKDIV_DIV4_U32 \
66    (SI32_SLEEPCTRL_A_CONTROL_CLKDIV_DIV4_VALUE << SI32_SLEEPCTRL_A_CONTROL_CLKDIV_SHIFT)
67 // RTC clock divided by 8
68 #define SI32_SLEEPCTRL_A_CONTROL_CLKDIV_DIV8_VALUE  3
69 #define SI32_SLEEPCTRL_A_CONTROL_CLKDIV_DIV8_U32 \
70    (SI32_SLEEPCTRL_A_CONTROL_CLKDIV_DIV8_VALUE << SI32_SLEEPCTRL_A_CONTROL_CLKDIV_SHIFT)
71 
72 #define SI32_SLEEPCTRL_A_CONTROL_CPMD_MASK  0x0000000C
73 #define SI32_SLEEPCTRL_A_CONTROL_CPMD_SHIFT  2
74 // VBAT is passed directly to VCP
75 #define SI32_SLEEPCTRL_A_CONTROL_CPMD_VBAT_VALUE  0
76 #define SI32_SLEEPCTRL_A_CONTROL_CPMD_VBAT_U32 \
77    (SI32_SLEEPCTRL_A_CONTROL_CPMD_VBAT_VALUE << SI32_SLEEPCTRL_A_CONTROL_CPMD_SHIFT)
78 // VCP equals VBAT / 2
79 #define SI32_SLEEPCTRL_A_CONTROL_CPMD_VBATDIV2_VALUE  1
80 #define SI32_SLEEPCTRL_A_CONTROL_CPMD_VBATDIV2_U32 \
81    (SI32_SLEEPCTRL_A_CONTROL_CPMD_VBATDIV2_VALUE << SI32_SLEEPCTRL_A_CONTROL_CPMD_SHIFT)
82 // VCP is tri-stated
83 #define SI32_SLEEPCTRL_A_CONTROL_CPMD_TRISTATE_VALUE  2
84 #define SI32_SLEEPCTRL_A_CONTROL_CPMD_TRISTATE_U32 \
85    (SI32_SLEEPCTRL_A_CONTROL_CPMD_TRISTATE_VALUE << SI32_SLEEPCTRL_A_CONTROL_CPMD_SHIFT)
86 // VCP is connected to ground
87 #define SI32_SLEEPCTRL_A_CONTROL_CPMD_GROUND_VALUE  3
88 #define SI32_SLEEPCTRL_A_CONTROL_CPMD_GROUND_U32 \
89    (SI32_SLEEPCTRL_A_CONTROL_CPMD_GROUND_VALUE << SI32_SLEEPCTRL_A_CONTROL_CPMD_SHIFT)
90 
91 
92 
93 typedef struct SI32_SLEEPCTRL_A_Struct
94 {
95    uint32_t                                        reserved0[4];
96    struct SI32_SLEEPCTRL_A_CONTROL_Struct          CONTROL        ; // Base Address + 0x10
97    volatile uint32_t                               CONTROL_SET;
98    volatile uint32_t                               CONTROL_CLR;
99    uint32_t                                        reserved1;
100 } SI32_SLEEPCTRL_A_Type;
101 
102 #ifdef __cplusplus
103 }
104 #endif
105 
106 #endif // __SI32_SLEEPCTRL_A_REGISTERS_H__
107 
108 //-eof--------------------------------------------------------------------------
109 
110