1 //----------------------------------------------------------------------------- 2 // Copyright 2012 (c) Silicon Laboratories Inc. 3 // 4 // SPDX-License-Identifier: Zlib 5 // 6 // This siHAL software is provided 'as-is', without any express or implied 7 // warranty. In no event will the authors be held liable for any damages 8 // arising from the use of this software. 9 // 10 // Permission is granted to anyone to use this software for any purpose, 11 // including commercial applications, and to alter it and redistribute it 12 // freely, subject to the following restrictions: 13 // 14 // 1. The origin of this software must not be misrepresented; you must not 15 // claim that you wrote the original software. If you use this software 16 // in a product, an acknowledgment in the product documentation would be 17 // appreciated but is not required. 18 // 2. Altered source versions must be plainly marked as such, and must not be 19 // misrepresented as being the original software. 20 // 3. This notice may not be removed or altered from any source distribution. 21 //----------------------------------------------------------------------------- 22 // 23 // This file applies to the SIM3L1XX_CLKCTRL_A module 24 // 25 // Script: 0.61 26 // Version: 1 27 28 #ifndef __SI32_CLKCTRL_A_REGISTERS_H__ 29 #define __SI32_CLKCTRL_A_REGISTERS_H__ 30 31 #include <stdint.h> 32 33 #ifdef __cplusplus 34 extern "C" { 35 #endif 36 37 struct SI32_CLKCTRL_A_CONTROL_Struct 38 { 39 union 40 { 41 struct 42 { 43 // AHB Clock Source Select 44 volatile uint32_t AHBSEL: 3; 45 uint32_t reserved0: 5; 46 // AHB Clock Divider 47 volatile uint32_t AHBDIV: 3; 48 uint32_t reserved1: 5; 49 // APB Clock Divider 50 volatile uint32_t APBDIV: 1; 51 uint32_t reserved2: 11; 52 // External Clock Edge Select 53 volatile uint32_t EXTESEL: 1; 54 // Oscillators Busy Flag 55 volatile uint32_t OBUSYF: 1; 56 // VIORF Clock Enable 57 volatile uint32_t VIORFCLKEN: 1; 58 // External Clock Input Enable 59 volatile uint32_t EXTOSCEN: 1; 60 }; 61 volatile uint32_t U32; 62 }; 63 }; 64 65 #define SI32_CLKCTRL_A_CONTROL_AHBSEL_MASK 0x00000007 66 #define SI32_CLKCTRL_A_CONTROL_AHBSEL_SHIFT 0 67 // AHB clock source is the Low-Power Oscillator. 68 #define SI32_CLKCTRL_A_CONTROL_AHBSEL_LPOSC0_VALUE 0 69 #define SI32_CLKCTRL_A_CONTROL_AHBSEL_LPOSC0_U32 \ 70 (SI32_CLKCTRL_A_CONTROL_AHBSEL_LPOSC0_VALUE << SI32_CLKCTRL_A_CONTROL_AHBSEL_SHIFT) 71 // AHB clock source is the Low-Frequency Oscillator. 72 #define SI32_CLKCTRL_A_CONTROL_AHBSEL_LFOSC0_VALUE 1 73 #define SI32_CLKCTRL_A_CONTROL_AHBSEL_LFOSC0_U32 \ 74 (SI32_CLKCTRL_A_CONTROL_AHBSEL_LFOSC0_VALUE << SI32_CLKCTRL_A_CONTROL_AHBSEL_SHIFT) 75 // AHB clock source is the RTC0TCLK signal. 76 #define SI32_CLKCTRL_A_CONTROL_AHBSEL_RTC0TCLK_VALUE 2 77 #define SI32_CLKCTRL_A_CONTROL_AHBSEL_RTC0TCLK_U32 \ 78 (SI32_CLKCTRL_A_CONTROL_AHBSEL_RTC0TCLK_VALUE << SI32_CLKCTRL_A_CONTROL_AHBSEL_SHIFT) 79 // AHB clock source is the External Oscillator. 80 #define SI32_CLKCTRL_A_CONTROL_AHBSEL_EXTOSC0_VALUE 3 81 #define SI32_CLKCTRL_A_CONTROL_AHBSEL_EXTOSC0_U32 \ 82 (SI32_CLKCTRL_A_CONTROL_AHBSEL_EXTOSC0_VALUE << SI32_CLKCTRL_A_CONTROL_AHBSEL_SHIFT) 83 // AHB clock source is the VIORFCLK input pin. 84 #define SI32_CLKCTRL_A_CONTROL_AHBSEL_VIORFCLK_VALUE 4 85 #define SI32_CLKCTRL_A_CONTROL_AHBSEL_VIORFCLK_U32 \ 86 (SI32_CLKCTRL_A_CONTROL_AHBSEL_VIORFCLK_VALUE << SI32_CLKCTRL_A_CONTROL_AHBSEL_SHIFT) 87 // AHB clock source is the PLL. 88 #define SI32_CLKCTRL_A_CONTROL_AHBSEL_PLL0OSC_VALUE 5 89 #define SI32_CLKCTRL_A_CONTROL_AHBSEL_PLL0OSC_U32 \ 90 (SI32_CLKCTRL_A_CONTROL_AHBSEL_PLL0OSC_VALUE << SI32_CLKCTRL_A_CONTROL_AHBSEL_SHIFT) 91 // AHB clock source is a divided version of the Low-Power Oscillator. 92 #define SI32_CLKCTRL_A_CONTROL_AHBSEL_LPOSC0_DIV_VALUE 6 93 #define SI32_CLKCTRL_A_CONTROL_AHBSEL_LPOSC0_DIV_U32 \ 94 (SI32_CLKCTRL_A_CONTROL_AHBSEL_LPOSC0_DIV_VALUE << SI32_CLKCTRL_A_CONTROL_AHBSEL_SHIFT) 95 96 #define SI32_CLKCTRL_A_CONTROL_AHBDIV_MASK 0x00000700 97 #define SI32_CLKCTRL_A_CONTROL_AHBDIV_SHIFT 8 98 // AHB clock divided by 1. 99 #define SI32_CLKCTRL_A_CONTROL_AHBDIV_DIV1_VALUE 0 100 #define SI32_CLKCTRL_A_CONTROL_AHBDIV_DIV1_U32 \ 101 (SI32_CLKCTRL_A_CONTROL_AHBDIV_DIV1_VALUE << SI32_CLKCTRL_A_CONTROL_AHBDIV_SHIFT) 102 // AHB clock divided by 2. 103 #define SI32_CLKCTRL_A_CONTROL_AHBDIV_DIV2_VALUE 1 104 #define SI32_CLKCTRL_A_CONTROL_AHBDIV_DIV2_U32 \ 105 (SI32_CLKCTRL_A_CONTROL_AHBDIV_DIV2_VALUE << SI32_CLKCTRL_A_CONTROL_AHBDIV_SHIFT) 106 // AHB clock divided by 4. 107 #define SI32_CLKCTRL_A_CONTROL_AHBDIV_DIV4_VALUE 2 108 #define SI32_CLKCTRL_A_CONTROL_AHBDIV_DIV4_U32 \ 109 (SI32_CLKCTRL_A_CONTROL_AHBDIV_DIV4_VALUE << SI32_CLKCTRL_A_CONTROL_AHBDIV_SHIFT) 110 // AHB clock divided by 8. 111 #define SI32_CLKCTRL_A_CONTROL_AHBDIV_DIV8_VALUE 3 112 #define SI32_CLKCTRL_A_CONTROL_AHBDIV_DIV8_U32 \ 113 (SI32_CLKCTRL_A_CONTROL_AHBDIV_DIV8_VALUE << SI32_CLKCTRL_A_CONTROL_AHBDIV_SHIFT) 114 // AHB clock divided by 16. 115 #define SI32_CLKCTRL_A_CONTROL_AHBDIV_DIV16_VALUE 4 116 #define SI32_CLKCTRL_A_CONTROL_AHBDIV_DIV16_U32 \ 117 (SI32_CLKCTRL_A_CONTROL_AHBDIV_DIV16_VALUE << SI32_CLKCTRL_A_CONTROL_AHBDIV_SHIFT) 118 // AHB clock divided by 32. 119 #define SI32_CLKCTRL_A_CONTROL_AHBDIV_DIV32_VALUE 5 120 #define SI32_CLKCTRL_A_CONTROL_AHBDIV_DIV32_U32 \ 121 (SI32_CLKCTRL_A_CONTROL_AHBDIV_DIV32_VALUE << SI32_CLKCTRL_A_CONTROL_AHBDIV_SHIFT) 122 // AHB clock divided by 64. 123 #define SI32_CLKCTRL_A_CONTROL_AHBDIV_DIV64_VALUE 6 124 #define SI32_CLKCTRL_A_CONTROL_AHBDIV_DIV64_U32 \ 125 (SI32_CLKCTRL_A_CONTROL_AHBDIV_DIV64_VALUE << SI32_CLKCTRL_A_CONTROL_AHBDIV_SHIFT) 126 // AHB clock divided by 128. 127 #define SI32_CLKCTRL_A_CONTROL_AHBDIV_DIV128_VALUE 7 128 #define SI32_CLKCTRL_A_CONTROL_AHBDIV_DIV128_U32 \ 129 (SI32_CLKCTRL_A_CONTROL_AHBDIV_DIV128_VALUE << SI32_CLKCTRL_A_CONTROL_AHBDIV_SHIFT) 130 131 #define SI32_CLKCTRL_A_CONTROL_APBDIV_MASK 0x00010000 132 #define SI32_CLKCTRL_A_CONTROL_APBDIV_SHIFT 16 133 // APB clock is the same as the AHB clock (divided by 1). 134 #define SI32_CLKCTRL_A_CONTROL_APBDIV_DIV1_VALUE 0 135 #define SI32_CLKCTRL_A_CONTROL_APBDIV_DIV1_U32 \ 136 (SI32_CLKCTRL_A_CONTROL_APBDIV_DIV1_VALUE << SI32_CLKCTRL_A_CONTROL_APBDIV_SHIFT) 137 // APB clock is the AHB clock divided by 2. 138 #define SI32_CLKCTRL_A_CONTROL_APBDIV_DIV2_VALUE 1 139 #define SI32_CLKCTRL_A_CONTROL_APBDIV_DIV2_U32 \ 140 (SI32_CLKCTRL_A_CONTROL_APBDIV_DIV2_VALUE << SI32_CLKCTRL_A_CONTROL_APBDIV_SHIFT) 141 142 #define SI32_CLKCTRL_A_CONTROL_EXTESEL_MASK 0x10000000 143 #define SI32_CLKCTRL_A_CONTROL_EXTESEL_SHIFT 28 144 // External clock generated by both rising and falling edges of the external 145 // oscillator. 146 #define SI32_CLKCTRL_A_CONTROL_EXTESEL_BOTH_EDGES_VALUE 0 147 #define SI32_CLKCTRL_A_CONTROL_EXTESEL_BOTH_EDGES_U32 \ 148 (SI32_CLKCTRL_A_CONTROL_EXTESEL_BOTH_EDGES_VALUE << SI32_CLKCTRL_A_CONTROL_EXTESEL_SHIFT) 149 // External clock generated by only rising edges of the external oscillator. 150 #define SI32_CLKCTRL_A_CONTROL_EXTESEL_RISING_ONLY_VALUE 1 151 #define SI32_CLKCTRL_A_CONTROL_EXTESEL_RISING_ONLY_U32 \ 152 (SI32_CLKCTRL_A_CONTROL_EXTESEL_RISING_ONLY_VALUE << SI32_CLKCTRL_A_CONTROL_EXTESEL_SHIFT) 153 154 #define SI32_CLKCTRL_A_CONTROL_OBUSYF_MASK 0x20000000 155 #define SI32_CLKCTRL_A_CONTROL_OBUSYF_SHIFT 29 156 // AHB and APB oscillators are not busy. 157 #define SI32_CLKCTRL_A_CONTROL_OBUSYF_NOT_SET_VALUE 0 158 #define SI32_CLKCTRL_A_CONTROL_OBUSYF_NOT_SET_U32 \ 159 (SI32_CLKCTRL_A_CONTROL_OBUSYF_NOT_SET_VALUE << SI32_CLKCTRL_A_CONTROL_OBUSYF_SHIFT) 160 // AHB and APB oscillators are busy and the AHBSEL, AHBDIV, and APBDIV fields 161 // should not be modified. 162 #define SI32_CLKCTRL_A_CONTROL_OBUSYF_SET_VALUE 1 163 #define SI32_CLKCTRL_A_CONTROL_OBUSYF_SET_U32 \ 164 (SI32_CLKCTRL_A_CONTROL_OBUSYF_SET_VALUE << SI32_CLKCTRL_A_CONTROL_OBUSYF_SHIFT) 165 166 #define SI32_CLKCTRL_A_CONTROL_VIORFCLKEN_MASK 0x40000000 167 #define SI32_CLKCTRL_A_CONTROL_VIORFCLKEN_SHIFT 30 168 // Disable the VIORFCLK input. 169 #define SI32_CLKCTRL_A_CONTROL_VIORFCLKEN_DISABLED_VALUE 0 170 #define SI32_CLKCTRL_A_CONTROL_VIORFCLKEN_DISABLED_U32 \ 171 (SI32_CLKCTRL_A_CONTROL_VIORFCLKEN_DISABLED_VALUE << SI32_CLKCTRL_A_CONTROL_VIORFCLKEN_SHIFT) 172 // Enable the VIORFCLK input. 173 #define SI32_CLKCTRL_A_CONTROL_VIORFCLKEN_ENABLED_VALUE 1 174 #define SI32_CLKCTRL_A_CONTROL_VIORFCLKEN_ENABLED_U32 \ 175 (SI32_CLKCTRL_A_CONTROL_VIORFCLKEN_ENABLED_VALUE << SI32_CLKCTRL_A_CONTROL_VIORFCLKEN_SHIFT) 176 177 #define SI32_CLKCTRL_A_CONTROL_EXTOSCEN_MASK 0x80000000 178 #define SI32_CLKCTRL_A_CONTROL_EXTOSCEN_SHIFT 31 179 // Disable the EXTOSC input. 180 #define SI32_CLKCTRL_A_CONTROL_EXTOSCEN_DISABLED_VALUE 0U 181 #define SI32_CLKCTRL_A_CONTROL_EXTOSCEN_DISABLED_U32 \ 182 (SI32_CLKCTRL_A_CONTROL_EXTOSCEN_DISABLED_VALUE << SI32_CLKCTRL_A_CONTROL_EXTOSCEN_SHIFT) 183 // Enable the EXTOSC input. 184 #define SI32_CLKCTRL_A_CONTROL_EXTOSCEN_ENABLED_VALUE 1U 185 #define SI32_CLKCTRL_A_CONTROL_EXTOSCEN_ENABLED_U32 \ 186 (SI32_CLKCTRL_A_CONTROL_EXTOSCEN_ENABLED_VALUE << SI32_CLKCTRL_A_CONTROL_EXTOSCEN_SHIFT) 187 188 189 190 struct SI32_CLKCTRL_A_AHBCLKG_Struct 191 { 192 union 193 { 194 struct 195 { 196 // RAM Clock Enable 197 volatile uint32_t RAMCEN: 1; 198 // DMA Clock Enable 199 volatile uint32_t DMACEN: 1; 200 // Flash Clock Enable 201 volatile uint32_t FLASHCEN: 1; 202 // DTM0 Clock Enable 203 volatile uint32_t DTM0EN: 1; 204 // DTM1 Clock Enable 205 volatile uint32_t DTM1EN: 1; 206 // DTM2 Clock Enable 207 volatile uint32_t DTM2EN: 1; 208 uint32_t reserved0: 26; 209 }; 210 volatile uint32_t U32; 211 }; 212 }; 213 214 #define SI32_CLKCTRL_A_AHBCLKG_RAMCEN_MASK 0x00000001 215 #define SI32_CLKCTRL_A_AHBCLKG_RAMCEN_SHIFT 0 216 // Disable the AHB clock to the RAM. 217 #define SI32_CLKCTRL_A_AHBCLKG_RAMCEN_DISABLED_VALUE 0 218 #define SI32_CLKCTRL_A_AHBCLKG_RAMCEN_DISABLED_U32 \ 219 (SI32_CLKCTRL_A_AHBCLKG_RAMCEN_DISABLED_VALUE << SI32_CLKCTRL_A_AHBCLKG_RAMCEN_SHIFT) 220 // Enable the AHB clock to the RAM. 221 #define SI32_CLKCTRL_A_AHBCLKG_RAMCEN_ENABLED_VALUE 1 222 #define SI32_CLKCTRL_A_AHBCLKG_RAMCEN_ENABLED_U32 \ 223 (SI32_CLKCTRL_A_AHBCLKG_RAMCEN_ENABLED_VALUE << SI32_CLKCTRL_A_AHBCLKG_RAMCEN_SHIFT) 224 225 #define SI32_CLKCTRL_A_AHBCLKG_DMACEN_MASK 0x00000002 226 #define SI32_CLKCTRL_A_AHBCLKG_DMACEN_SHIFT 1 227 // Disable the AHB clock to the DMA Controller. 228 #define SI32_CLKCTRL_A_AHBCLKG_DMACEN_DISABLED_VALUE 0 229 #define SI32_CLKCTRL_A_AHBCLKG_DMACEN_DISABLED_U32 \ 230 (SI32_CLKCTRL_A_AHBCLKG_DMACEN_DISABLED_VALUE << SI32_CLKCTRL_A_AHBCLKG_DMACEN_SHIFT) 231 // Enable the AHB clock to the DMA Controller. 232 #define SI32_CLKCTRL_A_AHBCLKG_DMACEN_ENABLED_VALUE 1 233 #define SI32_CLKCTRL_A_AHBCLKG_DMACEN_ENABLED_U32 \ 234 (SI32_CLKCTRL_A_AHBCLKG_DMACEN_ENABLED_VALUE << SI32_CLKCTRL_A_AHBCLKG_DMACEN_SHIFT) 235 236 #define SI32_CLKCTRL_A_AHBCLKG_FLASHCEN_MASK 0x00000004 237 #define SI32_CLKCTRL_A_AHBCLKG_FLASHCEN_SHIFT 2 238 // Disable the AHB clock to the Flash. 239 #define SI32_CLKCTRL_A_AHBCLKG_FLASHCEN_DISABLED_VALUE 0 240 #define SI32_CLKCTRL_A_AHBCLKG_FLASHCEN_DISABLED_U32 \ 241 (SI32_CLKCTRL_A_AHBCLKG_FLASHCEN_DISABLED_VALUE << SI32_CLKCTRL_A_AHBCLKG_FLASHCEN_SHIFT) 242 // Enable the AHB clock to the Flash. 243 #define SI32_CLKCTRL_A_AHBCLKG_FLASHCEN_ENABLED_VALUE 1 244 #define SI32_CLKCTRL_A_AHBCLKG_FLASHCEN_ENABLED_U32 \ 245 (SI32_CLKCTRL_A_AHBCLKG_FLASHCEN_ENABLED_VALUE << SI32_CLKCTRL_A_AHBCLKG_FLASHCEN_SHIFT) 246 247 #define SI32_CLKCTRL_A_AHBCLKG_DTM0EN_MASK 0x00000008 248 #define SI32_CLKCTRL_A_AHBCLKG_DTM0EN_SHIFT 3 249 // Disable the AHB clock to Data Transfer Manager 0 (DTM0). 250 #define SI32_CLKCTRL_A_AHBCLKG_DTM0EN_DISABLED_VALUE 0 251 #define SI32_CLKCTRL_A_AHBCLKG_DTM0EN_DISABLED_U32 \ 252 (SI32_CLKCTRL_A_AHBCLKG_DTM0EN_DISABLED_VALUE << SI32_CLKCTRL_A_AHBCLKG_DTM0EN_SHIFT) 253 // Enable the AHB clock to Data Transfer Manager 0 (DTM0). 254 #define SI32_CLKCTRL_A_AHBCLKG_DTM0EN_ENABLED_VALUE 1 255 #define SI32_CLKCTRL_A_AHBCLKG_DTM0EN_ENABLED_U32 \ 256 (SI32_CLKCTRL_A_AHBCLKG_DTM0EN_ENABLED_VALUE << SI32_CLKCTRL_A_AHBCLKG_DTM0EN_SHIFT) 257 258 #define SI32_CLKCTRL_A_AHBCLKG_DTM1EN_MASK 0x00000010 259 #define SI32_CLKCTRL_A_AHBCLKG_DTM1EN_SHIFT 4 260 // Disable the AHB clock to Data Transfer Manager 1 (DTM1). 261 #define SI32_CLKCTRL_A_AHBCLKG_DTM1EN_DISABLED_VALUE 0 262 #define SI32_CLKCTRL_A_AHBCLKG_DTM1EN_DISABLED_U32 \ 263 (SI32_CLKCTRL_A_AHBCLKG_DTM1EN_DISABLED_VALUE << SI32_CLKCTRL_A_AHBCLKG_DTM1EN_SHIFT) 264 // Enable the AHB clock to Data Transfer Manager 1 (DTM1). 265 #define SI32_CLKCTRL_A_AHBCLKG_DTM1EN_ENABLED_VALUE 1 266 #define SI32_CLKCTRL_A_AHBCLKG_DTM1EN_ENABLED_U32 \ 267 (SI32_CLKCTRL_A_AHBCLKG_DTM1EN_ENABLED_VALUE << SI32_CLKCTRL_A_AHBCLKG_DTM1EN_SHIFT) 268 269 #define SI32_CLKCTRL_A_AHBCLKG_DTM2EN_MASK 0x00000020 270 #define SI32_CLKCTRL_A_AHBCLKG_DTM2EN_SHIFT 5 271 // Disable the AHB clock to Data Transfer Manager 2 (DTM2). 272 #define SI32_CLKCTRL_A_AHBCLKG_DTM2EN_DISABLED_VALUE 0 273 #define SI32_CLKCTRL_A_AHBCLKG_DTM2EN_DISABLED_U32 \ 274 (SI32_CLKCTRL_A_AHBCLKG_DTM2EN_DISABLED_VALUE << SI32_CLKCTRL_A_AHBCLKG_DTM2EN_SHIFT) 275 // Enable the AHB clock to Data Transfer Manager 2 (DTM2). 276 #define SI32_CLKCTRL_A_AHBCLKG_DTM2EN_ENABLED_VALUE 1 277 #define SI32_CLKCTRL_A_AHBCLKG_DTM2EN_ENABLED_U32 \ 278 (SI32_CLKCTRL_A_AHBCLKG_DTM2EN_ENABLED_VALUE << SI32_CLKCTRL_A_AHBCLKG_DTM2EN_SHIFT) 279 280 281 282 struct SI32_CLKCTRL_A_APBCLKG0_Struct 283 { 284 union 285 { 286 struct 287 { 288 // Flash Controller Clock Enable 289 volatile uint32_t FLCTRLCEN: 1; 290 // Port Bank Clock Enable 291 volatile uint32_t PB0CEN: 1; 292 // USART0 Clock Enable 293 volatile uint32_t USART0CEN: 1; 294 // UART0 Clock Enable 295 volatile uint32_t UART0CEN: 1; 296 // SPI0 Clock Enable 297 volatile uint32_t SPI0CEN: 1; 298 // SPI1 Clock Enable 299 volatile uint32_t SPI1CEN: 1; 300 // I2C0 Clock Enable 301 volatile uint32_t I2C0CEN: 1; 302 // EPCA0 Clock Enable 303 volatile uint32_t EPCA0CEN: 1; 304 // TIMER0 Clock Enable 305 volatile uint32_t TIMER0CEN: 1; 306 // TIMER1 Clock Enable 307 volatile uint32_t TIMER1CEN: 1; 308 // TIMER2 Clock Enable 309 volatile uint32_t TIMER2CEN: 1; 310 // SARADC0 Clock Enable 311 volatile uint32_t ADC0CEN: 1; 312 // CMP0 Clock Enable 313 volatile uint32_t CMP0CEN: 1; 314 // CMP1 Clock Enable 315 volatile uint32_t CMP1CEN: 1; 316 // AES0 Clock Enable 317 volatile uint32_t AES0CEN: 1; 318 // CRC0 Clock Enable 319 volatile uint32_t CRC0CEN: 1; 320 // IDAC0 Clock Enable 321 volatile uint32_t IDAC0CEN: 1; 322 // LPT0 Clock Enable 323 volatile uint32_t LPT0CEN: 1; 324 // ACCTR0 Enable 325 volatile uint32_t ACCTR0CEN: 1; 326 // DTM0 Clock Enable 327 volatile uint32_t DTM0CEN: 1; 328 // DTM1 Clock Enable 329 volatile uint32_t DTM1CEN: 1; 330 // DTM2 Clock Enable 331 volatile uint32_t DTM2CEN: 1; 332 // LCD0 Clock Enable 333 volatile uint32_t LCD0CEN: 1; 334 // DCDC0 Clock Enable 335 volatile uint32_t DCDC0CEN: 1; 336 // ENCDEC0 Clock Enable 337 volatile uint32_t ENCDEC0CEN: 1; 338 // PLL0 Clock Enable 339 volatile uint32_t PLL0CEN: 1; 340 uint32_t reserved0: 6; 341 }; 342 volatile uint32_t U32; 343 }; 344 }; 345 346 #define SI32_CLKCTRL_A_APBCLKG0_FLCTRLCEN_MASK 0x00000001 347 #define SI32_CLKCTRL_A_APBCLKG0_FLCTRLCEN_SHIFT 0 348 // Disable the APB clock to the Flash Controller Module (FLASHCTRL0). 349 #define SI32_CLKCTRL_A_APBCLKG0_FLCTRLCEN_DISABLED_VALUE 0 350 #define SI32_CLKCTRL_A_APBCLKG0_FLCTRLCEN_DISABLED_U32 \ 351 (SI32_CLKCTRL_A_APBCLKG0_FLCTRLCEN_DISABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_FLCTRLCEN_SHIFT) 352 // Enable the APB clock to the Flash Controller Module (FLASHCTRL0). 353 #define SI32_CLKCTRL_A_APBCLKG0_FLCTRLCEN_ENABLED_VALUE 1 354 #define SI32_CLKCTRL_A_APBCLKG0_FLCTRLCEN_ENABLED_U32 \ 355 (SI32_CLKCTRL_A_APBCLKG0_FLCTRLCEN_ENABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_FLCTRLCEN_SHIFT) 356 357 #define SI32_CLKCTRL_A_APBCLKG0_PB0CEN_MASK 0x00000002 358 #define SI32_CLKCTRL_A_APBCLKG0_PB0CEN_SHIFT 1 359 // Disable the APB clock to the Port Bank Modules. 360 #define SI32_CLKCTRL_A_APBCLKG0_PB0CEN_DISABLED_VALUE 0 361 #define SI32_CLKCTRL_A_APBCLKG0_PB0CEN_DISABLED_U32 \ 362 (SI32_CLKCTRL_A_APBCLKG0_PB0CEN_DISABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_PB0CEN_SHIFT) 363 // Enable the APB clock to the Port Bank Modules. 364 #define SI32_CLKCTRL_A_APBCLKG0_PB0CEN_ENABLED_VALUE 1 365 #define SI32_CLKCTRL_A_APBCLKG0_PB0CEN_ENABLED_U32 \ 366 (SI32_CLKCTRL_A_APBCLKG0_PB0CEN_ENABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_PB0CEN_SHIFT) 367 368 #define SI32_CLKCTRL_A_APBCLKG0_USART0CEN_MASK 0x00000004 369 #define SI32_CLKCTRL_A_APBCLKG0_USART0CEN_SHIFT 2 370 // Disable the APB clock to the USART0 Module. 371 #define SI32_CLKCTRL_A_APBCLKG0_USART0CEN_DISABLED_VALUE 0 372 #define SI32_CLKCTRL_A_APBCLKG0_USART0CEN_DISABLED_U32 \ 373 (SI32_CLKCTRL_A_APBCLKG0_USART0CEN_DISABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_USART0CEN_SHIFT) 374 // Enable the APB clock to the USART0 Module. 375 #define SI32_CLKCTRL_A_APBCLKG0_USART0CEN_ENABLED_VALUE 1 376 #define SI32_CLKCTRL_A_APBCLKG0_USART0CEN_ENABLED_U32 \ 377 (SI32_CLKCTRL_A_APBCLKG0_USART0CEN_ENABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_USART0CEN_SHIFT) 378 379 #define SI32_CLKCTRL_A_APBCLKG0_UART0CEN_MASK 0x00000008 380 #define SI32_CLKCTRL_A_APBCLKG0_UART0CEN_SHIFT 3 381 // Disable the APB clock to the UART0 Module. 382 #define SI32_CLKCTRL_A_APBCLKG0_UART0CEN_DISABLED_VALUE 0 383 #define SI32_CLKCTRL_A_APBCLKG0_UART0CEN_DISABLED_U32 \ 384 (SI32_CLKCTRL_A_APBCLKG0_UART0CEN_DISABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_UART0CEN_SHIFT) 385 // Enable the APB clock to the UART0 Module. 386 #define SI32_CLKCTRL_A_APBCLKG0_UART0CEN_ENABLED_VALUE 1 387 #define SI32_CLKCTRL_A_APBCLKG0_UART0CEN_ENABLED_U32 \ 388 (SI32_CLKCTRL_A_APBCLKG0_UART0CEN_ENABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_UART0CEN_SHIFT) 389 390 #define SI32_CLKCTRL_A_APBCLKG0_SPI0CEN_MASK 0x00000010 391 #define SI32_CLKCTRL_A_APBCLKG0_SPI0CEN_SHIFT 4 392 // Disable the APB clock to the SPI0 Module. 393 #define SI32_CLKCTRL_A_APBCLKG0_SPI0CEN_DISABLED_VALUE 0 394 #define SI32_CLKCTRL_A_APBCLKG0_SPI0CEN_DISABLED_U32 \ 395 (SI32_CLKCTRL_A_APBCLKG0_SPI0CEN_DISABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_SPI0CEN_SHIFT) 396 // Enable the APB clock to the SPI0 Module. 397 #define SI32_CLKCTRL_A_APBCLKG0_SPI0CEN_ENABLED_VALUE 1 398 #define SI32_CLKCTRL_A_APBCLKG0_SPI0CEN_ENABLED_U32 \ 399 (SI32_CLKCTRL_A_APBCLKG0_SPI0CEN_ENABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_SPI0CEN_SHIFT) 400 401 #define SI32_CLKCTRL_A_APBCLKG0_SPI1CEN_MASK 0x00000020 402 #define SI32_CLKCTRL_A_APBCLKG0_SPI1CEN_SHIFT 5 403 // Disable the APB clock to the SPI1 Module. 404 #define SI32_CLKCTRL_A_APBCLKG0_SPI1CEN_DISABLED_VALUE 0 405 #define SI32_CLKCTRL_A_APBCLKG0_SPI1CEN_DISABLED_U32 \ 406 (SI32_CLKCTRL_A_APBCLKG0_SPI1CEN_DISABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_SPI1CEN_SHIFT) 407 // Enable the APB clock to the SPI1 Module. 408 #define SI32_CLKCTRL_A_APBCLKG0_SPI1CEN_ENABLED_VALUE 1 409 #define SI32_CLKCTRL_A_APBCLKG0_SPI1CEN_ENABLED_U32 \ 410 (SI32_CLKCTRL_A_APBCLKG0_SPI1CEN_ENABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_SPI1CEN_SHIFT) 411 412 #define SI32_CLKCTRL_A_APBCLKG0_I2C0CEN_MASK 0x00000040 413 #define SI32_CLKCTRL_A_APBCLKG0_I2C0CEN_SHIFT 6 414 // Disable the APB clock to the I2C0 Module. 415 #define SI32_CLKCTRL_A_APBCLKG0_I2C0CEN_DISABLED_VALUE 0 416 #define SI32_CLKCTRL_A_APBCLKG0_I2C0CEN_DISABLED_U32 \ 417 (SI32_CLKCTRL_A_APBCLKG0_I2C0CEN_DISABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_I2C0CEN_SHIFT) 418 // Enable the APB clock to the I2C0 Module. 419 #define SI32_CLKCTRL_A_APBCLKG0_I2C0CEN_ENABLED_VALUE 1 420 #define SI32_CLKCTRL_A_APBCLKG0_I2C0CEN_ENABLED_U32 \ 421 (SI32_CLKCTRL_A_APBCLKG0_I2C0CEN_ENABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_I2C0CEN_SHIFT) 422 423 #define SI32_CLKCTRL_A_APBCLKG0_EPCA0CEN_MASK 0x00000080 424 #define SI32_CLKCTRL_A_APBCLKG0_EPCA0CEN_SHIFT 7 425 // Disable the APB clock to the EPCA0 Module. 426 #define SI32_CLKCTRL_A_APBCLKG0_EPCA0CEN_DISABLED_VALUE 0 427 #define SI32_CLKCTRL_A_APBCLKG0_EPCA0CEN_DISABLED_U32 \ 428 (SI32_CLKCTRL_A_APBCLKG0_EPCA0CEN_DISABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_EPCA0CEN_SHIFT) 429 // Enable the APB clock to the EPCA0 Module. 430 #define SI32_CLKCTRL_A_APBCLKG0_EPCA0CEN_ENABLED_VALUE 1 431 #define SI32_CLKCTRL_A_APBCLKG0_EPCA0CEN_ENABLED_U32 \ 432 (SI32_CLKCTRL_A_APBCLKG0_EPCA0CEN_ENABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_EPCA0CEN_SHIFT) 433 434 #define SI32_CLKCTRL_A_APBCLKG0_TIMER0CEN_MASK 0x00000100 435 #define SI32_CLKCTRL_A_APBCLKG0_TIMER0CEN_SHIFT 8 436 // Disable the APB clock to the TIMER0 Module. 437 #define SI32_CLKCTRL_A_APBCLKG0_TIMER0CEN_DISABLED_VALUE 0 438 #define SI32_CLKCTRL_A_APBCLKG0_TIMER0CEN_DISABLED_U32 \ 439 (SI32_CLKCTRL_A_APBCLKG0_TIMER0CEN_DISABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_TIMER0CEN_SHIFT) 440 // Enable the APB clock to the TIMER0 Module. 441 #define SI32_CLKCTRL_A_APBCLKG0_TIMER0CEN_ENABLED_VALUE 1 442 #define SI32_CLKCTRL_A_APBCLKG0_TIMER0CEN_ENABLED_U32 \ 443 (SI32_CLKCTRL_A_APBCLKG0_TIMER0CEN_ENABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_TIMER0CEN_SHIFT) 444 445 #define SI32_CLKCTRL_A_APBCLKG0_TIMER1CEN_MASK 0x00000200 446 #define SI32_CLKCTRL_A_APBCLKG0_TIMER1CEN_SHIFT 9 447 // Disable the APB clock to the TIMER1 Module. 448 #define SI32_CLKCTRL_A_APBCLKG0_TIMER1CEN_DISABLED_VALUE 0 449 #define SI32_CLKCTRL_A_APBCLKG0_TIMER1CEN_DISABLED_U32 \ 450 (SI32_CLKCTRL_A_APBCLKG0_TIMER1CEN_DISABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_TIMER1CEN_SHIFT) 451 // Enable the APB clock to the TIMER1 Module. 452 #define SI32_CLKCTRL_A_APBCLKG0_TIMER1CEN_ENABLED_VALUE 1 453 #define SI32_CLKCTRL_A_APBCLKG0_TIMER1CEN_ENABLED_U32 \ 454 (SI32_CLKCTRL_A_APBCLKG0_TIMER1CEN_ENABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_TIMER1CEN_SHIFT) 455 456 #define SI32_CLKCTRL_A_APBCLKG0_TIMER2CEN_MASK 0x00000400 457 #define SI32_CLKCTRL_A_APBCLKG0_TIMER2CEN_SHIFT 10 458 // Disable the APB clock to the TIMER2 Module. 459 #define SI32_CLKCTRL_A_APBCLKG0_TIMER2CEN_DISABLED_VALUE 0 460 #define SI32_CLKCTRL_A_APBCLKG0_TIMER2CEN_DISABLED_U32 \ 461 (SI32_CLKCTRL_A_APBCLKG0_TIMER2CEN_DISABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_TIMER2CEN_SHIFT) 462 // Enable the APB clock to the TIMER2 Module. 463 #define SI32_CLKCTRL_A_APBCLKG0_TIMER2CEN_ENABLED_VALUE 1 464 #define SI32_CLKCTRL_A_APBCLKG0_TIMER2CEN_ENABLED_U32 \ 465 (SI32_CLKCTRL_A_APBCLKG0_TIMER2CEN_ENABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_TIMER2CEN_SHIFT) 466 467 #define SI32_CLKCTRL_A_APBCLKG0_ADC0CEN_MASK 0x00000800 468 #define SI32_CLKCTRL_A_APBCLKG0_ADC0CEN_SHIFT 11 469 // Disable the APB clock to the SARADC0 Module. 470 #define SI32_CLKCTRL_A_APBCLKG0_ADC0CEN_DISABLED_VALUE 0 471 #define SI32_CLKCTRL_A_APBCLKG0_ADC0CEN_DISABLED_U32 \ 472 (SI32_CLKCTRL_A_APBCLKG0_ADC0CEN_DISABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_ADC0CEN_SHIFT) 473 // Enable the APB clock to the SARADC0 Module. 474 #define SI32_CLKCTRL_A_APBCLKG0_ADC0CEN_ENABLED_VALUE 1 475 #define SI32_CLKCTRL_A_APBCLKG0_ADC0CEN_ENABLED_U32 \ 476 (SI32_CLKCTRL_A_APBCLKG0_ADC0CEN_ENABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_ADC0CEN_SHIFT) 477 478 #define SI32_CLKCTRL_A_APBCLKG0_CMP0CEN_MASK 0x00001000 479 #define SI32_CLKCTRL_A_APBCLKG0_CMP0CEN_SHIFT 12 480 // Disable the APB clock to the Comparator 0 Module. 481 #define SI32_CLKCTRL_A_APBCLKG0_CMP0CEN_DISABLED_VALUE 0 482 #define SI32_CLKCTRL_A_APBCLKG0_CMP0CEN_DISABLED_U32 \ 483 (SI32_CLKCTRL_A_APBCLKG0_CMP0CEN_DISABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_CMP0CEN_SHIFT) 484 // Enable the APB clock to the Comparator 0 Module. 485 #define SI32_CLKCTRL_A_APBCLKG0_CMP0CEN_ENABLED_VALUE 1 486 #define SI32_CLKCTRL_A_APBCLKG0_CMP0CEN_ENABLED_U32 \ 487 (SI32_CLKCTRL_A_APBCLKG0_CMP0CEN_ENABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_CMP0CEN_SHIFT) 488 489 #define SI32_CLKCTRL_A_APBCLKG0_CMP1CEN_MASK 0x00002000 490 #define SI32_CLKCTRL_A_APBCLKG0_CMP1CEN_SHIFT 13 491 // Disable the APB clock to the Comparator 1 Module. 492 #define SI32_CLKCTRL_A_APBCLKG0_CMP1CEN_DISABLED_VALUE 0 493 #define SI32_CLKCTRL_A_APBCLKG0_CMP1CEN_DISABLED_U32 \ 494 (SI32_CLKCTRL_A_APBCLKG0_CMP1CEN_DISABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_CMP1CEN_SHIFT) 495 // Enable the APB clock to the Comparator 1 Module. 496 #define SI32_CLKCTRL_A_APBCLKG0_CMP1CEN_ENABLED_VALUE 1 497 #define SI32_CLKCTRL_A_APBCLKG0_CMP1CEN_ENABLED_U32 \ 498 (SI32_CLKCTRL_A_APBCLKG0_CMP1CEN_ENABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_CMP1CEN_SHIFT) 499 500 #define SI32_CLKCTRL_A_APBCLKG0_AES0CEN_MASK 0x00004000 501 #define SI32_CLKCTRL_A_APBCLKG0_AES0CEN_SHIFT 14 502 // Disable the APB clock to the AES0 Module. 503 #define SI32_CLKCTRL_A_APBCLKG0_AES0CEN_DISABLED_VALUE 0 504 #define SI32_CLKCTRL_A_APBCLKG0_AES0CEN_DISABLED_U32 \ 505 (SI32_CLKCTRL_A_APBCLKG0_AES0CEN_DISABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_AES0CEN_SHIFT) 506 // Enable the APB clock to the AES0 Module. 507 #define SI32_CLKCTRL_A_APBCLKG0_AES0CEN_ENABLED_VALUE 1 508 #define SI32_CLKCTRL_A_APBCLKG0_AES0CEN_ENABLED_U32 \ 509 (SI32_CLKCTRL_A_APBCLKG0_AES0CEN_ENABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_AES0CEN_SHIFT) 510 511 #define SI32_CLKCTRL_A_APBCLKG0_CRC0CEN_MASK 0x00008000 512 #define SI32_CLKCTRL_A_APBCLKG0_CRC0CEN_SHIFT 15 513 // Disable the APB clock to the CRC0 Module. 514 #define SI32_CLKCTRL_A_APBCLKG0_CRC0CEN_DISABLED_VALUE 0 515 #define SI32_CLKCTRL_A_APBCLKG0_CRC0CEN_DISABLED_U32 \ 516 (SI32_CLKCTRL_A_APBCLKG0_CRC0CEN_DISABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_CRC0CEN_SHIFT) 517 // Enable the APB clock to the CRC0 Module. 518 #define SI32_CLKCTRL_A_APBCLKG0_CRC0CEN_ENABLED_VALUE 1 519 #define SI32_CLKCTRL_A_APBCLKG0_CRC0CEN_ENABLED_U32 \ 520 (SI32_CLKCTRL_A_APBCLKG0_CRC0CEN_ENABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_CRC0CEN_SHIFT) 521 522 #define SI32_CLKCTRL_A_APBCLKG0_IDAC0CEN_MASK 0x00010000 523 #define SI32_CLKCTRL_A_APBCLKG0_IDAC0CEN_SHIFT 16 524 // Disable the APB clock to the IDAC0 Module. 525 #define SI32_CLKCTRL_A_APBCLKG0_IDAC0CEN_DISABLED_VALUE 0 526 #define SI32_CLKCTRL_A_APBCLKG0_IDAC0CEN_DISABLED_U32 \ 527 (SI32_CLKCTRL_A_APBCLKG0_IDAC0CEN_DISABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_IDAC0CEN_SHIFT) 528 // Enable the APB clock to the IDAC0 Module. 529 #define SI32_CLKCTRL_A_APBCLKG0_IDAC0CEN_ENABLED_VALUE 1 530 #define SI32_CLKCTRL_A_APBCLKG0_IDAC0CEN_ENABLED_U32 \ 531 (SI32_CLKCTRL_A_APBCLKG0_IDAC0CEN_ENABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_IDAC0CEN_SHIFT) 532 533 #define SI32_CLKCTRL_A_APBCLKG0_LPT0CEN_MASK 0x00020000 534 #define SI32_CLKCTRL_A_APBCLKG0_LPT0CEN_SHIFT 17 535 // Disable the APB clock to the LPTIMER0 Module. 536 #define SI32_CLKCTRL_A_APBCLKG0_LPT0CEN_DISABLED_VALUE 0 537 #define SI32_CLKCTRL_A_APBCLKG0_LPT0CEN_DISABLED_U32 \ 538 (SI32_CLKCTRL_A_APBCLKG0_LPT0CEN_DISABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_LPT0CEN_SHIFT) 539 // Enable the APB clock to the LPTIMER0 Module. 540 #define SI32_CLKCTRL_A_APBCLKG0_LPT0CEN_ENABLED_VALUE 1 541 #define SI32_CLKCTRL_A_APBCLKG0_LPT0CEN_ENABLED_U32 \ 542 (SI32_CLKCTRL_A_APBCLKG0_LPT0CEN_ENABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_LPT0CEN_SHIFT) 543 544 #define SI32_CLKCTRL_A_APBCLKG0_ACCTR0CEN_MASK 0x00040000 545 #define SI32_CLKCTRL_A_APBCLKG0_ACCTR0CEN_SHIFT 18 546 // Disable the APB clock to the ACCTR0 Module. 547 #define SI32_CLKCTRL_A_APBCLKG0_ACCTR0CEN_DISABLED_VALUE 0 548 #define SI32_CLKCTRL_A_APBCLKG0_ACCTR0CEN_DISABLED_U32 \ 549 (SI32_CLKCTRL_A_APBCLKG0_ACCTR0CEN_DISABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_ACCTR0CEN_SHIFT) 550 // Enable the APB clock to the ACCTR0 Module. 551 #define SI32_CLKCTRL_A_APBCLKG0_ACCTR0CEN_ENABLED_VALUE 1 552 #define SI32_CLKCTRL_A_APBCLKG0_ACCTR0CEN_ENABLED_U32 \ 553 (SI32_CLKCTRL_A_APBCLKG0_ACCTR0CEN_ENABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_ACCTR0CEN_SHIFT) 554 555 #define SI32_CLKCTRL_A_APBCLKG0_DTM0CEN_MASK 0x00080000 556 #define SI32_CLKCTRL_A_APBCLKG0_DTM0CEN_SHIFT 19 557 // Disable the APB clock to the DTM0 Register interface. 558 #define SI32_CLKCTRL_A_APBCLKG0_DTM0CEN_DISABLED_VALUE 0 559 #define SI32_CLKCTRL_A_APBCLKG0_DTM0CEN_DISABLED_U32 \ 560 (SI32_CLKCTRL_A_APBCLKG0_DTM0CEN_DISABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_DTM0CEN_SHIFT) 561 // Enable the APB clock to the DTM0 Register interface. 562 #define SI32_CLKCTRL_A_APBCLKG0_DTM0CEN_ENABLED_VALUE 1 563 #define SI32_CLKCTRL_A_APBCLKG0_DTM0CEN_ENABLED_U32 \ 564 (SI32_CLKCTRL_A_APBCLKG0_DTM0CEN_ENABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_DTM0CEN_SHIFT) 565 566 #define SI32_CLKCTRL_A_APBCLKG0_DTM1CEN_MASK 0x00100000 567 #define SI32_CLKCTRL_A_APBCLKG0_DTM1CEN_SHIFT 20 568 // Disable the APB clock to the DTM1 Register interface. 569 #define SI32_CLKCTRL_A_APBCLKG0_DTM1CEN_DISABLED_VALUE 0 570 #define SI32_CLKCTRL_A_APBCLKG0_DTM1CEN_DISABLED_U32 \ 571 (SI32_CLKCTRL_A_APBCLKG0_DTM1CEN_DISABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_DTM1CEN_SHIFT) 572 // Enable the APB clock to the DTM1 Register interface. 573 #define SI32_CLKCTRL_A_APBCLKG0_DTM1CEN_ENABLED_VALUE 1 574 #define SI32_CLKCTRL_A_APBCLKG0_DTM1CEN_ENABLED_U32 \ 575 (SI32_CLKCTRL_A_APBCLKG0_DTM1CEN_ENABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_DTM1CEN_SHIFT) 576 577 #define SI32_CLKCTRL_A_APBCLKG0_DTM2CEN_MASK 0x00200000 578 #define SI32_CLKCTRL_A_APBCLKG0_DTM2CEN_SHIFT 21 579 // Disable the APB clock to the DTM2 Register interface. 580 #define SI32_CLKCTRL_A_APBCLKG0_DTM2CEN_DISABLED_VALUE 0 581 #define SI32_CLKCTRL_A_APBCLKG0_DTM2CEN_DISABLED_U32 \ 582 (SI32_CLKCTRL_A_APBCLKG0_DTM2CEN_DISABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_DTM2CEN_SHIFT) 583 // Enable the APB clock to the DTM2 Register interface. 584 #define SI32_CLKCTRL_A_APBCLKG0_DTM2CEN_ENABLED_VALUE 1 585 #define SI32_CLKCTRL_A_APBCLKG0_DTM2CEN_ENABLED_U32 \ 586 (SI32_CLKCTRL_A_APBCLKG0_DTM2CEN_ENABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_DTM2CEN_SHIFT) 587 588 #define SI32_CLKCTRL_A_APBCLKG0_LCD0CEN_MASK 0x00400000 589 #define SI32_CLKCTRL_A_APBCLKG0_LCD0CEN_SHIFT 22 590 // Disable the APB clock to the LCD0 Module. 591 #define SI32_CLKCTRL_A_APBCLKG0_LCD0CEN_DISABLED_VALUE 0 592 #define SI32_CLKCTRL_A_APBCLKG0_LCD0CEN_DISABLED_U32 \ 593 (SI32_CLKCTRL_A_APBCLKG0_LCD0CEN_DISABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_LCD0CEN_SHIFT) 594 // Enable the APB clock to the LCD0 Module. 595 #define SI32_CLKCTRL_A_APBCLKG0_LCD0CEN_ENABLED_VALUE 1 596 #define SI32_CLKCTRL_A_APBCLKG0_LCD0CEN_ENABLED_U32 \ 597 (SI32_CLKCTRL_A_APBCLKG0_LCD0CEN_ENABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_LCD0CEN_SHIFT) 598 599 #define SI32_CLKCTRL_A_APBCLKG0_DCDC0CEN_MASK 0x00800000 600 #define SI32_CLKCTRL_A_APBCLKG0_DCDC0CEN_SHIFT 23 601 // Disable the APB clock to the DCDC0 Module. 602 #define SI32_CLKCTRL_A_APBCLKG0_DCDC0CEN_DISABLED_VALUE 0 603 #define SI32_CLKCTRL_A_APBCLKG0_DCDC0CEN_DISABLED_U32 \ 604 (SI32_CLKCTRL_A_APBCLKG0_DCDC0CEN_DISABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_DCDC0CEN_SHIFT) 605 // Enable the APB clock to the DCDC0 Module. 606 #define SI32_CLKCTRL_A_APBCLKG0_DCDC0CEN_ENABLED_VALUE 1 607 #define SI32_CLKCTRL_A_APBCLKG0_DCDC0CEN_ENABLED_U32 \ 608 (SI32_CLKCTRL_A_APBCLKG0_DCDC0CEN_ENABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_DCDC0CEN_SHIFT) 609 610 #define SI32_CLKCTRL_A_APBCLKG0_ENCDEC0CEN_MASK 0x01000000 611 #define SI32_CLKCTRL_A_APBCLKG0_ENCDEC0CEN_SHIFT 24 612 // Disable the APB clock to the ENCDEC0 Module. 613 #define SI32_CLKCTRL_A_APBCLKG0_ENCDEC0CEN_DISABLED_VALUE 0 614 #define SI32_CLKCTRL_A_APBCLKG0_ENCDEC0CEN_DISABLED_U32 \ 615 (SI32_CLKCTRL_A_APBCLKG0_ENCDEC0CEN_DISABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_ENCDEC0CEN_SHIFT) 616 // Enable the APB clock to the ENCDEC0 Module. 617 #define SI32_CLKCTRL_A_APBCLKG0_ENCDEC0CEN_ENABLED_VALUE 1 618 #define SI32_CLKCTRL_A_APBCLKG0_ENCDEC0CEN_ENABLED_U32 \ 619 (SI32_CLKCTRL_A_APBCLKG0_ENCDEC0CEN_ENABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_ENCDEC0CEN_SHIFT) 620 621 #define SI32_CLKCTRL_A_APBCLKG0_PLL0CEN_MASK 0x02000000 622 #define SI32_CLKCTRL_A_APBCLKG0_PLL0CEN_SHIFT 25 623 // Disable the APB clock to the PLL0 registers. 624 #define SI32_CLKCTRL_A_APBCLKG0_PLL0CEN_DISABLED_VALUE 0 625 #define SI32_CLKCTRL_A_APBCLKG0_PLL0CEN_DISABLED_U32 \ 626 (SI32_CLKCTRL_A_APBCLKG0_PLL0CEN_DISABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_PLL0CEN_SHIFT) 627 // Enable the APB clock to the PLL0 registers. 628 #define SI32_CLKCTRL_A_APBCLKG0_PLL0CEN_ENABLED_VALUE 1 629 #define SI32_CLKCTRL_A_APBCLKG0_PLL0CEN_ENABLED_U32 \ 630 (SI32_CLKCTRL_A_APBCLKG0_PLL0CEN_ENABLED_VALUE << SI32_CLKCTRL_A_APBCLKG0_PLL0CEN_SHIFT) 631 632 633 634 struct SI32_CLKCTRL_A_APBCLKG1_Struct 635 { 636 union 637 { 638 struct 639 { 640 // Miscellaneous 0 Clock Enable 641 volatile uint32_t MISC0CEN: 1; 642 // Miscellaneous 1 Clock Enable 643 volatile uint32_t MISC1CEN: 1; 644 uint32_t reserved0: 30; 645 }; 646 volatile uint32_t U32; 647 }; 648 }; 649 650 #define SI32_CLKCTRL_A_APBCLKG1_MISC0CEN_MASK 0x00000001 651 #define SI32_CLKCTRL_A_APBCLKG1_MISC0CEN_SHIFT 0 652 // Disable the APB clock to the VMON0, LDO0, EXTOSC0, LPOSC0, RTC0 and RSTSRC 653 // modules. 654 #define SI32_CLKCTRL_A_APBCLKG1_MISC0CEN_DISABLED_VALUE 0 655 #define SI32_CLKCTRL_A_APBCLKG1_MISC0CEN_DISABLED_U32 \ 656 (SI32_CLKCTRL_A_APBCLKG1_MISC0CEN_DISABLED_VALUE << SI32_CLKCTRL_A_APBCLKG1_MISC0CEN_SHIFT) 657 // Enable the APB clock to the VMON0, LDO0, EXTOSC0, LPOSC0, RTC0 and RSTSRC 658 // modules. 659 #define SI32_CLKCTRL_A_APBCLKG1_MISC0CEN_ENABLED_VALUE 1 660 #define SI32_CLKCTRL_A_APBCLKG1_MISC0CEN_ENABLED_U32 \ 661 (SI32_CLKCTRL_A_APBCLKG1_MISC0CEN_ENABLED_VALUE << SI32_CLKCTRL_A_APBCLKG1_MISC0CEN_SHIFT) 662 663 #define SI32_CLKCTRL_A_APBCLKG1_MISC1CEN_MASK 0x00000002 664 #define SI32_CLKCTRL_A_APBCLKG1_MISC1CEN_SHIFT 1 665 // Disable the APB clock to the Watchdog Timer (WDTIMER0) and DMA Crossbar 666 // (DMAXBAR0) modules. 667 #define SI32_CLKCTRL_A_APBCLKG1_MISC1CEN_DISABLED_VALUE 0 668 #define SI32_CLKCTRL_A_APBCLKG1_MISC1CEN_DISABLED_U32 \ 669 (SI32_CLKCTRL_A_APBCLKG1_MISC1CEN_DISABLED_VALUE << SI32_CLKCTRL_A_APBCLKG1_MISC1CEN_SHIFT) 670 // Enable the APB clock to the Watchdog Timer (WDTIMER0) and DMA Crossbar 671 // (DMAXBAR0) modules. 672 #define SI32_CLKCTRL_A_APBCLKG1_MISC1CEN_ENABLED_VALUE 1 673 #define SI32_CLKCTRL_A_APBCLKG1_MISC1CEN_ENABLED_U32 \ 674 (SI32_CLKCTRL_A_APBCLKG1_MISC1CEN_ENABLED_VALUE << SI32_CLKCTRL_A_APBCLKG1_MISC1CEN_SHIFT) 675 676 677 678 struct SI32_CLKCTRL_A_PM3CN_Struct 679 { 680 union 681 { 682 struct 683 { 684 // Power Mode 3 Fast-Wake Clock Source 685 volatile uint32_t PM3CSEL: 3; 686 uint32_t reserved0: 13; 687 // Power Mode 3 Fast-Wake Clock Enable 688 volatile uint32_t PM3CEN: 1; 689 uint32_t reserved1: 15; 690 }; 691 volatile uint32_t U32; 692 }; 693 }; 694 695 #define SI32_CLKCTRL_A_PM3CN_PM3CSEL_MASK 0x00000007 696 #define SI32_CLKCTRL_A_PM3CN_PM3CSEL_SHIFT 0 697 // Power Mode 3 clock source is the Low-Power Oscillator. 698 #define SI32_CLKCTRL_A_PM3CN_PM3CSEL_LPOSC0_VALUE 0 699 #define SI32_CLKCTRL_A_PM3CN_PM3CSEL_LPOSC0_U32 \ 700 (SI32_CLKCTRL_A_PM3CN_PM3CSEL_LPOSC0_VALUE << SI32_CLKCTRL_A_PM3CN_PM3CSEL_SHIFT) 701 // Power Mode 3 clock source is the Low-Frequency Oscillator. 702 #define SI32_CLKCTRL_A_PM3CN_PM3CSEL_LFOSC0_VALUE 1 703 #define SI32_CLKCTRL_A_PM3CN_PM3CSEL_LFOSC0_U32 \ 704 (SI32_CLKCTRL_A_PM3CN_PM3CSEL_LFOSC0_VALUE << SI32_CLKCTRL_A_PM3CN_PM3CSEL_SHIFT) 705 // Power Mode 3 clock source is the RTC0TCLK signal. 706 #define SI32_CLKCTRL_A_PM3CN_PM3CSEL_RTC0TCLK_VALUE 2 707 #define SI32_CLKCTRL_A_PM3CN_PM3CSEL_RTC0TCLK_U32 \ 708 (SI32_CLKCTRL_A_PM3CN_PM3CSEL_RTC0TCLK_VALUE << SI32_CLKCTRL_A_PM3CN_PM3CSEL_SHIFT) 709 // Power Mode 3 clock source is the External Oscillator. 710 #define SI32_CLKCTRL_A_PM3CN_PM3CSEL_EXTOSC0_VALUE 3 711 #define SI32_CLKCTRL_A_PM3CN_PM3CSEL_EXTOSC0_U32 \ 712 (SI32_CLKCTRL_A_PM3CN_PM3CSEL_EXTOSC0_VALUE << SI32_CLKCTRL_A_PM3CN_PM3CSEL_SHIFT) 713 // Power Mode 3 clock source is the VIORFCLK input pin. 714 #define SI32_CLKCTRL_A_PM3CN_PM3CSEL_VIORFCLK_VALUE 4 715 #define SI32_CLKCTRL_A_PM3CN_PM3CSEL_VIORFCLK_U32 \ 716 (SI32_CLKCTRL_A_PM3CN_PM3CSEL_VIORFCLK_VALUE << SI32_CLKCTRL_A_PM3CN_PM3CSEL_SHIFT) 717 // Power Mode 3 clock source is the PLL. 718 #define SI32_CLKCTRL_A_PM3CN_PM3CSEL_PLL0OSC_VALUE 5 719 #define SI32_CLKCTRL_A_PM3CN_PM3CSEL_PLL0OSC_U32 \ 720 (SI32_CLKCTRL_A_PM3CN_PM3CSEL_PLL0OSC_VALUE << SI32_CLKCTRL_A_PM3CN_PM3CSEL_SHIFT) 721 // Power Mode 3 clock source is a divided version of the Low-Power Oscillator. 722 #define SI32_CLKCTRL_A_PM3CN_PM3CSEL_LPOSC0_DIV_VALUE 6 723 #define SI32_CLKCTRL_A_PM3CN_PM3CSEL_LPOSC0_DIV_U32 \ 724 (SI32_CLKCTRL_A_PM3CN_PM3CSEL_LPOSC0_DIV_VALUE << SI32_CLKCTRL_A_PM3CN_PM3CSEL_SHIFT) 725 726 #define SI32_CLKCTRL_A_PM3CN_PM3CEN_MASK 0x00010000 727 #define SI32_CLKCTRL_A_PM3CN_PM3CEN_SHIFT 16 728 // Disable the core clock when in Power Mode 3. 729 #define SI32_CLKCTRL_A_PM3CN_PM3CEN_DISABLED_VALUE 0 730 #define SI32_CLKCTRL_A_PM3CN_PM3CEN_DISABLED_U32 \ 731 (SI32_CLKCTRL_A_PM3CN_PM3CEN_DISABLED_VALUE << SI32_CLKCTRL_A_PM3CN_PM3CEN_SHIFT) 732 // The core clock is enabled and runs off the clock selected by PM3CSEL in Power 733 // Mode 3. 734 #define SI32_CLKCTRL_A_PM3CN_PM3CEN_ENABLED_VALUE 1 735 #define SI32_CLKCTRL_A_PM3CN_PM3CEN_ENABLED_U32 \ 736 (SI32_CLKCTRL_A_PM3CN_PM3CEN_ENABLED_VALUE << SI32_CLKCTRL_A_PM3CN_PM3CEN_SHIFT) 737 738 739 740 struct SI32_CLKCTRL_A_CONFIG_Struct 741 { 742 union 743 { 744 struct 745 { 746 // Power Mode Select 747 volatile uint32_t PMSEL: 1; 748 uint32_t reserved0: 31; 749 }; 750 volatile uint32_t U32; 751 }; 752 }; 753 754 #define SI32_CLKCTRL_A_CONFIG_PMSEL_MASK 0x00000001 755 #define SI32_CLKCTRL_A_CONFIG_PMSEL_SHIFT 0 756 // Power Mode < PM8. 757 #define SI32_CLKCTRL_A_CONFIG_PMSEL_PM8_DIS_VALUE 0 758 #define SI32_CLKCTRL_A_CONFIG_PMSEL_PM8_DIS_U32 \ 759 (SI32_CLKCTRL_A_CONFIG_PMSEL_PM8_DIS_VALUE << SI32_CLKCTRL_A_CONFIG_PMSEL_SHIFT) 760 // Power Mode = PM8. 761 #define SI32_CLKCTRL_A_CONFIG_PMSEL_PM8_EN_VALUE 1 762 #define SI32_CLKCTRL_A_CONFIG_PMSEL_PM8_EN_U32 \ 763 (SI32_CLKCTRL_A_CONFIG_PMSEL_PM8_EN_VALUE << SI32_CLKCTRL_A_CONFIG_PMSEL_SHIFT) 764 765 766 767 typedef struct SI32_CLKCTRL_A_Struct 768 { 769 struct SI32_CLKCTRL_A_CONTROL_Struct CONTROL ; // Base Address + 0x0 770 uint32_t reserved0; 771 uint32_t reserved1; 772 uint32_t reserved2; 773 struct SI32_CLKCTRL_A_AHBCLKG_Struct AHBCLKG ; // Base Address + 0x10 774 volatile uint32_t AHBCLKG_SET; 775 volatile uint32_t AHBCLKG_CLR; 776 uint32_t reserved3; 777 struct SI32_CLKCTRL_A_APBCLKG0_Struct APBCLKG0 ; // Base Address + 0x20 778 volatile uint32_t APBCLKG0_SET; 779 volatile uint32_t APBCLKG0_CLR; 780 uint32_t reserved4; 781 struct SI32_CLKCTRL_A_APBCLKG1_Struct APBCLKG1 ; // Base Address + 0x30 782 volatile uint32_t APBCLKG1_SET; 783 volatile uint32_t APBCLKG1_CLR; 784 uint32_t reserved5; 785 struct SI32_CLKCTRL_A_PM3CN_Struct PM3CN ; // Base Address + 0x40 786 uint32_t reserved6; 787 uint32_t reserved7; 788 uint32_t reserved8; 789 uint32_t reserved9[4]; 790 struct SI32_CLKCTRL_A_CONFIG_Struct CONFIG ; // Base Address + 0x60 791 volatile uint32_t CONFIG_SET; 792 volatile uint32_t CONFIG_CLR; 793 uint32_t reserved10; 794 uint32_t reserved11[4]; 795 } SI32_CLKCTRL_A_Type; 796 797 #ifdef __cplusplus 798 } 799 #endif 800 801 #endif // __SI32_CLKCTRL_A_REGISTERS_H__ 802 803 //-eof-------------------------------------------------------------------------- 804 805
