1 /***************************************************************************//**
2 * @file
3 * @brief Security Management Unit (SMU) peripheral API
4 *******************************************************************************
5 * # License
6 * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b>
7 *******************************************************************************
8 *
9 * SPDX-License-Identifier: Zlib
10 *
11 * The licensor of this software is Silicon Laboratories Inc.
12 *
13 * This software is provided 'as-is', without any express or implied
14 * warranty. In no event will the authors be held liable for any damages
15 * arising from the use of this software.
16 *
17 * Permission is granted to anyone to use this software for any purpose,
18 * including commercial applications, and to alter it and redistribute it
19 * freely, subject to the following restrictions:
20 *
21 * 1. The origin of this software must not be misrepresented; you must not
22 * claim that you wrote the original software. If you use this software
23 * in a product, an acknowledgment in the product documentation would be
24 * appreciated but is not required.
25 * 2. Altered source versions must be plainly marked as such, and must not be
26 * misrepresented as being the original software.
27 * 3. This notice may not be removed or altered from any source distribution.
28 *
29 ******************************************************************************/
30
31 #ifndef EM_SMU_H
32 #define EM_SMU_H
33
34 #include "em_device.h"
35 #if defined(SMU_COUNT) && (SMU_COUNT > 0)
36
37 #include "sl_assert.h"
38 #include "em_bus.h"
39
40 #include <stdint.h>
41 #include <stdbool.h>
42
43 #ifdef __cplusplus
44 extern "C" {
45 #endif
46
47 /***************************************************************************//**
48 * @addtogroup smu SMU - Security Management Unit
49 * @brief Security Management Unit (SMU) Peripheral API
50 *
51 * @details
52 * SMU forms the control and status/reporting component of bus-level
53 * security in EFM32/EFR32 devices.
54 *
55 * Peripheral-level protection is provided via the Peripheral Protection Unit
56 * (PPU). PPU provides hardware access barrier to any peripheral that is
57 * configured to be protected. When an attempt is made to access a peripheral
58 * without the required privilege/security level, PPU detects the fault
59 * and intercepts the access. No write or read of the peripheral register
60 * space occurs, and an all-zero value is returned if the access is a read.
61 *
62 * Usage example
63 * @include em_smu_init.c
64 * @{
65 ******************************************************************************/
66
67 /*******************************************************************************
68 ******************************** ENUMS ************************************
69 ******************************************************************************/
70
71 /** SMU peripheral identifiers. */
72 typedef enum {
73 #if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_84)
74 smuPeripheralACMP0 = _SMU_PPUPATD0_ACMP0_SHIFT, /**< SMU peripheral identifier for ACMP0. */
75 smuPeripheralACMP1 = _SMU_PPUPATD0_ACMP1_SHIFT, /**< SMU peripheral identifier for ACMP1. */
76 smuPeripheralADC0 = _SMU_PPUPATD0_ADC0_SHIFT, /**< SMU peripheral identifier for ADC0. */
77 smuPeripheralCMU = _SMU_PPUPATD0_CMU_SHIFT, /**< SMU peripheral identifier for CMU. */
78 smuPeripheralCRYOTIMER = _SMU_PPUPATD0_CRYOTIMER_SHIFT, /**< SMU peripheral identifier for CRYOTIMER. */
79 smuPeripheralCRYPTO0 = _SMU_PPUPATD0_CRYPTO0_SHIFT, /**< SMU peripheral identifier for CRYPTO0. */
80 smuPeripheralCRYPTO1 = _SMU_PPUPATD0_CRYPTO1_SHIFT, /**< SMU peripheral identifier for CRYPTO1. */
81 smuPeripheralCSEN = _SMU_PPUPATD0_CSEN_SHIFT, /**< SMU peripheral identifier for CSEN. */
82 smuPeripheralVDAC0 = _SMU_PPUPATD0_VDAC0_SHIFT, /**< SMU peripheral identifier for VDAC0. */
83 smuPeripheralPRS = _SMU_PPUPATD0_PRS_SHIFT, /**< SMU peripheral identifier for PRS. */
84 smuPeripheralEMU = _SMU_PPUPATD0_EMU_SHIFT, /**< SMU peripheral identifier for EMU. */
85 smuPeripheralFPUEH = _SMU_PPUPATD0_FPUEH_SHIFT, /**< SMU peripheral identifier for FPUEH. */
86 smuPeripheralGPCRC = _SMU_PPUPATD0_GPCRC_SHIFT, /**< SMU peripheral identifier for GPCRC. */
87 smuPeripheralGPIO = _SMU_PPUPATD0_GPIO_SHIFT, /**< SMU peripheral identifier for GPIO. */
88 smuPeripheralI2C0 = _SMU_PPUPATD0_I2C0_SHIFT, /**< SMU peripheral identifier for I2C0. */
89 smuPeripheralI2C1 = _SMU_PPUPATD0_I2C1_SHIFT, /**< SMU peripheral identifier for I2C1. */
90 smuPeripheralIDAC0 = _SMU_PPUPATD0_IDAC0_SHIFT, /**< SMU peripheral identifier for IDAC0. */
91 smuPeripheralMSC = _SMU_PPUPATD0_MSC_SHIFT, /**< SMU peripheral identifier for MSC. */
92 smuPeripheralLDMA = _SMU_PPUPATD0_LDMA_SHIFT, /**< SMU peripheral identifier for LDMA. */
93 smuPeripheralLESENSE = _SMU_PPUPATD0_LESENSE_SHIFT, /**< SMU peripheral identifier for LESENSE. */
94 smuPeripheralLETIMER0 = _SMU_PPUPATD0_LETIMER0_SHIFT, /**< SMU peripheral identifier for LETIMER0. */
95 smuPeripheralLEUART0 = _SMU_PPUPATD0_LEUART0_SHIFT, /**< SMU peripheral identifier for LEUART0. */
96 smuPeripheralPCNT0 = _SMU_PPUPATD0_PCNT0_SHIFT, /**< SMU peripheral identifier for PCNT0. */
97 smuPeripheralPCNT1 = _SMU_PPUPATD0_PCNT1_SHIFT, /**< SMU peripheral identifier for PCNT1. */
98 smuPeripheralPCNT2 = _SMU_PPUPATD0_PCNT2_SHIFT, /**< SMU peripheral identifier for PCNT2. */
99 smuPeripheralRMU = 32 + _SMU_PPUPATD1_RMU_SHIFT, /**< SMU peripheral identifier for RMU. */
100 smuPeripheralRTCC = 32 + _SMU_PPUPATD1_RTCC_SHIFT, /**< SMU peripheral identifier for RTCC. */
101 smuPeripheralSMU = 32 + _SMU_PPUPATD1_SMU_SHIFT, /**< SMU peripheral identifier for SMU. */
102 smuPeripheralTIMER0 = 32 + _SMU_PPUPATD1_TIMER0_SHIFT, /**< SMU peripheral identifier for TIMER0. */
103 smuPeripheralTIMER1 = 32 + _SMU_PPUPATD1_TIMER1_SHIFT, /**< SMU peripheral identifier for TIMER1. */
104 smuPeripheralTRNG0 = 32 + _SMU_PPUPATD1_TRNG0_SHIFT, /**< SMU peripheral identifier for TRNG0. */
105 smuPeripheralUSART0 = 32 + _SMU_PPUPATD1_USART0_SHIFT, /**< SMU peripheral identifier for USART0. */
106 smuPeripheralUSART1 = 32 + _SMU_PPUPATD1_USART1_SHIFT, /**< SMU peripheral identifier for USART1. */
107 smuPeripheralUSART2 = 32 + _SMU_PPUPATD1_USART2_SHIFT, /**< SMU peripheral identifier for USART2. */
108 smuPeripheralUSART3 = 32 + _SMU_PPUPATD1_USART3_SHIFT, /**< SMU peripheral identifier for USART3. */
109 smuPeripheralWDOG0 = 32 + _SMU_PPUPATD1_WDOG0_SHIFT, /**< SMU peripheral identifier for WDOG0. */
110 smuPeripheralWDOG1 = 32 + _SMU_PPUPATD1_WDOG1_SHIFT, /**< SMU peripheral identifier for WDOG1. */
111 smuPeripheralWTIMER0 = 32 + _SMU_PPUPATD1_WTIMER0_SHIFT, /**< SMU peripheral identifier for WTIMER0. */
112 smuPeripheralWTIMER1 = 32 + _SMU_PPUPATD1_WTIMER1_SHIFT, /**< SMU peripheral identifier for WTIMER1. */
113
114 #elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_89)
115 smuPeripheralACMP0 = _SMU_PPUPATD0_ACMP0_SHIFT, /**< SMU peripheral identifier for ACMP0. */
116 smuPeripheralACMP1 = _SMU_PPUPATD0_ACMP1_SHIFT, /**< SMU peripheral identifier for ACMP1. */
117 smuPeripheralADC0 = _SMU_PPUPATD0_ADC0_SHIFT, /**< SMU peripheral identifier for ADC0. */
118 smuPeripheralCMU = _SMU_PPUPATD0_CMU_SHIFT, /**< SMU peripheral identifier for CMU. */
119 smuPeripheralCRYOTIMER = _SMU_PPUPATD0_CRYOTIMER_SHIFT, /**< SMU peripheral identifier for CRYOTIMER. */
120 smuPeripheralCRYPTO0 = _SMU_PPUPATD0_CRYPTO0_SHIFT, /**< SMU peripheral identifier for CRYPTO0. */
121 smuPeripheralCRYPTO1 = _SMU_PPUPATD0_CRYPTO1_SHIFT, /**< SMU peripheral identifier for CRYPTO1. */
122 #if defined(_SMU_PPUPATD0_CSEN_SHIFT)
123 smuPeripheralCSEN = _SMU_PPUPATD0_CSEN_SHIFT, /**< SMU peripheral identifier for CSEN. */
124 #endif
125 #if defined(_SMU_PPUPATD0_VDAC0_SHIFT)
126 smuPeripheralVDAC0 = _SMU_PPUPATD0_VDAC0_SHIFT, /**< SMU peripheral identifier for VDAC0. */
127 #endif
128 smuPeripheralPRS = _SMU_PPUPATD0_PRS_SHIFT, /**< SMU peripheral identifier for PRS. */
129 smuPeripheralEMU = _SMU_PPUPATD0_EMU_SHIFT, /**< SMU peripheral identifier for EMU. */
130 smuPeripheralFPUEH = _SMU_PPUPATD0_FPUEH_SHIFT, /**< SMU peripheral identifier for FPUEH. */
131 smuPeripheralGPCRC = _SMU_PPUPATD0_GPCRC_SHIFT, /**< SMU peripheral identifier for GPCRC. */
132 smuPeripheralGPIO = _SMU_PPUPATD0_GPIO_SHIFT, /**< SMU peripheral identifier for GPIO. */
133 smuPeripheralI2C0 = _SMU_PPUPATD0_I2C0_SHIFT, /**< SMU peripheral identifier for I2C0. */
134 smuPeripheralI2C1 = _SMU_PPUPATD0_I2C1_SHIFT, /**< SMU peripheral identifier for I2C1. */
135 #if defined(_SMU_PPUPATD0_IDAC0_SHIFT)
136 smuPeripheralIDAC0 = _SMU_PPUPATD0_IDAC0_SHIFT, /**< SMU peripheral identifier for IDAC0. */
137 #endif
138 smuPeripheralMSC = _SMU_PPUPATD0_MSC_SHIFT, /**< SMU peripheral identifier for MSC. */
139 smuPeripheralLDMA = _SMU_PPUPATD0_LDMA_SHIFT, /**< SMU peripheral identifier for LDMA. */
140 smuPeripheralLESENSE = _SMU_PPUPATD0_LESENSE_SHIFT, /**< SMU peripheral identifier for LESENSE. */
141 smuPeripheralLETIMER0 = _SMU_PPUPATD0_LETIMER0_SHIFT, /**< SMU peripheral identifier for LETIMER0. */
142 smuPeripheralLEUART0 = _SMU_PPUPATD0_LEUART0_SHIFT, /**< SMU peripheral identifier for LEUART0. */
143 smuPeripheralPCNT0 = _SMU_PPUPATD0_PCNT0_SHIFT, /**< SMU peripheral identifier for PCNT0. */
144 smuPeripheralRMU = 32 + _SMU_PPUPATD1_RMU_SHIFT, /**< SMU peripheral identifier for RMU. */
145 smuPeripheralRTCC = 32 + _SMU_PPUPATD1_RTCC_SHIFT, /**< SMU peripheral identifier for RTCC. */
146 smuPeripheralSMU = 32 + _SMU_PPUPATD1_SMU_SHIFT, /**< SMU peripheral identifier for SMU. */
147 smuPeripheralTIMER0 = 32 + _SMU_PPUPATD1_TIMER0_SHIFT, /**< SMU peripheral identifier for TIMER0. */
148 smuPeripheralTIMER1 = 32 + _SMU_PPUPATD1_TIMER1_SHIFT, /**< SMU peripheral identifier for TIMER1. */
149 smuPeripheralTRNG0 = 32 + _SMU_PPUPATD1_TRNG0_SHIFT, /**< SMU peripheral identifier for TRNG0. */
150 smuPeripheralUSART0 = 32 + _SMU_PPUPATD1_USART0_SHIFT, /**< SMU peripheral identifier for USART0. */
151 smuPeripheralUSART1 = 32 + _SMU_PPUPATD1_USART1_SHIFT, /**< SMU peripheral identifier for USART1. */
152 smuPeripheralUSART2 = 32 + _SMU_PPUPATD1_USART2_SHIFT, /**< SMU peripheral identifier for USART2. */
153 smuPeripheralWDOG0 = 32 + _SMU_PPUPATD1_WDOG0_SHIFT, /**< SMU peripheral identifier for WDOG0. */
154 smuPeripheralWDOG1 = 32 + _SMU_PPUPATD1_WDOG1_SHIFT, /**< SMU peripheral identifier for WDOG1. */
155 smuPeripheralWTIMER0 = 32 + _SMU_PPUPATD1_WTIMER0_SHIFT, /**< SMU peripheral identifier for WTIMER0. */
156
157 #elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_95)
158 #if defined(_SMU_PPUPATD0_ACMP0_SHIFT)
159 smuPeripheralACMP0 = _SMU_PPUPATD0_ACMP0_SHIFT, /**< SMU peripheral identifier for ACMP0. */
160 #endif
161 #if defined(_SMU_PPUPATD0_ACMP1_SHIFT)
162 smuPeripheralACMP1 = _SMU_PPUPATD0_ACMP1_SHIFT, /**< SMU peripheral identifier for ACMP1. */
163 #endif
164 #if defined(_SMU_PPUPATD0_ADC0_SHIFT)
165 smuPeripheralADC0 = _SMU_PPUPATD0_ADC0_SHIFT, /**< SMU peripheral identifier for ADC0. */
166 #endif
167 smuPeripheralCMU = _SMU_PPUPATD0_CMU_SHIFT, /**< SMU peripheral identifier for CMU. */
168 smuPeripheralCRYOTIMER = _SMU_PPUPATD0_CRYOTIMER_SHIFT, /**< SMU peripheral identifier for CRYOTIMER. */
169 smuPeripheralCRYPTO = _SMU_PPUPATD0_CRYPTO0_SHIFT, /**< SMU peripheral identifier for CRYPTO0. */
170 #if defined(_SMU_PPUPATD0_VDAC0_SHIFT)
171 smuPeripheralVDAC0 = _SMU_PPUPATD0_VDAC0_SHIFT, /**< SMU peripheral identifier for VDAC0. */
172 #endif
173 smuPeripheralPRS = _SMU_PPUPATD0_PRS_SHIFT, /**< SMU peripheral identifier for PRS. */
174 smuPeripheralEMU = _SMU_PPUPATD0_EMU_SHIFT, /**< SMU peripheral identifier for EMU. */
175 smuPeripheralFPUEH = _SMU_PPUPATD0_FPUEH_SHIFT, /**< SMU peripheral identifier for FPUEH. */
176 smuPeripheralGPCRC = _SMU_PPUPATD0_GPCRC_SHIFT, /**< SMU peripheral identifier for GPCRC. */
177 smuPeripheralGPIO = _SMU_PPUPATD0_GPIO_SHIFT, /**< SMU peripheral identifier for GPIO. */
178 smuPeripheralI2C0 = _SMU_PPUPATD0_I2C0_SHIFT, /**< SMU peripheral identifier for I2C0. */
179 #if defined(_SMU_PPUPATD0_IDAC0_SHIFT)
180 smuPeripheralIDAC0 = _SMU_PPUPATD0_IDAC0_SHIFT, /**< SMU peripheral identifier for IDAC0. */
181 #endif
182 smuPeripheralMSC = _SMU_PPUPATD0_MSC_SHIFT, /**< SMU peripheral identifier for MSC. */
183 smuPeripheralLDMA = _SMU_PPUPATD0_LDMA_SHIFT, /**< SMU peripheral identifier for LDMA. */
184 #if defined(_SMU_PPUPATD0_LESENSE_SHIFT)
185 smuPeripheralLESENSE = _SMU_PPUPATD0_LESENSE_SHIFT, /**< SMU peripheral identifier for LESENSE. */
186 #endif
187 smuPeripheralLETIMER0 = _SMU_PPUPATD0_LETIMER0_SHIFT, /**< SMU peripheral identifier for LETIMER0. */
188 smuPeripheralLEUART = _SMU_PPUPATD0_LEUART0_SHIFT, /**< SMU peripheral identifier for LEUART0. */
189 #if defined(_SMU_PPUPATD0_PCNT0_SHIFT)
190 smuPeripheralPCNT0 = _SMU_PPUPATD0_PCNT0_SHIFT, /**< SMU peripheral identifier for PCNT0. */
191 #endif
192 smuPeripheralRMU = _SMU_PPUPATD0_RMU_SHIFT, /**< SMU peripheral identifier for RMU. */
193 smuPeripheralRTCC = _SMU_PPUPATD0_RTCC_SHIFT, /**< SMU peripheral identifier for RTCC. */
194 smuPeripheralSMU = _SMU_PPUPATD0_SMU_SHIFT, /**< SMU peripheral identifier for SMU. */
195 smuPeripheralTIMER0 = 32 + _SMU_PPUPATD1_TIMER0_SHIFT, /**< SMU peripheral identifier for TIMER0. */
196 smuPeripheralTIMER1 = 32 + _SMU_PPUPATD1_TIMER1_SHIFT, /**< SMU peripheral identifier for TIMER1. */
197 smuPeripheralTRNG0 = 32 + _SMU_PPUPATD1_TRNG0_SHIFT, /**< SMU peripheral identifier for TRNG0. */
198 smuPeripheralUSART0 = 32 + _SMU_PPUPATD1_USART0_SHIFT, /**< SMU peripheral identifier for USART0. */
199 smuPeripheralUSART1 = 32 + _SMU_PPUPATD1_USART1_SHIFT, /**< SMU peripheral identifier for USART1. */
200 smuPeripheralWDOG0 = 32 + _SMU_PPUPATD1_WDOG0_SHIFT, /**< SMU peripheral identifier for WDOG0. */
201 smuPeripheralWDOG1 = 32 + _SMU_PPUPATD1_WDOG1_SHIFT, /**< SMU peripheral identifier for WDOG1. */
202 smuPeripheralWTIMER0 = 32 + _SMU_PPUPATD1_WTIMER0_SHIFT, /**< SMU peripheral identifier for WTIMER0. */
203
204 #elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_100)
205 smuPeripheralACMP0 = _SMU_PPUPATD0_ACMP0_SHIFT, /**< SMU peripheral identifier for ACMP0. */
206 smuPeripheralACMP1 = _SMU_PPUPATD0_ACMP1_SHIFT, /**< SMU peripheral identifier for ACMP1. */
207 smuPeripheralACMP2 = _SMU_PPUPATD0_ACMP2_SHIFT, /**< SMU peripheral identifier for ACMP2. */
208 smuPeripheralACMP3 = _SMU_PPUPATD0_ACMP3_SHIFT, /**< SMU peripheral identifier for ACMP3. */
209 smuPeripheralADC0 = _SMU_PPUPATD0_ADC0_SHIFT, /**< SMU peripheral identifier for ADC0. */
210 smuPeripheralADC1 = _SMU_PPUPATD0_ADC1_SHIFT, /**< SMU peripheral identifier for ADC1. */
211 smuPeripheralCAN0 = _SMU_PPUPATD0_CAN0_SHIFT, /**< SMU peripheral identifier for CAN0. */
212 smuPeripheralCAN1 = _SMU_PPUPATD0_CAN1_SHIFT, /**< SMU peripheral identifier for CAN1. */
213 smuPeripheralCMU = _SMU_PPUPATD0_CMU_SHIFT, /**< SMU peripheral identifier for CMU. */
214 smuPeripheralCRYOTIMER = _SMU_PPUPATD0_CRYOTIMER_SHIFT, /**< SMU peripheral identifier for CRYOTIMER. */
215 smuPeripheralCRYPTO0 = _SMU_PPUPATD0_CRYPTO0_SHIFT, /**< SMU peripheral identifier for CRYPTO0. */
216 smuPeripheralCSEN = _SMU_PPUPATD0_CSEN_SHIFT, /**< SMU peripheral identifier for CSEN. */
217 smuPeripheralVDAC0 = _SMU_PPUPATD0_VDAC0_SHIFT, /**< SMU peripheral identifier for VDAC0. */
218 smuPeripheralPRS = _SMU_PPUPATD0_PRS_SHIFT, /**< SMU peripheral identifier for PRS. */
219 smuPeripheralEBI = _SMU_PPUPATD0_EBI_SHIFT, /**< SMU peripheral identifier for EBI. */
220 smuPeripheralEMU = _SMU_PPUPATD0_EMU_SHIFT, /**< SMU peripheral identifier for EMU. */
221 #if defined(_SMU_PPUPATD0_ETH_SHIFT)
222 smuPeripheralETH = _SMU_PPUPATD0_ETH_SHIFT, /**< SMU peripheral identifier for ETH. */
223 #endif
224 smuPeripheralFPUEH = _SMU_PPUPATD0_FPUEH_SHIFT, /**< SMU peripheral identifier for FPUEH. */
225 smuPeripheralGPCRC = _SMU_PPUPATD0_GPCRC_SHIFT, /**< SMU peripheral identifier for GPCRC. */
226 smuPeripheralGPIO = _SMU_PPUPATD0_GPIO_SHIFT, /**< SMU peripheral identifier for GPIO. */
227 smuPeripheralI2C0 = _SMU_PPUPATD0_I2C0_SHIFT, /**< SMU peripheral identifier for I2C0. */
228 smuPeripheralI2C1 = _SMU_PPUPATD0_I2C1_SHIFT, /**< SMU peripheral identifier for I2C1. */
229 smuPeripheralI2C2 = _SMU_PPUPATD0_I2C2_SHIFT, /**< SMU peripheral identifier for I2C2. */
230 smuPeripheralIDAC0 = _SMU_PPUPATD0_IDAC0_SHIFT, /**< SMU peripheral identifier for IDAC0. */
231 smuPeripheralMSC = _SMU_PPUPATD0_MSC_SHIFT, /**< SMU peripheral identifier for MAC. */
232 #if defined(_SMU_PPUPATD0_LCD_SHIFT)
233 smuPeripheralLCD = _SMU_PPUPATD0_LCD_SHIFT, /**< SMU peripheral identifier for LCD. */
234 #endif
235 smuPeripheralLDMA = _SMU_PPUPATD0_LDMA_SHIFT, /**< SMU peripheral identifier for LDMA. */
236 smuPeripheralLESENSE = _SMU_PPUPATD0_LESENSE_SHIFT, /**< SMU peripheral identifier for LESENSE. */
237 smuPeripheralLETIMER0 = _SMU_PPUPATD0_LETIMER0_SHIFT, /**< SMU peripheral identifier for LETIMER0. */
238 smuPeripheralLETIMER1 = _SMU_PPUPATD0_LETIMER1_SHIFT, /**< SMU peripheral identifier for LETIMER1. */
239 smuPeripheralLEUART0 = _SMU_PPUPATD0_LEUART0_SHIFT, /**< SMU peripheral identifier for LEUART0. */
240 smuPeripheralLEUART1 = _SMU_PPUPATD0_LEUART1_SHIFT, /**< SMU peripheral identifier for LEUART1. */
241 smuPeripheralPCNT0 = 32 + _SMU_PPUPATD1_PCNT0_SHIFT, /**< SMU peripheral identifier for PCNT0. */
242 smuPeripheralPCNT1 = 32 + _SMU_PPUPATD1_PCNT1_SHIFT, /**< SMU peripheral identifier for PCNT1. */
243 smuPeripheralPCNT2 = 32 + _SMU_PPUPATD1_PCNT2_SHIFT, /**< SMU peripheral identifier for PCNT2. */
244 #if defined(_SMU_PPUPATD1_QSPI0_SHIFT)
245 smuPeripheralQSPI0 = 32 + _SMU_PPUPATD1_QSPI0_SHIFT, /**< SMU peripheral identifier for QSPI0. */
246 #endif
247 smuPeripheralRMU = 32 + _SMU_PPUPATD1_RMU_SHIFT, /**< SMU peripheral identifier for RMU. */
248 smuPeripheralRTC = 32 + _SMU_PPUPATD1_RTC_SHIFT, /**< SMU peripheral identifier for RTC. */
249 smuPeripheralRTCC = 32 + _SMU_PPUPATD1_RTCC_SHIFT, /**< SMU peripheral identifier for RTCC. */
250 #if defined(_SMU_PPUPATD1_SDIO_SHIFT)
251 smuPeripheralSDIO = 32 + _SMU_PPUPATD1_SDIO_SHIFT, /**< SMU peripheral identifier for SDIO. */
252 #endif
253 smuPeripheralSMU = 32 + _SMU_PPUPATD1_SMU_SHIFT, /**< SMU peripheral identifier for SMU. */
254 smuPeripheralTIMER0 = 32 + _SMU_PPUPATD1_TIMER0_SHIFT, /**< SMU peripheral identifier for TIMER0. */
255 smuPeripheralTIMER1 = 32 + _SMU_PPUPATD1_TIMER1_SHIFT, /**< SMU peripheral identifier for TIMER1. */
256 smuPeripheralTIMER2 = 32 + _SMU_PPUPATD1_TIMER2_SHIFT, /**< SMU peripheral identifier for TIMER2. */
257 smuPeripheralTIMER3 = 32 + _SMU_PPUPATD1_TIMER3_SHIFT, /**< SMU peripheral identifier for TIMER3. */
258 smuPeripheralTIMER4 = 32 + _SMU_PPUPATD1_TIMER4_SHIFT, /**< SMU peripheral identifier for TIMER4. */
259 smuPeripheralTIMER5 = 32 + _SMU_PPUPATD1_TIMER5_SHIFT, /**< SMU peripheral identifier for TIMER5. */
260 smuPeripheralTIMER6 = 32 + _SMU_PPUPATD1_TIMER6_SHIFT, /**< SMU peripheral identifier for TIMER6. */
261 smuPeripheralTRNG0 = 32 + _SMU_PPUPATD1_TRNG0_SHIFT, /**< SMU peripheral identifier for TRNG0. */
262 smuPeripheralUART0 = 32 + _SMU_PPUPATD1_UART0_SHIFT, /**< SMU peripheral identifier for UART0. */
263 smuPeripheralUART1 = 32 + _SMU_PPUPATD1_UART1_SHIFT, /**< SMU peripheral identifier for UART1. */
264 smuPeripheralUSART0 = 32 + _SMU_PPUPATD1_USART0_SHIFT, /**< SMU peripheral identifier for USART0. */
265 smuPeripheralUSART1 = 32 + _SMU_PPUPATD1_USART1_SHIFT, /**< SMU peripheral identifier for USART1. */
266 smuPeripheralUSART2 = 32 + _SMU_PPUPATD1_USART2_SHIFT, /**< SMU peripheral identifier for USART2. */
267 smuPeripheralUSART3 = 32 + _SMU_PPUPATD1_USART3_SHIFT, /**< SMU peripheral identifier for USART3. */
268 smuPeripheralUSART4 = 32 + _SMU_PPUPATD1_USART4_SHIFT, /**< SMU peripheral identifier for USART4. */
269 smuPeripheralUSART5 = 32 + _SMU_PPUPATD1_USART5_SHIFT, /**< SMU peripheral identifier for USART5. */
270 #if defined(_SMU_PPUPATD1_USB_SHIFT)
271 smuPeripheralUSB = 32 + _SMU_PPUPATD1_USB_SHIFT, /**< SMU peripheral identifier for USB. */
272 #endif
273 smuPeripheralWDOG0 = 32 + _SMU_PPUPATD1_WDOG0_SHIFT, /**< SMU peripheral identifier for WDOG0. */
274 smuPeripheralWDOG1 = 32 + _SMU_PPUPATD1_WDOG1_SHIFT, /**< SMU peripheral identifier for WDOG1. */
275 smuPeripheralWTIMER0 = 32 + _SMU_PPUPATD1_WTIMER0_SHIFT, /**< SMU peripheral identifier for WTIMER0. */
276 smuPeripheralWTIMER1 = 32 + _SMU_PPUPATD1_WTIMER1_SHIFT, /**< SMU peripheral identifier for WTIMER1. */
277 smuPeripheralWTIMER2 = 32 + _SMU_PPUPATD1_WTIMER2_SHIFT, /**< SMU peripheral identifier for WTIMER2. */
278 smuPeripheralWTIMER3 = 32 + _SMU_PPUPATD1_WTIMER3_SHIFT, /**< SMU peripheral identifier for WTIMER3. */
279
280 #elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_106)
281 smuPeripheralACMP0 = _SMU_PPUPATD0_ACMP0_SHIFT, /**< SMU peripheral identifier for ACMP0. */
282 smuPeripheralACMP1 = _SMU_PPUPATD0_ACMP1_SHIFT, /**< SMU peripheral identifier for ACMP1. */
283 smuPeripheralACMP2 = _SMU_PPUPATD0_ACMP2_SHIFT, /**< SMU peripheral identifier for ACMP2. */
284 smuPeripheralADC0 = _SMU_PPUPATD0_ADC0_SHIFT, /**< SMU peripheral identifier for ADC0. */
285 smuPeripheralADC1 = _SMU_PPUPATD0_ADC1_SHIFT, /**< SMU peripheral identifier for ADC1. */
286 smuPeripheralCAN0 = _SMU_PPUPATD0_CAN0_SHIFT, /**< SMU peripheral identifier for CAN0. */
287 smuPeripheralCAN1 = _SMU_PPUPATD0_CAN1_SHIFT, /**< SMU peripheral identifier for CAN1. */
288 smuPeripheralCMU = _SMU_PPUPATD0_CMU_SHIFT, /**< SMU peripheral identifier for CMU. */
289 smuPeripheralCRYOTIMER = _SMU_PPUPATD0_CRYOTIMER_SHIFT, /**< SMU peripheral identifier for CRYOTIMER. */
290 smuPeripheralCRYPTO0 = _SMU_PPUPATD0_CRYPTO0_SHIFT, /**< SMU peripheral identifier for CRYPTO0. */
291 smuPeripheralCSEN = _SMU_PPUPATD0_CSEN_SHIFT, /**< SMU peripheral identifier for CSEN. */
292 smuPeripheralVDAC0 = _SMU_PPUPATD0_VDAC0_SHIFT, /**< SMU peripheral identifier for VDAC0. */
293 smuPeripheralPRS = _SMU_PPUPATD0_PRS_SHIFT, /**< SMU peripheral identifier for PRS. */
294 smuPeripheralEBI = _SMU_PPUPATD0_EBI_SHIFT, /**< SMU peripheral identifier for EBI. */
295 smuPeripheralEMU = _SMU_PPUPATD0_EMU_SHIFT, /**< SMU peripheral identifier for EMU. */
296 #if defined(_SMU_PPUPATD0_ETH_SHIFT)
297 smuPeripheralETH = _SMU_PPUPATD0_ETH_SHIFT, /**< SMU peripheral identifier for ETH. */
298 #endif
299 smuPeripheralFPUEH = _SMU_PPUPATD0_FPUEH_SHIFT, /**< SMU peripheral identifier for FPUEH. */
300 smuPeripheralGPCRC = _SMU_PPUPATD0_GPCRC_SHIFT, /**< SMU peripheral identifier for GPCRC. */
301 smuPeripheralGPIO = _SMU_PPUPATD0_GPIO_SHIFT, /**< SMU peripheral identifier for GPIO. */
302 smuPeripheralI2C0 = _SMU_PPUPATD0_I2C0_SHIFT, /**< SMU peripheral identifier for I2C0. */
303 smuPeripheralI2C1 = _SMU_PPUPATD0_I2C1_SHIFT, /**< SMU peripheral identifier for I2C1. */
304 smuPeripheralIDAC0 = _SMU_PPUPATD0_IDAC0_SHIFT, /**< SMU peripheral identifier for IDAC0. */
305 smuPeripheralMSC = _SMU_PPUPATD0_MSC_SHIFT, /**< SMU peripheral identifier for MAC. */
306 #if defined(_SMU_PPUPATD0_LCD_SHIFT)
307 smuPeripheralLCD = _SMU_PPUPATD0_LCD_SHIFT, /**< SMU peripheral identifier for LCD. */
308 #endif
309 smuPeripheralLDMA = _SMU_PPUPATD0_LDMA_SHIFT, /**< SMU peripheral identifier for LDMA. */
310 smuPeripheralLESENSE = _SMU_PPUPATD0_LESENSE_SHIFT, /**< SMU peripheral identifier for LESENSE. */
311 smuPeripheralLETIMER0 = _SMU_PPUPATD0_LETIMER0_SHIFT, /**< SMU peripheral identifier for LETIMER0. */
312 smuPeripheralLETIMER1 = _SMU_PPUPATD0_LETIMER1_SHIFT, /**< SMU peripheral identifier for LETIMER1. */
313 smuPeripheralLEUART0 = _SMU_PPUPATD0_LEUART0_SHIFT, /**< SMU peripheral identifier for LEUART0. */
314 smuPeripheralLEUART1 = _SMU_PPUPATD0_LEUART1_SHIFT, /**< SMU peripheral identifier for LEUART1. */
315 smuPeripheralPCNT0 = 32 + _SMU_PPUPATD1_PCNT0_SHIFT, /**< SMU peripheral identifier for PCNT0. */
316 smuPeripheralPCNT1 = 32 + _SMU_PPUPATD1_PCNT1_SHIFT, /**< SMU peripheral identifier for PCNT1. */
317 smuPeripheralPCNT2 = 32 + _SMU_PPUPATD1_PCNT2_SHIFT, /**< SMU peripheral identifier for PCNT2. */
318 #if defined(_SMU_PPUPATD1_QSPI0_SHIFT)
319 smuPeripheralQSPI0 = 32 + _SMU_PPUPATD1_QSPI0_SHIFT, /**< SMU peripheral identifier for QSPI0. */
320 #endif
321 smuPeripheralRMU = 32 + _SMU_PPUPATD1_RMU_SHIFT, /**< SMU peripheral identifier for RMU. */
322 smuPeripheralRTC = 32 + _SMU_PPUPATD1_RTC_SHIFT, /**< SMU peripheral identifier for RTC. */
323 smuPeripheralRTCC = 32 + _SMU_PPUPATD1_RTCC_SHIFT, /**< SMU peripheral identifier for RTCC. */
324 #if defined(_SMU_PPUPATD1_SDIO_SHIFT)
325 smuPeripheralSDIO = 32 + _SMU_PPUPATD1_SDIO_SHIFT, /**< SMU peripheral identifier for SDIO. */
326 #endif
327 smuPeripheralSMU = 32 + _SMU_PPUPATD1_SMU_SHIFT, /**< SMU peripheral identifier for SMU. */
328 smuPeripheralTIMER0 = 32 + _SMU_PPUPATD1_TIMER0_SHIFT, /**< SMU peripheral identifier for TIMER0. */
329 smuPeripheralTIMER1 = 32 + _SMU_PPUPATD1_TIMER1_SHIFT, /**< SMU peripheral identifier for TIMER1. */
330 smuPeripheralTIMER2 = 32 + _SMU_PPUPATD1_TIMER2_SHIFT, /**< SMU peripheral identifier for TIMER2. */
331 smuPeripheralTIMER3 = 32 + _SMU_PPUPATD1_TIMER3_SHIFT, /**< SMU peripheral identifier for TIMER3. */
332 smuPeripheralTRNG0 = 32 + _SMU_PPUPATD1_TRNG0_SHIFT, /**< SMU peripheral identifier for TRNG0. */
333 smuPeripheralUART0 = 32 + _SMU_PPUPATD1_UART0_SHIFT, /**< SMU peripheral identifier for UART0. */
334 smuPeripheralUART1 = 32 + _SMU_PPUPATD1_UART1_SHIFT, /**< SMU peripheral identifier for UART1. */
335 smuPeripheralUSART0 = 32 + _SMU_PPUPATD1_USART0_SHIFT, /**< SMU peripheral identifier for USART0. */
336 smuPeripheralUSART1 = 32 + _SMU_PPUPATD1_USART1_SHIFT, /**< SMU peripheral identifier for USART1. */
337 smuPeripheralUSART2 = 32 + _SMU_PPUPATD1_USART2_SHIFT, /**< SMU peripheral identifier for USART2. */
338 smuPeripheralUSART3 = 32 + _SMU_PPUPATD1_USART3_SHIFT, /**< SMU peripheral identifier for USART3. */
339 smuPeripheralUSART4 = 32 + _SMU_PPUPATD1_USART4_SHIFT, /**< SMU peripheral identifier for USART4. */
340 #if defined(_SMU_PPUPATD1_USB_SHIFT)
341 smuPeripheralUSB = 32 + _SMU_PPUPATD1_USB_SHIFT, /**< SMU peripheral identifier for USB. */
342 #endif
343 smuPeripheralWDOG0 = 32 + _SMU_PPUPATD1_WDOG0_SHIFT, /**< SMU peripheral identifier for WDOG0. */
344 smuPeripheralWDOG1 = 32 + _SMU_PPUPATD1_WDOG1_SHIFT, /**< SMU peripheral identifier for WDOG1. */
345 smuPeripheralWTIMER0 = 32 + _SMU_PPUPATD1_WTIMER0_SHIFT, /**< SMU peripheral identifier for WTIMER0. */
346 smuPeripheralWTIMER1 = 32 + _SMU_PPUPATD1_WTIMER1_SHIFT, /**< SMU peripheral identifier for WTIMER1. */
347
348 #elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_103)
349 smuPeripheralACMP0 = _SMU_PPUPATD0_ACMP0_SHIFT, /**< SMU peripheral identifier for ACMP0. */
350 smuPeripheralACMP1 = _SMU_PPUPATD0_ACMP1_SHIFT, /**< SMU peripheral identifier for ACMP1. */
351 smuPeripheralADC0 = _SMU_PPUPATD0_ADC0_SHIFT, /**< SMU peripheral identifier for ADC0. */
352 smuPeripheralCAN0 = _SMU_PPUPATD0_CAN0_SHIFT, /**< SMU peripheral identifier for CAN0. */
353 smuPeripheralCMU = _SMU_PPUPATD0_CMU_SHIFT, /**< SMU peripheral identifier for CMU. */
354 smuPeripheralCRYOTIMER = _SMU_PPUPATD0_CRYOTIMER_SHIFT, /**< SMU peripheral identifier for CRYOTIMER. */
355 smuPeripheralCRYPTO0 = _SMU_PPUPATD0_CRYPTO0_SHIFT, /**< SMU peripheral identifier for CRYPTO0. */
356 smuPeripheralCSEN = _SMU_PPUPATD0_CSEN_SHIFT, /**< SMU peripheral identifier for CSEN. */
357 smuPeripheralVDAC0 = _SMU_PPUPATD0_VDAC0_SHIFT, /**< SMU peripheral identifier for VDAC0. */
358 smuPeripheralPRS = _SMU_PPUPATD0_PRS_SHIFT, /**< SMU peripheral identifier for PRS. */
359 smuPeripheralEMU = _SMU_PPUPATD0_EMU_SHIFT, /**< SMU peripheral identifier for EMU. */
360 smuPeripheralGPCRC = _SMU_PPUPATD0_GPCRC_SHIFT, /**< SMU peripheral identifier for GPCRC. */
361 smuPeripheralGPIO = _SMU_PPUPATD0_GPIO_SHIFT, /**< SMU peripheral identifier for GPIO. */
362 smuPeripheralI2C0 = _SMU_PPUPATD0_I2C0_SHIFT, /**< SMU peripheral identifier for I2C0. */
363 smuPeripheralI2C1 = _SMU_PPUPATD0_I2C1_SHIFT, /**< SMU peripheral identifier for I2C1. */
364 smuPeripheralMSC = _SMU_PPUPATD0_MSC_SHIFT, /**< SMU peripheral identifier for MAC. */
365 #if defined(_SMU_PPUPATD0_LCD_SHIFT)
366 smuPeripheralLCD = _SMU_PPUPATD0_LCD_SHIFT, /**< SMU peripheral identifier for LCD. */
367 #endif
368 smuPeripheralLDMA = _SMU_PPUPATD0_LDMA_SHIFT, /**< SMU peripheral identifier for LDMA. */
369 smuPeripheralLESENSE = _SMU_PPUPATD0_LESENSE_SHIFT, /**< SMU peripheral identifier for LESENSE. */
370 smuPeripheralLETIMER0 = _SMU_PPUPATD0_LETIMER0_SHIFT, /**< SMU peripheral identifier for LETIMER0. */
371 smuPeripheralLEUART0 = _SMU_PPUPATD0_LEUART0_SHIFT, /**< SMU peripheral identifier for LEUART0. */
372 smuPeripheralPCNT0 = _SMU_PPUPATD0_PCNT0_SHIFT, /**< SMU peripheral identifier for PCNT0. */
373 smuPeripheralRMU = _SMU_PPUPATD0_RMU_SHIFT, /**< SMU peripheral identifier for RMU. */
374 smuPeripheralRTCC = _SMU_PPUPATD0_RTCC_SHIFT, /**< SMU peripheral identifier for RTCC. */
375 smuPeripheralSMU = _SMU_PPUPATD0_SMU_SHIFT, /**< SMU peripheral identifier for SMU. */
376 smuPeripheralTIMER0 = _SMU_PPUPATD0_TIMER0_SHIFT, /**< SMU peripheral identifier for TIMER0. */
377 smuPeripheralTIMER1 = _SMU_PPUPATD0_TIMER1_SHIFT, /**< SMU peripheral identifier for TIMER0. */
378 smuPeripheralTRNG0 = _SMU_PPUPATD0_TRNG0_SHIFT, /**< SMU peripheral identifier for TRNG0. */
379 smuPeripheralUART0 = _SMU_PPUPATD0_UART0_SHIFT, /**< SMU peripheral identifier for UART0. */
380 smuPeripheralUSART0 = _SMU_PPUPATD0_USART0_SHIFT, /**< SMU peripheral identifier for USART0. */
381 smuPeripheralUSART1 = _SMU_PPUPATD0_USART1_SHIFT, /**< SMU peripheral identifier for USART1. */
382 smuPeripheralUSART2 = _SMU_PPUPATD0_USART2_SHIFT, /**< SMU peripheral identifier for USART2. */
383 smuPeripheralUSART3 = 32 + _SMU_PPUPATD1_USART3_SHIFT, /**< SMU peripheral identifier for USART3. */
384 smuPeripheralWDOG0 = 32 + _SMU_PPUPATD1_WDOG0_SHIFT, /**< SMU peripheral identifier for WDOG0. */
385 smuPeripheralWTIMER0 = 32 + _SMU_PPUPATD1_WTIMER0_SHIFT, /**< SMU peripheral identifier for WTIMER0. */
386 smuPeripheralWTIMER1 = 32 + _SMU_PPUPATD1_WTIMER1_SHIFT, /**< SMU peripheral identifier for WTIMER1. */
387
388 #elif defined(_SILICON_LABS_32B_SERIES_2)
389 #if defined(SMU_PPUPATD0_SCRATCHPAD)
390 smuPeripheralSCRATCHPAD = _SMU_PPUPATD0_SCRATCHPAD_SHIFT, /**< SMU peripheral identifier for SCRATCHPAD */
391 #endif
392 smuPeripheralEMU = _SMU_PPUPATD0_EMU_SHIFT, /**< SMU peripheral identifier for EMU */
393 smuPeripheralCMU = _SMU_PPUPATD0_CMU_SHIFT, /**< SMU peripheral identifier for CMU */
394 #if defined(_SMU_PPUPATD0_HFXO0_SHIFT)
395 smuPeripheralHFXO = _SMU_PPUPATD0_HFXO0_SHIFT, /**< SMU peripheral identifier for HFXO0 */
396 #endif
397 #if defined(_SMU_PPUPATD1_HFXO0_SHIFT)
398 smuPeripheralHFXO = 32 + _SMU_PPUPATD1_HFXO0_SHIFT, /**< SMU peripheral identifier for HFXO0 */
399 #endif
400 smuPeripheralHFRCO0 = _SMU_PPUPATD0_HFRCO0_SHIFT, /**< SMU peripheral identifier for HFRCO0 */
401 smuPeripheralFSRCO = _SMU_PPUPATD0_FSRCO_SHIFT, /**< SMU peripheral identifier for FSRCO */
402 smuPeripheralDPLL0 = _SMU_PPUPATD0_DPLL0_SHIFT, /**< SMU peripheral identifier for DPLL0 */
403 smuPeripheralLFXO = _SMU_PPUPATD0_LFXO_SHIFT, /**< SMU peripheral identifier for LFXO */
404 smuPeripheralLFRCO = _SMU_PPUPATD0_LFRCO_SHIFT, /**< SMU peripheral identifier for LFRCO */
405 smuPeripheralULFRCO = _SMU_PPUPATD0_ULFRCO_SHIFT, /**< SMU peripheral identifier for ULFRCO */
406 smuPeripheralMSC = _SMU_PPUPATD0_MSC_SHIFT, /**< SMU peripheral identifier for MSC */
407 smuPeripheralICACHE0 = _SMU_PPUPATD0_ICACHE0_SHIFT, /**< SMU peripheral identifier for ICACHE0 */
408 smuPeripheralPRS = _SMU_PPUPATD0_PRS_SHIFT, /**< SMU peripheral identifier for PRS */
409 smuPeripheralGPIO = _SMU_PPUPATD0_GPIO_SHIFT, /**< SMU peripheral identifier for GPIO */
410 smuPeripheralLDMA = _SMU_PPUPATD0_LDMA_SHIFT, /**< SMU peripheral identifier for LDMA */
411 smuPeripheralLDMAXBAR = _SMU_PPUPATD0_LDMAXBAR_SHIFT, /**< SMU peripheral identifier for LDMAXBAR */
412 smuPeripheralTIMER0 = _SMU_PPUPATD0_TIMER0_SHIFT, /**< SMU peripheral identifier for TIMER0 */
413 smuPeripheralTIMER1 = _SMU_PPUPATD0_TIMER1_SHIFT, /**< SMU peripheral identifier for TIMER1 */
414 smuPeripheralTIMER2 = _SMU_PPUPATD0_TIMER2_SHIFT, /**< SMU peripheral identifier for TIMER2 */
415 smuPeripheralTIMER3 = _SMU_PPUPATD0_TIMER3_SHIFT, /**< SMU peripheral identifier for TIMER3 */
416 #if defined(_SMU_PPUPATD0_TIMER4_SHIFT)
417 smuPeripheralTIMER4 = _SMU_PPUPATD0_TIMER4_SHIFT, /**< SMU peripheral identifier for TIMER4 */
418 #endif
419 #if defined(_SMU_PPUPATD0_TIMER5_SHIFT)
420 smuPeripheralTIMER5 = _SMU_PPUPATD0_TIMER5_SHIFT, /**< SMU peripheral identifier for TIMER5 */
421 #endif
422 #if defined(_SMU_PPUPATD0_TIMER6_SHIFT)
423 smuPeripheralTIMER6 = _SMU_PPUPATD0_TIMER6_SHIFT, /**< SMU peripheral identifier for TIMER6 */
424 #endif
425 #if defined(_SMU_PPUPATD0_TIMER7_SHIFT)
426 smuPeripheralTIMER7 = _SMU_PPUPATD0_TIMER7_SHIFT, /**< SMU peripheral identifier for TIMER7 */
427 #endif
428 #if defined(_SMU_PPUPATD0_USART0_SHIFT)
429 smuPeripheralUSART0 = _SMU_PPUPATD0_USART0_SHIFT, /**< SMU peripheral identifier for USART0 */
430 #endif
431 #if defined(_SMU_PPUPATD0_USART1_SHIFT)
432 smuPeripheralUSART1 = _SMU_PPUPATD0_USART1_SHIFT, /**< SMU peripheral identifier for USART1 */
433 #endif
434 #if defined(_SMU_PPUPATD0_USART2_SHIFT)
435 smuPeripheralUSART2 = _SMU_PPUPATD0_USART2_SHIFT, /**< SMU peripheral identifier for USART2 */
436 #endif
437 smuPeripheralBURTC = _SMU_PPUPATD0_BURTC_SHIFT, /**< SMU peripheral identifier for BURTC */
438 #if defined(_SMU_PPUPATD0_I2C1_SHIFT)
439 smuPeripheralI2C1 = _SMU_PPUPATD0_I2C1_SHIFT, /**< SMU peripheral identifier for I2C1 */
440 #endif
441 #if defined(_SMU_PPUPATD0_CHIPTESTCTRL_SHIFT)
442 smuPeripheralCHIPTESTCTRL = _SMU_PPUPATD0_CHIPTESTCTRL_SHIFT, /**< SMU peripheral identifier for CHIPTESTCTRL */
443 #endif
444 #if defined(_SMU_PPUPATD0_SYSCFGCFGNS_SHIFT)
445 smuPeripheralSYSCFGCFGNS = _SMU_PPUPATD0_SYSCFGCFGNS_SHIFT, /**< SMU peripheral identifier for SYSCFGCFGNS */
446 #endif
447
448 #if defined(SMU_PPUPATD0_LVGD)
449 smuPeripheralLVGD = _SMU_PPUPATD0_LVGD_SHIFT, /**< SMU peripheral identifier for LVGD */
450 #endif
451 smuPeripheralSYSCFG = _SMU_PPUPATD0_SYSCFG_SHIFT, /**< SMU peripheral identifier for SYSCFG */
452 #if defined(_SMU_PPUPATD0_BURAM_SHIFT)
453 smuPeripheralBURAM = _SMU_PPUPATD0_BURAM_SHIFT, /**< SMU peripheral identifier for BURAM */
454 #endif
455 #if defined(_SMU_PPUPATD1_BURAM_SHIFT)
456 smuPeripheralBURAM = _SMU_PPUPATD1_BURAM_SHIFT, /**< SMU peripheral identifier for BURAM */
457 #endif
458 #if defined(_SMU_PPUPATD0_IFADCDEBUG_SHIFT)
459 smuPeripheralIFADCDEBUG = _SMU_PPUPATD0_IFADCDEBUG_SHIFT, /**< SMU peripheral identifier for IFADCDEBUG*/
460 #endif
461 #if defined(_SMU_PPUPATD0_GPCRC_SHIFT)
462 smuPeripheralGPCRC = _SMU_PPUPATD0_GPCRC_SHIFT, /**< SMU peripheral identifier for GPCRC */
463 #endif
464 #if defined(_SMU_PPUPATD1_GPCRC_SHIFT)
465 smuPeripheralGPCRC = 32 + _SMU_PPUPATD1_GPCRC_SHIFT, /**< SMU peripheral identifier for GPCRC */
466 #endif
467 #if defined(_SMU_PPUPATD0_DCDC_SHIFT)
468 smuPeripheralDCDC = _SMU_PPUPATD0_DCDC_SHIFT, /**< SMU peripheral identifier for DCDC */
469 #endif
470 #if defined(_SMU_PPUPATD0_RTCC_SHIFT)
471 smuPeripheralRTCC = _SMU_PPUPATD0_RTCC_SHIFT, /**< SMU peripheral identifier for RTCC */
472 #endif
473 #if defined(_SMU_PPUPATD0_HOSTMAILBOX_SHIFT)
474 smuPeripheralHOSTMAILBOX = _SMU_PPUPATD0_HOSTMAILBOX_SHIFT, /**< SMU peripheral identifier for HOSTMAILBOX */
475 #endif
476 #if defined(_SMU_PPUPATD1_EUSART0_SHIFT)
477 smuPeripheralEUSART0 = 32 + _SMU_PPUPATD1_EUSART0_SHIFT, /**< SMU peripheral identifier for EUSART0 */
478 #endif
479 #if defined(_SMU_PPUPATD0_EUSART1_SHIFT)
480 smuPeripheralEUSART1 = _SMU_PPUPATD0_EUSART1_SHIFT, /**< SMU peripheral identifier for EUSART1 */
481 #endif
482 #if defined(_SMU_PPUPATD1_EUSART1_SHIFT)
483 smuPeripheralEUSART1 = 32 + _SMU_PPUPATD1_EUSART1_SHIFT, /**< SMU peripheral identifier for EUSART1 */
484 #endif
485 #if defined(_SMU_PPUPATD0_EUSART2_SHIFT)
486 smuPeripheralEUSART2 = _SMU_PPUPATD0_EUSART2_SHIFT, /**< SMU peripheral identifier for EUSART2 */
487 #endif
488 #if defined(_SMU_PPUPATD1_EUSART2_SHIFT)
489 smuPeripheralEUSART2 = 32 + _SMU_PPUPATD1_EUSART2_SHIFT, /**< SMU peripheral identifier for EUSART2 */
490 #endif
491 #if defined(_SMU_PPUPATD1_EUSART3_SHIFT)
492 smuPeripheralEUSART3 = 32 + _SMU_PPUPATD1_EUSART3_SHIFT, /**< SMU peripheral identifier for EUSART3 */
493 #endif
494 #if defined(_SMU_PPUPATD1_EUSART4_SHIFT)
495 smuPeripheralEUSART4 = 32 + _SMU_PPUPATD1_EUSART4_SHIFT, /**< SMU peripheral identifier for EUSART4 */
496 #endif
497 #if defined(_SMU_PPUPATD1_RTCC_SHIFT)
498 smuPeripheralRTCC = 32 + _SMU_PPUPATD1_RTCC_SHIFT, /**< SMU peripheral identifier for RTCC */
499 #endif
500 #if defined(_SMU_PPUPATD1_SYSRTC_SHIFT)
501 smuPeripheralSYSRTC = 32 + _SMU_PPUPATD1_SYSRTC_SHIFT, /**< SMU peripheral identifier for SYSRTC */
502 #endif
503 #if defined(_SMU_PPUPATD1_LCD_SHIFT)
504 smuPeripheralLCD = 32 + _SMU_PPUPATD1_LCD_SHIFT, /**< SMU peripheral identifier for LCD */
505 #endif
506 #if defined(_SMU_PPUPATD1_KEYSCAN_SHIFT)
507 smuPeripheralKEYSCAN = 32 + _SMU_PPUPATD1_KEYSCAN_SHIFT, /**< SMU peripheral identifier for KEYSCAN */
508 #endif
509 #if defined(_SMU_PPUPATD1_DMEM_SHIFT)
510 smuPeripheralDMEM = 32 + _SMU_PPUPATD1_DMEM_SHIFT, /**< SMU peripheral identifier for DMEM */
511 #endif
512 #if defined(_SMU_PPUPATD1_LCDRF_SHIFT)
513 smuPeripheralLCDRF = 32 + _SMU_PPUPATD1_LCDRF_SHIFT, /**< SMU peripheral identifier for LCDRF */
514 #endif
515 #if defined(_SMU_PPUPATD1_PFMXPPRF_SHIFT)
516 smuPeripheralPFMXPPRF = 32 + _SMU_PPUPATD1_PFMXPPRF_SHIFT, /**< SMU peripheral identifier for PFMXPPRF */
517 #endif
518 #if defined(_SMU_PPUPATD1_RFFPLL0_SHIFT)
519 smuPeripheralRFFPLL0 = 32 + _SMU_PPUPATD1_RFFPLL0_SHIFT, /**< SMU peripheral identifier for RFFPLL0 */
520 #endif
521 #if defined(_SMU_PPUPATD1_ETAMPDET_SHIFT)
522 smuPeripheralETAMPDET = 32 + _SMU_PPUPATD1_ETAMPDET_SHIFT, /**< SMU peripheral identifier for ETAMPDET */
523 #endif
524 #if defined(_SMU_PPUPATD1_VDAC0_SHIFT)
525 smuPeripheralVDAC0 = 32 + _SMU_PPUPATD1_VDAC0_SHIFT, /**< SMU peripheral identifier for VDAC0 */
526 #endif
527 #if defined(_SMU_PPUPATD1_VDAC1_SHIFT)
528 smuPeripheralVDAC1 = 32 + _SMU_PPUPATD1_VDAC1_SHIFT, /**< SMU peripheral identifier for VDAC1 */
529 #endif
530 #if defined(_SMU_PPUPATD1_PCNT_SHIFT)
531 smuPeripheralPCNT = 32 + _SMU_PPUPATD1_PCNT_SHIFT, /**< SMU peripheral identifier for PCNT */
532 #endif
533 #if defined(_SMU_PPUPATD1_LESENSE_SHIFT)
534 smuPeripheralLESENSE = 32 + _SMU_PPUPATD1_LESENSE_SHIFT, /**< SMU peripheral identifier for LESENSE */
535 #endif
536 #if defined(_SMU_PPUPATD1_HFRCO1_SHIFT)
537 smuPeripheralHFRCO1 = 32 + _SMU_PPUPATD1_HFRCO1_SHIFT, /**< SMU peripheral identifier for HFRCO1 */
538 #endif
539 #if defined(_SMU_PPUPATD1_HFXO0_SHIFT)
540 smuPeripheralHFXO0 = 32 + _SMU_PPUPATD1_HFXO0_SHIFT, /**< SMU peripheral identifier for HFXO0 */
541 #endif
542 #if defined(_SMU_PPUPATD1_DCDC_SHIFT)
543 smuPeripheralDCDC = 32 + _SMU_PPUPATD1_DCDC_SHIFT, /**< SMU peripheral identifier for DCDC */
544 #endif
545 #if defined(_SMU_PPUPATD1_PDM_SHIFT)
546 smuPeripheralPDM = 32 + _SMU_PPUPATD1_PDM_SHIFT, /**< SMU peripheral identifier for PDM */
547 #endif
548 #if defined(_SMU_PPUPATD1_RFSENSE_SHIFT)
549 smuPeripheralRFSENSE = 32 + _SMU_PPUPATD1_RFSENSE_SHIFT, /**< SMU peripheral identifier for RFSENSE */
550 #endif
551 #if defined(_SMU_PPUPATD1_SEPUF_SHIFT)
552 smuPeripheralSEPUF = 32 + _SMU_PPUPATD1_SEPUF_SHIFT, /**< SMU peripheral identifier for SEPUF */
553 #endif
554 smuPeripheralLETIMER0 = 32 + _SMU_PPUPATD1_LETIMER0_SHIFT, /**< SMU peripheral identifier for LETIMER */
555 #if defined(_SMU_PPUPATD1_IADC0_SHIFT)
556 smuPeripheralIADC0 = 32 + _SMU_PPUPATD1_IADC0_SHIFT, /**< SMU peripheral identifier for IADC0 */
557 #endif
558 #if defined(_SMU_PPUPATD1_ACMP0_SHIFT)
559 smuPeripheralACMP0 = 32 + _SMU_PPUPATD1_ACMP0_SHIFT, /**< SMU peripheral identifier for ACMP0 */
560 #endif
561 #if defined(_SMU_PPUPATD1_ACMP1_SHIFT)
562 smuPeripheralACMP1 = 32 + _SMU_PPUPATD1_ACMP1_SHIFT, /**< SMU peripheral identifier for ACMP1 */
563 #endif
564 #if defined(_SMU_PPUPATD1_I2C0_SHIFT)
565 smuPeripheralI2C0 = 32 + _SMU_PPUPATD1_I2C0_SHIFT, /**< SMU peripheral identifier for I2C0 */
566 #endif
567 #if defined(_SMU_PPUPATD1_HFRCOEM23_SHIFT)
568 smuPeripheralHFRCOEM23 = 32 + _SMU_PPUPATD1_HFRCOEM23_SHIFT, /**< SMU peripheral identifier for HFRCOEM23 */
569 #endif
570 smuPeripheralWDOG0 = 32 + _SMU_PPUPATD1_WDOG0_SHIFT, /**< SMU peripheral identifier for WDOG0 */
571 #if defined(_SMU_PPUPATD1_WDOG1_SHIFT)
572 smuPeripheralWDOG1 = 32 + _SMU_PPUPATD1_WDOG1_SHIFT, /**< SMU peripheral identifier for WDOG1 */
573 #endif
574 smuPeripheralAMUXCP0 = 32 + _SMU_PPUPATD1_AMUXCP0_SHIFT, /**< SMU peripheral identifier for AMUXCP0 */
575 #if defined(_SMU_PPUPATD1_RADIOAES_SHIFT)
576 smuPeripheralRADIOAES = 32 + _SMU_PPUPATD1_RADIOAES_SHIFT, /**< SMU peripheral identifier for RADIOAES */
577 #endif
578 #if defined(_SMU_PPUPATD1_EUART0_SHIFT)
579 smuPeripheralEUART0 = 32 + _SMU_PPUPATD1_EUART0_SHIFT, /**< SMU peripheral identifier for EUART0 */
580 #endif
581 #if defined(_SMU_PPUPATD1_BUFC_SHIFT)
582 smuPeripheralBUFC = 32 + _SMU_PPUPATD1_BUFC_SHIFT, /**< SMU peripheral identifier for BUFC */
583 #endif
584 smuPeripheralSMU = 32 + _SMU_PPUPATD1_SMU_SHIFT, /**< SMU peripheral identifier for SMU */
585 #if defined(_SMU_PPUPATD1_SMUCFGNS_SHIFT)
586 smuPeripheralSMUCFGNS = 32 + _SMU_PPUPATD1_SMUCFGNS_SHIFT, /**< SMU peripheral identifier for SMUCFGNS */
587 #endif
588 #if defined(_SMU_PPUPATD1_AHBUSBSYS_SHIFT)
589 smuPeripheralAHBUSBSYS = 32 + _SMU_PPUPATD1_AHBUSBSYS_SHIFT, /**< SMU peripheral identifier for AHBUSBSYS */
590 #endif
591 #if defined(_SMU_PPUPATD1_AHBRADIO_SHIFT)
592 smuPeripheralAHBRADIO = 32 + _SMU_PPUPATD1_AHBRADIO_SHIFT, /**< SMU peripheral identifier for AHBRADIO */
593 #endif
594 #if defined(_SMU_PPUPATD1_SEMAILBOX_SHIFT)
595 smuPeripheralSEMAILBOX = 32 + _SMU_PPUPATD1_SEMAILBOX_SHIFT, /**< SMU peripheral identifier for SEMAILBOX */
596 #endif
597 #if defined(_SMU_PPUPATD1_MVP_SHIFT)
598 smuPeripheralMVP = 32 + _SMU_PPUPATD1_MVP_SHIFT, /**< SMU peripheral identifier for MVP */
599 #endif
600 #if defined(_SMU_PPUPATD1_CRYPTOACC_SHIFT)
601 smuPeripheralCRYPTOACC = 32 + _SMU_PPUPATD1_CRYPTOACC_SHIFT, /**< SMU peripheral identifier for CRYPTOACC */
602 #endif
603 #else
604 #error "No peripherals defined for SMU for this device configuration."
605 #endif
606 smuPeripheralEnd /**< SMU peripheral end. */
607 } SMU_Peripheral_TypeDef;
608
609 /** SMU peripheral privileged access enablers. */
610 typedef struct {
611 #if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_84)
612 bool privilegedACMP0 : 1; /**< Privileged access enabler for ACMP0. */
613 bool privilegedACMP1 : 1; /**< Privileged access enabler for ACMP1. */
614 bool privilegedADC0 : 1; /**< Privileged access enabler for ADC0. */
615 bool privilegedReserved0 : 1; /**< Reserved privileged access enabler. */
616 bool privilegedReserved1 : 1; /**< Reserved privileged access enabler. */
617 bool privilegedCMU : 1; /**< Privileged access enabler for CMU. */
618 bool privilegedReserved2 : 1; /**< Reserved privileged access enabler. */
619 bool privilegedCRYOTIMER : 1; /**< Privileged access enabler for CRYOTIMER. */
620 bool privilegedCRYPTO0 : 1; /**< Privileged access enabler for CRYPTO0. */
621 bool privilegedCRYPTO1 : 1; /**< Privileged access enabler for CRYPTO1. */
622 bool privilegedCSEN : 1; /**< Privileged access enabler for CSEN. */
623 bool privilegedVDAC0 : 1; /**< Privileged access enabler for VDAC0. */
624 bool privilegedPRS : 1; /**< Privileged access enabler for PRS. */
625 bool privilegedEMU : 1; /**< Privileged access enabler for EMU. */
626 bool privilegedFPUEH : 1; /**< Privileged access enabler for FPUEH. */
627 bool privilegedReserved3 : 1; /**< Reserved privileged access enabler. */
628 bool privilegedGPCRC : 1; /**< Privileged access enabler for GPCRC. */
629 bool privilegedGPIO : 1; /**< Privileged access enabler for GPIO. */
630 bool privilegedI2C0 : 1; /**< Privileged access enabler for I2C0. */
631 bool privilegedI2C1 : 1; /**< Privileged access enabler for I2C1. */
632 bool privilegedIDAC0 : 1; /**< Privileged access enabler for IDAC0. */
633 bool privilegedMSC : 1; /**< Privileged access enabler for MSC. */
634 bool privilegedLDMA : 1; /**< Privileged access enabler for LDMA. */
635 bool privilegedLESENSE : 1; /**< Privileged access enabler for LESENSE. */
636 bool privilegedLETIMER0 : 1; /**< Privileged access enabler for LETIMER0. */
637 bool privilegedLEUART0 : 1; /**< Privileged access enabler for LEUART0. */
638 bool privilegedReserved4 : 1; /**< Reserved privileged access enabler. */
639 bool privilegedPCNT0 : 1; /**< Privileged access enabler for PCNT0. */
640 bool privilegedPCNT1 : 1; /**< Privileged access enabler for PCNT1. */
641 bool privilegedPCNT2 : 1; /**< Privileged access enabler for PCNT2. */
642 bool privilegedReserved5 : 1; /**< Reserved privileged access enabler. */
643 bool privilegedReserved6 : 1; /**< Reserved privileged access enabler. */
644 bool privilegedReserved7 : 1; /**< Reserved privileged access enabler. */
645 bool privilegedRMU : 1; /**< Privileged access enabler for RMU. */
646 bool privilegedRTCC : 1; /**< Privileged access enabler for RTCC. */
647 bool privilegedSMU : 1; /**< Privileged access enabler for SMU. */
648 bool privilegedReserved8 : 1; /**< Reserved privileged access enabler. */
649 bool privilegedTIMER0 : 1; /**< Privileged access enabler for TIMER0. */
650 bool privilegedTIMER1 : 1; /**< Privileged access enabler for TIMER1. */
651 bool privilegedTRNG0 : 1; /**< Privileged access enabler for TRNG0. */
652 bool privilegedUSART0 : 1; /**< Privileged access enabler for USART0. */
653 bool privilegedUSART1 : 1; /**< Privileged access enabler for USART1. */
654 bool privilegedUSART2 : 1; /**< Privileged access enabler for USART2. */
655 bool privilegedUSART3 : 1; /**< Privileged access enabler for USART3. */
656 bool privilegedWDOG0 : 1; /**< Privileged access enabler for WDOG0. */
657 bool privilegedWDOG1 : 1; /**< Privileged access enabler for WDOG1. */
658 bool privilegedWTIMER0 : 1; /**< Privileged access enabler for WTIMER0. */
659 bool privilegedWTIMER1 : 1; /**< Privileged access enabler for WTIMER1. */
660
661 #elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_89)
662 bool privilegedACMP0 : 1; /**< Privileged access enabler for ACMP0. */
663 bool privilegedACMP1 : 1; /**< Privileged access enabler for ACMP1. */
664 bool privilegedADC0 : 1; /**< Privileged access enabler for ADC0. */
665 bool privilegedReserved0 : 1; /**< Reserved privileged access enabler. */
666 bool privilegedReserved1 : 1; /**< Reserved privileged access enabler. */
667 bool privilegedCMU : 1; /**< Privileged access enabler for CMU. */
668 bool privilegedReserved2 : 1; /**< Reserved privileged access enabler. */
669 bool privilegedCRYOTIMER : 1; /**< Privileged access enabler for CRYOTIMER. */
670 bool privilegedCRYPTO0 : 1; /**< Privileged access enabler for CRYPTO0. */
671 bool privilegedCRYPTO1 : 1; /**< Privileged access enabler for CRYPTO1. */
672 bool privilegedCSEN : 1; /**< Privileged access enabler for CSEN. */
673 bool privilegedVDAC0 : 1; /**< Privileged access enabler for VDAC0. */
674 bool privilegedPRS : 1; /**< Privileged access enabler for PRS. */
675 bool privilegedEMU : 1; /**< Privileged access enabler for EMU. */
676 bool privilegedFPUEH : 1; /**< Privileged access enabler for FPUEH. */
677 bool privilegedReserved3 : 1; /**< Reserved privileged access enabler. */
678 bool privilegedGPCRC : 1; /**< Privileged access enabler for GPCRC. */
679 bool privilegedGPIO : 1; /**< Privileged access enabler for GPIO. */
680 bool privilegedI2C0 : 1; /**< Privileged access enabler for I2C0. */
681 bool privilegedI2C1 : 1; /**< Privileged access enabler for I2C1. */
682 bool privilegedIDAC0 : 1; /**< Privileged access enabler for IDAC0. */
683 bool privilegedMSC : 1; /**< Privileged access enabler for MSC. */
684 bool privilegedLDMA : 1; /**< Privileged access enabler for LDMA. */
685 bool privilegedLESENSE : 1; /**< Privileged access enabler for LESENSE. */
686 bool privilegedLETIMER0 : 1; /**< Privileged access enabler for LETIMER0. */
687 bool privilegedLEUART0 : 1; /**< Privileged access enabler for LEUART0. */
688 bool privilegedReserved4 : 1; /**< Reserved privileged access enabler. */
689 bool privilegedPCNT0 : 1; /**< Privileged access enabler for PCNT0. */
690 bool privilegedReserved5 : 1; /**< Reserved privileged access enabler. */
691 bool privilegedReserved6 : 1; /**< Reserved privileged access enabler. */
692 bool privilegedReserved7 : 1; /**< Reserved privileged access enabler. */
693 bool privilegedReserved8 : 1; /**< Reserved privileged access enabler. */
694 bool privilegedRMU : 1; /**< Privileged access enabler for RMU. */
695 bool privilegedRTCC : 1; /**< Privileged access enabler for RTCC. */
696 bool privilegedSMU : 1; /**< Privileged access enabler for SMU. */
697 bool privilegedReserved9 : 1; /**< Reserved privileged access enabler. */
698 bool privilegedTIMER0 : 1; /**< Privileged access enabler for TIMER0. */
699 bool privilegedTIMER1 : 1; /**< Privileged access enabler for TIMER1. */
700 bool privilegedTRNG0 : 1; /**< Privileged access enabler for TRNG0. */
701 bool privilegedUSART0 : 1; /**< Privileged access enabler for USART0. */
702 bool privilegedUSART1 : 1; /**< Privileged access enabler for USART1. */
703 bool privilegedUSART2 : 1; /**< Privileged access enabler for USART2. */
704 bool privilegedWDOG0 : 1; /**< Privileged access enabler for WDOG0. */
705 bool privilegedWDOG1 : 1; /**< Privileged access enabler for WDOG1. */
706 bool privilegedWTIMER0 : 1; /**< Privileged access enabler for WTIMER0. */
707
708 #elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_95)
709 bool privilegedACMP0 : 1; /**< Privileged access enabler for ACMP0. */
710 bool privilegedACMP1 : 1; /**< Privileged access enabler for ACMP1. */
711 bool privilegedADC0 : 1; /**< Privileged access enabler for ADC0. */
712 bool privilegedReserved0 : 1; /**< Reserved privileged access enabler. */
713 bool privilegedReserved1 : 1; /**< Reserved privileged access enabler. */
714 bool privilegedCMU : 1; /**< Privileged access enabler for CMU. */
715 bool privilegedReserved2 : 1; /**< Reserved privileged access enabler. */
716 bool privilegedCRYOTIMER : 1; /**< Privileged access enabler for CRYOTIMER. */
717 bool privilegedCRYPTO : 1; /**< Privileged access enabler for CRYPTO. */
718 bool privilegedVDAC0 : 1; /**< Privileged access enabler for VDAC0. */
719 bool privilegedPRS : 1; /**< Privileged access enabler for PRS. */
720 bool privilegedEMU : 1; /**< Privileged access enabler for EMU. */
721 bool privilegedFPUEH : 1; /**< Privileged access enabler for FPUEH. */
722 bool privilegedReserved3 : 1; /**< Reserved privileged access enabler. */
723 bool privilegedGPCRC : 1; /**< Privileged access enabler for GPCRC. */
724 bool privilegedGPIO : 1; /**< Privileged access enabler for GPIO. */
725 bool privilegedI2C0 : 1; /**< Privileged access enabler for I2C0. */
726 bool privilegedIDAC0 : 1; /**< Privileged access enabler for IDAC0. */
727 bool privilegedMSC : 1; /**< Privileged access enabler for MSC. */
728 bool privilegedLDMA : 1; /**< Privileged access enabler for LDMA. */
729 bool privilegedLESENSE : 1; /**< Privileged access enabler for LESENSE. */
730 bool privilegedLETIMER0 : 1; /**< Privileged access enabler for LETIMER0. */
731 bool privilegedLEUART : 1; /**< Privileged access enabler for LEUART0. */
732 bool privilegedReserved4 : 1; /**< Reserved privileged access enabler. */
733 bool privilegedPCNT0 : 1; /**< Privileged access enabler for PCNT0. */
734 bool privilegedReserved5 : 1; /**< Reserved privileged access enabler. */
735 bool privilegedReserved6 : 1; /**< Reserved privileged access enabler. */
736 bool privilegedReserved7 : 1; /**< Reserved privileged access enabler. */
737 bool privilegedReserved8 : 1; /**< Reserved privileged access enabler. */
738 bool privilegedRMU : 1; /**< Privileged access enabler for RMU. */
739 bool privilegedRTCC : 1; /**< Privileged access enabler for RTCC. */
740 bool privilegedSMU : 1; /**< Privileged access enabler for SMU. */
741
742 bool privilegedReserved9 : 1; /**< Reserved privileged access enabler. */
743 bool privilegedTIMER0 : 1; /**< Privileged access enabler for TIMER0. */
744 bool privilegedTIMER1 : 1; /**< Privileged access enabler for TIMER1. */
745 bool privilegedTRNG0 : 1; /**< Privileged access enabler for TRNG0. */
746 bool privilegedUSART0 : 1; /**< Privileged access enabler for USART0. */
747 bool privilegedUSART1 : 1; /**< Privileged access enabler for USART1. */
748 bool privilegedWDOG0 : 1; /**< Privileged access enabler for WDOG0. */
749 bool privilegedWDOG1 : 1; /**< Privileged access enabler for WDOG1. */
750 bool privilegedWTIMER0 : 1; /**< Privileged access enabler for WTIMER0. */
751
752 #elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_100)
753 bool privilegedACMP0 : 1; /**< Privileged access enabler for ACMP0. */
754 bool privilegedACMP1 : 1; /**< Privileged access enabler for ACMP1. */
755 bool privilegedACMP2 : 1; /**< Privileged access enabler for ACMP2. */
756 bool privilegedACMP3 : 1; /**< Privileged access enabler for ACMP3. */
757 bool privilegedADC0 : 1; /**< Privileged access enabler for ADC0. */
758 bool privilegedADC1 : 1; /**< Privileged access enabler for ADC1. */
759 bool privilegedCAN0 : 1; /**< Privileged access enabler for CAN0. */
760 bool privilegedCAN1 : 1; /**< Privileged access enabler for CAN1. */
761 bool privilegedCMU : 1; /**< Privileged access enabler for CMU. */
762 bool privilegedCRYOTIMER : 1; /**< Privileged access enabler for CRYOTIMER. */
763 bool privilegedCRYPTO0 : 1; /**< Privileged access enabler for CRYPTO0. */
764 bool privilegedCSEN : 1; /**< Privileged access enabler for CSEN. */
765 bool privilegedVDAC0 : 1; /**< Privileged access enabler for VDAC0. */
766 bool privilegedPRS : 1; /**< Privileged access enabler for PRS. */
767 bool privilegedEBI : 1; /**< Privileged access enabler for EBI. */
768 bool privilegedEMU : 1; /**< Privileged access enabler for EMU. */
769 bool privilegedETH : 1; /**< Privileged access enabler for ETH. */
770 bool privilegedFPUEH : 1; /**< Privileged access enabler for FPUEH. */
771 bool privilegedGPCRC : 1; /**< Privileged access enabler for GPCRC. */
772 bool privilegedGPIO : 1; /**< Privileged access enabler for GPIO. */
773 bool privilegedI2C0 : 1; /**< Privileged access enabler for I2C0. */
774 bool privilegedI2C1 : 1; /**< Privileged access enabler for I2C1. */
775 bool privilegedI2C2 : 1; /**< Privileged access enabler for I2C2. */
776 bool privilegedIDAC0 : 1; /**< Privileged access enabler for IDAC0. */
777 bool privilegedMSC : 1; /**< Privileged access enabler for MAC. */
778 bool privilegedLCD : 1; /**< Privileged access enabler for LCD. */
779 bool privilegedLDMA : 1; /**< Privileged access enabler for LDMA. */
780 bool privilegedLESENSE : 1; /**< Privileged access enabler for LESENSE. */
781 bool privilegedLETIMER0 : 1; /**< Privileged access enabler for LETIMER0. */
782 bool privilegedLETIMER1 : 1; /**< Privileged access enabler for LETIMER1. */
783 bool privilegedLEUART0 : 1; /**< Privileged access enabler for LEUART0. */
784 bool privilegedLEUART1 : 1; /**< Privileged access enabler for LEUART1. */
785 bool privilegedPCNT0 : 1; /**< Privileged access enabler for PCNT0. */
786 bool privilegedPCNT1 : 1; /**< Privileged access enabler for PCNT1. */
787 bool privilegedPCNT2 : 1; /**< Privileged access enabler for PCNT2. */
788 bool privilegedQSPI0 : 1; /**< Privileged access enabler for QSPI0. */
789 bool privilegedRMU : 1; /**< Privileged access enabler for RMU. */
790 bool privilegedRTC : 1; /**< Privileged access enabler for RTC. */
791 bool privilegedRTCC : 1; /**< Privileged access enabler for RTCC. */
792 bool privilegedSDIO : 1; /**< Privileged access enabler for SDIO. */
793 bool privilegedSMU : 1; /**< Privileged access enabler for SMU. */
794 bool privilegedTIMER0 : 1; /**< Privileged access enabler for TIMER0. */
795 bool privilegedTIMER1 : 1; /**< Privileged access enabler for TIMER1. */
796 bool privilegedTIMER2 : 1; /**< Privileged access enabler for TIMER2. */
797 bool privilegedTIMER3 : 1; /**< Privileged access enabler for TIMER3. */
798 bool privilegedTIMER4 : 1; /**< Privileged access enabler for TIMER4. */
799 bool privilegedTIMER5 : 1; /**< Privileged access enabler for TIMER5. */
800 bool privilegedTIMER6 : 1; /**< Privileged access enabler for TIMER6. */
801 bool privilegedTRNG0 : 1; /**< Privileged access enabler for TRNG0. */
802 bool privilegedUART0 : 1; /**< Privileged access enabler for UART0. */
803 bool privilegedUART1 : 1; /**< Privileged access enabler for UART1. */
804 bool privilegedUSART0 : 1; /**< Privileged access enabler for USART0. */
805 bool privilegedUSART1 : 1; /**< Privileged access enabler for USART1. */
806 bool privilegedUSART2 : 1; /**< Privileged access enabler for USART2. */
807 bool privilegedUSART3 : 1; /**< Privileged access enabler for USART3. */
808 bool privilegedUSART4 : 1; /**< Privileged access enabler for USART4. */
809 bool privilegedUSART5 : 1; /**< Privileged access enabler for USART5. */
810 bool privilegedUSB : 1; /**< Privileged access enabler for USB. */
811 bool privilegedWDOG0 : 1; /**< Privileged access enabler for WDOG0. */
812 bool privilegedWDOG1 : 1; /**< Privileged access enabler for WDOG1. */
813 bool privilegedWTIMER0 : 1; /**< Privileged access enabler for WTIMER0. */
814 bool privilegedWTIMER1 : 1; /**< Privileged access enabler for WTIMER1. */
815 bool privilegedWTIMER2 : 1; /**< Privileged access enabler for WTIMER2. */
816 bool privilegedWTIMER3 : 1; /**< Privileged access enabler for WTIMER3. */
817
818 #elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_103)
819 bool privilegedACMP0 : 1; /**< Privileged access enabler for ACMP0. */
820 bool privilegedACMP1 : 1; /**< Privileged access enabler for ACMP1. */
821 bool privilegedADC0 : 1; /**< Privileged access enabler for ADC0. */
822 bool privilegedCAN0 : 1; /**< Privileged access enabler for CAN0. */
823 bool privilegedCMU : 1; /**< Privileged access enabler for CMU. */
824 bool privilegedCRYOTIMER : 1; /**< Privileged access enabler for CRYOTIMER. */
825 bool privilegedCRYPTO0 : 1; /**< Privileged access enabler for CRYPTO0. */
826 bool privilegedCSEN : 1; /**< Privileged access enabler for CSEN. */
827 bool privilegedVDAC0 : 1; /**< Privileged access enabler for VDAC0. */
828 bool privilegedPRS : 1; /**< Privileged access enabler for PRS. */
829 bool privilegedEMU : 1; /**< Privileged access enabler for EMU. */
830 bool privilegedGPCRC : 1; /**< Privileged access enabler for GPCRC. */
831 bool privilegedGPIO : 1; /**< Privileged access enabler for GPIO. */
832 bool privilegedI2C0 : 1; /**< Privileged access enabler for I2C0. */
833 bool privilegedI2C1 : 1; /**< Privileged access enabler for I2C1. */
834 bool privilegedMSC : 1; /**< Privileged access enabler for MAC. */
835 bool privilegedLCD : 1; /**< Privileged access enabler for LCD. */
836 bool privilegedLDMA : 1; /**< Privileged access enabler for LDMA. */
837 bool privilegedLESENSE : 1; /**< Privileged access enabler for LESENSE. */
838 bool privilegedLETIMER0 : 1; /**< Privileged access enabler for LETIMER0. */
839 bool privilegedLEUART0 : 1; /**< Privileged access enabler for LEUART0. */
840 bool privilegedPCNT0 : 1; /**< Privileged access enabler for PCNT0. */
841 bool privilegedRMU : 1; /**< Privileged access enabler for RMU. */
842 bool privilegedRTCC : 1; /**< Privileged access enabler for RTCC. */
843 bool privilegedSMU : 1; /**< Privileged access enabler for SMU. */
844 bool privilegedTIMER0 : 1; /**< Privileged access enabler for TIMER0. */
845 bool privilegedTIMER1 : 1; /**< Privileged access enabler for TIMER1. */
846 bool privilegedTRNG0 : 1; /**< Privileged access enabler for TRNG0. */
847 bool privilegedUART0 : 1; /**< Privileged access enabler for UART0. */
848 bool privilegedUSART0 : 1; /**< Privileged access enabler for USART0. */
849 bool privilegedUSART1 : 1; /**< Privileged access enabler for USART1. */
850 bool privilegedUSART2 : 1; /**< Privileged access enabler for USART2. */
851 bool privilegedUSART3 : 1; /**< Privileged access enabler for USART3. */
852 bool privilegedWDOG0 : 1; /**< Privileged access enabler for WDOG0. */
853 bool privilegedWTIMER0 : 1; /**< Privileged access enabler for WTIMER0. */
854 bool privilegedWTIMER1 : 1; /**< Privileged access enabler for WTIMER1. */
855
856 #elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_106)
857 bool privilegedACMP0 : 1; /**< Privileged access enabler for ACMP0. */
858 bool privilegedACMP1 : 1; /**< Privileged access enabler for ACMP1. */
859 bool privilegedACMP2 : 1; /**< Privileged access enabler for ACMP2. */
860 bool privilegedADC0 : 1; /**< Privileged access enabler for ADC0. */
861 bool privilegedADC1 : 1; /**< Privileged access enabler for ADC1. */
862 bool privilegedCAN0 : 1; /**< Privileged access enabler for CAN0. */
863 bool privilegedCAN1 : 1; /**< Privileged access enabler for CAN1. */
864 bool privilegedCMU : 1; /**< Privileged access enabler for CMU. */
865 bool privilegedCRYOTIMER : 1; /**< Privileged access enabler for CRYOTIMER. */
866 bool privilegedCRYPTO0 : 1; /**< Privileged access enabler for CRYPTO0. */
867 bool privilegedCSEN : 1; /**< Privileged access enabler for CSEN. */
868 bool privilegedVDAC0 : 1; /**< Privileged access enabler for VDAC0. */
869 bool privilegedPRS : 1; /**< Privileged access enabler for PRS. */
870 bool privilegedEBI : 1; /**< Privileged access enabler for EBI. */
871 bool privilegedEMU : 1; /**< Privileged access enabler for EMU. */
872 bool privilegedFPUEH : 1; /**< Privileged access enabler for FPUEH. */
873 bool privilegedGPCRC : 1; /**< Privileged access enabler for GPCRC. */
874 bool privilegedGPIO : 1; /**< Privileged access enabler for GPIO. */
875 bool privilegedI2C0 : 1; /**< Privileged access enabler for I2C0. */
876 bool privilegedI2C1 : 1; /**< Privileged access enabler for I2C1. */
877 bool privilegedIDAC0 : 1; /**< Privileged access enabler for IDAC0. */
878 bool privilegedMSC : 1; /**< Privileged access enabler for MAC. */
879 bool privilegedLCD : 1; /**< Privileged access enabler for LCD. */
880 bool privilegedLDMA : 1; /**< Privileged access enabler for LDMA. */
881 bool privilegedLESENSE : 1; /**< Privileged access enabler for LESENSE. */
882 bool privilegedLETIMER0 : 1; /**< Privileged access enabler for LETIMER0. */
883 bool privilegedLETIMER1 : 1; /**< Privileged access enabler for LETIMER1. */
884 bool privilegedLEUART0 : 1; /**< Privileged access enabler for LEUART0. */
885 bool privilegedLEUART1 : 1; /**< Privileged access enabler for LEUART1. */
886 bool privilegedReserved0 : 1; /**< Reserved privileged access enabler. */
887 bool privilegedReserved1 : 1; /**< Reserved privileged access enabler. */
888 bool privilegedReserved2 : 1; /**< Reserved privileged access enabler. */
889 bool privilegedPCNT0 : 1; /**< Privileged access enabler for PCNT0. */
890 bool privilegedPCNT1 : 1; /**< Privileged access enabler for PCNT1. */
891 bool privilegedPCNT2 : 1; /**< Privileged access enabler for PCNT2. */
892 bool privilegedPDM : 1; /**< Privileged access enabler for PDM. */
893 bool privilegedQSPI0 : 1; /**< Privileged access enabler for QSPI0. */
894 bool privilegedRMU : 1; /**< Privileged access enabler for RMU. */
895 bool privilegedRTC : 1; /**< Privileged access enabler for RTC. */
896 bool privilegedRTCC : 1; /**< Privileged access enabler for RTCC. */
897 bool privilegedSDIO : 1; /**< Privileged access enabler for SDIO. */
898 bool privilegedSMU : 1; /**< Privileged access enabler for SMU. */
899 bool privilegedTIMER0 : 1; /**< Privileged access enabler for TIMER0. */
900 bool privilegedTIMER1 : 1; /**< Privileged access enabler for TIMER1. */
901 bool privilegedTIMER2 : 1; /**< Privileged access enabler for TIMER2. */
902 bool privilegedTIMER3 : 1; /**< Privileged access enabler for TIMER3. */
903 bool privilegedTRNG0 : 1; /**< Privileged access enabler for TRNG0. */
904 bool privilegedUART0 : 1; /**< Privileged access enabler for UART0. */
905 bool privilegedUART1 : 1; /**< Privileged access enabler for UART1. */
906 bool privilegedUSART0 : 1; /**< Privileged access enabler for USART0. */
907 bool privilegedUSART1 : 1; /**< Privileged access enabler for USART1. */
908 bool privilegedUSART2 : 1; /**< Privileged access enabler for USART2. */
909 bool privilegedUSART3 : 1; /**< Privileged access enabler for USART3. */
910 bool privilegedUSART4 : 1; /**< Privileged access enabler for USART4. */
911 bool privilegedUSB : 1; /**< Privileged access enabler for USB. */
912 bool privilegedWDOG0 : 1; /**< Privileged access enabler for WDOG0. */
913 bool privilegedWDOG1 : 1; /**< Privileged access enabler for WDOG1. */
914 bool privilegedWTIMER0 : 1; /**< Privileged access enabler for WTIMER0. */
915 bool privilegedWTIMER1 : 1; /**< Privileged access enabler for WTIMER1. */
916
917 #elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_1)
918 bool privilegedReserved0 : 1; /**< Reserved privileged access enabler. */
919 bool privilegedEMU : 1; /**< Privileged access enabler for EMU */
920 bool privilegedCMU : 1; /**< Privileged access enabler for CMU */
921 bool privilegedHFXO0 : 1; /**< Privileged access enabler for HFXO0 */
922 bool privilegedHFRCO0 : 1; /**< Privileged access enabler for HFRCO0 */
923 bool privilegedFSRCO : 1; /**< Privileged access enabler for FSRCO */
924 bool privilegedDPLL0 : 1; /**< Privileged access enabler for DPLL0 */
925 bool privilegedLFXO : 1; /**< Privileged access enabler for LFXO */
926 bool privilegedLFRCO : 1; /**< Privileged access enabler for LFRCO */
927 bool privilegedULFRCO : 1; /**< Privileged access enabler for ULFRCO */
928 bool privilegedMSC : 1; /**< Privileged access enabler for MSC */
929 bool privilegedICACHE0 : 1; /**< Privileged access enabler for ICACHE0 */
930 bool privilegedPRS : 1; /**< Privileged access enabler for PRS */
931 bool privilegedGPIO : 1; /**< Privileged access enabler for GPIO */
932 bool privilegedLDMA : 1; /**< Privileged access enabler for LDMA */
933 bool privilegedLDMAXBAR : 1; /**< Privileged access enabler for LDMAXBAR */
934 bool privilegedTIMER0 : 1; /**< Privileged access enabler for TIMER0 */
935 bool privilegedTIMER1 : 1; /**< Privileged access enabler for TIMER1 */
936 bool privilegedTIMER2 : 1; /**< Privileged access enabler for TIMER2 */
937 bool privilegedTIMER3 : 1; /**< Privileged access enabler for TIMER3 */
938 bool privilegedUSART0 : 1; /**< Privileged access enabler for USART0 */
939 bool privilegedUSART1 : 1; /**< Privileged access enabler for USART1 */
940 bool privilegedUSART2 : 1; /**< Privileged access enabler for USART2 */
941 bool privilegedBURTC : 1; /**< Privileged access enabler for BURTC */
942 bool privilegedI2C1 : 1; /**< Privileged access enabler for I2C1 */
943 bool privilegedCHIPTESTCTRL : 1; /**< Privileged access enabler for CHIPTESTCTRL */
944 bool privilegedLVGD : 1; /**< Privileged access enabler for LVGD */
945 bool privilegedSYSCFG : 1; /**< Privileged access enabler for SYSCFG */
946 bool privilegedBURAM : 1; /**< Privileged access enabler for BURAM */
947 bool privilegedIFADCDEBUG : 1; /**< Privileged access enabler for IFADCDEBUG */
948 bool privilegedGPCRC : 1; /**< Privileged access enabler for GPCRC */
949 bool privilegedRTCC : 1; /**< Privileged access enabler for RTCC */
950
951 bool privilegedLETIMER0 : 1; /**< Privileged access enabler for LETIMER */
952 bool privilegedIADC0 : 1; /**< Privileged access enabler for IADC0 */
953 bool privilegedACMP0 : 1; /**< Privileged access enabler for ACMP0 */
954 bool privilegedACMP1 : 1; /**< Privileged access enabler for ACMP1 */
955 bool privilegedI2C0 : 1; /**< Privileged access enabler for I2C0 */
956 bool privilegedHFRCOEM23 : 1; /**< Privileged access enabler for HFRCOEM23 */
957 bool privilegedWDOG0 : 1; /**< Privileged access enabler for WDOG0 */
958 bool privilegedWDOG1 : 1; /**< Privileged access enabler for WDOG1 */
959 bool privilegedAMUXCP0 : 1; /**< Privileged access enabler for AMUXCP0 */
960 bool privilegedRADIOAES : 1; /**< Privileged access enabler for RADIOAES */
961 bool privilegedBUFC : 1; /**< Privileged access enabler for BUFC */
962 bool privilegedSMU : 1; /**< Privileged access enabler for SMU */
963 bool privilegedAHBRADIO : 1; /**< Privileged access enabler for AHBRADIO */
964 bool privilegedSEMAILBOX : 1; /**< Privileged access enabler for SEMAILBOX */
965
966 #elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_2)
967 bool privilegedSCRATCHPAD : 1; /**< Privileged access enabler for SCRATCHPAD */
968 bool privilegedEMU : 1; /**< Privileged access enabler for EMU */
969 bool privilegedCMU : 1; /**< Privileged access enabler for CMU */
970 bool privilegedHFXO0 : 1; /**< Privileged access enabler for HFXO0 */
971 bool privilegedHFRCO0 : 1; /**< Privileged access enabler for HFRCO0 */
972 bool privilegedFSRCO : 1; /**< Privileged access enabler for FSRCO */
973 bool privilegedDPLL0 : 1; /**< Privileged access enabler for DPLL0 */
974 bool privilegedLFXO : 1; /**< Privileged access enabler for LFXO */
975 bool privilegedLFRCO : 1; /**< Privileged access enabler for LFRCO */
976 bool privilegedULFRCO : 1; /**< Privileged access enabler for ULFRCO */
977 bool privilegedMSC : 1; /**< Privileged access enabler for MSC */
978 bool privilegedICACHE0 : 1; /**< Privileged access enabler for ICACHE0 */
979 bool privilegedPRS : 1; /**< Privileged access enabler for PRS0 */
980 bool privilegedGPIO : 1; /**< Privileged access enabler for GPIO */
981 bool privilegedLDMA : 1; /**< Privileged access enabler for LDMA */
982 bool privilegedLDMAXBAR : 1; /**< Privileged access enabler for LDMAXBAR */
983 bool privilegedTIMER0 : 1; /**< Privileged access enabler for TIMER0 */
984 bool privilegedTIMER1 : 1; /**< Privileged access enabler for TIMER1 */
985 bool privilegedTIMER2 : 1; /**< Privileged access enabler for TIMER2 */
986 bool privilegedTIMER3 : 1; /**< Privileged access enabler for TIMER3 */
987 bool privilegedTIMER4 : 1; /**< Privileged access enabler for TIMER4 */
988 bool privilegedUSART0 : 1; /**< Privileged access enabler for USART0 */
989 bool privilegedUSART1 : 1; /**< Privileged access enabler for USART1 */
990 bool privilegedBURTC : 1; /**< Privileged access enabler for BURTC */
991 bool privilegedI2C1 : 1; /**< Privileged access enabler for I2C1 */
992 bool privilegedCHIPTESTCTRL : 1; /**< Privileged access enabler for CHIPTESTCTRL */
993 bool privilegedSYSCFGCFGNS : 1; /**< Privileged access enabler for SYSCFGCFGNS */
994 bool privilegedSYSCFG : 1; /**< Privileged access enabler for SYSCFG */
995 bool privilegedBURAM : 1; /**< Privileged access enabler for BURAM */
996 bool privilegedIFADCDEBUG : 1; /**< Privileged access enabler for IFADCDEBUG */
997 bool privilegedGPCRC : 1; /**< Privileged access enabler for GPCRC */
998 bool privilegedDCI : 1; /**< Privileged access enabler for DCI */
999
1000 bool privilegedROOTCFG : 1; /**< Privileged access enabler for ROOTCFG */
1001 bool privilegedDCDC : 1; /**< Privileged access enabler for DCDC */
1002 bool privilegedPDM : 1; /**< Privileged access enabler for PDM */
1003 bool privilegedRFSENSE : 1; /**< Privileged access enabler for RFSENSE */
1004 bool privilegedRADIOAES : 1; /**< Privileged access enabler for RADIOAES */
1005 bool privilegedSMU : 1; /**< Privileged access enabler for SMU */
1006 bool privilegedSMUCFGNS : 1; /**< Privileged access enabler for SMUCFGNS */
1007 bool privilegedRTCC : 1; /**< Privileged access enabler for RTCC */
1008 bool privilegedLETIMER0 : 1; /**< Privileged access enabler for LETIMER0 */
1009 bool privilegedIADC0 : 1; /**< Privileged access enabler for IADC0 */
1010 bool privilegedI2C0 : 1; /**< Privileged access enabler for I2C0 */
1011 bool privilegedWDOG0 : 1; /**< Privileged access enabler for WDOG0 */
1012 bool privilegedAMUXCP0 : 1; /**< Privileged access enabler for AMUXCP0 */
1013 bool privilegedEUART0 : 1; /**< Privileged access enabler for EUART0 */
1014 bool privilegedCRYPTOACC : 1; /**< Privileged access enabler for CRYPTOACC */
1015 bool privilegedAHBRADIO : 1; /**< Privileged access enabler for AHBRADIO */
1016
1017 #elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_3)
1018 bool privilegedReserved0 : 1; /**< Reserved privileged access enabler */
1019 bool privilegedEMU : 1; /**< Privileged access enabler for EMU */
1020 bool privilegedCMU : 1; /**< Privileged access enabler for CMU */
1021 bool privilegedHFRCO0 : 1; /**< Privileged access enabler for HFRCO0 */
1022 bool privilegedFSRCO : 1; /**< Privileged access enabler for FSRCO */
1023 bool privilegedDPLL0 : 1; /**< Privileged access enabler for DPLL0 */
1024 bool privilegedLFXO : 1; /**< Privileged access enabler for LFXO */
1025 bool privilegedLFRCO : 1; /**< Privileged access enabler for LFRCO */
1026 bool privilegedULFRCO : 1; /**< Privileged access enabler for ULFRCO */
1027 bool privilegedMSC : 1; /**< Privileged access enabler for MSC */
1028 bool privilegedICACHE0 : 1; /**< Privileged access enabler for ICACHE0 */
1029 bool privilegedPRS : 1; /**< Privileged access enabler for PRS0 */
1030 bool privilegedGPIO : 1; /**< Privileged access enabler for GPIO */
1031 bool privilegedLDMA : 1; /**< Privileged access enabler for LDMA */
1032 bool privilegedLDMAXBAR : 1; /**< Privileged access enabler for LDMAXBAR */
1033 bool privilegedTIMER0 : 1; /**< Privileged access enabler for TIMER0 */
1034 bool privilegedTIMER1 : 1; /**< Privileged access enabler for TIMER1 */
1035 bool privilegedTIMER2 : 1; /**< Privileged access enabler for TIMER2 */
1036 bool privilegedTIMER3 : 1; /**< Privileged access enabler for TIMER3 */
1037 bool privilegedTIMER4 : 1; /**< Privileged access enabler for TIMER4 */
1038 bool privilegedUSART0 : 1; /**< Privileged access enabler for USART0 */
1039 bool privilegedBURTC : 1; /**< Privileged access enabler for BURTC */
1040 bool privilegedI2C1 : 1; /**< Privileged access enabler for I2C1 */
1041 bool privilegedCHIPTESTCTRL : 1; /**< Privileged access enabler for CHIPTESTCTRL */
1042 bool privilegedSYSCFGCFGNS : 1; /**< Privileged access enabler for SYSCFGCFGNS */
1043 bool privilegedSYSCFG : 1; /**< Privileged access enabler for SYSCFG */
1044 bool privilegedBURAM : 1; /**< Privileged access enabler for BURAM */
1045 bool privilegedGPCRC : 1; /**< Privileged access enabler for GPCRC */
1046 bool privilegedDCDC : 1; /**< Privileged access enabler for DCDC */
1047 bool privilegedHOSTMAILBOX : 1; /**< Privileged access enabler for HOSTMAILBOX */
1048 bool privilegedEUSART1 : 1; /**< Privileged access enabler for EUSART1 */
1049 bool privilegedEUSART2 : 1; /**< Privileged access enabler for EUSART2 */
1050
1051 bool privilegedSYSRTC : 1; /**< Privileged access enabler for SYSRTC */
1052 bool privilegedLCD : 1; /**< Privileged access enabler for LCD */
1053 bool privilegedKEYSCAN : 1; /**< Privileged access enabler for KEYSCAN */
1054 bool privilegedDMEM : 1; /**< Privileged access enabler for DMEM */
1055 bool privilegedLCDRF : 1; /**< Privileged access enabler for LCDRF */
1056 bool privilegedPFMXPPRF : 1; /**< Privileged access enabler for PFMXPPRF */
1057 bool privilegedRADIOAES : 1; /**< Privileged access enabler for RADIOAES */
1058 bool privilegedSMU : 1; /**< Privileged access enabler for SMU */
1059 bool privilegedSMUCFGNS : 1; /**< Privileged access enabler for SMUCFGNS */
1060 bool privilegedLETIMER0 : 1; /**< Privileged access enabler for LETIMER0 */
1061 bool privilegedIADC0 : 1; /**< Privileged access enabler for IADC0 */
1062 bool privilegedACMP0 : 1; /**< Privileged access enabler for ACMP0 */
1063 bool privilegedACMP1 : 1; /**< Privileged access enabler for ACMP1 */
1064 bool privilegedAMUXCP0 : 1; /**< Privileged access enabler for AMUXCP0 */
1065 bool privilegedVDAC0 : 1; /**< Privileged access enabler for VDAC0 */
1066 bool privilegedPCNT : 1; /**< Privileged access enabler for PCNT */
1067 bool privilegedLESENSE : 1; /**< Privileged access enabler for LESENSE */
1068 bool privilegedHFRCO1 : 1; /**< Privileged access enabler for HFRCO1 */
1069 bool privilegedHFXO0 : 1; /**< Privileged access enabler for HFXO0 */
1070 bool privilegedI2C0 : 1; /**< Privileged access enabler for I2C0 */
1071 bool privilegedWDOG0 : 1; /**< Privileged access enabler for WDOG0 */
1072 bool privilegedWDOG1 : 1; /**< Privileged access enabler for WDOG1 */
1073 bool privilegedEUSART0 : 1; /**< Privileged access enabler for EUSART0 */
1074 bool privilegedSEMAILBOX : 1; /**< Privileged access enabler for SEMAILBOX */
1075 bool privilegedAHBRADIO : 1; /**< Privileged access enabler for AHBRADIO */
1076
1077 #elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_4)
1078 bool privilegedReserved0 : 1; /**< Reserved privileged access enabler */
1079 bool privilegedEMU : 1; /**< Privileged access enabler for EMU */
1080 bool privilegedCMU : 1; /**< Privileged access enabler for CMU */
1081 bool privilegedHFRCO0 : 1; /**< Privileged access enabler for HFRCO0 */
1082 bool privilegedFSRCO : 1; /**< Privileged access enabler for FSRCO */
1083 bool privilegedDPLL0 : 1; /**< Privileged access enabler for DPLL0 */
1084 bool privilegedLFXO : 1; /**< Privileged access enabler for LFXO */
1085 bool privilegedLFRCO : 1; /**< Privileged access enabler for LFRCO */
1086 bool privilegedULFRCO : 1; /**< Privileged access enabler for ULFRCO */
1087 bool privilegedMSC : 1; /**< Privileged access enabler for MSC */
1088 bool privilegedICACHE0 : 1; /**< Privileged access enabler for ICACHE0 */
1089 bool privilegedPRS : 1; /**< Privileged access enabler for PRS0 */
1090 bool privilegedGPIO : 1; /**< Privileged access enabler for GPIO */
1091 bool privilegedLDMA : 1; /**< Privileged access enabler for LDMA */
1092 bool privilegedLDMAXBAR : 1; /**< Privileged access enabler for LDMAXBAR */
1093 bool privilegedTIMER0 : 1; /**< Privileged access enabler for TIMER0 */
1094 bool privilegedTIMER1 : 1; /**< Privileged access enabler for TIMER1 */
1095 bool privilegedTIMER2 : 1; /**< Privileged access enabler for TIMER2 */
1096 bool privilegedTIMER3 : 1; /**< Privileged access enabler for TIMER3 */
1097 bool privilegedTIMER4 : 1; /**< Privileged access enabler for TIMER4 */
1098 bool privilegedUSART0 : 1; /**< Privileged access enabler for USART0 */
1099 bool privilegedBURTC : 1; /**< Privileged access enabler for BURTC */
1100 bool privilegedI2C1 : 1; /**< Privileged access enabler for I2C1 */
1101 bool privilegedCHIPTESTCTRL : 1; /**< Privileged access enabler for CHIPTESTCTRL */
1102 bool privilegedSYSCFGCFGNS : 1; /**< Privileged access enabler for SYSCFGCFGNS */
1103 bool privilegedSYSCFG : 1; /**< Privileged access enabler for SYSCFG */
1104 bool privilegedBURAM : 1; /**< Privileged access enabler for BURAM */
1105 bool privilegedGPCRC : 1; /**< Privileged access enabler for GPCRC */
1106 bool privilegedDCDC : 1; /**< Privileged access enabler for DCDC */
1107 bool privilegedHOSTMAILBOX : 1; /**< Privileged access enabler for HOSTMAILBOX */
1108 bool privilegedEUSART1 : 1; /**< Privileged access enabler for EUSART1 */
1109 bool privilegedSYSRTC : 1; /**< Privileged access enabler for SYSRTC */
1110
1111 bool privilegedKEYPAD : 1; /**< Privileged access enabler for KEYPAD */
1112 bool privilegedDMEM : 1; /**< Privileged access enabler for DMEM */
1113 bool privilegedRADIOAES : 1; /**< Privileged access enabler for RADIOAES */
1114 bool privilegedSMU : 1; /**< Privileged access enabler for SMU */
1115 bool privilegedSMUCFGNS : 1; /**< Privileged access enabler for SMUCFGNS */
1116 bool privilegedLETIMER0 : 1; /**< Privileged access enabler for LETIMER0 */
1117 bool privilegedIADC0 : 1; /**< Privileged access enabler for IADC0 */
1118 bool privilegedACMP0 : 1; /**< Privileged access enabler for ACMP0 */
1119 bool privilegedACMP1 : 1; /**< Privileged access enabler for ACMP1 */
1120 bool privilegedAMUXCP0 : 1; /**< Privileged access enabler for AMUXCP0 */
1121 bool privilegedVDAC0 : 1; /**< Privileged access enabler for VDAC0 */
1122 bool privilegedVDAC1 : 1; /**< Privileged access enabler for VDAC1 */
1123 bool privilegedPCNT : 1; /**< Privileged access enabler for PCNT */
1124 bool privilegedHFRCO1 : 1; /**< Privileged access enabler for HFRCO1 */
1125 bool privilegedHFXO0 : 1; /**< Privileged access enabler for HFXO0 */
1126 bool privilegedI2C0 : 1; /**< Privileged access enabler for I2C0 */
1127 bool privilegedWDOG0 : 1; /**< Privileged access enabler for WDOG0 */
1128 bool privilegedWDOG1 : 1; /**< Privileged access enabler for WDOG1 */
1129 bool privilegedEUSART0 : 1; /**< Privileged access enabler for EUSART0 */
1130 bool privilegedSEMAILBOX : 1; /**< Privileged access enabler for SEMAILBOX */
1131 bool privilegedMVP : 1; /**< Privileged access enabler for MVP */
1132 bool privilegedAHBRADIO : 1; /**< Privileged access enabler for AHBRADIO */
1133
1134 #elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_5)
1135 bool privilegedReserved0 : 1; /**< Reserved privileged access enabler */
1136 bool privilegedEMU : 1; /**< Privileged access enabler for EMU */
1137 bool privilegedCMU : 1; /**< Privileged access enabler for CMU */
1138 bool privilegedHFRCO0 : 1; /**< Privileged access enabler for HFRCO0 */
1139 bool privilegedFSRCO : 1; /**< Privileged access enabler for FSRCO */
1140 bool privilegedDPLL0 : 1; /**< Privileged access enabler for DPLL0 */
1141 bool privilegedLFXO : 1; /**< Privileged access enabler for LFXO */
1142 bool privilegedLFRCO : 1; /**< Privileged access enabler for LFRCO */
1143 bool privilegedULFRCO : 1; /**< Privileged access enabler for ULFRCO */
1144 bool privilegedMSC : 1; /**< Privileged access enabler for MSC */
1145 bool privilegedICACHE0 : 1; /**< Privileged access enabler for ICACHE0 */
1146 bool privilegedPRS : 1; /**< Privileged access enabler for PRS0 */
1147 bool privilegedGPIO : 1; /**< Privileged access enabler for GPIO */
1148 bool privilegedLDMA : 1; /**< Privileged access enabler for LDMA */
1149 bool privilegedLDMAXBAR : 1; /**< Privileged access enabler for LDMAXBAR */
1150 bool privilegedTIMER0 : 1; /**< Privileged access enabler for TIMER0 */
1151 bool privilegedTIMER1 : 1; /**< Privileged access enabler for TIMER1 */
1152 bool privilegedTIMER2 : 1; /**< Privileged access enabler for TIMER2 */
1153 bool privilegedTIMER3 : 1; /**< Privileged access enabler for TIMER3 */
1154 bool privilegedTIMER4 : 1; /**< Privileged access enabler for TIMER4 */
1155 bool privilegedTIMER5 : 1; /**< Privileged access enabler for TIMER5 */
1156 bool privilegedTIMER6 : 1; /**< Privileged access enabler for TIMER6 */
1157 bool privilegedTIMER7 : 1; /**< Privileged access enabler for TIMER7 */
1158 bool privilegedBURTC : 1; /**< Privileged access enabler for BURTC */
1159 bool privilegedI2C1 : 1; /**< Privileged access enabler for I2C1 */
1160 bool privilegedCHIPTESTCTRL : 1; /**< Privileged access enabler for CHIPTESTCTRL */
1161 bool privilegedSYSCFGCFGNS : 1; /**< Privileged access enabler for SYSCFGCFGNS */
1162 bool privilegedSYSCFG : 1; /**< Privileged access enabler for SYSCFG */
1163 bool privilegedBURAM : 1; /**< Privileged access enabler for BURAM */
1164 bool privilegedGPCRC : 1; /**< Privileged access enabler for GPCRC */
1165 bool privilegedDCDC : 1; /**< Privileged access enabler for DCDC */
1166 bool privilegedHOSTMAILBOX : 1; /**< Privileged access enabler for HOSTMAILBOX */
1167
1168 bool privilegedEUSART1 : 1; /**< Privileged access enabler for EUSART1 */
1169 bool privilegedEUSART2 : 1; /**< Privileged access enabler for EUSART2 */
1170 bool privilegedEUSART3 : 1; /**< Privileged access enabler for EUSART3 */
1171 bool privilegedEUSART4 : 1; /**< Privileged access enabler for EUSART4 */
1172 bool privilegedSYSRTC : 1; /**< Privileged access enabler for SYSRTC */
1173 bool privilegedDMEM : 1; /**< Privileged access enabler for DMEM */
1174 bool privilegedPFMXPPRF : 1; /**< Privileged access enabler for PFMXPPRF */
1175 bool privilegedRFFPLL0 : 1; /**< Privileged access enabler for RFFPLL0 */
1176 bool privilegedETAMPDET : 1; /**< Privileged access enabler for ETAMPDET */
1177 bool privilegedBUFC : 1; /**< Privileged access enabler for BUFC */
1178 bool privilegedRADIOAES : 1; /**< Privileged access enabler for RADIOAES */
1179 bool privilegedSMU : 1; /**< Privileged access enabler for SMU */
1180 bool privilegedSMUCFGNS : 1; /**< Privileged access enabler for SMUCFGNS */
1181 bool privilegedAHBUSBSYS : 1; /**< Privileged access enabler for AHBUSBSYS */
1182 bool privilegedLETIMER0 : 1; /**< Privileged access enabler for LETIMER0 */
1183 bool privilegedIADC0 : 1; /**< Privileged access enabler for IADC0 */
1184 bool privilegedACMP0 : 1; /**< Privileged access enabler for ACMP0 */
1185 bool privilegedACMP1 : 1; /**< Privileged access enabler for ACMP1 */
1186 bool privilegedAMUXCP0 : 1; /**< Privileged access enabler for AMUXCP0 */
1187 bool privilegedVDAC0 : 1; /**< Privileged access enabler for VDAC0 */
1188 bool privilegedPCNT : 1; /**< Privileged access enabler for PCNT */
1189 bool privilegedLESENSE : 1; /**< Privileged access enabler for LESENSE */
1190 bool privilegedHFRCO1 : 1; /**< Privileged access enabler for HFRCO1 */
1191 bool privilegedHFXO0 : 1; /**< Privileged access enabler for HFXO0 */
1192 bool privilegedI2C0 : 1; /**< Privileged access enabler for I2C0 */
1193 bool privilegedWDOG0 : 1; /**< Privileged access enabler for WDOG0 */
1194 bool privilegedWDOG1 : 1; /**< Privileged access enabler for WDOG1 */
1195 bool privilegedEUSART0 : 1; /**< Privileged access enabler for EUSART0 */
1196 bool privilegedSEMAILBOX : 1; /**< Privileged access enabler for SEMAILBOX */
1197 bool privilegedAHBRADIO : 1; /**< Privileged access enabler for AHBRADIO */
1198
1199 #elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_6)
1200 bool privilegedReserved0 : 1; /**< Reserved privileged access enabler */
1201 bool privilegedEMU : 1; /**< Privileged access enabler for EMU */
1202 bool privilegedCMU : 1; /**< Privileged access enabler for CMU */
1203 bool privilegedBURTC : 1; /**< Privileged access enabler for BURTC */
1204 bool privilegedHFRCO0 : 1; /**< Privileged access enabler for HFRCO0 */
1205 bool privilegedFSRCO : 1; /**< Privileged access enabler for FSRCO */
1206 bool privilegedDPLL0 : 1; /**< Privileged access enabler for DPLL0 */
1207 bool privilegedLFXO : 1; /**< Privileged access enabler for LFXO */
1208 bool privilegedLFRCO : 1; /**< Privileged access enabler for LFRCO */
1209 bool privilegedULFRCO : 1; /**< Privileged access enabler for ULFRCO */
1210 bool privilegedKEYSCAN : 1; /**< Privileged access enabler for KEYSCAN */
1211 bool privilegedMSC : 1; /**< Privileged access enabler for MSC */
1212 bool privilegedICACHE0 : 1; /**< Privileged access enabler for ICACHE0 */
1213 bool privilegedPRS : 1; /**< Privileged access enabler for PRS0 */
1214 bool privilegedGPIO : 1; /**< Privileged access enabler for GPIO */
1215 bool privilegedLDMA : 1; /**< Privileged access enabler for LDMA */
1216 bool privilegedLDMAXBAR : 1; /**< Privileged access enabler for LDMAXBAR */
1217 bool privilegedTIMER0 : 1; /**< Privileged access enabler for TIMER0 */
1218 bool privilegedTIMER1 : 1; /**< Privileged access enabler for TIMER1 */
1219 bool privilegedTIMER2 : 1; /**< Privileged access enabler for TIMER2 */
1220 bool privilegedTIMER3 : 1; /**< Privileged access enabler for TIMER3 */
1221 bool privilegedTIMER4 : 1; /**< Privileged access enabler for TIMER4 */
1222 bool privilegedTIMER5 : 1; /**< Privileged access enabler for TIMER5 */
1223 bool privilegedTIMER6 : 1; /**< Privileged access enabler for TIMER6 */
1224 bool privilegedTIMER7 : 1; /**< Privileged access enabler for TIMER7 */
1225 bool privilegedTIMER8 : 1; /**< Privileged access enabler for TIMER8 */
1226 bool privilegedTIMER9 : 1; /**< Privileged access enabler for TIMER9 */
1227 bool privilegedCHIPTESTCTRL : 1; /**< Privileged access enabler for CHIPTESTCTRL */
1228 bool privilegedDMEM0 : 1; /**< Privileged access enabler for DMEM0 */
1229 bool privilegedDMEM1 : 1; /**< Privileged access enabler for DMEM1 */
1230 bool privilegedSYSCFGCFGNS : 1; /**< Privileged access enabler for SYSCFGCFGNS */
1231 bool privilegedSYSCFG : 1; /**< Privileged access enabler for SYSCFG */
1232
1233 bool privilegedBURAM : 1; /**< Privileged access enabler for BURAM */
1234 bool privilegedGPCRC : 1; /**< Privileged access enabler for GPCRC */
1235 bool privilegedEUSART1 : 1; /**< Privileged access enabler for EUSART1 */
1236 bool privilegedEUSART2 : 1; /**< Privileged access enabler for EUSART2 */
1237 bool privilegedEUSART3 : 1; /**< Privileged access enabler for EUSART3 */
1238 bool privilegedDCDC : 1; /**< Privileged access enabler for DCDC */
1239 bool privilegedHOSTMAILBOX : 1; /**< Privileged access enabler for HOSTMAILBOX */
1240 bool privilegedUSART0 : 1; /**< Privileged access enabler for USART0 */
1241 bool privilegedUSART1 : 1; /**< Privileged access enabler for USART1 */
1242 bool privilegedUSART2 : 1; /**< Privileged access enabler for USART2 */
1243 bool privilegedSYSRTC0 : 1; /**< Privileged access enabler for SYSRTC0 */
1244 bool privilegedI2C1 : 1; /**< Privileged access enabler for I2C1 */
1245 bool privilegedI2C2 : 1; /**< Privileged access enabler for I2C2 */
1246 bool privilegedI2C3 : 1; /**< Privileged access enabler for I2C3 */
1247 bool privilegedLCD : 1; /**< Privileged access enabler for LCD */
1248 bool privilegedLCDRF : 1; /**< Privileged access enabler for LCDRF */
1249 bool privilegedRADIOAES : 1; /**< Privileged access enabler for RADIOAES */
1250 bool privilegedSMU : 1; /**< Privileged access enabler for SMU */
1251 bool privilegedSMUCFGNS : 1; /**< Privileged access enabler for SMUCFGNS */
1252 bool privilegedLETIMER0 : 1; /**< Privileged access enabler for LETIMER0 */
1253 bool privilegedIADC0 : 1; /**< Privileged access enabler for IADC0 */
1254 bool privilegedACMP0 : 1; /**< Privileged access enabler for ACMP0 */
1255 bool privilegedACMP1 : 1; /**< Privileged access enabler for ACMP1 */
1256 bool privilegedAMUXCP0 : 1; /**< Privileged access enabler for AMUXCP0 */
1257 bool privilegedVDAC0 : 1; /**< Privileged access enabler for VDAC0 */
1258 bool privilegedVDAC1 : 1; /**< Privileged access enabler for VDAC1 */
1259 bool privilegedPCNT0 : 1; /**< Privileged access enabler for PCNT0 */
1260 bool privilegedHFRCO1 : 1; /**< Privileged access enabler for HFRCO1 */
1261 bool privilegedHFXO0 : 1; /**< Privileged access enabler for HFXO0 */
1262 bool privilegedI2C0 : 1; /**< Privileged access enabler for I2C0 */
1263 bool privilegedWDOG0 : 1; /**< Privileged access enabler for WDOG0 */
1264 bool privilegedWDOG1 : 1; /**< Privileged access enabler for WDOG1 */
1265
1266 bool privilegedEUSART0 : 1; /**< Privileged access enabler for EUSART0 */
1267 bool privilegedSEMAILBOX : 1; /**< Privileged access enabler for SEMAILBOX */
1268 bool privilegedMVP : 1; /**< Privileged access enabler for MVP */
1269 bool privilegedAHBRADIO : 1; /**< Privileged access enabler for AHBRADIO */
1270
1271 #elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_7)
1272 bool privilegedSCRATCHPAD : 1; /**< Privileged access enabler for SCRATCHPAD */
1273 bool privilegedEMU : 1; /**< Privileged access enabler for EMU */
1274 bool privilegedCMU : 1; /**< Privileged access enabler for CMU */
1275 bool privilegedHFXO0 : 1; /**< Privileged access enabler for HFXO0 */
1276 bool privilegedHFRCO0 : 1; /**< Privileged access enabler for HFRCO0 */
1277 bool privilegedFSRCO : 1; /**< Privileged access enabler for FSRCO */
1278 bool privilegedDPLL0 : 1; /**< Privileged access enabler for DPLL0 */
1279 bool privilegedLFXO : 1; /**< Privileged access enabler for LFXO */
1280 bool privilegedLFRCO : 1; /**< Privileged access enabler for LFRCO */
1281 bool privilegedULFRCO : 1; /**< Privileged access enabler for ULFRCO */
1282 bool privilegedMSC : 1; /**< Privileged access enabler for MSC */
1283 bool privilegedICACHE0 : 1; /**< Privileged access enabler for ICACHE0 */
1284 bool privilegedPRS : 1; /**< Privileged access enabler for PRS0 */
1285 bool privilegedGPIO : 1; /**< Privileged access enabler for GPIO */
1286 bool privilegedLDMA : 1; /**< Privileged access enabler for LDMA */
1287 bool privilegedLDMAXBAR : 1; /**< Privileged access enabler for LDMAXBAR */
1288 bool privilegedTIMER0 : 1; /**< Privileged access enabler for TIMER0 */
1289 bool privilegedTIMER1 : 1; /**< Privileged access enabler for TIMER1 */
1290 bool privilegedTIMER2 : 1; /**< Privileged access enabler for TIMER2 */
1291 bool privilegedTIMER3 : 1; /**< Privileged access enabler for TIMER3 */
1292 bool privilegedTIMER4 : 1; /**< Privileged access enabler for TIMER4 */
1293 bool privilegedUSART0 : 1; /**< Privileged access enabler for USART0 */
1294 bool privilegedUSART1 : 1; /**< Privileged access enabler for USART1 */
1295 bool privilegedBURTC : 1; /**< Privileged access enabler for BURTC */
1296 bool privilegedI2C1 : 1; /**< Privileged access enabler for I2C1 */
1297 bool privilegedCHIPTESTCTRL : 1; /**< Privileged access enabler for CHIPTESTCTRL */
1298 bool privilegedSYSCFGCFGNS : 1; /**< Privileged access enabler for SYSCFGCFGNS */
1299 bool privilegedSYSCFG : 1; /**< Privileged access enabler for SYSCFG */
1300 bool privilegedBURAM : 1; /**< Privileged access enabler for BURAM */
1301 bool privilegedIFADCDEBUG : 1; /**< Privileged access enabler for IFADCDEBUG */
1302 bool privilegedGPCRC : 1; /**< Privileged access enabler for GPCRC */
1303 bool privilegedDCI : 1; /**< Privileged access enabler for DCI */
1304
1305 bool privilegedReserved0 : 1; /**< Reserved privileged access enabler */
1306 bool privilegedDCDC : 1; /**< Privileged access enabler for DCDC */
1307 bool privilegedPDM : 1; /**< Privileged access enabler for PDM */
1308 bool privilegedRFSENSE : 1; /**< Privileged access enabler for RFSENSE */
1309 bool privilegedSEPUF : 1; /**< Privileged access enabler for SEPUF */
1310 bool privilegedETAMPDET : 1; /**< Privileged access enabler for ETAMPDET */
1311 bool privilegedRADIOAES : 1; /**< Privileged access enabler for RADIOAES */
1312 bool privilegedSMU : 1; /**< Privileged access enabler for SMU */
1313 bool privilegedSMUCFGNS : 1; /**< Privileged access enabler for SMUCFGNS */
1314 bool privilegedRTCC : 1; /**< Privileged access enabler for RTCC */
1315 bool privilegedLETIMER0 : 1; /**< Privileged access enabler for LETIMER0 */
1316 bool privilegedIADC0 : 1; /**< Privileged access enabler for IADC0 */
1317 bool privilegedACMP0 : 1; /**< Privileged access enabler for ACMP0 */
1318 bool privilegedI2C0 : 1; /**< Privileged access enabler for I2C0 */
1319 bool privilegedWDOG0 : 1; /**< Privileged access enabler for WDOG0 */
1320 bool privilegedAMUXCP0 : 1; /**< Privileged access enabler for AMUXCP0 */
1321 bool privilegedEUSART0 : 1; /**< Privileged access enabler for EUSART0 */
1322 bool privilegedCRYPTOACC : 1; /**< Privileged access enabler for CRYPTOACC */
1323 bool privilegedAHBRADIO : 1; /**< Privileged access enabler for AHBRADIO */
1324
1325 #elif defined(_SILICON_LABS_32B_SERIES_2_CONFIG_8)
1326 bool privilegedReserved0 : 1; /**< Reserved privileged access enabler */
1327 bool privilegedEMU : 1; /**< Privileged access enabler for EMU */
1328 bool privilegedCMU : 1; /**< Privileged access enabler for CMU */
1329 bool privilegedHFRCO0 : 1; /**< Privileged access enabler for HFRCO0 */
1330 bool privilegedFSRCO : 1; /**< Privileged access enabler for FSRCO */
1331 bool privilegedDPLL0 : 1; /**< Privileged access enabler for DPLL0 */
1332 bool privilegedLFXO : 1; /**< Privileged access enabler for LFXO */
1333 bool privilegedLFRCO : 1; /**< Privileged access enabler for LFRCO */
1334 bool privilegedULFRCO : 1; /**< Privileged access enabler for ULFRCO */
1335 bool privilegedMSC : 1; /**< Privileged access enabler for MSC */
1336 bool privilegedICACHE0 : 1; /**< Privileged access enabler for ICACHE0 */
1337 bool privilegedPRS : 1; /**< Privileged access enabler for PRS0 */
1338 bool privilegedGPIO : 1; /**< Privileged access enabler for GPIO */
1339 bool privilegedLDMA : 1; /**< Privileged access enabler for LDMA */
1340 bool privilegedLDMAXBAR : 1; /**< Privileged access enabler for LDMAXBAR */
1341 bool privilegedTIMER0 : 1; /**< Privileged access enabler for TIMER0 */
1342 bool privilegedTIMER1 : 1; /**< Privileged access enabler for TIMER1 */
1343 bool privilegedTIMER2 : 1; /**< Privileged access enabler for TIMER2 */
1344 bool privilegedTIMER3 : 1; /**< Privileged access enabler for TIMER3 */
1345 bool privilegedTIMER4 : 1; /**< Privileged access enabler for TIMER4 */
1346 bool privilegedUSART0 : 1; /**< Privileged access enabler for USART0 */
1347 bool privilegedBURTC : 1; /**< Privileged access enabler for BURTC */
1348 bool privilegedI2C1 : 1; /**< Privileged access enabler for I2C1 */
1349 bool privilegedCHIPTESTCTRL : 1; /**< Privileged access enabler for CHIPTESTCTRL */
1350 bool privilegedSYSCFGCFGNS : 1; /**< Privileged access enabler for SYSCFGCFGNS */
1351 bool privilegedSYSCFG : 1; /**< Privileged access enabler for SYSCFG */
1352 bool privilegedBURAM : 1; /**< Privileged access enabler for BURAM */
1353 bool privilegedGPCRC : 1; /**< Privileged access enabler for GPCRC */
1354 bool privilegedDCDC : 1; /**< Privileged access enabler for DCDC */
1355 bool privilegedHOSTMAILBOX : 1; /**< Privileged access enabler for HOSTMAILBOX */
1356 bool privilegedEUSART1 : 1; /**< Privileged access enabler for EUSART1 */
1357 bool privilegedEUSART2 : 1; /**< Privileged access enabler for EUSART2 */
1358
1359 bool privilegedSYSRTC : 1; /**< Privileged access enabler for SYSRTC */
1360 bool privilegedLCD : 1; /**< Privileged access enabler for LCD */
1361 bool privilegedKEYSCAN : 1; /**< Privileged access enabler for KEYSCAN */
1362 bool privilegedDMEM : 1; /**< Privileged access enabler for DMEM */
1363 bool privilegedLCDRF : 1; /**< Privileged access enabler for LCDRF */
1364 bool privilegedPFMXPPRF : 1; /**< Privileged access enabler for PFMXPPRF */
1365 bool privilegedRADIOAES : 1; /**< Privileged access enabler for RADIOAES */
1366 bool privilegedSMU : 1; /**< Privileged access enabler for SMU */
1367 bool privilegedSMUCFGNS : 1; /**< Privileged access enabler for SMUCFGNS */
1368 bool privilegedLETIMER0 : 1; /**< Privileged access enabler for LETIMER0 */
1369 bool privilegedIADC0 : 1; /**< Privileged access enabler for IADC0 */
1370 bool privilegedACMP0 : 1; /**< Privileged access enabler for ACMP0 */
1371 bool privilegedACMP1 : 1; /**< Privileged access enabler for ACMP1 */
1372 bool privilegedAMUXCP0 : 1; /**< Privileged access enabler for AMUXCP0 */
1373 bool privilegedVDAC0 : 1; /**< Privileged access enabler for VDAC0 */
1374 bool privilegedPCNT : 1; /**< Privileged access enabler for PCNT */
1375 bool privilegedLESENSE : 1; /**< Privileged access enabler for LESENSE */
1376 bool privilegedHFRCO1 : 1; /**< Privileged access enabler for HFRCO1 */
1377 bool privilegedHFXO0 : 1; /**< Privileged access enabler for HFXO0 */
1378 bool privilegedI2C0 : 1; /**< Privileged access enabler for I2C0 */
1379 bool privilegedWDOG0 : 1; /**< Privileged access enabler for WDOG0 */
1380 bool privilegedWDOG1 : 1; /**< Privileged access enabler for WDOG1 */
1381 bool privilegedEUSART0 : 1; /**< Privileged access enabler for EUSART0 */
1382 bool privilegedSEMAILBOX : 1; /**< Privileged access enabler for SEMAILBOX */
1383 bool privilegedMVP : 1; /**< Privileged access enabler for MVP */
1384 bool privilegedAHBRADIO : 1; /**< Privileged access enabler for AHBRADIO */
1385
1386 #else
1387 #error "No peripherals defined for SMU for this device configuration"
1388 #endif
1389 } SMU_PrivilegedAccess_TypeDef;
1390
1391 /*******************************************************************************
1392 ****************************** STRUCTS ************************************
1393 ******************************************************************************/
1394
1395 /** SMU initialization structure. */
1396 typedef struct {
1397 union {
1398 #if defined(_SMU_PPUNSPATD2_MASK)
1399 uint32_t reg[3]; /**< Peripheral access control array.*/
1400 #else
1401 uint32_t reg[2]; /**< Peripheral access control array.*/
1402 #endif
1403 SMU_PrivilegedAccess_TypeDef access; /**< Peripheral access control array.*/
1404 } ppu; /**< PPU init array.*/
1405 bool enable; /**< SMU enable flag. When set, SMU_Init() will enable SMU.*/
1406 } SMU_Init_TypeDef;
1407
1408 /** Default SMU initialization structure settings. */
1409 #define SMU_INIT_DEFAULT { \
1410 { { 0 } }, /* No peripherals access protected. */ \
1411 true /* Enable SMU.*/ \
1412 }
1413
1414 /*******************************************************************************
1415 ***************************** PROTOTYPES **********************************
1416 ******************************************************************************/
1417
1418 /***************************************************************************//**
1419 * @brief
1420 * Enable or disable PPU of SMU.
1421 *
1422 * @param[in] enable
1423 * Set to true to enable PPU; set to false otherwise.
1424 ******************************************************************************/
SMU_EnablePPU(bool enable)1425 __STATIC_INLINE void SMU_EnablePPU(bool enable)
1426 {
1427 #if defined (_SMU_PPUCTRL_ENABLE_SHIFT)
1428 BUS_RegBitWrite(&SMU->PPUCTRL, _SMU_PPUCTRL_ENABLE_SHIFT, enable);
1429 #else
1430 (void)enable;
1431 #endif
1432 }
1433
1434 /***************************************************************************//**
1435 * @brief
1436 * Initialize PPU of SMU.
1437 *
1438 * @param[in] init
1439 * Pointer to initialization structure that defines which peripherals should
1440 * only be accessed from privileged mode, and if PPU should be enabled.
1441 ******************************************************************************/
SMU_Init(const SMU_Init_TypeDef * init)1442 __STATIC_INLINE void SMU_Init(const SMU_Init_TypeDef *init)
1443 {
1444 #if !defined (SL_TRUSTZONE_SECURE) && defined(_SILICON_LABS_32B_SERIES_2_CONFIG) \
1445 && (_SILICON_LABS_32B_SERIES_2_CONFIG >= 2)
1446 SMU_NS_CFGNS->PPUNSPATD0 = init->ppu.reg[0];
1447 SMU_NS_CFGNS->PPUNSPATD1 = init->ppu.reg[1];
1448 #if defined(_SMU_PPUNSPATD2_MASK)
1449 SMU_NS_CFGNS->PPUNSPATD2 = init->ppu.reg[2];
1450 #endif //defined(_SMU_PPUNSPATD2_MASK)
1451 #else
1452 SMU->PPUPATD0 = init->ppu.reg[0];
1453 SMU->PPUPATD1 = init->ppu.reg[1];
1454 #if defined(_SMU_PPUNSPATD2_MASK)
1455 SMU->PPUPATD2 = init->ppu.reg[2];
1456 #endif //defined(_SMU_PPUNSPATD2_MASK)
1457 #endif //SL_TRUSTZONE_SECURE
1458
1459 SMU_EnablePPU(init->enable);
1460 }
1461 /***************************************************************************//**
1462 * @brief
1463 * Change access settings for a peripheral.
1464 *
1465 * @details
1466 * Set to limit access of a peripheral from privileged mode.
1467 *
1468 * @param[in] peripheral
1469 * ID of the peripheral to change access settings for.
1470 *
1471 * @param[in] privileged
1472 * Set to true if the peripheral should only be accessed from privileged
1473 * mode; set to false otherwise.
1474 ******************************************************************************/
SMU_SetPrivilegedAccess(SMU_Peripheral_TypeDef peripheral,bool privileged)1475 __STATIC_INLINE void SMU_SetPrivilegedAccess(SMU_Peripheral_TypeDef peripheral,
1476 bool privileged)
1477 {
1478 EFM_ASSERT(peripheral < smuPeripheralEnd);
1479
1480 #if !defined (SL_TRUSTZONE_SECURE) && defined(_SILICON_LABS_32B_SERIES_2_CONFIG) \
1481 && (_SILICON_LABS_32B_SERIES_2_CONFIG >= 2)
1482 if (peripheral < 32) {
1483 BUS_RegBitWrite(&SMU_NS_CFGNS->PPUNSPATD0, peripheral, privileged);
1484 } else if (peripheral < 64) {
1485 BUS_RegBitWrite(&SMU_NS_CFGNS->PPUNSPATD1, peripheral - 32, privileged);
1486 } else {
1487 #if defined(_SMU_PPUNSPATD2_MASK)
1488 BUS_RegBitWrite(&SMU_NS_CFGNS->PPUNSPATD2, peripheral - 64, privileged);
1489 #else
1490 EFM_ASSERT(false);
1491 #endif //defined(_SMU_PPUNSPATD2_MASK)
1492 }
1493 #else
1494 if (peripheral < 32) {
1495 BUS_RegBitWrite(&SMU->PPUPATD0, peripheral, privileged);
1496 } else if (peripheral < 64) {
1497 BUS_RegBitWrite(&SMU->PPUPATD1, peripheral - 32, privileged);
1498 } else {
1499 #if defined(_SMU_PPUNSPATD2_MASK)
1500 BUS_RegBitWrite(&SMU_NS_CFGNS->PPUNSPATD2, peripheral - 64, privileged);
1501 #else
1502 EFM_ASSERT(false);
1503 #endif //defined(_SMU_PPUNSPATD2_MASK)
1504 }
1505 #endif //SL_TRUSTZONE_SECURE
1506 }
1507
1508 /***************************************************************************//**
1509 * @brief
1510 * Get the ID of the peripheral that caused an access fault.
1511 *
1512 * @note
1513 * The return value is only valid if SMU_IF_PPUPRIV interrupt flag
1514 * is set.
1515 *
1516 * @return
1517 * ID of the peripheral that caused an access fault.
1518 ******************************************************************************/
SMU_GetFaultingPeripheral(void)1519 __STATIC_INLINE SMU_Peripheral_TypeDef SMU_GetFaultingPeripheral(void)
1520 {
1521 #if !defined (SL_TRUSTZONE_SECURE) && defined(_SILICON_LABS_32B_SERIES_2_CONFIG) \
1522 && (_SILICON_LABS_32B_SERIES_2_CONFIG >= 2)
1523 return (SMU_Peripheral_TypeDef)SMU_NS_CFGNS->PPUNSFS;
1524 #else
1525 return (SMU_Peripheral_TypeDef)SMU->PPUFS;
1526 #endif //SL_TRUSTZONE_SECURE
1527 }
1528
1529 /***************************************************************************//**
1530 * @brief
1531 * Clear one or more pending SMU interrupts.
1532 *
1533 * @param[in] flags
1534 * Bitwise logic OR of SMU interrupt sources to clear.
1535 ******************************************************************************/
SMU_IntClear(uint32_t flags)1536 __STATIC_INLINE void SMU_IntClear(uint32_t flags)
1537 {
1538 #if defined (SMU_HAS_SET_CLEAR)
1539 #if !defined (SL_TRUSTZONE_SECURE) && defined(_SILICON_LABS_32B_SERIES_2_CONFIG) \
1540 && (_SILICON_LABS_32B_SERIES_2_CONFIG >= 2)
1541 SMU_NS_CFGNS->NSIF_CLR = flags;
1542 #else
1543 SMU->IF_CLR = flags;
1544 #endif //SL_TRUSTZONE_SECURE
1545 #else
1546 SMU->IFC = flags;
1547 #endif //SMU_HAS_SET_CLEAR
1548 }
1549
1550 /***************************************************************************//**
1551 * @brief
1552 * Disable one or more SMU interrupts.
1553 *
1554 * @param[in] flags
1555 * SMU interrupt sources to disable.
1556 ******************************************************************************/
SMU_IntDisable(uint32_t flags)1557 __STATIC_INLINE void SMU_IntDisable(uint32_t flags)
1558 {
1559 #if defined (SMU_HAS_SET_CLEAR)
1560 #if !defined (SL_TRUSTZONE_SECURE) && defined(_SILICON_LABS_32B_SERIES_2_CONFIG) \
1561 && (_SILICON_LABS_32B_SERIES_2_CONFIG >= 2)
1562 SMU_NS_CFGNS->NSIEN_CLR = flags;
1563 #else
1564 SMU->IEN_CLR = flags;
1565 #endif //SL_TRUSTZONE_SECURE
1566 #else
1567 SMU->IEN &= ~flags;
1568 #endif //SMU_HAS_SET_CLEAR
1569 }
1570
1571 /***************************************************************************//**
1572 * @brief
1573 * Enable one or more SMU interrupts.
1574 *
1575 * @note
1576 * Depending on the use, a pending interrupt may already be set prior to
1577 * enabling the interrupt. To ignore a pending interrupt, consider using
1578 * SMU_IntClear() prior to enabling the interrupt.
1579 *
1580 * @param[in] flags
1581 * SMU interrupt sources to enable.
1582 ******************************************************************************/
SMU_IntEnable(uint32_t flags)1583 __STATIC_INLINE void SMU_IntEnable(uint32_t flags)
1584 {
1585 #if defined (SMU_HAS_SET_CLEAR)
1586 #if !defined (SL_TRUSTZONE_SECURE) && defined(_SILICON_LABS_32B_SERIES_2_CONFIG) \
1587 && (_SILICON_LABS_32B_SERIES_2_CONFIG >= 2)
1588 SMU_NS_CFGNS->NSIEN_SET = flags;
1589 #else
1590 SMU->IEN_SET = flags;
1591 #endif //SL_TRUSTZONE_SECURE
1592 #else
1593 SMU->IEN |= flags;
1594 #endif //SMU_HAS_SET_CLEAR
1595 }
1596
1597 /***************************************************************************//**
1598 * @brief
1599 * Get pending SMU interrupts.
1600 *
1601 * @return
1602 * SMU interrupt sources pending.
1603 ******************************************************************************/
SMU_IntGet(void)1604 __STATIC_INLINE uint32_t SMU_IntGet(void)
1605 {
1606 #if !defined (SL_TRUSTZONE_SECURE) && defined(_SILICON_LABS_32B_SERIES_2_CONFIG) \
1607 && (_SILICON_LABS_32B_SERIES_2_CONFIG >= 2)
1608 return SMU_NS_CFGNS->NSIF;
1609 #else
1610 return SMU->IF;
1611 #endif //SL_TRUSTZONE_SECURE
1612 }
1613
1614 /***************************************************************************//**
1615 * @brief
1616 * Get enabled and pending SMU interrupt flags.
1617 * Useful for handling more interrupt sources in the same interrupt handler.
1618 *
1619 * @note
1620 * Interrupt flags are not cleared by this function.
1621 *
1622 * @return
1623 * Pending and enabled SMU interrupt sources.
1624 * The return value is the bitwise AND combination of
1625 * - the OR combination of enabled interrupt sources in SMU_IEN register
1626 * and
1627 * - the OR combination of valid interrupt flags in SMU_IF register.
1628 ******************************************************************************/
SMU_IntGetEnabled(void)1629 __STATIC_INLINE uint32_t SMU_IntGetEnabled(void)
1630 {
1631 uint32_t tmp;
1632
1633 #if !defined (SL_TRUSTZONE_SECURE) && defined(_SILICON_LABS_32B_SERIES_2_CONFIG) \
1634 && (_SILICON_LABS_32B_SERIES_2_CONFIG >= 2)
1635 // Store SMU->IEN in temporary variable to define explicit order
1636 // of volatile accesses.
1637 tmp = SMU_NS_CFGNS->NSIEN;
1638
1639 // Bitwise AND of pending and enabled interrupts.
1640 return SMU_NS_CFGNS->NSIF & tmp;
1641 #else
1642 // Store SMU->IEN in temporary variable to define explicit order
1643 // of volatile accesses.
1644 tmp = SMU->IEN;
1645
1646 // Bitwise AND of pending and enabled interrupts.
1647 return SMU->IF & tmp;
1648 #endif //SL_TRUSTZONE_SECURE
1649 }
1650
1651 /***************************************************************************//**
1652 * @brief
1653 * Set one or more pending SMU interrupts from SW.
1654 *
1655 * @param[in] flags
1656 * SMU interrupt sources to set to pending.
1657 ******************************************************************************/
SMU_IntSet(uint32_t flags)1658 __STATIC_INLINE void SMU_IntSet(uint32_t flags)
1659 {
1660 #if defined (SMU_HAS_SET_CLEAR)
1661 #if !defined (SL_TRUSTZONE_SECURE) && defined(_SILICON_LABS_32B_SERIES_2_CONFIG) \
1662 && (_SILICON_LABS_32B_SERIES_2_CONFIG >= 2)
1663 SMU_NS_CFGNS->NSIF_SET = flags;
1664 #else
1665 SMU->IF_SET = flags;
1666 #endif //SL_TRUSTZONE_SECURE
1667 #else
1668 SMU->IFS = flags;
1669 #endif //SMU_HAS_SET_CLEAR
1670 }
1671
1672 /**************************************************************************//**
1673 * @brief
1674 * SMU secure IRQ Handler.
1675 *
1676 * @details
1677 * When a PPU detects an access to a secure peripheral at its non-secure
1678 * address or an access to a non-secure peripheral at its secure
1679 * address, PPUSECIF in SMU_IF is set and the ID of the peripheral being
1680 * accessed is written to SMU_PPUFS. If PPUSECIEN is set and the SMU's
1681 * Secure IRQ enabled, the CPU will be interrupted and SMU_SECURE_IRQHandler
1682 * Will handle the interrupt.
1683 ******************************************************************************/
1684 #if !defined (SL_TRUSTZONE_SECURE) && defined (_SILICON_LABS_32B_SERIES_2)
SMU_SECURE_IRQHandler(void)1685 void SMU_SECURE_IRQHandler(void)
1686 {
1687 if (SMU_IF_PPUSEC) {
1688 EFM_ASSERT(SMU->IF & SMU_IF_PPUSEC);
1689 }
1690
1691 if (SMU_IF_BMPUSEC) {
1692 EFM_ASSERT(SMU->IF & SMU_IF_BMPUSEC);
1693 }
1694
1695 // PPUFS contains the ID of the peripheral caused the fault
1696 // The ID is ordered after the PPUSATD0-PPUSATD1 register bit fields.
1697 EFM_ASSERT(SMU->PPUFS);
1698
1699 while (1) {
1700 // do nothing
1701 }
1702 }
1703 #endif //SL_TRUSTZONE_SECURE
1704
1705 /** @} (end addtogroup smu) */
1706
1707 #ifdef __cplusplus
1708 }
1709 #endif
1710
1711 #endif // defined(SMU_COUNT) && (SMU_COUNT > 0)
1712 #endif // EM_SMU_H
1713
