1 /***************************************************************************//**
2 * @file
3 * @brief Direct memory access (LDMA) API
4 *******************************************************************************
5 * # License
6 * <b>Copyright 2018 Silicon Laboratories Inc. www.silabs.com</b>
7 *******************************************************************************
8 *
9 * SPDX-License-Identifier: Zlib
10 *
11 * The licensor of this software is Silicon Laboratories Inc.
12 *
13 * This software is provided 'as-is', without any express or implied
14 * warranty. In no event will the authors be held liable for any damages
15 * arising from the use of this software.
16 *
17 * Permission is granted to anyone to use this software for any purpose,
18 * including commercial applications, and to alter it and redistribute it
19 * freely, subject to the following restrictions:
20 *
21 * 1. The origin of this software must not be misrepresented; you must not
22 * claim that you wrote the original software. If you use this software
23 * in a product, an acknowledgment in the product documentation would be
24 * appreciated but is not required.
25 * 2. Altered source versions must be plainly marked as such, and must not be
26 * misrepresented as being the original software.
27 * 3. This notice may not be removed or altered from any source distribution.
28 *
29 ******************************************************************************/
30
31 #ifndef EM_LDMA_H
32 #define EM_LDMA_H
33
34 #include "em_device.h"
35
36 #if defined(LDMA_PRESENT) && (LDMA_COUNT == 1)
37
38 #include <stdbool.h>
39
40 #ifdef __cplusplus
41 extern "C" {
42 #endif
43
44 /***************************************************************************//**
45 * @addtogroup ldma LDMA - Linked DMA
46 * @brief Linked Direct Memory Access (LDMA) Peripheral API
47 *
48 * @details
49 * LDMA API functions provide full support for the LDMA peripheral.
50 *
51 * LDMA supports these DMA transfer types:
52 *
53 * @li Memory to memory.
54 * @li Memory to peripheral.
55 * @li Peripheral to memory.
56 * @li Peripheral to peripheral.
57 * @li Constant value to memory.
58 *
59 * LDMA supports linked lists of DMA descriptors allowing:
60 *
61 * @li Circular and ping-pong buffer transfers.
62 * @li Scatter-gather transfers.
63 * @li Looped transfers.
64 *
65 * LDMA has some advanced features:
66 *
67 * @li Intra-channel synchronization (SYNC), allowing hardware events to
68 * pause and restart a DMA sequence.
69 * @li Immediate-write (WRI), allowing DMA to write a constant anywhere
70 * in the memory map.
71 * @li Complex flow control allowing if-else constructs.
72 *
73 * Basic understanding of LDMA controller is assumed. Please refer to
74 * the reference manual for further details. The LDMA examples described
75 * in the reference manual are particularly helpful in understanding LDMA
76 * operations.
77 *
78 * In order to use the DMA controller, the initialization function @ref
79 * LDMA_Init() must have been executed once (normally during system initialization).
80 *
81 * DMA transfers are initiated by a call to @ref LDMA_StartTransfer(),
82 * transfer properties are controlled by the contents of @ref LDMA_TransferCfg_t
83 * and @ref LDMA_Descriptor_t structure parameters.
84 * The LDMA_Descriptor_t structure parameter may be a
85 * pointer to an array of descriptors, descriptors in array should
86 * be linked together as needed.
87 *
88 * Transfer and descriptor initialization macros are provided for the most common
89 * transfer types. Due to the flexibility of LDMA peripheral, only a small
90 * subset of all possible initializer macros are provided, users should create
91 * new ones when needed.
92 *
93 * <b> Examples of LDMA usage: </b>
94 *
95 * A simple memory to memory transfer:
96 *
97 * @include em_ldma_single.c
98 *
99 * @n A linked list of three memory to memory transfers:
100 *
101 * @include em_ldma_link_memory.c
102 *
103 * @n DMA from serial port peripheral to memory:
104 *
105 * @include em_ldma_peripheral.c
106 *
107 * @n Ping-pong DMA from serial port peripheral to memory:
108 *
109 * @include em_ldma_pingpong.c
110 *
111 * @note LDMA module does not implement LDMA interrupt handler. A
112 * template for an LDMA IRQ handler is included here as an example.
113 *
114 * @include em_ldma_irq.c
115 *
116 * @{
117 ******************************************************************************/
118
119 /*******************************************************************************
120 ******************************** ENUMS ************************************
121 ******************************************************************************/
122
123 /**
124 * Controls the number of unit data transfers per arbitration
125 * cycle, providing a means to balance DMA channels' load on the controller.
126 */
127 typedef enum {
128 ldmaCtrlBlockSizeUnit1 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT1, /**< One transfer per arbitration. */
129 ldmaCtrlBlockSizeUnit2 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT2, /**< Two transfers per arbitration. */
130 ldmaCtrlBlockSizeUnit3 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT3, /**< Three transfers per arbitration. */
131 ldmaCtrlBlockSizeUnit4 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT4, /**< Four transfers per arbitration. */
132 ldmaCtrlBlockSizeUnit6 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT6, /**< Six transfers per arbitration. */
133 ldmaCtrlBlockSizeUnit8 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT8, /**< Eight transfers per arbitration. */
134 ldmaCtrlBlockSizeUnit16 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT16, /**< 16 transfers per arbitration. */
135 ldmaCtrlBlockSizeUnit32 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT32, /**< 32 transfers per arbitration. */
136 ldmaCtrlBlockSizeUnit64 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT64, /**< 64 transfers per arbitration. */
137 ldmaCtrlBlockSizeUnit128 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT128, /**< 128 transfers per arbitration. */
138 ldmaCtrlBlockSizeUnit256 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT256, /**< 256 transfers per arbitration. */
139 ldmaCtrlBlockSizeUnit512 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT512, /**< 512 transfers per arbitration. */
140 ldmaCtrlBlockSizeUnit1024 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT1024, /**< 1024 transfers per arbitration. */
141 ldmaCtrlBlockSizeAll = _LDMA_CH_CTRL_BLOCKSIZE_ALL /**< Lock arbitration during transfer. */
142 } LDMA_CtrlBlockSize_t;
143
144 /** DMA structure type. */
145 typedef enum {
146 ldmaCtrlStructTypeXfer = _LDMA_CH_CTRL_STRUCTTYPE_TRANSFER, /**< TRANSFER transfer type. */
147 ldmaCtrlStructTypeSync = _LDMA_CH_CTRL_STRUCTTYPE_SYNCHRONIZE, /**< SYNCHRONIZE transfer type. */
148 ldmaCtrlStructTypeWrite = _LDMA_CH_CTRL_STRUCTTYPE_WRITE /**< WRITE transfer type. */
149 } LDMA_CtrlStructType_t;
150
151 /** DMA transfer block or cycle selector. */
152 typedef enum {
153 ldmaCtrlReqModeBlock = _LDMA_CH_CTRL_REQMODE_BLOCK, /**< Each DMA request trigger transfer of one block. */
154 ldmaCtrlReqModeAll = _LDMA_CH_CTRL_REQMODE_ALL /**< A DMA request trigger transfer of a complete cycle. */
155 } LDMA_CtrlReqMode_t;
156
157 /** Source address increment unit size. */
158 typedef enum {
159 ldmaCtrlSrcIncOne = _LDMA_CH_CTRL_SRCINC_ONE, /**< Increment source address by one unit data size. */
160 ldmaCtrlSrcIncTwo = _LDMA_CH_CTRL_SRCINC_TWO, /**< Increment source address by two unit data sizes. */
161 ldmaCtrlSrcIncFour = _LDMA_CH_CTRL_SRCINC_FOUR, /**< Increment source address by four unit data sizes. */
162 ldmaCtrlSrcIncNone = _LDMA_CH_CTRL_SRCINC_NONE /**< Do not increment source address. */
163 } LDMA_CtrlSrcInc_t;
164
165 /** DMA transfer unit size. */
166 typedef enum {
167 ldmaCtrlSizeByte = _LDMA_CH_CTRL_SIZE_BYTE, /**< Each unit transfer is a byte. */
168 ldmaCtrlSizeHalf = _LDMA_CH_CTRL_SIZE_HALFWORD, /**< Each unit transfer is a half-word. */
169 ldmaCtrlSizeWord = _LDMA_CH_CTRL_SIZE_WORD /**< Each unit transfer is a word. */
170 } LDMA_CtrlSize_t;
171
172 /** Destination address increment unit size. */
173 typedef enum {
174 ldmaCtrlDstIncOne = _LDMA_CH_CTRL_DSTINC_ONE, /**< Increment destination address by one unit data size. */
175 ldmaCtrlDstIncTwo = _LDMA_CH_CTRL_DSTINC_TWO, /**< Increment destination address by two unit data sizes. */
176 ldmaCtrlDstIncFour = _LDMA_CH_CTRL_DSTINC_FOUR, /**< Increment destination address by four unit data sizes. */
177 ldmaCtrlDstIncNone = _LDMA_CH_CTRL_DSTINC_NONE /**< Do not increment destination address. */
178 } LDMA_CtrlDstInc_t;
179
180 /** Source addressing mode. */
181 typedef enum {
182 ldmaCtrlSrcAddrModeAbs = _LDMA_CH_CTRL_SRCMODE_ABSOLUTE, /**< Address fetched from a linked structure is absolute. */
183 ldmaCtrlSrcAddrModeRel = _LDMA_CH_CTRL_SRCMODE_RELATIVE /**< Address fetched from a linked structure is relative. */
184 } LDMA_CtrlSrcAddrMode_t;
185
186 /** Destination addressing mode. */
187 typedef enum {
188 ldmaCtrlDstAddrModeAbs = _LDMA_CH_CTRL_DSTMODE_ABSOLUTE, /**< Address fetched from a linked structure is absolute. */
189 ldmaCtrlDstAddrModeRel = _LDMA_CH_CTRL_DSTMODE_RELATIVE /**< Address fetched from a linked structure is relative. */
190 } LDMA_CtrlDstAddrMode_t;
191
192 /** DMA link load address mode. */
193 typedef enum {
194 ldmaLinkModeAbs = _LDMA_CH_LINK_LINKMODE_ABSOLUTE, /**< Link address is an absolute address value. */
195 ldmaLinkModeRel = _LDMA_CH_LINK_LINKMODE_RELATIVE /**< Link address is a two's complement relative address. */
196 } LDMA_LinkMode_t;
197
198 /** Insert extra arbitration slots to increase channel arbitration priority. */
199 typedef enum {
200 ldmaCfgArbSlotsAs1 = _LDMA_CH_CFG_ARBSLOTS_ONE, /**< One arbitration slot selected. */
201 ldmaCfgArbSlotsAs2 = _LDMA_CH_CFG_ARBSLOTS_TWO, /**< Two arbitration slots selected. */
202 ldmaCfgArbSlotsAs4 = _LDMA_CH_CFG_ARBSLOTS_FOUR, /**< Four arbitration slots selected. */
203 ldmaCfgArbSlotsAs8 = _LDMA_CH_CFG_ARBSLOTS_EIGHT /**< Eight arbitration slots selected. */
204 } LDMA_CfgArbSlots_t;
205
206 /** Source address increment sign. */
207 typedef enum {
208 ldmaCfgSrcIncSignPos = _LDMA_CH_CFG_SRCINCSIGN_POSITIVE, /**< Increment source address. */
209 ldmaCfgSrcIncSignNeg = _LDMA_CH_CFG_SRCINCSIGN_NEGATIVE /**< Decrement source address. */
210 } LDMA_CfgSrcIncSign_t;
211
212 /** Destination address increment sign. */
213 typedef enum {
214 ldmaCfgDstIncSignPos = _LDMA_CH_CFG_DSTINCSIGN_POSITIVE, /**< Increment destination address. */
215 ldmaCfgDstIncSignNeg = _LDMA_CH_CFG_DSTINCSIGN_NEGATIVE /**< Decrement destination address. */
216 } LDMA_CfgDstIncSign_t;
217
218 #if defined(_LDMA_CH_CFG_STRUCTBUSPORT_MASK)
219 /** Structure fetch operation bus port. */
220 typedef enum {
221 ldmaCfgStructBusPort0 = _LDMA_CH_CFG_STRUCTBUSPORT_AHBM0, /**< AHB Master 0 port. */
222 ldmaCfgStructBusPort1 = _LDMA_CH_CFG_STRUCTBUSPORT_AHBM1 /**< AHB Master 1 port. */
223 } LDMA_CfgStructBusPort_t;
224 #endif
225
226 #if defined(_LDMA_CH_CFG_SRCBUSPORT_MASK)
227 /** Source operation bus port. */
228 typedef enum {
229 ldmaCfgSrcBusPort0 = _LDMA_CH_CFG_SRCBUSPORT_AHBM0, /**< AHB Master 0 port. */
230 ldmaCfgSrcBusPort1 = _LDMA_CH_CFG_SRCBUSPORT_AHBM1 /**< AHB Master 1 port. */
231 } LDMA_CfgSrcBusPort_t;
232 #endif
233
234 #if defined(_LDMA_CH_CFG_DSTBUSPORT_MASK)
235 /** Destination operation bus port. */
236 typedef enum {
237 ldmaCfgDstBusPort0 = _LDMA_CH_CFG_DSTBUSPORT_AHBM0, /**< AHB Master 0 port. */
238 ldmaCfgDstBusPort1 = _LDMA_CH_CFG_DSTBUSPORT_AHBM1 /**< AHB Master 1 port. */
239 } LDMA_CfgDstBusPort_t;
240 #endif
241
242 #if defined(_LDMA_CH_CTRL_EXTEND_MASK)
243 /** Rules table mode (interleaving destination). */
244 typedef enum {
245 ldmaIlModeAbsolute = _LDMA_CH_XCTRL_ILMODE_ABSOLUTE, /**< Address by value in rules. Size of WORD */
246 ldmaIlModeRelative16 = _LDMA_CH_XCTRL_ILMODE_RELATIVE16, /**< Address by adding rules to DST. size of HALFWORD */
247 ldmaIlModeRelative8 = _LDMA_CH_XCTRL_ILMODE_RELATIVE8 /**< Address by adding rules to DST. size of BYTE */
248 } LDMA_RulesTblMode_t;
249 #endif
250
251 #if defined(LDMAXBAR_COUNT) && (LDMAXBAR_COUNT > 0)
252 /** Peripherals that can trigger LDMA transfers. */
253 typedef enum {
254 ldmaPeripheralSignal_NONE = LDMAXBAR_CH_REQSEL_SOURCESEL_NONE, ///< No peripheral selected for DMA triggering.
255 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_LDMAXBARPRSREQ0
256 ldmaPeripheralSignal_LDMAXBAR_PRSREQ0 = LDMAXBAR_CH_REQSEL_SIGSEL_LDMAXBARPRSREQ0 | LDMAXBAR_CH_REQSEL_SOURCESEL_LDMAXBAR, ///< Trigger on PRS REQ0.
257 #endif
258 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_LDMAXBARPRSREQ1
259 ldmaPeripheralSignal_LDMAXBAR_PRSREQ1 = LDMAXBAR_CH_REQSEL_SIGSEL_LDMAXBARPRSREQ1 | LDMAXBAR_CH_REQSEL_SOURCESEL_LDMAXBAR, ///< Trigger on PRS REQ1.
260 #endif
261 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC0
262 ldmaPeripheralSignal_TIMER0_CC0 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC0 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER0, ///< Trigger on TIMER0_CC0.
263 #endif
264 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC1
265 ldmaPeripheralSignal_TIMER0_CC1 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC1 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER0, ///< Trigger on TIMER0_CC1.
266 #endif
267 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC2
268 ldmaPeripheralSignal_TIMER0_CC2 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0CC2 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER0, ///< Trigger on TIMER0_CC2.
269 #endif
270 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0UFOF
271 ldmaPeripheralSignal_TIMER0_UFOF = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER0UFOF | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER0, ///< Trigger on TIMER0_UFOF.
272 #endif
273 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC0
274 ldmaPeripheralSignal_TIMER1_CC0 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC0 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER1, ///< Trigger on TIMER1_CC0.
275 #endif
276 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC1
277 ldmaPeripheralSignal_TIMER1_CC1 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC1 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER1, ///< Trigger on TIMER1_CC1.
278 #endif
279 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC2
280 ldmaPeripheralSignal_TIMER1_CC2 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1CC2 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER1, ///< Trigger on TIMER1_CC2.
281 #endif
282 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1UFOF
283 ldmaPeripheralSignal_TIMER1_UFOF = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER1UFOF | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER1, ///< Trigger on TIMER1_UFOF.
284 #endif
285 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART0RXDATAV
286 ldmaPeripheralSignal_USART0_RXDATAV = LDMAXBAR_CH_REQSEL_SIGSEL_USART0RXDATAV | LDMAXBAR_CH_REQSEL_SOURCESEL_USART0, ///< Trigger on USART0_RXDATAV.
287 #endif
288 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART0RXDATAVRIGHT
289 ldmaPeripheralSignal_USART0_RXDATAVRIGHT = LDMAXBAR_CH_REQSEL_SIGSEL_USART0RXDATAVRIGHT | LDMAXBAR_CH_REQSEL_SOURCESEL_USART0,///< Trigger on USART0_RXDATAVRIGHT.
290 #endif
291 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXBL
292 ldmaPeripheralSignal_USART0_TXBL = LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXBL | LDMAXBAR_CH_REQSEL_SOURCESEL_USART0, ///< Trigger on USART0_TXBL.
293 #endif
294 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXBLRIGHT
295 ldmaPeripheralSignal_USART0_TXBLRIGHT = LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXBLRIGHT | LDMAXBAR_CH_REQSEL_SOURCESEL_USART0, ///< Trigger on USART0_TXBLRIGHT.
296 #endif
297 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXEMPTY
298 ldmaPeripheralSignal_USART0_TXEMPTY = LDMAXBAR_CH_REQSEL_SIGSEL_USART0TXEMPTY | LDMAXBAR_CH_REQSEL_SOURCESEL_USART0, ///< Trigger on USART0_TXEMPTY.
299 #endif
300 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART1RXDATAV
301 ldmaPeripheralSignal_USART1_RXDATAV = LDMAXBAR_CH_REQSEL_SIGSEL_USART1RXDATAV | LDMAXBAR_CH_REQSEL_SOURCESEL_USART1, ///< Trigger on USART1_RXDATAV.
302 #endif
303 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT
304 ldmaPeripheralSignal_USART1_RXDATAVRIGHT = LDMAXBAR_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT | LDMAXBAR_CH_REQSEL_SOURCESEL_USART1,///< Trigger on USART1_RXDATAVRIGHT.
305 #endif
306 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART1TXBL
307 ldmaPeripheralSignal_USART1_TXBL = LDMAXBAR_CH_REQSEL_SIGSEL_USART1TXBL | LDMAXBAR_CH_REQSEL_SOURCESEL_USART1, ///< Trigger on USART1_TXBL.
308 #endif
309 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART1TXBLRIGHT
310 ldmaPeripheralSignal_USART1_TXBLRIGHT = LDMAXBAR_CH_REQSEL_SIGSEL_USART1TXBLRIGHT | LDMAXBAR_CH_REQSEL_SOURCESEL_USART1, ///< Trigger on USART1_TXBLRIGHT.
311 #endif
312 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART1TXEMPTY
313 ldmaPeripheralSignal_USART1_TXEMPTY = LDMAXBAR_CH_REQSEL_SIGSEL_USART1TXEMPTY | LDMAXBAR_CH_REQSEL_SOURCESEL_USART1, ///< Trigger on USART1_TXEMPTY.
314 #endif
315 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART2RXDATAV
316 ldmaPeripheralSignal_USART2_RXDATAV = LDMAXBAR_CH_REQSEL_SIGSEL_USART2RXDATAV | LDMAXBAR_CH_REQSEL_SOURCESEL_USART2, ///< Trigger on USART2_RXDATAV.
317 #endif
318 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART2RXDATAVRIGHT
319 ldmaPeripheralSignal_USART2_RXDATAVRIGHT = LDMAXBAR_CH_REQSEL_SIGSEL_USART2RXDATAVRIGHT | LDMAXBAR_CH_REQSEL_SOURCESEL_USART2,///< Trigger on USART2_RXDATAVRIGHT.
320 #endif
321 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART2TXBL
322 ldmaPeripheralSignal_USART2_TXBL = LDMAXBAR_CH_REQSEL_SIGSEL_USART2TXBL | LDMAXBAR_CH_REQSEL_SOURCESEL_USART2, ///< Trigger on USART2_TXBL.
323 #endif
324 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART2TXBLRIGHT
325 ldmaPeripheralSignal_USART2_TXBLRIGHT = LDMAXBAR_CH_REQSEL_SIGSEL_USART2TXBLRIGHT | LDMAXBAR_CH_REQSEL_SOURCESEL_USART2, ///< Trigger on USART2_TXBLRIGHT.
326 #endif
327 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_USART2TXEMPTY
328 ldmaPeripheralSignal_USART2_TXEMPTY = LDMAXBAR_CH_REQSEL_SIGSEL_USART2TXEMPTY | LDMAXBAR_CH_REQSEL_SOURCESEL_USART2, ///< Trigger on USART2_TXEMPTY.
329 #endif
330 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_I2C0RXDATAV
331 ldmaPeripheralSignal_I2C0_RXDATAV = LDMAXBAR_CH_REQSEL_SIGSEL_I2C0RXDATAV | LDMAXBAR_CH_REQSEL_SOURCESEL_I2C0, ///< Trigger on I2C0_RXDATAV.
332 #endif
333 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_I2C0TXBL
334 ldmaPeripheralSignal_I2C0_TXBL = LDMAXBAR_CH_REQSEL_SIGSEL_I2C0TXBL | LDMAXBAR_CH_REQSEL_SOURCESEL_I2C0, ///< Trigger on I2C0_TXBL.
335 #endif
336 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_I2C1RXDATAV
337 ldmaPeripheralSignal_I2C1_RXDATAV = LDMAXBAR_CH_REQSEL_SIGSEL_I2C1RXDATAV | LDMAXBAR_CH_REQSEL_SOURCESEL_I2C1, ///< Trigger on I2C1_RXDATAV.
338 #endif
339 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_I2C1TXBL
340 ldmaPeripheralSignal_I2C1_TXBL = LDMAXBAR_CH_REQSEL_SIGSEL_I2C1TXBL | LDMAXBAR_CH_REQSEL_SOURCESEL_I2C1, ///< Trigger on I2C1_TXBL.
341 #endif
342 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_AGCRSSI
343 ldmaPeripheralSignal_AGC_RSSI = LDMAXBAR_CH_REQSEL_SIGSEL_AGCRSSI | LDMAXBAR_CH_REQSEL_SOURCESEL_AGC, ///< Trigger on AGC_RSSI.
344 #endif
345 #if defined(LDMAXBAR_CH_REQSEL_SIGSEL_PDMRXDATAV)
346 ldmaPeripheralSignal_PDM_RXDATAV = LDMAXBAR_CH_REQSEL_SIGSEL_PDMRXDATAV | LDMAXBAR_CH_REQSEL_SOURCESEL_PDM, ///< Trigger on PDM_RXDATAV.
347 #endif
348 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERBOF
349 ldmaPeripheralSignal_PROTIMER_BOF = LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERBOF | LDMAXBAR_CH_REQSEL_SOURCESEL_PROTIMER, ///< Trigger on PROTIMER_BOF.
350 #endif
351 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC0
352 ldmaPeripheralSignal_PROTIMER_CC0 = LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC0 | LDMAXBAR_CH_REQSEL_SOURCESEL_PROTIMER, ///< Trigger on PROTIMER_CC0.
353 #endif
354 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC1
355 ldmaPeripheralSignal_PROTIMER_CC1 = LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC1 | LDMAXBAR_CH_REQSEL_SOURCESEL_PROTIMER, ///< Trigger on PROTIMER_CC1.
356 #endif
357 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC2
358 ldmaPeripheralSignal_PROTIMER_CC2 = LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC2 | LDMAXBAR_CH_REQSEL_SOURCESEL_PROTIMER, ///< Trigger on PROTIMER_CC2.
359 #endif
360 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC3
361 ldmaPeripheralSignal_PROTIMER_CC3 = LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC3 | LDMAXBAR_CH_REQSEL_SOURCESEL_PROTIMER, ///< Trigger on PROTIMER_CC3.
362 #endif
363 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC4
364 ldmaPeripheralSignal_PROTIMER_CC4 = LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERCC4 | LDMAXBAR_CH_REQSEL_SOURCESEL_PROTIMER, ///< Trigger on PROTIMER_CC4.
365 #endif
366 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERPOF
367 ldmaPeripheralSignal_PROTIMER_POF = LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERPOF | LDMAXBAR_CH_REQSEL_SOURCESEL_PROTIMER, ///< Trigger on PROTIMER_POF.
368 #endif
369 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERWOF
370 ldmaPeripheralSignal_PROTIMER_WOF = LDMAXBAR_CH_REQSEL_SIGSEL_PROTIMERWOF | LDMAXBAR_CH_REQSEL_SOURCESEL_PROTIMER, ///< Trigger on PROTIMER_WOF.
371 #endif
372 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_MODEMDEBUG
373 ldmaPeripheralSignal_MODEM_DEBUG = LDMAXBAR_CH_REQSEL_SIGSEL_MODEMDEBUG | LDMAXBAR_CH_REQSEL_SOURCESEL_MODEM, ///< Trigger on MODEM_DEBUG.
374 #endif
375 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_IADC0IADC_SCAN
376 ldmaPeripheralSignal_IADC0_IADC_SCAN = LDMAXBAR_CH_REQSEL_SIGSEL_IADC0IADC_SCAN | LDMAXBAR_CH_REQSEL_SOURCESEL_IADC0, ///< Trigger on IADC0_IADC_SCAN.
377 #endif
378 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_IADC0IADC_SINGLE
379 ldmaPeripheralSignal_IADC0_IADC_SINGLE = LDMAXBAR_CH_REQSEL_SIGSEL_IADC0IADC_SINGLE | LDMAXBAR_CH_REQSEL_SOURCESEL_IADC0, ///< Trigger on IADC0_IADC_SINGLE.
380 #endif
381 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_MSCWDATA
382 ldmaPeripheralSignal_MSC_WDATA = LDMAXBAR_CH_REQSEL_SIGSEL_MSCWDATA | LDMAXBAR_CH_REQSEL_SOURCESEL_MSC, ///< Trigger on MSC_WDATA.
383 #endif
384 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC0
385 ldmaPeripheralSignal_TIMER2_CC0 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC0 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER2, ///< Trigger on TIMER2_CC0.
386 #endif
387 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC1
388 ldmaPeripheralSignal_TIMER2_CC1 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC1 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER2, ///< Trigger on TIMER2_CC1.
389 #endif
390 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC2
391 ldmaPeripheralSignal_TIMER2_CC2 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2CC2 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER2, ///< Trigger on TIMER2_CC2.
392 #endif
393 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2UFOF
394 ldmaPeripheralSignal_TIMER2_UFOF = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER2UFOF | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER2, ///< Trigger on TIMER2_UFOF.
395 #endif
396 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC0
397 ldmaPeripheralSignal_TIMER3_CC0 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC0 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER3, ///< Trigger on TIMER3_CC0.
398 #endif
399 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC1
400 ldmaPeripheralSignal_TIMER3_CC1 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC1 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER3, ///< Trigger on TIMER3_CC1.
401 #endif
402 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC2
403 ldmaPeripheralSignal_TIMER3_CC2 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3CC2 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER3, ///< Trigger on TIMER3_CC2.
404 #endif
405 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3UFOF
406 ldmaPeripheralSignal_TIMER3_UFOF = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER3UFOF | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER3, ///< Trigger on TIMER3_UFOF.
407 #endif
408 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER5CC0
409 ldmaPeripheralSignal_TIMER5_CC0 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER5CC0 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER5, ///< Trigger on TIMER5_CC0.
410 #endif
411 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER5CC1
412 ldmaPeripheralSignal_TIMER5_CC1 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER5CC1 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER5, ///< Trigger on TIMER5_CC1.
413 #endif
414 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER5CC2
415 ldmaPeripheralSignal_TIMER5_CC2 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER5CC2 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER5, ///< Trigger on TIMER5_CC2.
416 #endif
417 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER5UFOF
418 ldmaPeripheralSignal_TIMER5_UFOF = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER5UFOF | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER5, ///< Trigger on TIMER5_UFOF.
419 #endif
420 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER6CC0
421 ldmaPeripheralSignal_TIMER6_CC0 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER6CC0 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER6, ///< Trigger on TIMER6_CC0.
422 #endif
423 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER6CC1
424 ldmaPeripheralSignal_TIMER6_CC1 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER6CC1 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER6, ///< Trigger on TIMER6_CC1.
425 #endif
426 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER6CC2
427 ldmaPeripheralSignal_TIMER6_CC2 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER6CC2 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER6, ///< Trigger on TIMER6_CC2.
428 #endif
429 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER6UFOF
430 ldmaPeripheralSignal_TIMER6_UFOF = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER6UFOF | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER6, ///< Trigger on TIMER6_UFOF.
431 #endif
432 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER7CC0
433 ldmaPeripheralSignal_TIMER7_CC0 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER7CC0 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER7, ///< Trigger on TIMER7_CC0.
434 #endif
435 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER7CC1
436 ldmaPeripheralSignal_TIMER7_CC1 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER7CC1 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER7, ///< Trigger on TIMER7_CC1.
437 #endif
438 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER7CC2
439 ldmaPeripheralSignal_TIMER7_CC2 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER7CC2 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER7, ///< Trigger on TIMER7_CC2.
440 #endif
441 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER7UFOF
442 ldmaPeripheralSignal_TIMER7_UFOF = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER7UFOF | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER7, ///< Trigger on TIMER7_UFOF.
443 #endif
444 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_LCD
445 ldmaPeripheralSignal_LCD = LDMAXBAR_CH_REQSEL_SIGSEL_LCD | LDMAXBAR_CH_REQSEL_SOURCESEL_LCD,
446 #endif
447 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC0
448 ldmaPeripheralSignal_TIMER4_CC0 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC0 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER4, ///< Trigger on TIMER4_CC0.
449 #endif
450 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC1
451 ldmaPeripheralSignal_TIMER4_CC1 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC1 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER4, ///< Trigger on TIMER4_CC1.
452 #endif
453 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC2
454 ldmaPeripheralSignal_TIMER4_CC2 = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4CC2 | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER4, ///< Trigger on TIMER4_CC2.
455 #endif
456 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4UFOF
457 ldmaPeripheralSignal_TIMER4_UFOF = LDMAXBAR_CH_REQSEL_SIGSEL_TIMER4UFOF | LDMAXBAR_CH_REQSEL_SOURCESEL_TIMER4, ///< Trigger on TIMER4_UFOF.
458 #endif
459 #if defined(LDMAXBAR_CH_REQSEL_SIGSEL_VDAC0CH0_REQ)
460 ldmaPeripheralSignal_VDAC0CH0REQ = LDMAXBAR_CH_REQSEL_SIGSEL_VDAC0CH0_REQ | LDMAXBAR_CH_REQSEL_SOURCESEL_VDAC0, ///< Trigger on VDAC0_CH0REQ.
461 #endif
462 #if defined(LDMAXBAR_CH_REQSEL_SIGSEL_VDAC0CH1_REQ)
463 ldmaPeripheralSignal_VDAC0CH1REQ = LDMAXBAR_CH_REQSEL_SIGSEL_VDAC0CH1_REQ | LDMAXBAR_CH_REQSEL_SOURCESEL_VDAC0, ///< Trigger on VDAC0_CH1REQ.
464 #endif
465 #if defined(LDMAXBAR_CH_REQSEL_SIGSEL_VDAC1CH0_REQ)
466 ldmaPeripheralSignal_VDAC1CH0REQ = LDMAXBAR_CH_REQSEL_SIGSEL_VDAC1CH0_REQ | LDMAXBAR_CH_REQSEL_SOURCESEL_VDAC1, ///< Trigger on VDAC1_CH0REQ.
467 #endif
468 #if defined(LDMAXBAR_CH_REQSEL_SIGSEL_VDAC1CH1_REQ)
469 ldmaPeripheralSignal_VDAC1CH1REQ = LDMAXBAR_CH_REQSEL_SIGSEL_VDAC1CH1_REQ | LDMAXBAR_CH_REQSEL_SOURCESEL_VDAC1, ///< Trigger on VDAC1_CH1REQ.
470 #endif
471 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUART0RXFL
472 ldmaPeripheralSignal_EUART0_RXFL = LDMAXBAR_CH_REQSEL_SIGSEL_EUART0RXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUART0, ///< Trigger on EUART0_RXFL.
473 #endif
474 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUART0TXFL
475 ldmaPeripheralSignal_EUART0_TXFL = LDMAXBAR_CH_REQSEL_SIGSEL_EUART0TXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUART0, ///< Trigger on EUART0_TXFL.
476 #endif
477 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUSART0RXFL
478 ldmaPeripheralSignal_EUSART0_RXFL = LDMAXBAR_CH_REQSEL_SIGSEL_EUSART0RXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART0, ///< Trigger on EUSART0_RXFL.
479 #endif
480 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUSART0TXFL
481 ldmaPeripheralSignal_EUSART0_TXFL = LDMAXBAR_CH_REQSEL_SIGSEL_EUSART0TXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART0, ///< Trigger on EUSART0_TXFL.
482 #endif
483 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUSART1RXFL
484 ldmaPeripheralSignal_EUSART1_RXFL = LDMAXBAR_CH_REQSEL_SIGSEL_EUSART1RXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART1, ///< Trigger on EUSART1_RXFL.
485 #endif
486 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUSART1TXFL
487 ldmaPeripheralSignal_EUSART1_TXFL = LDMAXBAR_CH_REQSEL_SIGSEL_EUSART1TXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART1, ///< Trigger on EUSART1_TXFL.
488 #endif
489 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUSART2RXFL
490 ldmaPeripheralSignal_EUSART2_RXFL = LDMAXBAR_CH_REQSEL_SIGSEL_EUSART2RXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART2, ///< Trigger on EUSART2_RXFL.
491 #endif
492 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUSART2TXFL
493 ldmaPeripheralSignal_EUSART2_TXFL = LDMAXBAR_CH_REQSEL_SIGSEL_EUSART2TXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART2, ///< Trigger on EUSART2_TXFL.
494 #endif
495 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUSART3RXFL
496 ldmaPeripheralSignal_EUSART3_RXFL = LDMAXBAR_CH_REQSEL_SIGSEL_EUSART3RXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART3, ///< Trigger on EUSART3_RXFL.
497 #endif
498 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUSART3TXFL
499 ldmaPeripheralSignal_EUSART3_TXFL = LDMAXBAR_CH_REQSEL_SIGSEL_EUSART3TXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART3, ///< Trigger on EUSART3_TXFL.
500 #endif
501 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUSART4RXFL
502 ldmaPeripheralSignal_EUSART4_RXFL = LDMAXBAR_CH_REQSEL_SIGSEL_EUSART4RXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART4, ///< Trigger on EUSART4_RXFL.
503 #endif
504 #if defined LDMAXBAR_CH_REQSEL_SIGSEL_EUSART4TXFL
505 ldmaPeripheralSignal_EUSART4_TXFL = LDMAXBAR_CH_REQSEL_SIGSEL_EUSART4TXFL | LDMAXBAR_CH_REQSEL_SOURCESEL_EUSART4, ///< Trigger on EUSART4_TXFL.
506 #endif
507 #if defined(LDMAXBAR_CH_REQSEL_SIGSEL_LESENSEFIFO)
508 ldmaPeripheralSignal_LESENSE_BUFDATAV = LDMAXBAR_CH_REQSEL_SIGSEL_LESENSEFIFO | LDMAXBAR_CH_REQSEL_SOURCESEL_LESENSE, ///< Trigger on LESENSEFIFO.
509 #endif
510 } LDMA_PeripheralSignal_t;
511
512 #else
513 /** Peripherals that can trigger LDMA transfers. */
514 typedef enum {
515 ldmaPeripheralSignal_NONE = LDMA_CH_REQSEL_SOURCESEL_NONE, ///< No peripheral selected for DMA triggering.
516 #if defined(LDMA_CH_REQSEL_SIGSEL_ADC0SCAN)
517 ldmaPeripheralSignal_ADC0_SCAN = LDMA_CH_REQSEL_SIGSEL_ADC0SCAN | LDMA_CH_REQSEL_SOURCESEL_ADC0, ///< Trigger on ADC0_SCAN.
518 #endif
519 #if defined(LDMA_CH_REQSEL_SIGSEL_ADC0SINGLE)
520 ldmaPeripheralSignal_ADC0_SINGLE = LDMA_CH_REQSEL_SIGSEL_ADC0SINGLE | LDMA_CH_REQSEL_SOURCESEL_ADC0, ///< Trigger on ADC0_SINGLE.
521 #endif
522 #if defined(LDMA_CH_REQSEL_SIGSEL_ADC1SCAN)
523 ldmaPeripheralSignal_ADC1_SCAN = LDMA_CH_REQSEL_SIGSEL_ADC1SCAN | LDMA_CH_REQSEL_SOURCESEL_ADC1, ///< Trigger on ADC1_SCAN.
524 #endif
525 #if defined(LDMA_CH_REQSEL_SIGSEL_ADC1SINGLE)
526 ldmaPeripheralSignal_ADC1_SINGLE = LDMA_CH_REQSEL_SIGSEL_ADC1SINGLE | LDMA_CH_REQSEL_SOURCESEL_ADC1, ///< Trigger on ADC1_SINGLE.
527 #endif
528 #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0RD)
529 ldmaPeripheralSignal_CRYPTO_DATA0RD = LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0RD | LDMA_CH_REQSEL_SOURCESEL_CRYPTO, ///< Trigger on CRYPTO_DATA0RD.
530 #endif
531 #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0WR)
532 ldmaPeripheralSignal_CRYPTO_DATA0WR = LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0WR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO, ///< Trigger on CRYPTO_DATA0WR.
533 #endif
534 #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0XWR)
535 ldmaPeripheralSignal_CRYPTO_DATA0XWR = LDMA_CH_REQSEL_SIGSEL_CRYPTODATA0XWR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO, ///< Trigger on CRYPTO_DATA0XWR.
536 #endif
537 #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTODATA1RD)
538 ldmaPeripheralSignal_CRYPTO_DATA1RD = LDMA_CH_REQSEL_SIGSEL_CRYPTODATA1RD | LDMA_CH_REQSEL_SOURCESEL_CRYPTO, ///< Trigger on CRYPTO_DATA1RD.
539 #endif
540 #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTODATA1WR)
541 ldmaPeripheralSignal_CRYPTO_DATA1WR = LDMA_CH_REQSEL_SIGSEL_CRYPTODATA1WR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO, ///< Trigger on CRYPTO_DATA1WR.
542 #endif
543 #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0RD)
544 ldmaPeripheralSignal_CRYPTO0_DATA0RD = LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0RD | LDMA_CH_REQSEL_SOURCESEL_CRYPTO0, ///< Trigger on CRYPTO0_DATA0RD.
545 #endif
546 #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0WR)
547 ldmaPeripheralSignal_CRYPTO0_DATA0WR = LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0WR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO0, ///< Trigger on CRYPTO0_DATA0WR.
548 #endif
549 #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0XWR)
550 ldmaPeripheralSignal_CRYPTO0_DATA0XWR = LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0XWR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO0, ///< Trigger on CRYPTO0_DATA0XWR.
551 #endif
552 #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1RD)
553 ldmaPeripheralSignal_CRYPTO0_DATA1RD = LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1RD | LDMA_CH_REQSEL_SOURCESEL_CRYPTO0, ///< Trigger on CRYPTO0_DATA1RD.
554 #endif
555 #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1WR)
556 ldmaPeripheralSignal_CRYPTO0_DATA1WR = LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1WR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO0, ///< Trigger on CRYPTO0_DATA1WR.
557 #endif
558 #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0RD)
559 ldmaPeripheralSignal_CRYPTO1_DATA0RD = LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0RD | LDMA_CH_REQSEL_SOURCESEL_CRYPTO1, ///< Trigger on CRYPTO1_DATA0RD.
560 #endif
561 #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0WR)
562 ldmaPeripheralSignal_CRYPTO1_DATA0WR = LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0WR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO1, ///< Trigger on CRYPTO1_DATA0WR.
563 #endif
564 #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0XWR)
565 ldmaPeripheralSignal_CRYPTO1_DATA0XWR = LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA0XWR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO1, ///< Trigger on CRYPTO1_DATA0XWR.
566 #endif
567 #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA1RD)
568 ldmaPeripheralSignal_CRYPTO1_DATA1RD = LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA1RD | LDMA_CH_REQSEL_SOURCESEL_CRYPTO1, ///< Trigger on CRYPTO1_DATA1RD.
569 #endif
570 #if defined(LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA1WR)
571 ldmaPeripheralSignal_CRYPTO1_DATA1WR = LDMA_CH_REQSEL_SIGSEL_CRYPTO1DATA1WR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO1, ///< Trigger on CRYPTO1_DATA1WR.
572 #endif
573 #if defined(LDMA_CH_REQSEL_SIGSEL_CSENBSLN)
574 ldmaPeripheralSignal_CSEN_BSLN = LDMA_CH_REQSEL_SIGSEL_CSENBSLN | LDMA_CH_REQSEL_SOURCESEL_CSEN, ///< Trigger on CSEN_BSLN.
575 #endif
576 #if defined(LDMA_CH_REQSEL_SIGSEL_CSENDATA)
577 ldmaPeripheralSignal_CSEN_DATA = LDMA_CH_REQSEL_SIGSEL_CSENDATA | LDMA_CH_REQSEL_SOURCESEL_CSEN, ///< Trigger on CSEN_DATA.
578 #endif
579 #if defined(LDMA_CH_REQSEL_SIGSEL_EBIPXL0EMPTY)
580 ldmaPeripheralSignal_EBI_PXL0EMPTY = LDMA_CH_REQSEL_SIGSEL_EBIPXL0EMPTY | LDMA_CH_REQSEL_SOURCESEL_EBI, ///< Trigger on EBI_PXL0EMPTY.
581 #endif
582 #if defined(LDMA_CH_REQSEL_SIGSEL_EBIPXL1EMPTY)
583 ldmaPeripheralSignal_EBI_PXL1EMPTY = LDMA_CH_REQSEL_SIGSEL_EBIPXL1EMPTY | LDMA_CH_REQSEL_SOURCESEL_EBI, ///< Trigger on EBI_PXL1EMPTY.
584 #endif
585 #if defined(LDMA_CH_REQSEL_SIGSEL_EBIPXLFULL)
586 ldmaPeripheralSignal_EBI_PXLFULL = LDMA_CH_REQSEL_SIGSEL_EBIPXLFULL | LDMA_CH_REQSEL_SOURCESEL_EBI, ///< Trigger on EBI_PXLFULL.
587 #endif
588 #if defined(LDMA_CH_REQSEL_SIGSEL_EBIDDEMPTY)
589 ldmaPeripheralSignal_EBI_DDEMPTY = LDMA_CH_REQSEL_SIGSEL_EBIDDEMPTY | LDMA_CH_REQSEL_SOURCESEL_EBI, ///< Trigger on EBI_DDEMPTY.
590 #endif
591 #if defined(LDMA_CH_REQSEL_SIGSEL_EBIVSYNC)
592 ldmaPeripheralSignal_EBI_VSYNC = LDMA_CH_REQSEL_SIGSEL_EBIVSYNC | LDMA_CH_REQSEL_SOURCESEL_EBI, ///< Trigger on EBI_VSYNC.
593 #endif
594 #if defined(LDMA_CH_REQSEL_SIGSEL_EBIHSYNC)
595 ldmaPeripheralSignal_EBI_HSYNC = LDMA_CH_REQSEL_SIGSEL_EBIHSYNC | LDMA_CH_REQSEL_SOURCESEL_EBI, ///< Trigger on EBI_HSYNC.
596 #endif
597 #if defined(LDMA_CH_REQSEL_SIGSEL_I2C0RXDATAV)
598 ldmaPeripheralSignal_I2C0_RXDATAV = LDMA_CH_REQSEL_SIGSEL_I2C0RXDATAV | LDMA_CH_REQSEL_SOURCESEL_I2C0, ///< Trigger on I2C0_RXDATAV.
599 #endif
600 #if defined(LDMA_CH_REQSEL_SIGSEL_I2C0TXBL)
601 ldmaPeripheralSignal_I2C0_TXBL = LDMA_CH_REQSEL_SIGSEL_I2C0TXBL | LDMA_CH_REQSEL_SOURCESEL_I2C0, ///< Trigger on I2C0_TXBL.
602 #endif
603 #if defined(LDMA_CH_REQSEL_SIGSEL_I2C1RXDATAV)
604 ldmaPeripheralSignal_I2C1_RXDATAV = LDMA_CH_REQSEL_SIGSEL_I2C1RXDATAV | LDMA_CH_REQSEL_SOURCESEL_I2C1, ///< Trigger on I2C1_RXDATAV.
605 #endif
606 #if defined(LDMA_CH_REQSEL_SIGSEL_I2C1TXBL)
607 ldmaPeripheralSignal_I2C1_TXBL = LDMA_CH_REQSEL_SIGSEL_I2C1TXBL | LDMA_CH_REQSEL_SOURCESEL_I2C1, ///< Trigger on I2C1_TXBL.
608 #endif
609 #if defined(LDMA_CH_REQSEL_SIGSEL_I2C2RXDATAV)
610 ldmaPeripheralSignal_I2C2_RXDATAV = LDMA_CH_REQSEL_SIGSEL_I2C2RXDATAV | LDMA_CH_REQSEL_SOURCESEL_I2C2, ///< Trigger on I2C2_RXDATAV.
611 #endif
612 #if defined(LDMA_CH_REQSEL_SIGSEL_I2C2TXBL)
613 ldmaPeripheralSignal_I2C2_TXBL = LDMA_CH_REQSEL_SIGSEL_I2C2TXBL | LDMA_CH_REQSEL_SOURCESEL_I2C2, ///< Trigger on I2C2_TXBL.
614 #endif
615 #if defined(LDMA_CH_REQSEL_SIGSEL_LESENSEBUFDATAV)
616 ldmaPeripheralSignal_LESENSE_BUFDATAV = LDMA_CH_REQSEL_SIGSEL_LESENSEBUFDATAV | LDMA_CH_REQSEL_SOURCESEL_LESENSE, ///< Trigger on LESENSE_BUFDATAV.
617 #endif
618 #if defined(LDMA_CH_REQSEL_SIGSEL_LEUART0RXDATAV)
619 ldmaPeripheralSignal_LEUART0_RXDATAV = LDMA_CH_REQSEL_SIGSEL_LEUART0RXDATAV | LDMA_CH_REQSEL_SOURCESEL_LEUART0, ///< Trigger on LEUART0_RXDATAV.
620 #endif
621 #if defined(LDMA_CH_REQSEL_SIGSEL_LEUART0TXBL)
622 ldmaPeripheralSignal_LEUART0_TXBL = LDMA_CH_REQSEL_SIGSEL_LEUART0TXBL | LDMA_CH_REQSEL_SOURCESEL_LEUART0, ///< Trigger on LEUART0_TXBL.
623 #endif
624 #if defined(LDMA_CH_REQSEL_SIGSEL_LEUART0TXEMPTY)
625 ldmaPeripheralSignal_LEUART0_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_LEUART0TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_LEUART0, ///< Trigger on LEUART0_TXEMPTY.
626 #endif
627 #if defined(LDMA_CH_REQSEL_SIGSEL_LEUART1RXDATAV)
628 ldmaPeripheralSignal_LEUART1_RXDATAV = LDMA_CH_REQSEL_SIGSEL_LEUART1RXDATAV | LDMA_CH_REQSEL_SOURCESEL_LEUART1, ///< Trigger on LEUART1_RXDATAV.
629 #endif
630 #if defined(LDMA_CH_REQSEL_SIGSEL_LEUART1TXBL)
631 ldmaPeripheralSignal_LEUART1_TXBL = LDMA_CH_REQSEL_SIGSEL_LEUART1TXBL | LDMA_CH_REQSEL_SOURCESEL_LEUART1, ///< Trigger on LEUART1_TXBL.
632 #endif
633 #if defined(LDMA_CH_REQSEL_SIGSEL_LEUART1TXEMPTY)
634 ldmaPeripheralSignal_LEUART1_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_LEUART1TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_LEUART1, ///< Trigger on LEUART1_TXEMPTY.
635 #endif
636 #if defined(LDMA_CH_REQSEL_SIGSEL_MSCWDATA)
637 ldmaPeripheralSignal_MSC_WDATA = LDMA_CH_REQSEL_SIGSEL_MSCWDATA | LDMA_CH_REQSEL_SOURCESEL_MSC, ///< Trigger on MSC_WDATA.
638 #endif
639 #if defined(LDMA_CH_REQSEL_SIGSEL_PDMRXDATAV)
640 ldmaPeripheralSignal_PDM_RXDATAV = LDMA_CH_REQSEL_SIGSEL_PDMRXDATAV | LDMA_CH_REQSEL_SOURCESEL_PDM, ///< Trigger on PDM_RXDATAV.
641 #endif
642 #if defined(LDMA_CH_REQSEL_SIGSEL_PRSREQ0)
643 ldmaPeripheralSignal_PRS_REQ0 = LDMA_CH_REQSEL_SIGSEL_PRSREQ0 | LDMA_CH_REQSEL_SOURCESEL_PRS, ///< Trigger on PRS_REQ0.
644 #endif
645 #if defined(LDMA_CH_REQSEL_SIGSEL_PRSREQ1)
646 ldmaPeripheralSignal_PRS_REQ1 = LDMA_CH_REQSEL_SIGSEL_PRSREQ1 | LDMA_CH_REQSEL_SOURCESEL_PRS, ///< Trigger on PRS_REQ1.
647 #endif
648 #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER0CC0)
649 ldmaPeripheralSignal_TIMER0_CC0 = LDMA_CH_REQSEL_SIGSEL_TIMER0CC0 | LDMA_CH_REQSEL_SOURCESEL_TIMER0, ///< Trigger on TIMER0_CC0.
650 #endif
651 #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER0CC1)
652 ldmaPeripheralSignal_TIMER0_CC1 = LDMA_CH_REQSEL_SIGSEL_TIMER0CC1 | LDMA_CH_REQSEL_SOURCESEL_TIMER0, ///< Trigger on TIMER0_CC1.
653 #endif
654 #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER0CC2)
655 ldmaPeripheralSignal_TIMER0_CC2 = LDMA_CH_REQSEL_SIGSEL_TIMER0CC2 | LDMA_CH_REQSEL_SOURCESEL_TIMER0, ///< Trigger on TIMER0_CC2.
656 #endif
657 #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER0UFOF)
658 ldmaPeripheralSignal_TIMER0_UFOF = LDMA_CH_REQSEL_SIGSEL_TIMER0UFOF | LDMA_CH_REQSEL_SOURCESEL_TIMER0, ///< Trigger on TIMER0_UFOF.
659 #endif
660 #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER1CC0)
661 ldmaPeripheralSignal_TIMER1_CC0 = LDMA_CH_REQSEL_SIGSEL_TIMER1CC0 | LDMA_CH_REQSEL_SOURCESEL_TIMER1, ///< Trigger on TIMER1_CC0.
662 #endif
663 #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER1CC1)
664 ldmaPeripheralSignal_TIMER1_CC1 = LDMA_CH_REQSEL_SIGSEL_TIMER1CC1 | LDMA_CH_REQSEL_SOURCESEL_TIMER1, ///< Trigger on TIMER1_CC1.
665 #endif
666 #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER1CC2)
667 ldmaPeripheralSignal_TIMER1_CC2 = LDMA_CH_REQSEL_SIGSEL_TIMER1CC2 | LDMA_CH_REQSEL_SOURCESEL_TIMER1, ///< Trigger on TIMER1_CC2.
668 #endif
669 #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER1CC3)
670 ldmaPeripheralSignal_TIMER1_CC3 = LDMA_CH_REQSEL_SIGSEL_TIMER1CC3 | LDMA_CH_REQSEL_SOURCESEL_TIMER1, ///< Trigger on TIMER1_CC3.
671 #endif
672 #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER1UFOF)
673 ldmaPeripheralSignal_TIMER1_UFOF = LDMA_CH_REQSEL_SIGSEL_TIMER1UFOF | LDMA_CH_REQSEL_SOURCESEL_TIMER1, ///< Trigger on TIMER1_UFOF.
674 #endif
675 #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER2CC0)
676 ldmaPeripheralSignal_TIMER2_CC0 = LDMA_CH_REQSEL_SIGSEL_TIMER2CC0 | LDMA_CH_REQSEL_SOURCESEL_TIMER2, ///< Trigger on TIMER2_CC0.
677 #endif
678 #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER2CC1)
679 ldmaPeripheralSignal_TIMER2_CC1 = LDMA_CH_REQSEL_SIGSEL_TIMER2CC1 | LDMA_CH_REQSEL_SOURCESEL_TIMER2, ///< Trigger on TIMER2_CC1.
680 #endif
681 #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER2CC2)
682 ldmaPeripheralSignal_TIMER2_CC2 = LDMA_CH_REQSEL_SIGSEL_TIMER2CC2 | LDMA_CH_REQSEL_SOURCESEL_TIMER2, ///< Trigger on TIMER2_CC2.
683 #endif
684 #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER2UFOF)
685 ldmaPeripheralSignal_TIMER2_UFOF = LDMA_CH_REQSEL_SIGSEL_TIMER2UFOF | LDMA_CH_REQSEL_SOURCESEL_TIMER2, ///< Trigger on TIMER2_UFOF.
686 #endif
687 #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER3CC0)
688 ldmaPeripheralSignal_TIMER3_CC0 = LDMA_CH_REQSEL_SIGSEL_TIMER3CC0 | LDMA_CH_REQSEL_SOURCESEL_TIMER3, ///< Trigger on TIMER3_CC0.
689 #endif
690 #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER3CC1)
691 ldmaPeripheralSignal_TIMER3_CC1 = LDMA_CH_REQSEL_SIGSEL_TIMER3CC1 | LDMA_CH_REQSEL_SOURCESEL_TIMER3, ///< Trigger on TIMER3_CC1.
692 #endif
693 #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER3CC2)
694 ldmaPeripheralSignal_TIMER3_CC2 = LDMA_CH_REQSEL_SIGSEL_TIMER3CC2 | LDMA_CH_REQSEL_SOURCESEL_TIMER3, ///< Trigger on TIMER3_CC2.
695 #endif
696 #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER3UFOF)
697 ldmaPeripheralSignal_TIMER3_UFOF = LDMA_CH_REQSEL_SIGSEL_TIMER3UFOF | LDMA_CH_REQSEL_SOURCESEL_TIMER3, ///< Trigger on TIMER3_UFOF.
698 #endif
699 #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER4CC0)
700 ldmaPeripheralSignal_TIMER4_CC0 = LDMA_CH_REQSEL_SIGSEL_TIMER4CC0 | LDMA_CH_REQSEL_SOURCESEL_TIMER4, ///< Trigger on TIMER4_CC0.
701 #endif
702 #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER4CC1)
703 ldmaPeripheralSignal_TIMER4_CC1 = LDMA_CH_REQSEL_SIGSEL_TIMER4CC1 | LDMA_CH_REQSEL_SOURCESEL_TIMER4, ///< Trigger on TIMER4_CC1.
704 #endif
705 #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER4CC2)
706 ldmaPeripheralSignal_TIMER4_CC2 = LDMA_CH_REQSEL_SIGSEL_TIMER4CC2 | LDMA_CH_REQSEL_SOURCESEL_TIMER4, ///< Trigger on TIMER4_CC2.
707 #endif
708 #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER4UFOF)
709 ldmaPeripheralSignal_TIMER4_UFOF = LDMA_CH_REQSEL_SIGSEL_TIMER4UFOF | LDMA_CH_REQSEL_SOURCESEL_TIMER4, ///< Trigger on TIMER4_UFOF.
710 #endif
711 #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER5CC0)
712 ldmaPeripheralSignal_TIMER5_CC0 = LDMA_CH_REQSEL_SIGSEL_TIMER5CC0 | LDMA_CH_REQSEL_SOURCESEL_TIMER5, ///< Trigger on TIMER5_CC0.
713 #endif
714 #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER5CC1)
715 ldmaPeripheralSignal_TIMER5_CC1 = LDMA_CH_REQSEL_SIGSEL_TIMER5CC1 | LDMA_CH_REQSEL_SOURCESEL_TIMER5, ///< Trigger on TIMER5_CC1.
716 #endif
717 #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER5CC2)
718 ldmaPeripheralSignal_TIMER5_CC2 = LDMA_CH_REQSEL_SIGSEL_TIMER5CC2 | LDMA_CH_REQSEL_SOURCESEL_TIMER5, ///< Trigger on TIMER5_CC2.
719 #endif
720 #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER5UFOF)
721 ldmaPeripheralSignal_TIMER5_UFOF = LDMA_CH_REQSEL_SIGSEL_TIMER5UFOF | LDMA_CH_REQSEL_SOURCESEL_TIMER5, ///< Trigger on TIMER5_UFOF.
722 #endif
723 #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER6CC0)
724 ldmaPeripheralSignal_TIMER6_CC0 = LDMA_CH_REQSEL_SIGSEL_TIMER6CC0 | LDMA_CH_REQSEL_SOURCESEL_TIMER6, ///< Trigger on TIMER6_CC0.
725 #endif
726 #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER6CC1)
727 ldmaPeripheralSignal_TIMER6_CC1 = LDMA_CH_REQSEL_SIGSEL_TIMER6CC1 | LDMA_CH_REQSEL_SOURCESEL_TIMER6, ///< Trigger on TIMER6_CC1.
728 #endif
729 #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER6CC2)
730 ldmaPeripheralSignal_TIMER6_CC2 = LDMA_CH_REQSEL_SIGSEL_TIMER6CC2 | LDMA_CH_REQSEL_SOURCESEL_TIMER6, ///< Trigger on TIMER6_CC2.
731 #endif
732 #if defined(LDMA_CH_REQSEL_SIGSEL_TIMER6UFOF)
733 ldmaPeripheralSignal_TIMER6_UFOF = LDMA_CH_REQSEL_SIGSEL_TIMER6UFOF | LDMA_CH_REQSEL_SOURCESEL_TIMER6, ///< Trigger on TIMER6_UFOF.
734 #endif
735 #if defined(LDMA_CH_REQSEL_SIGSEL_UART0RXDATAV)
736 ldmaPeripheralSignal_UART0_RXDATAV = LDMA_CH_REQSEL_SIGSEL_UART0RXDATAV | LDMA_CH_REQSEL_SOURCESEL_UART0, ///< Trigger on UART0_RXDATAV.
737 #endif
738 #if defined(LDMA_CH_REQSEL_SIGSEL_UART0TXBL)
739 ldmaPeripheralSignal_UART0_TXBL = LDMA_CH_REQSEL_SIGSEL_UART0TXBL | LDMA_CH_REQSEL_SOURCESEL_UART0, ///< Trigger on UART0_TXBL.
740 #endif
741 #if defined(LDMA_CH_REQSEL_SIGSEL_UART0TXEMPTY)
742 ldmaPeripheralSignal_UART0_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_UART0TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_UART0, ///< Trigger on UART0_TXEMPTY.
743 #endif
744 #if defined(LDMA_CH_REQSEL_SIGSEL_UART1RXDATAV)
745 ldmaPeripheralSignal_UART1_RXDATAV = LDMA_CH_REQSEL_SIGSEL_UART1RXDATAV | LDMA_CH_REQSEL_SOURCESEL_UART1, ///< Trigger on UART1_RXDATAV.
746 #endif
747 #if defined(LDMA_CH_REQSEL_SIGSEL_UART1TXBL)
748 ldmaPeripheralSignal_UART1_TXBL = LDMA_CH_REQSEL_SIGSEL_UART1TXBL | LDMA_CH_REQSEL_SOURCESEL_UART1, ///< Trigger on UART1_TXBL.
749 #endif
750 #if defined(LDMA_CH_REQSEL_SIGSEL_UART1TXEMPTY)
751 ldmaPeripheralSignal_UART1_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_UART1TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_UART1, ///< Trigger on UART1_TXEMPTY.
752 #endif
753 #if defined(LDMA_CH_REQSEL_SIGSEL_USART0RXDATAV)
754 ldmaPeripheralSignal_USART0_RXDATAV = LDMA_CH_REQSEL_SIGSEL_USART0RXDATAV | LDMA_CH_REQSEL_SOURCESEL_USART0, ///< Trigger on USART0_RXDATAV.
755 #endif
756 #if defined(LDMA_CH_REQSEL_SIGSEL_USART0TXBL)
757 ldmaPeripheralSignal_USART0_TXBL = LDMA_CH_REQSEL_SIGSEL_USART0TXBL | LDMA_CH_REQSEL_SOURCESEL_USART0, ///< Trigger on USART0_TXBL.
758 #endif
759 #if defined(LDMA_CH_REQSEL_SIGSEL_USART0TXEMPTY)
760 ldmaPeripheralSignal_USART0_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_USART0TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_USART0, ///< Trigger on USART0_TXEMPTY.
761 #endif
762 #if defined(LDMA_CH_REQSEL_SIGSEL_USART1RXDATAV)
763 ldmaPeripheralSignal_USART1_RXDATAV = LDMA_CH_REQSEL_SIGSEL_USART1RXDATAV | LDMA_CH_REQSEL_SOURCESEL_USART1, ///< Trigger on USART1_RXDATAV.
764 #endif
765 #if defined(LDMA_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT)
766 ldmaPeripheralSignal_USART1_RXDATAVRIGHT = LDMA_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT | LDMA_CH_REQSEL_SOURCESEL_USART1, ///< Trigger on USART1_RXDATAVRIGHT.
767 #endif
768 #if defined(LDMA_CH_REQSEL_SIGSEL_USART1TXBL)
769 ldmaPeripheralSignal_USART1_TXBL = LDMA_CH_REQSEL_SIGSEL_USART1TXBL | LDMA_CH_REQSEL_SOURCESEL_USART1, ///< Trigger on USART1_TXBL.
770 #endif
771 #if defined(LDMA_CH_REQSEL_SIGSEL_USART1TXBLRIGHT)
772 ldmaPeripheralSignal_USART1_TXBLRIGHT = LDMA_CH_REQSEL_SIGSEL_USART1TXBLRIGHT | LDMA_CH_REQSEL_SOURCESEL_USART1, ///< Trigger on USART1_TXBLRIGHT.
773 #endif
774 #if defined(LDMA_CH_REQSEL_SIGSEL_USART1TXEMPTY)
775 ldmaPeripheralSignal_USART1_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_USART1TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_USART1, ///< Trigger on USART1_TXEMPTY.
776 #endif
777 #if defined(LDMA_CH_REQSEL_SIGSEL_USART2RXDATAV)
778 ldmaPeripheralSignal_USART2_RXDATAV = LDMA_CH_REQSEL_SIGSEL_USART2RXDATAV | LDMA_CH_REQSEL_SOURCESEL_USART2, ///< Trigger on USART2_RXDATAV.
779 #endif
780 #if defined(LDMA_CH_REQSEL_SIGSEL_USART2TXBL)
781 ldmaPeripheralSignal_USART2_TXBL = LDMA_CH_REQSEL_SIGSEL_USART2TXBL | LDMA_CH_REQSEL_SOURCESEL_USART2, ///< Trigger on USART2_TXBL.
782 #endif
783 #if defined(LDMA_CH_REQSEL_SIGSEL_USART2TXEMPTY)
784 ldmaPeripheralSignal_USART2_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_USART2TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_USART2, ///< Trigger on USART2_TXEMPTY.
785 #endif
786 #if defined(LDMA_CH_REQSEL_SIGSEL_USART3RXDATAV)
787 ldmaPeripheralSignal_USART3_RXDATAV = LDMA_CH_REQSEL_SIGSEL_USART3RXDATAV | LDMA_CH_REQSEL_SOURCESEL_USART3, ///< Trigger on USART3_RXDATAV.
788 #endif
789 #if defined(LDMA_CH_REQSEL_SIGSEL_USART3RXDATAVRIGHT)
790 ldmaPeripheralSignal_USART3_RXDATAVRIGHT = LDMA_CH_REQSEL_SIGSEL_USART3RXDATAVRIGHT | LDMA_CH_REQSEL_SOURCESEL_USART3, ///< Trigger on USART3_RXDATAVRIGHT.
791 #endif
792 #if defined(LDMA_CH_REQSEL_SIGSEL_USART3TXBL)
793 ldmaPeripheralSignal_USART3_TXBL = LDMA_CH_REQSEL_SIGSEL_USART3TXBL | LDMA_CH_REQSEL_SOURCESEL_USART3, ///< Trigger on USART3_TXBL.
794 #endif
795 #if defined(LDMA_CH_REQSEL_SIGSEL_USART3TXBLRIGHT)
796 ldmaPeripheralSignal_USART3_TXBLRIGHT = LDMA_CH_REQSEL_SIGSEL_USART3TXBLRIGHT | LDMA_CH_REQSEL_SOURCESEL_USART3, ///< Trigger on USART3_TXBLRIGHT.
797 #endif
798 #if defined(LDMA_CH_REQSEL_SIGSEL_USART3TXEMPTY)
799 ldmaPeripheralSignal_USART3_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_USART3TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_USART3, ///< Trigger on USART3_TXEMPTY.
800 #endif
801 #if defined(LDMA_CH_REQSEL_SIGSEL_USART4RXDATAV)
802 ldmaPeripheralSignal_USART4_RXDATAV = LDMA_CH_REQSEL_SIGSEL_USART4RXDATAV | LDMA_CH_REQSEL_SOURCESEL_USART4, ///< Trigger on USART4_RXDATAV.
803 #endif
804 #if defined(LDMA_CH_REQSEL_SIGSEL_USART4RXDATAVRIGHT)
805 ldmaPeripheralSignal_USART4_RXDATAVRIGHT = LDMA_CH_REQSEL_SIGSEL_USART4RXDATAVRIGHT | LDMA_CH_REQSEL_SOURCESEL_USART4, ///< Trigger on USART4_RXDATAVRIGHT.
806 #endif
807 #if defined(LDMA_CH_REQSEL_SIGSEL_USART4TXBL)
808 ldmaPeripheralSignal_USART4_TXBL = LDMA_CH_REQSEL_SIGSEL_USART4TXBL | LDMA_CH_REQSEL_SOURCESEL_USART4, ///< Trigger on USART4_TXBL.
809 #endif
810 #if defined(LDMA_CH_REQSEL_SIGSEL_USART4TXBLRIGHT)
811 ldmaPeripheralSignal_USART4_TXBLRIGHT = LDMA_CH_REQSEL_SIGSEL_USART4TXBLRIGHT | LDMA_CH_REQSEL_SOURCESEL_USART4, ///< Trigger on USART4_TXBLRIGHT.
812 #endif
813 #if defined(LDMA_CH_REQSEL_SIGSEL_USART4TXEMPTY)
814 ldmaPeripheralSignal_USART4_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_USART4TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_USART4, ///< Trigger on USART4_TXEMPTY.
815 #endif
816 #if defined(LDMA_CH_REQSEL_SIGSEL_USART5RXDATAV)
817 ldmaPeripheralSignal_USART5_RXDATAV = LDMA_CH_REQSEL_SIGSEL_USART5RXDATAV | LDMA_CH_REQSEL_SOURCESEL_USART5, ///< Trigger on USART5_RXDATAV.
818 #endif
819 #if defined(LDMA_CH_REQSEL_SIGSEL_USART5TXBL)
820 ldmaPeripheralSignal_USART5_TXBL = LDMA_CH_REQSEL_SIGSEL_USART5TXBL | LDMA_CH_REQSEL_SOURCESEL_USART5, ///< Trigger on USART5_TXBL.
821 #endif
822 #if defined(LDMA_CH_REQSEL_SIGSEL_USART5TXEMPTY)
823 ldmaPeripheralSignal_USART5_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_USART5TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_USART5, ///< Trigger on USART5_TXEMPTY.
824 #endif
825 #if defined(LDMA_CH_REQSEL_SIGSEL_VDAC0CH0)
826 ldmaPeripheralSignal_VDAC0_CH0 = LDMA_CH_REQSEL_SIGSEL_VDAC0CH0 | LDMA_CH_REQSEL_SOURCESEL_VDAC0, ///< Trigger on VDAC0_CH0.
827 #endif
828 #if defined(LDMA_CH_REQSEL_SIGSEL_VDAC0CH1)
829 ldmaPeripheralSignal_VDAC0_CH1 = LDMA_CH_REQSEL_SIGSEL_VDAC0CH1 | LDMA_CH_REQSEL_SOURCESEL_VDAC0, ///< Trigger on VDAC0_CH1.
830 #endif
831 #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER0CC0)
832 ldmaPeripheralSignal_WTIMER0_CC0 = LDMA_CH_REQSEL_SIGSEL_WTIMER0CC0 | LDMA_CH_REQSEL_SOURCESEL_WTIMER0, ///< Trigger on WTIMER0_CC0.
833 #endif
834 #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER0CC1)
835 ldmaPeripheralSignal_WTIMER0_CC1 = LDMA_CH_REQSEL_SIGSEL_WTIMER0CC1 | LDMA_CH_REQSEL_SOURCESEL_WTIMER0, ///< Trigger on WTIMER0_CC1.
836 #endif
837 #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER0CC2)
838 ldmaPeripheralSignal_WTIMER0_CC2 = LDMA_CH_REQSEL_SIGSEL_WTIMER0CC2 | LDMA_CH_REQSEL_SOURCESEL_WTIMER0, ///< Trigger on WTIMER0_CC2.
839 #endif
840 #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER0UFOF)
841 ldmaPeripheralSignal_WTIMER0_UFOF = LDMA_CH_REQSEL_SIGSEL_WTIMER0UFOF | LDMA_CH_REQSEL_SOURCESEL_WTIMER0, ///< Trigger on WTIMER0_UFOF.
842 #endif
843 #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER1CC0)
844 ldmaPeripheralSignal_WTIMER1_CC0 = LDMA_CH_REQSEL_SIGSEL_WTIMER1CC0 | LDMA_CH_REQSEL_SOURCESEL_WTIMER1, ///< Trigger on WTIMER1_CC0.
845 #endif
846 #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER1CC1)
847 ldmaPeripheralSignal_WTIMER1_CC1 = LDMA_CH_REQSEL_SIGSEL_WTIMER1CC1 | LDMA_CH_REQSEL_SOURCESEL_WTIMER1, ///< Trigger on WTIMER1_CC1.
848 #endif
849 #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER1CC2)
850 ldmaPeripheralSignal_WTIMER1_CC2 = LDMA_CH_REQSEL_SIGSEL_WTIMER1CC2 | LDMA_CH_REQSEL_SOURCESEL_WTIMER1, ///< Trigger on WTIMER1_CC2.
851 #endif
852 #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER1CC3)
853 ldmaPeripheralSignal_WTIMER1_CC3 = LDMA_CH_REQSEL_SIGSEL_WTIMER1CC3 | LDMA_CH_REQSEL_SOURCESEL_WTIMER1, ///< Trigger on WTIMER1_CC3.
854 #endif
855 #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER1UFOF)
856 ldmaPeripheralSignal_WTIMER1_UFOF = LDMA_CH_REQSEL_SIGSEL_WTIMER1UFOF | LDMA_CH_REQSEL_SOURCESEL_WTIMER1, ///< Trigger on WTIMER1_UFOF.
857 #endif
858 #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER2CC0)
859 ldmaPeripheralSignal_WTIMER2_CC0 = LDMA_CH_REQSEL_SIGSEL_WTIMER2CC0 | LDMA_CH_REQSEL_SOURCESEL_WTIMER2, ///< Trigger on WTIMER2_CC0.
860 #endif
861 #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER2CC1)
862 ldmaPeripheralSignal_WTIMER2_CC1 = LDMA_CH_REQSEL_SIGSEL_WTIMER2CC1 | LDMA_CH_REQSEL_SOURCESEL_WTIMER2, ///< Trigger on WTIMER2_CC1.
863 #endif
864 #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER2CC2)
865 ldmaPeripheralSignal_WTIMER2_CC2 = LDMA_CH_REQSEL_SIGSEL_WTIMER2CC2 | LDMA_CH_REQSEL_SOURCESEL_WTIMER2, ///< Trigger on WTIMER2_CC2.
866 #endif
867 #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER2UFOF)
868 ldmaPeripheralSignal_WTIMER2_UFOF = LDMA_CH_REQSEL_SIGSEL_WTIMER2UFOF | LDMA_CH_REQSEL_SOURCESEL_WTIMER2, ///< Trigger on WTIMER2_UFOF.
869 #endif
870 #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER3CC0)
871 ldmaPeripheralSignal_WTIMER3_CC0 = LDMA_CH_REQSEL_SIGSEL_WTIMER3CC0 | LDMA_CH_REQSEL_SOURCESEL_WTIMER3, ///< Trigger on WTIMER3_CC0.
872 #endif
873 #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER3CC1)
874 ldmaPeripheralSignal_WTIMER3_CC1 = LDMA_CH_REQSEL_SIGSEL_WTIMER3CC1 | LDMA_CH_REQSEL_SOURCESEL_WTIMER3, ///< Trigger on WTIMER3_CC1.
875 #endif
876 #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER3CC2)
877 ldmaPeripheralSignal_WTIMER3_CC2 = LDMA_CH_REQSEL_SIGSEL_WTIMER3CC2 | LDMA_CH_REQSEL_SOURCESEL_WTIMER3, ///< Trigger on WTIMER3_CC2.
878 #endif
879 #if defined(LDMA_CH_REQSEL_SIGSEL_WTIMER3UFOF)
880 ldmaPeripheralSignal_WTIMER3_UFOF = LDMA_CH_REQSEL_SIGSEL_WTIMER3UFOF | LDMA_CH_REQSEL_SOURCESEL_WTIMER3, ///< Trigger on WTIMER3_UFOF.
881 #endif
882 } LDMA_PeripheralSignal_t;
883 #endif
884
885 /*******************************************************************************
886 ******************************* STRUCTS ***********************************
887 ******************************************************************************/
888
889 /**
890 * @brief
891 * DMA descriptor.
892 * @details
893 * The LDMA DMA controller supports three different DMA descriptors. Each
894 * consists of four WORDs which map directly onto HW control registers for a
895 * given DMA channel. The three descriptor types are XFER, SYNC and WRI.
896 * Refer to the reference manual for further information.
897 */
898 typedef union {
899 /**
900 * TRANSFER DMA descriptor, this is the only descriptor type which can be
901 * used to start a DMA transfer.
902 */
903 struct {
904 uint32_t structType : 2; /**< Set to 0 to select XFER descriptor type. */
905 uint32_t reserved0 : 1; /**< Reserved. */
906 uint32_t structReq : 1; /**< DMA transfer trigger during LINKLOAD. */
907 uint32_t xferCnt : 11; /**< Transfer count minus one. */
908 uint32_t byteSwap : 1; /**< Enable byte swapping transfers. */
909 uint32_t blockSize : 4; /**< Number of unit transfers per arbitration cycle. */
910 uint32_t doneIfs : 1; /**< Generate interrupt when done. */
911 uint32_t reqMode : 1; /**< Block or cycle transfer selector. */
912 uint32_t decLoopCnt : 1; /**< Enable looped transfers. */
913 uint32_t ignoreSrec : 1; /**< Ignore single requests. */
914 uint32_t srcInc : 2; /**< Source address increment unit size. */
915 uint32_t size : 2; /**< DMA transfer unit size. */
916 uint32_t dstInc : 2; /**< Destination address increment unit size. */
917 uint32_t srcAddrMode : 1; /**< Source addressing mode. */
918 uint32_t dstAddrMode : 1; /**< Destination addressing mode. */
919
920 uint32_t srcAddr; /**< DMA source address. */
921 uint32_t dstAddr; /**< DMA destination address. */
922
923 uint32_t linkMode : 1; /**< Select absolute or relative link address. */
924 uint32_t link : 1; /**< Enable LINKLOAD when transfer is done. */
925 int32_t linkAddr : 30; /**< Address of next (linked) descriptor. */
926 } xfer;
927
928 /** SYNCHRONIZE DMA descriptor, used for intra channel transfer
929 * synchronization.
930 */
931 struct {
932 uint32_t structType : 2; /**< Set to 1 to select SYNC descriptor type. */
933 uint32_t reserved0 : 1; /**< Reserved. */
934 uint32_t structReq : 1; /**< DMA transfer trigger during LINKLOAD. */
935 uint32_t xferCnt : 11; /**< Transfer count minus one. */
936 uint32_t byteSwap : 1; /**< Enable byte swapping transfers. */
937 uint32_t blockSize : 4; /**< Number of unit transfers per arbitration cycle. */
938 uint32_t doneIfs : 1; /**< Generate interrupt when done. */
939 uint32_t reqMode : 1; /**< Block or cycle transfer selector. */
940 uint32_t decLoopCnt : 1; /**< Enable looped transfers. */
941 uint32_t ignoreSrec : 1; /**< Ignore single requests. */
942 uint32_t srcInc : 2; /**< Source address increment unit size. */
943 uint32_t size : 2; /**< DMA transfer unit size. */
944 uint32_t dstInc : 2; /**< Destination address increment unit size. */
945 uint32_t srcAddrMode : 1; /**< Source addressing mode. */
946 uint32_t dstAddrMode : 1; /**< Destination addressing mode. */
947
948 uint32_t syncSet : 8; /**< Set bits in LDMA_CTRL.SYNCTRIG register. */
949 uint32_t syncClr : 8; /**< Clear bits in LDMA_CTRL.SYNCTRIG register. */
950 uint32_t reserved1 : 16; /**< Reserved. */
951 uint32_t matchVal : 8; /**< Sync trigger match value. */
952 uint32_t matchEn : 8; /**< Sync trigger match enable. */
953 uint32_t reserved2 : 16; /**< Reserved. */
954
955 uint32_t linkMode : 1; /**< Select absolute or relative link address. */
956 uint32_t link : 1; /**< Enable LINKLOAD when transfer is done. */
957 int32_t linkAddr : 30; /**< Address of next (linked) descriptor. */
958 } sync;
959
960 /** WRITE DMA descriptor, used for write immediate operations. */
961 struct {
962 uint32_t structType : 2; /**< Set to 2 to select WRITE descriptor type. */
963 uint32_t reserved0 : 1; /**< Reserved. */
964 uint32_t structReq : 1; /**< DMA transfer trigger during LINKLOAD. */
965 uint32_t xferCnt : 11; /**< Transfer count minus one. */
966 uint32_t byteSwap : 1; /**< Enable byte swapping transfers. */
967 uint32_t blockSize : 4; /**< Number of unit transfers per arbitration cycle. */
968 uint32_t doneIfs : 1; /**< Generate interrupt when done. */
969 uint32_t reqMode : 1; /**< Block or cycle transfer selector. */
970 uint32_t decLoopCnt : 1; /**< Enable looped transfers. */
971 uint32_t ignoreSrec : 1; /**< Ignore single requests. */
972 uint32_t srcInc : 2; /**< Source address increment unit size. */
973 uint32_t size : 2; /**< DMA transfer unit size. */
974 uint32_t dstInc : 2; /**< Destination address increment unit size. */
975 uint32_t srcAddrMode : 1; /**< Source addressing mode. */
976 uint32_t dstAddrMode : 1; /**< Destination addressing mode. */
977
978 uint32_t immVal; /**< Data to be written at dstAddr. */
979 uint32_t dstAddr; /**< DMA write destination address. */
980
981 uint32_t linkMode : 1; /**< Select absolute or relative link address. */
982 uint32_t link : 1; /**< Enable LINKLOAD when transfer is done. */
983 int32_t linkAddr : 30; /**< Address of next (linked) descriptor. */
984 } wri;
985 } LDMA_Descriptor_t;
986
987 #if defined(_LDMA_CH_CTRL_EXTEND_MASK)
988 /**
989 * @brief
990 * DMA extended descriptor.
991 * @details
992 * The extended descriptor adds additional fields for the extended features
993 * available on the MMLDMA peripheral: destination interleaving and bufferable.
994 * The same three different DMA descriptors supported by the LDMA DMA controller
995 * are available. Each consists of seven WORDs (instead of four in non-extended
996 * descriptors) which map directly onto HW control registers for a given DMA
997 * channel. The three descriptor types are XFER, SYNC and WRI. But the
998 * extended fields are true only for XFER. The extended fields are the following:
999 *
1000 * +- +- CTRL
1001 * | Original | SRC
1002 * | Structure | DST
1003 * Extended | +- LINK
1004 * Structure | XCTRL
1005 * | Reserved for future usage
1006 * +- ILSRC
1007 *
1008 * Refer to the reference manual for further information.
1009 */
1010 typedef struct {
1011 uint32_t structType : 2; /**< Set to 0 to select XFER descriptor type. */
1012 uint32_t extend : 1; /**< Extend data structure. */
1013 uint32_t structReq : 1; /**< DMA transfer trigger during LINKLOAD. */
1014 uint32_t xferCnt : 11; /**< Transfer count minus one. */
1015 uint32_t byteSwap : 1; /**< Enable byte swapping transfers. */
1016 uint32_t blockSize : 4; /**< Number of unit transfers per arbitration cycle. */
1017 uint32_t doneIfs : 1; /**< Generate interrupt when done. */
1018 uint32_t reqMode : 1; /**< Block or cycle transfer selector. */
1019 uint32_t decLoopCnt : 1; /**< Enable looped transfers. */
1020 uint32_t ignoreSrec : 1; /**< Ignore single requests. */
1021 uint32_t srcInc : 2; /**< Source address increment unit size. */
1022 uint32_t size : 2; /**< DMA transfer unit size. */
1023 uint32_t dstInc : 2; /**< Destination address increment unit size. */
1024 uint32_t srcAddrMode : 1; /**< Source addressing mode. */
1025 uint32_t dstAddrMode : 1; /**< Destination addressing mode. */
1026
1027 uint32_t srcAddr; /**< DMA source address. */
1028 uint32_t dstAddr; /**< DMA destination address. */
1029
1030 uint32_t linkMode : 1; /**< Select absolute or relative link address. */
1031 uint32_t link : 1; /**< Enable LINKLOAD when transfer is done. */
1032 int32_t linkAddr : 30; /**< Address of next (linked) descriptor. */
1033
1034 uint32_t reserved1 : 4; /**< Reserved */
1035 uint32_t dstIlEn : 1; /**< Destination interleave. */
1036 uint32_t IlMode : 2; /**< Interleave mode. */
1037 uint32_t bufferable : 1; /**< Allow AHB buffering. */
1038 uint32_t reserved2 : 24; /**< Reserved */
1039
1040 uint32_t reserved3; /**< Reserved */
1041 uint32_t IlSrc; /**< DMA rules table base address in memory. */
1042 } LDMA_DescriptorExtend_t;
1043 #endif
1044
1045 /** @brief LDMA initialization configuration structure. */
1046 typedef struct {
1047 uint8_t ldmaInitCtrlNumFixed; /**< Arbitration mode separator. */
1048 uint8_t ldmaInitCtrlSyncPrsClrEn; /**< PRS Synctrig clear enable. */
1049 uint8_t ldmaInitCtrlSyncPrsSetEn; /**< PRS Synctrig set enable. */
1050 uint8_t ldmaInitIrqPriority; /**< LDMA IRQ priority (0..7). */
1051 } LDMA_Init_t;
1052
1053 /**
1054 * @brief
1055 * DMA transfer configuration structure.
1056 * @details
1057 * This structure configures all aspects of a DMA transfer.
1058 */
1059 typedef struct {
1060 uint32_t ldmaReqSel; /**< Selects DMA trigger source. */
1061 uint8_t ldmaCtrlSyncPrsClrOff; /**< PRS Synctrig clear enables to clear. */
1062 uint8_t ldmaCtrlSyncPrsClrOn; /**< PRS Synctrig clear enables to set. */
1063 uint8_t ldmaCtrlSyncPrsSetOff; /**< PRS Synctrig set enables to clear. */
1064 uint8_t ldmaCtrlSyncPrsSetOn; /**< PRS Synctrig set enables to set. */
1065 bool ldmaReqDis; /**< Mask the PRS trigger input. */
1066 bool ldmaDbgHalt; /**< Dis. DMA trig when CPU is halted. */
1067 LDMA_CfgArbSlots_t ldmaCfgArbSlots; /**< Arbitration slot number. */
1068 LDMA_CfgSrcIncSign_t ldmaCfgSrcIncSign; /**< Source address increment sign. */
1069 LDMA_CfgDstIncSign_t ldmaCfgDstIncSign; /**< Destination address increment sign. */
1070 uint8_t ldmaLoopCnt; /**< Counter for looped transfers. */
1071 #if defined(_LDMA_CH_CFG_SRCBUSPORT_MASK)
1072 LDMA_CfgStructBusPort_t ldmaCfgStructBusPort; /**< Structure fetch operation bus port. */
1073 LDMA_CfgSrcBusPort_t ldmaCfgSrcBusPort; /**< Source operation bus port. */
1074 LDMA_CfgDstBusPort_t ldmaCfgDstBusPort; /**< Destination operation bus port. */
1075 #endif
1076 } LDMA_TransferCfg_t;
1077
1078 /*******************************************************************************
1079 ******************************** DEFINES **********************************
1080 ******************************************************************************/
1081
1082 /** @brief Size in words of a non-extended DMA descriptor. */
1083 #define LDMA_DESCRIPTOR_NON_EXTEND_SIZE_WORD 4
1084
1085 /** @brief Size in words of an extended DMA descriptor. */
1086 #define LDMA_DESCRIPTOR_EXTEND_SIZE_WORD 7
1087
1088 /** @brief Maximum transfer size possible per descriptor. */
1089 #define LDMA_DESCRIPTOR_MAX_XFER_SIZE (((_LDMA_CH_CTRL_XFERCNT_MASK >> _LDMA_CH_CTRL_XFERCNT_SHIFT) + 1))
1090
1091 /** @brief Converts a LDMA_Descriptor_t pointer to the value suitable to write to the linkAddr field of a LDMA_Descriptor_t. */
1092 #define LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR(addr) (int32_t) ((((uintptr_t)addr) & _LDMA_CH_LINK_LINKADDR_MASK) >> _LDMA_CH_LINK_LINKADDR_SHIFT)
1093
1094 /** @brief Converts a LDMA_Descriptor_t linkAddr field value back to a LDMA_Descriptor_t pointer. */
1095 #define LDMA_DESCRIPTOR_LINKABS_LINKADDR_TO_ADDR(linkAddr) (LDMA_Descriptor_t *) (linkAddr << _LDMA_CH_LINK_LINKADDR_SHIFT)
1096
1097 /*******************************************************************************
1098 ************************** STRUCT INITIALIZERS ****************************
1099 ******************************************************************************/
1100
1101 /** @brief Default DMA initialization structure. */
1102 #define LDMA_INIT_DEFAULT \
1103 { \
1104 .ldmaInitCtrlNumFixed = _LDMA_CTRL_NUMFIXED_DEFAULT,/* Fixed priority arbitration.*/ \
1105 .ldmaInitCtrlSyncPrsClrEn = 0, /* No PRS Synctrig clear enable*/ \
1106 .ldmaInitCtrlSyncPrsSetEn = 0, /* No PRS Synctrig set enable. */ \
1107 .ldmaInitIrqPriority = 3 /* IRQ priority level 3. */ \
1108 }
1109
1110 /**
1111 * @brief
1112 * Generic DMA transfer configuration for memory to memory transfers.
1113 */
1114 #if defined(_LDMA_CH_CFG_SRCBUSPORT_MASK)
1115 #define LDMA_TRANSFER_CFG_MEMORY() \
1116 { \
1117 0, 0, 0, 0, 0, \
1118 false, false, ldmaCfgArbSlotsAs1, \
1119 ldmaCfgSrcIncSignPos, ldmaCfgDstIncSignPos, 0, \
1120 ldmaCfgStructBusPort0, ldmaCfgSrcBusPort0, ldmaCfgDstBusPort0 \
1121 }
1122 #else
1123 #define LDMA_TRANSFER_CFG_MEMORY() \
1124 { \
1125 0, 0, 0, 0, 0, \
1126 false, false, ldmaCfgArbSlotsAs1, \
1127 ldmaCfgSrcIncSignPos, ldmaCfgDstIncSignPos, 0 \
1128 }
1129 #endif
1130
1131 /**
1132 * @brief
1133 * Generic DMA transfer configuration for looped memory to memory transfers.
1134 */
1135 #if defined(_LDMA_CH_CFG_SRCBUSPORT_MASK)
1136 #define LDMA_TRANSFER_CFG_MEMORY_LOOP(loopCnt) \
1137 { \
1138 0, 0, 0, 0, 0, \
1139 false, false, ldmaCfgArbSlotsAs1, \
1140 ldmaCfgSrcIncSignPos, ldmaCfgDstIncSignPos, \
1141 loopCnt, \
1142 ldmaCfgStructBusPort0, ldmaCfgSrcBusPort0, ldmaCfgDstBusPort0 \
1143 }
1144 #else
1145 #define LDMA_TRANSFER_CFG_MEMORY_LOOP(loopCnt) \
1146 { \
1147 0, 0, 0, 0, 0, \
1148 false, false, ldmaCfgArbSlotsAs1, \
1149 ldmaCfgSrcIncSignPos, ldmaCfgDstIncSignPos, \
1150 loopCnt \
1151 }
1152 #endif
1153
1154 /**
1155 * @brief
1156 * Generic DMA transfer configuration for memory to/from peripheral transfers.
1157 */
1158 #if defined(_LDMA_CH_CFG_SRCBUSPORT_MASK)
1159 #define LDMA_TRANSFER_CFG_PERIPHERAL(signal) \
1160 { \
1161 signal, 0, 0, 0, 0, \
1162 false, false, ldmaCfgArbSlotsAs1, \
1163 ldmaCfgSrcIncSignPos, ldmaCfgDstIncSignPos, 0, \
1164 ldmaCfgStructBusPort0, ldmaCfgSrcBusPort0, ldmaCfgDstBusPort0 \
1165 }
1166 #else
1167 #define LDMA_TRANSFER_CFG_PERIPHERAL(signal) \
1168 { \
1169 signal, 0, 0, 0, 0, \
1170 false, false, ldmaCfgArbSlotsAs1, \
1171 ldmaCfgSrcIncSignPos, ldmaCfgDstIncSignPos, 0 \
1172 }
1173 #endif
1174
1175 /**
1176 * @brief
1177 * Generic DMA transfer configuration for looped memory to/from peripheral transfers.
1178 */
1179 #if defined(_LDMA_CH_CFG_SRCBUSPORT_MASK)
1180 #define LDMA_TRANSFER_CFG_PERIPHERAL_LOOP(signal, loopCnt) \
1181 { \
1182 signal, 0, 0, 0, 0, \
1183 false, false, ldmaCfgArbSlotsAs1, \
1184 ldmaCfgSrcIncSignPos, ldmaCfgDstIncSignPos, loopCnt, \
1185 ldmaCfgStructBusPort0, ldmaCfgSrcBusPort0, ldmaCfgDstBusPort0 \
1186 }
1187 #else
1188 #define LDMA_TRANSFER_CFG_PERIPHERAL_LOOP(signal, loopCnt) \
1189 { \
1190 signal, 0, 0, 0, 0, \
1191 false, false, ldmaCfgArbSlotsAs1, \
1192 ldmaCfgSrcIncSignPos, ldmaCfgDstIncSignPos, loopCnt \
1193 }
1194 #endif
1195
1196 /**
1197 * @brief
1198 * DMA descriptor initializer for single memory to memory word transfer.
1199 * @param[in] src Source data address.
1200 * @param[in] dest Destination data address.
1201 * @param[in] count Number of words to transfer.
1202 */
1203 #define LDMA_DESCRIPTOR_SINGLE_M2M_WORD(src, dest, count) \
1204 { \
1205 .xfer = \
1206 { \
1207 .structType = ldmaCtrlStructTypeXfer, \
1208 .structReq = 1, \
1209 .xferCnt = (count) - 1, \
1210 .byteSwap = 0, \
1211 .blockSize = ldmaCtrlBlockSizeUnit1, \
1212 .doneIfs = 1, \
1213 .reqMode = ldmaCtrlReqModeAll, \
1214 .decLoopCnt = 0, \
1215 .ignoreSrec = 0, \
1216 .srcInc = ldmaCtrlSrcIncOne, \
1217 .size = ldmaCtrlSizeWord, \
1218 .dstInc = ldmaCtrlDstIncOne, \
1219 .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \
1220 .dstAddrMode = ldmaCtrlDstAddrModeAbs, \
1221 .srcAddr = (uint32_t)(src), \
1222 .dstAddr = (uint32_t)(dest), \
1223 .linkMode = 0, \
1224 .link = 0, \
1225 .linkAddr = 0 \
1226 } \
1227 }
1228
1229 #if defined(_LDMA_CH_CTRL_EXTEND_MASK)
1230 /**
1231 * @brief
1232 * DMA descriptor initializer for single memory to memory word transfer
1233 * using the extended descriptor fields.
1234 * @param[in] src Source data address.
1235 * @param[in] dest Destination data address.
1236 * @param[in] count Number of words to transfer.
1237 */
1238 #define LDMA_DESCRIPTOR_SINGLE_M2M_WORD_EXTEND(src, dest, count) \
1239 { \
1240 .structType = ldmaCtrlStructTypeXfer, \
1241 .extend = 1, \
1242 .structReq = 1, \
1243 .xferCnt = (count) - 1, \
1244 .byteSwap = 0, \
1245 .blockSize = ldmaCtrlBlockSizeUnit1, \
1246 .doneIfs = 1, \
1247 .reqMode = ldmaCtrlReqModeAll, \
1248 .decLoopCnt = 0, \
1249 .ignoreSrec = 0, \
1250 .srcInc = ldmaCtrlSrcIncOne, \
1251 .size = ldmaCtrlSizeWord, \
1252 .dstInc = ldmaCtrlDstIncNone, /* Ignored since destination addressing is non-sequential */ \
1253 .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \
1254 .dstAddrMode = ldmaCtrlDstAddrModeAbs, \
1255 .srcAddr = (uint32_t)(src), \
1256 .dstAddr = (uint32_t)(dest), \
1257 .linkMode = 0, \
1258 .link = 0, \
1259 .linkAddr = 0, \
1260 .dstIlEn = 0, \
1261 .IlMode = 0, \
1262 .bufferable = 0, \
1263 .IlSrc = 0 \
1264 }
1265 #endif
1266
1267 /**
1268 * @brief
1269 * DMA descriptor initializer for single memory to memory half-word transfer.
1270 * @param[in] src Source data address.
1271 * @param[in] dest Destination data address.
1272 * @param[in] count Number of half-words to transfer.
1273 */
1274 #define LDMA_DESCRIPTOR_SINGLE_M2M_HALF(src, dest, count) \
1275 { \
1276 .xfer = \
1277 { \
1278 .structType = ldmaCtrlStructTypeXfer, \
1279 .structReq = 1, \
1280 .xferCnt = (count) - 1, \
1281 .byteSwap = 0, \
1282 .blockSize = ldmaCtrlBlockSizeUnit1, \
1283 .doneIfs = 1, \
1284 .reqMode = ldmaCtrlReqModeAll, \
1285 .decLoopCnt = 0, \
1286 .ignoreSrec = 0, \
1287 .srcInc = ldmaCtrlSrcIncOne, \
1288 .size = ldmaCtrlSizeHalf, \
1289 .dstInc = ldmaCtrlDstIncOne, \
1290 .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \
1291 .dstAddrMode = ldmaCtrlDstAddrModeAbs, \
1292 .srcAddr = (uint32_t)(src), \
1293 .dstAddr = (uint32_t)(dest), \
1294 .linkMode = 0, \
1295 .link = 0, \
1296 .linkAddr = 0 \
1297 } \
1298 }
1299
1300 #if defined(_LDMA_CH_CTRL_EXTEND_MASK)
1301 /**
1302 * @brief
1303 * DMA descriptor initializer for single memory to memory half-word transfer
1304 * using the extended descriptor fields.
1305 * @param[in] src Source data address.
1306 * @param[in] dest Destination data address.
1307 * @param[in] count Number of half-words to transfer.
1308 */
1309 #define LDMA_DESCRIPTOR_SINGLE_M2M_HALF_EXTEND(src, dest, count) \
1310 { \
1311 .structType = ldmaCtrlStructTypeXfer, \
1312 .extend = 1, \
1313 .structReq = 1, \
1314 .xferCnt = (count) - 1, \
1315 .byteSwap = 0, \
1316 .blockSize = ldmaCtrlBlockSizeUnit1, \
1317 .doneIfs = 1, \
1318 .reqMode = ldmaCtrlReqModeAll, \
1319 .decLoopCnt = 0, \
1320 .ignoreSrec = 0, \
1321 .srcInc = ldmaCtrlSrcIncOne, \
1322 .size = ldmaCtrlSizeHalf, \
1323 .dstInc = ldmaCtrlDstIncNone, \
1324 .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \
1325 .dstAddrMode = ldmaCtrlDstAddrModeAbs, \
1326 .srcAddr = (uint32_t)(src), \
1327 .dstAddr = (uint32_t)(dest), \
1328 .linkMode = 0, \
1329 .link = 0, \
1330 .linkAddr = 0, \
1331 .dstIlEn = 0, \
1332 .IlMode = 0, \
1333 .bufferable = 0, \
1334 .IlSrc = 0 \
1335 }
1336 #endif
1337
1338 /**
1339 * @brief
1340 * DMA descriptor initializer for single memory to memory byte transfer.
1341 * @param[in] src Source data address.
1342 * @param[in] dest Destination data address.
1343 * @param[in] count Number of bytes to transfer.
1344 */
1345 #define LDMA_DESCRIPTOR_SINGLE_M2M_BYTE(src, dest, count) \
1346 { \
1347 .xfer = \
1348 { \
1349 .structType = ldmaCtrlStructTypeXfer, \
1350 .structReq = 1, \
1351 .xferCnt = (count) - 1, \
1352 .byteSwap = 0, \
1353 .blockSize = ldmaCtrlBlockSizeUnit1, \
1354 .doneIfs = 1, \
1355 .reqMode = ldmaCtrlReqModeAll, \
1356 .decLoopCnt = 0, \
1357 .ignoreSrec = 0, \
1358 .srcInc = ldmaCtrlSrcIncOne, \
1359 .size = ldmaCtrlSizeByte, \
1360 .dstInc = ldmaCtrlDstIncOne, \
1361 .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \
1362 .dstAddrMode = ldmaCtrlDstAddrModeAbs, \
1363 .srcAddr = (uint32_t)(src), \
1364 .dstAddr = (uint32_t)(dest), \
1365 .linkMode = 0, \
1366 .link = 0, \
1367 .linkAddr = 0 \
1368 } \
1369 }
1370
1371 #if defined(_LDMA_CH_CTRL_EXTEND_MASK)
1372 /**
1373 * @brief
1374 * DMA descriptor initializer for single memory to memory byte transfer
1375 * using the extended descriptor fields.
1376 * @param[in] src Source data address.
1377 * @param[in] dest Destination data address.
1378 * @param[in] count Number of bytes to transfer.
1379 */
1380 #define LDMA_DESCRIPTOR_SINGLE_M2M_BYTE_EXTEND(src, dest, count) \
1381 { \
1382 .structType = ldmaCtrlStructTypeXfer, \
1383 .extend = 1, \
1384 .structReq = 1, \
1385 .xferCnt = (count) - 1, \
1386 .byteSwap = 0, \
1387 .blockSize = ldmaCtrlBlockSizeUnit1, \
1388 .doneIfs = 1, \
1389 .reqMode = ldmaCtrlReqModeAll, \
1390 .decLoopCnt = 0, \
1391 .ignoreSrec = 0, \
1392 .srcInc = ldmaCtrlSrcIncOne, \
1393 .size = ldmaCtrlSizeByte, \
1394 .dstInc = ldmaCtrlDstIncNone, \
1395 .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \
1396 .dstAddrMode = ldmaCtrlDstAddrModeAbs, \
1397 .srcAddr = (uint32_t)(src), \
1398 .dstAddr = (uint32_t)(dest), \
1399 .linkMode = 0, \
1400 .link = 0, \
1401 .linkAddr = 0, \
1402 .dstIlEn = 0, \
1403 .IlMode = 0, \
1404 .bufferable = 0, \
1405 .IlSrc = 0 \
1406 }
1407 #endif
1408
1409 /**
1410 * @brief
1411 * DMA descriptor initializer for linked memory to memory word transfer.
1412 *
1413 * Link address must be an absolute address.
1414 * @note
1415 * The linkAddr member of the transfer descriptor is not initialized.
1416 * linkAddr must be initialized by using the proper bits right-shift
1417 * to get the correct bits from the absolute address.
1418 * LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR macro should be used for that operation:
1419 * @code
1420 desc.linkAddr = LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR(&next_desc);@endcode
1421 * The opposite bit shift (left) must be done with LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR
1422 * if linkAddr is read.
1423 * @param[in] src Source data address.
1424 * @param[in] dest Destination data address.
1425 * @param[in] count Number of words to transfer.
1426 */
1427 #define LDMA_DESCRIPTOR_LINKABS_M2M_WORD(src, dest, count) \
1428 { \
1429 .xfer = \
1430 { \
1431 .structType = ldmaCtrlStructTypeXfer, \
1432 .structReq = 1, \
1433 .xferCnt = (count) - 1, \
1434 .byteSwap = 0, \
1435 .blockSize = ldmaCtrlBlockSizeUnit1, \
1436 .doneIfs = 0, \
1437 .reqMode = ldmaCtrlReqModeAll, \
1438 .decLoopCnt = 0, \
1439 .ignoreSrec = 0, \
1440 .srcInc = ldmaCtrlSrcIncOne, \
1441 .size = ldmaCtrlSizeWord, \
1442 .dstInc = ldmaCtrlDstIncOne, \
1443 .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \
1444 .dstAddrMode = ldmaCtrlDstAddrModeAbs, \
1445 .srcAddr = (uint32_t)(src), \
1446 .dstAddr = (uint32_t)(dest), \
1447 .linkMode = ldmaLinkModeAbs, \
1448 .link = 1, \
1449 .linkAddr = 0 /* Must be set runtime ! */ \
1450 } \
1451 }
1452
1453 #if defined(_LDMA_CH_CTRL_EXTEND_MASK)
1454 /**
1455 * @brief
1456 * DMA descriptor initializer for linked memory to memory word transfer
1457 * using the extended descriptor fields.
1458 *
1459 * Link address must be an absolute address.
1460 * @note
1461 * The linkAddr member of the transfer descriptor is not initialized.
1462 * linkAddr must be initialized by using the proper bits right-shift
1463 * to get the correct bits from the absolute address.
1464 * LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR macro should be used for that operation:
1465 * @code
1466 desc.linkAddr = LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR(&next_desc);@endcode
1467 * The opposite bit shift (left) must be done with LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR
1468 * if linkAddr is read.
1469 * @param[in] src Source data address.
1470 * @param[in] dest Destination data address.
1471 * @param[in] count Number of words to transfer.
1472 */
1473 #define LDMA_DESCRIPTOR_LINKABS_M2M_WORD_EXTEND(src, dest, count) \
1474 { \
1475 .structType = ldmaCtrlStructTypeXfer, \
1476 .extend = 1, \
1477 .structReq = 1, \
1478 .xferCnt = (count) - 1, \
1479 .byteSwap = 0, \
1480 .blockSize = ldmaCtrlBlockSizeUnit1, \
1481 .doneIfs = 0, \
1482 .reqMode = ldmaCtrlReqModeAll, \
1483 .decLoopCnt = 0, \
1484 .ignoreSrec = 0, \
1485 .srcInc = ldmaCtrlSrcIncOne, \
1486 .size = ldmaCtrlSizeWord, \
1487 .dstInc = ldmaCtrlDstIncNone, \
1488 .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \
1489 .dstAddrMode = ldmaCtrlDstAddrModeAbs, \
1490 .srcAddr = (uint32_t)(src), \
1491 .dstAddr = (uint32_t)(dest), \
1492 .linkMode = ldmaLinkModeAbs, \
1493 .link = 1, \
1494 .linkAddr = 0, /* Must be set runtime ! */ \
1495 .dstIlEn = 0, \
1496 .IlMode = 0, \
1497 .bufferable = 0, \
1498 .IlSrc = 0 \
1499 }
1500 #endif
1501
1502 /**
1503 * @brief
1504 * DMA descriptor initializer for linked memory to memory half-word transfer.
1505 *
1506 * Link address must be an absolute address.
1507 * @note
1508 * The linkAddr member of the transfer descriptor is not initialized.
1509 * linkAddr must be initialized by using the proper bits right-shift
1510 * to get the correct bits from the absolute address.
1511 * LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR macro should be used for that operation:
1512 * @code
1513 desc.linkAddr = LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR(&next_desc);@endcode
1514 * The opposite bit shift (left) must be done with LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR
1515 * if linkAddr is read.
1516 * @param[in] src Source data address.
1517 * @param[in] dest Destination data address.
1518 * @param[in] count Number of half-words to transfer.
1519 */
1520 #define LDMA_DESCRIPTOR_LINKABS_M2M_HALF(src, dest, count) \
1521 { \
1522 .xfer = \
1523 { \
1524 .structType = ldmaCtrlStructTypeXfer, \
1525 .structReq = 1, \
1526 .xferCnt = (count) - 1, \
1527 .byteSwap = 0, \
1528 .blockSize = ldmaCtrlBlockSizeUnit1, \
1529 .doneIfs = 0, \
1530 .reqMode = ldmaCtrlReqModeAll, \
1531 .decLoopCnt = 0, \
1532 .ignoreSrec = 0, \
1533 .srcInc = ldmaCtrlSrcIncOne, \
1534 .size = ldmaCtrlSizeHalf, \
1535 .dstInc = ldmaCtrlDstIncOne, \
1536 .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \
1537 .dstAddrMode = ldmaCtrlDstAddrModeAbs, \
1538 .srcAddr = (uint32_t)(src), \
1539 .dstAddr = (uint32_t)(dest), \
1540 .linkMode = ldmaLinkModeAbs, \
1541 .link = 1, \
1542 .linkAddr = 0 /* Must be set runtime ! */ \
1543 } \
1544 }
1545
1546 #if defined(_LDMA_CH_CTRL_EXTEND_MASK)
1547 /**
1548 * @brief
1549 * DMA descriptor initializer for linked memory to memory half-word transfer
1550 * using the extended descriptor fields.
1551 *
1552 * Link address must be an absolute address.
1553 * @note
1554 * The linkAddr member of the transfer descriptor is not initialized.
1555 * linkAddr must be initialized by using the proper bits right-shift
1556 * to get the correct bits from the absolute address.
1557 * LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR macro should be used for that operation:
1558 * @code
1559 desc.linkAddr = LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR(&next_desc);@endcode
1560 * The opposite bit shift (left) must be done with LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR
1561 * if linkAddr is read.
1562 * @param[in] src Source data address.
1563 * @param[in] dest Destination data address.
1564 * @param[in] count Number of half-words to transfer.
1565 */
1566 #define LDMA_DESCRIPTOR_LINKABS_M2M_HALF_EXTEND(src, dest, count) \
1567 { \
1568 .structType = ldmaCtrlStructTypeXfer, \
1569 .extend = 1, \
1570 .structReq = 1, \
1571 .xferCnt = (count) - 1, \
1572 .byteSwap = 0, \
1573 .blockSize = ldmaCtrlBlockSizeUnit1, \
1574 .doneIfs = 0, \
1575 .reqMode = ldmaCtrlReqModeAll, \
1576 .decLoopCnt = 0, \
1577 .ignoreSrec = 0, \
1578 .srcInc = ldmaCtrlSrcIncOne, \
1579 .size = ldmaCtrlSizeHalf, \
1580 .dstInc = ldmaCtrlDstIncNone, \
1581 .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \
1582 .dstAddrMode = ldmaCtrlDstAddrModeAbs, \
1583 .srcAddr = (uint32_t)(src), \
1584 .dstAddr = (uint32_t)(dest), \
1585 .linkMode = ldmaLinkModeAbs, \
1586 .link = 1, \
1587 .linkAddr = 0, /* Must be set runtime ! */ \
1588 .dstIlEn = 0, \
1589 .IlMode = 0, \
1590 .bufferable = 0, \
1591 .IlSrc = 0 \
1592 }
1593 #endif
1594
1595 /**
1596 * @brief
1597 * DMA descriptor initializer for linked memory to memory byte transfer.
1598 *
1599 * Link address must be an absolute address.
1600 * @note
1601 * The linkAddr member of the transfer descriptor is not initialized.
1602 * linkAddr must be initialized by using the proper bits right-shift
1603 * to get the correct bits from the absolute address.
1604 * LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR macro should be used for that operation:
1605 * @code
1606 desc.linkAddr = LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR(&next_desc);@endcode
1607 * The opposite bit shift (left) must be done with LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR
1608 * if linkAddr is read.
1609 * @param[in] src Source data address.
1610 * @param[in] dest Destination data address.
1611 * @param[in] count Number of bytes to transfer.
1612 */
1613 #define LDMA_DESCRIPTOR_LINKABS_M2M_BYTE(src, dest, count) \
1614 { \
1615 .xfer = \
1616 { \
1617 .structType = ldmaCtrlStructTypeXfer, \
1618 .structReq = 1, \
1619 .xferCnt = (count) - 1, \
1620 .byteSwap = 0, \
1621 .blockSize = ldmaCtrlBlockSizeUnit1, \
1622 .doneIfs = 0, \
1623 .reqMode = ldmaCtrlReqModeAll, \
1624 .decLoopCnt = 0, \
1625 .ignoreSrec = 0, \
1626 .srcInc = ldmaCtrlSrcIncOne, \
1627 .size = ldmaCtrlSizeByte, \
1628 .dstInc = ldmaCtrlDstIncOne, \
1629 .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \
1630 .dstAddrMode = ldmaCtrlDstAddrModeAbs, \
1631 .srcAddr = (uint32_t)(src), \
1632 .dstAddr = (uint32_t)(dest), \
1633 .linkMode = ldmaLinkModeAbs, \
1634 .link = 1, \
1635 .linkAddr = 0 /* Must be set runtime ! */ \
1636 } \
1637 }
1638
1639 #if defined(_LDMA_CH_CTRL_EXTEND_MASK)
1640 /**
1641 * @brief
1642 * DMA descriptor initializer for linked memory to memory byte transfer
1643 * using the extended descriptor fields.
1644 *
1645 * Link address must be an absolute address.
1646 * @note
1647 * The linkAddr member of the transfer descriptor is not initialized.
1648 * linkAddr must be initialized by using the proper bits right-shift
1649 * to get the correct bits from the absolute address.
1650 * LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR macro should be used for that operation:
1651 * @code
1652 desc.linkAddr = LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR(&next_desc);@endcode
1653 * The opposite bit shift (left) must be done with LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR
1654 * if linkAddr is read.
1655 * @param[in] src Source data address.
1656 * @param[in] dest Destination data address.
1657 * @param[in] count Number of bytes to transfer.
1658 */
1659 #define LDMA_DESCRIPTOR_LINKABS_M2M_BYTE_EXTEND(src, dest, count) \
1660 { \
1661 .structType = ldmaCtrlStructTypeXfer, \
1662 .extend = 1, \
1663 .structReq = 1, \
1664 .xferCnt = (count) - 1, \
1665 .byteSwap = 0, \
1666 .blockSize = ldmaCtrlBlockSizeUnit1, \
1667 .doneIfs = 0, \
1668 .reqMode = ldmaCtrlReqModeAll, \
1669 .decLoopCnt = 0, \
1670 .ignoreSrec = 0, \
1671 .srcInc = ldmaCtrlSrcIncOne, \
1672 .size = ldmaCtrlSizeByte, \
1673 .dstInc = ldmaCtrlDstIncNone, \
1674 .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \
1675 .dstAddrMode = ldmaCtrlDstAddrModeAbs, \
1676 .srcAddr = (uint32_t)(src), \
1677 .dstAddr = (uint32_t)(dest), \
1678 .linkMode = ldmaLinkModeAbs, \
1679 .link = 1, \
1680 .linkAddr = 0, /* Must be set runtime ! */ \
1681 .dstIlEn = 0, \
1682 .IlMode = 0, \
1683 .bufferable = 0, \
1684 .IlSrc = 0 \
1685 }
1686 #endif
1687
1688 /**
1689 * @brief
1690 * DMA descriptor initializer for linked memory to memory word transfer.
1691 *
1692 * Link address is a relative address.
1693 * @note
1694 * The linkAddr member of the transfer descriptor is initialized to 4
1695 * (regular descriptor) or 7 (extended descriptor), assuming that
1696 * the next descriptor immediately follows this descriptor (in memory).
1697 * @param[in] src Source data address.
1698 * @param[in] dest Destination data address.
1699 * @param[in] count Number of words to transfer.
1700 * @param[in] linkjmp Address of descriptor to link to, expressed as a
1701 * signed number of descriptors from "here".
1702 * 1=one descriptor forward in memory,
1703 * 0=this descriptor,
1704 * -1=one descriptor back in memory.
1705 */
1706 #define LDMA_DESCRIPTOR_LINKREL_M2M_WORD(src, dest, count, linkjmp) \
1707 { \
1708 .xfer = \
1709 { \
1710 .structType = ldmaCtrlStructTypeXfer, \
1711 .structReq = 1, \
1712 .xferCnt = (count) - 1, \
1713 .byteSwap = 0, \
1714 .blockSize = ldmaCtrlBlockSizeUnit1, \
1715 .doneIfs = 0, \
1716 .reqMode = ldmaCtrlReqModeAll, \
1717 .decLoopCnt = 0, \
1718 .ignoreSrec = 0, \
1719 .srcInc = ldmaCtrlSrcIncOne, \
1720 .size = ldmaCtrlSizeWord, \
1721 .dstInc = ldmaCtrlDstIncOne, \
1722 .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \
1723 .dstAddrMode = ldmaCtrlDstAddrModeAbs, \
1724 .srcAddr = (uint32_t)(src), \
1725 .dstAddr = (uint32_t)(dest), \
1726 .linkMode = ldmaLinkModeRel, \
1727 .link = 1, \
1728 .linkAddr = (linkjmp) * LDMA_DESCRIPTOR_NON_EXTEND_SIZE_WORD \
1729 } \
1730 }
1731
1732 #if defined(_LDMA_CH_CTRL_EXTEND_MASK)
1733 /**
1734 * @brief
1735 * DMA descriptor initializer for linked memory to memory word transfer
1736 * using the extended descriptor fields.
1737 *
1738 * Link address is a relative address.
1739 * @note
1740 * The linkAddr member of the transfer descriptor is initialized to 4
1741 * (regular descriptor) or 7 (extended descriptor), assuming that
1742 * the next descriptor immediately follows this descriptor (in memory).
1743 * @param[in] src Source data address.
1744 * @param[in] dest Destination data address.
1745 * @param[in] count Number of words to transfer.
1746 * @param[in] linkjmp Address of descriptor to link to, expressed as a
1747 * signed number of descriptors from "here".
1748 * 1=one descriptor forward in memory,
1749 * 0=this descriptor,
1750 * -1=one descriptor back in memory.
1751 */
1752 #define LDMA_DESCRIPTOR_LINKREL_M2M_WORD_EXTEND(src, dest, count, linkjmp) \
1753 { \
1754 .structType = ldmaCtrlStructTypeXfer, \
1755 .extend = 1, \
1756 .structReq = 1, \
1757 .xferCnt = (count) - 1, \
1758 .byteSwap = 0, \
1759 .blockSize = ldmaCtrlBlockSizeUnit1, \
1760 .doneIfs = 0, \
1761 .reqMode = ldmaCtrlReqModeAll, \
1762 .decLoopCnt = 0, \
1763 .ignoreSrec = 0, \
1764 .srcInc = ldmaCtrlSrcIncOne, \
1765 .size = ldmaCtrlSizeWord, \
1766 .dstInc = ldmaCtrlDstIncNone, \
1767 .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \
1768 .dstAddrMode = ldmaCtrlDstAddrModeAbs, \
1769 .srcAddr = (uint32_t)(src), \
1770 .dstAddr = (uint32_t)(dest), \
1771 .linkMode = ldmaLinkModeRel, \
1772 .link = 1, \
1773 .linkAddr = (linkjmp) * LDMA_DESCRIPTOR_EXTEND_SIZE_WORD, \
1774 .dstIlEn = 0, \
1775 .IlMode = 0, \
1776 .bufferable = 0, \
1777 .IlSrc = 0 \
1778 }
1779 #endif
1780
1781 /**
1782 * @brief
1783 * DMA descriptor initializer for linked memory to memory half-word transfer.
1784 *
1785 * Link address is a relative address.
1786 * @note
1787 * The linkAddr member of the transfer descriptor is initialized to 4
1788 * (regular descriptor) or 7 (extended descriptor), assuming that
1789 * the next descriptor immediately follows this descriptor (in memory).
1790 * @param[in] src Source data address.
1791 * @param[in] dest Destination data address.
1792 * @param[in] count Number of half-words to transfer.
1793 * @param[in] linkjmp Address of descriptor to link to, expressed as a
1794 * signed number of descriptors from "here".
1795 * 1=one descriptor forward in memory,
1796 * 0=this descriptor,
1797 * -1=one descriptor back in memory.
1798 */
1799 #define LDMA_DESCRIPTOR_LINKREL_M2M_HALF(src, dest, count, linkjmp) \
1800 { \
1801 .xfer = \
1802 { \
1803 .structType = ldmaCtrlStructTypeXfer, \
1804 .structReq = 1, \
1805 .xferCnt = (count) - 1, \
1806 .byteSwap = 0, \
1807 .blockSize = ldmaCtrlBlockSizeUnit1, \
1808 .doneIfs = 0, \
1809 .reqMode = ldmaCtrlReqModeAll, \
1810 .decLoopCnt = 0, \
1811 .ignoreSrec = 0, \
1812 .srcInc = ldmaCtrlSrcIncOne, \
1813 .size = ldmaCtrlSizeHalf, \
1814 .dstInc = ldmaCtrlDstIncOne, \
1815 .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \
1816 .dstAddrMode = ldmaCtrlDstAddrModeAbs, \
1817 .srcAddr = (uint32_t)(src), \
1818 .dstAddr = (uint32_t)(dest), \
1819 .linkMode = ldmaLinkModeRel, \
1820 .link = 1, \
1821 .linkAddr = (linkjmp) * LDMA_DESCRIPTOR_NON_EXTEND_SIZE_WORD \
1822 } \
1823 }
1824
1825 #if defined(_LDMA_CH_CTRL_EXTEND_MASK)
1826 /**
1827 * @brief
1828 * DMA descriptor initializer for linked memory to memory half-word transfer
1829 * using the extended descriptor fields.
1830 *
1831 * Link address is a relative address.
1832 * @note
1833 * The linkAddr member of the transfer descriptor is initialized to 4
1834 * (regular descriptor) or 7 (extended descriptor), assuming that
1835 * the next descriptor immediately follows this descriptor (in memory).
1836 * @param[in] src Source data address.
1837 * @param[in] dest Destination data address.
1838 * @param[in] count Number of half-words to transfer.
1839 * @param[in] linkjmp Address of descriptor to link to, expressed as a
1840 * signed number of descriptors from "here".
1841 * 1=one descriptor forward in memory,
1842 * 0=this descriptor,
1843 * -1=one descriptor back in memory.
1844 */
1845 #define LDMA_DESCRIPTOR_LINKREL_M2M_HALF_EXTEND(src, dest, count, linkjmp) \
1846 { \
1847 .structType = ldmaCtrlStructTypeXfer, \
1848 .extend = 1, \
1849 .structReq = 1, \
1850 .xferCnt = (count) - 1, \
1851 .byteSwap = 0, \
1852 .blockSize = ldmaCtrlBlockSizeUnit1, \
1853 .doneIfs = 0, \
1854 .reqMode = ldmaCtrlReqModeAll, \
1855 .decLoopCnt = 0, \
1856 .ignoreSrec = 0, \
1857 .srcInc = ldmaCtrlSrcIncOne, \
1858 .size = ldmaCtrlSizeHalf, \
1859 .dstInc = ldmaCtrlDstIncNone, \
1860 .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \
1861 .dstAddrMode = ldmaCtrlDstAddrModeAbs, \
1862 .srcAddr = (uint32_t)(src), \
1863 .dstAddr = (uint32_t)(dest), \
1864 .linkMode = ldmaLinkModeRel, \
1865 .link = 1, \
1866 .linkAddr = (linkjmp) * LDMA_DESCRIPTOR_EXTEND_SIZE_WORD, \
1867 .dstIlEn = 0, \
1868 .IlMode = 0, \
1869 .bufferable = 0, \
1870 .IlSrc = 0 \
1871 }
1872 #endif
1873
1874 /**
1875 * @brief
1876 * DMA descriptor initializer for linked memory to memory byte transfer.
1877 *
1878 * Link address is a relative address.
1879 * @note
1880 * The linkAddr member of the transfer descriptor is initialized to 4
1881 * (regular descriptor) or 7 (extended descriptor), assuming that
1882 * the next descriptor immediately follows this descriptor (in memory).
1883 * @param[in] src Source data address.
1884 * @param[in] dest Destination data address.
1885 * @param[in] count Number of bytes to transfer.
1886 * @param[in] linkjmp Address of descriptor to link to, expressed as a
1887 * signed number of descriptors from "here".
1888 * 1=one descriptor forward in memory,
1889 * 0=this descriptor,
1890 * -1=one descriptor back in memory.
1891 */
1892 #define LDMA_DESCRIPTOR_LINKREL_M2M_BYTE(src, dest, count, linkjmp) \
1893 { \
1894 .xfer = \
1895 { \
1896 .structType = ldmaCtrlStructTypeXfer, \
1897 .structReq = 1, \
1898 .xferCnt = (count) - 1, \
1899 .byteSwap = 0, \
1900 .blockSize = ldmaCtrlBlockSizeUnit1, \
1901 .doneIfs = 0, \
1902 .reqMode = ldmaCtrlReqModeAll, \
1903 .decLoopCnt = 0, \
1904 .ignoreSrec = 0, \
1905 .srcInc = ldmaCtrlSrcIncOne, \
1906 .size = ldmaCtrlSizeByte, \
1907 .dstInc = ldmaCtrlDstIncOne, \
1908 .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \
1909 .dstAddrMode = ldmaCtrlDstAddrModeAbs, \
1910 .srcAddr = (uint32_t)(src), \
1911 .dstAddr = (uint32_t)(dest), \
1912 .linkMode = ldmaLinkModeRel, \
1913 .link = 1, \
1914 .linkAddr = (linkjmp) * LDMA_DESCRIPTOR_NON_EXTEND_SIZE_WORD \
1915 } \
1916 }
1917
1918 #if defined(_LDMA_CH_CTRL_EXTEND_MASK)
1919 /**
1920 * @brief
1921 * DMA descriptor initializer for linked memory to memory byte transfer
1922 * using the extended descriptor fields.
1923 *
1924 * Link address is a relative address.
1925 * @note
1926 * The linkAddr member of the transfer descriptor is initialized to 4
1927 * (regular descriptor) or 7 (extended descriptor), assuming that
1928 * the next descriptor immediately follows this descriptor (in memory).
1929 * @param[in] src Source data address.
1930 * @param[in] dest Destination data address.
1931 * @param[in] count Number of bytes to transfer.
1932 * @param[in] linkjmp Address of descriptor to link to, expressed as a
1933 * signed number of descriptors from "here".
1934 * 1=one descriptor forward in memory,
1935 * 0=this descriptor,
1936 * -1=one descriptor back in memory.
1937 */
1938 #define LDMA_DESCRIPTOR_LINKREL_M2M_BYTE_EXTEND(src, dest, count, linkjmp) \
1939 { \
1940 .structType = ldmaCtrlStructTypeXfer, \
1941 .extend = 1, \
1942 .structReq = 1, \
1943 .xferCnt = (count) - 1, \
1944 .byteSwap = 0, \
1945 .blockSize = ldmaCtrlBlockSizeUnit1, \
1946 .doneIfs = 0, \
1947 .reqMode = ldmaCtrlReqModeAll, \
1948 .decLoopCnt = 0, \
1949 .ignoreSrec = 0, \
1950 .srcInc = ldmaCtrlSrcIncOne, \
1951 .size = ldmaCtrlSizeByte, \
1952 .dstInc = ldmaCtrlDstIncNone, \
1953 .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \
1954 .dstAddrMode = ldmaCtrlDstAddrModeAbs, \
1955 .srcAddr = (uint32_t)(src), \
1956 .dstAddr = (uint32_t)(dest), \
1957 .linkMode = ldmaLinkModeRel, \
1958 .link = 1, \
1959 .linkAddr = (linkjmp) * LDMA_DESCRIPTOR_EXTEND_SIZE_WORD, \
1960 .dstIlEn = 0, \
1961 .IlMode = 0, \
1962 .bufferable = 0, \
1963 .IlSrc = 0 \
1964 }
1965 #endif
1966
1967 /**
1968 * @brief
1969 * DMA descriptor initializer for byte transfers from a peripheral to memory.
1970 * @param[in] src Peripheral data source register address.
1971 * @param[in] dest Destination data address.
1972 * @param[in] count Number of bytes to transfer.
1973 */
1974 #define LDMA_DESCRIPTOR_SINGLE_P2M_BYTE(src, dest, count) \
1975 { \
1976 .xfer = \
1977 { \
1978 .structType = ldmaCtrlStructTypeXfer, \
1979 .structReq = 0, \
1980 .xferCnt = (count) - 1, \
1981 .byteSwap = 0, \
1982 .blockSize = ldmaCtrlBlockSizeUnit1, \
1983 .doneIfs = 1, \
1984 .reqMode = ldmaCtrlReqModeBlock, \
1985 .decLoopCnt = 0, \
1986 .ignoreSrec = 0, \
1987 .srcInc = ldmaCtrlSrcIncNone, \
1988 .size = ldmaCtrlSizeByte, \
1989 .dstInc = ldmaCtrlDstIncOne, \
1990 .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \
1991 .dstAddrMode = ldmaCtrlDstAddrModeAbs, \
1992 .srcAddr = (uint32_t)(src), \
1993 .dstAddr = (uint32_t)(dest), \
1994 .linkMode = 0, \
1995 .link = 0, \
1996 .linkAddr = 0 \
1997 } \
1998 }
1999
2000 #if defined(_LDMA_CH_CTRL_EXTEND_MASK)
2001 /**
2002 * @brief
2003 * DMA descriptor initializer for byte transfers from a peripheral to memory
2004 * using the extended descriptor fields.
2005 * @param[in] src Peripheral data source register address.
2006 * @param[in] dest Destination data address.
2007 * @param[in] count Number of bytes to transfer.
2008 */
2009 #define LDMA_DESCRIPTOR_SINGLE_P2M_BYTE_EXTEND(src, dest, count) \
2010 { \
2011 .structType = ldmaCtrlStructTypeXfer, \
2012 .extend = 1, \
2013 .structReq = 0, \
2014 .xferCnt = (count) - 1, \
2015 .byteSwap = 0, \
2016 .blockSize = ldmaCtrlBlockSizeUnit1, \
2017 .doneIfs = 1, \
2018 .reqMode = ldmaCtrlReqModeBlock, \
2019 .decLoopCnt = 0, \
2020 .ignoreSrec = 0, \
2021 .srcInc = ldmaCtrlSrcIncNone, \
2022 .size = ldmaCtrlSizeByte, \
2023 .dstInc = ldmaCtrlDstIncNone, \
2024 .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \
2025 .dstAddrMode = ldmaCtrlDstAddrModeAbs, \
2026 .srcAddr = (uint32_t)(src), \
2027 .dstAddr = (uint32_t)(dest), \
2028 .linkMode = 0, \
2029 .link = 0, \
2030 .linkAddr = 0, \
2031 .dstIlEn = 0, \
2032 .IlMode = 0, \
2033 .bufferable = 0, \
2034 .IlSrc = 0 \
2035 }
2036 #endif
2037
2038 /**
2039 * @brief
2040 * DMA descriptor initializer for byte transfers from a peripheral to a peripheral.
2041 * @param[in] src Peripheral data source register address.
2042 * @param[in] dest Peripheral data destination register address.
2043 * @param[in] count Number of bytes to transfer.
2044 */
2045 #define LDMA_DESCRIPTOR_SINGLE_P2P_BYTE(src, dest, count) \
2046 { \
2047 .xfer = \
2048 { \
2049 .structType = ldmaCtrlStructTypeXfer, \
2050 .structReq = 0, \
2051 .xferCnt = (count) - 1, \
2052 .byteSwap = 0, \
2053 .blockSize = ldmaCtrlBlockSizeUnit1, \
2054 .doneIfs = 1, \
2055 .reqMode = ldmaCtrlReqModeBlock, \
2056 .decLoopCnt = 0, \
2057 .ignoreSrec = 0, \
2058 .srcInc = ldmaCtrlSrcIncNone, \
2059 .size = ldmaCtrlSizeByte, \
2060 .dstInc = ldmaCtrlDstIncNone, \
2061 .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \
2062 .dstAddrMode = ldmaCtrlDstAddrModeAbs, \
2063 .srcAddr = (uint32_t)(src), \
2064 .dstAddr = (uint32_t)(dest), \
2065 .linkMode = 0, \
2066 .link = 0, \
2067 .linkAddr = 0 \
2068 } \
2069 }
2070
2071 /**
2072 * @brief
2073 * DMA descriptor initializer for byte transfers from memory to a peripheral.
2074 * @param[in] src Source data address.
2075 * @param[in] dest Peripheral data register destination address.
2076 * @param[in] count Number of bytes to transfer.
2077 */
2078 #define LDMA_DESCRIPTOR_SINGLE_M2P_BYTE(src, dest, count) \
2079 { \
2080 .xfer = \
2081 { \
2082 .structType = ldmaCtrlStructTypeXfer, \
2083 .structReq = 0, \
2084 .xferCnt = (count) - 1, \
2085 .byteSwap = 0, \
2086 .blockSize = ldmaCtrlBlockSizeUnit1, \
2087 .doneIfs = 1, \
2088 .reqMode = ldmaCtrlReqModeBlock, \
2089 .decLoopCnt = 0, \
2090 .ignoreSrec = 0, \
2091 .srcInc = ldmaCtrlSrcIncOne, \
2092 .size = ldmaCtrlSizeByte, \
2093 .dstInc = ldmaCtrlDstIncNone, \
2094 .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \
2095 .dstAddrMode = ldmaCtrlDstAddrModeAbs, \
2096 .srcAddr = (uint32_t)(src), \
2097 .dstAddr = (uint32_t)(dest), \
2098 .linkMode = 0, \
2099 .link = 0, \
2100 .linkAddr = 0 \
2101 } \
2102 }
2103
2104 #if defined(_LDMA_CH_CTRL_EXTEND_MASK)
2105 /**
2106 * @brief
2107 * DMA descriptor initializer for byte transfers from memory to a peripheral
2108 * using the extended descriptor fields.
2109 * @note
2110 * For the extended descriptor, if IlMode uses the absolute addressing, the
2111 * rules are used directly as the destination addresses of the corresponding
2112 * data. Thus the argument 'dest' will be ignored by the DMA engine.
2113 * @param[in] src Source data address.
2114 * @param[in] dest Peripheral data register destination address.
2115 * @param[in] count Number of bytes to transfer.
2116 */
2117 #define LDMA_DESCRIPTOR_SINGLE_M2P_BYTE_EXTEND(src, dest, count) \
2118 { \
2119 .structType = ldmaCtrlStructTypeXfer, \
2120 .extend = 1, \
2121 .structReq = 0, \
2122 .xferCnt = (count) - 1, \
2123 .byteSwap = 0, \
2124 .blockSize = ldmaCtrlBlockSizeUnit1, \
2125 .doneIfs = 1, \
2126 .reqMode = ldmaCtrlReqModeBlock, \
2127 .decLoopCnt = 0, \
2128 .ignoreSrec = 0, \
2129 .srcInc = ldmaCtrlSrcIncOne, \
2130 .size = ldmaCtrlSizeByte, \
2131 .dstInc = ldmaCtrlDstIncNone, \
2132 .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \
2133 .dstAddrMode = ldmaCtrlDstAddrModeAbs, \
2134 .srcAddr = (uint32_t)(src), \
2135 .dstAddr = (uint32_t)(dest), \
2136 .linkMode = 0, \
2137 .link = 0, \
2138 .linkAddr = 0, \
2139 .dstIlEn = 0, \
2140 .IlMode = 0, \
2141 .bufferable = 0, \
2142 .IlSrc = 0 \
2143 }
2144 #endif
2145
2146 /**
2147 * @brief
2148 * DMA descriptor initializer for byte transfers from a peripheral to memory.
2149 * @param[in] src Peripheral data source register address.
2150 * @param[in] dest Destination data address.
2151 * @param[in] count Number of bytes to transfer.
2152 * @param[in] linkjmp Address of descriptor to link to, expressed as a
2153 * signed number of descriptors from "here".
2154 * 1=one descriptor forward in memory,
2155 * 0=this descriptor,
2156 * -1=one descriptor back in memory.
2157 */
2158 #define LDMA_DESCRIPTOR_LINKREL_P2M_BYTE(src, dest, count, linkjmp) \
2159 { \
2160 .xfer = \
2161 { \
2162 .structType = ldmaCtrlStructTypeXfer, \
2163 .structReq = 0, \
2164 .xferCnt = (count) - 1, \
2165 .byteSwap = 0, \
2166 .blockSize = ldmaCtrlBlockSizeUnit1, \
2167 .doneIfs = 1, \
2168 .reqMode = ldmaCtrlReqModeBlock, \
2169 .decLoopCnt = 0, \
2170 .ignoreSrec = 0, \
2171 .srcInc = ldmaCtrlSrcIncNone, \
2172 .size = ldmaCtrlSizeByte, \
2173 .dstInc = ldmaCtrlDstIncOne, \
2174 .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \
2175 .dstAddrMode = ldmaCtrlDstAddrModeAbs, \
2176 .srcAddr = (uint32_t)(src), \
2177 .dstAddr = (uint32_t)(dest), \
2178 .linkMode = ldmaLinkModeRel, \
2179 .link = 1, \
2180 .linkAddr = (linkjmp) * LDMA_DESCRIPTOR_NON_EXTEND_SIZE_WORD \
2181 } \
2182 }
2183
2184 #if defined(_LDMA_CH_CTRL_EXTEND_MASK)
2185 /**
2186 * @brief
2187 * DMA descriptor initializer for byte transfers from a peripheral to memory
2188 * using the extended descriptor fields.
2189 * @param[in] src Peripheral data source register address.
2190 * @param[in] dest Destination data address.
2191 * @param[in] count Number of bytes to transfer.
2192 * @param[in] linkjmp Address of descriptor to link to, expressed as a
2193 * signed number of descriptors from "here".
2194 * 1=one descriptor forward in memory,
2195 * 0=this descriptor,
2196 * -1=one descriptor back in memory.
2197 */
2198 #define LDMA_DESCRIPTOR_LINKREL_P2M_BYTE_EXTEND(src, dest, count, linkjmp) \
2199 { \
2200 .structType = ldmaCtrlStructTypeXfer, \
2201 .extend = 1, \
2202 .structReq = 0, \
2203 .xferCnt = (count) - 1, \
2204 .byteSwap = 0, \
2205 .blockSize = ldmaCtrlBlockSizeUnit1, \
2206 .doneIfs = 1, \
2207 .reqMode = ldmaCtrlReqModeBlock, \
2208 .decLoopCnt = 0, \
2209 .ignoreSrec = 0, \
2210 .srcInc = ldmaCtrlSrcIncNone, \
2211 .size = ldmaCtrlSizeByte, \
2212 .dstInc = ldmaCtrlDstIncNone, \
2213 .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \
2214 .dstAddrMode = ldmaCtrlDstAddrModeAbs, \
2215 .srcAddr = (uint32_t)(src), \
2216 .dstAddr = (uint32_t)(dest), \
2217 .linkMode = ldmaLinkModeRel, \
2218 .link = 1, \
2219 .linkAddr = (linkjmp) * LDMA_DESCRIPTOR_EXTEND_SIZE_WORD, \
2220 .dstIlEn = 0, \
2221 .IlMode = 0, \
2222 .bufferable = 0, \
2223 .IlSrc = 0 \
2224 }
2225 #endif
2226
2227 /**
2228 * @brief
2229 * DMA descriptor initializer for word transfers from a peripheral to memory.
2230 * @param[in] src Peripheral data source register address.
2231 * @param[in] dest Destination data address.
2232 * @param[in] count Number of words to transfer.
2233 * @param[in] linkjmp Address of descriptor to link to, expressed as a
2234 * signed number of descriptors from "here".
2235 * 1=one descriptor forward in memory,
2236 * 0=this descriptor,
2237 * -1=one descriptor back in memory.
2238 */
2239 #define LDMA_DESCRIPTOR_LINKREL_P2M_WORD(src, dest, count, linkjmp) \
2240 { \
2241 .xfer = \
2242 { \
2243 .structType = ldmaCtrlStructTypeXfer, \
2244 .structReq = 0, \
2245 .xferCnt = (count) - 1, \
2246 .byteSwap = 0, \
2247 .blockSize = ldmaCtrlBlockSizeUnit1, \
2248 .doneIfs = 1, \
2249 .reqMode = ldmaCtrlReqModeBlock, \
2250 .decLoopCnt = 0, \
2251 .ignoreSrec = 0, \
2252 .srcInc = ldmaCtrlSrcIncNone, \
2253 .size = ldmaCtrlSizeWord, \
2254 .dstInc = ldmaCtrlDstIncOne, \
2255 .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \
2256 .dstAddrMode = ldmaCtrlDstAddrModeAbs, \
2257 .srcAddr = (uint32_t)(src), \
2258 .dstAddr = (uint32_t)(dest), \
2259 .linkMode = ldmaLinkModeRel, \
2260 .link = 1, \
2261 .linkAddr = (linkjmp) * LDMA_DESCRIPTOR_NON_EXTEND_SIZE_WORD \
2262 } \
2263 }
2264
2265 #if defined(_LDMA_CH_CTRL_EXTEND_MASK)
2266 /**
2267 * @brief
2268 * DMA descriptor initializer for word transfers from a peripheral to memory
2269 * using the extended descriptor fields.
2270 * @param[in] src Peripheral data source register address.
2271 * @param[in] dest Destination data address.
2272 * @param[in] count Number of words to transfer.
2273 * @param[in] linkjmp Address of descriptor to link to, expressed as a
2274 * signed number of descriptors from "here".
2275 * 1=one descriptor forward in memory,
2276 * 0=this descriptor,
2277 * -1=one descriptor back in memory.
2278 */
2279 #define LDMA_DESCRIPTOR_LINKREL_P2M_WORD_EXTEND(src, dest, count, linkjmp) \
2280 { \
2281 .structType = ldmaCtrlStructTypeXfer, \
2282 .extend = 1, \
2283 .structReq = 0, \
2284 .xferCnt = (count) - 1, \
2285 .byteSwap = 0, \
2286 .blockSize = ldmaCtrlBlockSizeUnit1, \
2287 .doneIfs = 1, \
2288 .reqMode = ldmaCtrlReqModeBlock, \
2289 .decLoopCnt = 0, \
2290 .ignoreSrec = 0, \
2291 .srcInc = ldmaCtrlSrcIncNone, \
2292 .size = ldmaCtrlSizeWord, \
2293 .dstInc = ldmaCtrlDstIncNone, \
2294 .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \
2295 .dstAddrMode = ldmaCtrlDstAddrModeAbs, \
2296 .srcAddr = (uint32_t)(src), \
2297 .dstAddr = (uint32_t)(dest), \
2298 .linkMode = ldmaLinkModeRel, \
2299 .link = 1, \
2300 .linkAddr = (linkjmp) * LDMA_DESCRIPTOR_EXTEND_SIZE_WORD, \
2301 .dstIlEn = 0, \
2302 .IlMode = 0, \
2303 .bufferable = 0, \
2304 .IlSrc = 0 \
2305 }
2306 #endif
2307
2308 /**
2309 * @brief
2310 * DMA descriptor initializer for byte transfers from memory to a peripheral.
2311 * @param[in] src Source data address.
2312 * @param[in] dest Peripheral data register destination address.
2313 * @param[in] count Number of bytes to transfer.
2314 * @param[in] linkjmp Address of descriptor to link to, expressed as a
2315 * signed number of descriptors from "here".
2316 * 1=one descriptor forward in memory,
2317 * 0=this descriptor,
2318 * -1=one descriptor back in memory.
2319 */
2320 #define LDMA_DESCRIPTOR_LINKREL_M2P_BYTE(src, dest, count, linkjmp) \
2321 { \
2322 .xfer = \
2323 { \
2324 .structType = ldmaCtrlStructTypeXfer, \
2325 .structReq = 0, \
2326 .xferCnt = (count) - 1, \
2327 .byteSwap = 0, \
2328 .blockSize = ldmaCtrlBlockSizeUnit1, \
2329 .doneIfs = 1, \
2330 .reqMode = ldmaCtrlReqModeBlock, \
2331 .decLoopCnt = 0, \
2332 .ignoreSrec = 0, \
2333 .srcInc = ldmaCtrlSrcIncOne, \
2334 .size = ldmaCtrlSizeByte, \
2335 .dstInc = ldmaCtrlDstIncNone, \
2336 .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \
2337 .dstAddrMode = ldmaCtrlDstAddrModeAbs, \
2338 .srcAddr = (uint32_t)(src), \
2339 .dstAddr = (uint32_t)(dest), \
2340 .linkMode = ldmaLinkModeRel, \
2341 .link = 1, \
2342 .linkAddr = (linkjmp) * LDMA_DESCRIPTOR_NON_EXTEND_SIZE_WORD \
2343 } \
2344 }
2345
2346 #if defined(_LDMA_CH_CTRL_EXTEND_MASK)
2347 /**
2348 * @brief
2349 * DMA descriptor initializer for byte transfers from memory to a peripheral
2350 * using the extended descriptor fields.
2351 * @note
2352 * For the extended descriptor, if IlMode uses the absolute addressing, the
2353 * rules are used directly as the destination addresses of the corresponding
2354 * data. Thus the argument 'dest' will be ignored by the DMA engine.
2355 * @param[in] src Source data address.
2356 * @param[in] dest Peripheral data register destination address.
2357 * @param[in] count Number of bytes to transfer.
2358 * @param[in] linkjmp Address of descriptor to link to, expressed as a
2359 * signed number of descriptors from "here".
2360 * 1=one descriptor forward in memory,
2361 * 0=this descriptor,
2362 * -1=one descriptor back in memory.
2363 */
2364 #define LDMA_DESCRIPTOR_LINKREL_M2P_BYTE_EXTEND(src, dest, count, linkjmp) \
2365 { \
2366 .structType = ldmaCtrlStructTypeXfer, \
2367 .extend = 1, \
2368 .structReq = 0, \
2369 .xferCnt = (count) - 1, \
2370 .byteSwap = 0, \
2371 .blockSize = ldmaCtrlBlockSizeUnit1, \
2372 .doneIfs = 1, \
2373 .reqMode = ldmaCtrlReqModeBlock, \
2374 .decLoopCnt = 0, \
2375 .ignoreSrec = 0, \
2376 .srcInc = ldmaCtrlSrcIncOne, \
2377 .size = ldmaCtrlSizeByte, \
2378 .dstInc = ldmaCtrlDstIncNone, \
2379 .srcAddrMode = ldmaCtrlSrcAddrModeAbs, \
2380 .dstAddrMode = ldmaCtrlDstAddrModeAbs, \
2381 .srcAddr = (uint32_t)(src), \
2382 .dstAddr = (uint32_t)(dest), \
2383 .linkMode = ldmaLinkModeRel, \
2384 .link = 1, \
2385 .linkAddr = (linkjmp) * LDMA_DESCRIPTOR_EXTEND_SIZE_WORD, \
2386 .dstIlEn = 0, \
2387 .IlMode = 0, \
2388 .bufferable = 0, \
2389 .IlSrc = 0 \
2390 }
2391 #endif
2392
2393 /**
2394 * @brief
2395 * DMA descriptor initializer for Immediate WRITE transfer
2396 * @param[in] value Immediate value to write.
2397 * @param[in] address Write address.
2398 */
2399 #define LDMA_DESCRIPTOR_SINGLE_WRITE(value, address) \
2400 { \
2401 .wri = \
2402 { \
2403 .structType = ldmaCtrlStructTypeWrite, \
2404 .structReq = 1, \
2405 .xferCnt = 0, \
2406 .byteSwap = 0, \
2407 .blockSize = 0, \
2408 .doneIfs = 1, \
2409 .reqMode = 0, \
2410 .decLoopCnt = 0, \
2411 .ignoreSrec = 0, \
2412 .srcInc = 0, \
2413 .size = 0, \
2414 .dstInc = 0, \
2415 .srcAddrMode = 0, \
2416 .dstAddrMode = 0, \
2417 .immVal = (value), \
2418 .dstAddr = (uint32_t)(address), \
2419 .linkMode = 0, \
2420 .link = 0, \
2421 .linkAddr = 0 \
2422 } \
2423 }
2424
2425 /**
2426 * @brief
2427 * DMA descriptor initializer for Immediate WRITE transfer
2428 *
2429 * Link address must be an absolute address.
2430 * @note
2431 * The linkAddr member of the transfer descriptor is not initialized.
2432 * linkAddr must be initialized by using the proper bits right-shift
2433 * to get the correct bits from the absolute address.
2434 * LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR should be used for that operation:
2435 * @code
2436 desc.linkAddr = LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR(&next_desc);@endcode
2437 * The opposite bit shift (left) must be done with LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR
2438 * if linkAddr is read.
2439 * @param[in] value Immediate value to write.
2440 * @param[in] address Write address.
2441 */
2442 #define LDMA_DESCRIPTOR_LINKABS_WRITE(value, address) \
2443 { \
2444 .wri = \
2445 { \
2446 .structType = ldmaCtrlStructTypeWrite, \
2447 .structReq = 1, \
2448 .xferCnt = 0, \
2449 .byteSwap = 0, \
2450 .blockSize = 0, \
2451 .doneIfs = 0, \
2452 .reqMode = 0, \
2453 .decLoopCnt = 0, \
2454 .ignoreSrec = 0, \
2455 .srcInc = 0, \
2456 .size = 0, \
2457 .dstInc = 0, \
2458 .srcAddrMode = 0, \
2459 .dstAddrMode = 0, \
2460 .immVal = (value), \
2461 .dstAddr = (uint32_t)(address), \
2462 .linkMode = ldmaLinkModeAbs, \
2463 .link = 1, \
2464 .linkAddr = 0 /* Must be set runtime ! */ \
2465 } \
2466 }
2467
2468 /**
2469 * @brief
2470 * DMA descriptor initializer for Immediate WRITE transfer
2471 * @param[in] value Immediate value to write.
2472 * @param[in] address Write address.
2473 * @param[in] linkjmp Address of descriptor to link to, expressed as a
2474 * signed number of descriptors from "here".
2475 * 1=one descriptor forward in memory,
2476 * 0=this descriptor,
2477 * -1=one descriptor back in memory.
2478 */
2479 #define LDMA_DESCRIPTOR_LINKREL_WRITE(value, address, linkjmp) \
2480 { \
2481 .wri = \
2482 { \
2483 .structType = ldmaCtrlStructTypeWrite, \
2484 .structReq = 1, \
2485 .xferCnt = 0, \
2486 .byteSwap = 0, \
2487 .blockSize = 0, \
2488 .doneIfs = 0, \
2489 .reqMode = 0, \
2490 .decLoopCnt = 0, \
2491 .ignoreSrec = 0, \
2492 .srcInc = 0, \
2493 .size = 0, \
2494 .dstInc = 0, \
2495 .srcAddrMode = 0, \
2496 .dstAddrMode = 0, \
2497 .immVal = (value), \
2498 .dstAddr = (uint32_t)(address), \
2499 .linkMode = ldmaLinkModeRel, \
2500 .link = 1, \
2501 .linkAddr = (linkjmp) * LDMA_DESCRIPTOR_NON_EXTEND_SIZE_WORD \
2502 } \
2503 }
2504
2505 /**
2506 * @brief
2507 * DMA descriptor initializer for SYNC transfer
2508 * @param[in] set Sync pattern bits to set.
2509 * @param[in] clr Sync pattern bits to clear.
2510 * @param[in] matchValue Sync pattern to match.
2511 * @param[in] matchEnable Sync pattern bits to enable for match.
2512 */
2513 #define LDMA_DESCRIPTOR_SINGLE_SYNC(set, clr, matchValue, matchEnable) \
2514 { \
2515 .sync = \
2516 { \
2517 .structType = ldmaCtrlStructTypeSync, \
2518 .structReq = 1, \
2519 .xferCnt = 0, \
2520 .byteSwap = 0, \
2521 .blockSize = 0, \
2522 .doneIfs = 1, \
2523 .reqMode = 0, \
2524 .decLoopCnt = 0, \
2525 .ignoreSrec = 0, \
2526 .srcInc = 0, \
2527 .size = 0, \
2528 .dstInc = 0, \
2529 .srcAddrMode = 0, \
2530 .dstAddrMode = 0, \
2531 .syncSet = (set), \
2532 .syncClr = (clr), \
2533 .matchVal = (matchValue), \
2534 .matchEn = (matchEnable), \
2535 .linkMode = 0, \
2536 .link = 0, \
2537 .linkAddr = 0 \
2538 } \
2539 }
2540
2541 /**
2542 * @brief
2543 * DMA descriptor initializer for SYNC transfer
2544 *
2545 * Link address must be an absolute address.
2546 * @note
2547 * The linkAddr member of the transfer descriptor is not initialized.
2548 * linkAddr must be initialized by using the proper bits right-shift
2549 * to get the correct bits from the absolute address.
2550 * LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR should be used for that operation:
2551 * @code
2552 desc.linkAddr = LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR(&next_desc);@endcode
2553 * The opposite bit shift (left) must be done with LDMA_DESCRIPTOR_LINKABS_ADDR_TO_LINKADDR
2554 * if linkAddr is read.
2555 * @param[in] set Sync pattern bits to set.
2556 * @param[in] clr Sync pattern bits to clear.
2557 * @param[in] matchValue Sync pattern to match.
2558 * @param[in] matchEnable Sync pattern bits to enable for match.
2559 */
2560 #define LDMA_DESCRIPTOR_LINKABS_SYNC(set, clr, matchValue, matchEnable) \
2561 { \
2562 .sync = \
2563 { \
2564 .structType = ldmaCtrlStructTypeSync, \
2565 .structReq = 1, \
2566 .xferCnt = 0, \
2567 .byteSwap = 0, \
2568 .blockSize = 0, \
2569 .doneIfs = 0, \
2570 .reqMode = 0, \
2571 .decLoopCnt = 0, \
2572 .ignoreSrec = 0, \
2573 .srcInc = 0, \
2574 .size = 0, \
2575 .dstInc = 0, \
2576 .srcAddrMode = 0, \
2577 .dstAddrMode = 0, \
2578 .syncSet = (set), \
2579 .syncClr = (clr), \
2580 .matchVal = (matchValue), \
2581 .matchEn = (matchEnable), \
2582 .linkMode = ldmaLinkModeAbs, \
2583 .link = 1, \
2584 .linkAddr = 0 /* Must be set runtime ! */ \
2585 } \
2586 }
2587
2588 /**
2589 * @brief
2590 * DMA descriptor initializer for SYNC transfer
2591 * @param[in] set Sync pattern bits to set.
2592 * @param[in] clr Sync pattern bits to clear.
2593 * @param[in] matchValue Sync pattern to match.
2594 * @param[in] matchEnable Sync pattern bits to enable for match.
2595 * @param[in] linkjmp Address of descriptor to link to, expressed as a
2596 * signed number of descriptors from "here".
2597 * 1=one descriptor forward in memory,
2598 * 0=this descriptor,
2599 * -1=one descriptor back in memory.
2600 */
2601 #define LDMA_DESCRIPTOR_LINKREL_SYNC(set, clr, matchValue, matchEnable, linkjmp) \
2602 { \
2603 .sync = \
2604 { \
2605 .structType = ldmaCtrlStructTypeSync, \
2606 .structReq = 1, \
2607 .xferCnt = 0, \
2608 .byteSwap = 0, \
2609 .blockSize = 0, \
2610 .doneIfs = 0, \
2611 .reqMode = 0, \
2612 .decLoopCnt = 0, \
2613 .ignoreSrec = 0, \
2614 .srcInc = 0, \
2615 .size = 0, \
2616 .dstInc = 0, \
2617 .srcAddrMode = 0, \
2618 .dstAddrMode = 0, \
2619 .syncSet = (set), \
2620 .syncClr = (clr), \
2621 .matchVal = (matchValue), \
2622 .matchEn = (matchEnable), \
2623 .linkMode = ldmaLinkModeRel, \
2624 .link = 1, \
2625 .linkAddr = (linkjmp) * LDMA_DESCRIPTOR_NON_EXTEND_SIZE_WORD \
2626 } \
2627 }
2628
2629 #if defined(_LDMA_CH_CTRL_EXTEND_MASK)
2630 /**
2631 * @brief
2632 * Initializer for the destination interleaving portion of the DMA extended descriptor.
2633 * @param[in] desc Transfer-type descriptor.
2634 * @param[in] ilmode Rules table addressing mode for interleaved data.
2635 * @param[in] ilsrc Base address for rules table in memory.
2636 */
2637 #define LDMA_DESCRIPTOR_EXTEND_DST_IL_CFG(desc, ilmode, ilsrc) \
2638 { \
2639 (desc).dstIlEn = true; \
2640 (desc).IlMode = (ilmode); \
2641 (desc).IlSrc = (uint32_t)(ilsrc); \
2642 }
2643 #endif
2644
2645 /*******************************************************************************
2646 ***************************** PROTOTYPES **********************************
2647 ******************************************************************************/
2648
2649 void LDMA_DeInit(void);
2650 void LDMA_EnableChannelRequest(int ch, bool enable);
2651 void LDMA_Init(const LDMA_Init_t *init);
2652 void LDMA_StartTransfer(int ch,
2653 const LDMA_TransferCfg_t *transfer,
2654 const LDMA_Descriptor_t *descriptor);
2655 #if defined(_LDMA_CH_CTRL_EXTEND_MASK)
2656 void LDMA_StartTransferExtend(int ch,
2657 const LDMA_TransferCfg_t *transfer,
2658 const LDMA_DescriptorExtend_t *descriptor_ext);
2659 #endif
2660 void LDMA_StopTransfer(int ch);
2661 bool LDMA_TransferDone(int ch);
2662 uint32_t LDMA_TransferRemainingCount(int ch);
2663
2664 #if defined(_LDMA_SWRST_MASK)
2665 /***************************************************************************//**
2666 * @brief
2667 * Reset the LDMA.
2668 ******************************************************************************/
LDMA_Reset(void)2669 __STATIC_INLINE void LDMA_Reset(void)
2670 {
2671 LDMA->SWRST_SET = LDMA_SWRST_SWRST;
2672
2673 /* Wait for reset to complete. */
2674 while (0UL != (LDMA->SWRST & _LDMA_SWRST_RESETTING_MASK)) {
2675 }
2676 }
2677 #endif
2678
2679 /***************************************************************************//**
2680 * @brief
2681 * Check if a certain channel is enabled.
2682 *
2683 * @param[in] ch
2684 * LDMA channel to check.
2685 *
2686 * @return
2687 * return true if the LDMA channel is enabled and false if the channel is not
2688 * enabled.
2689 ******************************************************************************/
LDMA_ChannelEnabled(int ch)2690 __STATIC_INLINE bool LDMA_ChannelEnabled(int ch)
2691 {
2692 if ((ch < 0) || (ch > 31)) {
2693 return false;
2694 }
2695 #if defined(_LDMA_CHSTATUS_MASK)
2696 return (0UL != (LDMA->CHSTATUS & (1UL << (uint8_t)ch)));
2697 #else
2698 // We've already confirmed ch is between 0 and 31,
2699 // so it's now safe to cast it to uint8_t
2700 return (0UL != (LDMA->CHEN & (1 << (uint8_t)ch)));
2701 #endif
2702 }
2703
2704 /***************************************************************************//**
2705 * @brief
2706 * Clear one or more pending LDMA interrupts.
2707 *
2708 * @param[in] flags
2709 * Pending LDMA interrupt sources to clear. Use one or more valid
2710 * interrupt flags for the LDMA module. The flags are LDMA_IFC_ERROR
2711 * and one done flag for each channel.
2712 ******************************************************************************/
LDMA_IntClear(uint32_t flags)2713 __STATIC_INLINE void LDMA_IntClear(uint32_t flags)
2714 {
2715 #if defined (LDMA_HAS_SET_CLEAR)
2716 LDMA->IF_CLR = flags;
2717 #else
2718 LDMA->IFC = flags;
2719 #endif
2720 }
2721
2722 /***************************************************************************//**
2723 * @brief
2724 * Disable one or more LDMA interrupts.
2725 *
2726 * @param[in] flags
2727 * LDMA interrupt sources to disable. Use one or more valid
2728 * interrupt flags for LDMA module. The flags are LDMA_IEN_ERROR
2729 * and one done flag for each channel.
2730 ******************************************************************************/
LDMA_IntDisable(uint32_t flags)2731 __STATIC_INLINE void LDMA_IntDisable(uint32_t flags)
2732 {
2733 LDMA->IEN &= ~flags;
2734 }
2735
2736 /***************************************************************************//**
2737 * @brief
2738 * Enable one or more LDMA interrupts.
2739 *
2740 * @note
2741 * Depending on the use, a pending interrupt may already be set prior to
2742 * enabling the interrupt. To ignore a pending interrupt, consider using
2743 * LDMA_IntClear() prior to enabling the interrupt.
2744 *
2745 * @param[in] flags
2746 * LDMA interrupt sources to enable. Use one or more valid
2747 * interrupt flags for LDMA module. The flags are LDMA_IEN_ERROR
2748 * and one done flag for each channel.
2749 ******************************************************************************/
LDMA_IntEnable(uint32_t flags)2750 __STATIC_INLINE void LDMA_IntEnable(uint32_t flags)
2751 {
2752 LDMA->IEN |= flags;
2753 }
2754
2755 /***************************************************************************//**
2756 * @brief
2757 * Get pending LDMA interrupt flags.
2758 *
2759 * @note
2760 * Event bits are not cleared by the use of this function.
2761 *
2762 * @return
2763 * LDMA interrupt sources pending. Returns one or more valid
2764 * interrupt flags for LDMA module. The flags are LDMA_IF_ERROR and
2765 * one flag for each LDMA channel.
2766 ******************************************************************************/
LDMA_IntGet(void)2767 __STATIC_INLINE uint32_t LDMA_IntGet(void)
2768 {
2769 return LDMA->IF;
2770 }
2771
2772 /***************************************************************************//**
2773 * @brief
2774 * Get enabled and pending LDMA interrupt flags.
2775 * Useful for handling more interrupt sources in the same interrupt handler.
2776 *
2777 * @note
2778 * Interrupt flags are not cleared by the use of this function.
2779 *
2780 * @return
2781 * Pending and enabled LDMA interrupt sources
2782 * Return value is the bitwise AND of
2783 * - the enabled interrupt sources in LDMA_IEN and
2784 * - the pending interrupt flags LDMA_IF
2785 ******************************************************************************/
LDMA_IntGetEnabled(void)2786 __STATIC_INLINE uint32_t LDMA_IntGetEnabled(void)
2787 {
2788 uint32_t ien;
2789
2790 ien = LDMA->IEN;
2791 return LDMA->IF & ien;
2792 }
2793
2794 /***************************************************************************//**
2795 * @brief
2796 * Set one or more pending LDMA interrupts
2797 *
2798 * @param[in] flags
2799 * LDMA interrupt sources to set to pending. Use one or more valid
2800 * interrupt flags for LDMA module. The flags are LDMA_IFS_ERROR and
2801 * one done flag for each LDMA channel.
2802 ******************************************************************************/
LDMA_IntSet(uint32_t flags)2803 __STATIC_INLINE void LDMA_IntSet(uint32_t flags)
2804 {
2805 #if defined (LDMA_HAS_SET_CLEAR)
2806 LDMA->IF_SET = flags;
2807 #else
2808 LDMA->IFS = flags;
2809 #endif
2810 }
2811
2812 /** @} (end addtogroup ldma) */
2813
2814 #ifdef __cplusplus
2815 }
2816 #endif
2817
2818 #endif /* defined( LDMA_PRESENT ) && ( LDMA_COUNT == 1 ) */
2819 #endif /* EM_LDMA_H */
2820
