1 /* 2 * Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef FSP_FEATURES_H 8 #define FSP_FEATURES_H 9 10 /*********************************************************************************************************************** 11 * Includes <System Includes> , "Project Includes" 12 **********************************************************************************************************************/ 13 14 /* C99 includes. */ 15 #include <stdint.h> 16 #include <stddef.h> 17 #include <stdbool.h> 18 #include <assert.h> 19 20 /* Different compiler support. */ 21 #include "fsp_common_api.h" 22 #include "../../fsp/src/bsp/mcu/all/bsp_compiler_support.h" 23 24 /*********************************************************************************************************************** 25 * Macro definitions 26 **********************************************************************************************************************/ 27 28 /*******************************************************************************************************************//** 29 * @addtogroup BSP_MCU 30 * @{ 31 **********************************************************************************************************************/ 32 33 /* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ 34 FSP_HEADER 35 36 /*********************************************************************************************************************** 37 * Typedef definitions 38 **********************************************************************************************************************/ 39 40 /** Available modules. */ 41 typedef enum e_fsp_ip 42 { 43 FSP_IP_CFLASH = 0, ///< Code Flash 44 FSP_IP_DFLASH = 1, ///< Data Flash 45 FSP_IP_RAM = 2, ///< RAM 46 FSP_IP_LVD = 3, ///< Low Voltage Detection 47 FSP_IP_CGC = 3, ///< Clock Generation Circuit 48 FSP_IP_LPM = 3, ///< Low Power Modes 49 FSP_IP_FCU = 4, ///< Flash Control Unit 50 FSP_IP_ICU = 6, ///< Interrupt Control Unit 51 FSP_IP_DMAC = 7, ///< DMA Controller 52 FSP_IP_DTC = 8, ///< Data Transfer Controller 53 FSP_IP_IOPORT = 9, ///< I/O Ports 54 FSP_IP_PFS = 10, ///< Pin Function Select 55 FSP_IP_ELC = 11, ///< Event Link Controller 56 FSP_IP_MPU = 13, ///< Memory Protection Unit 57 FSP_IP_MSTP = 14, ///< Module Stop 58 FSP_IP_MMF = 15, ///< Memory Mirror Function 59 FSP_IP_KEY = 16, ///< Key Interrupt Function 60 FSP_IP_CAC = 17, ///< Clock Frequency Accuracy Measurement Circuit 61 FSP_IP_DOC = 18, ///< Data Operation Circuit 62 FSP_IP_CRC = 19, ///< Cyclic Redundancy Check Calculator 63 FSP_IP_SCI = 20, ///< Serial Communications Interface 64 FSP_IP_IIC = 21, ///< I2C Bus Interface 65 FSP_IP_SPI = 22, ///< Serial Peripheral Interface 66 FSP_IP_CTSU = 23, ///< Capacitive Touch Sensing Unit 67 FSP_IP_SCE = 24, ///< Secure Cryptographic Engine 68 FSP_IP_SLCDC = 25, ///< Segment LCD Controller 69 FSP_IP_AES = 26, ///< Advanced Encryption Standard 70 FSP_IP_TRNG = 27, ///< True Random Number Generator 71 FSP_IP_FCACHE = 30, ///< Flash Cache 72 FSP_IP_SRAM = 31, ///< SRAM 73 FSP_IP_ADC = 32, ///< A/D Converter 74 FSP_IP_DAC = 33, ///< 12-Bit D/A Converter 75 FSP_IP_TSN = 34, ///< Temperature Sensor 76 FSP_IP_DAAD = 35, ///< D/A A/D Synchronous Unit 77 FSP_IP_ACMPHS = 36, ///< High Speed Analog Comparator 78 FSP_IP_ACMPLP = 37, ///< Low Power Analog Comparator 79 FSP_IP_OPAMP = 38, ///< Operational Amplifier 80 FSP_IP_SDADC = 39, ///< Sigma Delta A/D Converter 81 FSP_IP_RTC = 40, ///< Real Time Clock 82 FSP_IP_WDT = 41, ///< Watch Dog Timer 83 FSP_IP_IWDT = 42, ///< Independent Watch Dog Timer 84 FSP_IP_GPT = 43, ///< General PWM Timer 85 FSP_IP_POEG = 44, ///< Port Output Enable for GPT 86 FSP_IP_OPS = 45, ///< Output Phase Switch 87 FSP_IP_AGT = 47, ///< Asynchronous General-Purpose Timer 88 FSP_IP_CAN = 48, ///< Controller Area Network 89 FSP_IP_IRDA = 49, ///< Infrared Data Association 90 FSP_IP_QSPI = 50, ///< Quad Serial Peripheral Interface 91 FSP_IP_USBFS = 51, ///< USB Full Speed 92 FSP_IP_SDHI = 52, ///< SD/MMC Host Interface 93 FSP_IP_SRC = 53, ///< Sampling Rate Converter 94 FSP_IP_SSI = 54, ///< Serial Sound Interface 95 FSP_IP_DALI = 55, ///< Digital Addressable Lighting Interface 96 FSP_IP_ETHER = 64, ///< Ethernet MAC Controller 97 FSP_IP_EDMAC = 64, ///< Ethernet DMA Controller 98 FSP_IP_EPTPC = 65, ///< Ethernet PTP Controller 99 FSP_IP_PDC = 66, ///< Parallel Data Capture Unit 100 FSP_IP_GLCDC = 67, ///< Graphics LCD Controller 101 FSP_IP_DRW = 68, ///< 2D Drawing Engine 102 FSP_IP_JPEG = 69, ///< JPEG 103 FSP_IP_DAC8 = 70, ///< 8-Bit D/A Converter 104 FSP_IP_USBHS = 71, ///< USB High Speed 105 FSP_IP_OSPI = 72, ///< Octa Serial Peripheral Interface 106 FSP_IP_CEC = 73, ///< HDMI CEC 107 FSP_IP_TFU = 74, ///< Trigonometric Function Unit 108 FSP_IP_IIRFA = 75, ///< IIR Filter Accelerator 109 FSP_IP_CANFD = 76, ///< CAN-FD 110 FSP_IP_ULPT = 77, ///< Ultra Low Power Timer ULPT 111 FSP_IP_SAU = 78, ///< Serial Array Unit 112 FSP_IP_IICA = 79, ///< Serial Interface IICA 113 FSP_IP_UARTA = 80, ///< Serial Interface UARTA 114 FSP_IP_TAU = 81, ///< Timer Array Unit 115 FSP_IP_TML = 82, ///< 32-bit Interval Timer 116 FSP_IP_MACL = 83, ///< 32-bit Multiply-Accumulator 117 } fsp_ip_t; 118 119 /** Signals that can be mapped to an interrupt. */ 120 typedef enum e_fsp_signal 121 { 122 FSP_SIGNAL_ADC_COMPARE_MATCH = 0, ///< ADC COMPARE MATCH 123 FSP_SIGNAL_ADC_COMPARE_MISMATCH, ///< ADC COMPARE MISMATCH 124 FSP_SIGNAL_ADC_SCAN_END, ///< ADC SCAN END 125 FSP_SIGNAL_ADC_SCAN_END_B, ///< ADC SCAN END B 126 FSP_SIGNAL_ADC_WINDOW_A, ///< ADC WINDOW A 127 FSP_SIGNAL_ADC_WINDOW_B, ///< ADC WINDOW B 128 FSP_SIGNAL_AES_RDREQ = 0, ///< AES RDREQ 129 FSP_SIGNAL_AES_WRREQ, ///< AES WRREQ 130 FSP_SIGNAL_AGT_COMPARE_A = 0, ///< AGT COMPARE A 131 FSP_SIGNAL_AGT_COMPARE_B, ///< AGT COMPARE B 132 FSP_SIGNAL_AGT_INT, ///< AGT INT 133 FSP_SIGNAL_CAC_FREQUENCY_ERROR = 0, ///< CAC FREQUENCY ERROR 134 FSP_SIGNAL_CAC_MEASUREMENT_END, ///< CAC MEASUREMENT END 135 FSP_SIGNAL_CAC_OVERFLOW, ///< CAC OVERFLOW 136 FSP_SIGNAL_CAN_ERROR = 0, ///< CAN ERROR 137 FSP_SIGNAL_CAN_FIFO_RX, ///< CAN FIFO RX 138 FSP_SIGNAL_CAN_FIFO_TX, ///< CAN FIFO TX 139 FSP_SIGNAL_CAN_MAILBOX_RX, ///< CAN MAILBOX RX 140 FSP_SIGNAL_CAN_MAILBOX_TX, ///< CAN MAILBOX TX 141 FSP_SIGNAL_CGC_MOSC_STOP = 0, ///< CGC MOSC STOP 142 FSP_SIGNAL_LPM_SNOOZE_REQUEST, ///< LPM SNOOZE REQUEST 143 FSP_SIGNAL_LVD_LVD1, ///< LVD LVD1 144 FSP_SIGNAL_LVD_LVD2, ///< LVD LVD2 145 FSP_SIGNAL_VBATT_LVD, ///< VBATT LVD 146 FSP_SIGNAL_LVD_VBATT = FSP_SIGNAL_VBATT_LVD, ///< LVD VBATT 147 FSP_SIGNAL_ACMPHS_INT = 0, ///< ACMPHS INT 148 FSP_SIGNAL_ACMPLP_INT = 0, ///< ACMPLP INT 149 FSP_SIGNAL_CTSU_END = 0, ///< CTSU END 150 FSP_SIGNAL_CTSU_READ, ///< CTSU READ 151 FSP_SIGNAL_CTSU_WRITE, ///< CTSU WRITE 152 FSP_SIGNAL_DALI_DEI = 0, ///< DALI DEI 153 FSP_SIGNAL_DALI_CLI, ///< DALI CLI 154 FSP_SIGNAL_DALI_SDI, ///< DALI SDI 155 FSP_SIGNAL_DALI_BPI, ///< DALI BPI 156 FSP_SIGNAL_DALI_FEI, ///< DALI FEI 157 FSP_SIGNAL_DALI_SDI_OR_BPI, ///< DALI SDI OR BPI 158 FSP_SIGNAL_DMAC_INT = 0, ///< DMAC INT 159 FSP_SIGNAL_DOC_INT = 0, ///< DOC INT 160 FSP_SIGNAL_DRW_INT = 0, ///< DRW INT 161 FSP_SIGNAL_DTC_COMPLETE = 0, ///< DTC COMPLETE 162 FSP_SIGNAL_DTC_END, ///< DTC END 163 FSP_SIGNAL_EDMAC_EINT = 0, ///< EDMAC EINT 164 FSP_SIGNAL_ELC_SOFTWARE_EVENT_0 = 0, ///< ELC SOFTWARE EVENT 0 165 FSP_SIGNAL_ELC_SOFTWARE_EVENT_1, ///< ELC SOFTWARE EVENT 1 166 FSP_SIGNAL_EPTPC_IPLS = 0, ///< EPTPC IPLS 167 FSP_SIGNAL_EPTPC_MINT, ///< EPTPC MINT 168 FSP_SIGNAL_EPTPC_PINT, ///< EPTPC PINT 169 FSP_SIGNAL_EPTPC_TIMER0_FALL, ///< EPTPC TIMER0 FALL 170 FSP_SIGNAL_EPTPC_TIMER0_RISE, ///< EPTPC TIMER0 RISE 171 FSP_SIGNAL_EPTPC_TIMER1_FALL, ///< EPTPC TIMER1 FALL 172 FSP_SIGNAL_EPTPC_TIMER1_RISE, ///< EPTPC TIMER1 RISE 173 FSP_SIGNAL_EPTPC_TIMER2_FALL, ///< EPTPC TIMER2 FALL 174 FSP_SIGNAL_EPTPC_TIMER2_RISE, ///< EPTPC TIMER2 RISE 175 FSP_SIGNAL_EPTPC_TIMER3_FALL, ///< EPTPC TIMER3 FALL 176 FSP_SIGNAL_EPTPC_TIMER3_RISE, ///< EPTPC TIMER3 RISE 177 FSP_SIGNAL_EPTPC_TIMER4_FALL, ///< EPTPC TIMER4 FALL 178 FSP_SIGNAL_EPTPC_TIMER4_RISE, ///< EPTPC TIMER4 RISE 179 FSP_SIGNAL_EPTPC_TIMER5_FALL, ///< EPTPC TIMER5 FALL 180 FSP_SIGNAL_EPTPC_TIMER5_RISE, ///< EPTPC TIMER5 RISE 181 FSP_SIGNAL_FCU_FIFERR = 0, ///< FCU FIFERR 182 FSP_SIGNAL_FCU_FRDYI, ///< FCU FRDYI 183 FSP_SIGNAL_GLCDC_LINE_DETECT = 0, ///< GLCDC LINE DETECT 184 FSP_SIGNAL_GLCDC_UNDERFLOW_1, ///< GLCDC UNDERFLOW 1 185 FSP_SIGNAL_GLCDC_UNDERFLOW_2, ///< GLCDC UNDERFLOW 2 186 FSP_SIGNAL_GPT_CAPTURE_COMPARE_A = 0, ///< GPT CAPTURE COMPARE A 187 FSP_SIGNAL_GPT_CAPTURE_COMPARE_B, ///< GPT CAPTURE COMPARE B 188 FSP_SIGNAL_GPT_COMPARE_C, ///< GPT COMPARE C 189 FSP_SIGNAL_GPT_COMPARE_D, ///< GPT COMPARE D 190 FSP_SIGNAL_GPT_COMPARE_E, ///< GPT COMPARE E 191 FSP_SIGNAL_GPT_COMPARE_F, ///< GPT COMPARE F 192 FSP_SIGNAL_GPT_COUNTER_OVERFLOW, ///< GPT COUNTER OVERFLOW 193 FSP_SIGNAL_GPT_COUNTER_UNDERFLOW, ///< GPT COUNTER UNDERFLOW 194 FSP_SIGNAL_GPT_AD_TRIG_A, ///< GPT AD TRIG A 195 FSP_SIGNAL_GPT_AD_TRIG_B, ///< GPT AD TRIG B 196 FSP_SIGNAL_OPS_UVW_EDGE, ///< OPS UVW EDGE 197 FSP_SIGNAL_ICU_IRQ0 = 0, ///< ICU IRQ0 198 FSP_SIGNAL_ICU_IRQ1, ///< ICU IRQ1 199 FSP_SIGNAL_ICU_IRQ2, ///< ICU IRQ2 200 FSP_SIGNAL_ICU_IRQ3, ///< ICU IRQ3 201 FSP_SIGNAL_ICU_IRQ4, ///< ICU IRQ4 202 FSP_SIGNAL_ICU_IRQ5, ///< ICU IRQ5 203 FSP_SIGNAL_ICU_IRQ6, ///< ICU IRQ6 204 FSP_SIGNAL_ICU_IRQ7, ///< ICU IRQ7 205 FSP_SIGNAL_ICU_IRQ8, ///< ICU IRQ8 206 FSP_SIGNAL_ICU_IRQ9, ///< ICU IRQ9 207 FSP_SIGNAL_ICU_IRQ10, ///< ICU IRQ10 208 FSP_SIGNAL_ICU_IRQ11, ///< ICU IRQ11 209 FSP_SIGNAL_ICU_IRQ12, ///< ICU IRQ12 210 FSP_SIGNAL_ICU_IRQ13, ///< ICU IRQ13 211 FSP_SIGNAL_ICU_IRQ14, ///< ICU IRQ14 212 FSP_SIGNAL_ICU_IRQ15, ///< ICU IRQ15 213 FSP_SIGNAL_ICU_SNOOZE_CANCEL, ///< ICU SNOOZE CANCEL 214 FSP_SIGNAL_IIC_ERI = 0, ///< IIC ERI 215 FSP_SIGNAL_IIC_RXI, ///< IIC RXI 216 FSP_SIGNAL_IIC_TEI, ///< IIC TEI 217 FSP_SIGNAL_IIC_TXI, ///< IIC TXI 218 FSP_SIGNAL_IIC_WUI, ///< IIC WUI 219 FSP_SIGNAL_IOPORT_EVENT_1 = 0, ///< IOPORT EVENT 1 220 FSP_SIGNAL_IOPORT_EVENT_2, ///< IOPORT EVENT 2 221 FSP_SIGNAL_IOPORT_EVENT_3, ///< IOPORT EVENT 3 222 FSP_SIGNAL_IOPORT_EVENT_4, ///< IOPORT EVENT 4 223 FSP_SIGNAL_IOPORT_EVENT_B = 0, ///< IOPORT EVENT B 224 FSP_SIGNAL_IOPORT_EVENT_C, ///< IOPORT EVENT C 225 FSP_SIGNAL_IOPORT_EVENT_D, ///< IOPORT EVENT D 226 FSP_SIGNAL_IOPORT_EVENT_E, ///< IOPORT EVENT E 227 FSP_SIGNAL_IWDT_UNDERFLOW = 0, ///< IWDT UNDERFLOW 228 FSP_SIGNAL_JPEG_JDTI = 0, ///< JPEG JDTI 229 FSP_SIGNAL_JPEG_JEDI, ///< JPEG JEDI 230 FSP_SIGNAL_KEY_INT = 0, ///< KEY INT 231 FSP_SIGNAL_PDC_FRAME_END = 0, ///< PDC FRAME END 232 FSP_SIGNAL_PDC_INT, ///< PDC INT 233 FSP_SIGNAL_PDC_RECEIVE_DATA_READY, ///< PDC RECEIVE DATA READY 234 FSP_SIGNAL_POEG_EVENT = 0, ///< POEG EVENT 235 FSP_SIGNAL_QSPI_INT = 0, ///< QSPI INT 236 FSP_SIGNAL_RTC_ALARM = 0, ///< RTC ALARM 237 FSP_SIGNAL_RTC_PERIOD, ///< RTC PERIOD 238 FSP_SIGNAL_RTC_CARRY, ///< RTC CARRY 239 FSP_SIGNAL_SCE_INTEGRATE_RDRDY = 0, ///< SCE INTEGRATE RDRDY 240 FSP_SIGNAL_SCE_INTEGRATE_WRRDY, ///< SCE INTEGRATE WRRDY 241 FSP_SIGNAL_SCE_LONG_PLG, ///< SCE LONG PLG 242 FSP_SIGNAL_SCE_PROC_BUSY, ///< SCE PROC BUSY 243 FSP_SIGNAL_SCE_RDRDY_0, ///< SCE RDRDY 0 244 FSP_SIGNAL_SCE_RDRDY_1, ///< SCE RDRDY 1 245 FSP_SIGNAL_SCE_ROMOK, ///< SCE ROMOK 246 FSP_SIGNAL_SCE_TEST_BUSY, ///< SCE TEST BUSY 247 FSP_SIGNAL_SCE_WRRDY_0, ///< SCE WRRDY 0 248 FSP_SIGNAL_SCE_WRRDY_1, ///< SCE WRRDY 1 249 FSP_SIGNAL_SCE_WRRDY_4, ///< SCE WRRDY 4 250 FSP_SIGNAL_SCI_AM = 0, ///< SCI AM 251 FSP_SIGNAL_SCI_ERI, ///< SCI ERI 252 FSP_SIGNAL_SCI_RXI, ///< SCI RXI 253 FSP_SIGNAL_SCI_RXI_OR_ERI, ///< SCI RXI OR ERI 254 FSP_SIGNAL_SCI_TEI, ///< SCI TEI 255 FSP_SIGNAL_SCI_TXI, ///< SCI TXI 256 FSP_SIGNAL_SDADC_ADI = 0, ///< SDADC ADI 257 FSP_SIGNAL_SDADC_SCANEND, ///< SDADC SCANEND 258 FSP_SIGNAL_SDADC_CALIEND, ///< SDADC CALIEND 259 FSP_SIGNAL_SDHIMMC_ACCS = 0, ///< SDHIMMC ACCS 260 FSP_SIGNAL_SDHIMMC_CARD, ///< SDHIMMC CARD 261 FSP_SIGNAL_SDHIMMC_DMA_REQ, ///< SDHIMMC DMA REQ 262 FSP_SIGNAL_SDHIMMC_SDIO, ///< SDHIMMC SDIO 263 FSP_SIGNAL_SPI_ERI = 0, ///< SPI ERI 264 FSP_SIGNAL_SPI_IDLE, ///< SPI IDLE 265 FSP_SIGNAL_SPI_RXI, ///< SPI RXI 266 FSP_SIGNAL_SPI_TEI, ///< SPI TEI 267 FSP_SIGNAL_SPI_TXI, ///< SPI TXI 268 FSP_SIGNAL_SRC_CONVERSION_END = 0, ///< SRC CONVERSION END 269 FSP_SIGNAL_SRC_INPUT_FIFO_EMPTY, ///< SRC INPUT FIFO EMPTY 270 FSP_SIGNAL_SRC_OUTPUT_FIFO_FULL, ///< SRC OUTPUT FIFO FULL 271 FSP_SIGNAL_SRC_OUTPUT_FIFO_OVERFLOW, ///< SRC OUTPUT FIFO OVERFLOW 272 FSP_SIGNAL_SRC_OUTPUT_FIFO_UNDERFLOW, ///< SRC OUTPUT FIFO UNDERFLOW 273 FSP_SIGNAL_SSI_INT = 0, ///< SSI INT 274 FSP_SIGNAL_SSI_RXI, ///< SSI RXI 275 FSP_SIGNAL_SSI_TXI, ///< SSI TXI 276 FSP_SIGNAL_SSI_TXI_RXI, ///< SSI TXI RXI 277 FSP_SIGNAL_TRNG_RDREQ = 0, ///< TRNG RDREQ 278 FSP_SIGNAL_USB_FIFO_0 = 0, ///< USB FIFO 0 279 FSP_SIGNAL_USB_FIFO_1, ///< USB FIFO 1 280 FSP_SIGNAL_USB_INT, ///< USB INT 281 FSP_SIGNAL_USB_RESUME, ///< USB RESUME 282 FSP_SIGNAL_USB_USB_INT_RESUME, ///< USB USB INT RESUME 283 FSP_SIGNAL_WDT_UNDERFLOW = 0, ///< WDT UNDERFLOW 284 FSP_SIGNAL_ULPT_COMPARE_A = 0, ///< ULPT COMPARE A 285 FSP_SIGNAL_ULPT_COMPARE_B, ///< ULPT COMPARE B 286 FSP_SIGNAL_ULPT_INT, ///< ULPT INT 287 } fsp_signal_t; 288 289 typedef void (* fsp_vector_t)(void); 290 291 /** @} (end addtogroup BSP_MCU) */ 292 293 /** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ 294 FSP_FOOTER 295 296 #endif 297
