1 /* 2 * ========================================================== 3 * 4 * Copyright (C) 2020 QuickLogic Corporation 5 * Licensed under the Apache License, Version 2.0 (the "License"); 6 * you may not use this file except in compliance with the License. 7 * You may obtain a copy of the License at 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * Unless required by applicable law or agreed to in writing, software 10 * distributed under the License is distributed on an "AS IS" BASIS, 11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 * See the License for the specific language governing permissions and 13 * limitations under the License. 14 * 15 * File : eoss3_dev.h 16 * Purpose : This file contains device mapping for 17 * interrupt vector, peripherals register mapping 18 * 19 * 20 * =========================================================== 21 * 22 */ 23 24 #ifndef __EOSS3_DEV_H 25 #define __EOSS3_DEV_H 26 27 #ifdef __cplusplus 28 extern "C" { 29 #endif /* __cplusplus */ 30 31 #include <stdint.h> 32 33 /// @cond EOSS3_DEV_MACROS 34 /** 35 * @brief Configuration of the Cortex-M4 Processor and Core Peripherals 36 */ 37 #define __CM4_REV 0x0001 /*!< Core revision r0p1 */ 38 #define __MPU_PRESENT 1 /*!< Tamar provides an MPU */ 39 #define __NVIC_PRIO_BITS 3 /*!< Tamar uses 3 Bits for the Priority Levels */ 40 #define __Vendor_SysTickConfig 1 /*!< Set to 1 if different SysTick Config is used */ 41 #define __FPU_PRESENT 1 /*!< FPU present */ 42 43 /* 44 * Interrupt Number Definition 45 */ 46 47 typedef enum 48 { 49 /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/ 50 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ 51 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ 52 BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ 53 UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ 54 SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ 55 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ 56 PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ 57 SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ 58 /****** Specific Interrupt Numbers **********************************************************************/ 59 SwInt2_IRQn = 0, 60 SwInt1_IRQn = 1, 61 Reserved1_IRQn = 2, 62 Ffe0Msg_IRQn = 3, 63 FbMsg_IRQn = 4, 64 Gpio_IRQn = 5, 65 SramSleep_IRQn = 6, 66 Uart_IRQn = 7, 67 Timer_IRQn = 8, 68 CpuWdtInt_IRQn = 9, 69 CpuWdtRst_IRQn = 10, 70 BusTimeout_IRQn = 11, 71 Fpu_IRQn = 12, 72 Pkfb_IRQn = 13, 73 Reserved_I2s_IRQn = 14, 74 Reserved_Audio_IRQn = 15, 75 SpiMs_IRQn = 16, 76 CfgDma_IRQn = 17, 77 PmuTimer_IRQn = 18, 78 AdcDone_IRQn = 19, 79 RtcAlarm_IRQn = 20, 80 ResetInt_IRQn = 21, 81 Ffe0_IRQn = 22, 82 FfeWdt_IRQn = 23, 83 ApBoot_IRQn = 24, 84 Ldo30_pg_IRQn = 25, 85 Ldo50_pg_IRQn = 26, 86 Sram_to_IRQn = 27, 87 Lpsd_IRQn = 28, 88 Dmic_IRQn = 29, 89 Reserved2_IRQn = 30, 90 Sdma_Done1_IRQn = 31, 91 Sdma_Done2_IRQn = 32, 92 Sdma_Done3_IRQn = 33, 93 Sdma_Done4_IRQn = 34, 94 Sdma_Done5_IRQn = 35, 95 Sdma_Done6_IRQn = 36, 96 Sdma_Done7_IRQn = 37, 97 Sdma_Done8_IRQn = 38, 98 Sdma_Done9_IRQn = 39, 99 Sdma_Done10_IRQn = 40, 100 Sdma_Done11_IRQn = 41, 101 Ap_Pdm_Clock_On_IRQn = 42, 102 Ap_Pdm_Clock_Off_IRQn = 43, 103 Dmac0_Block_Done_IRQn = 44, 104 Dmac0_Buffer_Done_IRQn = 45, 105 Dmac1_Block_Done_IRQn = 46, 106 Dmac1_Buffer_Done_IRQn = 47, 107 Sdma_Done0_IRQn = 48, 108 Sdma_Err_IRQn = 49, 109 I2SSlv_M4_IRQn = 50, 110 Lpsd_Voice_Off_IRQn = 51, 111 Dmic_Voice_Off_IRQn = 52 112 113 } IRQn_Type; 114 #include <core_cm4.h> /* Cortex-M4 processor and core peripherals */ 115 116 /* 117 * Peripheral_registers_structures 118 */ 119 120 /* 121 * Uart 122 */ 123 typedef struct 124 { 125 __IO uint32_t UART_DR; /* Data Address: 0x00 */ 126 __IO uint32_t UART_RSR; /* Receive Status Register: 0x04 */ 127 __IO uint32_t reserved1[4]; /* Reserved: 0x08 - 0x14 */ 128 __IO uint32_t UART_TFR; /* Flag Register 0x18 */ 129 __IO uint32_t reserved2[1]; /* Reserved 0x1C */ 130 __IO uint32_t UART_ILPR; /* IrDA Low Power Counter Register 0x20 */ 131 __IO uint32_t UART_IBRD; /* Integer Baud Rate Register 0x24 */ 132 __IO uint32_t UART_FBRD; /* Fractional Baud Rate Register 0x28 */ 133 __IO uint32_t UART_LCR_H; /* Line Control Register 0x2C */ 134 __IO uint32_t UART_CR; /* Control Register 0x30 */ 135 __IO uint32_t UART_IFLS; /* Interrupt FIFO Level Select Register 0x34 */ 136 __IO uint32_t UART_IMSC; /* Interrupt Mask Set/Clear Register 0x38 */ 137 __IO uint32_t UART_RIS; /* Raw Interrupt Status Register 0x3C */ 138 __IO uint32_t UART_MIS; /* Masked Interrupt Status Register 0x40 */ 139 __IO uint32_t UART_ICR; /* Interrupt Clear Register 0x44 */ 140 __IO uint32_t reserved4[14]; 141 __IO uint32_t UART_TCR; /* Test Control Register 0x48 */ 142 __IO uint32_t UART_ITIP; 143 __IO uint32_t UART_ITOP; 144 __IO uint32_t UART_TDR; 145 __IO uint32_t reserved3[980]; /* Reserved 0x4c - 0cFDC */ 146 __IO uint32_t UART_PeriphID0; /* Peri. ID0 Register (0x11) Address offset: 0xFE0 */ 147 __IO uint32_t UART_PeriphID1; /* Peri. ID1 Register (0x10) Address offset: 0xFE4 */ 148 __IO uint32_t UART_PeriphID2; /* Peri. ID2 Register Address offset: 0xFE8 */ 149 __IO uint32_t UART_PeriphID3; /* Peri. ID3 Register (0x00) Address offset: 0xFEC */ 150 __IO uint32_t UART_CellID0; /* Cell ID0 Register (0x0D) Address offset: 0xFF0 */ 151 __IO uint32_t UART_CellID1; /* Cell ID1 Register (0xF0) Address offset: 0xFF4 */ 152 __IO uint32_t UART_CellID2; /* Cell ID2 Register (0x05) Address offset: 0xFF8 */ 153 __IO uint32_t UART_CellID3; /* Cell ID3 Register (0xB1) Address offset: 0xFFC */ 154 } UART_TypeDef; 155 156 /* 157 * Pkfb 158 */ 159 typedef struct 160 { 161 __IO uint32_t PKFB_FIFOCTRL; /* PktFIFO Control Register 0x00 */ 162 __IO uint32_t PKFB_FIFOSRAMCTRL0; /* SRAM Test Control Register 0x04 */ 163 __IO uint32_t PKFB_FIFOSRAMCTRL1; /* SRAM Test Control Register, Address offset: 0x08 */ 164 __IO uint32_t PKFB_FIFOSTATUS; /* FIFO Status Register, Address offset: 0x0C */ 165 __IO uint32_t PKFB_PF0PUSHCTRL; /* FIFO 0 Push Control, Address offset: 0x10 */ 166 __IO uint32_t PKFB_PF0POPCTRL; /* FIFO 0 Pop Control, Address offset: 0x14 */ 167 __IO uint32_t PKFB_PF0CNT; /* FIFO 0 Count, Address offset: 0x18 */ 168 __IO uint32_t PKFB_PF0DATA; /* FIFO 0 Push/Pop Data Register, Address offset: 0x1C */ 169 __IO uint32_t PKFB_PF1PUSHCTRL; /* FIFO 1 Push Control, Address offset: 0x20 */ 170 __IO uint32_t PKFB_PF1POPCTRL; /* FIFO 1 Pop Control, Address offset: 0x24 */ 171 __IO uint32_t PKFB_PF1CNT; /* FIFO 1 Count, Address offset: 0x28 */ 172 __IO uint32_t PKFB_PF1DATA; /* FIFO 1 Push/Pop Data Register, Address offset: 0x2C */ 173 __IO uint32_t PKFB_PF2PUSHCTRL; /* FIFO 2 Push Control, Address offset: 0x30 */ 174 __IO uint32_t PKFB_PF2POPCTRL; /* FIFO 2 Pop Control, Address offset: 0x34 */ 175 __IO uint32_t PKFB_PF2CNT; /* FIFO 2 Count, Address offset: 0x38 */ 176 __IO uint32_t PKFB_PF2DATA; /* FIFO 2 Push/Pop Data Register, Address offset: 0x3C */ 177 __IO uint32_t PKFB_PF8KPUSHCTRL; /* FIFO 8K Push Control, Address offset: 0x40 */ 178 __IO uint32_t PKFB_PF8KPOPCTRL; /* FIFO 8K Pop Control, Address offset: 0x44 */ 179 __IO uint32_t PKFB_PF8KCNT; /* FIFO 8K Count, Address offset: 0x48 */ 180 __IO uint32_t PKFB_PF8KDATA; /* FIFO 8K Push/Pop Data Register, Address offset: 0x4C */ 181 __IO uint32_t PKFB_FIFO_COLL_INTR; /* FIFO Collision Interrupt Register, Address offset: 0x50 */ 182 __IO uint32_t PKFB_FIFO_COLL_INTR_EN; /* FIFO Collision Interrupt Enable Register Address offset: 0x54 */ 183 } PKFB_TypeDef; 184 185 typedef struct 186 { 187 __IO uint32_t CLK_CTRL_A_0; /* For Clock 1 & 10 0x00 */ 188 __IO uint32_t CLK_CTRL_A_1; /* 0x04 */ 189 __IO uint32_t CLK_CTRL_B_0; /* For Clock 2 0x08 */ 190 __IO uint32_t reserved; /* 0x0C */ 191 __IO uint32_t CLK_CTRL_C_0; /* For Clock 8 0x10 */ 192 __IO uint32_t CLK_CTRL_D_0; /* For Clock 11 0x14 */ 193 __IO uint32_t CLK_CTRL_E_0; /* For Clock 12 0x18 */ 194 __IO uint32_t reserved1; 195 __IO uint32_t CLK_CTRL_F_0; /* For Clock 16 0x20 */ 196 __IO uint32_t CLK_CTRL_F_1; /* 0x24 */ 197 __IO uint32_t CLK_CTRL_G_0; /* For Clock 18 0x28 */ 198 __IO uint32_t CLK_CTRL_H_0; /* For Clock 19 0x2C */ 199 __IO uint32_t reserved2; 200 __IO uint32_t CLK_CTRL_I_0; /* 0x34 */ 201 __IO uint32_t CLK_CTRL_I_1; /* 0x38 */ 202 __IO uint32_t reverved3; /* 0x3C */ 203 __IO uint32_t C01_CLK_GATE; /* 0x40 */ 204 __IO uint32_t C02_CLK_GATE; /* 0x44 */ 205 __IO uint32_t C08_X4_CLK_GATE; /* 0x48 */ 206 __IO uint32_t C08_X1_CLK_GATE; /* 0x4C */ 207 __IO uint32_t C10_FCLK_GATE; /* 0x50 */ 208 __IO uint32_t C11_CLK_GATE; /* 0x54 */ 209 __IO uint32_t C12_CLK_GATE; /* 0x58 */ 210 __IO uint32_t CS_CLK_GATE; /* 0x5C */ 211 __IO uint32_t CU_CLK_GATE; /* 0x60 */ 212 __IO uint32_t C16_CLK_GATE; /* 0x64 */ 213 __IO uint32_t reversed4; /* 0x68 */ 214 __IO uint32_t C19_CLK_GATE; /* 0x6C */ 215 __IO uint32_t C21_CLK_GATE; /* 0x70 */ 216 __IO uint32_t reversed5[3]; 217 __IO uint32_t PF_SW_RESET; /* 0x80 */ 218 __IO uint32_t FFE_SW_RESET; /* 0x84 */ 219 __IO uint32_t FB_SW_RESET; /* 0x88 */ 220 __IO uint32_t A1_SW_RESET; /* 0x8C */ 221 __IO uint32_t AUDIO_MISC_SW_RST; /* 0x90 */ 222 __IO uint32_t FB_MISC_SW_RST_CTL; /* 0x94 */ 223 __IO uint32_t reversed6[26]; 224 __IO uint32_t CLK_CTRL_PMU; /* 0x100 */ 225 __IO uint32_t CRU_GENERAL; /* 0x104 */ 226 __IO uint32_t CRU_DEBUG; /* 0x108 */ 227 __IO uint32_t reversed7[1]; 228 __IO uint32_t C01_CLK_DIV; /* 0x110 */ 229 __IO uint32_t C09_CLK_DIV; /* 0x114 */ 230 __IO uint32_t C31_CLK_DIV; /* 0x118 */ 231 __IO uint32_t C09_CLK_GATE; /* 0x11C */ 232 __IO uint32_t C30_31_CLK_GATE; /* 0x120 */ 233 __IO uint32_t CLK_DIVIDER_CLK_GATING; /* 0x124 */ 234 __IO uint32_t reserved8[2]; 235 __IO uint32_t CLK_SWITCH_FOR_B; 236 __IO uint32_t CLK_SWITCH_FOR_C; 237 __IO uint32_t CLK_SWITCH_FOR_D; 238 __IO uint32_t CLK_SWITCH_FOR_H; 239 __IO uint32_t CLK_SWITCH_FOR_J; 240 __IO uint32_t CLK_SWITCH_FOR_G; 241 } CRU_TypeDef; 242 243 typedef struct 244 { 245 __IO uint32_t MISC_POR_0; /* 0x000 */ 246 __IO uint32_t MISC_POR_1; /* 0x004 */ 247 __IO uint32_t MISC_POR_2; /* 0x008 */ 248 __IO uint32_t MISC_POR_3; /* 0x00C */ 249 __IO uint32_t RST_CTRL_0; /* 0x010 */ 250 __IO uint32_t RST_CTRL_1; /* 0x014 */ 251 __IO uint32_t CHIP_STA_0; /* 0x018 */ 252 __IO uint32_t CHIP_STA_1; /* 0x01C */ 253 __IO uint32_t WIC_CTRL; /* 0x020 */ 254 __IO uint32_t WIC_STATUS; /* 0x024 */ 255 __IO uint32_t reserved[2]; 256 __IO uint32_t PWR_DWN_SCH; /* 0x030 */ 257 __IO uint32_t reserved1[3]; 258 __IO uint32_t PWR_OFF_OSC; /* 0x040 */ 259 __IO uint32_t EXT_WAKING_UP_SRC; /* 0x044 */ 260 __IO uint32_t reserved2[10]; 261 __IO uint32_t SDMA_STATUS; /* 0x070 */ 262 __IO uint32_t SDMA_POWER_MODE_CFG; /* 0x074 */ 263 __IO uint32_t SDMA_PD_SRC_MASK_N; /* 0x078 */ 264 __IO uint32_t SDMA_WU_SRC_MASK_N; /* 0x07C */ 265 __IO uint32_t M4_STATUS; /* 0x080 */ 266 __IO uint32_t M4_PWR_MODE_CFG; /* 0x084 */ 267 __IO uint32_t M4_PD_SRC_MASK_N; /* 0x088 */ 268 __IO uint32_t M4_WU_SRC_MASK_N; /* 0x08C */ 269 __IO uint32_t FFE_STATUS; /* 0x090 */ 270 __IO uint32_t FFE_PWR_MODE_CFG; /* 0x094 */ 271 __IO uint32_t FFE_PD_SRC_MASK_N; /* 0x098 */ 272 __IO uint32_t FFE_WU_SRC_MASK_N; /* 0x09C */ 273 __IO uint32_t FB_STATUS; /* 0x0A0 */ 274 __IO uint32_t FB_PWR_MODE_CFG; /* 0x0A4 */ 275 __IO uint32_t FB_PD_SRC_MASK_N; /* 0x0A8 */ 276 __IO uint32_t FB_WU_SRC_MASK_N; /* 0x0AC */ 277 __IO uint32_t PF_STATUS; /* 0x0B0 */ 278 __IO uint32_t PF_PWR_MODE_CFG; /* 0x0B4 */ 279 __IO uint32_t PF_PD_SRC_MASK_N; /* 0x0B8 */ 280 __IO uint32_t PF_WU_SRC_MASK_N; /* 0x0BC */ 281 __IO uint32_t M4S0_SRAM_STATUS; /* 0x0C0 */ 282 __IO uint32_t M4S0_PWR_MODE_CFG; /* 0x0C4 */ 283 __IO uint32_t M4S0_PD_SRC_MASK_N; /* 0x0C8 */ 284 __IO uint32_t M4S0_WU_SRC_MASK_N; /* 0x0CC */ 285 __IO uint32_t A1_STATUS; /* 0x0D0 */ 286 __IO uint32_t A1_PWR_MODE_CFG; /* 0x0D4 */ 287 __IO uint32_t A1_PD_SRC_MASK_N; /* 0x0D8 */ 288 __IO uint32_t A1_WU_SRC_MASK_N; /* 0x0DC */ 289 __IO uint32_t MISC_STATUS; /* 0x0E0 */ 290 __IO uint32_t AUDIO_STATUS; /* 0x0E4 */ 291 __IO uint32_t M4_SRAM_STATUS; /* 0x0E8 */ 292 __IO uint32_t AUDIO_WU_SRC_MASK_N; /* 0x0EC */ 293 __IO uint32_t reserved3[4]; 294 __IO uint32_t M4_MEM_CTRL_0; /* 0x100 */ 295 __IO uint32_t M4_MEM_CTRL_1; /* 0x104 */ 296 __IO uint32_t PF_MEM_CTRL_0; /* 0x108 */ 297 __IO uint32_t PF_MEM_CTRL_1; /* 0x10C */ 298 __IO uint32_t FFE_MEM_CTRL_0; /* 0x110 */ 299 __IO uint32_t FFE_MEM_CTRL_1; /* 0x114 */ 300 __IO uint32_t AUDIO_MEM_CTRL_0; /* 0x118 */ 301 __IO uint32_t AUDIO_MEM_CTRL_1; /* 0x11C */ 302 __IO uint32_t M4_MEM_CFG; /* 0x120 */ 303 __IO uint32_t PF_MEM_CFG; /* 0x124 */ 304 __IO uint32_t FFE_MEM_CFG; /* 0x128 */ 305 __IO uint32_t AUDIO_MEM_CFG; /* 0x12C */ 306 __IO uint32_t M4_MEM_CTRL_PWR_0; /* 0x130 */ 307 __IO uint32_t M4_MEM_CTRL_PWR_1; /* 0x134 */ 308 __IO uint32_t M4_MEM_CTRL_PWR_2; /* 0x138 */ 309 __IO uint32_t reserved4[1]; 310 __IO uint32_t SDMA_MEM_CTRL_0; /* 0x140 */ 311 __IO uint32_t SDMA_MEM_CTRL_1; /* 0x144 */ 312 __IO uint32_t reserved5[14]; 313 __IO uint32_t MEM_PWR_DOWN_CTRL; /* 0x180 */ 314 __IO uint32_t PMU_TIMER_CFG_0; /* 0x184 */ 315 __IO uint32_t PMU_TIMER_CFG_1; /* 0x188 */ 316 __IO uint32_t PDWU_TIMER_CFG; /* 0x18C */ 317 __IO uint32_t reserved6[28]; 318 __IO uint32_t FFE_FB_PF_SW_PD; /* 0x200 */ 319 __IO uint32_t M4_SRAM_SW_PD; /* 0x204 */ 320 __IO uint32_t MISC_SW_PD; /* 0x208 */ 321 __IO uint32_t AUDIO_SW_PD; /* 0x20C */ 322 __IO uint32_t FFE_FB_PF_SW_WU; /* 0x210 */ 323 __IO uint32_t M4_SRAM_SW_WU; /* 0x214 */ 324 __IO uint32_t MISC_SW_WU; /* 0x218 */ 325 __IO uint32_t AUD_SRAM_SW_WU; /* 0x21C */ 326 __IO uint32_t PMU_STM_PRIORITY; /* 0x220 */ 327 __IO uint32_t reserved7[3]; 328 __IO uint32_t M4SRAM_SSW_LPMF; /* 0x230 */ 329 __IO uint32_t M4SRAM_SSW_LPMH_MASK_N; /* 0x234 */ 330 __IO uint32_t reserved8[106]; 331 __IO uint32_t EFUSE_BITS; /* 0x3E0 */ 332 __IO uint32_t reserved9[1]; 333 __IO uint32_t FBVLPMinWidth; /* 0x3E8 */ 334 __IO uint32_t APRebootStatus; /* 0x3EC */ 335 __IO uint32_t GEN_PURPOSE_0; /* 0x3F0 */ 336 __IO uint32_t FB_ISOLATION; /* 0x3F4 */ 337 __IO uint32_t GEN_PURPOSE_1; /* 0x3F8 */ 338 339 } PMU_TypeDef; 340 341 typedef struct 342 { 343 __IO uint32_t ADDR; /* 0x000 */ 344 __IO uint32_t WDATA; /* 0x004 */ 345 __IO uint32_t CSR; /* 0x008 */ 346 __IO uint32_t RDATA; /* 0x00C */ 347 __IO uint32_t reserved0[1]; /* 0x010 */ 348 __IO uint32_t SRAM_TEST_REG1; /* 0x014 */ 349 __IO uint32_t SRAM_TEST_REG2; /* 0x018 */ 350 __IO uint32_t reserved1[1]; /* 0x01C */ 351 __IO uint32_t FFE_CSR; /* 0x020 */ 352 __IO uint32_t reserved2[5]; /* 0x024 */ 353 __IO uint32_t FFE_DBG_COMBINED; /* 0x038 */ 354 __IO uint32_t reserved3[49]; /* 0x03C */ 355 __IO uint32_t CMD; /* 0x100 */ 356 __IO uint32_t reserved4[1]; /* 0x104 */ 357 __IO uint32_t INTERRUPT; /* 0x108 */ 358 __IO uint32_t INTERRUPT_EN; /* 0x10C */ 359 __IO uint32_t STATUS; /* 0x110 */ 360 __IO uint32_t MAILBOX_TO_FFE0; /* 0x114 */ 361 __IO uint32_t reserved5[2]; /* 0x118 */ 362 __IO uint32_t SM_RUNTIME_ADDR; /* 0x120 */ 363 __IO uint32_t SM0_RUNTIME_ADDR_CTRL; /* 0x124 */ 364 __IO uint32_t SM1_RUNTIME_ADDR_CTRL; /* 0x128 */ 365 __IO uint32_t SM0_RUNTIME_ADDR_CUR; /* 0x12C */ 366 __IO uint32_t SM1_RUNTIME_ADDR_CUR; /* 0x130 */ 367 __IO uint32_t reserved6[3]; /* 0x134 */ 368 __IO uint32_t SM0_DEBUG_SEL; /* 0x140 */ 369 __IO uint32_t SM1_DEBUG_SEL; /* 0x144 */ 370 __IO uint32_t FFE_DEBUG_SEL; /* 0x148 */ 371 __IO uint32_t reserved7[1]; /* 0x14C */ 372 __IO uint32_t FFE0_BREAK_POINT_CFG; /* 0x150 */ 373 __IO uint32_t FFE0_BREAK_POINT_CONT; /* 0x154 */ 374 __IO uint32_t FFE0_BREAK_POINT_STAT; /* 0x158 */ 375 __IO uint32_t reserved8[1]; /* 0x15C */ 376 __IO uint32_t FFE0_BP_XPC_0; /* 0x160 */ 377 __IO uint32_t FFE0_BP_XPC_1; /* 0x164 */ 378 __IO uint32_t FFE0_BP_XPC_2; /* 0x168 */ 379 __IO uint32_t FFE0_BP_XPC_3; /* 0x16C */ 380 } EXT_REGS_FFE_TypeDef; 381 382 typedef struct 383 { 384 __IO uint32_t DBG_MON; /* 0x000 */ 385 __IO uint32_t SUBSYS_DBG_MON_SEL; /* 0x004 */ 386 __IO uint32_t A0_DBG_MON_SEL; /* 0x008 */ 387 __IO uint32_t A0_PMU_DBG_MON_SEL; /* 0x00C */ 388 __IO uint32_t reserved1[60]; /* 0x010 */ 389 __IO uint32_t IO_INPUT; /* 0x100 */ 390 __IO uint32_t IO_OUTPUT; /* 0x104 */ 391 __IO uint32_t reserved2[2]; /* 0x108 */ 392 __IO uint32_t SW_MB_1; /* 0x110 */ 393 __IO uint32_t SW_MB_2; /* 0x114 */ 394 __IO uint32_t reserved3[58]; /* 0x118 */ 395 __IO uint32_t PAD_SEL18; /* 0x200 */ 396 __IO uint32_t reserved4[3]; /* 0x204 */ 397 __IO uint32_t CONFIG_MEM128_AON; /* 0x210 */ 398 __IO uint32_t reserved5[63]; /* 0x214 */ 399 __IO uint32_t LOCK_KEY_CTRL; /* 0x310 */ 400 __IO uint32_t reserved6[58]; /* 0x314 */ 401 __IO uint32_t FB_DEVICE_ID; /* 0x3FC */ 402 } MISC_CTRL_BASE_TypeDef; 403 404 /* 405 * IO MUX 406 */ 407 typedef struct 408 { 409 __IO uint32_t PAD_0_CTRL; /* PAD 0 Control 0x000 */ 410 __IO uint32_t PAD_1_CTRL; /* PAD 1 Control 0x004 */ 411 __IO uint32_t PAD_2_CTRL; /* PAD 2 Control 0x008 */ 412 __IO uint32_t PAD_3_CTRL; /* PAD 3 Control 0x00C */ 413 __IO uint32_t PAD_4_CTRL; /* PAD 4 Control 0x010 */ 414 __IO uint32_t PAD_5_CTRL; /* PAD 5 Control 0x014 */ 415 __IO uint32_t PAD_6_CTRL; /* PAD 6 Control 0x018 */ 416 __IO uint32_t PAD_7_CTRL; /* PAD 7 Control 0x01C */ 417 __IO uint32_t PAD_8_CTRL; /* PAD 8 Control 0x020 */ 418 __IO uint32_t PAD_9_CTRL; /* PAD 9 Control 0x024 */ 419 __IO uint32_t PAD_10_CTRL; /* PAD 10 Control 0x028 */ 420 __IO uint32_t PAD_11_CTRL; /* PAD 11 Control 0x02C */ 421 __IO uint32_t PAD_12_CTRL; /* PAD 12 Control 0x030 */ 422 __IO uint32_t PAD_13_CTRL; /* PAD 13 Control 0x034 */ 423 __IO uint32_t PAD_14_CTRL; /* PAD 14 Control 0x038 */ 424 __IO uint32_t PAD_15_CTRL; /* PAD 15 Control 0x03C */ 425 __IO uint32_t PAD_16_CTRL; /* PAD 16 Control 0x040 */ 426 __IO uint32_t PAD_17_CTRL; /* PAD 17 Control 0x044 */ 427 __IO uint32_t PAD_18_CTRL; /* PAD 18 Control 0x048 */ 428 __IO uint32_t PAD_19_CTRL; /* PAD 19 Control 0x04C */ 429 __IO uint32_t PAD_20_CTRL; /* PAD 20 Control 0x050 */ 430 __IO uint32_t PAD_21_CTRL; /* PAD 21 Control 0x054 */ 431 __IO uint32_t PAD_22_CTRL; /* PAD 22 Control 0x058 */ 432 __IO uint32_t PAD_23_CTRL; /* PAD 23 Control 0x05C */ 433 __IO uint32_t PAD_24_CTRL; /* PAD 24 Control 0x060 */ 434 __IO uint32_t PAD_25_CTRL; /* PAD 25 Control 0x064 */ 435 __IO uint32_t PAD_26_CTRL; /* PAD 26 Control 0x068 */ 436 __IO uint32_t PAD_27_CTRL; /* PAD 27 Control 0x06C */ 437 __IO uint32_t PAD_28_CTRL; /* PAD 28 Control 0x070 */ 438 __IO uint32_t PAD_29_CTRL; /* PAD 29 Control 0x074 */ 439 __IO uint32_t PAD_30_CTRL; /* PAD 30 Control 0x078 */ 440 __IO uint32_t PAD_31_CTRL; /* PAD 31 Control 0x07C */ 441 __IO uint32_t PAD_32_CTRL; /* PAD 32 Control 0x080 */ 442 __IO uint32_t PAD_33_CTRL; /* PAD 33 Control 0x084 */ 443 __IO uint32_t PAD_34_CTRL; /* PAD 34 Control 0x088 */ 444 __IO uint32_t PAD_35_CTRL; /* PAD 35 Control 0x08C */ 445 __IO uint32_t PAD_36_CTRL; /* PAD 36 Control 0x090 */ 446 __IO uint32_t PAD_37_CTRL; /* PAD 37 Control 0x094 */ 447 __IO uint32_t PAD_38_CTRL; /* PAD 38 Control 0x098 */ 448 __IO uint32_t PAD_39_CTRL; /* PAD 39 Control 0x09C */ 449 __IO uint32_t PAD_40_CTRL; /* PAD 40 Control 0x0A0 */ 450 __IO uint32_t PAD_41_CTRL; /* PAD 41 Control 0x0A4 */ 451 __IO uint32_t PAD_42_CTRL; /* PAD 42 Control 0x0A8 */ 452 __IO uint32_t PAD_43_CTRL; /* PAD 43 Control 0x0AC */ 453 __IO uint32_t PAD_44_CTRL; /* PAD 44 Control 0x0B0 */ 454 __IO uint32_t PAD_45_CTRL; /* PAD 45 Control 0x0B4 */ 455 __IO uint32_t reserved1[18]; 456 __IO uint32_t SDA0_SEL_REG; /* Address offset: 0x100 */ 457 __IO uint32_t SDA1_SEL_REG; /* Address offset: 0x104 */ 458 __IO uint32_t SDA2_SEL_REG; /* Address offset: 0x108 */ 459 __IO uint32_t SCL0_SEL_REG; /* Address offset: 0x10C */ 460 __IO uint32_t SCL1_SEL_REG; /* Address offset: 0x110 */ 461 __IO uint32_t SCL2_SEL_REG; /* Address offset: 0x114 */ 462 __IO uint32_t SPIs_CLK_SEL; /* Address offset: 0x118 */ 463 __IO uint32_t SPIs_SSn_SEL; /* Address offset: 0x11C */ 464 __IO uint32_t SPIs_MOSI_SEL; /* Address offset: 0x120 */ 465 __IO uint32_t SPIm_MISO_SEL; /* Address offset: 0x124 */ 466 __IO uint32_t PDM_DATA_SELE; /* Address offset: 0x128 */ 467 __IO uint32_t I2S_DATA_SELECT; /* Address offset: 0x12C */ 468 __IO uint32_t reserved2[1]; 469 __IO uint32_t UART_rxd_SEL; /* Address offset: 0x134 */ 470 __IO uint32_t IrDA_Sirin_SEL; /* Address offset: 0x138 */ 471 __IO uint32_t S_INTR_0_SEL_REG; /* Address offset: 0x13C */ 472 __IO uint32_t S_INTR_1_SEL_REG; /* Address offset: 0x140 */ 473 __IO uint32_t S_INTR_2_SEL_REG; /* Address offset: 0x144 */ 474 __IO uint32_t S_INTR_3_SEL_REG; /* Address offset: 0x148 */ 475 __IO uint32_t S_INTR_4_SEL_REG; /* Address offset: 0x14C */ 476 __IO uint32_t S_INTR_5_SEL_REG; /* Address offset: 0x150 */ 477 __IO uint32_t S_INTR_6_SEL_REG; /* Address offset: 0x154 */ 478 __IO uint32_t S_INTR_7_SEL_REG; /* Address offset: 0x158 */ 479 __IO uint32_t NUARTCTS_SEL; /* Address offset: 0x15C */ 480 __IO uint32_t IO_REG_SEL_REG; /* Address offset: 0x160 */ 481 __IO uint32_t reserved3[3]; 482 __IO uint32_t SW_CLK_SEL; /* Address offset: 0x170 */ 483 __IO uint32_t SW_IO_SEL; /* Address offset: 0x174 */ 484 __IO uint32_t reserved4[2]; 485 __IO uint32_t FBIO_SEL_1_REG; /* Address offset: 0x180 */ 486 __IO uint32_t FBIO_SEL_2_REG; /* Address offset: 0x184 */ 487 __IO uint32_t reserved5[2]; 488 __IO uint32_t SPI_SENSOR_MISO_SEL; /* Address offset: 0x190 */ 489 __IO uint32_t SPI_SENSOR_MOSI_SEL; /* Address offset: 0x194 */ 490 __IO uint32_t reserved6[2]; 491 __IO uint32_t I2S_WD_CLKIN_SEL; /* Address offset: 0x1A0 */ 492 __IO uint32_t I2S_CLKIN_SEL; /* Address offset: 0x1A4 */ 493 __IO uint32_t PDM_STAT_IN_SEL; /* Address offset: 0x1A8 */ 494 __IO uint32_t PDM_CLKIN_SEL; /* Address offset: 0x1AC */ 495 } IO_MUX_TypeDef; 496 497 typedef struct 498 { 499 __IO uint32_t SPT_CFG; 500 __IO uint32_t SLEEP_MODE; 501 __IO uint32_t ERR_CMP_40M; 502 __IO uint32_t ERR_CMP_1S_0; 503 __IO uint32_t ERR_CMP_1S_1; 504 __IO uint32_t ERR_CMP_1S_2; 505 __IO uint32_t ERR_CMP_1S_3; 506 __IO uint32_t ERR_CMP_RTC_0; 507 __IO uint32_t ERR_CMP_RTC_1; 508 __IO uint32_t ERR_CMP_RTC_2; 509 __IO uint32_t ERR_CMP_RTC_3; 510 __IO uint32_t UPDATE_TMR_VAL; 511 __IO uint32_t SPARE_BITS; 512 __IO uint32_t TIMER_VAL; 513 __IO uint32_t EVENT_CNT_VAL; 514 __IO uint32_t MS_CNT_VAL; 515 516 }SPT_REGS_TypeDef; 517 518 typedef struct 519 { 520 __IO uint32_t GPIO_INTR; /* Address offset: 0x00 */ 521 __IO uint32_t GPIO_INTR_RAW; /* Address offset: 0x04 */ 522 __IO uint32_t GPIO_INTR_TYPE; /* Address offset: 0x08 */ 523 __IO uint32_t GPIO_INTR_POL; /* Address offset: 0x0C */ 524 __IO uint32_t GPIO_INTR_EN_AP; /* Address offset: 0x10 */ 525 __IO uint32_t GPIO_INTR_EN_M4; /* Address offset: 0x14 */ 526 __IO uint32_t GPIO_INTR_EN_FFE0; /* Address offset: 0x18 */ 527 __IO uint32_t GPIO_INTR_EN_FFE1; /* Address offset: 0x1C */ 528 __IO uint32_t reserved1[4]; 529 __IO uint32_t OTHER_INTR; /* Address offset: 0x30 */ 530 __IO uint32_t OTHER_INTR_EN_AP; /* Address offset: 0x34 */ 531 __IO uint32_t OTHER_INTR_EN_M4; /* Address offset: 0x38 */ 532 __IO uint32_t reserved2[1]; 533 __IO uint32_t SOFTWARE_INTR_1; /* Address offset: 0x40 */ 534 __IO uint32_t SOFTWARE_INTR_1_EN_AP; /* Address offset: 0x44 */ 535 __IO uint32_t SOFTWARE_INTR_1_EN_M4; /* Address offset: 0x48 */ 536 __IO uint32_t reserved3[1]; 537 __IO uint32_t SOFTWARE_INTR_2; /* Address offset: 0x50 */ 538 __IO uint32_t SOFTWARE_INTR_2_EN_AP; /* Address offset: 0x54 */ 539 __IO uint32_t SOFTWARE_INTR_2_EN_M4; /* Address offset: 0x58 */ 540 __IO uint32_t reserved4[1]; 541 __IO uint32_t FFE_INTR; /* Address offset: 0x60 */ 542 __IO uint32_t FFE_INTR_EN_AP; /* Address offset: 0x64 */ 543 __IO uint32_t FFE_INTR_EN_M4; /* Address offset: 0x68 */ 544 __IO uint32_t reserved5[1]; 545 __IO uint32_t FFE1_FB_INTR; /* Address offset: 0x70 */ 546 __IO uint32_t FFE1_FB_INTR_EN_AP; /* Address offset: 0x74 */ 547 __IO uint32_t FFE1_FB_INTR_EN_M4; /* Address offset: 0x78 */ 548 __IO uint32_t reserved6[1]; 549 __IO uint32_t FB_INTR; /* Address offset: 0x80 */ 550 __IO uint32_t FB_INTR_RAW; /* Address offset: 0x84 */ 551 __IO uint32_t FB_INTR_TYPE; /* Address offset: 0x88 */ 552 __IO uint32_t FB_INTR_POL; /* Address offset: 0x8C */ 553 __IO uint32_t FB_INTR_EN_AP; /* Address offset: 0x90 */ 554 __IO uint32_t FB_INTR_EN_M4; /* Address offset: 0x94 */ 555 __IO uint32_t reserved7[2]; 556 __IO uint32_t M4_MEM_AON_INTR; /* Address offset: 0xA0 */ 557 __IO uint32_t M4_MEM_AON_INTR_EN; /* Address offset: 0xA4 */ 558 } INTR_CTRL_TypeDef; 559 560 typedef struct 561 { 562 __IO uint32_t CTRLR0; /* Control Register #0, Address offset: 0x00 */ 563 __IO uint32_t CTRLR1; /* Control Register #1, Address offset: 0x04 */ 564 __IO uint32_t SSIENR; /* SSI Enable Register, Address offset: 0x08 */ 565 __IO uint32_t reserved1; 566 __IO uint32_t SER; /* Slave Enable Register, Address offset: 0x10 */ 567 __IO uint32_t BAUDR; /* Baud Rate Register, Address offset: 0x14 */ 568 __IO uint32_t TXFTLR; /* Tx FIFO Threshold Register, Address offset: 0x18 */ 569 __IO uint32_t RXFTLR; /* Rx FIFO Threshold Register, Address offset: 0x1C */ 570 __IO uint32_t TXFLR; /* Tx FIFO Level Register, Address offset: 0x20 */ 571 __IO uint32_t RXFLR; /* Rx FIFO Level Register, Address offset: 0x24 */ 572 __IO uint32_t SR; /* Status Register, Address offset: 0x28 */ 573 __IO uint32_t IMR; /* Interrupt Mask Register, Address offset: 0x2C */ 574 __IO uint32_t ISR; /* Interrupt Status Register, Address offset: 0x30 */ 575 __IO uint32_t RISR; /* Interrupt Raw Status Register, Address offset: 0x34 */ 576 __IO uint32_t TXOICR; /* Tx FIFO Overflow Interrupt Clear Register, Address offset: 0x38 */ 577 __IO uint32_t RXOICR; /* Rx FIFO Overflow Interrupt Clear Register, Address offset: 0x3C */ 578 __IO uint32_t RXUICR; /* Rx FIFO Underflow Interrupt Clear Register, Address offset: 0x40 */ 579 __IO uint32_t MSTICR; /* Multi-Master Contention Interrupt Clear Register, Address offset: 0x44 */ 580 __IO uint32_t ICR; /* Interrupt Clear Register, Address offset: 0x48 */ 581 __IO uint32_t reserved2[3]; 582 __IO uint32_t IDR; 583 __IO uint32_t SSI_COMP_VERSION; 584 __IO uint32_t DR0; /* Data Register, Address offset: 0x60 */ 585 } SPI_TypeDef; 586 587 588 typedef struct 589 { 590 __IO uint32_t IER; /* I2S Enable Register 0x00 */ 591 __IO uint32_t reserved1[1]; 592 __IO uint32_t ITER; /* Tx block enable 0x008 */ 593 __IO uint32_t reserved2[3]; 594 __IO uint32_t TXFFR; /* Tx block fifo reset reg 0x018 */ 595 __IO uint32_t reserved3[1]; 596 __IO uint32_t LTHR0; /* Left tx holding reg 0x020 */ 597 __IO uint32_t RTHR0; /* Right tx holding reg 0x020 */ 598 __IO uint32_t reserved4[1]; 599 __IO uint32_t TER0; /* Tx enable reg 0x02C */ 600 __IO uint32_t reserved5[1]; 601 __IO uint32_t TCR0; /* Tx config reg 0x034 */ 602 __IO uint32_t ISR0; /* Intr status reg 0x038 */ 603 __IO uint32_t IMR0; /* Intr mask reg 0x03C */ 604 __IO uint32_t reserved6[1]; 605 __IO uint32_t TOR0; /* Tx overrun reg 0x044 */ 606 __IO uint32_t reserved7[1]; 607 __IO uint32_t TFCR0; /* Tx fifo config reg 0x04C */ 608 __IO uint32_t reserved8[1]; 609 __IO uint32_t TFF0; /* Tx fifo flush reg 0x054 */ 610 __IO uint32_t reserved9[92]; 611 __IO uint32_t TXDMA; /* Tx block dma reg 0x1C8 */ 612 __IO uint32_t RTXDMA; /* Reset Tx block dma reg 0x1CC */ 613 __IO uint32_t reserved10[9]; 614 __IO uint32_t I2S_COMP_PARAM_1; /* Component parm reg 0x1F4 */ 615 __IO uint32_t I2S_COMP_VERSION; /* Component version reg 0x1F8 */ 616 __IO uint32_t I2S_COMP_TYPE; /* Component type reg 0x1FC */ 617 __IO uint32_t resereved11[126]; 618 __IO uint32_t I2S_STEREO_EN; /* Stereo enable reg 0x3F8 */ 619 } I2S_TypeDef; 620 621 // Naveen - Aud Block definition according to tamar2 register spec available @ ${SVN_URL}/svn/Platform/Tamar2/Design/ASSP/doc/tamar2_regs.xlsx 622 typedef struct { 623 __IO uint32_t VOICE_CONFIG; // 0x000 624 __IO uint32_t LPSD_CONFIG; // 0x004 625 __IO uint32_t VOICE_DMAC_CONFIG; // 0x008 626 __IO uint32_t VOICE_DMAC_LEN; // 0x00C 627 __IO uint32_t VOICE_DMAC_FIFO; // 0x010 628 __IO uint32_t VOICE_DMAC_DST_ADDR0; // 0x014 629 __IO uint32_t VOICE_DMAC_DST_ADDR1; // 0x018 630 __IO uint32_t PDM_CORE_CONFIG; // 0x01C 631 __IO uint32_t VOICE_STATUS; // 0x020 632 __IO uint32_t I2S_CONFIG; // 0x024 633 634 } AUD_TypeDef; 635 636 637 typedef struct 638 { 639 __IO uint32_t DMA_CTRL; /* DMA Control Register 0x00 */ 640 __IO uint32_t DMA_DEST_ADDR; /* DMA Destination Address 0x04 */ 641 __IO uint32_t DMA_XFER_CNT; /* DMA Transfer Count 0x08 */ 642 __IO uint32_t CFG_FLASH_HEADER; /* CFG FLASH Header 0x0C */ 643 __IO uint32_t DMA_INTR; /* DMA Interrupt Register 0x10 */ 644 __IO uint32_t DMA_INTR_MASK; /* DMA Interrupt Mask Register 0x14 */ 645 } DMA_SPI_MS_TypeDef; 646 647 648 /* 649 * System DMA 650 */ 651 typedef struct 652 { 653 __IO uint32_t SRC_DATA_END_PTR_CH0; /* Ptr to the end address of the source of Ch0 Address offset: 0x00 */ 654 __IO uint32_t DST_DATA_END_PTR_CH0; /* Ptr to the end address of the dest of Ch0 Address offset: 0x04 */ 655 __IO uint32_t CH_CFG_CH0; /* Configuration of Ch0 Address offset: 0x08 */ 656 __IO uint32_t reserved0[1]; 657 __IO uint32_t SRC_DATA_END_PTR_CH1; /* Ptr to the end address of the source of Ch1 Address offset: 0x10 */ 658 __IO uint32_t DST_DATA_END_PTR_CH1; /* Ptr to the end address of the dest of Ch1 Address offset: 0x14 */ 659 __IO uint32_t CH_CFG_CH1; /* Configuration of Ch1 Address offset: 0x18 */ 660 __IO uint32_t reserved1[1]; 661 __IO uint32_t SRC_DATA_END_PTR_CH2; /* Ptr to the end address of the source of Ch2 Address offset: 0x20 */ 662 __IO uint32_t DST_DATA_END_PTR_CH2; /* Ptr to the end address of the dest of Ch2 Address offset: 0x24 */ 663 __IO uint32_t CH_CFG_CH2; /* Configuration of Ch2 Address offset: 0x28 */ 664 __IO uint32_t reserved2[1]; 665 __IO uint32_t SRC_DATA_END_PTR_CH3; /* Ptr to the end address of the source of Ch3 Address offset: 0x30 */ 666 __IO uint32_t DST_DATA_END_PTR_CH3; /* Ptr to the end address of the dest of Ch3 Address offset: 0x34 */ 667 __IO uint32_t CH_CFG_CH3; /* Configuration of Ch3 Address offset: 0x38 */ 668 __IO uint32_t reserved3[1]; 669 __IO uint32_t SRC_DATA_END_PTR_CH4; /* Ptr to the end address of the source of Ch4 Address offset: 0x40 */ 670 __IO uint32_t DST_DATA_END_PTR_CH4; /* Ptr to the end address of the dest of Ch4 Address offset: 0x44 */ 671 __IO uint32_t CH_CFG_CH4; /* Configuration of Ch4 Address offset: 0x48 */ 672 __IO uint32_t reserved4[1]; 673 __IO uint32_t SRC_DATA_END_PTR_CH5; /* Ptr to the end address of the source of Ch5 Address offset: 0x50 */ 674 __IO uint32_t DST_DATA_END_PTR_CH5; /* Ptr to the end address of the dest of Ch5 Address offset: 0x54 */ 675 __IO uint32_t CH_CFG_CH5; /* Configuration of Ch5 Address offset: 0x58 */ 676 __IO uint32_t reserved5[1]; 677 __IO uint32_t SRC_DATA_END_PTR_CH6; /* Ptr to the end address of the source of Ch6 Address offset: 0x60 */ 678 __IO uint32_t DST_DATA_END_PTR_CH6; /* Ptr to the end address of the dest of Ch6 Address offset: 0x64 */ 679 __IO uint32_t CH_CFG_CH6; /* Configuration of Ch6 Address offset: 0x68 */ 680 __IO uint32_t reserved6[1]; 681 __IO uint32_t SRC_DATA_END_PTR_CH7; /* Ptr to the end address of the source of Ch7 Address offset: 0x70 */ 682 __IO uint32_t DST_DATA_END_PTR_CH7; /* Ptr to the end address of the dest of Ch7 Address offset: 0x74 */ 683 __IO uint32_t CH_CFG_CH7; /* Configuration of Ch7 Address offset: 0x78 */ 684 __IO uint32_t reserved7[1]; 685 __IO uint32_t SRC_DATA_END_PTR_CH8; /* Ptr to the end address of the source of Ch8 Address offset: 0x80 */ 686 __IO uint32_t DST_DATA_END_PTR_CH8; /* Ptr to the end address of the dest of Ch8 Address offset: 0x84 */ 687 __IO uint32_t CH_CFG_CH8; /* Configuration of Ch8 Address offset: 0x88 */ 688 __IO uint32_t reserved8[1]; 689 __IO uint32_t SRC_DATA_END_PTR_CH9; /* Ptr to the end address of the source of Ch9 Address offset: 0x90 */ 690 __IO uint32_t DST_DATA_END_PTR_CH9; /* Ptr to the end address of the dest of Ch9 Address offset: 0x94 */ 691 __IO uint32_t CH_CFG_CH9; /* Configuration of Ch9 Address offset: 0x98 */ 692 __IO uint32_t reserved9[1]; 693 __IO uint32_t SRC_DATA_END_PTR_CH10; /* Ptr to the end address of the source of Ch10 Address offset: 0xA0 */ 694 __IO uint32_t DST_DATA_END_PTR_CH10; /* Ptr to the end address of the dest of Ch10 Address offset: 0xA4 */ 695 __IO uint32_t CH_CFG_CH10; /* Configuration of Ch10 Address offset: 0xA8 */ 696 __IO uint32_t reserved10[1]; 697 __IO uint32_t SRC_DATA_END_PTR_CH11; /* Ptr to the end address of the source of Ch11 Address offset: 0xB0 */ 698 __IO uint32_t DST_DATA_END_PTR_CH11; /* Ptr to the end address of the dest of Ch11 Address offset: 0xB4 */ 699 __IO uint32_t CH_CFG_CH11; /* Configuration of Ch11 Address offset: 0xB8 */ 700 __IO uint32_t reserved11[1]; 701 __IO uint32_t SRC_DATA_END_PTR_CH12; /* Ptr to the end address of the source of Ch12 Address offset: 0xC0 */ 702 __IO uint32_t DST_DATA_END_PTR_CH12; /* Ptr to the end address of the dest of Ch12 Address offset: 0xC4 */ 703 __IO uint32_t CH_CFG_CH12; /* Configuration of Ch12 Address offset: 0xC8 */ 704 __IO uint32_t reserved12[1]; 705 __IO uint32_t SRC_DATA_END_PTR_CH13; /* Ptr to the end address of the source of Ch13 Address offset: 0xD0 */ 706 __IO uint32_t DST_DATA_END_PTR_CH13; /* Ptr to the end address of the dest of Ch13 Address offset: 0xD4 */ 707 __IO uint32_t CH_CFG_CH13; /* Configuration of Ch13 Address offset: 0xD8 */ 708 __IO uint32_t reserved13[1]; 709 __IO uint32_t SRC_DATA_END_PTR_CH14; /* Ptr to the end address of the source of Ch14 Address offset: 0xE0 */ 710 __IO uint32_t DST_DATA_END_PTR_CH14; /* Ptr to the end address of the dest of Ch14 Address offset: 0xE4 */ 711 __IO uint32_t CH_CFG_CH14; /* Configuration of Ch14 Address offset: 0xE8 */ 712 __IO uint32_t reserved14[1]; 713 __IO uint32_t SRC_DATA_END_PTR_CH15; /* Ptr to the end address of the source of Ch15 Address offset: 0xF0 */ 714 __IO uint32_t DST_DATA_END_PTR_CH15; /* Ptr to the end address of the dest of Ch15 Address offset: 0xF4 */ 715 __IO uint32_t CH_CFG_CH15; /* Configuration of Ch15 Address offset: 0xF8 */ 716 __IO uint32_t reserved15[1]; 717 __IO uint32_t ALT_SRC_DATA_END_PTR_CH0; 718 __IO uint32_t ALT_DST_DATA_END_PTR_CH0; 719 __IO uint32_t ALT_CHN_CFG_CH0; 720 __IO uint32_t resereved16[1]; 721 __IO uint32_t ALT_SRC_DATA_END_PTR_CH1; 722 __IO uint32_t ALT_DST_DATA_END_PTR_CH1; 723 __IO uint32_t ALT_CHN_CFG_CH1; 724 __IO uint32_t resereved17[1]; 725 __IO uint32_t ALT_SRC_DATA_END_PTR_CH2; 726 __IO uint32_t ALT_DST_DATA_END_PTR_CH2; 727 __IO uint32_t ALT_CHN_CFG_CH2; 728 __IO uint32_t resereved18[1]; 729 __IO uint32_t ALT_SRC_DATA_END_PTR_CH3; 730 __IO uint32_t ALT_DST_DATA_END_PTR_CH3; 731 __IO uint32_t ALT_CHN_CFG_CH3; 732 __IO uint32_t resereved19[1]; 733 __IO uint32_t ALT_SRC_DATA_END_PTR_CH4; 734 __IO uint32_t ALT_DST_DATA_END_PTR_CH4; 735 __IO uint32_t ALT_CHN_CFG_CH4; 736 __IO uint32_t resereved20[1]; 737 __IO uint32_t ALT_SRC_DATA_END_PTR_CH5; 738 __IO uint32_t ALT_DST_DATA_END_PTR_CH5; 739 __IO uint32_t ALT_CHN_CFG_CH5; 740 __IO uint32_t resereved21[1]; 741 __IO uint32_t ALT_SRC_DATA_END_PTR_CH6; 742 __IO uint32_t ALT_DST_DATA_END_PTR_CH6; 743 __IO uint32_t ALT_CHN_CFG_CH6; 744 __IO uint32_t resereved22[1]; 745 __IO uint32_t ALT_SRC_DATA_END_PTR_CH7; 746 __IO uint32_t ALT_DST_DATA_END_PTR_CH7; 747 __IO uint32_t ALT_CHN_CFG_CH7; 748 __IO uint32_t resereved23[1]; 749 __IO uint32_t ALT_SRC_DATA_END_PTR_CH8; 750 __IO uint32_t ALT_DST_DATA_END_PTR_CH8; 751 __IO uint32_t ALT_CHN_CFG_CH8; 752 __IO uint32_t resereved24[1]; 753 __IO uint32_t ALT_SRC_DATA_END_PTR_CH9; 754 __IO uint32_t ALT_DST_DATA_END_PTR_CH9; 755 __IO uint32_t ALT_CHN_CFG_CH9; 756 __IO uint32_t resereved25[1]; 757 __IO uint32_t ALT_SRC_DATA_END_PTR_CH10; 758 __IO uint32_t ALT_DST_DATA_END_PTR_CH10; 759 __IO uint32_t ALT_CHN_CFG_CH10; 760 __IO uint32_t resereved26[1]; 761 __IO uint32_t ALT_SRC_DATA_END_PTR_CH11; 762 __IO uint32_t ALT_DST_DATA_END_PTR_CH11; 763 __IO uint32_t ALT_CHN_CFG_CH11; 764 __IO uint32_t resereved27[1]; 765 __IO uint32_t ALT_SRC_DATA_END_PTR_CH12; 766 __IO uint32_t ALT_DST_DATA_END_PTR_CH12; 767 __IO uint32_t ALT_CHN_CFG_CH12; 768 __IO uint32_t resereved28[1]; 769 __IO uint32_t ALT_SRC_DATA_END_PTR_CH13; 770 __IO uint32_t ALT_DST_DATA_END_PTR_CH13; 771 __IO uint32_t ALT_CHN_CFG_CH13; 772 __IO uint32_t resereved29[1]; 773 __IO uint32_t ALT_SRC_DATA_END_PTR_CH14; 774 __IO uint32_t ALT_DST_DATA_END_PTR_CH14; 775 __IO uint32_t ALT_CHN_CFG_CH14; 776 __IO uint32_t resereved30[1]; 777 __IO uint32_t ALT_SRC_DATA_END_PTR_CH15; 778 __IO uint32_t ALT_DST_DATA_END_PTR_CH15; 779 780 }SDMA_SRAM_TypeDef; 781 782 typedef struct 783 { 784 __IO uint32_t SRC_DATA_END_PTR; /* Ptr to the end address of the source */ 785 __IO uint32_t DST_DATA_END_PTR; /* Ptr to the end address of the dest */ 786 __IO uint32_t CH_CFG; /* Configuration of Ch0 */ 787 uint32_t reserved0; 788 }SDMA_SRAM_ENTRY_TypeDef; 789 790 typedef struct 791 { 792 __IO uint32_t DMA_REQ; /* Dma Request Address offset: 0x00 */ 793 __IO uint32_t DMA_WAITONREQ_REG; 794 __IO uint32_t DMA_ACTIVE_REG; 795 __IO uint32_t SDMA_PWRDN_CNT; 796 __IO uint32_t SDMA_SRAM_CTRL; 797 }SDMA_BRIDGE_TypeDef; 798 799 typedef struct 800 { 801 __IO uint32_t DMA_STATUS; /* Dma status Address offset: 0x00 */ 802 __IO uint32_t DMA_CFG; /* Dma configuration Address offset: 0x04 */ 803 __IO uint32_t CTRL_BASE_PTR; /* Control base pointer Address offset: 0x08 */ 804 __IO uint32_t ALT_CTRL_BASE_PTR; /* Alt. Control base pointer Address offset: 0x0C */ 805 __IO uint32_t DMA_WAITONREQ_STATUS; /* Channel wait on req status Address offset: 0x10 */ 806 __IO uint32_t CHNL_SW_REQ; /* Channel switch req Address offset: 0x14 */ 807 __IO uint32_t CHNL_USEBURST_SET; /* Channel burst set Address offset: 0x18 */ 808 __IO uint32_t CHNL_USEBURST_CLR; /* Channel burst clear Address offset: 0x1C */ 809 __IO uint32_t CHNL_REQ_MASK_SET; /* Channel req mask set Address offset: 0x20 */ 810 __IO uint32_t CHNL_REQ_MASK_CLR; /* Channel req mask clear Address offset: 0x24 */ 811 __IO uint32_t CHNL_ENABLE_SET; /* Channel enable set Address offset: 0x28 */ 812 __IO uint32_t CHNL_ENABLE_CLR; /* Channel enable clear Address offset: 0x2C */ 813 __IO uint32_t CHNL_PRI_ALT_SET; /* Channel primary alt set Address offset: 0x30 */ 814 __IO uint32_t CHNL_PRI_ALT_CLR; /* Channel primary alt clear Address offset: 0x34 */ 815 __IO uint32_t CHNL_PRIORITY_SET; /* Channel priority set Address offset: 0x38 */ 816 __IO uint32_t CHNL_PRIORITY_CLR; /* Channel priority clear Address offset: 0x3C */ 817 __IO uint32_t reserved0[3]; 818 __IO uint32_t ERR_CLR; /* Clear error Address offset: 0x4C */ 819 __IO uint32_t reserved1[995]; 820 __IO uint32_t PERIPH_ID_4; /* Peripheral identification 4 Address offset: 0xFD0 */ 821 __IO uint32_t reserved2[3]; 822 __IO uint32_t PERIPH_ID_0; /* Peripheral identification 0 Address offset: 0xFE0 */ 823 __IO uint32_t PERIPH_ID_1; /* Peripheral identification 1 Address offset: 0xFE4 */ 824 __IO uint32_t PERIPH_ID_2; /* Peripheral identification 2 Address offset: 0xFE8 */ 825 __IO uint32_t PERIPH_ID_3; /* Peripheral identification 3 Address offset: 0xFEC */ 826 __IO uint32_t PCELL_ID_0; /* PrimeCell identification 0 Address offset: 0xFF0 */ 827 __IO uint32_t PCELL_ID_1; /* PrimeCell identification 1 Address offset: 0xFF4 */ 828 __IO uint32_t PCELL_ID_2; /* PrimeCell identification 2 Address offset: 0xFF8 */ 829 __IO uint32_t PCELL_ID_3; /* PrimeCell identification 3 Address offset: 0xFFC */ 830 831 } SDMA_TypeDef; 832 833 // i2s slave typedef 834 typedef struct 835 { 836 __IO uint32_t IER; // i2s enable register - offset 0x0 837 __IO uint32_t reserved0; // hole - offset: 0x04 838 __IO uint32_t ITER; // i2s transmitter block enable register - offset:0x8 839 __IO uint32_t reserved1[3]; // holes - offset: 0x0C 840 __IO uint32_t TXFFR; // transmitter block fifo reset register - offset: 0x18 841 __IO uint32_t reserved2; // offset: 0x1c 842 __IO uint32_t LTHR0; // left transmit holding register - offset: 0x20 843 __IO uint32_t RTHR0; // right transmit holding register - offset: 0x24 844 __IO uint32_t reserved3; // hole - offset: 0x28 845 __IO uint32_t TER0; // transmit enable register - offset: 0x2C 846 __IO uint32_t reserved4; // hole - offset: 0x30 847 __IO uint32_t TCR0; // transmit configuration register - offset: 0x34 848 __IO uint32_t ISR0; // interrupt status register - offset: 0x38 849 __IO uint32_t IMR0; // interrupt mask register - offset: 0x3C 850 __IO uint32_t reserved5; // hole - offset: 0x40 851 __IO uint32_t TOR0; // transmit overrun register - offset: 0x44 852 __IO uint32_t reserved6; // hole - offset: 0x48 853 __IO uint32_t TFCR0; // transmit fifo configuration register - offset: 0x4C 854 __IO uint32_t reserved7; // hole - offset 0x50 855 __IO uint32_t TFFO; // transmit fifo flush - offset: 0x54 856 __IO uint32_t reserved8[92]; // holes - offset: 0x58 857 __IO uint32_t TXDMA; // transmit block dma register - offset: 0x1C8 858 __IO uint32_t RTXDMA; // reset transmit block dma register - offset: 0x1CC 859 __IO uint32_t reserved9[9]; // holes - offset: 0x1D0 860 __IO uint32_t I2S_COMP_PARAM_1; // component parameter register 1 - offset: 0x1F4 861 __IO uint32_t I2S_COMP_VERSION; // offset: 0x1F8 862 __IO uint32_t I2S_COMP_TYPE; // offset: 0x1FC 863 __IO uint32_t hole9[126]; // holes - offset 0x200 864 __IO uint32_t I2S_STEREO_EN; // i2s stereo enable register - offset: 0x3F8 865 } I2S_SLAVE_TypeDef; 866 867 /* 868 * External Interrupt/Event Controller 869 */ 870 871 typedef struct 872 { 873 __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */ 874 __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */ 875 __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */ 876 __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */ 877 __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */ 878 __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */ 879 } EXTI_TypeDef; 880 881 typedef struct 882 { 883 __IO uint32_t reserved; /* Address offset: 0x00 */ 884 __IO uint32_t RTC_CTRL_1; /* Address offset: 0x04 */ 885 __IO uint32_t RTC_CTRL_2; /* Address offset: 0x08 */ 886 __IO uint32_t RTC_CTRL_3; /* Address offset: 0x0C */ 887 __IO uint32_t RTC_CTRL_4; /* Address offset: 0x10 */ 888 __IO uint32_t RTC_CTRL_5; /* Address offset: 0x14 */ 889 __IO uint32_t RTC_CTRL_6; /* Address offset: 0x18 */ 890 __IO uint32_t RTC_CTRL_7; /* Address offset: 0x1C */ 891 __IO uint32_t RTC_STA_0; /* Address offset: 0x20 */ 892 __IO uint32_t RTC_STA_1; /* Address offset: 0x24 */ 893 __IO uint32_t reserved1[22]; 894 __IO uint32_t OSC_CTRL_0; /* Address offset: 0x80 */ 895 __IO uint32_t OSC_CTRL_1; /* Address offset: 0x84 */ 896 __IO uint32_t OSC_CTRL_2; /* Address offset: 0x88 */ 897 __IO uint32_t OSC_CTRL_3; /* Address offset: 0x8C */ 898 __IO uint32_t OSC_CTRL_4; /* Address offset: 0x90 */ 899 __IO uint32_t OSC_CTRL_5; /* Address offset: 0x94 */ 900 __IO uint32_t OSC_CTRL_6; /* Address offset: 0x98 */ 901 __IO uint32_t OSC_CTRL_7; /* Address offset: 0x9C */ 902 __IO uint32_t OSC_STA_0; /* Address offset: 0xA0 */ 903 __IO uint32_t OSC_STA_1; /* Address offset: 0xA4 */ 904 __IO uint32_t reserved2[22]; 905 __IO uint32_t APC_CTRL_0; /* Address offset: 0x100 */ 906 __IO uint32_t APC_CTRL_1; /* Address offset: 0x104 */ 907 __IO uint32_t APC_CTRL_2; /* Address offset: 0x108 */ 908 __IO uint32_t APC_CTRL_3; /* Address offset: 0x10C */ 909 __IO uint32_t APC_CTRL_4; /* Address offset: 0x110 */ 910 __IO uint32_t APC_CTRL_5; /* Address offset: 0x114 */ 911 __IO uint32_t APC_CTRL_6; /* Address offset: 0x118 */ 912 __IO uint32_t APC_CTRL_7; /* Address offset: 0x11C */ 913 __IO uint32_t APC_STA_0; /* Address offset: 0x120 */ 914 __IO uint32_t APC_STA_1; /* Address offset: 0x124 */ 915 __IO uint32_t reserved3[22]; 916 __IO uint32_t RING_OSC; /* Address offset: 0x180 */ 917 __IO uint32_t reserved4[31]; 918 __IO uint32_t LD0_30_CTRL_0; 919 __IO uint32_t LD0_30_CTRL_1; 920 __IO uint32_t reserved5[2]; 921 __IO uint32_t LD0_50_CTRL_0; 922 __IO uint32_t LD0_50_CTRL_1; 923 }AIP_Typedef; 924 925 /* 926 * Watchdog timer 927 */ 928 typedef struct 929 { 930 __IO uint32_t WDOGLOAD; /* WDOG Load Register Address offset: 0x00 */ 931 __IO uint32_t WDOGVALUE; /* WDOG Current Value Register Address offset: 0x04 */ 932 __IO uint32_t WDOGCONTROL; /* WDOG Control Register Address offset: 0x08 */ 933 __IO uint32_t WDOGINTCLR; /* WDOG Clear Int Register Address offset: 0x0C */ 934 __IO uint32_t WDOGRIS; /* WDOG Raw Int Status Register Address offset: 0x10 */ 935 __IO uint32_t WDOGMIS; /* WDOG Masked Int Status Register Address offset: 0x14 */ 936 __IO uint32_t reserved1[762]; 937 __IO uint32_t WDOGLOCK; /* WDOG Disable Write Register Address offset: 0xC00 */ 938 __IO uint32_t reserved2[191]; 939 __IO uint32_t WDOGITCR; /* WDOG Enable Integration Test Register Address offset: 0xF00 */ 940 __IO uint32_t WDOGITOP; /* WDOG Integration Test Output Register Address offset: 0xF00 */ 941 uint32_t reserved3[50]; 942 __IO uint32_t WDOGPERIPHID4; /* WDOG Peripheral ID Register 4 Address offset: 0xFD0 */ 943 __IO uint32_t WDOGPERIPHID5; /* WDOG Peripheral ID Register 5 Address offset: 0xFD4 */ 944 __IO uint32_t WDOGPERIPHID6; /* WDOG Peripheral ID Register 6 Address offset: 0xFD8 */ 945 __IO uint32_t WDOGPERIPHID7; /* WDOG Peripheral ID Register 7 Address offset: 0xFDC */ 946 __IO uint32_t WDOGPERIPHID0; /* WDOG Peripheral ID Register 0 Address offset: 0xFE0 */ 947 __IO uint32_t WDOGPERIPHID1; /* WDOG Peripheral ID Register 1 Address offset: 0xFE4 */ 948 __IO uint32_t WDOGPERIPHID2; /* WDOG Peripheral ID Register 2 Address offset: 0xFE8 */ 949 __IO uint32_t WDOGPERIPHID3; /* WDOG Peripheral ID Register 3 Address offset: 0xFEC */ 950 __IO uint32_t WDOGPCELLID0; /* WDOG Component ID Register 0 Address offset: 0xFF0 */ 951 __IO uint32_t WDOGPCELLID1; /* WDOG Component ID Register 1 Address offset: 0xFF4 */ 952 __IO uint32_t WDOGPCELLID2; /* WDOG Component ID Register 2 Address offset: 0xFF8 */ 953 __IO uint32_t WDOGPCELLID3; /* WDOG Component ID Register 3 Address offset: 0xFFC */ 954 } WDT_TypeDef; 955 956 /* 957 * CWM Batching Type Define 958 */ 959 960 typedef struct 961 { 962 __IO uint8_t TAG; /* Data Address: 0x00 */ 963 __IO uint8_t WRITE_POS; 964 __IO uint8_t HDR_RESERVED0[2]; 965 __IO uint8_t READ_POS; 966 __IO uint8_t HDR_RESERVED1[3]; 967 __IO uint8_t HDR_RESERVED2[120]; 968 __IO uint8_t DATA0[128]; /* Data Address: 0x80 */ 969 __IO uint8_t DATA1[128]; /* Data Address: 0x100 */ 970 __IO uint8_t DATA2[128]; /* Data Address: 0x180 */ 971 __IO uint8_t DATA3[128]; /* Data Address: 0x200 */ 972 __IO uint8_t DATA4[128]; /* Data Address: 0x280 */ 973 __IO uint8_t DATA5[128]; /* Data Address: 0x300 */ 974 __IO uint8_t DATA6[128]; /* Data Address: 0x380 */ 975 } BATCHING_TypeDef; 976 977 typedef struct 978 { 979 __IO uint8_t DATA[16]; /* Data Address: 0x00 */ 980 } RECV_DATA_TypeDef; 981 982 983 typedef struct 984 { 985 __IO uint32_t CTRL; 986 __IO uint32_t VALUE; 987 __IO uint32_t RELOAD; 988 __IO uint32_t INTSTATUS_INTCLEAR; 989 __IO uint32_t reserved[1008]; 990 __IO uint32_t PID4; 991 __IO uint32_t PID5; 992 __IO uint32_t PID6; 993 __IO uint32_t PID7; 994 __IO uint32_t PID0; 995 __IO uint32_t PID1; 996 __IO uint32_t PID2; 997 __IO uint32_t PID3; 998 __IO uint32_t CID0; 999 __IO uint32_t CID1; 1000 __IO uint32_t CID2; 1001 __IO uint32_t CID3; 1002 }TIMER_TypeDef; 1003 1004 /** 1005 * @brief Peripheral_memory_map 1006 */ 1007 #define SRAM1_BASE ((uint32_t)0x20000000) /*!< SRAM1(128 KB) base address */ 1008 #define SRAM2_BASE ((uint32_t)0x20020000) /*!< SRAM2(128 KB) base address */ 1009 #define SRAM3_BASE ((uint32_t)0x20040000) /*!< SRAM3(128 KB) base address */ 1010 1011 /* Legacy defines */ 1012 #define SRAM_BASE SRAM1_BASE 1013 1014 /*!< Peripheral memory map */ 1015 #define PERIPH_BASE (0x40000000) 1016 #define AON_PERIPH_BASE (PERIPH_BASE) 1017 #define APB0_PERIPH_BASE (PERIPH_BASE + 0x00010000) 1018 #define FPGA_PERIPH_BASE (PERIPH_BASE + 0x00020000) 1019 #define FFE_PERIPH_BASE (PERIPH_BASE + 0x00040000) 1020 1021 /* Bit bang memory map */ 1022 #define BB_BASE (0x42000000) 1023 #define AON_BB_BASE (BB_BASE) 1024 #define APB0_BB_BASE (BB_BASE + 0x00200000) 1025 #define FPGA_BB_BASE (BB_BASE + 0x00400000) 1026 #define FFE_BB_BASE (BB_BASE + 0x00800000) 1027 1028 /* AON peripherals */ 1029 #define PKFB_BASE (AON_PERIPH_BASE+0x2000) 1030 #define CRU_BASE (AON_PERIPH_BASE+0x4000) 1031 #define PMU_BASE (AON_PERIPH_BASE+0x4400) 1032 #define INTR_CTRL_BASE (AON_PERIPH_BASE+0x4800) 1033 #define IO_MUX_BASE (AON_PERIPH_BASE+0x4C00) 1034 #define MISC_CTRL_BASE (AON_PERIPH_BASE+0x5000) 1035 #define AIP_BASE (AON_PERIPH_BASE+0x5400) 1036 #define JTM_BASE (AON_PERIPH_BASE+0x5A00) 1037 #define SPT_BASE (AON_PERIPH_BASE+0x5C00) 1038 #define A1_REG_BASE (AON_PERIPH_BASE+0x6000) 1039 #define SPI_MS_BASE (AON_PERIPH_BASE+0x7000) 1040 #define DMA_SPI_MS_BASE (AON_PERIPH_BASE+0x7400) 1041 #define I2S_BASE (AON_PERIPH_BASE+0x8000) 1042 #define I2S_SLAVE_BASE (AON_PERIPH_BASE+0xB000) 1043 #define SDMA_BASE (AON_PERIPH_BASE+0xC000) 1044 #define SDMA_BRIDGE_BASE (AON_PERIPH_BASE+0xD000) 1045 #define SDMA_SRAM_BASE (AON_PERIPH_BASE+0xF000) 1046 1047 /* APB0 peripherals */ 1048 #define UART_BASE (APB0_PERIPH_BASE) 1049 #define WDT1_BASE (APB0_PERIPH_BASE+0x2000) 1050 #define TIMER1_BASE (APB0_PERIPH_BASE+0x3000) 1051 #define PIF_CTRL_BASE (APB0_PERIPH_BASE+0x4000) 1052 #define AUD_BASE (APB0_PERIPH_BASE+0x5000) 1053 #define RAM_FIFO0_BASE (APB0_PERIPH_BASE+0x8000) 1054 #define RAM_FIFO1_BASE (APB0_PERIPH_BASE+0x9000) 1055 #define RAM_FIFO2_BASE (APB0_PERIPH_BASE+0xA000) 1056 #define RAM_FIFO3_BASE (APB0_PERIPH_BASE+0xB000) 1057 1058 /* FFE peripherals */ 1059 #define DM0_BASE (FFE_PERIPH_BASE) 1060 #define SM0_BASE (FFE_PERIPH_BASE+0x04000) 1061 #define SM1_BASE (FFE_PERIPH_BASE+0x08000) 1062 #define EXT_REGS_FFE_BASE (FFE_PERIPH_BASE+0x0A000) 1063 #define DM_FFE1_BASE (FFE_PERIPH_BASE+0x0C000) 1064 #define CM_BASE (FFE_PERIPH_BASE+0x10000) 1065 1066 /* M4 Internal Registers */ 1067 1068 /* Debug MCU registers base address */ 1069 #define DBGMCU_BASE ((uint32_t )0xE0042000) 1070 1071 /* 1072 * Peripheral_declaration 1073 */ 1074 1075 #define UART ((UART_TypeDef *)UART_BASE) 1076 #define PKFB ((PKFB_TypeDef *)PKFB_BASE) 1077 #define IO_MUX ((IO_MUX_TypeDef *)IO_MUX_BASE) 1078 #define INTR_CTRL ((INTR_CTRL_TypeDef *)INTR_CTRL_BASE) 1079 #define SPI_MS ((SPI_TypeDef *) SPI_MS_BASE) 1080 #define I2S ((I2S_TypeDef *) I2S_BASE) 1081 #define AUD ((AUD_TypeDef *) AUD_BASE) 1082 #define CRU ((CRU_TypeDef *) CRU_BASE) 1083 #define PMU ((PMU_TypeDef *) PMU_BASE) 1084 #define MISC_CTRL ((MISC_CTRL_BASE_TypeDef *)MISC_CTRL_BASE) 1085 #define WDT ((WDT_TypeDef *) WDT1_BASE) 1086 #define DMA_SPI_MS ((DMA_SPI_MS_TypeDef *) DMA_SPI_MS_BASE) 1087 #define I2S_SLAVE ((I2S_SLAVE_TypeDef *)I2S_SLAVE_BASE) 1088 #define SDMA ((SDMA_TypeDef *) SDMA_BASE) 1089 #define SDMA_BRIDGE ((SDMA_BRIDGE_TypeDef *) SDMA_BRIDGE_BASE) 1090 #define SDMA_SRAM_TAB ((SDMA_SRAM_ENTRY_TypeDef *) SDMA_SRAM_BASE) 1091 #define EXT_REGS_FFE ((EXT_REGS_FFE_TypeDef *)EXT_REGS_FFE_BASE) 1092 #define AIP ((AIP_Typedef*)AIP_BASE) 1093 #define SPT ((SPT_REGS_TypeDef *)SPT_BASE) 1094 #define TIMER ((TIMER_TypeDef *)TIMER1_BASE) 1095 #define SHM_QL_BASE (0x2007C000) 1096 1097 /****************************************************************************** 1098 * FFE * 1099 ******************************************************************************/ 1100 #define FFE_CMD_RUN_FFE0_ONCE ((uint32_t) (0x00000001)) 1101 #define FFE_CMD_RUN_FFE1 ((uint32_t) (0x00000002)) 1102 #define FFE_CMD_RUN_SM0_ONCE ((uint32_t) (0x00000004)) 1103 #define FFE_CMD_RUN_SM1_ONCE ((uint32_t) (0x00000008)) 1104 1105 #define FFE_INTR_SM_MULT_WR_INTR ((uint32_t) (0x00000001)) 1106 #define FFE_INTR_FFE0_OVERRUN ((uint32_t) (0x00000002)) 1107 #define FFE_INTR_FFE1_SM1_OVERRUN ((uint32_t) (0x00000004)) 1108 #define FFE_INTR_FFE1_SM0_OVERRUN ((uint32_t) (0x00000008)) 1109 #define FFE_INTR_FFE0_SM1_OVERRUN ((uint32_t) (0x00000010)) 1110 #define FFE_INTR_FFE0_SM0_OVERRUN ((uint32_t) (0x00000020)) 1111 #define FFE_INTR_I2C_MS_1_ERROR ((uint32_t) (0x00000040)) 1112 #define FFE_INTR_I2C_MS_0_ERROR ((uint32_t) (0x00000080)) 1113 #define FFE_INTR_CM0_LP_INTR ((uint32_t) (0x00000100)) 1114 #define FFE_INTR_DM0_LP_INTR ((uint32_t) (0x00000200)) 1115 #define FFE_INTR_DM1_LP_INTR ((uint32_t) (0x00000400)) 1116 #define FFE_INTR_SM0_LP_INTR ((uint32_t) (0x00000800)) 1117 #define FFE_INTR_SM1_LP_INTR ((uint32_t) (0x00001000)) 1118 #define FFE_INTR_FFE0_BP_MATCH_INTR ((uint32_t) (0x00002000)) 1119 #define FFE_INTR_FFE1_OVERRUN ((uint32_t) (0x00004000)) 1120 #define FFE_INTR_PKFB_OVF_INTR ((uint32_t) (0x00008000)) 1121 1122 #define FFE_SMO_BUSY ((uint32_t) (0x00000001)) 1123 #define FFE_SM1_BUSY ((uint32_t) (0x00000002)) 1124 #define FFE_FFEO_BUSY ((uint32_t) (0x00000004)) 1125 #define FFE_FFE1_BUSY ((uint32_t) (0x00000008)) 1126 #define FFE_FFEO_BG_FLAG ((uint32_t) (0x00000010)) 1127 #define FFE_FFE0_FG_FLAG ((uint32_t) (0x00000020)) 1128 /****************************************************************************** 1129 * MISC * 1130 ******************************************************************************/ 1131 #define MISC_RUN_FFE_CNT ((uint32_t) (0x00000001)) 1132 #define MISC_FFE_START_PERIOD_LATCH_EN ((uint32_t) (0x00000002)) 1133 #define MISC_PMU_START_PERIOD_LATCH_EN ((uint32_t) (0x00000004)) 1134 #define MISC_FFE_KICKOFF_MODE ((uint32_t) (0x00000008)) 1135 #define MISC_FFE_SPT_EN ((uint32_t) (0x00000010)) 1136 #define MISC_FFE_SLEEP_MODE ((uint32_t) (0x00000020)) 1137 #define MISC_RUN_FFE_CONT_ASYNC ((uint32_t) (0x00000100)) 1138 #define MISC_FFE_KICKOFF_MODE_ASYNC ((uint32_t) (0x00000800)) 1139 #define MISC_FFE_SPT_EN_ASYNC ((uint32_t) (0x00001000)) 1140 #define MISC_FFE_SLEEP_MODE_ASYNC ((uint32_t) (0x00002000)) 1141 1142 /****************************************************************************** 1143 * UART * 1144 ******************************************************************************/ 1145 1146 /* Bit definition for data register */ 1147 #define UART_DR_OVERRUN_ERR ((uint32_t) (1 << 11)) 1148 #define UART_DR_BREAK_ERR ((uint32_t) (1 << 10)) 1149 #define UART_DR_PARITY_ERR ((uint32_t) (1 << 9)) 1150 #define UART_DR_FRAMING_ERR ((uint32_t) (1 << 8)) 1151 #define UART_DR_DATA ((uint32_t) (0xFF)) 1152 1153 /* Bit definition for rx status register */ 1154 #define UART_RSR_OVERRUN_ERR ((uint32_t) (1 << 3)) 1155 #define UART_RSR_BREAK_ERR ((uint32_t) (1 << 2)) 1156 #define UART_RSR_PARITY_ERR ((uint32_t) (1 << 1)) 1157 #define UART_RSR_FRAMING_ERR ((uint32_t) (1 << 0)) 1158 1159 /* Bit definition for flag register */ 1160 #define UART_TFR_RING_INDICATOR ((uint32_t) (1 << 8)) 1161 #define UART_TFR_TX_FIFO_EMPTY ((uint32_t) (1 << 7)) 1162 #define UART_TFR_RX_FIFO_FULL ((uint32_t) (1 << 6)) 1163 #define UART_TFR_TX_FIFO_FULL ((uint32_t) (1 << 5)) 1164 #define UART_TFR_RX_FIFO_EMPTY ((uint32_t) (1 << 4)) 1165 #define UART_TFR_BUSY ((uint32_t) (1 << 3)) 1166 #define UART_TFR_DATA_CARRY_DETECT ((uint32_t) (1 << 2)) 1167 #define UART_TFR_DATA_SET_RDY ((uint32_t) (1 << 1)) 1168 #define UART_TFR_CLEAR_TO_SEND ((uint32_t) (1 << 0)) 1169 1170 /* Bit definition for IrDA low power counter register */ 1171 #define UART_ILPR_LOW_POWER_DIVISOR ((uint32_t) (0xFF)) 1172 1173 /* Bit definition for integer baud rate register */ 1174 #define UART_IBRD_BAUD_INT_DIVISOR ((uint32_t) (0xFFFF)) 1175 1176 1177 /* Bit definition for fractional baud rate register */ 1178 #define UART_IBRD_BAUD_FRACT_DIVISOR ((uint32_t) (0x1F)) 1179 1180 /* Bit definition for line control register */ 1181 #define UART_LCR_STICK_PARITY_SELECT ((uint32_t) (0x80)) 1182 #define UART_LCR_WLEN_8_BITS ((uint32_t) (0x60)) 1183 #define UART_LCR_WLEN_7_BITS ((uint32_t) (0x40)) 1184 #define UART_LCR_WLEN_6_BITS ((uint32_t) (0x20)) 1185 #define UART_LCR_WLEN_5_BITS ((uint32_t) (0x00)) 1186 #define UART_LCR_ENABLE_FIFO ((uint32_t) (0x10)) 1187 #define UART_LCR_TWO_STOP_BITS ((uint32_t) (0x08)) 1188 #define UART_LCR_EVEN_PARITY ((uint32_t) (0x04)) 1189 #define UART_LCR_ODD_PARITY ((uint32_t) (0x00)) 1190 #define UART_LCR_PARITY_ENABLE ((uint32_t) (0x02)) 1191 #define UART_LCR_SEND_BREAK ((uint32_t) (0x01)) 1192 1193 /* Bit definition for control register */ 1194 #define UART_CR_CTS_ENABLE ((uint32_t) (0x8000)) 1195 #define UART_CR_RTS_ENABLE ((uint32_t) (0x4000)) 1196 #define UART_CR_OUT2 ((uint32_t) (0x2000)) 1197 #define UART_CR_OUT1 ((uint32_t) (0x1000)) 1198 #define UART_CR_RTS ((uint32_t) (0x0800)) 1199 #define UART_CR_DTR ((uint32_t) (0x0400)) 1200 #define UART_CR_RX_ENABLE ((uint32_t) (0x0200)) 1201 #define UART_CR_TX_ENABLE ((uint32_t) (0x0100)) 1202 #define UART_CR_LOOPBACK_ENABLE ((uint32_t) (0x0080)) 1203 #define UART_CR_SIR_LOWPOWER ((uint32_t) (0x0004)) 1204 #define UART_CR_SIR_ENABLE ((uint32_t) (0x0002)) 1205 #define UART_CR_UART_ENABLE ((uint32_t) (0x0001)) 1206 1207 /* Bit definition for interrupt FIFO level select register */ 1208 #define UART_IFLS_RX_1_8_FULL ((uint32_t) (0x0000)) 1209 #define UART_IFLS_RX_1_4_FULL ((uint32_t) (0x0008)) 1210 #define UART_IFLS_RX_1_2_FULL ((uint32_t) (0x0010)) 1211 #define UART_IFLS_RX_3_4_FULL ((uint32_t) (0x0018)) 1212 #define UART_IFLS_RX_7_8_FULL ((uint32_t) (0x0020)) 1213 #define UART_IFLS_TX_1_8_FULL ((uint32_t) (0x0000)) 1214 #define UART_IFLS_TX_1_4_FULL ((uint32_t) (0x0001)) 1215 #define UART_IFLS_TX_1_2_FULL ((uint32_t) (0x0002)) 1216 #define UART_IFLS_TX_3_4_FULL ((uint32_t) (0x0003)) 1217 #define UART_IFLS_TX_7_8_FULL ((uint32_t) (0x0004)) 1218 1219 /* Bit definition for interrupt mask set/clear register */ 1220 #define UART_IMSC_OVERRUN_ERR ((uint32_t) (0x0400)) 1221 #define UART_IMSC_BREAK_ERR ((uint32_t) (0x0200)) 1222 #define UART_IMSC_PARITY_ERR ((uint32_t) (0x0100)) 1223 #define UART_IMSC_FRAMING_ERR ((uint32_t) (0x0080)) 1224 #define UART_IMSC_RX_TIMEOUT ((uint32_t) (0x0040)) 1225 #define UART_IMSC_TX ((uint32_t) (0x0020)) 1226 #define UART_IMSC_RX ((uint32_t) (0x0010)) 1227 #define UART_IMSC_DSR ((uint32_t) (0x0008)) 1228 #define UART_IMSC_DCD ((uint32_t) (0x0004)) 1229 #define UART_IMSC_CTS ((uint32_t) (0x0002)) 1230 #define UART_IMSC_RI ((uint32_t) (0x0001)) 1231 1232 /* Bit definition for raw interrupt status register */ 1233 #define UART_RIS_OVERRUN_ERR ((uint32_t) (0x0400)) 1234 #define UART_RIS_BREAK_ERR ((uint32_t) (0x0200)) 1235 #define UART_RIS_PARITY_ERR ((uint32_t) (0x0100)) 1236 #define UART_RIS_FRAMING_ERR ((uint32_t) (0x0080)) 1237 #define UART_RIS_RX_TIMEOUT ((uint32_t) (0x0040)) 1238 #define UART_RIS_TX ((uint32_t) (0x0020)) 1239 #define UART_RIS_RX ((uint32_t) (0x0010)) 1240 #define UART_RIS_DSR ((uint32_t) (0x0008)) 1241 #define UART_RIS_DCD ((uint32_t) (0x0004)) 1242 #define UART_RIS_CTS ((uint32_t) (0x0002)) 1243 #define UART_RIS_RI ((uint32_t) (0x0001)) 1244 1245 /* Bit definition for masked interrupt status register */ 1246 #define UART_MIS_OVERRUN_ERR ((uint32_t) (0x0400)) 1247 #define UART_MIS_BREAK_ERR ((uint32_t) (0x0200)) 1248 #define UART_MIS_PARITY_ERR ((uint32_t) (0x0100)) 1249 #define UART_MIS_FRAMING_ERR ((uint32_t) (0x0080)) 1250 #define UART_MIS_RX_TIMEOUT ((uint32_t) (0x0040)) 1251 #define UART_MIS_TX ((uint32_t) (0x0020)) 1252 #define UART_MIS_RX ((uint32_t) (0x0010)) 1253 #define UART_MIS_DSR ((uint32_t) (0x0008)) 1254 #define UART_MIS_DCD ((uint32_t) (0x0004)) 1255 #define UART_MIS_CTS ((uint32_t) (0x0002)) 1256 #define UART_MIS_RI ((uint32_t) (0x0001)) 1257 1258 /* Bit definition for interrupt clear register */ 1259 #define UART_IC_OVERRUN_ERR ((uint32_t) (0x0400)) 1260 #define UART_IC_BREAK_ERR ((uint32_t) (0x0200)) 1261 #define UART_IC_PARITY_ERR ((uint32_t) (0x0100)) 1262 #define UART_IC_FRAMING_ERR ((uint32_t) (0x0080)) 1263 #define UART_IC_RX_TIMEOUT ((uint32_t) (0x0040)) 1264 #define UART_IC_TX ((uint32_t) (0x0020)) 1265 #define UART_IC_RX ((uint32_t) (0x0010)) 1266 #define UART_IC_DSR ((uint32_t) (0x0008)) 1267 #define UART_IC_DCD ((uint32_t) (0x0004)) 1268 #define UART_IC_CTS ((uint32_t) (0x0002)) 1269 #define UART_IC_RI ((uint32_t) (0x0001)) 1270 1271 /* Bit definition for dma control register */ 1272 #define UART_DMACR_ON_ERR ((uint32_t) (0x0004)) 1273 #define UART_DMACR_TX_DMA_ENABLE ((uint32_t) (0x0002)) 1274 #define UART_DMACR_RX_DMA_ENABLE ((uint32_t) (0x0001)) 1275 1276 /****************************************************************************** 1277 * WDT * 1278 ******************************************************************************/ 1279 #define WDOG_CTRL_RESEN ((uint32_t) (0x0002)) 1280 #define WDOG_CTRL_INTEN ((uint32_t) (0x0001)) 1281 1282 /****************************************************************************** 1283 * DMA * 1284 ******************************************************************************/ 1285 #define DMA_CTRL_START_BIT ((uint32_t) (0x00000001)) 1286 #define DMA_CTRL_STOP_BIT ((uint32_t) (0x00000002)) 1287 #define DMA_CTRL_AHB_SEL_BIT ((uint32_t) (0x00000004)) 1288 1289 #define DMA_INTR_HERROR ((uint32_t) (0x00000001)) 1290 #define DMA_INTR_RX_DATA_AVAIL ((uint32_t) (0x00000002)) 1291 #define DMA_INTR_AHB_BRIDGE_FIFO_OFL ((uint32_t) (0x00000004)) 1292 1293 #define DMA_HERROR_INTR_MSK ((uint32_t) (0x00000001)) 1294 #define DMA_RX_DATA_AVAIL_INTR_MSK ((uint32_t) (0x00000002)) 1295 #define DMA_AHB_FIFO_OFL_INTR_MSK ((uint32_t) (0x00000004)) 1296 1297 /****************************************************************************** 1298 * PKFB * 1299 ******************************************************************************/ 1300 1301 /* Bit definition for FIFO control register */ 1302 #define FIFO_CTRL_PF_ENABLE ((uint32_t) (0x00000001)) 1303 #define FIFO_CTRL_PF_PUSH_MUX_FFE ((uint32_t) (0x00000002)) 1304 #define FIFO_CTRL_PF_PUSH_MUX_M4 ((uint32_t) (0x00000000)) 1305 #define FIFO_CTRL_PF_POP_MUX_AP ((uint32_t) (0x00000004)) 1306 #define FIFO_CTRL_PF_POP_MUX_M4 ((uint32_t) (0x00000000)) 1307 #define FIFO_CTRL_PF_PUSH_INT_MUX_AP ((uint32_t) (0x00000008)) 1308 #define FIFO_CTRL_PF_PUSH_INT_MUX_M4 ((uint32_t) (0x00000000)) 1309 #define FIFO_CTRL_PF_POP_INT_MUX_AP ((uint32_t) (0x00000010)) 1310 #define FIFO_CTRL_PF_POP_INT_MUX_M4 ((uint32_t) (0x00000000)) 1311 #define FIFO_CTRL_PF_FFE_SEL_FFE1 ((uint32_t) (0x00000020)) 1312 #define FIFO_CTRL_PF_FFE_SEL_FFE0 ((uint32_t) (0x00000000)) 1313 1314 #define FIFO_CTRL_PF0_SHIFT (0) 1315 #define FIFO_CTRL_PF1_SHIFT (8) 1316 #define FIFO_CTRL_PF2_SHIFT (16) 1317 #define FIFO_CTRL_PF8K_SHIFT (24) 1318 1319 #define FIFO_SRAM_CTRL_PF_TEST1A_ENABLE ((uint32_t) (0x00000000)) 1320 #define FIFO_SRAM_CTRL_PF_TEST1A_DISABLE ((uint32_t) (0x00000001)) 1321 #define FIFO_SRAM_CTRL_PF_RMEA_ENABLE ((uint32_t) (0x00000000)) 1322 #define FIFO_SRAM_CTRL_PF_RMEA_DISABLE ((uint32_t) (0x00000002)) 1323 #define FIFO_SRAM_CTRL_PF_RMA_MASK ((uint32_t) (0x0000003C)) 1324 #define FIFO_SRAM_CTRL_PF_TEST1B_ENABLE ((uint32_t) (0x00000000)) 1325 #define FIFO_SRAM_CTRL_PF_TEST1B_DISABLE ((uint32_t) (0x00000100)) 1326 #define FIFO_SRAM_CTRL_PF_RMEB_ENABLE ((uint32_t) (0x00000000)) 1327 #define FIFO_SRAM_CTRL_PF_RMEB_DISABLE ((uint32_t) (0x00000200)) 1328 #define FIFO_SRAM_CTRL_PF_RMB_MASK ((uint32_t) (0x00003C00)) 1329 1330 #define FIFO_SRAM_CTRL0_PF0_SHIFT (0) 1331 #define FIFO_SRAM_CTRL0_PF1_SHIFT (16) 1332 #define FIFO_SRAM_CTRL1_PF2_SHIFT (0) 1333 #define FIFO_SRAM_CTRL1_PF8K_SHIFT (16) 1334 1335 #define FIFO_STATUS_PF_SRAM_SLEEP_ACTIVE ((uint32_t) (0x00000000)) 1336 #define FIFO_STATUS_PF_SRAM_SLEEP_LIGHT ((uint32_t) (0x00000001)) 1337 #define FIFO_STATUS_PF_SRAM_SLEEP_DEEP ((uint32_t) (0x00000002)) 1338 #define FIFO_STATUS_PF_SRAM_SLEEP_SHUTDOWN ((uint32_t) (0x00000003)) 1339 #define FIFO_STATUS_PF_PUSH_INT_OVER ((uint32_t) (0x00000004)) 1340 #define FIFO_STATUS_PF_PUSH_INT_THRESH ((uint32_t) (0x00000008)) 1341 #define FIFO_STATUS_PF_PUSH_INT_SLEEP ((uint32_t) (0x00000010)) 1342 #define FIFO_STATUS_PF_POP_INT_UNDER ((uint32_t) (0x00000020)) 1343 #define FIFO_STATUS_PF_POP_INT_THRESH ((uint32_t) (0x00000040)) 1344 #define FIFO_STATUS_PF_POP_INT_SLEEP ((uint32_t) (0x00000080)) 1345 1346 #define FIFO_STATUS_PF0_SHIFT (0) 1347 #define FIFO_STATUS_PF1_SHIFT (8) 1348 #define FIFO_STATUS_PF2_SHIFT (16) 1349 #define FIFO_STATUS_PF8K_SHIFT (24) 1350 1351 #define PF_PUSH_CTRL_SLEEP_EN_ACTIVE ((uint32_t) (0x00000001)) 1352 #define PF_PUSH_CTRL_SLEEP_TYPE_SD ((uint32_t) (0x00000002)) 1353 #define PF_PUSH_CTRL_SLEEP_TYPE_DS ((uint32_t) (0x00000000)) 1354 #define PF_PUSH_CTRL_INT_EN_MASK ((uint32_t) (0x00000000)) 1355 #define PF_PUSH_CTRL_INT_EN_OVER ((uint32_t) (0x00000004)) 1356 #define PF_PUSH_CTRL_INT_EN_THRES ((uint32_t) (0x00000008)) 1357 #define PF_PUSH_CTRL_INT_EN_PUSH_ON_SLEEP ((uint32_t) (0x00000010)) 1358 #define PF_PUSH_CTRL_PUSH_THRESH_MASK ((uint32_t) (0x01FF0000)) 1359 1360 #define PF_POP_CTRL_SLEEP_EN_ACTIVE ((uint32_t) (0x00000001)) 1361 #define PF_POP_CTRL_SLEEP_TYPE_SD ((uint32_t) (0x00000002)) 1362 #define PF_POP_CTRL_SLEEP_TYPE_DS ((uint32_t) (0x00000000)) 1363 #define PF_POP_CTRL_INT_EN_MASK ((uint32_t) (0x00000000)) 1364 #define PF_POP_CTRL_INT_EN_UNDER ((uint32_t) (0x00000004)) 1365 #define PF_POP_CTRL_INT_EN_THRES ((uint32_t) (0x00000008)) 1366 #define PF_POP_CTRL_INT_EN_POP_ON_SLEEP ((uint32_t) (0x00000010)) 1367 #define PF_POP_CTRL_PUSH_THRESH_MASK ((uint32_t) (0x01FF0000)) 1368 1369 #define PF_CNT_POP_CNT_MASK ((uint32_t) (0x000001FF)) 1370 #define PF_CNT_POP_EMPTY_MASK ((uint32_t) (0x00008000)) 1371 #define PF_CNT_PUSH_CNT_MASK ((uint32_t) (0x01FF0000)) 1372 #define PF_CNT_PUSH_EMPTY_MASK ((uint32_t) (0x80000000)) 1373 1374 #define PF8K_DATA_REG_PUSH_EOP ((uint32_t) (0x00020000)) 1375 1376 #define FIFO_COLL_INTR_PF_COLL_INTR ((uint32_t) (0x00000001)) 1377 1378 #define FIFO_COLL_INTR_PF0_SHIFT (0) 1379 #define FIFO_COLL_INTR_PF1_SHIFT (1) 1380 #define FIFO_COLL_INTR_PF2_SHIFT (2) 1381 #define FIFO_COLL_INTR_PF8K_SHIFT (3) 1382 1383 #define FIFO_COLL_INTR_EN_PF_COLL_INTR ((uint32_t) (0x00000001)) 1384 1385 #define FIFO_COLL_INTR_EN_PF0_SHIFT (0) 1386 #define FIFO_COLL_INTR_EN_PF1_SHIFT (1) 1387 #define FIFO_COLL_INTR_EN_PF2_SHIFT (2) 1388 #define FIFO_COLL_INTR_EN_PF8K_SHIFT (3) 1389 1390 /****************************************************************************** 1391 * IO_MUX * 1392 ******************************************************************************/ 1393 1394 /* Common bit definition for all PAD control registers */ 1395 1396 #define PAD_CTRL_SEL_AO_REG ((uint32_t) (0x00000000)) 1397 #define PAD_CTRL_SEL_OTHER ((uint32_t) (0x00000008)) 1398 #define PAD_CTRL_SEL_FPGA ((uint32_t) (0x00000010)) 1399 #define PAD_OEN_DISABLE ((uint32_t) (0x00000020)) 1400 #define PAD_OEN_NORMAL ((uint32_t) (0x00000000)) 1401 #define PAD_P_Z ((uint32_t) (0x00000000)) 1402 #define PAD_P_PULLUP ((uint32_t) (0x00000040)) 1403 #define PAD_P_PULLDOWN ((uint32_t) (0x00000080)) 1404 #define PAD_P_KEEPER ((uint32_t) (0x000000C0)) 1405 #define PAD_E_2MA ((uint32_t) (0x00000000)) 1406 #define PAD_E_4MA ((uint32_t) (0x00000100)) 1407 #define PAD_E_8MA ((uint32_t) (0x00000200)) 1408 #define PAD_E_12MA ((uint32_t) (0x00000300)) 1409 #define PAD_SR_FAST ((uint32_t) (0x00000400)) 1410 #define PAD_SR_SLOW ((uint32_t) (0x00000000)) 1411 #define PAD_REN_ENABLE ((uint32_t) (0x00000800)) 1412 #define PAD_REN_DISABLE ((uint32_t) (0x00000000)) 1413 #define PAD_SMT_ENABLE ((uint32_t) (0x00001000)) 1414 #define PAD_SMT_DISABLE ((uint32_t) (0x00000000)) 1415 1416 1417 #define PAD_E_12MA ((uint32_t) (0x00000300)) 1418 #define PAD_OEN_NORMAL ((uint32_t) (0x00000000)) 1419 1420 #define SDA0_SEL_PAD1 ((uint32_t) (0x00000001)) 1421 #define SDA1_SEL_PAD10 ((uint32_t) (0x00000001)) 1422 #define SDA1_SEL_PAD32 ((uint32_t) (0x00000002)) 1423 #define SCL1_SEL_PAD33 ((uint32_t) (0x00000002)) 1424 #define SDA2_SEL_PAD34 ((uint32_t) (0x00000001)) 1425 #define SCL0_SEL_PAD0 ((uint32_t) (0x00000000)) 1426 #define SCL0_SEL_0 ((uint32_t) (0x00000001)) 1427 #define SCL1_SEL_0 ((uint32_t) (0x00000000)) 1428 #define SCL1_SEL_PAD9 ((uint32_t) (0x00000001)) 1429 #define SCL2_SEL_0 ((uint32_t) (0x00000000)) 1430 #define SCL2_SEL_PAD33 ((uint32_t) (0x00000001)) 1431 1432 #define SPIS_CLK_SEL_PAD17 ((uint32_t) (0x00000000)) 1433 #define SPIS_CLK_SEL_0 ((uint32_t) (0x00000001)) 1434 1435 #define SPIS_SSN_SEL_PAD20 ((uint32_t) (0x00000000)) 1436 #define SPIS_SSN_SEL_0 ((uint32_t) (0x00000001)) 1437 1438 #define SPIS_MOSI_SEL_PAD19 ((uint32_t) (0x00000000)) 1439 #define SPIS_MOSI_SEL_0 ((uint32_t) (0x00000001)) 1440 1441 #define SPIS_MISO_SEL_PAD23 ((uint32_t) (0x00000000)) 1442 #define SPIS_MISO_SEL_0 ((uint32_t) (0x00000001)) 1443 1444 #define PDM_DATA_SEL_0 ((uint32_t) (0x00000000)) 1445 #define PDM_DATA_SEL_PAD7 ((uint32_t) (0x00000001)) 1446 1447 #define I2S_DATA_SEL_0 ((uint32_t) (0x00000000)) 1448 #define I2S_DATA_SEL_PAD7 ((uint32_t) (0x00000001)) 1449 1450 #define UART_RXD_SEL_0 ((uint32_t) (0x00000000)) 1451 #define UART_RXD_SEL_PAD16 ((uint32_t) (0x00000002)) 1452 #define UART_RXD_SEL_PAD45 ((uint32_t) (0x00000004)) 1453 1454 #define UART_TXD_SEL_0 ((uint32_t) (0x00000000)) 1455 #define UART_TXD_SEL_PAD44 ((uint32_t) (0x00000003)) 1456 1457 #define IRDA_SIRIN_SEL_0 ((uint32_t) (0x00000000)) 1458 #define IRDA_SIRIN_SEL_PAD6 ((uint32_t) (0x00000001)) 1459 #define IRDA_SIRIN_SEL_PAD11 ((uint32_t) (0x00000002)) 1460 #define IRDA_SIRIN_SEL_PAD13 ((uint32_t) (0x00000003)) 1461 #define IRDA_SIRIN_SEL_PAD26 ((uint32_t) (0x00000004)) 1462 #define IRDA_SIRIN_SEL_PAD28 ((uint32_t) (0x00000005)) 1463 #define IRDA_SIRIN_SEL_PAD31 ((uint32_t) (0x00000006)) 1464 #define IRDA_SIRIN_SEL_PAD33 ((uint32_t) (0x00000007)) 1465 1466 #define S_INTR_0_SEL_0 ((uint32_t) (0x00000000)) 1467 #define S_INTR_0_SEL_PAD2 ((uint32_t) (0x00000001)) 1468 1469 #define S_INTR_1_SEL_0 ((uint32_t) (0x00000000)) 1470 #define S_INTR_1_SEL_PAD4 ((uint32_t) (0x00000001)) 1471 #define S_INTR_1_SEL_PAD11 ((uint32_t) (0x00000002)) 1472 #define S_INTR_1_SEL_PAD15 ((uint32_t) (0x00000003)) 1473 #define S_INTR_1_SEL_PAD26 ((uint32_t) (0x00000004)) 1474 #define S_INTR_1_SEL_PAD32 ((uint32_t) (0x00000005)) 1475 1476 #define S_INTR_2_SEL_0 ((uint32_t) (0x00000000)) 1477 #define S_INTR_2_SEL_PAD5 ((uint32_t) (0x00000001)) 1478 #define S_INTR_2_SEL_PAD12 ((uint32_t) (0x00000002)) 1479 #define S_INTR_2_SEL_PAD16 ((uint32_t) (0x00000003)) 1480 #define S_INTR_2_SEL_PAD27 ((uint32_t) (0x00000004)) 1481 #define S_INTR_2_SEL_PAD33 ((uint32_t) (0x00000005)) 1482 1483 #define S_INTR_3_SEL_0 ((uint32_t) (0x00000000)) 1484 #define S_INTR_3_SEL_PAD6 ((uint32_t) (0x00000001)) 1485 #define S_INTR_3_SEL_PAD13 ((uint32_t) (0x00000002)) 1486 #define S_INTR_3_SEL_PAD21 ((uint32_t) (0x00000003)) 1487 #define S_INTR_3_SEL_PAD28 ((uint32_t) (0x00000004)) 1488 #define S_INTR_3_SEL_PAD34 ((uint32_t) (0x00000005)) 1489 1490 #define S_INTR_4_SEL_0 ((uint32_t) (0x00000000)) 1491 #define S_INTR_4_SEL_PAD7 ((uint32_t) (0x00000001)) 1492 #define S_INTR_4_SEL_PAD14 ((uint32_t) (0x00000002)) 1493 #define S_INTR_4_SEL_PAD22 ((uint32_t) (0x00000003)) 1494 #define S_INTR_4_SEL_PAD35 ((uint32_t) (0x00000004)) 1495 1496 #define S_INTR_5_SEL_0 ((uint32_t) (0x00000000)) 1497 #define S_INTR_5_SEL_PAD8 ((uint32_t) (0x00000001)) 1498 #define S_INTR_5_SEL_PAD23 ((uint32_t) (0x00000002)) 1499 #define S_INTR_5_SEL_PAD29 ((uint32_t) (0x00000003)) 1500 1501 #define S_INTR_6_SEL_0 ((uint32_t) (0x00000000)) 1502 #define S_INTR_6_SEL_PAD9 ((uint32_t) (0x00000001)) 1503 #define S_INTR_6_SEL_PAD24 ((uint32_t) (0x00000002)) 1504 #define S_INTR_6_SEL_PAD30 ((uint32_t) (0x00000003)) 1505 1506 #define S_INTR_7_SEL_0 ((uint32_t) (0x00000000)) 1507 #define S_INTR_7_SEL_PAD10 ((uint32_t) (0x00000001)) 1508 #define S_INTR_7_SEL_PAD25 ((uint32_t) (0x00000002)) 1509 #define S_INTR_7_SEL_PAD31 ((uint32_t) (0x00000003)) 1510 1511 #define NUARTCTS_SEL_0 ((uint32_t) (0x00000000)) 1512 #define NUARTCTS_SEL_PAD21 ((uint32_t) (0x00000001)) 1513 1514 #define IO_REG_SEL_PAD7 ((uint32_t) (0x00000000)) 1515 #define IO_REG_SEL_PAD11 ((uint32_t) (0x00000001)) 1516 #define IO_REG_SEL_PAD10 ((uint32_t) (0x00000000)) 1517 #define IO_REG_SEL_PAD12 ((uint32_t) (0x00000002)) 1518 #define IO_REG_SEL_PAD15 ((uint32_t) (0x00000000)) 1519 #define IO_REG_SEL_PAD13 ((uint32_t) (0x00000004)) 1520 #define IO_REG_SEL_PAD16 ((uint32_t) (0x00000000)) 1521 #define IO_REG_SEL_PAD14 ((uint32_t) (0x00000008)) 1522 #define IO_REG_SEL_PAD22 ((uint32_t) (0x00000000)) 1523 #define IO_REG_SEL_PAD29 ((uint32_t) (0x00000010)) 1524 #define IO_REG_SEL_PAD23 ((uint32_t) (0x00000000)) 1525 #define IO_REG_SEL_PAD30 ((uint32_t) (0x00000020)) 1526 #define IO_REG_SEL_PAD25 ((uint32_t) (0x00000000)) 1527 #define IO_REG_SEL_PAD31 ((uint32_t) (0x00000040)) 1528 #define IO_REG_SEL_PAD26 ((uint32_t) (0x00000000)) 1529 #define IO_REG_SEL_PAD32 ((uint32_t) (0x00000080)) 1530 1531 #define SW_CLK_SEL_PAD8 ((uint32_t) (0x00000000)) 1532 #define SW_CLK_SEL_0 ((uint32_t) (0x00000001)) 1533 1534 #define SW_IO_SEL_PAD8 ((uint32_t) (0x00000000)) 1535 #define SW_IO_SEL_0 ((uint32_t) (0x00000001)) 1536 1537 #define FBIO_SEL_0 ((uint32_t) (0x00000000)) 1538 #define FBIO_SEL_PAD ((uint32_t) (0x00000001)) 1539 1540 #define FBIO_SEL_25_PAD17 ((uint32_t) (0x00000000)) 1541 #define FBIO_SEL_25_PAD34 ((uint32_t) (0x00000001)) 1542 #define FBIO_SEL_27_PAD18 ((uint32_t) (0x00000000)) 1543 #define FBIO_SEL_27_PAD26 ((uint32_t) (0x00000002)) 1544 #define FBIO_SEL_29_PAD19 ((uint32_t) (0x00000000)) 1545 #define FBIO_SEL_29_PAD27 ((uint32_t) (0x00000004)) 1546 #define FBIO_SEL_31_PAD20 ((uint32_t) (0x00000000)) 1547 #define FBIO_SEL_31_PAD35 ((uint32_t) (0x00000008)) 1548 1549 /****************************************************************************** 1550 * INTR_CTRL * 1551 ******************************************************************************/ 1552 #define GPIO_7_INTR ((uint32_t) (0x00000080)) 1553 #define GPIO_6_INTR ((uint32_t) (0x00000040)) 1554 #define GPIO_5_INTR ((uint32_t) (0x00000020)) 1555 #define GPIO_4_INTR ((uint32_t) (0x00000010)) 1556 #define GPIO_3_INTR ((uint32_t) (0x00000008)) 1557 #define GPIO_2_INTR ((uint32_t) (0x00000004)) 1558 #define GPIO_1_INTR ((uint32_t) (0x00000002)) 1559 #define GPIO_0_INTR ((uint32_t) (0x00000001)) 1560 1561 #define GPIO_7_INTR_RAW ((uint32_t) (0x00000080)) 1562 #define GPIO_6_INTR_RAW ((uint32_t) (0x00000040)) 1563 #define GPIO_5_INTR_RAW ((uint32_t) (0x00000020)) 1564 #define GPIO_4_INTR_RAW ((uint32_t) (0x00000010)) 1565 #define GPIO_3_INTR_RAW ((uint32_t) (0x00000008)) 1566 #define GPIO_2_INTR_RAW ((uint32_t) (0x00000004)) 1567 #define GPIO_1_INTR_RAW ((uint32_t) (0x00000002)) 1568 #define GPIO_0_INTR_RAW ((uint32_t) (0x00000001)) 1569 1570 #define GPIO_7_INTR_TYPE_EDGE ((uint32_t) (0x00000080)) 1571 #define GPIO_7_INTR_TYPE_LEVEL ((uint32_t) (0x00000000)) 1572 #define GPIO_6_INTR_TYPE_EDGE ((uint32_t) (0x00000040)) 1573 #define GPIO_6_INTR_TYPE_LEVEL ((uint32_t) (0x00000000)) 1574 #define GPIO_5_INTR_TYPE_EDGE ((uint32_t) (0x00000020)) 1575 #define GPIO_5_INTR_TYPE_LEVEL ((uint32_t) (0x00000000)) 1576 #define GPIO_4_INTR_TYPE_EDGE ((uint32_t) (0x00000010)) 1577 #define GPIO_4_INTR_TYPE_LEVEL ((uint32_t) (0x00000000)) 1578 #define GPIO_3_INTR_TYPE_EDGE ((uint32_t) (0x00000008)) 1579 #define GPIO_3_INTR_TYPE_LEVEL ((uint32_t) (0x00000000)) 1580 #define GPIO_2_INTR_TYPE_EDGE ((uint32_t) (0x00000004)) 1581 #define GPIO_2_INTR_TYPE_LEVEL ((uint32_t) (0x00000000)) 1582 #define GPIO_1_INTR_TYPE_EDGE ((uint32_t) (0x00000002)) 1583 #define GPIO_1_INTR_TYPE_LEVEL ((uint32_t) (0x00000000)) 1584 #define GPIO_0_INTR_TYPE_EDGE ((uint32_t) (0x00000001)) 1585 #define GPIO_0_INTR_TYPE_LEVEL ((uint32_t) (0x00000000)) 1586 1587 #define GPIO_7_INTR_POL_HI_RISE ((uint32_t) (0x00000080)) 1588 #define GPIO_7_INTR_POL_LO_FALL ((uint32_t) (0x00000000)) 1589 #define GPIO_6_INTR_POL_HI_RISE ((uint32_t) (0x00000040)) 1590 #define GPIO_6_INTR_POL_LO_FALL ((uint32_t) (0x00000000)) 1591 #define GPIO_5_INTR_POL_HI_RISE ((uint32_t) (0x00000020)) 1592 #define GPIO_5_INTR_POL_LO_FALL ((uint32_t) (0x00000000)) 1593 #define GPIO_4_INTR_POL_HI_RISE ((uint32_t) (0x00000010)) 1594 #define GPIO_4_INTR_POL_LO_FALL ((uint32_t) (0x00000000)) 1595 #define GPIO_3_INTR_POL_HI_RISE ((uint32_t) (0x00000008)) 1596 #define GPIO_3_INTR_POL_LO_FALL ((uint32_t) (0x00000000)) 1597 #define GPIO_2_INTR_POL_HI_RISE ((uint32_t) (0x00000004)) 1598 #define GPIO_2_INTR_POL_LO_FALL ((uint32_t) (0x00000000)) 1599 #define GPIO_1_INTR_POL_HI_RISE ((uint32_t) (0x00000002)) 1600 #define GPIO_1_INTR_POL_LO_FALL ((uint32_t) (0x00000000)) 1601 #define GPIO_0_INTR_POL_HI_RISE ((uint32_t) (0x00000001)) 1602 #define GPIO_0_INTR_POL_LO_FALL ((uint32_t) (0x00000000)) 1603 1604 #define GPIO_7_INTR_EN_AP_ENABLE ((uint32_t) (0x00000080)) 1605 #define GPIO_6_INTR_EN_AP_ENABLE ((uint32_t) (0x00000040)) 1606 #define GPIO_5_INTR_EN_AP_ENABLE ((uint32_t) (0x00000020)) 1607 #define GPIO_4_INTR_EN_AP_ENABLE ((uint32_t) (0x00000010)) 1608 #define GPIO_3_INTR_EN_AP_ENABLE ((uint32_t) (0x00000008)) 1609 #define GPIO_2_INTR_EN_AP_ENABLE ((uint32_t) (0x00000004)) 1610 #define GPIO_1_INTR_EN_AP_ENABLE ((uint32_t) (0x00000002)) 1611 #define GPIO_0_INTR_EN_AP_ENABLE ((uint32_t) (0x00000001)) 1612 1613 #define GPIO_7_INTR_EN_M4_ENABLE ((uint32_t) (0x00000080)) 1614 #define GPIO_6_INTR_EN_M4_ENABLE ((uint32_t) (0x00000040)) 1615 #define GPIO_5_INTR_EN_M4_ENABLE ((uint32_t) (0x00000020)) 1616 #define GPIO_4_INTR_EN_M4_ENABLE ((uint32_t) (0x00000010)) 1617 #define GPIO_3_INTR_EN_M4_ENABLE ((uint32_t) (0x00000008)) 1618 #define GPIO_2_INTR_EN_M4_ENABLE ((uint32_t) (0x00000004)) 1619 #define GPIO_1_INTR_EN_M4_ENABLE ((uint32_t) (0x00000002)) 1620 #define GPIO_0_INTR_EN_M4_ENABLE ((uint32_t) (0x00000001)) 1621 1622 #define GPIO_7_INTR_EN_FFE0_ENABLE ((uint32_t) (0x00000080)) 1623 #define GPIO_6_INTR_EN_FFE0_ENABLE ((uint32_t) (0x00000040)) 1624 #define GPIO_5_INTR_EN_FFE0_ENABLE ((uint32_t) (0x00000020)) 1625 #define GPIO_4_INTR_EN_FFE0_ENABLE ((uint32_t) (0x00000010)) 1626 #define GPIO_3_INTR_EN_FFE0_ENABLE ((uint32_t) (0x00000008)) 1627 #define GPIO_2_INTR_EN_FFE0_ENABLE ((uint32_t) (0x00000004)) 1628 #define GPIO_1_INTR_EN_FFE0_ENABLE ((uint32_t) (0x00000002)) 1629 #define GPIO_0_INTR_EN_FFE0_ENABLE ((uint32_t) (0x00000001)) 1630 1631 #define GPIO_7_INTR_EN_FFE1_ENABLE ((uint32_t) (0x00000080)) 1632 #define GPIO_6_INTR_EN_FFE1_ENABLE ((uint32_t) (0x00000040)) 1633 #define GPIO_5_INTR_EN_FFE1_ENABLE ((uint32_t) (0x00000020)) 1634 #define GPIO_4_INTR_EN_FFE1_ENABLE ((uint32_t) (0x00000010)) 1635 #define GPIO_3_INTR_EN_FFE1_ENABLE ((uint32_t) (0x00000008)) 1636 #define GPIO_2_INTR_EN_FFE1_ENABLE ((uint32_t) (0x00000004)) 1637 #define GPIO_1_INTR_EN_FFE1_ENABLE ((uint32_t) (0x00000002)) 1638 #define GPIO_0_INTR_EN_FFE1_ENABLE ((uint32_t) (0x00000001)) 1639 1640 // naveen - s3b 1641 #define DMIC_VOICE_DET ((uint32_t)1<<23) 1642 #define LPSD_VOICE_DET ((uint32_t)1<<22) 1643 #define APBOOT_EN_DETECT ((uint32_t) (0x00040000)) 1644 #define WDT_FFE_DETECT ((uint32_t) (0x00020000)) 1645 #define FFE0_INTR_OTHERS_DETECT ((uint32_t) (0x00010000)) 1646 #define RST_INTR_DETECT ((uint32_t) (0x00008000)) 1647 #define RTC_INTR_DETECT ((uint32_t) (0x00004000)) 1648 #define ADC_INTR_DETECT ((uint32_t) (0x00002000)) 1649 #define PMU_TMR_INTR_DETECT ((uint32_t) (0x00001000)) 1650 #define CFG_DMA_DONE_DETECT ((uint32_t) (0x00000800)) 1651 #define SPI_MS_INTR_DETECT ((uint32_t) (0x00000400)) 1652 #define AUD_INTR_DETECT ((uint32_t) (0x00000200)) 1653 #define I2S_INTR_DETECT ((uint32_t) (0x00000100)) 1654 1655 #define PKFB_INTR_DETECT ((uint32_t) (0x00000080)) 1656 #define FPU_INTR_DETECT ((uint32_t) (0x00000040)) 1657 #define TIMEOUT_INTR_DETECT ((uint32_t) (0x00000020)) 1658 #define WDOG_RST_DETECT ((uint32_t) (0x00000010)) 1659 #define WDOG_INTR_DETECT ((uint32_t) (0x00000008)) 1660 #define TIMER_INTR_DETECT ((uint32_t) (0x00000004)) 1661 #define UART_INTR_DETECT ((uint32_t) (0x00000002)) 1662 #define M4_SRAM_INTR_DETECT ((uint32_t) (0x00000001)) 1663 1664 #define DMIC_VOICE_INTR ((uint32_t) (0x00800000)) 1665 #define LPSD_VOICE_INTR ((uint32_t) (0x00400000)) 1666 #define SRAM_128KB_INTR ((uint32_t) (0x00200000)) 1667 #define LDO50_PG_INTR ((uint32_t) (0x00100000)) 1668 #define LDO30_PG_INTR ((uint32_t) (0x00080000)) 1669 1670 #define APBOOT_EN_DETECT ((uint32_t) (0x00040000)) 1671 #define WDT_FFE_DETECT ((uint32_t) (0x00020000)) 1672 #define FFE0_INTR_OTHERS_DETECT ((uint32_t) (0x00010000)) 1673 1674 #define DMIC_VOICE_EN_AP ((uint32_t) (0x00800000)) 1675 #define LPSD_VOICE_EN_AP ((uint32_t) (0x00400000)) 1676 #define SRAM_128KB_EN_AP ((uint32_t) (0x00200000)) 1677 #define LDO50_PG_EN_AP ((uint32_t) (0x00100000)) 1678 #define LDO30_PG_EN_AP ((uint32_t) (0x00080000)) 1679 #define APBOOT_EN_AP ((uint32_t) (0x00040000)) 1680 #define WDT_FFE_EN_AP ((uint32_t) (0x00020000)) 1681 #define FFE0_INTR_OTHERS_EN_AP ((uint32_t) (0x00010000)) 1682 #define RST_INTR_EN_AP ((uint32_t) (0x00008000)) 1683 #define RTC_INTR_EN_AP ((uint32_t) (0x00004000)) 1684 #define ADC_INTR_EN_AP ((uint32_t) (0x00002000)) 1685 #define PMU_TMR_INTR_EN_AP ((uint32_t) (0x00001000)) 1686 #define CFG_DMA_DONE_EN_AP ((uint32_t) (0x00000800)) 1687 #define SPI_MS_INTR_EN_AP ((uint32_t) (0x00000400)) 1688 #define PKFB_INTR_EN_AP ((uint32_t) (0x00000080)) 1689 #define FPU_INTR_EN_AP ((uint32_t) (0x00000040)) 1690 #define TIMEOUT_INTR_EN_AP ((uint32_t) (0x00000020)) 1691 #define WDOG_RST_EN_AP ((uint32_t) (0x00000010)) 1692 #define WDOG_INTR_EN_AP ((uint32_t) (0x00000008)) 1693 #define TIMER_INTR_EN_AP ((uint32_t) (0x00000004)) 1694 #define UART_INTR_EN_AP ((uint32_t) (0x00000002)) 1695 #define M4_SRAM_INTR_EN_AP ((uint32_t) (0x00000001)) 1696 1697 #define DMIC_VOICE_EN_M4 ((uint32_t) (0x00800000)) 1698 #define LPSD_VOICE_EN_M4 ((uint32_t) (0x00400000)) 1699 #define SRAM_128KB_EN_M4 ((uint32_t) (0x00200000)) 1700 #define LDO50_PG_EN_M4 ((uint32_t) (0x00100000)) 1701 #define LDO30_PG_EN_M4 ((uint32_t) (0x00080000)) 1702 #define APBOOT_EN_M4 ((uint32_t) (0x00040000)) 1703 #define WDT_FFE_EN_M4 ((uint32_t) (0x00020000)) 1704 #define FFE0_INTR_OTHERS_EN_M4 ((uint32_t) (0x00010000)) 1705 #define RST_INTR_EN_M4 ((uint32_t) (0x00008000)) 1706 #define RTC_INTR_EN_M4 ((uint32_t) (0x00004000)) 1707 #define ADC_INTR_EN_M4 ((uint32_t) (0x00002000)) 1708 #define PMU_TMR_INTR_EN_M4 ((uint32_t) (0x00001000)) 1709 #define CFG_DMA_DONE_EN_M4 ((uint32_t) (0x00000800)) 1710 #define SPI_MS_INTR_EN_M4 ((uint32_t) (0x00000400)) 1711 #define PKFB_INTR_EN_M4 ((uint32_t) (0x00000080)) 1712 #define FPU_INTR_EN_M4 ((uint32_t) (0x00000040)) 1713 #define TIMEOUT_INTR_EN_M4 ((uint32_t) (0x00000020)) 1714 #define WDOG_RST_EN_M4 ((uint32_t) (0x00000010)) 1715 #define WDOG_INTR_EN_M4 ((uint32_t) (0x00000008)) 1716 #define TIMER_INTR_EN_M4 ((uint32_t) (0x00000004)) 1717 #define UART_INTR_EN_M4 ((uint32_t) (0x00000002)) 1718 #define M4_SRAM_INTR_EN_M4 ((uint32_t) (0x00000001)) 1719 1720 #define SW_INTR_1 ((uint32_t) (0x00000001)) 1721 #define SW_INTR_1_EN_AP ((uint32_t) (0x00000001)) 1722 #define SW_INTR_1_EN_M4 ((uint32_t) (0x00000001)) 1723 #define SW_INTR_2 ((uint32_t) (0x00000001)) 1724 #define SW_INTR_2_EN_AP ((uint32_t) (0x00000001)) 1725 #define SW_INTR_2_EN_M4 ((uint32_t) (0x00000001)) 1726 1727 #define FFE0_7_INTR_DETECT ((uint32_t)0x00000080) 1728 #define FFE0_6_INTR_DETECT ((uint32_t) (0x00000040)) 1729 #define FFE0_5_INTR_DETECT ((uint32_t) (0x00000020)) 1730 #define FFE0_4_INTR_DETECT ((uint32_t) (0x00000010)) 1731 #define FFE0_3_INTR_DETECT ((uint32_t) (0x00000008)) 1732 #define FFE0_2_INTR_DETECT ((uint32_t) (0x00000004)) 1733 #define FFE0_1_INTR_DETECT ((uint32_t) (0x00000002)) 1734 #define FFE0_0_INTR_DETECT ((uint32_t) (0x00000001)) 1735 1736 #define FFE0_7_INTR_EN_AP ((uint32_t) (0x00000080)) 1737 #define FFE0_6_INTR_EN_AP ((uint32_t) (0x00000040)) 1738 #define FFE0_5_INTR_EN_AP ((uint32_t) (0x00000020)) 1739 #define FFE0_4_INTR_EN_AP ((uint32_t) (0x00000010)) 1740 #define FFE0_3_INTR_EN_AP ((uint32_t) (0x00000008)) 1741 #define FFE0_2_INTR_EN_AP ((uint32_t) (0x00000004)) 1742 #define FFE0_1_INTR_EN_AP ((uint32_t) (0x00000002)) 1743 #define FFE0_0_INTR_EN_AP ((uint32_t) (0x00000001)) 1744 1745 #define FFE0_7_INTR_EN_M4 ((uint32_t) (0x00000080)) 1746 #define FFE0_6_INTR_EN_M4 ((uint32_t) (0x00000040)) 1747 #define FFE0_5_INTR_EN_M4 ((uint32_t) (0x00000020)) 1748 #define FFE0_4_INTR_EN_M4 ((uint32_t) (0x00000010)) 1749 #define FFE0_3_INTR_EN_M4 ((uint32_t) (0x00000008)) 1750 #define FFE0_2_INTR_EN_M4 ((uint32_t) (0x00000004)) 1751 #define FFE0_1_INTR_EN_M4 ((uint32_t) (0x00000002)) 1752 #define FFE0_0_INTR_EN_M4 ((uint32_t) (0x00000001)) 1753 1754 #define FFE1_7_INTR_DETECT ((uint32_t) (0x00000080)) 1755 #define FFE1_6_INTR_DETECT ((uint32_t) (0x00000040)) 1756 #define FFE1_5_INTR_DETECT ((uint32_t) (0x00000020)) 1757 #define FFE1_4_INTR_DETECT ((uint32_t) (0x00000010)) 1758 #define FFE1_3_INTR_DETECT ((uint32_t) (0x00000008)) 1759 #define FFE1_2_INTR_DETECT ((uint32_t) (0x00000004)) 1760 #define FFE1_1_INTR_DETECT ((uint32_t) (0x00000002)) 1761 #define FFE1_0_INTR_DETECT ((uint32_t) (0x00000001)) 1762 1763 #define FFE1_7_INTR_EN_AP ((uint32_t) (0x00000080)) 1764 #define FFE1_6_INTR_EN_AP ((uint32_t) (0x00000040)) 1765 #define FFE1_5_INTR_EN_AP ((uint32_t) (0x00000020)) 1766 #define FFE1_4_INTR_EN_AP ((uint32_t) (0x00000010)) 1767 #define FFE1_3_INTR_EN_AP ((uint32_t) (0x00000008)) 1768 #define FFE1_2_INTR_EN_AP ((uint32_t) (0x00000004)) 1769 #define FFE1_1_INTR_EN_AP ((uint32_t) (0x00000002)) 1770 #define FFE1_0_INTR_EN_AP ((uint32_t) (0x00000001)) 1771 1772 #define FFE1_7_INTR_EN_M4 ((uint32_t) (0x00000080)) 1773 #define FFE1_6_INTR_EN_M4 ((uint32_t) (0x00000040)) 1774 #define FFE1_5_INTR_EN_M4 ((uint32_t) (0x00000020)) 1775 #define FFE1_4_INTR_EN_M4 ((uint32_t) (0x00000010)) 1776 #define FFE1_3_INTR_EN_M4 ((uint32_t) (0x00000008)) 1777 #define FFE1_2_INTR_EN_M4 ((uint32_t) (0x00000004)) 1778 #define FFE1_1_INTR_EN_M4 ((uint32_t) (0x00000002)) 1779 #define FFE1_0_INTR_EN_M4 ((uint32_t) (0x00000001)) 1780 1781 #define FB_3_INTR_DETECT ((uint32_t) (0x00000008)) 1782 #define FB_2_INTR_DETECT ((uint32_t) (0x00000004)) 1783 #define FB_1_INTR_DETECT ((uint32_t) (0x00000002)) 1784 #define FB_0_INTR_DETECT ((uint32_t) (0x00000001)) 1785 1786 #define FB_3_INTR_RAW ((uint32_t) (0x00000008)) 1787 #define FB_2_INTR_RAW ((uint32_t) (0x00000004)) 1788 #define FB_1_INTR_RAW ((uint32_t) (0x00000002)) 1789 #define FB_0_INTR_RAW ((uint32_t) (0x00000001)) 1790 1791 #define FB_3_INTR_TYPE_LEVEL ((uint32_t) (0x00000000)) 1792 #define FB_3_INTR_TYPE_EDGE ((uint32_t) (0x00000008)) 1793 #define FB_2_INTR_TYPE_LEVEL ((uint32_t) (0x00000000)) 1794 #define FB_2_INTR_TYPE_EDGE ((uint32_t) (0x00000004)) 1795 #define FB_1_INTR_TYPE_LEVEL ((uint32_t) (0x00000000)) 1796 #define FB_1_INTR_TYPE_EDGE ((uint32_t) (0x00000002)) 1797 #define FB_0_INTR_TYPE_LEVEL ((uint32_t) (0x00000000)) 1798 #define FB_0_INTR_TYPE_EDGE ((uint32_t) (0x00000001)) 1799 1800 #define FB_3_INTR_POL_LO_FALL ((uint32_t) (0x00000000)) 1801 #define FB_3_INTR_POL_HI_RISE ((uint32_t) (0x00000008)) 1802 #define FB_2_INTR_POL_LO_FALL ((uint32_t) (0x00000000)) 1803 #define FB_2_INTR_POL_HI_RISE ((uint32_t) (0x00000004)) 1804 #define FB_1_INTR_POL_LO_FALL ((uint32_t) (0x00000000)) 1805 #define FB_1_INTR_POL_HI_RISE ((uint32_t) (0x00000002)) 1806 #define FB_0_INTR_POL_LO_FALL ((uint32_t) (0x00000000)) 1807 #define FB_0_INTR_POL_HI_RISE ((uint32_t) (0x00000001)) 1808 1809 #define FB_3_INTR_EN_AP ((uint32_t) (0x00000008)) 1810 #define FB_2_INTR_EN_AP ((uint32_t) (0x00000004)) 1811 #define FB_1_INTR_EN_AP ((uint32_t) (0x00000002)) 1812 #define FB_0_INTR_EN_AP ((uint32_t) (0x00000001)) 1813 1814 #define FB_3_INTR_EN_M4 ((uint32_t) (0x00000008)) 1815 #define FB_2_INTR_EN_M4 ((uint32_t) (0x00000004)) 1816 #define FB_1_INTR_EN_M4 ((uint32_t) (0x00000002)) 1817 #define FB_0_INTR_EN_M4 ((uint32_t) (0x00000001)) 1818 1819 /****************************************************************************** 1820 * SPI_MS * 1821 ******************************************************************************/ 1822 1823 #define CTRLR0_DFS_32_4_BIT ((uint32_t) (0x00030000)) 1824 #define CTRLR0_DFS_32_5_BIT ((uint32_t) (0x00040000)) 1825 #define CTRLR0_DFS_32_6_BIT ((uint32_t) (0x00050000)) 1826 #define CTRLR0_DFS_32_7_BIT ((uint32_t) (0x00060000)) 1827 #define CTRLR0_DFS_32_8_BIT ((uint32_t) (0x00070000)) 1828 #define CTRLR0_DFS_32_9_BIT ((uint32_t) (0x00080000)) 1829 #define CTRLR0_DFS_32_10_BIT ((uint32_t) (0x00090000)) 1830 #define CTRLR0_DFS_32_11_BIT ((uint32_t) (0x000A0000)) 1831 #define CTRLR0_DFS_32_12_BIT ((uint32_t) (0x000B0000)) 1832 #define CTRLR0_DFS_32_13_BIT ((uint32_t) (0x000C0000)) 1833 #define CTRLR0_DFS_32_14_BIT ((uint32_t) (0x000D0000)) 1834 #define CTRLR0_DFS_32_15_BIT ((uint32_t) (0x000E0000)) 1835 #define CTRLR0_DFS_32_16_BIT ((uint32_t) (0x000F0000)) 1836 #define CTRLR0_CFS_1_BIT ((uint32_t) (0x00000000)) 1837 #define CTRLR0_CFS_2_BIT ((uint32_t) (0x00001000)) 1838 #define CTRLR0_CFS_3_BIT ((uint32_t) (0x00002000)) 1839 #define CTRLR0_CFS_4_BIT ((uint32_t) (0x00003000)) 1840 #define CTRLR0_CFS_5_BIT ((uint32_t) (0x00004000)) 1841 #define CTRLR0_CFS_6_BIT ((uint32_t) (0x00005000)) 1842 #define CTRLR0_CFS_7_BIT ((uint32_t) (0x00006000)) 1843 #define CTRLR0_CFS_8_BIT ((uint32_t) (0x00007000)) 1844 #define CTRLR0_CFS_9_BIT ((uint32_t) (0x00008000)) 1845 #define CTRLR0_CFS_10_BIT ((uint32_t) (0x00009000)) 1846 #define CTRLR0_CFS_11_BIT ((uint32_t) (0x0000A000)) 1847 #define CTRLR0_CFS_12_BIT ((uint32_t) (0x0000B000)) 1848 #define CTRLR0_CFS_13_BIT ((uint32_t) (0x0000C000)) 1849 #define CTRLR0_CFS_14_BIT ((uint32_t) (0x0000D000)) 1850 #define CTRLR0_CFS_15_BIT ((uint32_t) (0x0000E000)) 1851 #define CTRLR0_CFS_16_BIT ((uint32_t) (0x0000F000)) 1852 #define CTRLR0_SRL_TEST_MODE ((uint32_t) (0x00000800)) 1853 #define CTRLR0_SRL_NORMAL_MODE ((uint32_t) (0x00000000)) 1854 #define CTRLR0_SLV_OE ((uint32_t) (0x00000400)) 1855 #define CTRLR0_TMOD_TX_RX ((uint32_t) (0x00000000)) 1856 #define CTRLR0_TMOD_TX ((uint32_t) (0x00000100)) 1857 #define CTRLR0_TMOD_RX ((uint32_t) (0x00000200)) 1858 #define CTRLR0_TMOD_EEPROM ((uint32_t) (0x00000300)) 1859 #define CTRLR0_SCPOL_LO ((uint32_t) (0x00000000)) 1860 #define CTRLR0_SCPOL_HI ((uint32_t) (0x00000080)) 1861 #define CTRLR0_SCPH_MID ((uint32_t) (0x00000000)) 1862 #define CTRLR0_SCPH_START ((uint32_t) (0x00000040)) 1863 #define CTRLR0_DFS_4_BIT ((uint32_t) (0x00000003)) 1864 #define CTRLR0_DFS_5_BIT ((uint32_t) (0x00000004)) 1865 #define CTRLR0_DFS_6_BIT ((uint32_t) (0x00000005)) 1866 #define CTRLR0_DFS_7_BIT ((uint32_t) (0x00000006)) 1867 #define CTRLR0_DFS_8_BIT ((uint32_t) (0x00000007)) 1868 #define CTRLR0_DFS_9_BIT ((uint32_t) (0x00000008)) 1869 #define CTRLR0_DFS_10_BIT ((uint32_t) (0x00000009)) 1870 #define CTRLR0_DFS_11_BIT ((uint32_t) (0x0000000A)) 1871 #define CTRLR0_DFS_12_BIT ((uint32_t) (0x0000000B)) 1872 #define CTRLR0_DFS_13_BIT ((uint32_t) (0x0000000C)) 1873 #define CTRLR0_DFS_14_BIT ((uint32_t) (0x0000000D)) 1874 #define CTRLR0_DFS_15_BIT ((uint32_t) (0x0000000E)) 1875 #define CTRLR0_DFS_16_BIT ((uint32_t) (0x0000000F)) 1876 1877 #define SSIENR_SSI_DISABLE ((uint32_t) (0x00000000)) 1878 #define SSIENR_SSI_EN ((uint32_t) (0x00000001)) 1879 1880 #define SER_SS_0_N_SELECTED ((uint32_t) (0x00000001)) 1881 #define SER_SS_1_N_SELECTED ((uint32_t) (0x00000002)) 1882 #define SER_SS_2_N_SELECTED ((uint32_t) (0x00000004)) 1883 1884 #define SR_DCOL_TX_DATA_ERR ((uint32_t) (0x00000040)) 1885 #define SR_RFF ((uint32_t) (0x00000010)) 1886 #define SR_RFNE ((uint32_t) (0x00000008)) 1887 #define SR_TFE ((uint32_t) (0x00000004)) 1888 #define SR_TFNF ((uint32_t) (0x00000002)) 1889 #define SR_BUSY ((uint32_t) (0x00000001)) 1890 1891 #define IMR_MSTIM_UNMASK ((uint32_t) (0x00000020)) 1892 #define IMR_RXFIM_UNMASK ((uint32_t) (0x00000010)) 1893 #define IMR_RXFOIM_UNMASK ((uint32_t) (0x00000008)) 1894 #define IMR_RXUIM_UNMASK ((uint32_t) (0x00000004)) 1895 #define IMR_TXOIM_UNMASK ((uint32_t) (0x00000002)) 1896 #define IMR_TXEIM_UNMASK ((uint32_t) (0x00000001)) 1897 1898 #define ISR_MSTIM_ACTIVE ((uint32_t) (0x00000020)) 1899 #define ISR_RXFIM_ACTIVE ((uint32_t) (0x00000010)) 1900 #define ISR_RXFOIM_ACTIVE ((uint32_t) (0x00000008)) 1901 #define ISR_RXUIM_ACTIVE ((uint32_t) (0x00000004)) 1902 #define ISR_TXOIM_ACTIVE ((uint32_t) (0x00000002)) 1903 #define ISR_TXEIM_ACTIVE ((uint32_t) (0x00000001)) 1904 1905 #define RISR_MSTIM_ACTIVE ((uint32_t) (0x00000020)) 1906 #define RISR_RXFIM_ACTIVE ((uint32_t) (0x00000010)) 1907 #define RISR_RXFOIM_ACTIVE ((uint32_t) (0x00000008)) 1908 #define RISR_RXUIM_ACTIVE ((uint32_t) (0x00000004)) 1909 #define RISR_TXOIM_ACTIVE ((uint32_t) (0x00000002)) 1910 #define RISR_TXEIM_ACTIVE ((uint32_t) (0x00000002)) 1911 1912 /****************************************************************************** 1913 * I2S * 1914 ******************************************************************************/ 1915 #define IER_IEN ((uint32_t) (0x00000001)) 1916 1917 #define IRER_RXEN ((uint32_t) (0x00000001)) 1918 1919 #define CER_CLKEN ((uint32_t) (0x00000001)) 1920 1921 #define CCR_WSS_16_CYCLES ((uint32_t) (0x00000000)) 1922 #define CCR_WSS_24_CYCLES ((uint32_t) (0x00000008)) 1923 #define CCR_WSS_32_CYCLES ((uint32_t) (0x00000010)) 1924 #define CCR_SCLKG_NO_GATING ((uint32_t) (0x00000000)) 1925 #define CCR_SCLKG_12_GATING ((uint32_t) (0x00000001)) 1926 #define CCR_SCLKG_16_GATING ((uint32_t) (0x00000002)) 1927 #define CCR_SCLKG_20_GATING ((uint32_t) (0x00000003)) 1928 #define CCR_SCLKG_24_GATING ((uint32_t) (0x00000004)) 1929 1930 #define RXFFR_RESET ((uint32_t) (0x00000001)) 1931 1932 #define RER0_RX_CHEN0_ENABLE ((uint32_t) (0x00000001)) 1933 #define RER0_RX_CHEN0_DISABLE ((uint32_t) (0x00000000)) 1934 1935 #define RCR0_WLEN_IGNORE ((uint32_t) (0x00000000)) 1936 #define RCR0_WLEN_12BIT ((uint32_t) (0x00000001)) 1937 #define RCR0_WLEN_16BIT ((uint32_t) (0x00000002)) 1938 1939 #define ISR0_RXFO_VALID ((uint32_t) (0x00000002)) 1940 #define ISR0_RXDA_VALID ((uint32_t) (0x00000001)) 1941 1942 #define IMR0_RXFOM ((uint32_t) (0x00000002)) 1943 #define IMR0_RXDAM ((uint32_t) (0x00000001)) 1944 1945 #define RFCR0_RXCHDT_1BIT ((uint32_t) (0x00000000)) 1946 #define RFCR0_RXCHDT_2BIT ((uint32_t) (0x00000001)) 1947 #define RFCR0_RXCHDT_3BIT ((uint32_t) (0x00000002)) 1948 #define RFCR0_RXCHDT_4BIT ((uint32_t) (0x00000003)) 1949 #define RFCR0_RXCHDT_5BIT ((uint32_t) (0x00000004)) 1950 #define RFCR0_RXCHDT_6BIT ((uint32_t) (0x00000005)) 1951 #define RFCR0_RXCHDT_7BIT ((uint32_t) (0x00000006)) 1952 #define RFCR0_RXCHDT_8BIT ((uint32_t) (0x00000007)) 1953 1954 #define RFF0_RXCHFR_RESET ((uint32_t) (0x00000001)) 1955 1956 #define AUD_P_CTRL_DMA_MUX_SEL ((uint32_t) (0x00000001)) 1957 #define AUD_P_CTRL_MONO_SEL_MONO ((uint32_t) (0x00000002)) 1958 #define AUD_P_CTRL_MONO_SEL_STEREO ((uint32_t) (0x00000000)) 1959 #define AUD_P_CTRL_RIGHT_SEL_RIGHT ((uint32_t) (0x00000004)) 1960 #define AUD_P_CTRL_RIGHT_SEL_LEFT ((uint32_t) (0x00000000)) 1961 #define AUD_P_CTRL_I2S_SEL_I2S ((uint32_t) (0x00000008)) 1962 #define AUD_P_CTRL_I2S_SEL_PDM ((uint32_t) (0x00000000)) 1963 1964 #define AUD_P_INTR_FIFO_OVERFLOW ((uint32_t) (0x00000001)) 1965 #define AUD_P_INTR_RX_OVERRUN ((uint32_t) (0x00000002)) 1966 #define AUD_P_INTR_RX_DATA_AVALIABLE ((uint32_t) (0x00000004)) 1967 1968 #define AUD_P_INTR_MASK_FIFO_OVERFLOW_MASK ((uint32_t) (0x00000001)) 1969 #define AUD_P_INTR_MASK_RX_OVERRUN_MASK ((uint32_t) (0x00000002)) 1970 #define AUD_P_INTR_MASK_RX_DATA_AVALIABLE_MASK ((uint32_t) (0x00000004)) 1971 1972 /****************************************************************************** 1973 * AUD * 1974 ******************************************************************************/ 1975 #define AUD_H_CTRL_DMA_START ((uint32_t) (0x00000001)) 1976 #define AUD_H_CTRL_DMA_STOP ((uint32_t) (0x00000002)) 1977 #define AUD_H_CTRL_LS_ENABLE ((uint32_t) (0x00000004)) 1978 #define AUD_H_CTRL_POWER_REQ_DISABLE ((uint32_t) (0x00000008)) 1979 #define AUD_H_CTRL_AHB_ADDR_CYC ((uint32_t) (0x00000010)) 1980 #define AUD_H_CTRL_AHB_ADDR_XFR ((uint32_t) (0x00000020)) 1981 #define AUD_H_CTRL_AHB_DATA_CYC ((uint32_t) (0x00000040)) 1982 #define AUD_H_CTRL_AHB_DATA_XFR ((uint32_t) (0x00000080)) 1983 1984 #define IDLE_CYC_PERIOD_MASK ((uint32_t) (0x0000001F)) 1985 #define AHB_IDLE_PERIOD_MASK ((uint32_t) (0x0000001F)) 1986 #define DMA_BLOCK_SIZE_MASK ((uint32_t) (0x0003FFFC)) 1987 #define DMA_WRAP_SIZE_MASK ((uint32_t) (0x0003FFFC)) 1988 #define DMA_XFER_CNT_MASK ((uint32_t) (0x0003FFFC)) 1989 #define DMA_START_ADDR_MASK ((uint32_t) (0xFFFFFFFC)) 1990 #define DMA_DEST_ADDR_MASK ((uint32_t) (0xFFFFFFFC)) 1991 #define FIFO_SYNC_THRESHOLD_LVL_MASK ((uint32_t) (0x00003FFC)) 1992 1993 #define AHB_FIFO_SYNC_TEST_RM_MASK ((uint32_t) (0x00000003)) 1994 #define AHB_FIFO_SYNC_TEST_RM_RSV_MASK ((uint32_t) (0x0000000C)) 1995 #define AHB_FIFO_SYNC_TEST_RME_MASK ((uint32_t) (0x00000010)) 1996 #define AHB_FIFO_SYNC_TEST_1_MASK ((uint32_t) (0x00000020)) 1997 1998 #define AHB_H_INTR_AUD_POWER_ON_REQ ((uint32_t) (0x00000001)) 1999 #define AHB_H_INTR_AUD_POWER_OFF_REQ ((uint32_t) (0x00000002)) 2000 #define AHB_H_INTR_AUD_BLOCK ((uint32_t) (0x00000004)) 2001 #define AHB_H_INTR_AUD_WRAP ((uint32_t) (0x00000008)) 2002 #define AHB_H_INTR_FIFO_SYNC_UNDERFLOW ((uint32_t) (0x00000010)) 2003 #define AHB_H_INTR_FIFO_SYNC_OVERFLOW ((uint32_t) (0x00000020)) 2004 #define AHB_H_INTR_FIFO_ASYNC_UNDERFLOW ((uint32_t) (0x00000040)) 2005 #define AHB_H_INTR_DEEP_SLEEP_ERROR ((uint32_t) (0x00000080)) 2006 #define AHB_H_INTR_HERROR ((uint32_t) (0x00000100)) 2007 2008 #define AHB_H_INTR_MASK_AUD_POWER_ON_REQ ((uint32_t) (0x00000001)) 2009 #define AHB_H_INTR_MASK_AUD_POWER_OFF_REQ ((uint32_t) (0x00000002)) 2010 #define AHB_H_INTR_MASK_AUD_BLOCK ((uint32_t) (0x00000004)) 2011 #define AHB_H_INTR_MASK_AUD_WRAP ((uint32_t) (0x00000008)) 2012 #define AHB_H_INTR_MASK_FIFO_SYNC_UNDERFLOW ((uint32_t) (0x00000010)) 2013 #define AHB_H_INTR_MASK_FIFO_SYNC_OVERFLOW ((uint32_t) (0x00000020)) 2014 #define AHB_H_INTR_MASK_FIFO_ASYNC_UNDERFLOW ((uint32_t) (0x00000040)) 2015 #define AHB_H_INTR_MASK_DEEP_SLEEP_ERROR ((uint32_t) (0x00000080)) 2016 #define AHB_H_INTR_MASK_HERROR ((uint32_t) (0x00000100)) 2017 2018 #define DMA_WRAP_SIZE_MASK_MASK ((uint32_t) (0x0003FFFC)) 2019 #define DS_WAKEUP_DLY_MASK ((uint32_t) (0x0000000F)) 2020 2021 2022 /****************************************************************************** 2023 * PMU * 2024 ******************************************************************************/ 2025 #define PMU_WIC_CONTROL_ENABLE ((uint32_t) (0x00000001)) 2026 2027 #define PMU_MISC_SW_WU_A1_WU ((uint32_t) (0x00000040)) 2028 #define PMU_MISC_SW_WU_I2S_WU ((uint32_t) (0x00000020)) 2029 #define PMU_MISC_SW_WU_RES_WU ((uint32_t) (0x00000010)) 2030 #define PMU_MISC_SW_WU_DBG_WU ((uint32_t) (0x00000008)) 2031 #define PMU_MISC_SW_WU_EFUSE_WU ((uint32_t) (0x00000004)) 2032 #define PMU_MISC_SW_WU_TM_WU ((uint32_t) (0x00000002)) 2033 #define PMU_MISC_SW_WU_SDMA_WU ((uint32_t) (0x00000001)) 2034 2035 #define PMU_FFE_PD_SRC_MASK_N ((uint32_t) (0x00000001)) 2036 #define PMU_FFE_WU_SRC_MASK_N ((uint32_t) (0x00000001)) 2037 2038 #define PMU_FB_PD_SRC_MASK_N ((uint32_t) (0x00000001)) 2039 #define PMU_FB_WU_SRC_SEN_GPIO0_INT ((uint32_t) (0x00000001)) 2040 #define PMU_FB_WU_SRC_SEN_GPIO1_INT ((uint32_t) (0x00000002)) 2041 #define PMU_FB_WU_SRC_SEN_GPIO2_INT ((uint32_t) (0x00000004)) 2042 #define PMU_FB_WU_SRC_SEN_GPIO3_INT ((uint32_t) (0x00000008)) 2043 #define PMU_FB_WU_SRC_SEN_GPIO4_INT ((uint32_t) (0x00000010)) 2044 #define PMU_FB_WU_SRC_SEN_GPIO5_INT ((uint32_t) (0x00000020)) 2045 #define PMU_FB_WU_SRC_SEN_GPIO6_INT ((uint32_t) (0x00000040)) 2046 #define PMU_FB_WU_SRC_SEN_GPIO7_INT ((uint32_t) (0x00000080)) 2047 #define PMU_FB_WU_SRC_FFE_TIMER ((uint32_t) (0x00000100)) 2048 2049 #define PMU_FFE_FB_PF_SW_WU_PF_WU ((uint32_t) (0x00000004)) 2050 #define PMU_FFE_FB_PF_SW_WU_FB_WU ((uint32_t) (0x00000002)) 2051 #define PMU_FFE_FB_PF_SW_WU_FFE_WU ((uint32_t) (0x00000001)) 2052 2053 #define PMU_M4S0_EVENT_PD ((uint32_t) (0x00000001)) 2054 #define PMU_M4S0_EVENT_WU ((uint32_t) (0x00000001)) 2055 2056 #define PMU_M4S0_SW_PD ((uint32_t) (0x00000001)) 2057 #define PMU_M4S1_SW_PD ((uint32_t) (0x00000002)) 2058 #define PMU_M4S2_SW_PD ((uint32_t) (0x00000004)) 2059 #define PMU_M4S3_SW_PD ((uint32_t) (0x00000008)) 2060 #define PMU_M4S4_SW_PD ((uint32_t) (0x00000010)) 2061 #define PMU_M4S5_SW_PD ((uint32_t) (0x00000020)) 2062 #define PMU_M4S6_SW_PD ((uint32_t) (0x00000040)) 2063 #define PMU_M4S7_SW_PD ((uint32_t) (0x00000080)) 2064 #define PMU_M4S8_SW_PD ((uint32_t) (0x00000100)) 2065 #define PMU_M4S9_SW_PD ((uint32_t) (0x00000200)) 2066 #define PMU_M4S10_SW_PD ((uint32_t) (0x00000400)) 2067 #define PMU_M4S11_SW_PD ((uint32_t) (0x00000800)) 2068 #define PMU_M4S12_SW_PD ((uint32_t) (0x00001000)) 2069 #define PMU_M4S13_SW_PD ((uint32_t) (0x00002000)) 2070 #define PMU_M4S14_SW_PD ((uint32_t) (0x00004000)) 2071 #define PMU_M4S15_SW_PD ((uint32_t) (0x00008000)) 2072 2073 #define PMU_M4S0_SW_WU ((uint32_t) (0x00000001)) 2074 #define PMU_M4S1_SW_WU ((uint32_t) (0x00000002)) 2075 #define PMU_M4S2_SW_WU ((uint32_t) (0x00000004)) 2076 #define PMU_M4S3_SW_WU ((uint32_t) (0x00000008)) 2077 #define PMU_M4S4_SW_WU ((uint32_t) (0x00000010)) 2078 #define PMU_M4S5_SW_WU ((uint32_t) (0x00000020)) 2079 #define PMU_M4S6_SW_WU ((uint32_t) (0x00000040)) 2080 #define PMU_M4S7_SW_WU ((uint32_t) (0x00000080)) 2081 #define PMU_M4S8_SW_WU ((uint32_t) (0x00000100)) 2082 #define PMU_M4S9_SW_WU ((uint32_t) (0x00000200)) 2083 #define PMU_M4S10_SW_WU ((uint32_t) (0x00000400)) 2084 #define PMU_M4S11_SW_WU ((uint32_t) (0x00000800)) 2085 #define PMU_M4S12_SW_WU ((uint32_t) (0x00001000)) 2086 #define PMU_M4S13_SW_WU ((uint32_t) (0x00002000)) 2087 #define PMU_M4S14_SW_WU ((uint32_t) (0x00004000)) 2088 #define PMU_M4S15_SW_WU ((uint32_t) (0x00008000)) 2089 2090 #define PMU_AUDIO0_EVENT_WU ((uint32_t) (0x00000001)) 2091 #define PMU_AUDIO1_EVENT_WU ((uint32_t) (0x00000002)) 2092 #define PMU_AUDIO2_EVENT_WU ((uint32_t) (0x00000004)) 2093 #define PMU_AUDIO3_EVENT_WU ((uint32_t) (0x00000008)) 2094 #define PMU_AUDIO4_EVENT_WU ((uint32_t) (0x00000010)) 2095 #define PMU_AUDIO5_EVENT_WU ((uint32_t) (0x00000020)) 2096 2097 2098 #define PMU_M4_STATUS_WU ((uint32_t) (0x00000001)) 2099 #define PMU_M4_STATUS_PD ((uint32_t) (0x00000004)) 2100 2101 #define PMU_M4_SHUTDOWN_MODE ((uint32_t) (0x00000002)) 2102 #define PMU_M4S0_POWER_MODE ((uint32_t) (0x00000002)) 2103 2104 #define PMU_M4SRAM_LPMF ((uint32_t) (0x00000002)) 2105 #define PMU_M4SRAM_LPMH ((uint32_t) (0x00000002)) 2106 2107 #define PWR_DWN_SCH_M4S0_PD ((uint32_t) (0x00000080)) 2108 #define PWR_DWN_SCH_AUDIO_PD ((uint32_t) (0x00000040)) 2109 #define PWR_DWN_SCH_SRAM_PD ((uint32_t) (0x00000020)) 2110 #define PWR_DWN_SCH_FFEFB_PD ((uint32_t) (0x00000010)) 2111 #define PWR_DWN_SCH_M4M4S0_WU ((uint32_t) (0x00000008)) 2112 #define PWR_DWN_SCH_AUDIO_WU ((uint32_t) (0x00000004)) 2113 #define PWR_DWN_SCH_SRAM_WU ((uint32_t) (0x00000002)) 2114 #define PWR_DWN_SCH_FFEFB_WU ((uint32_t) (0x00000001)) 2115 2116 #define PWR_SDMA_SRAM_PD_CFG ((uint32_t) (0x00040000)) 2117 2118 #define PWR_AUDIO_SRAM_CFG ((uint32_t) (0x00000100)) 2119 2120 #define PWR_AUDIO_SRAM_LC_DS_R2 ((uint32_t) (0x00000004)) 2121 #define PWR_AUDIO_SRAM_LC_DS_R1 ((uint32_t) (0x00000002)) 2122 #define PWR_AUDIO_SRAM_LC_DS_R0 ((uint32_t) (0x00000001)) 2123 2124 #define M4_SRAM0_PD_WU (uint32_t)(0x1) 2125 #define M4_SRAM1_PD_WU (uint32_t)(0x2) 2126 #define M4_SRAM2_PD_WU (uint32_t)(0x4) 2127 #define M4_SRAM3_PD_WU (uint32_t)(0x8) 2128 #define M4_SRAM4_PD_WU (uint32_t)(0x10) 2129 #define M4_SRAM5_PD_WU (uint32_t)(0x20) 2130 #define M4_SRAM6_PD_WU (uint32_t)(0x40) 2131 #define M4_SRAM7_PD_WU (uint32_t)(0x80) 2132 #define M4_SRAM8_PD_WU (uint32_t)(0x100) 2133 #define M4_SRAM9_PD_WU (uint32_t)(0x200) 2134 #define M4_SRAM10_PD_WU (uint32_t)(0x400) 2135 #define M4_SRAM11_PD_WU (uint32_t)(0x800) 2136 #define M4_SRAM12_PD_WU (uint32_t)(0x1000) 2137 #define M4_SRAM13_PD_WU (uint32_t)(0x2000) 2138 #define M4_SRAM14_PD_WU (uint32_t)(0x4000) 2139 #define M4_SRAM15_PD_WU (uint32_t)(0x8000) 2140 2141 2142 #define SDMA_SW_PD_WU (uint32_t)(0x1) 2143 #define EFUSE_SW_PD_WU (uint32_t)(0x2) 2144 #define I2S_SW_PD_WU (uint32_t)(0x20) 2145 #define A1_SW_PD_WU (uint32_t)(0x40) 2146 2147 #define AUDIO_AD0_PD_WU (uint32_t)(0x1) 2148 #define AUDIO_AD1_PD_WU (uint32_t)(0x2) 2149 #define AUDIO_AD2_PD_WU (uint32_t)(0x4) 2150 #define AUDIO_AD3_PD_WU (uint32_t)(0x8) 2151 #define AUDIO_AD4_PD_WU (uint32_t)(0x10) 2152 #define AUDIO_AD5_PD_WU (uint32_t)(0x20) 2153 2154 2155 /****************************************************************************** 2156 * MISC * 2157 ******************************************************************************/ 2158 #define MISC_LOCK_KEY ((uint32_t)(0x1ACCE551)) 2159 2160 /****************************************************************************** 2161 * SDMA_SRAM * 2162 ******************************************************************************/ 2163 #define SDMA_SRAM_DST_INC_BYTE ((uint32_t) (0x00000000)) 2164 #define SDMA_SRAM_DST_INC_HWORD ((uint32_t) (0x40000000)) 2165 #define SDMA_SRAM_DST_INC_WORD ((uint32_t) (0x80000000)) 2166 #define SDMA_SRAM_DST_SZ_BYTE ((uint32_t) (0x00000000)) 2167 #define SDMA_SRAM_DST_SZ_HWORD ((uint32_t) (0x10000000)) 2168 #define SDMA_SRAM_DST_SZ_WORD ((uint32_t) (0x20000000)) 2169 2170 #define SDMA_SRAM_SRC_INC_BYTE ((uint32_t) (0x00000000)) 2171 #define SDMA_SRAM_SRC_INC_HWORD ((uint32_t) (0x04000000)) 2172 #define SDMA_SRAM_SRC_INC_WORD ((uint32_t) (0x08000000)) 2173 #define SDMA_SRAM_SRC_SZ_BYTE ((uint32_t) (0x00000000)) 2174 #define SDMA_SRAM_SRC_SZ_HWORD ((uint32_t) (0x01000000)) 2175 #define SDMA_SRAM_SRC_SZ_WORD ((uint32_t) (0x02000000)) 2176 2177 #define SDMA_SRAM_CH_CFG_DST_CACHABLE ((uint32_t) (0x00800000)) 2178 #define SDMA_SRAM_CH_CFG_DST_BUFFABLE ((uint32_t) (0x00400000)) 2179 #define SDMA_SRAM_CH_CFG_DST_PRIVILEGED ((uint32_t) (0x00200000)) 2180 2181 #define SDMA_SRAM_CH_CFG_SRC_CACHABLE ((uint32_t) (0x00100000)) 2182 #define SDMA_SRAM_CH_CFG_SRC_BUFFABLE ((uint32_t) (0x00080000)) 2183 #define SDMA_SRAM_CH_CFG_SRC_PRIVILEGED ((uint32_t) (0x00040000)) 2184 2185 #define SDMA_SRAM_R_POWER_0 ((uint32_t) (0x00000000)) 2186 #define SDMA_SRAM_R_POWER_2 ((uint32_t) (0x00004000)) 2187 #define SDMA_SRAM_R_POWER_4 ((uint32_t) (0x00008000)) 2188 #define SDMA_SRAM_R_POWER_8 ((uint32_t) (0x0000C000)) 2189 #define SDMA_SRAM_R_POWER_16 ((uint32_t) (0x00010000)) 2190 #define SDMA_SRAM_R_POWER_32 ((uint32_t) (0x00014000)) 2191 #define SDMA_SRAM_R_POWER_64 ((uint32_t) (0x00018000)) 2192 #define SDMA_SRAM_R_POWER_128 ((uint32_t) (0x0001C000)) 2193 #define SDMA_SRAM_R_POWER_256 ((uint32_t) (0x00020000)) 2194 #define SDMA_SRAM_R_POWER_512 ((uint32_t) (0x00024000)) 2195 #define SDMA_SRAM_R_POWER_NO ((uint32_t) (0x0003C000)) 2196 2197 #define SDMA_SRAM_N_MINUS_1_SHIFT ((uint32_t) 4) 2198 #define SDMA_SRAM_NEXT_USEBURST ((uint32_t) (0x00000008)) 2199 2200 #define SDMA_SRAM_CYCLE_CTRL_STOP ((uint32_t) (0x00000000)) 2201 #define SDMA_SRAM_CYCLE_CTRL_BASIC ((uint32_t) (0x00000001)) 2202 #define SDMA_SRAM_CYCLE_CTRL_AUTO_REQUEST ((uint32_t) (0x00000002)) 2203 #define SDMA_SRAM_CYCLE_CTRL_PING_PONG ((uint32_t) (0x00000003)) 2204 #define SDMA_SRAM_CYCLE_CTRL_PRI_SCATTER ((uint32_t) (0x00000004)) 2205 #define SDMA_SRAM_CYCLE_CTRL_ALT_SCATTER ((uint32_t) (0x00000005)) 2206 #define SDMA_SRAM_CYCLE_CTRL_PERI_SCATTER ((uint32_t) (0x00000006)) 2207 #define SDMA_SRAM_CYCLE_CTRL_ALT_PERI_SCATTER ((uint32_t) (0x00000007)) 2208 2209 #define SDMA_SRAM_CH0 (0) 2210 #define SDMA_SRAM_CH1 (1) 2211 #define SDMA_SRAM_CH2 (2) 2212 #define SDMA_SRAM_CH3 (3) 2213 #define SDMA_SRAM_CH4 (4) 2214 #define SDMA_SRAM_CH5 (5) 2215 #define SDMA_SRAM_CH6 (6) 2216 #define SDMA_SRAM_CH7 (7) 2217 #define SDMA_SRAM_CH8 (8) 2218 #define SDMA_SRAM_CH9 (9) 2219 #define SDMA_SRAM_CH10 (10) 2220 #define SDMA_SRAM_CH11 (11) 2221 #define SDMA_SRAM_CH12 (12) 2222 #define SDMA_SRAM_CH13 (13) 2223 #define SDMA_SRAM_CH14 (14) 2224 #define SDMA_SRAM_CH15 (15) 2225 2226 /****************************************************************************** 2227 * SDMA_BRIDGE * 2228 ******************************************************************************/ 2229 #define SDMA_BRIDGE_SINGLE_REQ_SHIFT ((uint32_t) 27) 2230 #define SDMA_BRIDGE_BURST_REQ_SHIFT ((uint32_t) 0) 2231 #define SDMA_BRIDGE_CH1_SELECT ((uint32_t) (1 << 0)) 2232 #define SDMA_BRIDGE_CH2_SELECT ((uint32_t) (1 << 1)) 2233 #define SDMA_BRIDGE_CH3_SELECT ((uint32_t) (1 << 2)) 2234 #define SDMA_BRIDGE_CH4_SELECT ((uint32_t) (1 << 3)) 2235 #define SDMA_BRIDGE_CH5_SELECT ((uint32_t) (1 << 4)) 2236 #define SDMA_BRIDGE_CH6_SELECT ((uint32_t) (1 << 5)) 2237 #define SDMA_BRIDGE_CH7_SELECT ((uint32_t) (1 << 6)) 2238 #define SDMA_BRIDGE_CH8_SELECT ((uint32_t) (1 << 7)) 2239 #define SDMA_BRIDGE_CH9_SELECT ((uint32_t) (1 << 8)) 2240 #define SDMA_BRIDGE_CH10_SELECT ((uint32_t) (1 << 9)) 2241 #define SDMA_BRIDGE_CH11_SELECT ((uint32_t) (1 << 10)) 2242 2243 /****************************************************************************** 2244 * SDMA * 2245 ******************************************************************************/ 2246 #define SDMA_DMA_STATUS_TEST_STATUS_SHIFT ((uint32_t) 28) 2247 #define SDMA_DMA_STATUS_CHNLS_MINUS_1_SHIFT ((uint32_t) 16) 2248 #define SDMA_DMA_STATUS_STATE_MASK ((uint32_t) 0x000000F0) 2249 #define SDMA_DMA_STATUS_IDLE_STATE ((uint32_t) 0x00000000) 2250 #define SDMA_DMA_STATUS_RD_CH_CTRL_DATA_STATE ((uint32_t) 0x00000010) 2251 #define SDMA_DMA_STATUS_RD_SRC_DATA_PTR_STATE ((uint32_t) 0x00000020) 2252 #define SDMA_DMA_STATUS_RD_DEST_DATA_PTR_STATE ((uint32_t) 0x00000030) 2253 #define SDMA_DMA_STATUS_RD_SRC_DATA_STATE ((uint32_t) 0x00000040) 2254 #define SDMA_DMA_STATUS_WR_DEST_DATA_STATE ((uint32_t) 0x00000050) 2255 #define SDMA_DMA_STATUS_WAIT_DMA_STATE ((uint32_t) 0x00000060) 2256 #define SDMA_DMA_STATUS_WR_CH_CTRL_DATA_STATE ((uint32_t) 0x00000070) 2257 #define SDMA_DMA_STATUS_STALLED_STATE ((uint32_t) 0x00000080) 2258 #define SDMA_DMA_STATUS_DONE_STATE ((uint32_t) 0x00000090) 2259 #define SDMA_DMA_STATUS_SCATTER_GATHER_STATE ((uint32_t) 0x000000A0) 2260 #define SDMA_DMA_STATUS_MASTER_ENABLE ((uint32_t) 0x00000001) 2261 2262 #define SDMA_DMA_CFG_HPROT3_SET ((uint32_t) 0x00000080) 2263 #define SDMA_DMA_CFG_HPROT2_SET ((uint32_t) 0x00000040) 2264 #define SDMA_DMA_CFG_HPROT1_SET ((uint32_t) 0x00000020) 2265 #define SDMA_DMA_CFG_MASTER_ENABLE ((uint32_t) 0x00000001) 2266 2267 #define SDMA_DMA_CH0_SELECT ((uint32_t) (1 << 0)) 2268 #define SDMA_DMA_CH1_SELECT ((uint32_t) (1 << 1)) 2269 #define SDMA_DMA_CH2_SELECT ((uint32_t) (1 << 2)) 2270 #define SDMA_DMA_CH3_SELECT ((uint32_t) (1 << 3)) 2271 #define SDMA_DMA_CH4_SELECT ((uint32_t) (1 << 4)) 2272 #define SDMA_DMA_CH5_SELECT ((uint32_t) (1 << 5)) 2273 #define SDMA_DMA_CH6_SELECT ((uint32_t) (1 << 6)) 2274 #define SDMA_DMA_CH7_SELECT ((uint32_t) (1 << 7)) 2275 #define SDMA_DMA_CH8_SELECT ((uint32_t) (1 << 8)) 2276 #define SDMA_DMA_CH9_SELECT ((uint32_t) (1 << 9)) 2277 #define SDMA_DMA_CH10_SELECT ((uint32_t) (1 << 10)) 2278 #define SDMA_DMA_CH11_SELECT ((uint32_t) (1 << 11)) 2279 #define SDMA_DMA_CH12_SELECT ((uint32_t) (1 << 12)) 2280 #define SDMA_DMA_CH13_SELECT ((uint32_t) (1 << 13)) 2281 #define SDMA_DMA_CH14_SELECT ((uint32_t) (1 << 14)) 2282 #define SDMA_DMA_CH15_SELECT ((uint32_t) (1 << 15)) 2283 2284 /****************************************************************************** 2285 * AIP * 2286 ******************************************************************************/ 2287 #define AIP_OSC_CTRL_EN ((uint32_t) (0x00000001)) 2288 #define AIP_OSC_CTRL_FRE_SEL ((uint32_t) (0x00000002)) 2289 2290 /****************************************************************************** 2291 * CRU * 2292 ******************************************************************************/ 2293 #define CLK_CTRL_CLK_DIVIDER_ENABLE ((uint32_t) (0x00000200)) 2294 #define CLK_CTRL_CLK_DIVIDER_RATIO_2 ((uint32_t) (0x00000000)) 2295 #define CLK_CTRL_CLK_DIVIDER_RATIO_3 ((uint32_t) (0x00000001)) 2296 #define CLK_CTRL_CLK_DIVIDER_RATIO_4 ((uint32_t) (0x00000002)) 2297 #define CLK_CTRL_CLK_DIVIDER_RATIO_5 ((uint32_t) (0x00000003)) 2298 #define CLK_CTRL_CLK_DIVIDER_RATIO_6 ((uint32_t) (0x00000004)) 2299 #define CLK_CTRL_CLK_DIVIDER_RATIO_7 ((uint32_t) (0x00000005)) 2300 #define CLK_CTRL_CLK_DIVIDER_RATIO_8 ((uint32_t) (0x00000006)) 2301 #define CLK_CTRL_CLK_DIVIDER_RATIO_9 ((uint32_t) (0x00000007)) 2302 #define CLK_CTRL_CLK_DIVIDER_RATIO_10 ((uint32_t) (0x00000008)) 2303 #define CLK_CTRL_CLK_DIVIDER_RATIO_11 ((uint32_t) (0x00000009)) 2304 #define CLK_CTRL_CLK_DIVIDER_RATIO_12 ((uint32_t) (0x0000000A)) 2305 #define CLK_CTRL_CLK_DIVIDER_RATIO_13 ((uint32_t) (0x0000000B)) 2306 #define CLK_CTRL_CLK_DIVIDER_RATIO_14 ((uint32_t) (0x0000000C)) 2307 #define CLK_CTRL_CLK_DIVIDER_RATIO_15 ((uint32_t) (0x0000000D)) 2308 #define CLK_CTRL_CLK_DIVIDER_RATIO_16 ((uint32_t) (0x0000000E)) 2309 2310 #define CLK_CTRL_A_CLK_SOURCE_SEL_HSPEED ((uint32_t) (0x00000000)) 2311 #define CLK_CTRL_A_CLK_SOURCE_SEL_32KHZ ((uint32_t) (0x00000001)) 2312 #define CLK_CTRL_B_CLK_SOURCE_SEL_HSPEED ((uint32_t) (0x00000000)) 2313 #define CLK_CTRL_B_CLK_SOURCE_SEL_32KHZ ((uint32_t) (0x00000001)) 2314 #define CLK_CTRL_E_CLK_SOURCE_SEL_HSPEED ((uint32_t) (0x00000000)) 2315 #define CLK_CTRL_E_CLK_SOURCE_SEL_32KHZ ((uint32_t) (0x00000001)) 2316 #define CLK_CTRL_F_CLK_SOURCE_SEL_HSPEED ((uint32_t) (0x00000000)) 2317 #define CLK_CTRL_F_CLK_SOURCE_SEL_32KHZ ((uint32_t) (0x00000001)) 2318 #define CLK_CTRL_H_CLK_SOURCE_SEL_HSPEED ((uint32_t) (0x00000000)) 2319 #define CLK_CTRL_H_CLK_SOURCE_SEL_32KHZ ((uint32_t) (0x00000001)) 2320 #define CLK_CTRL_I_CLK_SOURCE_SEL_HSPEED ((uint32_t) (0x00000000)) 2321 #define CLK_CTRL_I_CLK_SOURCE_SEL_32KHZ ((uint32_t) (0x00000001)) 2322 2323 #define HSPEED_CLK_SOURCE_SEL_FROM_OSC ((uint32_t) (0x00000000)) 2324 #define HSPEED_CLK_SOURCE_SEL_FROM_PAD ((uint32_t) (0x00000001)) 2325 2326 #define C01_CLK_GATE_PATH_0_OFF ((uint32_t) (0x00000000)) 2327 #define C01_CLK_GATE_PATH_0_ON ((uint32_t) (0x00000001)) 2328 #define C01_CLK_GATE_PATH_1_OFF ((uint32_t) (0x00000000)) 2329 #define C01_CLK_GATE_PATH_1_ON ((uint32_t) (0x00000002)) 2330 #define C01_CLK_GATE_PATH_2_OFF ((uint32_t) (0x00000000)) 2331 #define C01_CLK_GATE_PATH_2_ON ((uint32_t) (0x00000004)) 2332 #define C01_CLK_GATE_PATH_3_OFF ((uint32_t) (0x00000000)) 2333 #define C01_CLK_GATE_PATH_3_ON ((uint32_t) (0x00000008)) 2334 #define C01_CLK_GATE_PATH_4_OFF ((uint32_t) (0x00000000)) 2335 #define C01_CLK_GATE_PATH_4_ON ((uint32_t) (0x00000010)) 2336 #define C01_CLK_GATE_PATH_5_OFF ((uint32_t) (0x00000000)) 2337 #define C01_CLK_GATE_PATH_5_ON ((uint32_t) (0x00000020)) 2338 #define C01_CLK_GATE_PATH_6_OFF ((uint32_t) (0x00000000)) 2339 #define C01_CLK_GATE_PATH_6_ON ((uint32_t) (0x00000040)) 2340 #define C01_CLK_GATE_PATH_7_OFF ((uint32_t) (0x00000000)) 2341 #define C01_CLK_GATE_PATH_7_ON ((uint32_t) (0x00000080)) 2342 #define C01_CLK_GATE_PATH_8_OFF ((uint32_t) (0x00000000)) 2343 #define C01_CLK_GATE_PATH_8_ON ((uint32_t) (0x00000100)) 2344 #define C01_CLK_GATE_PATH_9_OFF ((uint32_t) (0x00000000)) 2345 #define C01_CLK_GATE_PATH_9_ON ((uint32_t) (0x00000200)) 2346 2347 #define C02_CLK_GATE_PATH_0_OFF ((uint32_t) (0x00000000)) 2348 #define C02_CLK_GATE_PATH_0_ON ((uint32_t) (0x00000001)) 2349 #define C02_CLK_GATE_PATH_1_OFF ((uint32_t) (0x00000000)) 2350 #define C02_CLK_GATE_PATH_1_ON ((uint32_t) (0x00000002)) 2351 #define C02_CLK_GATE_PATH_2_OFF ((uint32_t) (0x00000000)) 2352 #define C02_CLK_GATE_PATH_2_ON ((uint32_t) (0x00000004)) 2353 #define C02_CLK_GATE_PATH_3_OFF ((uint32_t) (0x00000000)) 2354 #define C02_CLK_GATE_PATH_3_ON ((uint32_t) (0x00000008)) 2355 #define C02_CLK_GATE_PATH_4_OFF ((uint32_t) (0x00000000)) 2356 #define C02_CLK_GATE_PATH_4_ON ((uint32_t) (0x00000010)) 2357 #define C02_CLK_GATE_PATH_5_OFF ((uint32_t) (0x00000000)) 2358 #define C02_CLK_GATE_PATH_5_ON ((uint32_t) (0x00000020)) 2359 2360 #define C08_X4_CLK_GATE_PATH_0_OFF ((uint32_t) (0x00000000)) 2361 #define C08_X4_CLK_GATE_PATH_0_ON ((uint32_t) (0x00000001)) 2362 2363 #define C08_X1_CLK_GATE_PATH_0_OFF ((uint32_t) (0x00000000)) 2364 #define C08_X1_CLK_GATE_PATH_0_ON ((uint32_t) (0x00000001)) 2365 #define C08_X1_CLK_GATE_PATH_1_OFF ((uint32_t) (0x00000000)) 2366 #define C08_X1_CLK_GATE_PATH_1_ON ((uint32_t) (0x00000002)) 2367 #define C08_X1_CLK_GATE_PATH_2_OFF ((uint32_t) (0x00000000)) 2368 #define C08_X1_CLK_GATE_PATH_2_ON ((uint32_t) (0x00000004)) 2369 #define C08_X1_CLK_GATE_PATH_3_OFF ((uint32_t) (0x00000000)) 2370 #define C08_X1_CLK_GATE_PATH_3_ON ((uint32_t) (0x00000008)) 2371 #define C08_X1_CLK_GATE_PATH_4_OFF ((uint32_t) (0x00000000)) 2372 #define C08_X1_CLK_GATE_PATH_4_ON ((uint32_t) (0x00000010)) 2373 #define C08_X1_CLK_GATE_PATH_5_OFF ((uint32_t) (0x00000000)) 2374 #define C08_X1_CLK_GATE_PATH_5_ON ((uint32_t) (0x00000020)) 2375 #define C08_X1_CLK_GATE_PATH_6_OFF ((uint32_t) (0x00000000)) 2376 #define C08_X1_CLK_GATE_PATH_6_ON ((uint32_t) (0x00000040)) 2377 2378 #define C10_FCLK_GATE_PATH_0_OFF ((uint32_t) (0x00000000)) 2379 #define C10_FCLK_GATE_PATH_0_ON ((uint32_t) (0x00000001)) 2380 #define C10_FCLK_GATE_PATH_1_OFF ((uint32_t) (0x00000000)) 2381 #define C10_FCLK_GATE_PATH_1_ON ((uint32_t) (0x00000002)) 2382 #define C10_FCLK_GATE_PATH_2_OFF ((uint32_t) (0x00000000)) 2383 #define C10_FCLK_GATE_PATH_2_ON ((uint32_t) (0x00000004)) 2384 #define C10_FCLK_GATE_PATH_3_OFF ((uint32_t) (0x00000000)) 2385 #define C10_FCLK_GATE_PATH_3_ON ((uint32_t) (0x00000008)) 2386 #define C10_FCLK_GATE_PATH_4_OFF ((uint32_t) (0x00000000)) 2387 #define C10_FCLK_GATE_PATH_4_ON ((uint32_t) (0x00000010)) 2388 #define C10_FCLK_GATE_PATH_5_OFF ((uint32_t) (0x00000000)) 2389 #define C10_FCLK_GATE_PATH_5_ON ((uint32_t) (0x00000020)) 2390 #define C10_FCLK_GATE_PATH_6_OFF ((uint32_t) (0x00000000)) 2391 #define C10_FCLK_GATE_PATH_6_ON ((uint32_t) (0x00000040)) 2392 2393 #define C11_CLK_GATE_PATH_0_OFF ((uint32_t) (0x00000000)) 2394 #define C11_CLK_GATE_PATH_0_ON ((uint32_t) (0x00000001)) 2395 #define C11_CLK_GATE_PATH_1_OFF ((uint32_t) (0x00000000)) 2396 #define C11_CLK_GATE_PATH_1_ON ((uint32_t) (0x00000002)) 2397 #define C11_CLK_GATE_PATH_2_OFF ((uint32_t) (0x00000000)) 2398 #define C11_CLK_GATE_PATH_2_ON ((uint32_t) (0x00000004)) 2399 #define C11_CLK_GATE_PATH_3_OFF ((uint32_t) (0x00000000)) 2400 #define C11_CLK_GATE_PATH_3_ON ((uint32_t) (0x00000008)) 2401 #define C11_CLK_GATE_PATH_4_OFF ((uint32_t) (0x00000000)) 2402 #define C11_CLK_GATE_PATH_4_ON ((uint32_t) (0x00000010)) 2403 #define C11_CLK_GATE_PATH_5_OFF ((uint32_t) (0x00000000)) 2404 #define C11_CLK_GATE_PATH_5_ON ((uint32_t) (0x00000020)) 2405 2406 #define C12_CLK_GATE_PATH_0_OFF ((uint32_t) (0x00000000)) 2407 #define C12_CLK_GATE_PATH_0_ON ((uint32_t) (0x00000001)) 2408 #define C12_CLK_GATE_PATH_1_OFF ((uint32_t) (0x00000000)) 2409 #define C12_CLK_GATE_PATH_1_ON ((uint32_t) (0x00000002)) 2410 2411 #define CS_CLK_GATE_PATH_0_OFF ((uint32_t) (0x00000000)) 2412 #define CS_CLK_GATE_PATH_0_ON ((uint32_t) (0x00000001)) 2413 2414 #define CU_CLK_GATE_PATH_0_OFF ((uint32_t) (0x00000000)) 2415 #define CU_CLK_GATE_PATH_0_ON ((uint32_t) (0x00000001)) 2416 #define CU_CLK_GATE_PATH_1_OFF ((uint32_t) (0x00000000)) 2417 #define CU_CLK_GATE_PATH_1_ON ((uint32_t) (0x00000002)) 2418 2419 #define C16_CLK_GATE_PATH_0_OFF ((uint32_t) (0x00000000)) 2420 #define C16_CLK_GATE_PATH_0_ON ((uint32_t) (0x00000001)) 2421 #define C18_CLK_GATE_PATH_0_OFF ((uint32_t) (0x00000000)) 2422 #define C18_CLK_GATE_PATH_0_ON ((uint32_t) (0x00000001)) 2423 #define C19_CLK_GATE_PATH_0_OFF ((uint32_t) (0x00000000)) 2424 #define C19_CLK_GATE_PATH_0_ON ((uint32_t) (0x00000001)) 2425 #define C21_CLK_GATE_PATH_0_OFF ((uint32_t) (0x00000000)) 2426 #define C21_CLK_GATE_PATH_0_ON ((uint32_t) (0x00000001)) 2427 2428 #define C22_CLK_CTRL_GATE_CTRL_OFF ((uint32_t) (0x00000000)) 2429 #define C22_CLK_CTRL_GATE_CTRL_ON ((uint32_t) (0x00000001)) 2430 #define C22_CLK_CTRL_SOURCE_SEL_I2S ((uint32_t) (0x00000000)) 2431 #define C22_CLK_CTRL_SOURCE_SEL_PDM ((uint32_t) (0x00000002)) 2432 2433 #define FB_C21_DOMAIN_SW_RESET ((uint32_t) (0x00000020)) 2434 #define FB_C16_DOMAIN_SW_RESET ((uint32_t) (0x00000010)) 2435 #define FB_C09_DOMAIN_SW_RESET ((uint32_t) (0x00000004)) 2436 #define FB_C02_DOMAIN_SW_RESET ((uint32_t) (0x00000001)) 2437 2438 #define C09_CLK_GATE_PATH_0_OFF ((uint32_t) (0x00000000)) 2439 #define C09_CLK_GATE_PATH_0_ON ((uint32_t) (0x00000001)) 2440 #define C09_CLK_GATE_PATH_1_OFF ((uint32_t) (0x00000000)) 2441 #define C09_CLK_GATE_PATH_1_ON ((uint32_t) (0x00000002)) 2442 #define C09_CLK_GATE_PATH_2_OFF ((uint32_t) (0x00000000)) 2443 #define C09_CLK_GATE_PATH_2_ON ((uint32_t) (0x00000004)) 2444 2445 #define C30C31_CLK_CTRL_SOURCE_PDM_LEFT ((uint32_t) (0x00000001)) 2446 #define C30C31_CLK_CTRL_SOURCE_PDM_RIGHT ((uint32_t) (0x00000002)) 2447 2448 #define CLK_DIVIDER_A_CG ((uint32_t) (0x00000001)) 2449 #define CLK_DIVIDER_B_CG ((uint32_t) (0x00000002)) 2450 #define CLK_DIVIDER_C_CG ((uint32_t) (0x00000004)) 2451 #define CLK_DIVIDER_D_CG ((uint32_t) (0x00000008)) 2452 #define CLK_DIVIDER_F_CG ((uint32_t) (0x00000020)) 2453 #define CLK_DIVIDER_G_CG ((uint32_t) (0x00000040)) 2454 #define CLK_DIVIDER_H_CG ((uint32_t) (0x00000080)) 2455 #define CLK_DIVIDER_I_CG ((uint32_t) (0x00000100)) 2456 #define CLK_DIVIDER_J_CG ((uint32_t) (0x00000200)) 2457 2458 /// @endcond EOSS3_DEV_MACROS 2459 2460 #define REBOOT_CAUSE_HARDFAULT (0x1) 2461 #define REBOOT_CAUSE_FLASHING (0x2) 2462 #define REBOOT_CAUSE_SOFTFAULT (0x3) 2463 #define REBOOT_CAUSE (0xF) 2464 #define REBOOT_STATUS_REG (PMU->MISC_POR_3) 2465 2466 #ifdef __cplusplus 2467 } 2468 #endif /* __cplusplus */ 2469 2470 #endif /* __EOSS3_DEV_H */ 2471 2472
