1 /*
2 * Copyright (c) 2016, Freescale Semiconductor, Inc.
3 * Copyright 2016-2017, 2021 NXP
4 * All rights reserved.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8 #ifndef FSL_PMC0_H_
9 #define FSL_PMC0_H_
10
11 #include "fsl_common.h"
12
13 /*! @addtogroup pmc0 */
14 /*! @{ */
15
16 /*! @file */
17
18 /*******************************************************************************
19 * Definitions
20 ******************************************************************************/
21
22 /* Component ID definition, used by tools. */
23 #ifndef FSL_COMPONENT_ID
24 #define FSL_COMPONENT_ID "platform.drivers.pmc0"
25 #endif
26
27 /*! @name Driver version */
28 /*! @{ */
29 /*! @brief PMC 0 driver version */
30 #define FSL_PMC0_DRIVER_VERSION (MAKE_VERSION(2, 1, 1)
31 /*! @} */
32
33 /*!
34 * @brief MAX valid values of Core Regulator Voltage Level
35 */
36 #define CORE_REGULATOR_VOLT_LEVEL_MAX 50U
37
38 /*!
39 * @brief High Voltage Detect Monitor Select
40 */
41 typedef enum _pmc0_high_volt_detect_monitor_select
42 {
43 kPMC0_HighVoltDetectLowPowerMonitor = 0U, /*!< LP monitor is selected. */
44 kPMC0_HighVoltDetectHighPowerMonitor = 1U /*!< HP monitor is selected. */
45 } pmc0_high_volt_detect_monitor_select_t;
46
47 /*!
48 * @brief Low Voltage Detect Monitor Select
49 */
50 typedef enum _pmc0_low_volt_detect_monitor_select
51 {
52 kPMC0_LowVoltDetectLowPowerMonitor = 0U, /*!< LP monitor is selected. */
53 kPMC0_LowVoltDetectHighPowerMonitor = 1U /*!< HP monitor is selected. */
54 } pmc0_low_volt_detect_monitor_select_t;
55
56 /*!
57 * @brief Core Regulator Select
58 */
59 typedef enum _pmc0_core_regulator_select
60 {
61 kPMC0_CoreLowPowerRegulator = 0U, /*!< Core LP regulator is selected. */
62 kPMC0_CoreHighPowerRegulator = 1U /*!< Core HP regulator is selected. */
63 } pmc0_core_regulator_select_t;
64
65 /*!
66 * @brief Array Regulator Select
67 */
68 typedef enum _pmc0_array_regulator_select
69 {
70 kPMC0_ArrayLowPowerRegulator = 0U, /*!< Array LP regulator is selected. */
71 kPMC0_ArrayHighPowerRegulator = 1U /*!< Array HP regulator is selected. */
72 } pmc0_array_regulator_select_t;
73
74 /*!
75 * @brief VLLS mode array Regulator Select
76 */
77 typedef enum _pmc0_vlls_array_regulator_select
78 {
79 kPMC0_VllsArrayRegulatorOff = 0U, /*!< Array regulator is selected OFF. This is selectable only for VLLS mode. */
80 kPMC0_VllsArrayLowPowerRegulator = 2U, /*!< Array LP regulator is selected. */
81 kPMC0_VllsArrayHighPowerRegulator = 3U /*!< Array HP regulator is selected. */
82 } pmc0_vlls_array_regulator_select_t;
83
84 /*!
85 * @brief FBB P-Well voltage level select
86 */
87 typedef enum _pmc0_fbb_p_well_voltage_level_select
88 {
89 kPMC0_FbbPWellNoBiasCondition = 0U, /*!< No BIAS condition is selected. */
90 kPMC0_FbbPWellVoltageLevelAt50Mv = 1U, /*!< Voltage level at 50mV is selected. */
91 kPMC0_FbbPWellVoltageLevelAt150Mv = 2U, /*!< Voltage level at 150mV is selected. */
92 kPMC0_FbbPWellVoltageLevelAt100Mv = 3U, /*!< Voltage level at 100mV is selected. */
93 kPMC0_FbbPWellVoltageLevelAt350Mv = 4U, /*!< Voltage level at 350mV is selected. */
94 kPMC0_FbbPWellVoltageLevelAt300Mv = 5U, /*!< Voltage level at 300mV is selected. */
95 kPMC0_FbbPWellVoltageLevelAt200Mv = 6U, /*!< Voltage level at 200mV is selected. */
96 kPMC0_FbbPWellVoltageLevelAt250Mv = 7U, /*!< Voltage level at 250mV is selected. */
97 } pmc0_fbb_p_well_voltage_level_select_t;
98
99 /*!
100 * @brief FBB N-Well voltage level select
101 */
102 typedef enum _pmc0_fbb_n_well_voltage_level_select
103 {
104 kPMC0_FbbNWellNoBiasCondition = 0U, /*!< No BIAS condition is selected. */
105 kPMC0_FbbNWellVoltageLevelAtMinus50Mv = 1U, /*!< Voltage level at -50mV is selected. */
106 kPMC0_FbbNWellVoltageLevelAtMinus150Mv = 2U, /*!< Voltage level at -150mV is selected. */
107 kPMC0_FbbNWellVoltageLevelAtMinus100Mv = 3U, /*!< Voltage level at -100mV is selected. */
108 kPMC0_FbbNWellVoltageLevelAtMinus350Mv = 4U, /*!< Voltage level at -350mV is selected. */
109 kPMC0_FbbNWellVoltageLevelAtMinus300Mv = 5U, /*!< Voltage level at -300mV is selected. */
110 kPMC0_FbbNWellVoltageLevelAtMinus200Mv = 6U, /*!< Voltage level at -200mV is selected. */
111 kPMC0_FbbNWellVoltageLevelAtMinus250Mv = 7U, /*!< Voltage level at -250mV is selected. */
112 } pmc0_fbb_n_well_voltage_level_select_t;
113
114 /*!
115 * @brief RBB P-Well voltage level select
116 */
117 typedef enum _pmc0_rbb_p_well_voltage_level_select
118 {
119 kPMC0_RBBPWellVoltageLevelAtMinus0_5V = 0U, /*!< Voltage level at -0.5V is selected. */
120 kPMC0_RBBPWellVoltageLevelAtMinus0_6V = 1U, /*!< Voltage level at -0.6V is selected. */
121 kPMC0_RBBPWellVoltageLevelAtMinus0_7V = 2U, /*!< Voltage level at -0.7V is selected. */
122 kPMC0_RBBPWellVoltageLevelAtMinus0_8V = 3U, /*!< Voltage level at -0.8V is selected. */
123 kPMC0_RBBPWellVoltageLevelAtMinus0_9V = 4U, /*!< Voltage level at -0.9V is selected. */
124 kPMC0_RBBPWellVoltageLevelAtMinus1_0V = 5U, /*!< Voltage level at -1.0V is selected. */
125 kPMC0_RBBPWellVoltageLevelAtMinus1_1V = 6U, /*!< Voltage level at -1.1V is selected. */
126 kPMC0_RBBPWellVoltageLevelAtMinus1_2V = 7U, /*!< Voltage level at -1.2V is selected. */
127 kPMC0_RBBPWellVoltageLevelAtMinus1_3V = 8U, /*!< Voltage level at -1.3V is selected. */
128 } pmc0_rbb_p_well_voltage_level_select_t;
129
130 /*!
131 * @brief RBB N-Well voltage level select
132 */
133 typedef enum _pmc0_rbb_n_well_voltage_level_select
134 {
135 kPMC0_RBBNWellVoltageLevelAt0_5V = 0U, /*!< Voltage level at 0.5V is selected. */
136 kPMC0_RBBNWellVoltageLevelAt0_6V = 1U, /*!< Voltage level at 0.6V is selected. */
137 kPMC0_RBBNWellVoltageLevelAt0_7V = 2U, /*!< Voltage level at 0.7V is selected. */
138 kPMC0_RBBNWellVoltageLevelAt0_8V = 3U, /*!< Voltage level at 0.8V is selected. */
139 kPMC0_RBBNWellVoltageLevelAt0_9V = 4U, /*!< Voltage level at 0.9V is selected. */
140 kPMC0_RBBNWellVoltageLevelAt1_0V = 5U, /*!< Voltage level at 1.0V is selected. */
141 kPMC0_RBBNWellVoltageLevelAt1_1V = 6U, /*!< Voltage level at 1.1V is selected. */
142 kPMC0_RBBNWellVoltageLevelAt1_2V = 7U, /*!< Voltage level at 1.2V is selected. */
143 kPMC0_RBBNWellVoltageLevelAt1_3V = 8U, /*!< Voltage level at 1.3V is selected. */
144 } pmc0_rbb_n_well_voltage_level_select_t;
145
146 /*!
147 * @brief PMC 0 status flags
148 */
149 enum _pmc0_status_flags
150 {
151 kPMC0_LowVoltDetectEventFlag =
152 PMC0_STATUS_LVDF_MASK, /*!< 1.2V Low-Voltage Detector Flag, sets when low-voltage event was detected. */
153 kPMC0_LowVoltDetectValueFlag = PMC0_STATUS_LVDV_MASK, /*!< 1.2V Low-Voltage Detector Value, sets when current
154 value of the 1.2V LVD monitor output is 1. */
155 kPMC0_HighVoltDetectEventFlag =
156 PMC0_STATUS_HVDF_MASK, /*!< 1.8V High-Voltage Detector Flag, sets when high-voltage event was detected. */
157 kPMC0_HighVoltDetectValueFlag = PMC0_STATUS_HVDV_MASK, /*!< 1.8V High-Voltage Detector Value, sets when current
158 value of the 1.8V HVD monitor output is 1. */
159 kPMC0_CoreRegulatorVoltLevelFlag = PMC0_STATUS_COREVLF_MASK, /*!< Core Regulator Voltage Level Flag, sets when core
160 regulator voltage level is changing (not stable). */
161 kPMC0_SramFlag =
162 PMC0_STATUS_SRAMF_MASK, /*!< SRAM Flag, sets when a change mode request is being processed in the SRAMs. */
163 kPMC0_PMC1VoltageSourceFlag =
164 PMC0_STATUS_PMC1VSRC_MASK, /*!< This flag indicates what is the voltage source selected to supply the PMC 1
165 and where the sense point of the PMC 1's LVD/HVD is placed. '0' means internal
166 LDO supplies the PMC 1. '1' means external PMIC supplies the PMC 1. */
167 };
168
169 /*!
170 * @brief PMC 0 power mode status flags.
171 */
172 enum _pmc0_power_mode_status_flags
173 {
174 kPMC0_HSRUNModeStatusFlags = 0U, /*!< The PMC 0 is in HSRUN mode. */
175 kPMC0_RUNModeStatusFlags = 1U, /*!< The PMC 0 is in RUN mode. */
176 kPMC0_STOPModeStatusFlags = 2U, /*!< The PMC 0 is in STOP mode. */
177 kPMC0_VLPRModeStatusFlags = 3U, /*!< The PMC 0 is in VLPR mode. */
178 kPMC0_VLPSModeStatusFlags = 4U, /*!< The PMC 0 is in VLPS mode. */
179 kPMC0_LLSModeStatusFlags = 5U, /*!< The PMC 0 is in LLSM mode. */
180 kPMC0_VLLSModeStatusFlags = 6U, /*!< The PMC 0 is in VLLS mode. */
181 };
182
183 /*!
184 * @brief PMC 0 HSRUN mode configuration.
185 */
186 typedef struct _pmc0_hsrun_mode_config
187 {
188 uint32_t : 16; /*!< Reserved. */
189 uint32_t coreRegulatorVoltLevel : 6; /*!< Core Regulator Voltage Level. */
190 uint32_t : 2; /*!< Reserved. */
191 uint32_t enableForwardBias : 1; /*!< Enable forward bias. */
192 uint32_t : 7; /*!< Reserved. */
193 } pmc0_hsrun_mode_config_t;
194
195 /*!
196 * @brief PMC 0 RUN mode configuration.
197 */
198 typedef struct _pmc0_run_mode_config
199 {
200 uint32_t : 16; /*!< Reserved. */
201 uint32_t coreRegulatorVoltLevel : 6; /*!< Core Regulator Voltage Level. */
202 uint32_t : 10; /*!< Reserved. */
203 } pmc0_run_mode_config_t;
204
205 /*!
206 * @brief PMC 0 VLPR mode configuration.
207 */
208 typedef struct _pmc0_vlpr_mode_config
209 {
210 uint32_t arrayRegulatorSelect : 1; /*!< Array Regulator Select. @ref pmc0_array_regulator_select_t*/
211 uint32_t : 1; /*!< Reserved. */
212 uint32_t coreRegulatorSelect : 1; /*!< Core Regulator Select. @ref pmc0_core_regulator_select_t*/
213 uint32_t : 1; /*!< Reserved. */
214 uint32_t lvdMonitorSelect : 1; /*!< 1.2V LVD Monitor Select. @ref pmc0_low_volt_detect_monitor_select_t */
215 uint32_t hvdMonitorSelect : 1; /*!< 1.2V HVD Monitor Select. @ref pmc0_high_volt_detect_monitor_select_t */
216 uint32_t : 1; /*!< Reserved. */
217 uint32_t enableForceHpBandgap : 1; /*!< Enable force HP band-gap. */
218 uint32_t : 8; /*!< Reserved. */
219 uint32_t coreRegulatorVoltLevel : 6; /*!< Core Regulator Voltage Level. */
220 uint32_t : 6; /*!< Reserved. */
221 uint32_t enableReverseBackBias : 1; /*!< Enable reverse back bias. */
222 uint32_t : 3; /*!< Reserved. */
223 } pmc0_vlpr_mode_config_t;
224
225 /*!
226 * @brief PMC 0 STOP mode configuration.
227 */
228 typedef struct _pmc0_stop_mode_config
229 {
230 uint32_t : 16; /*!< Reserved. */
231 uint32_t coreRegulatorVoltLevel : 6; /*!< Core Regulator Voltage Level. */
232 uint32_t : 10; /*!< Reserved. */
233 } pmc0_stop_mode_config_t;
234
235 /*!
236 * @brief PMC 0 VLPS mode configuration.
237 */
238 typedef struct _pmc0_vlps_mode_config
239 {
240 uint32_t arrayRegulatorSelect : 1; /*!< Array Regulator Select. @ref pmc0_array_regulator_select_t*/
241 uint32_t : 1; /*!< Reserved. */
242 uint32_t coreRegulatorSelect : 1; /*!< Core Regulator Select. @ref pmc0_core_regulator_select_t*/
243 uint32_t : 1; /*!< Reserved. */
244 uint32_t lvdMonitorSelect : 1; /*!< 1.2V LVD Monitor Select. @ref pmc0_low_volt_detect_monitor_select_t */
245 uint32_t hvdMonitorSelect : 1; /*!< 1.2V HVD Monitor Select. @ref pmc0_high_volt_detect_monitor_select_t */
246 uint32_t : 1; /*!< Reserved. */
247 uint32_t enableForceHpBandgap : 1; /*!< Enable force HP band-gap. */
248 uint32_t : 8; /*!< Reserved. */
249 uint32_t coreRegulatorVoltLevel : 6; /*!< Core Regulator Voltage Level. */
250 uint32_t : 6; /*!< Reserved. */
251 uint32_t enableReverseBackBias : 1; /*!< Enable reverse back bias. */
252 uint32_t : 3; /*!< Reserved. */
253 } pmc0_vlps_mode_config_t;
254
255 /*!
256 * @brief PMC 0 LLS mode configuration.
257 */
258 typedef struct _pmc0_lls_mode_config
259 {
260 uint32_t arrayRegulatorSelect : 1; /*!< Array Regulator Select. @ref pmc0_array_regulator_select_t*/
261 uint32_t : 1; /*!< Reserved. */
262 uint32_t coreRegulatorSelect : 1; /*!< Core Regulator Select. @ref pmc0_core_regulator_select_t*/
263 uint32_t : 1; /*!< Reserved. */
264 uint32_t lvdMonitorSelect : 1; /*!< 1.2V LVD Monitor Select. @ref pmc0_low_volt_detect_monitor_select_t */
265 uint32_t hvdMonitorSelect : 1; /*!< 1.2V HVD Monitor Select. @ref pmc0_high_volt_detect_monitor_select_t */
266 uint32_t : 1; /*!< Reserved. */
267 uint32_t enableForceHpBandgap : 1; /*!< Enable force HP band-gap. */
268 uint32_t : 8; /*!< Reserved. */
269 uint32_t coreRegulatorVoltLevel : 6; /*!< Core Regulator Voltage Level. */
270 uint32_t : 6; /*!< Reserved. */
271 uint32_t enableReverseBackBias : 1; /*!< Enable reverse back bias. */
272 uint32_t : 3; /*!< Reserved. */
273 } pmc0_lls_mode_config_t;
274
275 /*!
276 * @brief PMC 0 VLLS mode configuration.
277 */
278 typedef struct _pmc0_vlls_mode_config
279 {
280 uint32_t arrayRegulatorSelect : 2; /*!< Array Regulator Select. @ref pmc0_vlls_array_regulator_select_t */
281 uint32_t : 2; /*!< Reserved. */
282 uint32_t lvdMonitorSelect : 1; /*!< 1.2V LVD Monitor Select. @ref pmc0_low_volt_detect_monitor_select_t */
283 uint32_t hvdMonitorSelect : 1; /*!< 1.2V HVD Monitor Select. @ref pmc0_high_volt_detect_monitor_select_t */
284 uint32_t : 1; /*!< Reserved. */
285 uint32_t enableForceHpBandgap : 1; /*!< Enable force HP band-gap. */
286 uint32_t : 24; /*!< Reserved. */
287 } pmc0_vlls_mode_config_t;
288
289 /*!
290 * @brief PMC 0 bias configuration.
291 */
292 typedef struct _pmc0_bias_config
293 {
294 uint32_t RBBNWellVoltageLevelSelect : 4;
295 uint32_t : 4; /*!< Reserved. */
296 uint32_t RBBPWellVoltageLevelSelect : 4; /*!< Select PMC0 RBB P-Well voltage level. @ref
297 pmc0_rbb_p_well_voltage_level_select_t */
298 uint32_t : 3; /*!< Reserved. */
299 uint32_t DisableRBBPullDown : 1; /*!< Disable RBB pull-down. '1' means to disable pull-down. '0' means to enable
300 pull-down.*/
301 uint32_t FBBNWellVoltageLevelSelect : 4; /*!< Select PMC0 FBB N-Well voltage level. @ref
302 pmc0_fbb_n_well_voltage_level_select_t */
303 uint32_t : 4; /*!< Reserved. */
304 uint32_t FBBPWellVoltageLevelSelect : 4; /*!< Select PMC0 FBB P-Well voltage level. @ref
305 pmc0_fbb_p_well_voltage_level_select_t */
306 uint32_t : 4; /*!< Reserved. */
307 } pmc0_bias_config_t;
308
309 /*******************************************************************************
310 * API
311 ******************************************************************************/
312
313 #if defined(__cplusplus)
314 extern "C" {
315 #endif /* __cplusplus*/
316
317 /*! @name Power Management Controller Control APIs*/
318 /*! @{ */
319
320 /*!
321 * @brief Configure the HSRUN power mode.
322 *
323 * This function configures the HSRUN power mode, including the core regulator
324 * voltage Level setting, enable forward bias or not.
325 *
326 * @param config Low-Voltage detect configuration structure.
327 */
PMC0_ConfigureHsrunMode(const pmc0_hsrun_mode_config_t * config)328 static inline void PMC0_ConfigureHsrunMode(const pmc0_hsrun_mode_config_t *config)
329 {
330 /*
331 * The valid values of Core Regulator Voltage Level are between 0 and 50.
332 * These values correspond to a valid range of 0.596V to 1.138V with resolution of 10.83mV.
333 * The reset value correspond to 0.9V.
334 */
335 assert(config);
336 assert(config->coreRegulatorVoltLevel <= CORE_REGULATOR_VOLT_LEVEL_MAX);
337
338 /* Wait until COREVLF is cleared. */
339 while ((PMC0->STATUS & PMC0_STATUS_COREVLF_MASK) == PMC0_STATUS_COREVLF_MASK)
340 {
341 }
342
343 PMC0->HSRUN = (*((const uint32_t *)((const void *)config))) & (PMC0_HSRUN_COREREGVL_MASK | PMC0_HSRUN_FBBEN_MASK);
344
345 /* Wait until COREVLF is cleared. */
346 while ((PMC0->STATUS & PMC0_STATUS_COREVLF_MASK) == PMC0_STATUS_COREVLF_MASK)
347 {
348 }
349 }
350
351 /*!
352 * @brief Configure the RUN power mode.
353 *
354 * This function configures the RUN power mode, including the core regulator
355 * voltage Level setting.
356 *
357 * @param config Low-Voltage detect configuration structure.
358 */
PMC0_ConfigureRunMode(const pmc0_run_mode_config_t * config)359 static inline void PMC0_ConfigureRunMode(const pmc0_run_mode_config_t *config)
360 {
361 /*
362 * The valid values of Core Regulator Voltage Level are between 0 and 50.
363 * These values correspond to a valid range of 0.596V to 1.138V with resolution of 10.83mV.
364 * The reset value correspond to 0.9V.
365 */
366 assert(config);
367 assert(config->coreRegulatorVoltLevel <= CORE_REGULATOR_VOLT_LEVEL_MAX);
368
369 /* Wait until COREVLF is cleared. */
370 while ((PMC0->STATUS & PMC0_STATUS_COREVLF_MASK) == PMC0_STATUS_COREVLF_MASK)
371 {
372 }
373
374 PMC0->RUN = (*((const uint32_t *)((const void *)config))) & PMC0_RUN_COREREGVL_MASK;
375
376 /* Wait until COREVLF is cleared. */
377 while ((PMC0->STATUS & PMC0_STATUS_COREVLF_MASK) == PMC0_STATUS_COREVLF_MASK)
378 {
379 }
380 }
381
382 /*!
383 * @brief Configure the VLPR power mode.
384 *
385 * This function configures the VLPR power mode, including the core regulator
386 * voltage Level setting, enable reverse back bias or not, turn on force HP
387 * band-gap or not, select of HVD/LVD monitor and select of core/array regulator.
388 *
389 * @param config Low-Voltage detect configuration structure.
390 */
PMC0_ConfigureVlprMode(const pmc0_vlpr_mode_config_t * config)391 static inline void PMC0_ConfigureVlprMode(const pmc0_vlpr_mode_config_t *config)
392 {
393 /*
394 * The valid values of Core Regulator Voltage Level are between 0 and 50.
395 * These values correspond to a valid range of 0.596V to 1.138V with resolution of 10.83mV.
396 * The reset value correspond to 0.704V.
397 */
398 assert(config);
399 assert(config->coreRegulatorVoltLevel <= CORE_REGULATOR_VOLT_LEVEL_MAX);
400
401 PMC0->VLPR = (*((const uint32_t *)((const void *)config))) &
402 (PMC0_VLPR_ARRAYREG_MASK | PMC0_VLPR_COREREG_MASK | PMC0_VLPR_MONLVD_MASK | PMC0_VLPR_MONLVD_MASK |
403 PMC0_VLPR_FBGHP_MASK | PMC0_VLPR_COREREGVL_MASK | PMC0_VLPR_RBBEN_MASK);
404 }
405
406 /*!
407 * @brief Configure the STOP power mode.
408 *
409 * This function configures the STOP power mode, including the core regulator
410 * voltage Level setting.
411 *
412 * @param config Low-Voltage detect configuration structure.
413 */
PMC0_ConfigureStopMode(const pmc0_stop_mode_config_t * config)414 static inline void PMC0_ConfigureStopMode(const pmc0_stop_mode_config_t *config)
415 {
416 /*
417 * The valid values of Core Regulator Voltage Level are between 0 and 50.
418 * These values correspond to a valid range of 0.596V to 1.138V with resolution of 10.83mV.
419 * The reset value correspond to 0.9V.
420 */
421 assert(config);
422 assert(config->coreRegulatorVoltLevel <= CORE_REGULATOR_VOLT_LEVEL_MAX);
423
424 PMC0->STOP = (*((const uint32_t *)((const void *)config))) & PMC0_STOP_COREREGVL_MASK;
425 }
426
427 /*!
428 * @brief Configure the VLPS power mode.
429 *
430 * This function configures the VLPS power mode, including the core regulator
431 * voltage Level setting, enable reverse back bias or not, turn on force HP
432 * band-gap or not, select of HVD/LVD monitor and select of core/array regulator.
433 *
434 * @param config Low-Voltage detect configuration structure.
435 */
PMC0_ConfigureVlpsMode(const pmc0_vlps_mode_config_t * config)436 static inline void PMC0_ConfigureVlpsMode(const pmc0_vlps_mode_config_t *config)
437 {
438 /*
439 * The valid values of Core Regulator Voltage Level are between 0 and 50.
440 * These values correspond to a valid range of 0.596V to 1.138V with resolution of 10.83mV.
441 * The reset value correspond to 0.704V.
442 */
443 assert(config);
444 assert(config->coreRegulatorVoltLevel <= CORE_REGULATOR_VOLT_LEVEL_MAX);
445
446 PMC0->VLPS = (*((const uint32_t *)((const void *)config))) &
447 (PMC0_VLPS_ARRAYREG_MASK | PMC0_VLPS_COREREG_MASK | PMC0_VLPS_MONLVD_MASK | PMC0_VLPS_MONLVD_MASK |
448 PMC0_VLPS_FBGHP_MASK | PMC0_VLPS_COREREGVL_MASK | PMC0_VLPS_RBBEN_MASK);
449 }
450
451 /*!
452 * @brief Configure the LLS power mode.
453 *
454 * This function configures the LLS power mode, including the core regulator
455 * voltage Level setting, enable reverse back bias or not, turn on force HP
456 * band-gap or not, select of HVD/LVD monitor and select of core/array regulator.
457 *
458 * @param config Low-Voltage detect configuration structure.
459 */
PMC0_ConfigureLlsMode(const pmc0_lls_mode_config_t * config)460 static inline void PMC0_ConfigureLlsMode(const pmc0_lls_mode_config_t *config)
461 {
462 /*
463 * The valid values of Core Regulator Voltage Level are between 0 and 50.
464 * These values correspond to a valid range of 0.596V to 1.138V with resolution of 10.83mV.
465 * The reset value correspond to 0.704V.
466 */
467 assert(config);
468 assert(config->coreRegulatorVoltLevel <= CORE_REGULATOR_VOLT_LEVEL_MAX);
469
470 PMC0->LLS = (*((const uint32_t *)((const void *)config))) &
471 (PMC0_LLS_ARRAYREG_MASK | PMC0_LLS_COREREG_MASK | PMC0_LLS_MONLVD_MASK | PMC0_LLS_MONLVD_MASK |
472 PMC0_LLS_FBGHP_MASK | PMC0_LLS_COREREGVL_MASK | PMC0_LLS_RBBEN_MASK);
473 }
474
475 /*!
476 * @brief Configure the VLLS power mode.
477 *
478 * This function configures the VLLS power mode, including turn on force HP
479 * band-gap or not, select of HVD/LVD monitor and select of core/array regulator.
480 *
481 * The select of array regulator is different from the other mode configurations.
482 * PMC 0 VLLS config has three array regulator select options where the others have only the latter two,
483 * see @ref pmc0_vlls_array_regulator_select_t.
484 * Three array regulator select options in PMC 0 VLLS config are shown below:
485 * - Regulator is off (diffrentiator)
486 * - LP Regulator is on
487 * - HP Regulator is on
488 *
489 * @param config Low-Voltage detect configuration structure.
490 */
PMC0_ConfigureVllsMode(const pmc0_vlls_mode_config_t * config)491 static inline void PMC0_ConfigureVllsMode(const pmc0_vlls_mode_config_t *config)
492 {
493 assert(config);
494
495 PMC0->VLLS = (*((const uint32_t *)((const void *)config))) &
496 (PMC0_VLLS_ARRAYREG_MASK | PMC0_VLLS_MONLVD_MASK | PMC0_VLLS_MONLVD_MASK | PMC0_VLLS_FBGHP_MASK);
497 }
498
499 /*!
500 * @brief Get current power mode of PMC 0.
501 *
502 * @code
503 * if(kPMC0_HSRUNModeStatusFlags == PMC0_GetPMC0PowerModeStatusFlags(void))
504 * {
505 * ...
506 * }
507 * @endcode
508 *
509 * @return PMC 0 current power mode status flags in the _pmc0_power_mode_status_flags.
510 *
511 */
PMC0_GetPMC0PowerModeStatusFlags(void)512 static inline uint32_t PMC0_GetPMC0PowerModeStatusFlags(void)
513 {
514 return (PMC0->PM_STAT & PMC0_PM_STAT_PMC0CURRPM_MASK) >> PMC0_PM_STAT_PMC0CURRPM_SHIFT;
515 }
516
517 /*!
518 * @brief Get the status of PMC 0 power mode transition.
519 *
520 * @return If return 'true', which means PMC 0 is in a power mode transition.
521 * If return 'false', which means PMC 0 is not in a power mode transition.
522 */
PMC0_GetPMC0PowerTransitionStatus(void)523 static inline bool PMC0_GetPMC0PowerTransitionStatus(void)
524 {
525 if ((PMC0_PM_STAT_PMC0TRANPM_MASK & PMC0->PM_STAT) == PMC0_PM_STAT_PMC0TRANPM_MASK)
526 {
527 return true;
528 }
529 else
530 {
531 return false;
532 }
533 }
534
535 /*!
536 * @brief Get current power mode of PMC 1.
537 *
538 * @code
539 * if(kPMC0_HSRUNModeStatusFlags == PMC0_GetPMC1PowerModeStatusFlags(void))
540 * {
541 * ...
542 * }
543 * @endcode
544 *
545 * @return PMC 1 current power mode status flags in the _pmc0_power_mode_status_flags.
546 *
547 */
PMC0_GetPMC1PowerModeStatusFlags(void)548 static inline uint32_t PMC0_GetPMC1PowerModeStatusFlags(void)
549 {
550 return (PMC0->PM_STAT & PMC0_PM_STAT_PMC1CURRPM_MASK) >> PMC0_PM_STAT_PMC1CURRPM_SHIFT;
551 }
552
553 /*!
554 * @brief Get the status of PMC 1 power mode transition.
555 *
556 * @return If return 'true', which means PMC 1 is in a power mode transition.
557 * If return 'false', which means PMC 1 is not in a power mode transition.
558 */
PMC0_GetPMC1PowerTransitionStatus(void)559 static inline bool PMC0_GetPMC1PowerTransitionStatus(void)
560 {
561 if ((PMC0_PM_STAT_PMC1TRANPM_MASK & PMC0->PM_STAT) == PMC0_PM_STAT_PMC1TRANPM_MASK)
562 {
563 return true;
564 }
565 else
566 {
567 return false;
568 }
569 }
570
571 /*!
572 * @brief Gets PMC 0 status flags.
573 *
574 * This function gets all PMC 0 status flags. The flags are returned as the logical
575 * OR value of the enumerators @ref _pmc0_status_flags. To check for a specific status,
576 * compare the return value with enumerators in the @ref _pmc0_status_flags.
577 * For example, to check whether core regulator voltage level is changing:
578 * @code
579 * if (kPMC0_CoreRegulatorVoltLevelFlag & PMC0_GetStatusFlags(void))
580 * {
581 * ...
582 * }
583 * @endcode
584 *
585 * @return PMC 0 status flags which are ORed by the enumerators in the _pmc0_status_flags.
586 */
PMC0_GetStatusFlags(void)587 static inline uint32_t PMC0_GetStatusFlags(void)
588 {
589 return PMC0->STATUS;
590 }
591
592 /*!
593 * @brief Enables the 1.2V Low-Voltage Detector interrupt.
594 *
595 * This function enables the 1.2V Low-Voltage Detector interrupt.
596 *
597 */
PMC0_EnableLowVoltDetectInterrupt(void)598 static inline void PMC0_EnableLowVoltDetectInterrupt(void)
599 {
600 PMC0->CTRL |= PMC0_CTRL_LVDIE_MASK;
601 }
602
603 /*!
604 * @brief Disables the 1.2V Low-Voltage Detector interrupt.
605 *
606 * This function disables the 1.2V Low-Voltage Detector interrupt.
607 *
608 */
PMC0_DisableLowVoltDetectInterrupt(void)609 static inline void PMC0_DisableLowVoltDetectInterrupt(void)
610 {
611 PMC0->CTRL &= ~PMC0_CTRL_LVDIE_MASK;
612 }
613
614 /*!
615 * @brief Clears the 1.2V Low-Voltage Detector flag.
616 *
617 * This function enables the 1.2V Low-Voltage Detector flag.
618 *
619 */
PMC0_ClearLowVoltDetectFlag(void)620 static inline void PMC0_ClearLowVoltDetectFlag(void)
621 {
622 PMC0->CTRL |= PMC0_CTRL_LVDACK_MASK;
623 }
624
625 /*!
626 * @brief Enables the 1.8V High-Voltage Detector interrupt.
627 *
628 * This function enables the 1.8V High-Voltage Detector interrupt.
629 *
630 */
PMC0_EnableHighVoltDetectInterrupt(void)631 static inline void PMC0_EnableHighVoltDetectInterrupt(void)
632 {
633 PMC0->CTRL |= PMC0_CTRL_HVDIE_MASK;
634 }
635
636 /*!
637 * @brief Disables the 1.8V High-Voltage Detector interrupt.
638 *
639 * This function disables the 1.8V High-Voltage Detector interrupt.
640 *
641 */
PMC0_DisableHighVoltDetectInterrupt(void)642 static inline void PMC0_DisableHighVoltDetectInterrupt(void)
643 {
644 PMC0->CTRL &= ~PMC0_CTRL_HVDIE_MASK;
645 }
646
647 /*!
648 * @brief Clears the 1.8V High-Voltage Detector flag.
649 *
650 * This function enables the 1.8V High-Voltage Detector flag.
651 *
652 */
PMC0_ClearHighVoltDetectFlag(void)653 static inline void PMC0_ClearHighVoltDetectFlag(void)
654 {
655 PMC0->CTRL |= PMC0_CTRL_HVDACK_MASK;
656 }
657
658 /*!
659 * @brief Enables the 1.2V Low-Voltage Detector reset.
660 *
661 * This function enables 1.2V Low-Voltage Detector reset.
662 *
663 * @param enable Switcher of 1.2V Low-Voltage Detector reset feature. "true" means to enable, "false" means not.
664 */
PMC0_EnableLowVoltDetectReset(bool enable)665 static inline void PMC0_EnableLowVoltDetectReset(bool enable)
666 {
667 if (enable)
668 {
669 PMC0->CTRL |= PMC0_CTRL_LVDRE_MASK;
670 }
671 else
672 {
673 PMC0->CTRL &= ~PMC0_CTRL_LVDRE_MASK;
674 }
675 }
676
677 /*!
678 * @brief Enables the 1.8V High-Voltage Detector reset.
679 *
680 * This function enables 1.8V High-Voltage Detector reset.
681 *
682 * @param enable Switcher of 1.8V High-Voltage Detector reset feature. "true" means to enable, "false" means not.
683 */
PMC0_EnableHighVoltDetectReset(bool enable)684 static inline void PMC0_EnableHighVoltDetectReset(bool enable)
685 {
686 if (enable)
687 {
688 PMC0->CTRL |= PMC0_CTRL_HVDRE_MASK;
689 }
690 else
691 {
692 PMC0->CTRL &= ~PMC0_CTRL_HVDRE_MASK;
693 }
694 }
695
696 /*!
697 * @brief Releases/clears the isolation in the PADS.
698 *
699 * This function releases/clears the isolation in the PADS.
700 *
701 * The isolation in the pads only will be asserted during LLS/VLLS. On LLS exit, the isolation will
702 * release automatically. ISOACK must be set after a VLLS to RUN mode transition has completed.
703 *
704 */
PMC0_ClearPadsIsolation(void)705 static inline void PMC0_ClearPadsIsolation(void)
706 {
707 PMC0->CTRL |= PMC0_CTRL_ISOACK_MASK;
708 }
709
710 /*!
711 * @brief Powers on PMC 1.
712 *
713 * This function powers on PMC 1.
714 *
715 * When this bit field is asserted the PMC 1 is powered on. This bit would take action only once.
716 * This bit will be rearmed after a POR event only.
717 * NOTE: USB PHY-related interrupt (NVIC/GIC) and wake-up channels (AWIC/WKPU) must be disabled before turning PMC1 on.
718 *
719 */
PMC0_PowerOnPmc1(void)720 static inline void PMC0_PowerOnPmc1(void)
721 {
722 PMC0->CTRL |= PMC0_CTRL_PMC1ON_MASK;
723 }
724
725 /*!
726 * @brief Enables to wait LDO OK signal.
727 *
728 * This function enables to wait LDO OK signal.
729 *
730 * @param enable Switcher of wait LDO OK signal feature. "true" means to enable, "false" means not.
731 */
PMC0_EnableWaitLdoOkSignal(bool enable)732 static inline void PMC0_EnableWaitLdoOkSignal(bool enable)
733 {
734 if (enable)
735 {
736 PMC0->CTRL &= ~PMC0_CTRL_LDOOKDIS_MASK;
737 }
738 else
739 {
740 PMC0->CTRL |= PMC0_CTRL_LDOOKDIS_MASK;
741 }
742 }
743
744 /*!
745 * @brief Enables PMC 1 LDO Regulator.
746 *
747 * This function enables PMC 1 LDO Regulator.
748 *
749 * @param enable Switcher of PMC 1 LDO Regulator. "true" means to enable, "false" means not.
750 */
PMC0_EnablePmc1LdoRegulator(bool enable)751 static inline void PMC0_EnablePmc1LdoRegulator(bool enable)
752 {
753 if (enable)
754 {
755 PMC0->CTRL |= PMC0_CTRL_LDOEN_MASK;
756 }
757 else
758 {
759 PMC0->CTRL &= ~PMC0_CTRL_LDOEN_MASK;
760 }
761 }
762
763 /*!
764 * @brief Enable the PMC 1 RBB(reverse back bias) mode.
765 *
766 * This function enables PMC1 RBB mode. Since this circuit when enabled has current consumption.
767 * It is recommended to use it just in high temperatures when the leakage reduction is much higher
768 * than the current consumption.
769 *
770 * @param enable Switcher of PMC1 RBB mode. "true" means to enable, "false" means disable.
771 */
PMC0_EnablePmc1RBBMode(bool enable)772 static inline void PMC0_EnablePmc1RBBMode(bool enable)
773 {
774 if (enable)
775 {
776 PMC0->ACTRL |= PMC0_ACTRL_SWRBBEN_MASK;
777 }
778 else
779 {
780 PMC0->ACTRL &= ~PMC0_ACTRL_SWRBBEN_MASK;
781 }
782 }
783
784 /*!
785 * @brief Configure the PMC 0 bias voltage level and enable/disable pull-down.
786 *
787 * This function change the RBB&FBB voltage level and RBB pull-down.
788 *
789 * @param config PMC 0 bias configuration structure.
790 */
PMC0_SetBiasConfig(const pmc0_bias_config_t * config)791 static inline void PMC0_SetBiasConfig(const pmc0_bias_config_t *config)
792 {
793 assert(NULL != config);
794
795 PMC0->BCTRL = (*((const uint32_t *)((const void *)config))) &
796 (PMC0_BCTRL_RBBNLEVEL_MASK | PMC0_BCTRL_RBBPLEVEL_MASK | PMC0_BCTRL_RBBPDDIS_MASK |
797 PMC0_BCTRL_FBBNLEVEL_MASK | PMC0_BCTRL_FBBPLEVEL_MASK);
798 }
799
800 /*!
801 * @brief Configures PMC 0 SRAM bank power down.
802 *
803 * This function configures PMC 0 SRAM bank power down.
804 *
805 * The bit i controls the power mode of the PMC 0 SRAM bank i.
806 * PMC0_SRAM_PD[i] = 1'b0 - PMC 0 SRAM bank i is not affected.
807 * PMC0_SRAM_PD[i] = 1'b1 - PMC 0 SRAM bank i is in ASD or ARRAY_SHUTDOWN during all modes,
808 * except VLLS. During VLLS is in POWER_DOWN mode.
809 *
810 * Example: Enable band 0 and 1 in ASD or ARRAY_SHUTDOWN during all modes except VLLS
811 * @code
812 * PMC0_ConfigureSramBankPowerDown(0x3U);
813 * @endcode
814 *
815 * @param bankMask The bands to enable. Logical OR of all bits of band index to enbale.
816 */
PMC0_ConfigureSramBankPowerDown(uint32_t bankMask)817 static inline void PMC0_ConfigureSramBankPowerDown(uint32_t bankMask)
818 {
819 /* Wait until SRAMF is cleared. */
820 while ((PMC0->STATUS & PMC0_STATUS_SRAMF_MASK) == PMC0_STATUS_SRAMF_MASK)
821 {
822 }
823
824 PMC0->SRAMCTRL_0 = PMC0_SRAMCTRL_0_SRAM_PD(bankMask);
825
826 /* Wait until SRAMF is cleared. */
827 while ((PMC0->STATUS & PMC0_STATUS_SRAMF_MASK) == PMC0_STATUS_SRAMF_MASK)
828 {
829 }
830 }
831
832 /*!
833 * @brief Configures PMC 0 SRAM bank power down in stop modes.
834 *
835 * This function configures PMC 0 SRAM bank power down in stop modes.
836 *
837 * The bit i controls the PMC 0 SRAM bank i.
838 * PMC0_SRAM_PDS[i] = 1'b0 - PMC 0 SRAM bank i is not affected.
839 * PMC0_SRAM_PDS[i] = 1'b1 - PMC 0 SRAM bank i is in ASD or ARRAY_SHUTDOWN mode during
840 * STOP, VLPS and LLS modes. During VLLS is in POWER_DOWN mode.
841 *
842 * Example: Enable band 0 and 1 in ASD or ARRAY_SHUTDOWN during STOP, VLPS and LLS modes
843 * @code
844 * PMC0_ConfigureSramBankPowerDownStopMode(0x3U);
845 * @endcode
846 *
847 * @param bankMask The bands to enable. Logical OR of all bits of band index to enbale.
848 */
PMC0_ConfigureSramBankPowerDownStopMode(uint32_t bankMask)849 static inline void PMC0_ConfigureSramBankPowerDownStopMode(uint32_t bankMask)
850 {
851 PMC0->SRAMCTRL_1 = PMC0_SRAMCTRL_1_SRAM_PDS(bankMask);
852 }
853
854 /*!
855 * @brief Configures PMC 0 SRAM bank power down in Standby Mode.
856 *
857 * This function configures PMC 0 SRAM bank power down in Standby Mode.
858 *
859 * The bit i controls the PMC 0 SRAM bank i.
860 * PMC0_SRAM_STDY[i] = 1'b0 - PMC 0 SRAM bank i is not affected.
861 * PMC0_SRAM_STDY[i] = 1'b1 - PMC 0 SRAM bank i is in STANDBY mode during all modes (except VLLS and LLS).
862 *
863 * Example: Enable band 0 and 1 in STANDBY mode except VLLS and LLS
864 * @code
865 * PMC0_ConfigureSramBankPowerDownStandbyMode(0x3U);
866 * @endcode
867 *
868 * @param bankMask The bands to enable. Logical OR of all bits of band index to enbale.
869 */
PMC0_ConfigureSramBankPowerDownStandbyMode(uint32_t bankMask)870 static inline void PMC0_ConfigureSramBankPowerDownStandbyMode(uint32_t bankMask)
871 {
872 PMC0->SRAMCTRL_2 = PMC0_SRAMCTRL_2_SRAM_STDY(bankMask);
873 }
874
875 /*!
876 * @brief Enable/disable internal temperature sensor.
877 *
878 * @param enable Used to enable/disable internal temperature sensor.
879 * - \b true Enable internal temperature sensor.
880 * - \b false Disable internal temperature sensor.
881 */
PMC0_EnableTemperatureSensor(bool enable)882 static inline void PMC0_EnableTemperatureSensor(bool enable)
883 {
884 if (enable)
885 {
886 PMC0->ACTRL |= PMC0_ACTRL_TSENSEN_MASK;
887 }
888 else
889 {
890 PMC0->ACTRL &= ~PMC0_ACTRL_TSENSEN_MASK;
891 }
892 }
893
894 /*!
895 * @brief Set temperature sensor mode.
896 *
897 * @param mode The temperature sensor mode to set.
898 */
PMC0_SetTemperatureSensorMode(uint8_t mode)899 static inline void PMC0_SetTemperatureSensorMode(uint8_t mode)
900 {
901 PMC0->ACTRL = (PMC0->ACTRL & ~PMC0_ACTRL_TSENSM_MASK) | PMC0_ACTRL_TSENSM(mode);
902 }
903
904 /*! @} */
905
906 #if defined(__cplusplus)
907 }
908 #endif /* __cplusplus*/
909
910 /*! @}*/
911
912 #endif /* FSL_PMC_H_*/
913
