1 /*
2  * Copyright 2021-2022 NXP
3  * All rights reserved.
4  *
5  * SPDX-License-Identifier: BSD-3-Clause
6  */
7 #ifndef FSL_MCM_H_
8 #define FSL_MCM_H_
9 
10 #include "fsl_common.h"
11 
12 /*!
13  * @addtogroup mcm
14  * @{
15  */
16 
17 /*******************************************************************************
18  * Definitions
19  ******************************************************************************/
20 #define MCM_LMFATR_TYPE_MASK (0x1U)
21 #define MCM_LMFATR_MODE_MASK (0x2U)
22 #define MCM_LMFATR_BUFF_MASK (0x4U)
23 #define MCM_LMFATR_CACH_MASK (0x8U)
24 #define MCM_ISCR_STAT_MASK   (0xFFFFU)
25 #define MCM_ISCR_CPEE_MASK   (0x200000U)
26 
27 /* Component ID definition, used by tools. */
28 #ifndef FSL_COMPONENT_ID
29 #define FSL_COMPONENT_ID "platform.drivers.mcm"
30 #endif
31 
32 /*! @name Driver version */
33 /*! @{ */
34 /*! @brief MCM driver version. */
35 #define FSL_MCM_DRIVER_VERSION (MAKE_VERSION(2, 1, 0))
36 /*! @} */
37 
38 /*! @brief Enum _mcm_interrupt_flag. Interrupt status flag mask.
39  *  @anchor _mcm_interrupt_flag
40  */
41 enum
42 {
43     kMCM_CacheWriteBuffer          = MCM_ISCR_CWBEE_MASK, /*!< Cache Write Buffer Error Enable. */
44     kMCM_ParityError               = MCM_ISCR_CPEE_MASK,  /*!< Cache Parity Error Enable. */
45     kMCM_FPUInvalidOperation       = MCM_ISCR_FIOCE_MASK, /*!< FPU Invalid Operation Interrupt Enable. */
46     kMCM_FPUDivideByZero           = MCM_ISCR_FDZCE_MASK, /*!< FPU Divide-by-zero Interrupt Enable. */
47     kMCM_FPUOverflow               = MCM_ISCR_FOFCE_MASK, /*!< FPU Overflow Interrupt Enable. */
48     kMCM_FPUUnderflow              = MCM_ISCR_FUFCE_MASK, /*!< FPU Underflow Interrupt Enable. */
49     kMCM_FPUInexact                = MCM_ISCR_FIXCE_MASK, /*!< FPU Inexact Interrupt Enable. */
50     kMCM_FPUInputDenormalInterrupt = MCM_ISCR_FIDCE_MASK, /*!< FPU Input Denormal Interrupt Enable. */
51 };
52 
53 /*!
54  * @brief The union of buffer fault attribute.
55  */
56 
57 typedef union _mcm_buffer_fault_attribute
58 {
59     uint32_t attribute; /*!< Indicates the faulting attributes, when a properly-enabled cache write buffer
60                             error interrupt event is detected. */
61     struct _mcm_buffer_fault_attribut
62     {
63         uint32_t busErrorDataAccessType : 1; /*!< Indicates the type of cache write buffer access. */
64         uint32_t busErrorPrivilegeLevel : 1; /*!< Indicates the privilege level of the cache write buffer access. */
65         uint32_t reserved3 : 2;
66         uint32_t busErrorSize : 2; /*!< Indicates the size of the cache write buffer access. */
67         uint32_t reserved2 : 1;
68         uint32_t busErrorAccess : 1;   /*!< Indicates the type of system bus access. */
69         uint32_t busErrorMasterID : 4; /*!< Indicates the crossbar switch bus master number of the captured cache write
70                                           buffer bus error. */
71         uint32_t reserved : 19;
72         uint32_t busErrorOverrun : 1; /*!< Indicates if another cache write buffer bus error is detected. */
73     } attribute_memory;
74 } mcm_buffer_fault_attribute_t;
75 
76 /*!
77  * @brief The union of LMEM fault attribute.
78  */
79 typedef union _mcm_lmem_fault_attribute
80 {
81     uint32_t attribute; /*!< Indicates the attributes of the LMEM fault detected. */
82     struct _mcm_lmem_fault_attribut
83     {
84         uint32_t parityFaultProtectionSignal : 4; /*!< Indicates the features of parity fault protection signal. */
85         uint32_t parityFaultMasterSize : 3;       /*!< Indicates the parity fault master size. */
86         uint32_t parityFaultWrite : 1;            /*!< Indicates the parity fault is caused by read or write. */
87         uint32_t reserved3 : 7;
88         uint32_t
89             backdoorAccess : 1; /*!< Indicates the LMEM access fault is initiated by core access or backdoor access. */
90         uint32_t parityFaultSyndrome : 8; /*!< Indicates the parity fault syndrome. */
91         uint32_t reserved2 : 6;
92         uint32_t reserved : 1;
93         uint32_t overrun : 1; /*!< Indicates the number of faultss. */
94     } attribute_memory;
95 } mcm_lmem_fault_attribute_t;
96 
97 /*****************************************************************************
98  * API
99  ******************************************************************************/
100 
101 #if defined(__cplusplus)
102 extern "C" {
103 #endif
104 
105 /*!
106  * @brief Enables/Disables crossbar round robin.
107  *
108  * @param base MCM peripheral base address.
109  * @param enable Used to enable/disable crossbar round robin.
110  *          - \b true Enable crossbar round robin.
111  *          - \b false disable crossbar round robin.
112  */
MCM_EnableCrossbarRoundRobin(MCM_Type * base,bool enable)113 static inline void MCM_EnableCrossbarRoundRobin(MCM_Type *base, bool enable)
114 {
115     if (enable)
116     {
117         base->CPCR |= MCM_CPCR_CBRR_MASK;
118     }
119     else
120     {
121         base->CPCR &= ~MCM_CPCR_CBRR_MASK;
122     }
123 }
124 
125 /*!
126  * @brief Enables the interrupt.
127  *
128  * @param base MCM peripheral base address.
129  * @param mask Interrupt status flags mask(@ref _mcm_interrupt_flag).
130  */
MCM_EnableInterruptStatus(MCM_Type * base,uint32_t mask)131 static inline void MCM_EnableInterruptStatus(MCM_Type *base, uint32_t mask)
132 {
133     base->ISCR |= mask;
134 }
135 
136 /*!
137  * @brief Disables the interrupt.
138  *
139  * @param base MCM peripheral base address.
140  * @param mask Interrupt status flags mask(@ref _mcm_interrupt_flag).
141  */
MCM_DisableInterruptStatus(MCM_Type * base,uint32_t mask)142 static inline void MCM_DisableInterruptStatus(MCM_Type *base, uint32_t mask)
143 {
144     base->ISCR &= ~mask;
145 }
146 
147 /*!
148  * @brief Gets the Interrupt status .
149  *
150  * @param base MCM peripheral base address.
151  */
MCM_GetInterruptStatus(MCM_Type * base)152 static inline uint16_t MCM_GetInterruptStatus(MCM_Type *base)
153 {
154     return (uint16_t)(base->ISCR &= MCM_ISCR_STAT_MASK);
155 }
156 
157 /*!
158  * @brief Clears the Interrupt status .
159  *
160  * @param base MCM peripheral base address.
161  */
MCM_ClearCacheWriteBufferErroStatus(MCM_Type * base)162 static inline void MCM_ClearCacheWriteBufferErroStatus(MCM_Type *base)
163 {
164     base->ISCR &= ~MCM_ISCR_CWBER_MASK;
165 }
166 
167 /*!
168  * @brief Gets buffer fault address.
169  *
170  * @param base MCM peripheral base address.
171  */
MCM_GetBufferFaultAddress(MCM_Type * base)172 static inline uint32_t MCM_GetBufferFaultAddress(MCM_Type *base)
173 {
174     return base->FADR;
175 }
176 
177 /*!
178  * @brief Gets buffer fault attributes.
179  *
180  * @param base MCM peripheral base address.
181  */
MCM_GetBufferFaultAttribute(MCM_Type * base,mcm_buffer_fault_attribute_t * bufferfault)182 static inline void MCM_GetBufferFaultAttribute(MCM_Type *base, mcm_buffer_fault_attribute_t *bufferfault)
183 {
184     assert(bufferfault != NULL);
185     bufferfault->attribute = base->FATR;
186 }
187 
188 /*!
189  * @brief Gets buffer fault data.
190  *
191  * @param base MCM peripheral base address.
192  */
MCM_GetBufferFaultData(MCM_Type * base)193 static inline uint32_t MCM_GetBufferFaultData(MCM_Type *base)
194 {
195     return base->FDR;
196 }
197 
198 /*!
199  * @brief Limit code cache peripheral write buffering.
200  *
201  * @param base MCM peripheral base address.
202  * @param enable Used to enable/disable limit code cache peripheral write buffering.
203  *          - \b true Enable limit code cache peripheral write buffering.
204  *          - \b false disable limit code cache peripheral write buffering.
205  */
MCM_LimitCodeCachePeripheralWriteBuffering(MCM_Type * base,bool enable)206 static inline void MCM_LimitCodeCachePeripheralWriteBuffering(MCM_Type *base, bool enable)
207 {
208     if (enable)
209     {
210         base->CPCR2 |= MCM_CPCR2_LCCPWB_MASK;
211     }
212     else
213     {
214         base->CPCR2 &= ~MCM_CPCR2_LCCPWB_MASK;
215     }
216 }
217 
218 /*!
219  * @brief Bypass fixed code cache map.
220  *
221  * @param base MCM peripheral base address.
222  * @param enable Used to enable/disable bypass fixed code cache map.
223  *          - \b true Enable bypass fixed code cache map.
224  *          - \b false disable bypass fixed code cache map.
225  */
MCM_BypassFixedCodeCacheMap(MCM_Type * base,bool enable)226 static inline void MCM_BypassFixedCodeCacheMap(MCM_Type *base, bool enable)
227 {
228     if (enable)
229     {
230         base->CPCR2 |= MCM_CPCR2_PCCMCTRL_MASK;
231     }
232     else
233     {
234         base->CPCR2 &= ~MCM_CPCR2_PCCMCTRL_MASK;
235     }
236 }
237 
238 /*!
239  * @brief Enables/Disables code bus cache.
240  *
241  * @param base MCM peripheral base address.
242  * @param enable Used to disable/enable code bus cache.
243  *          - \b true Enable code bus cache.
244  *          - \b false disable code bus cache.
245  */
MCM_EnableCodeBusCache(MCM_Type * base,bool enable)246 static inline void MCM_EnableCodeBusCache(MCM_Type *base, bool enable)
247 {
248     if (enable)
249     {
250         base->CPCR2 &= ~MCM_CPCR2_DCBC_MASK;
251     }
252     else
253     {
254         base->CPCR2 |= MCM_CPCR2_DCBC_MASK;
255     }
256 }
257 
258 /*!
259  * @brief Force code cache to no allocation.
260  *
261  * @param base MCM peripheral base address.
262  * @param enable Used to force code cache to allocation or no allocation.
263  *          - \b true Force code cache to no allocation.
264  *          - \b false Force code cache to allocation.
265  */
MCM_ForceCodeCacheToNoAllocation(MCM_Type * base,bool enable)266 static inline void MCM_ForceCodeCacheToNoAllocation(MCM_Type *base, bool enable)
267 {
268     if (enable)
269     {
270         base->CPCR2 |= MCM_CPCR2_FCCNA_MASK;
271     }
272     else
273     {
274         base->CPCR2 &= ~MCM_CPCR2_FCCNA_MASK;
275     }
276 }
277 
278 /*!
279  * @brief Enables/Disables code cache write buffer.
280  *
281  * @param base MCM peripheral base address.
282  * @param enable Used to enable/disable code cache write buffer.
283  *          - \b true Enable code cache write buffer.
284  *          - \b false Disable code cache write buffer.
285  */
MCM_EnableCodeCacheWriteBuffer(MCM_Type * base,bool enable)286 static inline void MCM_EnableCodeCacheWriteBuffer(MCM_Type *base, bool enable)
287 {
288     if (enable)
289     {
290         base->CPCR2 &= ~MCM_CPCR2_DCCWB_MASK;
291     }
292     else
293     {
294         base->CPCR2 |= MCM_CPCR2_DCCWB_MASK;
295     }
296 }
297 
298 /*!
299  * @brief Clear code bus cache.
300  *
301  * @param base MCM peripheral base address.
302  */
MCM_ClearCodeBusCache(MCM_Type * base)303 static inline void MCM_ClearCodeBusCache(MCM_Type *base)
304 {
305     base->CPCR2 |= MCM_CPCR2_CCBC_MASK;
306 }
307 
308 /*!
309  * @brief Enables/Disables PC Parity Fault Report.
310  *
311  * @param base MCM peripheral base address.
312  * @param enable Used to enable/disable PC Parity Fault Report.
313  *          - \b true Enable PC Parity Fault Report.
314  *          - \b false disable PC Parity Fault Report.
315  */
MCM_EnablePcParityFaultReport(MCM_Type * base,bool enable)316 static inline void MCM_EnablePcParityFaultReport(MCM_Type *base, bool enable)
317 {
318     if (enable)
319     {
320         base->LMDR2 |= MCM_LMDR2_PCPFE_MASK;
321     }
322     else
323     {
324         base->LMDR2 &= ~MCM_LMDR2_PCPFE_MASK;
325     }
326 }
327 
328 /*!
329  * @brief Enables/Disables PC Parity.
330  *
331  * @param base MCM peripheral base address.
332  * @param enable Used to enable/disable PC Parity.
333  *          - \b true Enable PC Parity.
334  *          - \b false disable PC Parity.
335  */
MCM_EnablePcParity(MCM_Type * base,bool enable)336 static inline void MCM_EnablePcParity(MCM_Type *base, bool enable)
337 {
338     if (enable)
339     {
340         base->LMDR2 |= MCM_LMDR2_PCPME_MASK;
341     }
342     else
343     {
344         base->LMDR2 &= ~MCM_LMDR2_PCPME_MASK;
345     }
346 }
347 
348 /*!
349  * @brief Lock the configuration state.
350  *
351  * @param base MCM peripheral base address.
352  */
MCM_LockConfigState(MCM_Type * base)353 static inline void MCM_LockConfigState(MCM_Type *base)
354 {
355     base->LMDR2 |= MCM_LMDR2_RO_MASK;
356 }
357 
358 /*!
359  * @brief Enables/Disables cache parity reporting.
360  *
361  * @param base MCM peripheral base address.
362  * @param enable Used to enable/disable cache parity reporting.
363  *          - \b true Enable cache parity reporting.
364  *          - \b false disable cache parity reporting.
365  */
MCM_EnableCacheParityReporting(MCM_Type * base,bool enable)366 static inline void MCM_EnableCacheParityReporting(MCM_Type *base, bool enable)
367 {
368     if (enable)
369     {
370         base->LMPECR |= MCM_LMPECR_ECPR_MASK;
371     }
372     else
373     {
374         base->LMPECR &= ~MCM_LMPECR_ECPR_MASK;
375     }
376 }
377 
378 /*!
379  * @brief Gets LMEM fault address.
380  *
381  * @param base MCM peripheral base address.
382  */
MCM_GetLmemFaultAddress(MCM_Type * base)383 static inline uint32_t MCM_GetLmemFaultAddress(MCM_Type *base)
384 {
385     return base->LMFAR;
386 }
387 
388 /*!
389  * @brief Get LMEM fault attributes.
390  *
391  * @param base MCM peripheral base address.
392  */
MCM_GetLmemFaultAttribute(MCM_Type * base,mcm_lmem_fault_attribute_t * lmemFault)393 static inline void MCM_GetLmemFaultAttribute(MCM_Type *base, mcm_lmem_fault_attribute_t *lmemFault)
394 {
395     assert(lmemFault != NULL);
396     lmemFault->attribute = base->LMFATR;
397 }
398 
399 /*!
400  * @brief Gets LMEM fault data.
401  *
402  * @param base MCM peripheral base address.
403  */
MCM_GetLmemFaultData(MCM_Type * base)404 static inline uint64_t MCM_GetLmemFaultData(MCM_Type *base)
405 {
406     return ((uint64_t)base->LMFDHR << 32) | base->LMFDLR;
407 }
408 
409 #if defined(__cplusplus)
410 }
411 #endif
412 /*!
413  * @}
414  */
415 #endif /* FSL_MCM_H_ */
416