1 /*
2 * Copyright 2018-2024 NXP
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6 #ifndef FSL_I3C_H_
7 #define FSL_I3C_H_
8
9 #include "fsl_common.h"
10
11 /*******************************************************************************
12 * Definitions
13 ******************************************************************************/
14
15 /*!
16 * @addtogroup i3c
17 * @{
18 */
19
20 /*! @name Driver version */
21 /*! @{ */
22 /*! @brief I3C driver version */
23 #define FSL_I3C_DRIVER_VERSION (MAKE_VERSION(2, 12, 0))
24 /*! @} */
25
26 /*! @brief Timeout times for waiting flag. */
27 #ifndef I3C_RETRY_TIMES
28 #define I3C_RETRY_TIMES 0U /* Define to zero means keep waiting until the flag is assert/deassert. */
29 #endif
30
31 #define I3C_MAX_DEVCNT 10U
32
33 #ifndef I3C_IBI_BUFF_SIZE
34 #define I3C_IBI_BUFF_SIZE 10U
35 #endif
36
37 /*! @brief I3C status return codes. */
38 enum
39 {
40 kStatus_I3C_Busy = MAKE_STATUS(kStatusGroup_I3C, 0), /*!< The master is already performing a transfer. */
41 kStatus_I3C_Idle = MAKE_STATUS(kStatusGroup_I3C, 1), /*!< The slave driver is idle. */
42 kStatus_I3C_Nak = MAKE_STATUS(kStatusGroup_I3C, 2), /*!< The slave device sent a NAK in response to an address. */
43 kStatus_I3C_WriteAbort =
44 MAKE_STATUS(kStatusGroup_I3C, 3), /*!< The slave device sent a NAK in response to a write. */
45 kStatus_I3C_Term = MAKE_STATUS(kStatusGroup_I3C, 4), /*!< The master terminates slave read. */
46 kStatus_I3C_HdrParityError = MAKE_STATUS(kStatusGroup_I3C, 5), /*!< Parity error from DDR read. */
47 kStatus_I3C_CrcError = MAKE_STATUS(kStatusGroup_I3C, 6), /*!< CRC error from DDR read. */
48 kStatus_I3C_ReadFifoError = MAKE_STATUS(kStatusGroup_I3C, 7), /*!< Read from M/SRDATAB register when FIFO empty. */
49 kStatus_I3C_WriteFifoError = MAKE_STATUS(kStatusGroup_I3C, 8), /*!< Write to M/SWDATAB register when FIFO full. */
50 kStatus_I3C_MsgError =
51 MAKE_STATUS(kStatusGroup_I3C, 9), /*!< Message SDR/DDR mismatch or read/write message in wrong state */
52 kStatus_I3C_InvalidReq = MAKE_STATUS(kStatusGroup_I3C, 10), /*!< Invalid use of request. */
53 kStatus_I3C_Timeout = MAKE_STATUS(kStatusGroup_I3C, 11), /*!< The module has stalled too long in a frame. */
54 kStatus_I3C_SlaveCountExceed =
55 MAKE_STATUS(kStatusGroup_I3C, 12), /*!< The I3C slave count has exceed the definition in I3C_MAX_DEVCNT. */
56 kStatus_I3C_IBIWon = MAKE_STATUS(
57 kStatusGroup_I3C, 13), /*!< The I3C slave event IBI or MR or HJ won the arbitration on a header address. */
58 kStatus_I3C_OverrunError = MAKE_STATUS(kStatusGroup_I3C, 14), /*!< Slave internal from-bus buffer/FIFO overrun. */
59 kStatus_I3C_UnderrunError = MAKE_STATUS(kStatusGroup_I3C, 15), /*!< Slave internal to-bus buffer/FIFO underrun */
60 kStatus_I3C_UnderrunNak =
61 MAKE_STATUS(kStatusGroup_I3C, 16), /*!< Slave internal from-bus buffer/FIFO underrun and NACK error */
62 kStatus_I3C_InvalidStart = MAKE_STATUS(kStatusGroup_I3C, 17), /*!< Slave invalid start flag */
63 kStatus_I3C_SdrParityError = MAKE_STATUS(kStatusGroup_I3C, 18), /*!< SDR parity error */
64 kStatus_I3C_S0S1Error = MAKE_STATUS(kStatusGroup_I3C, 19), /*!< S0 or S1 error */
65 };
66
67 /*! @brief I3C HDR modes. */
68 typedef enum _i3c_hdr_mode
69 {
70 kI3C_HDRModeNone = 0x00U, /* Do not support HDR mode. */
71 kI3C_HDRModeDDR = 0x01U, /* HDR-DDR Mode. */
72 kI3C_HDRModeTSP = 0x02U, /* HDR-TSP Mode. */
73 kI3C_HDRModeTSL = 0x04U, /* HDR-TSL Mode. */
74 } i3c_hdr_mode_t;
75
76 /*! @brief I3C device information. */
77 typedef struct _i3c_device_info
78 {
79 uint8_t dynamicAddr; /*!< Device dynamic address. */
80 uint8_t staticAddr; /*!< Static address. */
81 uint8_t dcr; /*!< Device characteristics register information. */
82 uint8_t bcr; /*!< Bus characteristics register information. */
83 uint16_t vendorID; /*!< Device vendor ID(manufacture ID). */
84 uint32_t partNumber; /*!< Device part number info */
85 uint16_t maxReadLength; /*!< Maximum read length. */
86 uint16_t maxWriteLength; /*!< Maximum write length. */
87 uint8_t hdrMode; /*!< Support hdr mode, could be OR logic in i3c_hdr_mode. */
88 } i3c_device_info_t;
89
90 /*! @} */
91
92 /*!
93 * @addtogroup i3c_master_driver
94 * @{
95 */
96
97 /*!
98 * @brief I3C master peripheral flags.
99 *
100 * The following status register flags can be cleared:
101 * - #kI3C_MasterSlaveStartFlag
102 * - #kI3C_MasterControlDoneFlag
103 * - #kI3C_MasterCompleteFlag
104 * - #kI3C_MasterArbitrationWonFlag
105 * - #kI3C_MasterSlave2MasterFlag
106 *
107 * All flags except #kI3C_MasterBetweenFlag and #kI3C_MasterNackDetectFlag can be enabled as
108 * interrupts.
109 *
110 * @note These enums are meant to be OR'd together to form a bit mask.
111 */
112 enum _i3c_master_flags
113 {
114 kI3C_MasterBetweenFlag = I3C_MSTATUS_BETWEEN_MASK, /*!< Between messages/DAAs flag */
115 kI3C_MasterNackDetectFlag = I3C_MSTATUS_NACKED_MASK, /*!< NACK detected flag */
116 kI3C_MasterSlaveStartFlag = I3C_MSTATUS_SLVSTART_MASK, /*!< Slave request start flag */
117 kI3C_MasterControlDoneFlag = I3C_MSTATUS_MCTRLDONE_MASK, /*!< Master request complete flag */
118 kI3C_MasterCompleteFlag = I3C_MSTATUS_COMPLETE_MASK, /*!< Transfer complete flag */
119 kI3C_MasterRxReadyFlag = I3C_MSTATUS_RXPEND_MASK, /*!< Rx data ready in Rx buffer flag */
120 kI3C_MasterTxReadyFlag = I3C_MSTATUS_TXNOTFULL_MASK, /*!< Tx buffer ready for Tx data flag */
121 kI3C_MasterArbitrationWonFlag = I3C_MSTATUS_IBIWON_MASK, /*!< Header address won arbitration flag */
122 kI3C_MasterErrorFlag = I3C_MSTATUS_ERRWARN_MASK, /*!< Error occurred flag */
123 kI3C_MasterSlave2MasterFlag = I3C_MSTATUS_NOWMASTER_MASK, /*!< Switch from slave to master flag */
124 kI3C_MasterClearFlags = kI3C_MasterSlaveStartFlag | kI3C_MasterControlDoneFlag | kI3C_MasterCompleteFlag |
125 kI3C_MasterArbitrationWonFlag | kI3C_MasterSlave2MasterFlag | kI3C_MasterErrorFlag,
126 };
127
128 /*!
129 * @brief I3C master error flags to indicate the causes.
130 *
131 * @note These enums are meant to be OR'd together to form a bit mask.
132 */
133 enum _i3c_master_error_flags
134 {
135 kI3C_MasterErrorNackFlag = I3C_MERRWARN_NACK_MASK, /*!< Slave NACKed the last address */
136 kI3C_MasterErrorWriteAbortFlag = I3C_MERRWARN_WRABT_MASK, /*!< Slave NACKed the write data */
137 #if !defined(FSL_FEATURE_I3C_HAS_NO_MERRWARN_TERM) || (!FSL_FEATURE_I3C_HAS_NO_MERRWARN_TERM)
138 kI3C_MasterErrorTermFlag = I3C_MERRWARN_TERM_MASK, /*!< Master terminates slave read */
139 #endif
140 kI3C_MasterErrorParityFlag = I3C_MERRWARN_HPAR_MASK, /*!< Parity error from DDR read */
141 kI3C_MasterErrorCrcFlag = I3C_MERRWARN_HCRC_MASK, /*!< CRC error from DDR read */
142 kI3C_MasterErrorReadFlag = I3C_MERRWARN_OREAD_MASK, /*!< Read from MRDATAB register when FIFO empty */
143 kI3C_MasterErrorWriteFlag = I3C_MERRWARN_OWRITE_MASK, /*!< Write to MWDATAB register when FIFO full */
144 kI3C_MasterErrorMsgFlag = I3C_MERRWARN_MSGERR_MASK, /*!< Message SDR/DDR mismatch or
145 read/write message in wrong state */
146 kI3C_MasterErrorInvalidReqFlag = I3C_MERRWARN_INVREQ_MASK, /*!< Invalid use of request */
147 kI3C_MasterErrorTimeoutFlag = I3C_MERRWARN_TIMEOUT_MASK, /*!< The module has stalled too long in a frame */
148 kI3C_MasterAllErrorFlags = kI3C_MasterErrorNackFlag | kI3C_MasterErrorWriteAbortFlag |
149 #if !defined(FSL_FEATURE_I3C_HAS_NO_MERRWARN_TERM) || (!FSL_FEATURE_I3C_HAS_NO_MERRWARN_TERM)
150 kI3C_MasterErrorTermFlag |
151 #endif
152 kI3C_MasterErrorParityFlag | kI3C_MasterErrorCrcFlag | kI3C_MasterErrorReadFlag |
153 kI3C_MasterErrorWriteFlag | kI3C_MasterErrorMsgFlag | kI3C_MasterErrorInvalidReqFlag |
154 kI3C_MasterErrorTimeoutFlag, /*!< All error flags */
155 };
156
157 /*! @brief I3C working master state. */
158 typedef enum _i3c_master_state
159 {
160 kI3C_MasterStateIdle = 0U, /*!< Bus stopped. */
161 kI3C_MasterStateSlvReq = 1U, /*!< Bus stopped but slave holding SDA low. */
162 kI3C_MasterStateMsgSdr = 2U, /*!< In SDR Message mode from using MWMSG_SDR. */
163 kI3C_MasterStateNormAct = 3U, /*!< In normal active SDR mode. */
164 kI3C_MasterStateDdr = 4U, /*!< In DDR Message mode. */
165 kI3C_MasterStateDaa = 5U, /*!< In ENTDAA mode. */
166 kI3C_MasterStateIbiAck = 6U, /*!< Waiting on IBI ACK/NACK decision. */
167 kI3C_MasterStateIbiRcv = 7U, /*!< receiving IBI. */
168 } i3c_master_state_t;
169
170 /*! @brief I3C master enable configuration. */
171 typedef enum _i3c_master_enable
172 {
173 kI3C_MasterOff = 0U, /*!< Master off. */
174 kI3C_MasterOn = 1U, /*!< Master on. */
175 kI3C_MasterCapable = 2U /*!< Master capable. */
176 } i3c_master_enable_t;
177
178 /*! @brief I3C high keeper configuration. */
179 typedef enum _i3c_master_hkeep
180 {
181 kI3C_MasterHighKeeperNone = 0U, /*!< Use PUR to hold SCL high. */
182 kI3C_MasterHighKeeperWiredIn = 1U, /*!< Use pin_HK controls. */
183 kI3C_MasterPassiveSDA = 2U, /*!< Hi-Z for Bus Free and hold SDA. */
184 kI3C_MasterPassiveSDASCL = 3U /*!< Hi-Z both for Bus Free, and can Hi-Z SDA for hold. */
185 } i3c_master_hkeep_t;
186
187 /*! @brief Emits the requested operation when doing in pieces vs. by message. */
188 typedef enum _i3c_bus_request
189 {
190 kI3C_RequestNone = 0U, /*!< No request. */
191 kI3C_RequestEmitStartAddr = 1U, /*!< Request to emit start and address on bus. */
192 kI3C_RequestEmitStop = 2U, /*!< Request to emit stop on bus. */
193 kI3C_RequestIbiAckNack = 3U, /*!< Manual IBI ACK or NACK. */
194 kI3C_RequestProcessDAA = 4U, /*!< Process DAA. */
195 kI3C_RequestForceExit = 6U, /*!< Request to force exit. */
196 kI3C_RequestAutoIbi = 7U, /*!< Hold in stopped state, but Auto-emit START,7E. */
197 } i3c_bus_request_t;
198
199 /*! @brief Bus type with EmitStartAddr. */
200 typedef enum _i3c_bus_type
201 {
202 kI3C_TypeI3CSdr = 0U, /*!< SDR mode of I3C. */
203 kI3C_TypeI2C = 1U, /*!< Standard i2c protocol. */
204 kI3C_TypeI3CDdr = 2U, /*!< HDR-DDR mode of I3C. */
205 } i3c_bus_type_t;
206
207 /*! @brief IBI response. */
208 typedef enum _i3c_ibi_response
209 {
210 kI3C_IbiRespAck = 0U, /*!< ACK with no mandatory byte. */
211 kI3C_IbiRespNack = 1U, /*!< NACK. */
212 kI3C_IbiRespAckMandatory = 2U, /*!< ACK with mandatory byte. */
213 kI3C_IbiRespManual = 3U, /*!< Reserved. */
214 } i3c_ibi_response_t;
215
216 /*! @brief IBI type. */
217 typedef enum _i3c_ibi_type
218 {
219 kI3C_IbiNormal = 0U, /*!< In-band interrupt. */
220 kI3C_IbiHotJoin = 1U, /*!< slave hot join. */
221 kI3C_IbiMasterRequest = 2U, /*!< slave master ship request. */
222 } i3c_ibi_type_t;
223
224 /*! @brief IBI state. */
225 typedef enum _i3c_ibi_state
226 {
227 kI3C_IbiReady = 0U, /*!< In-band interrupt ready state, ready for user to handle. */
228 kI3C_IbiDataBuffNeed = 1U, /*!< In-band interrupt need data buffer for data receive. */
229 kI3C_IbiAckNackPending = 2U, /*!< In-band interrupt Ack/Nack pending for decision. */
230 } i3c_ibi_state_t;
231
232 /*! @brief Direction of master and slave transfers. */
233 typedef enum _i3c_direction
234 {
235 kI3C_Write = 0U, /*!< Master transmit. */
236 kI3C_Read = 1U /*!< Master receive. */
237 } i3c_direction_t;
238
239 /*! @brief Watermark of TX int/dma trigger level. */
240 typedef enum _i3c_tx_trigger_level
241 {
242 kI3C_TxTriggerOnEmpty = 0U, /*!< Trigger on empty. */
243 kI3C_TxTriggerUntilOneQuarterOrLess = 1U, /*!< Trigger on 1/4 full or less. */
244 kI3C_TxTriggerUntilOneHalfOrLess = 2U, /*!< Trigger on 1/2 full or less. */
245 kI3C_TxTriggerUntilOneLessThanFull = 3U, /*!< Trigger on 1 less than full or less. */
246 } i3c_tx_trigger_level_t;
247
248 /*! @brief Watermark of RX int/dma trigger level. */
249 typedef enum _i3c_rx_trigger_level
250 {
251 kI3C_RxTriggerOnNotEmpty = 0U, /*!< Trigger on not empty. */
252 kI3C_RxTriggerUntilOneQuarterOrMore = 1U, /*!< Trigger on 1/4 full or more. */
253 kI3C_RxTriggerUntilOneHalfOrMore = 2U, /*!< Trigger on 1/2 full or more. */
254 kI3C_RxTriggerUntilThreeQuarterOrMore = 3U, /*!< Trigger on 3/4 full or more. */
255 } i3c_rx_trigger_level_t;
256
257 /*! @brief I3C master read termination operations. */
258 typedef enum _i3c_rx_term_ops
259 {
260 kI3C_RxTermDisable = 0U, /*!< Master doesn't terminate read, used for CCC transfer. */
261 kI3C_RxAutoTerm = 1U, /*!< Master auto terminate read after receiving specified bytes(<=255). */
262 kI3C_RxTermLastByte = 2U, /*!< Master terminates read at any time after START, no length limitation. */
263 } i3c_rx_term_ops_t;
264
265 /*! @brief I3C start SCL delay options. */
266 typedef enum _i3c_start_scl_delay
267 {
268 kI3C_NoDelay = 0U, /*!< No delay. */
269 kI3C_IncreaseSclHalfPeriod = 1U, /*!< Increases SCL clock period by 1/2. */
270 kI3C_IncreaseSclOnePeriod = 2U, /*!< Increases SCL clock period by 1. */
271 kI3C_IncreaseSclOneAndHalfPeriod = 3U, /*!< Increases SCL clock period by 1 1/2 */
272 } i3c_start_scl_delay_t;
273
274 /*! @brief Structure with setting master IBI rules and slave registry. */
275 typedef struct _i3c_register_ibi_addr
276 {
277 uint8_t address[5]; /*!< Address array for registry. */
278 bool ibiHasPayload; /*!< Whether the address array has mandatory IBI byte. */
279 } i3c_register_ibi_addr_t;
280
281 /*! @brief Structure with I3C baudrate settings. */
282 typedef struct _i3c_baudrate
283 {
284 uint32_t i2cBaud; /*!< Desired I2C baud rate in Hertz. */
285 uint32_t i3cPushPullBaud; /*!< Desired I3C push-pull baud rate in Hertz. */
286 uint32_t i3cOpenDrainBaud; /*!< Desired I3C open-drain baud rate in Hertz. */
287 } i3c_baudrate_hz_t;
288
289 /*! @brief I3C DAA baud rate configuration. */
290 typedef struct _i3c_master_daa_baudrate
291 {
292 uint32_t sourceClock_Hz; /*!< FCLK, function clock in Hertz. */
293 uint32_t i3cPushPullBaud; /*!< Desired I3C push-pull baud rate in Hertz. */
294 uint32_t i3cOpenDrainBaud; /*!< Desired I3C open-drain baud rate in Hertz. */
295 } i3c_master_daa_baudrate_t;
296
297 /*!
298 * @brief Structure with settings to initialize the I3C master module.
299 *
300 * This structure holds configuration settings for the I3C peripheral. To initialize this
301 * structure to reasonable defaults, call the I3C_MasterGetDefaultConfig() function and
302 * pass a pointer to your configuration structure instance.
303 *
304 * The configuration structure can be made constant so it resides in flash.
305 */
306 typedef struct _i3c_master_config
307 {
308 i3c_master_enable_t enableMaster; /*!< Enable master mode. */
309 bool disableTimeout; /*!< Whether to disable timeout to prevent the ERRWARN. */
310 i3c_master_hkeep_t hKeep; /*!< High keeper mode setting. */
311 bool enableOpenDrainStop; /*!< Whether to emit open-drain speed STOP. */
312 bool enableOpenDrainHigh; /*!< Enable Open-Drain High to be 1 PPBAUD count for i3c messages, or 1 ODBAUD. */
313 i3c_baudrate_hz_t baudRate_Hz; /*!< Desired baud rate settings. */
314 #if !(defined(FSL_FEATURE_I3C_HAS_NO_SCONFIG_BAMATCH) && FSL_FEATURE_I3C_HAS_NO_SCONFIG_BAMATCH)
315 uint32_t slowClock_Hz; /*!< Slow clock frequency. */
316 #endif
317 #if defined(FSL_FEATURE_I3C_HAS_START_SCL_DELAY) && FSL_FEATURE_I3C_HAS_START_SCL_DELAY
318 i3c_start_scl_delay_t startSclDelay; /*!< I3C SCL delay after START. */
319 i3c_start_scl_delay_t restartSclDelay; /*!< I3C SCL delay after Repeated START. */
320 #endif
321 } i3c_master_config_t;
322
323 /* Forward declaration of the transfer descriptor and handle typedefs. */
324 typedef struct _i3c_master_transfer i3c_master_transfer_t;
325 typedef struct _i3c_master_handle i3c_master_handle_t;
326
327 /*! @brief i3c master callback functions. */
328 typedef struct _i3c_master_transfer_callback
329 {
330 void (*slave2Master)(I3C_Type *base, void *userData); /*!< Transfer complete callback */
331 void (*ibiCallback)(I3C_Type *base,
332 i3c_master_handle_t *handle,
333 i3c_ibi_type_t ibiType,
334 i3c_ibi_state_t ibiState); /*!< IBI event callback */
335 void (*transferComplete)(I3C_Type *base,
336 i3c_master_handle_t *handle,
337 status_t completionStatus,
338 void *userData); /*!< Transfer complete callback */
339 } i3c_master_transfer_callback_t;
340 /*!
341 * @brief Transfer option flags.
342 *
343 * @note These enumerations are intended to be OR'd together to form a bit mask of options for
344 * the #_i3c_master_transfer::flags field.
345 */
346 enum _i3c_master_transfer_flags
347 {
348 kI3C_TransferDefaultFlag = 0x00U, /*!< Transfer starts with a start signal, stops with a stop signal. */
349 kI3C_TransferNoStartFlag = 0x01U, /*!< Don't send a start condition, address, and sub address */
350 kI3C_TransferRepeatedStartFlag = 0x02U, /*!< Send a repeated start condition */
351 kI3C_TransferNoStopFlag = 0x04U, /*!< Don't send a stop condition. */
352 kI3C_TransferWordsFlag = 0x08U, /*!< Transfer in words, else transfer in bytes. */
353 kI3C_TransferDisableRxTermFlag = 0x10U, /*!< Disable Rx termination. Note: It's for I3C CCC transfer. */
354 kI3C_TransferRxAutoTermFlag =
355 0x20U, /*!< Set Rx auto-termination. Note: It's adaptive based on Rx size(<=255 bytes) except in I3C_MasterReceive. */
356 kI3C_TransferStartWithBroadcastAddr = 0x40U, /*!< Start transfer with 0x7E, then read/write data with device address. */
357 };
358
359 /*!
360 * @brief Non-blocking transfer descriptor structure.
361 *
362 * This structure is used to pass transaction parameters to the I3C_MasterTransferNonBlocking() API.
363 */
364 struct _i3c_master_transfer
365 {
366 uint32_t flags; /*!< Bit mask of options for the transfer. See enumeration #_i3c_master_transfer_flags for available
367 options. Set to 0 or #kI3C_TransferDefaultFlag for normal transfers. */
368 uint8_t slaveAddress; /*!< The 7-bit slave address. */
369 i3c_direction_t direction; /*!< Either #kI3C_Read or #kI3C_Write. */
370 uint32_t subaddress; /*!< Sub address. Transferred MSB first. */
371 size_t subaddressSize; /*!< Length of sub address to send in bytes. Maximum size is 4 bytes. */
372 void *data; /*!< Pointer to data to transfer. */
373 size_t dataSize; /*!< Number of bytes to transfer. */
374 i3c_bus_type_t busType; /*!< bus type. */
375 i3c_ibi_response_t ibiResponse; /*!< ibi response during transfer. */
376 };
377
378 /*!
379 * @brief Driver handle for master non-blocking APIs.
380 * @note The contents of this structure are private and subject to change.
381 */
382 struct _i3c_master_handle
383 {
384 uint8_t state; /*!< Transfer state machine current state. */
385 uint32_t remainingBytes; /*!< Remaining byte count in current state. */
386 i3c_rx_term_ops_t rxTermOps; /*!< Read termination operation. */
387 i3c_master_transfer_t transfer; /*!< Copy of the current transfer info. */
388 uint8_t ibiAddress; /*!< Slave address which request IBI. */
389 uint8_t *ibiBuff; /*!< Pointer to IBI buffer to keep ibi bytes. */
390 size_t ibiPayloadSize; /*!< IBI payload size. */
391 i3c_ibi_type_t ibiType; /*!< IBI type. */
392 i3c_master_transfer_callback_t callback; /*!< Callback functions pointer. */
393 void *userData; /*!< Application data passed to callback. */
394 };
395
396 /*! @brief Typedef for master interrupt handler. */
397 typedef void (*i3c_master_isr_t)(I3C_Type *base, void *handle);
398
399 /*! @} */
400
401 /*!
402 * @addtogroup i3c_slave_driver
403 * @{
404 */
405
406 /*!
407 * @brief I3C slave peripheral flags.
408 *
409 * The following status register flags can be cleared:
410 * - #kI3C_SlaveBusStartFlag
411 * - #kI3C_SlaveMatchedFlag
412 * - #kI3C_SlaveBusStopFlag
413 *
414 * Only below flags can be enabled as interrupts.
415 * - #kI3C_SlaveBusStartFlag
416 * - #kI3C_SlaveMatchedFlag
417 * - #kI3C_SlaveBusStopFlag
418 * - #kI3C_SlaveRxReadyFlag
419 * - #kI3C_SlaveTxReadyFlag
420 * - #kI3C_SlaveDynamicAddrChangedFlag
421 * - #kI3C_SlaveReceivedCCCFlag
422 * - #kI3C_SlaveErrorFlag
423 * - #kI3C_SlaveHDRCommandMatchFlag
424 * - #kI3C_SlaveCCCHandledFlag
425 * - #kI3C_SlaveEventSentFlag
426
427 * @note These enums are meant to be OR'd together to form a bit mask.
428 */
429 enum _i3c_slave_flags
430 {
431 kI3C_SlaveNotStopFlag = I3C_SSTATUS_STNOTSTOP_MASK, /*!< Slave status not stop flag */
432 kI3C_SlaveMessageFlag = I3C_SSTATUS_STMSG_MASK, /*!< Slave status message, indicating slave is
433 listening to the bus traffic or responding */
434 kI3C_SlaveRequiredReadFlag = I3C_SSTATUS_STREQRD_MASK, /*!< Slave status required, either is master doing SDR
435 read from slave, or is IBI pushing out. */
436 kI3C_SlaveRequiredWriteFlag = I3C_SSTATUS_STREQWR_MASK, /*!< Slave status request write, master is doing SDR
437 write to slave, except slave in ENTDAA mode */
438 kI3C_SlaveBusDAAFlag = I3C_SSTATUS_STDAA_MASK, /*!< I3C bus is in ENTDAA mode */
439 kI3C_SlaveBusHDRModeFlag = I3C_SSTATUS_STHDR_MASK, /*!< I3C bus is in HDR mode */
440 kI3C_SlaveBusStartFlag = I3C_SSTATUS_START_MASK, /*!< Start/Re-start event is seen since the bus was last cleared */
441 kI3C_SlaveMatchedFlag = I3C_SSTATUS_MATCHED_MASK, /*!< Slave address(dynamic/static) matched since last cleared */
442 kI3C_SlaveBusStopFlag = I3C_SSTATUS_STOP_MASK, /*!<Stop event is seen since the bus was last cleared */
443 kI3C_SlaveRxReadyFlag = I3C_SSTATUS_RX_PEND_MASK, /*!< Rx data ready in rx buffer flag */
444 kI3C_SlaveTxReadyFlag = I3C_SSTATUS_TXNOTFULL_MASK, /*!< Tx buffer ready for Tx data flag */
445 kI3C_SlaveDynamicAddrChangedFlag =
446 I3C_SSTATUS_DACHG_MASK, /*!< Slave dynamic address has been assigned, re-assigned, or lost */
447 kI3C_SlaveReceivedCCCFlag = I3C_SSTATUS_CCC_MASK, /*!< Slave received Common command code */
448 kI3C_SlaveErrorFlag = I3C_SSTATUS_ERRWARN_MASK, /*!< Error occurred flag */
449 kI3C_SlaveHDRCommandMatchFlag = I3C_SSTATUS_HDRMATCH_MASK, /*!< High data rate command match */
450 kI3C_SlaveCCCHandledFlag =
451 I3C_SSTATUS_CHANDLED_MASK, /*!< Slave received Common command code is handled by I3C module */
452 kI3C_SlaveEventSentFlag = I3C_SSTATUS_EVENT_MASK, /*!< Slave IBI/P2P/MR/HJ event has been sent */
453 kI3C_SlaveIbiDisableFlag = I3C_SSTATUS_IBIDIS_MASK, /*!< Slave in band interrupt is disabled. */
454 kI3C_SlaveMasterRequestDisabledFlag = I3C_SSTATUS_MRDIS_MASK, /*!< Slave master request is disabled. */
455 kI3C_SlaveHotJoinDisabledFlag = I3C_SSTATUS_HJDIS_MASK, /*!< Slave Hot-Join is disabled. */
456 /*! All flags which are cleared by the driver upon starting a transfer. */
457 kI3C_SlaveClearFlags = kI3C_SlaveBusStartFlag | kI3C_SlaveMatchedFlag | kI3C_SlaveBusStopFlag,
458
459 kI3C_SlaveAllIrqFlags = kI3C_SlaveBusStartFlag | kI3C_SlaveMatchedFlag | kI3C_SlaveBusStopFlag |
460 kI3C_SlaveRxReadyFlag | kI3C_SlaveTxReadyFlag | kI3C_SlaveDynamicAddrChangedFlag |
461 kI3C_SlaveReceivedCCCFlag | kI3C_SlaveErrorFlag | kI3C_SlaveHDRCommandMatchFlag |
462 kI3C_SlaveCCCHandledFlag | kI3C_SlaveEventSentFlag,
463
464 };
465
466 /*!
467 * @brief I3C slave error flags to indicate the causes.
468 *
469 * @note These enums are meant to be OR'd together to form a bit mask.
470 */
471 enum _i3c_slave_error_flags
472 {
473 kI3C_SlaveErrorOverrunFlag = I3C_SERRWARN_ORUN_MASK, /*!< Slave internal from-bus buffer/FIFO overrun. */
474 kI3C_SlaveErrorUnderrunFlag = I3C_SERRWARN_URUN_MASK, /*!< Slave internal to-bus buffer/FIFO underrun */
475 kI3C_SlaveErrorUnderrunNakFlag =
476 I3C_SERRWARN_URUNNACK_MASK, /*!< Slave internal from-bus buffer/FIFO underrun and NACK error */
477 kI3C_SlaveErrorTermFlag = I3C_SERRWARN_TERM_MASK, /*!< Terminate error from master */
478 kI3C_SlaveErrorInvalidStartFlag = I3C_SERRWARN_INVSTART_MASK, /*!< Slave invalid start flag */
479 kI3C_SlaveErrorSdrParityFlag = I3C_SERRWARN_SPAR_MASK, /*!< SDR parity error */
480 kI3C_SlaveErrorHdrParityFlag = I3C_SERRWARN_HPAR_MASK, /*!< HDR parity error */
481 kI3C_SlaveErrorHdrCRCFlag = I3C_SERRWARN_HCRC_MASK, /*!< HDR-DDR CRC error */
482 kI3C_SlaveErrorS0S1Flag = I3C_SERRWARN_S0S1_MASK, /*!< S0 or S1 error */
483 kI3C_SlaveErrorOverreadFlag = I3C_SERRWARN_OREAD_MASK, /*!< Over-read error */
484 kI3C_SlaveErrorOverwriteFlag = I3C_SERRWARN_OWRITE_MASK, /*!< Over-write error */
485 };
486
487 /*! @brief I3C slave.event */
488 typedef enum _i3c_slave_event
489 {
490 kI3C_SlaveEventNormal = 0U, /*!< Normal mode. */
491 kI3C_SlaveEventIBI = 1U, /*!< In band interrupt event. */
492 kI3C_SlaveEventMasterReq = 2U, /*!< Master request event. */
493 kI3C_SlaveEventHotJoinReq = 3U, /*!< Hot-join event. */
494 } i3c_slave_event_t;
495
496 /*! @brief I3C slave.activity state */
497 typedef enum _i3c_slave_activity_state
498 {
499 kI3C_SlaveNoLatency = 0U, /*!< Normal bus operation */
500 kI3C_SlaveLatency1Ms = 1U, /*!< 1ms of latency. */
501 kI3C_SlaveLatency100Ms = 2U, /*!< 100ms of latency. */
502 kI3C_SlaveLatency10S = 3U, /*!< 10s latency. */
503 } i3c_slave_activity_state_t;
504
505 /*!
506 * @brief Structure with settings to initialize the I3C slave module.
507 *
508 * This structure holds configuration settings for the I3C peripheral. To initialize this
509 * structure to reasonable defaults, call the I3C_SlaveGetDefaultConfig() function and
510 * pass a pointer to your configuration structure instance.
511 *
512 * The configuration structure can be made constant so it resides in flash.
513 */
514 typedef struct _i3c_slave_config
515 {
516 bool enableSlave; /*!< Whether to enable slave. */
517 #if !(defined(FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ) && FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ)
518 bool isHotJoin; /*!< Whether to enable slave hotjoin before enable slave. */
519 #endif
520 uint8_t staticAddr; /*!< Static address. */
521 uint16_t vendorID; /*!< Device vendor ID(manufacture ID). */
522 #if !(defined(FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND) && FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND)
523 bool enableRandomPart; /*!< Whether to generate random part number, if using random part number,
524 the partNumber variable setting is meaningless. */
525 #endif
526 uint32_t partNumber; /*!< Device part number info */
527 uint8_t dcr; /*!< Device characteristics register information. */
528 uint8_t bcr; /*!< Bus characteristics register information. */
529 uint8_t hdrMode; /*!< Support hdr mode, could be OR logic in enumeration:i3c_hdr_mode_t. */
530 bool nakAllRequest; /*!< Whether to reply NAK to all requests except broadcast CCC. */
531 bool ignoreS0S1Error; /*!< Whether to ignore S0/S1 error in SDR mode. */
532 bool offline; /*!< Whether to wait 60 us of bus quiet or HDR request to ensure slave track SDR mode safely. */
533 bool matchSlaveStartStop; /*!< Whether to assert start/stop status only the time slave is addressed. */
534 uint32_t maxWriteLength; /*!< Maximum write length. */
535 uint32_t maxReadLength; /*!< Maximum read length. */
536 } i3c_slave_config_t;
537
538 /*!
539 * @brief Set of events sent to the callback for non blocking slave transfers.
540 *
541 * These event enumerations are used for two related purposes. First, a bit mask created by OR'ing together
542 * events is passed to I3C_SlaveTransferNonBlocking() in order to specify which events to enable.
543 * Then, when the slave callback is invoked, it is passed the current event through its @a transfer
544 * parameter.
545 *
546 * @note These enumerations are meant to be OR'd together to form a bit mask of events.
547 */
548 typedef enum _i3c_slave_transfer_event
549 {
550 kI3C_SlaveAddressMatchEvent = 0x01U, /*!< Received the slave address after a start or repeated start. */
551 kI3C_SlaveTransmitEvent = 0x02U, /*!< Callback is requested to provide data to transmit
552 (slave-transmitter role). */
553 kI3C_SlaveReceiveEvent = 0x04U, /*!< Callback is requested to provide a buffer in which to place received
554 data (slave-receiver role). */
555 kI3C_SlaveRequiredTransmitEvent = 0x08U, /*!< Callback is requested to provide a buffer in which to place received
556 data (slave-receiver role). */
557 kI3C_SlaveStartEvent = 0x10U, /*!< A start/repeated start was detected. */
558 kI3C_SlaveHDRCommandMatchEvent = 0x20U, /*!< Slave Match HDR Command. */
559 kI3C_SlaveCompletionEvent = 0x40U, /*!< A stop was detected, completing the transfer. */
560 kI3C_SlaveRequestSentEvent = 0x80U, /*!< Slave request event sent. */
561 kI3C_SlaveReceivedCCCEvent = 0x100L, /*!< Slave received CCC event, need to handle by application. */
562
563 /*! Bit mask of all available events. */
564 kI3C_SlaveAllEvents = kI3C_SlaveAddressMatchEvent | kI3C_SlaveTransmitEvent | kI3C_SlaveReceiveEvent |
565 kI3C_SlaveStartEvent | kI3C_SlaveHDRCommandMatchEvent | kI3C_SlaveCompletionEvent |
566 kI3C_SlaveRequestSentEvent | kI3C_SlaveReceivedCCCEvent,
567 } i3c_slave_transfer_event_t;
568
569 /*! @brief I3C slave transfer structure */
570 typedef struct _i3c_slave_transfer
571 {
572 uint32_t event; /*!< Reason the callback is being invoked. */
573 uint8_t *txData; /*!< Transfer buffer */
574 size_t txDataSize; /*!< Transfer size */
575 uint8_t *rxData; /*!< Transfer buffer */
576 size_t rxDataSize; /*!< Transfer size */
577 status_t completionStatus; /*!< Success or error code describing how the transfer completed. Only applies for
578 #kI3C_SlaveCompletionEvent. */
579 size_t transferredCount; /*!< Number of bytes actually transferred since start or last repeated start. */
580 } i3c_slave_transfer_t;
581
582 /* Forward declaration. */
583 typedef struct _i3c_slave_handle i3c_slave_handle_t;
584
585 /*!
586 * @brief Slave event callback function pointer type.
587 *
588 * This callback is used only for the slave non-blocking transfer API. To install a callback,
589 * use the I3C_SlaveSetCallback() function after you have created a handle.
590 *
591 * @param base Base address for the I3C instance on which the event occurred.
592 * @param transfer Pointer to transfer descriptor containing values passed to and/or from the callback.
593 * @param userData Arbitrary pointer-sized value passed from the application.
594 */
595 typedef void (*i3c_slave_transfer_callback_t)(I3C_Type *base, i3c_slave_transfer_t *transfer, void *userData);
596
597 /*!
598 * @brief I3C slave handle structure.
599 * @note The contents of this structure are private and subject to change.
600 */
601 struct _i3c_slave_handle
602 {
603 i3c_slave_transfer_t transfer; /*!< I3C slave transfer copy. */
604 bool isBusy; /*!< Whether transfer is busy. */
605 bool wasTransmit; /*!< Whether the last transfer was a transmit. */
606 uint32_t eventMask; /*!< Mask of enabled events. */
607 uint32_t transferredCount; /*!< Count of bytes transferred. */
608 i3c_slave_transfer_callback_t callback; /*!< Callback function called at transfer event. */
609 void *userData; /*!< Callback parameter passed to callback. */
610 uint8_t txFifoSize; /*!< Tx Fifo size */
611 };
612
613 /*! @brief Typedef for slave interrupt handler. */
614 typedef void (*i3c_slave_isr_t)(I3C_Type *base, void *handle);
615 /*! @} */
616
617 /*!
618 * @addtogroup i3c_common_driver
619 * @{
620 */
621
622 /*!
623 * @brief Structure with settings to initialize the I3C module, could both initialize master and slave functionality.
624 *
625 * This structure holds configuration settings for the I3C peripheral. To initialize this
626 * structure to reasonable defaults, call the I3C_GetDefaultConfig() function and
627 * pass a pointer to your configuration structure instance.
628 *
629 * The configuration structure can be made constant so it resides in flash.
630 */
631 typedef struct _i3c_config
632 {
633 i3c_master_enable_t enableMaster; /*!< Enable master mode. */
634 bool disableTimeout; /*!< Whether to disable timeout to prevent the ERRWARN. */
635 i3c_master_hkeep_t hKeep; /*!< High keeper mode setting. */
636 bool enableOpenDrainStop; /*!< Whether to emit open-drain speed STOP. */
637 bool enableOpenDrainHigh; /*!< Enable Open-Drain High to be 1 PPBAUD count for i3c messages, or 1 ODBAUD. */
638 i3c_baudrate_hz_t baudRate_Hz; /*!< Desired baud rate settings. */
639 #if defined(FSL_FEATURE_I3C_HAS_START_SCL_DELAY) && FSL_FEATURE_I3C_HAS_START_SCL_DELAY
640 i3c_start_scl_delay_t startSclDelay; /*!< I3C SCL delay after START. */
641 i3c_start_scl_delay_t restartSclDelay; /*!< I3C SCL delay after Repeated START. */
642 #endif
643 uint8_t masterDynamicAddress; /*!< Main master dynamic address configuration. */
644 #if !(defined(FSL_FEATURE_I3C_HAS_NO_SCONFIG_BAMATCH) && FSL_FEATURE_I3C_HAS_NO_SCONFIG_BAMATCH)
645 uint32_t slowClock_Hz; /*!< Slow clock frequency for time control. */
646 #endif
647 uint32_t maxWriteLength; /*!< Maximum write length. */
648 uint32_t maxReadLength; /*!< Maximum read length. */
649 bool enableSlave; /*!< Whether to enable slave. */
650 uint8_t staticAddr; /*!< Static address. */
651 uint16_t vendorID; /*!< Device vendor ID(manufacture ID). */
652 #if !(defined(FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND) && FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND)
653 bool enableRandomPart; /*!< Whether to generate random part number, if using random part number,
654 the partNumber variable setting is meaningless. */
655 #endif
656 uint32_t partNumber; /*!< Device part number info */
657 uint8_t dcr; /*!< Device characteristics register information. */
658 uint8_t bcr; /*!< Bus characteristics register information. */
659 uint8_t hdrMode; /*!< Support hdr mode, could be OR logic in enumeration:i3c_hdr_mode_t. */
660 bool nakAllRequest; /*!< Whether to reply NAK to all requests except broadcast CCC. */
661 bool ignoreS0S1Error; /*!< Whether to ignore S0/S1 error in SDR mode. */
662 bool offline; /*!< Whether to wait 60 us of bus quiet or HDR request to ensure slave track SDR mode safely. */
663 bool matchSlaveStartStop; /*!< Whether to assert start/stop status only the time slave is addressed. */
664 } i3c_config_t;
665
666 /*! @} */
667
668 /*******************************************************************************
669 * Variables
670 ******************************************************************************/
671 /*! Array to map I3C instance number to IRQ number. */
672 extern IRQn_Type const kI3cIrqs[];
673
674 /*! Pointer to master IRQ handler for each instance. */
675 extern i3c_master_isr_t s_i3cMasterIsr;
676
677 /*! Pointers to master handles for each instance. */
678 extern void *s_i3cMasterHandle[];
679
680 /*! Pointers to slave handles for each instance. */
681 extern void *s_i3cSlaveHandle[];
682
683 /*! @brief Pointers to slave IRQ handler. */
684 extern i3c_slave_isr_t s_i3cSlaveIsr;
685 /*******************************************************************************
686 * API
687 ******************************************************************************/
688 #
689 #if defined(__cplusplus)
690 extern "C" {
691 #endif
692
693 /*!
694 * @addtogroup i3c_common_driver
695 * @{
696 */
697 /*!
698 * @brief Get which instance current I3C is used.
699 * @param base The I3C peripheral base address.
700 */
701 uint32_t I3C_GetInstance(I3C_Type *base);
702 /*!
703 * @brief Provides a default configuration for the I3C peripheral, the configuration covers both master
704 * functionality and slave functionality.
705 *
706 * This function provides the following default configuration for I3C:
707 * @code
708 * config->enableMaster = kI3C_MasterCapable;
709 * config->disableTimeout = false;
710 * config->hKeep = kI3C_MasterHighKeeperNone;
711 * config->enableOpenDrainStop = true;
712 * config->enableOpenDrainHigh = true;
713 * config->baudRate_Hz.i2cBaud = 400000U;
714 * config->baudRate_Hz.i3cPushPullBaud = 12500000U;
715 * config->baudRate_Hz.i3cOpenDrainBaud = 2500000U;
716 * config->masterDynamicAddress = 0x0AU;
717 * config->slowClock_Hz = 1000000U;
718 * config->enableSlave = true;
719 * config->vendorID = 0x11BU;
720 * config->enableRandomPart = false;
721 * config->partNumber = 0;
722 * config->dcr = 0;
723 * config->bcr = 0;
724 * config->hdrMode = (uint8_t)kI3C_HDRModeDDR;
725 * config->nakAllRequest = false;
726 * config->ignoreS0S1Error = false;
727 * config->offline = false;
728 * config->matchSlaveStartStop = false;
729 * @endcode
730 *
731 * After calling this function, you can override any settings in order to customize the configuration,
732 * prior to initializing the common I3C driver with I3C_Init().
733 *
734 * @param[out] config User provided configuration structure for default values. Refer to #i3c_config_t.
735 */
736 void I3C_GetDefaultConfig(i3c_config_t *config);
737
738 /*!
739 * @brief Initializes the I3C peripheral.
740 * This function enables the peripheral clock and initializes the I3C peripheral as described by the user
741 * provided configuration. This will initialize both the master peripheral and slave peripheral so that I3C
742 * module could work as pure master, pure slave or secondary master, etc.
743 * A software reset is performed prior to configuration.
744 *
745 * @param base The I3C peripheral base address.
746 * @param config User provided peripheral configuration. Use I3C_GetDefaultConfig() to get a set of
747 * defaults that you can override.
748 * @param sourceClock_Hz Frequency in Hertz of the I3C functional clock. Used to calculate the baud rate divisors,
749 * filter widths, and timeout periods.
750 */
751 void I3C_Init(I3C_Type *base, const i3c_config_t *config, uint32_t sourceClock_Hz);
752
753 /*! @} */
754
755 /*!
756 * @addtogroup i3c_master_driver
757 * @{
758 */
759
760 /*! @name Initialization and deinitialization */
761 /*! @{ */
762
763 /*!
764 * @brief Provides a default configuration for the I3C master peripheral.
765 *
766 * This function provides the following default configuration for the I3C master peripheral:
767 * @code
768 * masterConfig->enableMaster = kI3C_MasterOn;
769 * masterConfig->disableTimeout = false;
770 * masterConfig->hKeep = kI3C_MasterHighKeeperNone;
771 * masterConfig->enableOpenDrainStop = true;
772 * masterConfig->enableOpenDrainHigh = true;
773 * masterConfig->baudRate_Hz = 100000U;
774 * masterConfig->busType = kI3C_TypeI2C;
775 * @endcode
776 *
777 * After calling this function, you can override any settings in order to customize the configuration,
778 * prior to initializing the master driver with I3C_MasterInit().
779 *
780 * @param[out] masterConfig User provided configuration structure for default values. Refer to #i3c_master_config_t.
781 */
782 void I3C_MasterGetDefaultConfig(i3c_master_config_t *masterConfig);
783
784 /*!
785 * @brief Initializes the I3C master peripheral.
786 *
787 * This function enables the peripheral clock and initializes the I3C master peripheral as described by the user
788 * provided configuration. A software reset is performed prior to configuration.
789 *
790 * @param base The I3C peripheral base address.
791 * @param masterConfig User provided peripheral configuration. Use I3C_MasterGetDefaultConfig() to get a set of
792 * defaults that you can override.
793 * @param sourceClock_Hz Frequency in Hertz of the I3C functional clock. Used to calculate the baud rate divisors,
794 * filter widths, and timeout periods.
795 */
796 void I3C_MasterInit(I3C_Type *base, const i3c_master_config_t *masterConfig, uint32_t sourceClock_Hz);
797
798 /*!
799 * @brief Deinitializes the I3C master peripheral.
800 *
801 * This function disables the I3C master peripheral and gates the clock. It also performs a software
802 * reset to restore the peripheral to reset conditions.
803 *
804 * @param base The I3C peripheral base address.
805 */
806 void I3C_MasterDeinit(I3C_Type *base);
807
808 /* Not static so it can be used from fsl_i3c_dma.c. */
809 status_t I3C_MasterCheckAndClearError(I3C_Type *base, uint32_t status);
810
811 /* Not static so it can be used from fsl_i3c_dma.c. */
812 status_t I3C_MasterWaitForCtrlDone(I3C_Type *base, bool waitIdle);
813
814 /* Not static so it can be used from fsl_i3c_dma.c. */
815 status_t I3C_CheckForBusyBus(I3C_Type *base);
816
817 /*!
818 * @brief Set I3C module master mode.
819 *
820 * @param base The I3C peripheral base address.
821 * @param enable Enable master mode.
822 */
I3C_MasterEnable(I3C_Type * base,i3c_master_enable_t enable)823 static inline void I3C_MasterEnable(I3C_Type *base, i3c_master_enable_t enable)
824 {
825 base->MCONFIG = (base->MCONFIG & ~I3C_MCONFIG_MSTENA_MASK) | I3C_MCONFIG_MSTENA(enable);
826 }
827
828 /*! @} */
829
830 /*! @name Status */
831 /*! @{ */
832
833 /*!
834 * @brief Gets the I3C master status flags.
835 *
836 * A bit mask with the state of all I3C master status flags is returned. For each flag, the corresponding bit
837 * in the return value is set if the flag is asserted.
838 *
839 * @param base The I3C peripheral base address.
840 * @return State of the status flags:
841 * - 1: related status flag is set.
842 * - 0: related status flag is not set.
843 * @see _i3c_master_flags
844 */
I3C_MasterGetStatusFlags(I3C_Type * base)845 static inline uint32_t I3C_MasterGetStatusFlags(I3C_Type *base)
846 {
847 return base->MSTATUS & ~(I3C_MSTATUS_STATE_MASK | I3C_MSTATUS_IBITYPE_MASK);
848 }
849
850 /*!
851 * @brief Clears the I3C master status flag state.
852 *
853 * The following status register flags can be cleared:
854 * - #kI3C_MasterSlaveStartFlag
855 * - #kI3C_MasterControlDoneFlag
856 * - #kI3C_MasterCompleteFlag
857 * - #kI3C_MasterArbitrationWonFlag
858 * - #kI3C_MasterSlave2MasterFlag
859 *
860 * Attempts to clear other flags has no effect.
861 *
862 * @param base The I3C peripheral base address.
863 * @param statusMask A bitmask of status flags that are to be cleared. The mask is composed of
864 * #_i3c_master_flags enumerators OR'd together. You may pass the result of a previous call to
865 * I3C_MasterGetStatusFlags().
866 * @see _i3c_master_flags.
867 */
I3C_MasterClearStatusFlags(I3C_Type * base,uint32_t statusMask)868 static inline void I3C_MasterClearStatusFlags(I3C_Type *base, uint32_t statusMask)
869 {
870 base->MSTATUS = statusMask;
871 }
872
873 /*!
874 * @brief Gets the I3C master error status flags.
875 *
876 * A bit mask with the state of all I3C master error status flags is returned. For each flag, the corresponding bit
877 * in the return value is set if the flag is asserted.
878 *
879 * @param base The I3C peripheral base address.
880 * @return State of the error status flags:
881 * - 1: related status flag is set.
882 * - 0: related status flag is not set.
883 * @see _i3c_master_error_flags
884 */
I3C_MasterGetErrorStatusFlags(I3C_Type * base)885 static inline uint32_t I3C_MasterGetErrorStatusFlags(I3C_Type *base)
886 {
887 return base->MERRWARN;
888 }
889
890 /*!
891 * @brief Clears the I3C master error status flag state.
892 *
893 * @param base The I3C peripheral base address.
894 * @param statusMask A bitmask of error status flags that are to be cleared. The mask is composed of
895 * #_i3c_master_error_flags enumerators OR'd together. You may pass the result of a previous call to
896 * I3C_MasterGetStatusFlags().
897 * @see _i3c_master_error_flags.
898 */
I3C_MasterClearErrorStatusFlags(I3C_Type * base,uint32_t statusMask)899 static inline void I3C_MasterClearErrorStatusFlags(I3C_Type *base, uint32_t statusMask)
900 {
901 while ((base->MERRWARN & statusMask) != 0U)
902 {
903 base->MERRWARN = statusMask;
904 }
905 }
906
907 /*!
908 * @brief Gets the I3C master state.
909 *
910 * @param base The I3C peripheral base address.
911 * @return I3C master state.
912 */
913 i3c_master_state_t I3C_MasterGetState(I3C_Type *base);
914
915 /*! @} */
916
917 /*! @name Interrupts */
918 /*! @{ */
919
920 /*!
921 * @brief Enables the I3C master interrupt requests.
922 *
923 * All flags except #kI3C_MasterBetweenFlag and #kI3C_MasterNackDetectFlag can be enabled as
924 * interrupts.
925 *
926 * @param base The I3C peripheral base address.
927 * @param interruptMask Bit mask of interrupts to enable. See #_i3c_master_flags for the set
928 * of constants that should be OR'd together to form the bit mask.
929 */
I3C_MasterEnableInterrupts(I3C_Type * base,uint32_t interruptMask)930 static inline void I3C_MasterEnableInterrupts(I3C_Type *base, uint32_t interruptMask)
931 {
932 base->MINTSET |= interruptMask;
933 }
934
935 /*!
936 * @brief Disables the I3C master interrupt requests.
937 *
938 * All flags except #kI3C_MasterBetweenFlag and #kI3C_MasterNackDetectFlag can be enabled as
939 * interrupts.
940 *
941 * @param base The I3C peripheral base address.
942 * @param interruptMask Bit mask of interrupts to disable. See #_i3c_master_flags for the set
943 * of constants that should be OR'd together to form the bit mask.
944 */
I3C_MasterDisableInterrupts(I3C_Type * base,uint32_t interruptMask)945 static inline void I3C_MasterDisableInterrupts(I3C_Type *base, uint32_t interruptMask)
946 {
947 base->MINTCLR = interruptMask;
948 }
949
950 /*!
951 * @brief Returns the set of currently enabled I3C master interrupt requests.
952 *
953 * @param base The I3C peripheral base address.
954 * @return A bitmask composed of #_i3c_master_flags enumerators OR'd together to indicate the
955 * set of enabled interrupts.
956 */
I3C_MasterGetEnabledInterrupts(I3C_Type * base)957 static inline uint32_t I3C_MasterGetEnabledInterrupts(I3C_Type *base)
958 {
959 return base->MINTSET;
960 }
961
962 /*!
963 * @brief Returns the set of pending I3C master interrupt requests.
964 *
965 * @param base The I3C peripheral base address.
966 * @return A bitmask composed of #_i3c_master_flags enumerators OR'd together to indicate the
967 * set of pending interrupts.
968 */
I3C_MasterGetPendingInterrupts(I3C_Type * base)969 static inline uint32_t I3C_MasterGetPendingInterrupts(I3C_Type *base)
970 {
971 return base->MINTMASKED;
972 }
973
974 /*! @} */
975
976 /*! @name DMA control */
977 /*! @{ */
978
979 /*!
980 * @brief Enables or disables I3C master DMA requests.
981 *
982 * @param base The I3C peripheral base address.
983 * @param enableTx Enable flag for transmit DMA request. Pass true for enable, false for disable.
984 * @param enableRx Enable flag for receive DMA request. Pass true for enable, false for disable.
985 * @param width DMA read/write unit in bytes.
986 */
I3C_MasterEnableDMA(I3C_Type * base,bool enableTx,bool enableRx,uint32_t width)987 static inline void I3C_MasterEnableDMA(I3C_Type *base, bool enableTx, bool enableRx, uint32_t width)
988 {
989 assert(width <= 2U);
990 base->MDMACTRL =
991 I3C_MDMACTRL_DMAFB(enableRx ? 2U : 0U) | I3C_MDMACTRL_DMATB(enableTx ? 2U : 0U) | I3C_MDMACTRL_DMAWIDTH(width);
992 }
993
994 /*!
995 * @brief Gets I3C master transmit data register address for DMA transfer.
996 *
997 * @param base The I3C peripheral base address.
998 * @param width DMA read/write unit in bytes.
999 * @return The I3C Master Transmit Data Register address.
1000 */
I3C_MasterGetTxFifoAddress(I3C_Type * base,uint32_t width)1001 static inline uint32_t I3C_MasterGetTxFifoAddress(I3C_Type *base, uint32_t width)
1002 {
1003 assert(width <= 2U);
1004 return (uint32_t)((width == 2U) ? &base->MWDATAH : &base->MWDATAB);
1005 }
1006
1007 /*!
1008 * @brief Gets I3C master receive data register address for DMA transfer.
1009 *
1010 * @param base The I3C peripheral base address.
1011 * @param width DMA read/write unit in bytes.
1012 * @return The I3C Master Receive Data Register address.
1013 */
I3C_MasterGetRxFifoAddress(I3C_Type * base,uint32_t width)1014 static inline uint32_t I3C_MasterGetRxFifoAddress(I3C_Type *base, uint32_t width)
1015 {
1016 assert(width <= 2U);
1017 return (uint32_t)((width == 2U) ? &base->MRDATAH : &base->MRDATAB);
1018 }
1019
1020 /*! @} */
1021
1022 /*! @name FIFO control */
1023 /*! @{ */
1024
1025 /*!
1026 * @brief Sets the watermarks for I3C master FIFOs.
1027 *
1028 * @param base The I3C peripheral base address.
1029 * @param txLvl Transmit FIFO watermark level. The #kI3C_MasterTxReadyFlag flag is set whenever
1030 * the number of words in the transmit FIFO reaches @a txLvl.
1031 * @param rxLvl Receive FIFO watermark level. The #kI3C_MasterRxReadyFlag flag is set whenever
1032 * the number of words in the receive FIFO reaches @a rxLvl.
1033 * @param flushTx true if TX FIFO is to be cleared, otherwise TX FIFO remains unchanged.
1034 * @param flushRx true if RX FIFO is to be cleared, otherwise RX FIFO remains unchanged.
1035 */
I3C_MasterSetWatermarks(I3C_Type * base,i3c_tx_trigger_level_t txLvl,i3c_rx_trigger_level_t rxLvl,bool flushTx,bool flushRx)1036 static inline void I3C_MasterSetWatermarks(
1037 I3C_Type *base, i3c_tx_trigger_level_t txLvl, i3c_rx_trigger_level_t rxLvl, bool flushTx, bool flushRx)
1038 {
1039 base->MDATACTRL = I3C_MDATACTRL_UNLOCK_MASK | I3C_MDATACTRL_TXTRIG(txLvl) | I3C_MDATACTRL_RXTRIG(rxLvl) |
1040 (flushTx ? I3C_MDATACTRL_FLUSHTB_MASK : 0U) | (flushRx ? I3C_MDATACTRL_FLUSHFB_MASK : 0U);
1041 }
1042
1043 /*!
1044 * @brief Gets the current number of bytes in the I3C master FIFOs.
1045 *
1046 * @param base The I3C peripheral base address.
1047 * @param[out] txCount Pointer through which the current number of bytes in the transmit FIFO is returned.
1048 * Pass NULL if this value is not required.
1049 * @param[out] rxCount Pointer through which the current number of bytes in the receive FIFO is returned.
1050 * Pass NULL if this value is not required.
1051 */
I3C_MasterGetFifoCounts(I3C_Type * base,size_t * rxCount,size_t * txCount)1052 static inline void I3C_MasterGetFifoCounts(I3C_Type *base, size_t *rxCount, size_t *txCount)
1053 {
1054 if (NULL != txCount)
1055 {
1056 *txCount = (base->MDATACTRL & I3C_MDATACTRL_TXCOUNT_MASK) >> I3C_MDATACTRL_TXCOUNT_SHIFT;
1057 }
1058 if (NULL != rxCount)
1059 {
1060 *rxCount = (base->MDATACTRL & I3C_MDATACTRL_RXCOUNT_MASK) >> I3C_MDATACTRL_RXCOUNT_SHIFT;
1061 }
1062 }
1063
1064 /*! @} */
1065
1066 /*! @name Bus operations */
1067 /*! @{ */
1068
1069 /*!
1070 * @brief Sets the I3C bus frequency for master transactions.
1071 *
1072 * The I3C master is automatically disabled and re-enabled as necessary to configure the baud
1073 * rate. Do not call this function during a transfer, or the transfer is aborted.
1074 *
1075 * @param base The I3C peripheral base address.
1076 * @param baudRate_Hz Pointer to structure of requested bus frequency in Hertz.
1077 * @param sourceClock_Hz I3C functional clock frequency in Hertz.
1078 */
1079 void I3C_MasterSetBaudRate(I3C_Type *base, const i3c_baudrate_hz_t *baudRate_Hz, uint32_t sourceClock_Hz);
1080
1081 /*!
1082 * @brief Returns whether the bus is idle.
1083 *
1084 * Requires the master mode to be enabled.
1085 *
1086 * @param base The I3C peripheral base address.
1087 * @retval true Bus is busy.
1088 * @retval false Bus is idle.
1089 */
I3C_MasterGetBusIdleState(I3C_Type * base)1090 static inline bool I3C_MasterGetBusIdleState(I3C_Type *base)
1091 {
1092 return ((base->MSTATUS & I3C_MSTATUS_STATE_MASK) == (uint32_t)kI3C_MasterStateIdle ? true : false);
1093 }
1094
1095 /*!
1096 * @brief Sends a START signal and slave address on the I2C/I3C bus, receive size is also specified
1097 * in the call.
1098 *
1099 * This function is used to initiate a new master mode transfer. First, the bus state is checked to ensure
1100 * that another master is not occupying the bus. Then a START signal is transmitted, followed by the
1101 * 7-bit address specified in the a address parameter. Note that this function does not actually wait
1102 * until the START and address are successfully sent on the bus before returning.
1103 *
1104 * @param base The I3C peripheral base address.
1105 * @param type The bus type to use in this transaction.
1106 * @param address 7-bit slave device address, in bits [6:0].
1107 * @param dir Master transfer direction, either #kI3C_Read or #kI3C_Write. This parameter is used to set
1108 * the R/w bit (bit 0) in the transmitted slave address.
1109 * @param rxSize Read terminate size for the followed read transfer, limit to 255 bytes.
1110 * @retval #kStatus_Success START signal and address were successfully enqueued in the transmit FIFO.
1111 * @retval #kStatus_I3C_Busy Another master is currently utilizing the bus.
1112 */
1113 status_t I3C_MasterStartWithRxSize(
1114 I3C_Type *base, i3c_bus_type_t type, uint8_t address, i3c_direction_t dir, uint8_t rxSize);
1115
1116 /*!
1117 * @brief Sends a START signal and slave address on the I2C/I3C bus.
1118 *
1119 * This function is used to initiate a new master mode transfer. First, the bus state is checked to ensure
1120 * that another master is not occupying the bus. Then a START signal is transmitted, followed by the
1121 * 7-bit address specified in the @a address parameter. Note that this function does not actually wait
1122 * until the START and address are successfully sent on the bus before returning.
1123 *
1124 * @param base The I3C peripheral base address.
1125 * @param type The bus type to use in this transaction.
1126 * @param address 7-bit slave device address, in bits [6:0].
1127 * @param dir Master transfer direction, either #kI3C_Read or #kI3C_Write. This parameter is used to set
1128 * the R/w bit (bit 0) in the transmitted slave address.
1129 * @retval #kStatus_Success START signal and address were successfully enqueued in the transmit FIFO.
1130 * @retval #kStatus_I3C_Busy Another master is currently utilizing the bus.
1131 */
1132 status_t I3C_MasterStart(I3C_Type *base, i3c_bus_type_t type, uint8_t address, i3c_direction_t dir);
1133
1134 /*!
1135 * @brief Sends a repeated START signal and slave address on the I2C/I3C bus, receive size is also specified
1136 * in the call.
1137 *
1138 * This function is used to send a Repeated START signal when a transfer is already in progress. Like
1139 * I3C_MasterStart(), it also sends the specified 7-bit address. Call this API also configures the read
1140 * terminate size for the following read transfer. For example, set the rxSize = 2, the following read transfer
1141 * will be terminated after two bytes of data received. Write transfer will not be affected by the rxSize
1142 * configuration.
1143 *
1144 * @note This function exists primarily to maintain compatible APIs between I3C and I2C drivers,
1145 * as well as to better document the intent of code that uses these APIs.
1146 *
1147 * @param base The I3C peripheral base address.
1148 * @param type The bus type to use in this transaction.
1149 * @param address 7-bit slave device address, in bits [6:0].
1150 * @param dir Master transfer direction, either #kI3C_Read or #kI3C_Write. This parameter is used to set
1151 * the R/w bit (bit 0) in the transmitted slave address.
1152 * @param rxSize Read terminate size for the followed read transfer, limit to 255 bytes.
1153 * @retval #kStatus_Success Repeated START signal and address were successfully enqueued in the transmit FIFO.
1154 */
1155 status_t I3C_MasterRepeatedStartWithRxSize(
1156 I3C_Type *base, i3c_bus_type_t type, uint8_t address, i3c_direction_t dir, uint8_t rxSize);
1157
1158 /*!
1159 * @brief Sends a repeated START signal and slave address on the I2C/I3C bus.
1160 *
1161 * This function is used to send a Repeated START signal when a transfer is already in progress. Like
1162 * I3C_MasterStart(), it also sends the specified 7-bit address.
1163 *
1164 * @note This function exists primarily to maintain compatible APIs between I3C and I2C drivers,
1165 * as well as to better document the intent of code that uses these APIs.
1166 *
1167 * @param base The I3C peripheral base address.
1168 * @param type The bus type to use in this transaction.
1169 * @param address 7-bit slave device address, in bits [6:0].
1170 * @param dir Master transfer direction, either #kI3C_Read or #kI3C_Write. This parameter is used to set
1171 * the R/w bit (bit 0) in the transmitted slave address.
1172 * @retval #kStatus_Success Repeated START signal and address were successfully enqueued in the transmit FIFO.
1173 */
I3C_MasterRepeatedStart(I3C_Type * base,i3c_bus_type_t type,uint8_t address,i3c_direction_t dir)1174 static inline status_t I3C_MasterRepeatedStart(I3C_Type *base,
1175 i3c_bus_type_t type,
1176 uint8_t address,
1177 i3c_direction_t dir)
1178 {
1179 return I3C_MasterRepeatedStartWithRxSize(base, type, address, dir, 0);
1180 }
1181
1182 /*!
1183 * @brief Performs a polling send transfer on the I2C/I3C bus.
1184 *
1185 * Sends up to @a txSize number of bytes to the previously addressed slave device. The slave may
1186 * reply with a NAK to any byte in order to terminate the transfer early. If this happens, this
1187 * function returns #kStatus_I3C_Nak.
1188 *
1189 * @param base The I3C peripheral base address.
1190 * @param txBuff The pointer to the data to be transferred.
1191 * @param txSize The length in bytes of the data to be transferred.
1192 * @param flags Bit mask of options for the transfer. See enumeration #_i3c_master_transfer_flags for available options.
1193 * @retval #kStatus_Success Data was sent successfully.
1194 * @retval #kStatus_I3C_Busy Another master is currently utilizing the bus.
1195 * @retval #kStatus_I3C_Timeout The module has stalled too long in a frame.
1196 * @retval #kStatus_I3C_Nak The slave device sent a NAK in response to an address.
1197 * @retval #kStatus_I3C_WriteAbort The slave device sent a NAK in response to a write.
1198 * @retval #kStatus_I3C_MsgError Message SDR/DDR mismatch or read/write message in wrong state.
1199 * @retval #kStatus_I3C_WriteFifoError Write to M/SWDATAB register when FIFO full.
1200 * @retval #kStatus_I3C_InvalidReq Invalid use of request.
1201 */
1202 status_t I3C_MasterSend(I3C_Type *base, const void *txBuff, size_t txSize, uint32_t flags);
1203
1204 /*!
1205 * @brief Performs a polling receive transfer on the I2C/I3C bus.
1206 *
1207 * @param base The I3C peripheral base address.
1208 * @param rxBuff The pointer to the data to be transferred.
1209 * @param rxSize The length in bytes of the data to be transferred.
1210 * @param flags Bit mask of options for the transfer. See enumeration #_i3c_master_transfer_flags for available options.
1211 * @retval #kStatus_Success Data was received successfully.
1212 * @retval #kStatus_I3C_Busy Another master is currently utilizing the bus.
1213 * @retval #kStatus_I3C_Timeout The module has stalled too long in a frame.
1214 * @retval #kStatus_I3C_Term The master terminates slave read.
1215 * @retval #kStatus_I3C_HdrParityError Parity error from DDR read.
1216 * @retval #kStatus_I3C_CrcError CRC error from DDR read.
1217 * @retval #kStatus_I3C_MsgError Message SDR/DDR mismatch or read/write message in wrong state.
1218 * @retval #kStatus_I3C_ReadFifoError Read from M/SRDATAB register when FIFO empty.
1219 * @retval #kStatus_I3C_InvalidReq Invalid use of request.
1220 */
1221 status_t I3C_MasterReceive(I3C_Type *base, void *rxBuff, size_t rxSize, uint32_t flags);
1222
1223 /*!
1224 * @brief Sends a STOP signal on the I2C/I3C bus.
1225 *
1226 * This function does not return until the STOP signal is seen on the bus, or an error occurs.
1227 *
1228 * @param base The I3C peripheral base address.
1229 * @retval #kStatus_Success The STOP signal was successfully sent on the bus and the transaction terminated.
1230 * @retval #kStatus_I3C_Busy Another master is currently utilizing the bus.
1231 * @retval #kStatus_I3C_Timeout The module has stalled too long in a frame.
1232 * @retval #kStatus_I3C_InvalidReq Invalid use of request.
1233 */
1234 status_t I3C_MasterStop(I3C_Type *base);
1235
1236 /*!
1237 * @brief I3C master emit request.
1238 *
1239 * @param base The I3C peripheral base address.
1240 * @param masterReq I3C master request of type #i3c_bus_request_t
1241 */
1242 void I3C_MasterEmitRequest(I3C_Type *base, i3c_bus_request_t masterReq);
1243
1244 /*!
1245 * @brief I3C master emit request.
1246 *
1247 * @param base The I3C peripheral base address.
1248 * @param ibiResponse I3C master emit IBI response of type #i3c_ibi_response_t
1249 */
I3C_MasterEmitIBIResponse(I3C_Type * base,i3c_ibi_response_t ibiResponse)1250 static inline void I3C_MasterEmitIBIResponse(I3C_Type *base, i3c_ibi_response_t ibiResponse)
1251 {
1252 uint32_t ctrlVal = base->MCTRL;
1253 ctrlVal &= ~(I3C_MCTRL_IBIRESP_MASK | I3C_MCTRL_REQUEST_MASK);
1254 ctrlVal |= I3C_MCTRL_IBIRESP((uint32_t)ibiResponse) | I3C_MCTRL_REQUEST(kI3C_RequestIbiAckNack);
1255 base->MCTRL = ctrlVal;
1256 }
1257
1258 /*!
1259 * @brief I3C master register IBI rule.
1260 *
1261 * @param base The I3C peripheral base address.
1262 * @param ibiRule Pointer to ibi rule description of type #i3c_register_ibi_addr_t
1263 */
1264 void I3C_MasterRegisterIBI(I3C_Type *base, i3c_register_ibi_addr_t *ibiRule);
1265
1266 /*!
1267 * @brief I3C master get IBI rule.
1268 *
1269 * @param base The I3C peripheral base address.
1270 * @param ibiRule Pointer to store the read out ibi rule description.
1271 */
1272 void I3C_MasterGetIBIRules(I3C_Type *base, i3c_register_ibi_addr_t *ibiRule);
1273
1274 /*!
1275 * @brief I3C master get IBI Type.
1276 *
1277 * @param base The I3C peripheral base address.
1278 * @retval i3c_ibi_type_t Type of #i3c_ibi_type_t.
1279 */
1280 i3c_ibi_type_t I3C_GetIBIType(I3C_Type *base);
1281
1282 /*!
1283 * @brief I3C master get IBI Address.
1284 *
1285 * @param base The I3C peripheral base address.
1286 * @retval The 8-bit IBI address.
1287 */
I3C_GetIBIAddress(I3C_Type * base)1288 static inline uint8_t I3C_GetIBIAddress(I3C_Type *base)
1289 {
1290 return (uint8_t)((base->MSTATUS & I3C_MSTATUS_IBIADDR_MASK) >> I3C_MSTATUS_IBIADDR_SHIFT);
1291 }
1292
1293 /*!
1294 * @brief Performs a DAA in the i3c bus with specified temporary baud rate.
1295 *
1296 * @param base The I3C peripheral base address.
1297 * @param addressList The pointer for address list which is used to do DAA.
1298 * @param count The address count in the address list.
1299 * @param daaBaudRate The temporary baud rate in DAA process, NULL for using initial setting.
1300 * The initial setting is set back between the completion of the DAA and the return of this function.
1301 * @retval #kStatus_Success The transaction was started successfully.
1302 * @retval #kStatus_I3C_Busy Either another master is currently utilizing the bus, or a non-blocking
1303 * transaction is already in progress.
1304 * @retval #kStatus_I3C_SlaveCountExceed The I3C slave count has exceed the definition in I3C_MAX_DEVCNT.
1305 */
1306 status_t I3C_MasterProcessDAASpecifiedBaudrate(I3C_Type *base,
1307 uint8_t *addressList,
1308 uint32_t count,
1309 i3c_master_daa_baudrate_t *daaBaudRate);
1310
1311 /*!
1312 * @brief Performs a DAA in the i3c bus.
1313 *
1314 * @param base The I3C peripheral base address.
1315 * @param addressList The pointer for address list which is used to do DAA.
1316 * @param count The address count in the address list.
1317 * The initial setting is set back between the completion of the DAA and the return of this function.
1318 * @retval #kStatus_Success The transaction was started successfully.
1319 * @retval #kStatus_I3C_Busy Either another master is currently utilizing the bus, or a non-blocking
1320 * transaction is already in progress.
1321 * @retval #kStatus_I3C_SlaveCountExceed The I3C slave count has exceed the definition in I3C_MAX_DEVCNT.
1322 */
I3C_MasterProcessDAA(I3C_Type * base,uint8_t * addressList,uint32_t count)1323 static inline status_t I3C_MasterProcessDAA(I3C_Type *base, uint8_t *addressList, uint32_t count)
1324 {
1325 return I3C_MasterProcessDAASpecifiedBaudrate(base, addressList, count, NULL);
1326 }
1327
1328 /*!
1329 * @brief Get device information list after DAA process is done.
1330 *
1331 * @param base The I3C peripheral base address.
1332 * @param[out] count The pointer to store the available device count.
1333 * @return Pointer to the i3c_device_info_t array.
1334 */
1335 i3c_device_info_t *I3C_MasterGetDeviceListAfterDAA(I3C_Type *base, uint8_t *count);
1336 /*!
1337 * @brief Performs a master polling transfer on the I2C/I3C bus.
1338 *
1339 * @note The API does not return until the transfer succeeds or fails due
1340 * to error happens during transfer.
1341 *
1342 * @param base The I3C peripheral base address.
1343 * @param transfer Pointer to the transfer structure.
1344 * @retval #kStatus_Success Data was received successfully.
1345 * @retval #kStatus_I3C_Busy Another master is currently utilizing the bus.
1346 * @retval #kStatus_I3C_IBIWon The I3C slave event IBI or MR or HJ won the arbitration on a header address.
1347 * @retval #kStatus_I3C_Timeout The module has stalled too long in a frame.
1348 * @retval #kStatus_I3C_Nak The slave device sent a NAK in response to an address.
1349 * @retval #kStatus_I3C_WriteAbort The slave device sent a NAK in response to a write.
1350 * @retval #kStatus_I3C_Term The master terminates slave read.
1351 * @retval #kStatus_I3C_HdrParityError Parity error from DDR read.
1352 * @retval #kStatus_I3C_CrcError CRC error from DDR read.
1353 * @retval #kStatus_I3C_MsgError Message SDR/DDR mismatch or read/write message in wrong state.
1354 * @retval #kStatus_I3C_ReadFifoError Read from M/SRDATAB register when FIFO empty.
1355 * @retval #kStatus_I3C_WriteFifoError Write to M/SWDATAB register when FIFO full.
1356 * @retval #kStatus_I3C_InvalidReq Invalid use of request.
1357 */
1358 status_t I3C_MasterTransferBlocking(I3C_Type *base, i3c_master_transfer_t *transfer);
1359
1360 /*! @} */
1361
1362 /*! @name Non-blocking */
1363 /*! @{ */
1364
1365 /*!
1366 * @brief Creates a new handle for the I3C master non-blocking APIs.
1367 *
1368 * The creation of a handle is for use with the non-blocking APIs. Once a handle
1369 * is created, there is not a corresponding destroy handle. If the user wants to
1370 * terminate a transfer, the I3C_MasterTransferAbort() API shall be called.
1371 *
1372 *
1373 * @note The function also enables the NVIC IRQ for the input I3C. Need to notice
1374 * that on some SoCs the I3C IRQ is connected to INTMUX, in this case user needs to
1375 * enable the associated INTMUX IRQ in application.
1376 *
1377 * @param base The I3C peripheral base address.
1378 * @param[out] handle Pointer to the I3C master driver handle.
1379 * @param callback User provided pointer to the asynchronous callback function.
1380 * @param userData User provided pointer to the application callback data.
1381 */
1382 void I3C_MasterTransferCreateHandle(I3C_Type *base,
1383 i3c_master_handle_t *handle,
1384 const i3c_master_transfer_callback_t *callback,
1385 void *userData);
1386
1387 /*!
1388 * @brief Performs a non-blocking transaction on the I2C/I3C bus.
1389 *
1390 * @param base The I3C peripheral base address.
1391 * @param handle Pointer to the I3C master driver handle.
1392 * @param transfer The pointer to the transfer descriptor.
1393 * @retval #kStatus_Success The transaction was started successfully.
1394 * @retval #kStatus_I3C_Busy Either another master is currently utilizing the bus, or a non-blocking
1395 * transaction is already in progress.
1396 */
1397 status_t I3C_MasterTransferNonBlocking(I3C_Type *base, i3c_master_handle_t *handle, i3c_master_transfer_t *transfer);
1398
1399 /*!
1400 * @brief Returns number of bytes transferred so far.
1401 * @param base The I3C peripheral base address.
1402 * @param handle Pointer to the I3C master driver handle.
1403 * @param[out] count Number of bytes transferred so far by the non-blocking transaction.
1404 * @retval #kStatus_Success
1405 * @retval #kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress.
1406 */
1407 status_t I3C_MasterTransferGetCount(I3C_Type *base, i3c_master_handle_t *handle, size_t *count);
1408
1409 /*!
1410 * @brief Terminates a non-blocking I3C master transmission early.
1411 *
1412 * @note It is not safe to call this function from an IRQ handler that has a higher priority than the
1413 * I3C peripheral's IRQ priority.
1414 *
1415 * @param base The I3C peripheral base address.
1416 * @param handle Pointer to the I3C master driver handle.
1417 * @retval #kStatus_Success A transaction was successfully aborted.
1418 * @retval #kStatus_I3C_Idle There is not a non-blocking transaction currently in progress.
1419 */
1420 void I3C_MasterTransferAbort(I3C_Type *base, i3c_master_handle_t *handle);
1421
1422 /*! @} */
1423
1424 /*! @name IRQ handler */
1425 /*! @{ */
1426
1427 /*!
1428 * @brief Reusable routine to handle master interrupts.
1429 * @note This function does not need to be called unless you are reimplementing the
1430 * nonblocking API's interrupt handler routines to add special functionality.
1431 * @param base The I3C peripheral base address.
1432 * @param intHandle Pointer to the I3C master driver handle.
1433 */
1434 void I3C_MasterTransferHandleIRQ(I3C_Type *base, void *intHandle);
1435
1436 /*! @} */
1437
1438 /*! @} */
1439
1440 /*!
1441 * @addtogroup i3c_slave_driver
1442 * @{
1443 */
1444
1445 /*! @name Initialization and deinitialization */
1446 /*! @{ */
1447
1448 /*!
1449 * @brief Provides a default configuration for the I3C slave peripheral.
1450 *
1451 * This function provides the following default configuration for the I3C slave peripheral:
1452 * @code
1453 * slaveConfig->enableslave = true;
1454 * @endcode
1455 *
1456 * After calling this function, you can override any settings in order to customize the configuration,
1457 * prior to initializing the slave driver with I3C_SlaveInit().
1458 *
1459 * @param[out] slaveConfig User provided configuration structure for default values. Refer to #i3c_slave_config_t.
1460 */
1461 void I3C_SlaveGetDefaultConfig(i3c_slave_config_t *slaveConfig);
1462
1463 /*!
1464 * @brief Initializes the I3C slave peripheral.
1465 *
1466 * This function enables the peripheral clock and initializes the I3C slave peripheral as described by the user
1467 * provided configuration.
1468 *
1469 * @param base The I3C peripheral base address.
1470 * @param slaveConfig User provided peripheral configuration. Use I3C_SlaveGetDefaultConfig() to get a set of
1471 * defaults that you can override.
1472 * @param slowClock_Hz Frequency in Hertz of the I3C slow clock. Used to calculate the bus match condition values.
1473 * If FSL_FEATURE_I3C_HAS_NO_SCONFIG_BAMATCH defines as 1, this parameter is useless.
1474 */
1475 void I3C_SlaveInit(I3C_Type *base, const i3c_slave_config_t *slaveConfig, uint32_t slowClock_Hz);
1476
1477 /*!
1478 * @brief Deinitializes the I3C slave peripheral.
1479 *
1480 * This function disables the I3C slave peripheral and gates the clock.
1481 *
1482 * @param base The I3C peripheral base address.
1483 */
1484 void I3C_SlaveDeinit(I3C_Type *base);
1485
1486 /*!
1487 * @brief Enable/Disable Slave.
1488 *
1489 * @param base The I3C peripheral base address.
1490 * @param isEnable Enable or disable.
1491 */
I3C_SlaveEnable(I3C_Type * base,bool isEnable)1492 static inline void I3C_SlaveEnable(I3C_Type *base, bool isEnable)
1493 {
1494 base->SCONFIG = (base->SCONFIG & ~I3C_SCONFIG_SLVENA_MASK) | I3C_SCONFIG_SLVENA(isEnable);
1495 }
1496
1497 /*! @} */
1498
1499 /*! @name Status */
1500 /*! @{ */
1501
1502 /*!
1503 * @brief Gets the I3C slave status flags.
1504 *
1505 * A bit mask with the state of all I3C slave status flags is returned. For each flag, the corresponding bit
1506 * in the return value is set if the flag is asserted.
1507 *
1508 * @param base The I3C peripheral base address.
1509 * @return State of the status flags:
1510 * - 1: related status flag is set.
1511 * - 0: related status flag is not set.
1512 * @see _i3c_slave_flags
1513 */
I3C_SlaveGetStatusFlags(I3C_Type * base)1514 static inline uint32_t I3C_SlaveGetStatusFlags(I3C_Type *base)
1515 {
1516 return base->SSTATUS & ~(I3C_SSTATUS_EVDET_MASK | I3C_SSTATUS_ACTSTATE_MASK | I3C_SSTATUS_TIMECTRL_MASK);
1517 }
1518
1519 /*!
1520 * @brief Clears the I3C slave status flag state.
1521 *
1522 * The following status register flags can be cleared:
1523 * - #kI3C_SlaveBusStartFlag
1524 * - #kI3C_SlaveMatchedFlag
1525 * - #kI3C_SlaveBusStopFlag
1526 *
1527 * Attempts to clear other flags has no effect.
1528 *
1529 * @param base The I3C peripheral base address.
1530 * @param statusMask A bitmask of status flags that are to be cleared. The mask is composed of
1531 * #_i3c_slave_flags enumerators OR'd together. You may pass the result of a previous call to
1532 * I3C_SlaveGetStatusFlags().
1533 * @see _i3c_slave_flags.
1534 */
I3C_SlaveClearStatusFlags(I3C_Type * base,uint32_t statusMask)1535 static inline void I3C_SlaveClearStatusFlags(I3C_Type *base, uint32_t statusMask)
1536 {
1537 base->SSTATUS = statusMask;
1538 }
1539
1540 /*!
1541 * @brief Gets the I3C slave error status flags.
1542 *
1543 * A bit mask with the state of all I3C slave error status flags is returned. For each flag, the corresponding bit
1544 * in the return value is set if the flag is asserted.
1545 *
1546 * @param base The I3C peripheral base address.
1547 * @return State of the error status flags:
1548 * - 1: related status flag is set.
1549 * - 0: related status flag is not set.
1550 * @see _i3c_slave_error_flags
1551 */
I3C_SlaveGetErrorStatusFlags(I3C_Type * base)1552 static inline uint32_t I3C_SlaveGetErrorStatusFlags(I3C_Type *base)
1553 {
1554 return base->SERRWARN;
1555 }
1556
1557 /*!
1558 * @brief Clears the I3C slave error status flag state.
1559 *
1560 * @param base The I3C peripheral base address.
1561 * @param statusMask A bitmask of error status flags that are to be cleared. The mask is composed of
1562 * #_i3c_slave_error_flags enumerators OR'd together. You may pass the result of a previous call to
1563 * I3C_SlaveGetErrorStatusFlags().
1564 * @see _i3c_slave_error_flags.
1565 */
I3C_SlaveClearErrorStatusFlags(I3C_Type * base,uint32_t statusMask)1566 static inline void I3C_SlaveClearErrorStatusFlags(I3C_Type *base, uint32_t statusMask)
1567 {
1568 base->SERRWARN = statusMask;
1569 }
1570
1571 /*!
1572 * @brief Gets the I3C slave state.
1573 *
1574 * @param base The I3C peripheral base address.
1575 * @return I3C slave activity state, refer #i3c_slave_activity_state_t.
1576 */
1577 i3c_slave_activity_state_t I3C_SlaveGetActivityState(I3C_Type *base);
1578
1579 /* Not static so it can be used from fsl_i3c_dma.c. */
1580 status_t I3C_SlaveCheckAndClearError(I3C_Type *base, uint32_t status);
1581 /*! @} */
1582
1583 /*! @name Interrupts */
1584 /*! @{ */
1585
1586 /*!
1587 * @brief Enables the I3C slave interrupt requests.
1588 *
1589 * Only below flags can be enabled as interrupts.
1590 * - #kI3C_SlaveBusStartFlag
1591 * - #kI3C_SlaveMatchedFlag
1592 * - #kI3C_SlaveBusStopFlag
1593 * - #kI3C_SlaveRxReadyFlag
1594 * - #kI3C_SlaveTxReadyFlag
1595 * - #kI3C_SlaveDynamicAddrChangedFlag
1596 * - #kI3C_SlaveReceivedCCCFlag
1597 * - #kI3C_SlaveErrorFlag
1598 * - #kI3C_SlaveHDRCommandMatchFlag
1599 * - #kI3C_SlaveCCCHandledFlag
1600 * - #kI3C_SlaveEventSentFlag
1601 *
1602 * @param base The I3C peripheral base address.
1603 * @param interruptMask Bit mask of interrupts to enable. See #_i3c_slave_flags for the set
1604 * of constants that should be OR'd together to form the bit mask.
1605 */
I3C_SlaveEnableInterrupts(I3C_Type * base,uint32_t interruptMask)1606 static inline void I3C_SlaveEnableInterrupts(I3C_Type *base, uint32_t interruptMask)
1607 {
1608 base->SINTSET |= interruptMask;
1609 }
1610
1611 /*!
1612 * @brief Disables the I3C slave interrupt requests.
1613 *
1614 * Only below flags can be disabled as interrupts.
1615 * - #kI3C_SlaveBusStartFlag
1616 * - #kI3C_SlaveMatchedFlag
1617 * - #kI3C_SlaveBusStopFlag
1618 * - #kI3C_SlaveRxReadyFlag
1619 * - #kI3C_SlaveTxReadyFlag
1620 * - #kI3C_SlaveDynamicAddrChangedFlag
1621 * - #kI3C_SlaveReceivedCCCFlag
1622 * - #kI3C_SlaveErrorFlag
1623 * - #kI3C_SlaveHDRCommandMatchFlag
1624 * - #kI3C_SlaveCCCHandledFlag
1625 * - #kI3C_SlaveEventSentFlag
1626 *
1627 * @param base The I3C peripheral base address.
1628 * @param interruptMask Bit mask of interrupts to disable. See #_i3c_slave_flags for the set
1629 * of constants that should be OR'd together to form the bit mask.
1630 */
I3C_SlaveDisableInterrupts(I3C_Type * base,uint32_t interruptMask)1631 static inline void I3C_SlaveDisableInterrupts(I3C_Type *base, uint32_t interruptMask)
1632 {
1633 base->SINTCLR = interruptMask;
1634 }
1635
1636 /*!
1637 * @brief Returns the set of currently enabled I3C slave interrupt requests.
1638 *
1639 * @param base The I3C peripheral base address.
1640 * @return A bitmask composed of #_i3c_slave_flags enumerators OR'd together to indicate the
1641 * set of enabled interrupts.
1642 */
I3C_SlaveGetEnabledInterrupts(I3C_Type * base)1643 static inline uint32_t I3C_SlaveGetEnabledInterrupts(I3C_Type *base)
1644 {
1645 return base->SINTSET;
1646 }
1647
1648 /*!
1649 * @brief Returns the set of pending I3C slave interrupt requests.
1650 *
1651 * @param base The I3C peripheral base address.
1652 * @return A bitmask composed of #_i3c_slave_flags enumerators OR'd together to indicate the
1653 * set of pending interrupts.
1654 */
I3C_SlaveGetPendingInterrupts(I3C_Type * base)1655 static inline uint32_t I3C_SlaveGetPendingInterrupts(I3C_Type *base)
1656 {
1657 return base->SINTMASKED;
1658 }
1659
1660 /*! @} */
1661
1662 /*! @name DMA control */
1663 /*! @{ */
1664
1665 /*!
1666 * @brief Enables or disables I3C slave DMA requests.
1667 *
1668 * @param base The I3C peripheral base address.
1669 * @param enableTx Enable flag for transmit DMA request. Pass true for enable, false for disable.
1670 * @param enableRx Enable flag for receive DMA request. Pass true for enable, false for disable.
1671 * @param width DMA read/write unit in bytes.
1672 */
I3C_SlaveEnableDMA(I3C_Type * base,bool enableTx,bool enableRx,uint32_t width)1673 static inline void I3C_SlaveEnableDMA(I3C_Type *base, bool enableTx, bool enableRx, uint32_t width)
1674 {
1675 assert(width <= 2U);
1676 base->SDMACTRL =
1677 I3C_SDMACTRL_DMAFB(enableRx ? 2U : 0U) | I3C_SDMACTRL_DMATB(enableTx ? 2U : 0U) | I3C_SDMACTRL_DMAWIDTH(width);
1678 }
1679
1680 /*!
1681 * @brief Gets I3C slave transmit data register address for DMA transfer.
1682 *
1683 * @param base The I3C peripheral base address.
1684 * @param width DMA read/write unit in bytes.
1685 * @return The I3C Slave Transmit Data Register address.
1686 */
I3C_SlaveGetTxFifoAddress(I3C_Type * base,uint32_t width)1687 static inline uint32_t I3C_SlaveGetTxFifoAddress(I3C_Type *base, uint32_t width)
1688 {
1689 assert(width <= 2U);
1690 return (uint32_t)((width == 2U) ? &base->SWDATAH : &base->SWDATAB);
1691 }
1692
1693 /*!
1694 * @brief Gets I3C slave receive data register address for DMA transfer.
1695 *
1696 * @param base The I3C peripheral base address.
1697 * @param width DMA read/write unit in bytes.
1698 * @return The I3C Slave Receive Data Register address.
1699 */
I3C_SlaveGetRxFifoAddress(I3C_Type * base,uint32_t width)1700 static inline uint32_t I3C_SlaveGetRxFifoAddress(I3C_Type *base, uint32_t width)
1701 {
1702 assert(width <= 2U);
1703 return (uint32_t)((width == 2U) ? &base->SRDATAH : &base->SRDATAB);
1704 }
1705
1706 /*! @} */
1707
1708 /*! @name FIFO control */
1709 /*! @{ */
1710
1711 /*!
1712 * @brief Sets the watermarks for I3C slave FIFOs.
1713 *
1714 * @param base The I3C peripheral base address.
1715 * @param txLvl Transmit FIFO watermark level. The #kI3C_SlaveTxReadyFlag flag is set whenever
1716 * the number of words in the transmit FIFO reaches @a txLvl.
1717 * @param rxLvl Receive FIFO watermark level. The #kI3C_SlaveRxReadyFlag flag is set whenever
1718 * the number of words in the receive FIFO reaches @a rxLvl.
1719 * @param flushTx true if TX FIFO is to be cleared, otherwise TX FIFO remains unchanged.
1720 * @param flushRx true if RX FIFO is to be cleared, otherwise RX FIFO remains unchanged.
1721 */
I3C_SlaveSetWatermarks(I3C_Type * base,i3c_tx_trigger_level_t txLvl,i3c_rx_trigger_level_t rxLvl,bool flushTx,bool flushRx)1722 static inline void I3C_SlaveSetWatermarks(
1723 I3C_Type *base, i3c_tx_trigger_level_t txLvl, i3c_rx_trigger_level_t rxLvl, bool flushTx, bool flushRx)
1724 {
1725 base->SDATACTRL = I3C_SDATACTRL_UNLOCK_MASK | I3C_SDATACTRL_TXTRIG(txLvl) | I3C_SDATACTRL_RXTRIG(rxLvl) |
1726 (flushTx ? I3C_SDATACTRL_FLUSHTB_MASK : 0U) | (flushRx ? I3C_SDATACTRL_FLUSHFB_MASK : 0U);
1727 }
1728
1729 /*!
1730 * @brief Gets the current number of bytes in the I3C slave FIFOs.
1731 *
1732 * @param base The I3C peripheral base address.
1733 * @param[out] txCount Pointer through which the current number of bytes in the transmit FIFO is returned.
1734 * Pass NULL if this value is not required.
1735 * @param[out] rxCount Pointer through which the current number of bytes in the receive FIFO is returned.
1736 * Pass NULL if this value is not required.
1737 */
I3C_SlaveGetFifoCounts(I3C_Type * base,size_t * rxCount,size_t * txCount)1738 static inline void I3C_SlaveGetFifoCounts(I3C_Type *base, size_t *rxCount, size_t *txCount)
1739 {
1740 if (NULL != txCount)
1741 {
1742 *txCount = (base->SDATACTRL & I3C_SDATACTRL_TXCOUNT_MASK) >> I3C_SDATACTRL_TXCOUNT_SHIFT;
1743 }
1744 if (NULL != rxCount)
1745 {
1746 *rxCount = (base->SDATACTRL & I3C_SDATACTRL_RXCOUNT_MASK) >> I3C_SDATACTRL_RXCOUNT_SHIFT;
1747 }
1748 }
1749
1750 /*! @} */
1751
1752 /*! @name Bus operations */
1753 /*! @{ */
1754
1755 #if !(defined(FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ) && FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ)
1756 /*!
1757 * @brief I3C slave request event.
1758 *
1759 * @param base The I3C peripheral base address.
1760 * @param event I3C slave event of type #i3c_slave_event_t
1761 */
1762 void I3C_SlaveRequestEvent(I3C_Type *base, i3c_slave_event_t event);
1763 #endif
1764
1765 /*!
1766 * @brief Performs a polling send transfer on the I3C bus.
1767 *
1768 * @param base The I3C peripheral base address.
1769 * @param txBuff The pointer to the data to be transferred.
1770 * @param txSize The length in bytes of the data to be transferred.
1771 * @return Error or success status returned by API.
1772 */
1773 status_t I3C_SlaveSend(I3C_Type *base, const void *txBuff, size_t txSize);
1774
1775 /*!
1776 * @brief Performs a polling receive transfer on the I3C bus.
1777 *
1778 * @param base The I3C peripheral base address.
1779 * @param rxBuff The pointer to the data to be transferred.
1780 * @param rxSize The length in bytes of the data to be transferred.
1781 * @return Error or success status returned by API.
1782 */
1783 status_t I3C_SlaveReceive(I3C_Type *base, void *rxBuff, size_t rxSize);
1784
1785 /*! @} */
1786
1787 /*! @name Slave non-blocking */
1788 /*! @{ */
1789
1790 /*!
1791 * @brief Creates a new handle for the I3C slave non-blocking APIs.
1792 *
1793 * The creation of a handle is for use with the non-blocking APIs. Once a handle
1794 * is created, there is not a corresponding destroy handle. If the user wants to
1795 * terminate a transfer, the I3C_SlaveTransferAbort() API shall be called.
1796 *
1797 * @note The function also enables the NVIC IRQ for the input I3C. Need to notice
1798 * that on some SoCs the I3C IRQ is connected to INTMUX, in this case user needs to
1799 * enable the associated INTMUX IRQ in application.
1800
1801 * @param base The I3C peripheral base address.
1802 * @param[out] handle Pointer to the I3C slave driver handle.
1803 * @param callback User provided pointer to the asynchronous callback function.
1804 * @param userData User provided pointer to the application callback data.
1805 */
1806 void I3C_SlaveTransferCreateHandle(I3C_Type *base,
1807 i3c_slave_handle_t *handle,
1808 i3c_slave_transfer_callback_t callback,
1809 void *userData);
1810
1811 /*!
1812 * @brief Starts accepting slave transfers.
1813 *
1814 * Call this API after calling I2C_SlaveInit() and I3C_SlaveTransferCreateHandle() to start processing
1815 * transactions driven by an I2C master. The slave monitors the I2C bus and pass events to the
1816 * callback that was passed into the call to I3C_SlaveTransferCreateHandle(). The callback is always invoked
1817 * from the interrupt context.
1818 *
1819 * The set of events received by the callback is customizable. To do so, set the @a eventMask parameter to
1820 * the OR'd combination of #i3c_slave_transfer_event_t enumerators for the events you wish to receive.
1821 * The #kI3C_SlaveTransmitEvent and #kI3C_SlaveReceiveEvent events are always enabled and do not need
1822 * to be included in the mask. Alternatively, you can pass 0 to get a default set of only the transmit and
1823 * receive events that are always enabled. In addition, the #kI3C_SlaveAllEvents constant is provided as
1824 * a convenient way to enable all events.
1825 *
1826 * @param base The I3C peripheral base address.
1827 * @param handle Pointer to struct: _i3c_slave_handle structure which stores the transfer state.
1828 * @param eventMask Bit mask formed by OR'ing together #i3c_slave_transfer_event_t enumerators to specify
1829 * which events to send to the callback. Other accepted values are 0 to get a default set of
1830 * only the transmit and receive events, and #kI3C_SlaveAllEvents to enable all events.
1831 *
1832 * @retval #kStatus_Success Slave transfers were successfully started.
1833 * @retval #kStatus_I3C_Busy Slave transfers have already been started on this handle.
1834 */
1835 status_t I3C_SlaveTransferNonBlocking(I3C_Type *base, i3c_slave_handle_t *handle, uint32_t eventMask);
1836
1837 /*!
1838 * @brief Gets the slave transfer status during a non-blocking transfer.
1839 * @param base The I3C peripheral base address.
1840 * @param handle Pointer to i2c_slave_handle_t structure.
1841 * @param[out] count Pointer to a value to hold the number of bytes transferred. May be NULL if the count is not
1842 * required.
1843 * @retval #kStatus_Success
1844 * @retval #kStatus_NoTransferInProgress
1845 */
1846 status_t I3C_SlaveTransferGetCount(I3C_Type *base, i3c_slave_handle_t *handle, size_t *count);
1847
1848 /*!
1849 * @brief Aborts the slave non-blocking transfers.
1850 * @note This API could be called at any time to stop slave for handling the bus events.
1851 * @param base The I3C peripheral base address.
1852 * @param handle Pointer to struct: _i3c_slave_handle structure which stores the transfer state.
1853 * @retval #kStatus_Success
1854 * @retval #kStatus_I3C_Idle
1855 */
1856 void I3C_SlaveTransferAbort(I3C_Type *base, i3c_slave_handle_t *handle);
1857
1858 /*! @} */
1859
1860 /*! @name Slave IRQ handler */
1861 /*! @{ */
1862
1863 /*!
1864 * @brief Reusable routine to handle slave interrupts.
1865 * @note This function does not need to be called unless you are reimplementing the
1866 * non blocking API's interrupt handler routines to add special functionality.
1867 * @param base The I3C peripheral base address.
1868 * @param intHandle Pointer to struct: _i3c_slave_handle structure which stores the transfer state.
1869 */
1870 void I3C_SlaveTransferHandleIRQ(I3C_Type *base, void *intHandle);
1871
1872 #if !(defined(FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ) && FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ)
1873 /*!
1874 * @brief I3C slave request IBI event with data payload(mandatory and extended).
1875 *
1876 * @param base The I3C peripheral base address.
1877 * @param data Pointer to IBI data to be sent in the request.
1878 * @param dataSize IBI data size.
1879 */
1880 void I3C_SlaveRequestIBIWithData(I3C_Type *base, uint8_t *data, size_t dataSize);
1881
1882 /*!
1883 * @brief I3C slave request IBI event with single data.
1884 * @deprecated Do not use this function. It has been superseded by @ref I3C_SlaveRequestIBIWithData.
1885 *
1886 * @param base The I3C peripheral base address.
1887 * @param data IBI data to be sent in the request.
1888 * @param dataSize IBI data size.
1889 */
1890 void I3C_SlaveRequestIBIWithSingleData(I3C_Type *base, uint8_t data, size_t dataSize);
1891 #endif /* !(defined(FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ) && FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ) */
1892
1893 /*! @} */
1894 /*! @} */
1895 #if defined(__cplusplus)
1896 }
1897 #endif
1898
1899 #endif /* FSL_I3C_H_ */
1900
