1 /*
2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
3 * Copyright 2016-2023 NXP
4 * All rights reserved.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8 #ifndef FSL_FLEXCAN_H_
9 #define FSL_FLEXCAN_H_
10
11 #include "fsl_common.h"
12
13 /*!
14 * @addtogroup flexcan_driver
15 * @{
16 */
17
18 /******************************************************************************
19 * Definitions
20 *****************************************************************************/
21
22 /*! @name Driver version */
23 /*! @{ */
24 /*! @brief FlexCAN driver version. */
25 #define FSL_FLEXCAN_DRIVER_VERSION (MAKE_VERSION(2, 11, 6))
26 /*! @} */
27
28 #if !(defined(FLEXCAN_WAIT_TIMEOUT) && FLEXCAN_WAIT_TIMEOUT)
29 /* Define to 1000 means keep waiting 1000 times until the flag is assert/deassert. */
30 #define FLEXCAN_WAIT_TIMEOUT (1000U)
31 #endif
32
33 /*! @brief FlexCAN frame length helper macro. */
34 #if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE)
35 #define DLC_LENGTH_DECODE(dlc) (((dlc) <= 8U) ? (dlc) : (((dlc) <= 12U) ? (((dlc)-6U) * 4U) : (((dlc)-11U) * 16U)))
36 #endif
37
38 /*! @brief FlexCAN Frame ID helper macro. */
39 #define FLEXCAN_ID_STD(id) \
40 (((uint32_t)(((uint32_t)(id)) << CAN_ID_STD_SHIFT)) & CAN_ID_STD_MASK) /*!< Standard Frame ID helper macro. */
41 #define FLEXCAN_ID_EXT(id) \
42 (((uint32_t)(((uint32_t)(id)) << CAN_ID_EXT_SHIFT)) & \
43 (CAN_ID_EXT_MASK | CAN_ID_STD_MASK)) /*!< Extend Frame ID helper macro. */
44
45 /*! @brief FlexCAN Rx Message Buffer Mask helper macro. */
46 #define FLEXCAN_RX_MB_STD_MASK(id, rtr, ide) \
47 (((uint32_t)((uint32_t)(rtr) << 31) | (uint32_t)((uint32_t)(ide) << 30)) | \
48 FLEXCAN_ID_STD(id)) /*!< Standard Rx Message Buffer Mask helper macro. */
49 #define FLEXCAN_RX_MB_EXT_MASK(id, rtr, ide) \
50 (((uint32_t)((uint32_t)(rtr) << 31) | (uint32_t)((uint32_t)(ide) << 30)) | \
51 FLEXCAN_ID_EXT(id)) /*!< Extend Rx Message Buffer Mask helper macro. */
52
53 /*! @brief FlexCAN Legacy Rx FIFO Mask helper macro. */
54 #define FLEXCAN_RX_FIFO_STD_MASK_TYPE_A(id, rtr, ide) \
55 (((uint32_t)((uint32_t)(rtr) << 31) | (uint32_t)((uint32_t)(ide) << 30)) | \
56 (FLEXCAN_ID_STD(id) << 1)) /*!< Standard Rx FIFO Mask helper macro Type A helper macro. */
57 #define FLEXCAN_RX_FIFO_STD_MASK_TYPE_B_HIGH(id, rtr, ide) \
58 (((uint32_t)((uint32_t)(rtr) << 31) | (uint32_t)((uint32_t)(ide) << 30)) | \
59 (((uint32_t)(id)&0x7FF) << 19)) /*!< Standard Rx FIFO Mask helper macro Type B upper part helper macro. */
60 #define FLEXCAN_RX_FIFO_STD_MASK_TYPE_B_LOW(id, rtr, ide) \
61 (((uint32_t)((uint32_t)(rtr) << 15) | (uint32_t)((uint32_t)(ide) << 14)) | \
62 (((uint32_t)(id)&0x7FF) << 3)) /*!< Standard Rx FIFO Mask helper macro Type B lower part helper macro. */
63 #define FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_HIGH(id) \
64 (((uint32_t)(id)&0x7F8) << 21) /*!< Standard Rx FIFO Mask helper macro Type C upper part helper macro. */
65 #define FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_MID_HIGH(id) \
66 (((uint32_t)(id)&0x7F8) << 13) /*!< Standard Rx FIFO Mask helper macro Type C mid-upper part helper macro. */
67 #define FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_MID_LOW(id) \
68 (((uint32_t)(id)&0x7F8) << 5) /*!< Standard Rx FIFO Mask helper macro Type C mid-lower part helper macro. */
69 #define FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_LOW(id) \
70 (((uint32_t)(id)&0x7F8) >> 3) /*!< Standard Rx FIFO Mask helper macro Type C lower part helper macro. */
71 #define FLEXCAN_RX_FIFO_EXT_MASK_TYPE_A(id, rtr, ide) \
72 (((uint32_t)((uint32_t)(rtr) << 31) | (uint32_t)((uint32_t)(ide) << 30)) | \
73 (FLEXCAN_ID_EXT(id) << 1)) /*!< Extend Rx FIFO Mask helper macro Type A helper macro. */
74 #define FLEXCAN_RX_FIFO_EXT_MASK_TYPE_B_HIGH(id, rtr, ide) \
75 ( \
76 ((uint32_t)((uint32_t)(rtr) << 31) | (uint32_t)((uint32_t)(ide) << 30)) | \
77 ((FLEXCAN_ID_EXT(id) & 0x1FFF8000) \
78 << 1)) /*!< Extend Rx FIFO Mask helper macro Type B upper part helper macro. */
79 #define FLEXCAN_RX_FIFO_EXT_MASK_TYPE_B_LOW(id, rtr, ide) \
80 (((uint32_t)((uint32_t)(rtr) << 15) | (uint32_t)((uint32_t)(ide) << 14)) | \
81 ((FLEXCAN_ID_EXT(id) & 0x1FFF8000) >> \
82 15)) /*!< Extend Rx FIFO Mask helper macro Type B lower part helper macro. */
83 #define FLEXCAN_RX_FIFO_EXT_MASK_TYPE_C_HIGH(id) \
84 ((FLEXCAN_ID_EXT(id) & 0x1FE00000) << 3) /*!< Extend Rx FIFO Mask helper macro Type C upper part helper macro. */
85 #define FLEXCAN_RX_FIFO_EXT_MASK_TYPE_C_MID_HIGH(id) \
86 ((FLEXCAN_ID_EXT(id) & 0x1FE00000) >> \
87 5) /*!< Extend Rx FIFO Mask helper macro Type C mid-upper part helper macro. */
88 #define FLEXCAN_RX_FIFO_EXT_MASK_TYPE_C_MID_LOW(id) \
89 ((FLEXCAN_ID_EXT(id) & 0x1FE00000) >> \
90 13) /*!< Extend Rx FIFO Mask helper macro Type C mid-lower part helper macro. */
91 #define FLEXCAN_RX_FIFO_EXT_MASK_TYPE_C_LOW(id) \
92 ((FLEXCAN_ID_EXT(id) & 0x1FE00000) >> 21) /*!< Extend Rx FIFO Mask helper macro Type C lower part helper macro. */
93
94 /*! @brief FlexCAN Rx FIFO Filter helper macro. */
95 #define FLEXCAN_RX_FIFO_STD_FILTER_TYPE_A(id, rtr, ide) \
96 FLEXCAN_RX_FIFO_STD_MASK_TYPE_A(id, rtr, ide) /*!< Standard Rx FIFO Filter helper macro Type A helper macro. */
97 #define FLEXCAN_RX_FIFO_STD_FILTER_TYPE_B_HIGH(id, rtr, ide) \
98 FLEXCAN_RX_FIFO_STD_MASK_TYPE_B_HIGH( \
99 id, rtr, ide) /*!< Standard Rx FIFO Filter helper macro Type B upper part helper macro. */
100 #define FLEXCAN_RX_FIFO_STD_FILTER_TYPE_B_LOW(id, rtr, ide) \
101 FLEXCAN_RX_FIFO_STD_MASK_TYPE_B_LOW( \
102 id, rtr, ide) /*!< Standard Rx FIFO Filter helper macro Type B lower part helper macro. */
103 #define FLEXCAN_RX_FIFO_STD_FILTER_TYPE_C_HIGH(id) \
104 FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_HIGH( \
105 id) /*!< Standard Rx FIFO Filter helper macro Type C upper part helper macro. */
106 #define FLEXCAN_RX_FIFO_STD_FILTER_TYPE_C_MID_HIGH(id) \
107 FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_MID_HIGH( \
108 id) /*!< Standard Rx FIFO Filter helper macro Type C mid-upper part helper macro. */
109 #define FLEXCAN_RX_FIFO_STD_FILTER_TYPE_C_MID_LOW(id) \
110 FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_MID_LOW( \
111 id) /*!< Standard Rx FIFO Filter helper macro Type C mid-lower part helper macro. */
112 #define FLEXCAN_RX_FIFO_STD_FILTER_TYPE_C_LOW(id) \
113 FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_LOW( \
114 id) /*!< Standard Rx FIFO Filter helper macro Type C lower part helper macro. */
115 #define FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_A(id, rtr, ide) \
116 FLEXCAN_RX_FIFO_EXT_MASK_TYPE_A(id, rtr, ide) /*!< Extend Rx FIFO Filter helper macro Type A helper macro. */
117 #define FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_B_HIGH(id, rtr, ide) \
118 FLEXCAN_RX_FIFO_EXT_MASK_TYPE_B_HIGH( \
119 id, rtr, ide) /*!< Extend Rx FIFO Filter helper macro Type B upper part helper macro. */
120 #define FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_B_LOW(id, rtr, ide) \
121 FLEXCAN_RX_FIFO_EXT_MASK_TYPE_B_LOW( \
122 id, rtr, ide) /*!< Extend Rx FIFO Filter helper macro Type B lower part helper macro. */
123 #define FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_C_HIGH(id) \
124 FLEXCAN_RX_FIFO_EXT_MASK_TYPE_C_HIGH( \
125 id) /*!< Extend Rx FIFO Filter helper macro Type C upper part helper macro. */
126 #define FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_C_MID_HIGH(id) \
127 FLEXCAN_RX_FIFO_EXT_MASK_TYPE_C_MID_HIGH( \
128 id) /*!< Extend Rx FIFO Filter helper macro Type C mid-upper part helper macro. */
129 #define FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_C_MID_LOW(id) \
130 FLEXCAN_RX_FIFO_EXT_MASK_TYPE_C_MID_LOW( \
131 id) /*!< Extend Rx FIFO Filter helper macro Type C mid-lower part helper macro. */
132 #define FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_C_LOW(id) \
133 FLEXCAN_RX_FIFO_EXT_MASK_TYPE_C_LOW(id) /*!< Extend Rx FIFO Filter helper macro Type C lower part helper macro. */
134
135 #if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO)
136 /*! @brief FlexCAN Enhanced Rx FIFO Filter and Mask helper macro. */
137 #define ENHANCED_RX_FIFO_FSCH(x) (((uint32_t)(((uint32_t)(x)) << 30)) & 0xC0000000U)
138 #define RTR_STD_HIGH(x) (((uint32_t)(((uint32_t)(x)) << 27)) & 0x08000000U)
139 #define RTR_STD_LOW(x) (((uint32_t)(((uint32_t)(x)) << 11)) & 0x00000800U)
140 #define RTR_EXT(x) (((uint32_t)(((uint32_t)(x)) << 29)) & 0x40000000U)
141 #define ID_STD_LOW(id) (((uint32_t)id) & 0x7FFU)
142 #define ID_STD_HIGH(id) (((uint32_t)(((uint32_t)(id)) << 16)) & 0x07FF0000U)
143 #define ID_EXT(id) (((uint32_t)id) & 0x1FFFFFFFU)
144
145 /*! Standard ID filter element with filter + mask scheme. */
146 #define FLEXCAN_ENHANCED_RX_FIFO_STD_MASK_AND_FILTER(id, rtr, id_mask, rtr_mask) \
147 (ENHANCED_RX_FIFO_FSCH(0x0) | RTR_STD_HIGH(rtr) | ID_STD_HIGH(id) | RTR_STD_LOW(rtr_mask) | ID_STD_LOW(id_mask))
148 /*! Standard ID filter element with filter range. */
149 #define FLEXCAN_ENHANCED_RX_FIFO_STD_FILTER_WITH_RANGE(id_upper, rtr, id_lower, rtr_mask) \
150 (ENHANCED_RX_FIFO_FSCH(0x1) | RTR_STD_HIGH(rtr) | ID_STD_HIGH(id_upper) | RTR_STD_LOW(rtr_mask) | \
151 ID_STD_LOW(id_lower))
152 /*! Standard ID filter element with two filters without masks. */
153 #define FLEXCAN_ENHANCED_RX_FIFO_STD_TWO_FILTERS(id1, rtr1, id2, rtr2) \
154 (ENHANCED_RX_FIFO_FSCH(0x2) | RTR_STD_HIGH(rtr1) | ID_STD_HIGH(id1) | RTR_STD_LOW(rtr2) | ID_STD_LOW(id2))
155 /*! Extended ID filter element with filter + mask scheme low word. */
156 #define FLEXCAN_ENHANCED_RX_FIFO_EXT_MASK_AND_FILTER_LOW(id, rtr) \
157 (ENHANCED_RX_FIFO_FSCH(0x0) | RTR_EXT(rtr) | ID_EXT(id))
158 /*! Extended ID filter element with filter + mask scheme high word. */
159 #define FLEXCAN_ENHANCED_RX_FIFO_EXT_MASK_AND_FILTER_HIGH(id_mask, rtr_mask) \
160 (ENHANCED_RX_FIFO_FSCH(0x0) | RTR_EXT(rtr_mask) | ID_EXT(id_mask))
161 /*! Extended ID filter element with range scheme low word. */
162 #define FLEXCAN_ENHANCED_RX_FIFO_EXT_FILTER_WITH_RANGE_LOW(id_upper, rtr) \
163 (ENHANCED_RX_FIFO_FSCH(0x1) | RTR_EXT(rtr) | ID_EXT(id_upper))
164 /*! Extended ID filter element with range scheme high word. */
165 #define FLEXCAN_ENHANCED_RX_FIFO_EXT_FILTER_WITH_RANGE_HIGH(id_lower, rtr_mask) \
166 (ENHANCED_RX_FIFO_FSCH(0x1) | RTR_EXT(rtr_mask) | ID_EXT(id_lower))
167 /*! Extended ID filter element with two filters without masks low word. */
168 #define FLEXCAN_ENHANCED_RX_FIFO_EXT_TWO_FILTERS_LOW(id2, rtr2) \
169 (ENHANCED_RX_FIFO_FSCH(0x2) | RTR_EXT(rtr2) | ID_EXT(id2))
170 /*! Extended ID filter element with two filters without masks high word. */
171 #define FLEXCAN_ENHANCED_RX_FIFO_EXT_TWO_FILTERS_HIGH(id1, rtr1) \
172 (ENHANCED_RX_FIFO_FSCH(0x2) | RTR_EXT(rtr1) | ID_EXT(id1))
173 #endif
174
175 #if (defined(FSL_FEATURE_FLEXCAN_HAS_PN_MODE) && FSL_FEATURE_FLEXCAN_HAS_PN_MODE)
176 /*! @brief FlexCAN Pretended Networking ID Mask helper macro. */
177 #define FLEXCAN_PN_STD_MASK(id, rtr) \
178 ((uint32_t)((uint32_t)(rtr) << CAN_FLT_ID1_FLT_RTR_SHIFT) | \
179 FLEXCAN_ID_STD(id)) /*!< Standard Rx Message Buffer Mask helper macro. */
180 #define FLEXCAN_PN_EXT_MASK(id, rtr) \
181 ((uint32_t)CAN_FLT_ID1_FLT_IDE_MASK | (uint32_t)((uint32_t)(rtr) << CAN_FLT_ID1_FLT_RTR_SHIFT) | \
182 FLEXCAN_ID_EXT(id)) /*!< Extend Rx Message Buffer Mask helper macro. */
183 #endif
184
185 /*! @brief FlexCAN interrupt/status flag helper macro. */
186 #if (defined(FSL_FEATURE_FLEXCAN_HAS_PN_MODE) && FSL_FEATURE_FLEXCAN_HAS_PN_MODE)
187 #define FLEXCAN_PN_INT_MASK(x) (((uint64_t)(((uint64_t)(x)) << 32)) & 0x3000000000000U)
188 #define FLEXCAN_PN_INT_UNMASK(x) (((uint32_t)(((uint64_t)(x)) >> 32)) & 0x00030000U)
189 #define FLEXCAN_PN_STATUS_MASK(x) (((uint64_t)(((uint64_t)(x)) << 16)) & 0x300000000U)
190 #define FLEXCAN_PN_STATUS_UNMASK(x) (((uint32_t)(((uint64_t)(x)) >> 16)) & 0x00030000U)
191 #endif
192 #if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO)
193 #define FLEXCAN_EFIFO_INT_MASK(x) (((uint64_t)(((uint64_t)(x)) << 32)) & 0xF000000000000000U)
194 #define FLEXCAN_EFIFO_INT_UNMASK(x) (((uint32_t)(((uint64_t)(x)) >> 32)) & 0xF0000000U)
195 #define FLEXCAN_EFIFO_STATUS_MASK(x) (((uint64_t)(((uint64_t)(x)) << 32)) & 0xF003000000000000U)
196 #define FLEXCAN_EFIFO_STATUS_UNMASK(x) (((uint32_t)(((uint64_t)(x)) >> 32)) & 0xF0030000U)
197 #endif
198 #if (defined(FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) && FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL)
199 #define FLEXCAN_MECR_INT_MASK(x) (((uint64_t)(((uint64_t)(x)) << 16)) & 0xD00000000U)
200 #define FLEXCAN_MECR_INT_UNMASK(x) (((uint32_t)(((uint64_t)(x)) >> 16)) & 0x000D0000U)
201 #define FLEXCAN_MECR_STATUS_MASK(x) (((uint64_t)(((uint64_t)(x)) << 34)) & 0x34003400000000U)
202 #define FLEXCAN_MECR_STATUS_UNMASK(x) (((uint32_t)(((uint64_t)(x)) >> 34)) & 0x000D000DU)
203 #endif
204
205 #if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE)
206 #define FLEXCAN_ERROR_AND_STATUS_INIT_FLAG \
207 ((uint32_t)kFLEXCAN_ErrorOverrunFlag | (uint32_t)kFLEXCAN_FDErrorIntFlag | (uint32_t)kFLEXCAN_BusoffDoneIntFlag | \
208 (uint32_t)kFLEXCAN_TxWarningIntFlag | (uint32_t)kFLEXCAN_RxWarningIntFlag | (uint32_t)kFLEXCAN_BusOffIntFlag | \
209 (uint32_t)kFLEXCAN_ErrorIntFlag | FLEXCAN_MEMORY_ERROR_INIT_FLAG)
210 #else
211 #define FLEXCAN_ERROR_AND_STATUS_INIT_FLAG \
212 ((uint32_t)kFLEXCAN_TxWarningIntFlag | (uint32_t)kFLEXCAN_RxWarningIntFlag | (uint32_t)kFLEXCAN_BusOffIntFlag | \
213 (uint32_t)kFLEXCAN_ErrorIntFlag | FLEXCAN_MEMORY_ERROR_INIT_FLAG)
214 #endif
215 #if (defined(FSL_FEATURE_FLEXCAN_HAS_PN_MODE) && FSL_FEATURE_FLEXCAN_HAS_PN_MODE)
216 #if !(defined(FSL_FEATURE_FLEXCAN_HAS_NO_SLFWAK_SUPPORT) && FSL_FEATURE_FLEXCAN_HAS_NO_SLFWAK_SUPPORT)
217 #define FLEXCAN_WAKE_UP_FLAG \
218 ((uint32_t)kFLEXCAN_WakeUpIntFlag | (uint64_t)kFLEXCAN_PNMatchIntFlag | (uint64_t)kFLEXCAN_PNTimeoutIntFlag)
219 #endif
220 #else
221 #if !(defined(FSL_FEATURE_FLEXCAN_HAS_NO_SLFWAK_SUPPORT) && FSL_FEATURE_FLEXCAN_HAS_NO_SLFWAK_SUPPORT)
222 #define FLEXCAN_WAKE_UP_FLAG ((uint32_t)kFLEXCAN_WakeUpIntFlag)
223 #endif
224 #endif
225 #if (defined(FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) && FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL)
226 #define FLEXCAN_MEMORY_ERROR_INIT_FLAG ((uint64_t)kFLEXCAN_AllMemoryErrorFlag)
227 #else
228 #define FLEXCAN_MEMORY_ERROR_INIT_FLAG (0U)
229 #endif
230
231 #if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO)
232 #define FLEXCAN_MEMORY_ENHANCED_RX_FIFO_INIT_FLAG \
233 ((uint64_t)kFLEXCAN_ERxFifoUnderflowIntFlag | (uint64_t)kFLEXCAN_ERxFifoOverflowIntFlag | \
234 (uint64_t)kFLEXCAN_ERxFifoWatermarkIntFlag | (uint64_t)kFLEXCAN_ERxFifoDataAvlIntFlag)
235 #endif
236 /*! @brief FlexCAN Enhanced Rx FIFO base address helper macro. */
237 #if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO)
238 #define E_RX_FIFO(base) ((uintptr_t)(base) + 0x2000U)
239 #else
240 #define FLEXCAN_MEMORY_ENHANCED_RX_FIFO_INIT_FLAG (0U)
241 #endif
242 /*! @brief FlexCAN transfer status. */
243 enum
244 {
245 kStatus_FLEXCAN_TxBusy = MAKE_STATUS(kStatusGroup_FLEXCAN, 0), /*!< Tx Message Buffer is Busy. */
246 kStatus_FLEXCAN_TxIdle = MAKE_STATUS(kStatusGroup_FLEXCAN, 1), /*!< Tx Message Buffer is Idle. */
247 kStatus_FLEXCAN_TxSwitchToRx = MAKE_STATUS(
248 kStatusGroup_FLEXCAN, 2), /*!< Remote Message is send out and Message buffer changed to Receive one. */
249 kStatus_FLEXCAN_RxBusy = MAKE_STATUS(kStatusGroup_FLEXCAN, 3), /*!< Rx Message Buffer is Busy. */
250 kStatus_FLEXCAN_RxIdle = MAKE_STATUS(kStatusGroup_FLEXCAN, 4), /*!< Rx Message Buffer is Idle. */
251 kStatus_FLEXCAN_RxOverflow = MAKE_STATUS(kStatusGroup_FLEXCAN, 5), /*!< Rx Message Buffer is Overflowed. */
252 kStatus_FLEXCAN_RxFifoBusy = MAKE_STATUS(kStatusGroup_FLEXCAN, 6), /*!< Rx Message FIFO is Busy. */
253 kStatus_FLEXCAN_RxFifoIdle = MAKE_STATUS(kStatusGroup_FLEXCAN, 7), /*!< Rx Message FIFO is Idle. */
254 kStatus_FLEXCAN_RxFifoOverflow = MAKE_STATUS(kStatusGroup_FLEXCAN, 8), /*!< Rx Message FIFO is overflowed. */
255 kStatus_FLEXCAN_RxFifoWarning = MAKE_STATUS(kStatusGroup_FLEXCAN, 9), /*!< Rx Message FIFO is almost overflowed. */
256 kStatus_FLEXCAN_RxFifoDisabled =
257 MAKE_STATUS(kStatusGroup_FLEXCAN, 10), /*!< Rx Message FIFO is disabled during reading. */
258 kStatus_FLEXCAN_ErrorStatus = MAKE_STATUS(kStatusGroup_FLEXCAN, 11), /*!< FlexCAN Module Error and Status. */
259 kStatus_FLEXCAN_WakeUp = MAKE_STATUS(kStatusGroup_FLEXCAN, 12), /*!< FlexCAN is waken up from STOP mode. */
260 kStatus_FLEXCAN_UnHandled = MAKE_STATUS(kStatusGroup_FLEXCAN, 13), /*!< UnHadled Interrupt asserted. */
261 kStatus_FLEXCAN_RxRemote = MAKE_STATUS(kStatusGroup_FLEXCAN, 14), /*!< Rx Remote Message Received in Mail box. */
262 #if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO)
263 kStatus_FLEXCAN_RxFifoUnderflow =
264 MAKE_STATUS(kStatusGroup_FLEXCAN, 15), /*!< Enhanced Rx Message FIFO is underflow. */
265 #endif
266 };
267
268 /*! @brief FlexCAN frame format. */
269 typedef enum _flexcan_frame_format
270 {
271 kFLEXCAN_FrameFormatStandard = 0x0U, /*!< Standard frame format attribute. */
272 kFLEXCAN_FrameFormatExtend = 0x1U, /*!< Extend frame format attribute. */
273 } flexcan_frame_format_t;
274
275 /*! @brief FlexCAN frame type. */
276 typedef enum _flexcan_frame_type
277 {
278 kFLEXCAN_FrameTypeData = 0x0U, /*!< Data frame type attribute. */
279 kFLEXCAN_FrameTypeRemote = 0x1U, /*!< Remote frame type attribute. */
280 } flexcan_frame_type_t;
281
282 /*! @brief FlexCAN clock source.
283 * @deprecated Do not use the kFLEXCAN_ClkSrcOs. It has been superceded kFLEXCAN_ClkSrc0
284 * @deprecated Do not use the kFLEXCAN_ClkSrcPeri. It has been superceded kFLEXCAN_ClkSrc1
285 */
286 typedef enum _flexcan_clock_source
287 {
288 kFLEXCAN_ClkSrcOsc = 0x0U, /*!< FlexCAN Protocol Engine clock from Oscillator. */
289 kFLEXCAN_ClkSrcPeri = 0x1U, /*!< FlexCAN Protocol Engine clock from Peripheral Clock. */
290 kFLEXCAN_ClkSrc0 = 0x0U, /*!< FlexCAN Protocol Engine clock selected by user as SRC == 0. */
291 kFLEXCAN_ClkSrc1 = 0x1U, /*!< FlexCAN Protocol Engine clock selected by user as SRC == 1. */
292 } flexcan_clock_source_t;
293
294 #if !(defined(FSL_FEATURE_FLEXCAN_HAS_NO_WAKSRC_SUPPORT) && FSL_FEATURE_FLEXCAN_HAS_NO_WAKSRC_SUPPORT)
295 /*! @brief FlexCAN wake up source. */
296 typedef enum _flexcan_wake_up_source
297 {
298 kFLEXCAN_WakeupSrcUnfiltered = 0x0U, /*!< FlexCAN uses unfiltered Rx input to detect edge. */
299 kFLEXCAN_WakeupSrcFiltered = 0x1U, /*!< FlexCAN uses filtered Rx input to detect edge. */
300 } flexcan_wake_up_source_t;
301 #endif
302
303 /*! @brief FlexCAN Rx Fifo Filter type. */
304 typedef enum _flexcan_rx_fifo_filter_type
305 {
306 kFLEXCAN_RxFifoFilterTypeA = 0x0U, /*!< One full ID (standard and extended) per ID Filter element. */
307 kFLEXCAN_RxFifoFilterTypeB =
308 0x1U, /*!< Two full standard IDs or two partial 14-bit ID slices per ID Filter Table element. */
309 kFLEXCAN_RxFifoFilterTypeC =
310 0x2U, /*!< Four partial 8-bit Standard or extended ID slices per ID Filter Table element. */
311 kFLEXCAN_RxFifoFilterTypeD = 0x3U, /*!< All frames rejected. */
312 } flexcan_rx_fifo_filter_type_t;
313
314 #if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE)
315 /*!
316 * @brief FlexCAN Message Buffer Payload size.
317 */
318 typedef enum _flexcan_mb_size
319 {
320 kFLEXCAN_8BperMB = 0x0U, /*!< Selects 8 bytes per Message Buffer. */
321 kFLEXCAN_16BperMB = 0x1U, /*!< Selects 16 bytes per Message Buffer. */
322 kFLEXCAN_32BperMB = 0x2U, /*!< Selects 32 bytes per Message Buffer. */
323 kFLEXCAN_64BperMB = 0x3U, /*!< Selects 64 bytes per Message Buffer. */
324 } flexcan_mb_size_t;
325
326 /*!
327 * @brief FlexCAN CAN FD frame supporting data length (available DLC values).
328 *
329 * For Tx, when the Data size corresponding to DLC value stored in the MB selected for transmission is larger than the
330 * MB Payload size, FlexCAN adds the necessary number of bytes with constant 0xCC pattern to complete the expected DLC.
331 * For Rx, when the Data size corresponding to DLC value received from the CAN bus is larger than the MB Payload size,
332 * the high order bytes that do not fit the Payload size will lose.
333 */
334 enum _flexcan_fd_frame_length
335 {
336 kFLEXCAN_0BperFrame = 0x0U, /*!< Frame contains 0 valid data bytes. */
337 kFLEXCAN_1BperFrame, /*!< Frame contains 1 valid data bytes. */
338 kFLEXCAN_2BperFrame, /*!< Frame contains 2 valid data bytes. */
339 kFLEXCAN_3BperFrame, /*!< Frame contains 3 valid data bytes. */
340 kFLEXCAN_4BperFrame, /*!< Frame contains 4 valid data bytes. */
341 kFLEXCAN_5BperFrame, /*!< Frame contains 5 valid data bytes. */
342 kFLEXCAN_6BperFrame, /*!< Frame contains 6 valid data bytes. */
343 kFLEXCAN_7BperFrame, /*!< Frame contains 7 valid data bytes. */
344 kFLEXCAN_8BperFrame, /*!< Frame contains 8 valid data bytes. */
345 kFLEXCAN_12BperFrame, /*!< Frame contains 12 valid data bytes. */
346 kFLEXCAN_16BperFrame, /*!< Frame contains 16 valid data bytes. */
347 kFLEXCAN_20BperFrame, /*!< Frame contains 20 valid data bytes. */
348 kFLEXCAN_24BperFrame, /*!< Frame contains 24 valid data bytes. */
349 kFLEXCAN_32BperFrame, /*!< Frame contains 32 valid data bytes. */
350 kFLEXCAN_48BperFrame, /*!< Frame contains 48 valid data bytes. */
351 kFLEXCAN_64BperFrame, /*!< Frame contains 64 valid data bytes. */
352 };
353 #endif
354
355 #if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO)
356 /*! @brief FlexCAN Enhanced Rx Fifo DMA transfer per read length enumerations. */
357 typedef enum _flexcan_efifo_dma_per_read_length
358 {
359 kFLEXCAN_1WordPerRead = 0x0U, /*!< Transfer 1 32-bit words (CS).*/
360 kFLEXCAN_2WordPerRead, /*!< Transfer 2 32-bit words (CS + ID).*/
361 kFLEXCAN_3WordPerRead, /*!< Transfer 3 32-bit words (CS + ID + 1~4 bytes data).*/
362 kFLEXCAN_4WordPerRead, /*!< Transfer 4 32-bit words (CS + ID + 5~8 bytes data).*/
363 kFLEXCAN_5WordPerRead, /*!< Transfer 5 32-bit words (CS + ID + 9~12 bytes data).*/
364 kFLEXCAN_6WordPerRead, /*!< Transfer 6 32-bit words (CS + ID + 13~16 bytes data).*/
365 kFLEXCAN_7WordPerRead, /*!< Transfer 7 32-bit words (CS + ID + 17~20 bytes data).*/
366 kFLEXCAN_8WordPerRead, /*!< Transfer 8 32-bit words (CS + ID + 21~24 bytes data).*/
367 kFLEXCAN_9WordPerRead, /*!< Transfer 9 32-bit words (CS + ID + 25~28 bytes data).*/
368 kFLEXCAN_10WordPerRead, /*!< Transfer 10 32-bit words (CS + ID + 29~32 bytes data).*/
369 kFLEXCAN_11WordPerRead, /*!< Transfer 11 32-bit words (CS + ID + 33~36 bytes data).*/
370 kFLEXCAN_12WordPerRead, /*!< Transfer 12 32-bit words (CS + ID + 37~40 bytes data).*/
371 kFLEXCAN_13WordPerRead, /*!< Transfer 13 32-bit words (CS + ID + 41~44 bytes data).*/
372 kFLEXCAN_14WordPerRead, /*!< Transfer 14 32-bit words (CS + ID + 45~48 bytes data).*/
373 kFLEXCAN_15WordPerRead, /*!< Transfer 15 32-bit words (CS + ID + 49~52 bytes data).*/
374 kFLEXCAN_16WordPerRead, /*!< Transfer 16 32-bit words (CS + ID + 53~56 bytes data).*/
375 kFLEXCAN_17WordPerRead, /*!< Transfer 17 32-bit words (CS + ID + 57~60 bytes data).*/
376 kFLEXCAN_18WordPerRead, /*!< Transfer 18 32-bit words (CS + ID + 61~64 bytes data).*/
377 kFLEXCAN_19WordPerRead /*!< Transfer 19 32-bit words (CS + ID + 64 bytes data + ID HIT).*/
378 } flexcan_efifo_dma_per_read_length_t;
379 #endif
380
381 /*!
382 * @brief FlexCAN Enhanced/Legacy Rx FIFO priority.
383 *
384 * The matching process starts from the Rx MB(or Enhanced/Legacy Rx FIFO) with higher priority.
385 * If no MB(or Enhanced/Legacy Rx FIFO filter) is satisfied, the matching process goes on with
386 * the Enhanced/Legacy Rx FIFO(or Rx MB) with lower priority.
387 */
388 typedef enum _flexcan_rx_fifo_priority
389 {
390 kFLEXCAN_RxFifoPrioLow = 0x0U, /*!< Matching process start from Rx Message Buffer first. */
391 kFLEXCAN_RxFifoPrioHigh = 0x1U, /*!< Matching process start from Enhanced/Legacy Rx FIFO first. */
392 } flexcan_rx_fifo_priority_t;
393
394 /*!
395 * @brief FlexCAN interrupt enable enumerations.
396 *
397 * This provides constants for the FlexCAN interrupt enable enumerations for use in the FlexCAN functions.
398 * @note FlexCAN Message Buffers and Legacy Rx FIFO interrupts not included in.
399 */
400 enum _flexcan_interrupt_enable
401 {
402 kFLEXCAN_BusOffInterruptEnable = CAN_CTRL1_BOFFMSK_MASK, /*!< Bus Off interrupt, use bit 15. */
403 kFLEXCAN_ErrorInterruptEnable = CAN_CTRL1_ERRMSK_MASK, /*!< CAN Error interrupt, use bit 14. */
404 kFLEXCAN_TxWarningInterruptEnable = CAN_CTRL1_TWRNMSK_MASK, /*!< Tx Warning interrupt, use bit 11. */
405 kFLEXCAN_RxWarningInterruptEnable = CAN_CTRL1_RWRNMSK_MASK, /*!< Rx Warning interrupt, use bit 10. */
406 #if !(defined(FSL_FEATURE_FLEXCAN_HAS_NO_WAKMSK_SUPPORT) && FSL_FEATURE_FLEXCAN_HAS_NO_WAKMSK_SUPPORT)
407 kFLEXCAN_WakeUpInterruptEnable = CAN_MCR_WAKMSK_MASK, /*!< Self Wake Up interrupt, use bit 26. */
408 #endif
409 #if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE)
410 kFLEXCAN_FDErrorInterruptEnable = CAN_CTRL2_ERRMSK_FAST_MASK, /*!< CAN FD Error interrupt, use bit 31. */
411 #endif
412 #if (defined(FSL_FEATURE_FLEXCAN_HAS_PN_MODE) && FSL_FEATURE_FLEXCAN_HAS_PN_MODE)
413 /*! PN Match Wake Up interrupt, use high word bit 17. */
414 kFLEXCAN_PNMatchWakeUpInterruptEnable = FLEXCAN_PN_INT_MASK(CAN_CTRL1_PN_WTOF_MSK_MASK),
415 /*! PN Timeout Wake Up interrupt, use high word bit 16. */
416 kFLEXCAN_PNTimeoutWakeUpInterruptEnable = FLEXCAN_PN_INT_MASK(CAN_CTRL1_PN_WUMF_MSK_MASK),
417 #endif
418 #if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO)
419 /*!< Enhanced Rx FIFO Underflow interrupt, use high word bit 31. */
420 kFLEXCAN_ERxFifoUnderflowInterruptEnable = FLEXCAN_EFIFO_INT_MASK(CAN_ERFIER_ERFUFWIE_MASK),
421 /*!< Enhanced Rx FIFO Overflow interrupt, use high word bit 30. */
422 kFLEXCAN_ERxFifoOverflowInterruptEnable = FLEXCAN_EFIFO_INT_MASK(CAN_ERFIER_ERFOVFIE_MASK),
423 /*!< Enhanced Rx FIFO Watermark interrupt, use high word bit 29. */
424 kFLEXCAN_ERxFifoWatermarkInterruptEnable = FLEXCAN_EFIFO_INT_MASK(CAN_ERFIER_ERFWMIIE_MASK),
425 /*!< Enhanced Rx FIFO Data Avilable interrupt, use high word bit 28. */
426 kFLEXCAN_ERxFifoDataAvlInterruptEnable = FLEXCAN_EFIFO_INT_MASK(CAN_ERFIER_ERFDAIE_MASK),
427 #endif
428 #if (defined(FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) && FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL)
429 #if !(defined(FSL_FEATURE_FLEXCAN_HAS_NO_HANCEI_SUPPORT) && FSL_FEATURE_FLEXCAN_HAS_NO_HANCEI_SUPPORT)
430 /*! Host Access With Non-Correctable Errors interrupt, use high word bit 0. */
431 kFLEXCAN_HostAccessNCErrorInterruptEnable = FLEXCAN_MECR_INT_MASK(CAN_MECR_HANCEI_MSK_MASK),
432 #endif
433 #if !(defined(FSL_FEATURE_FLEXCAN_HAS_NO_FANCEI_SUPPORT) && FSL_FEATURE_FLEXCAN_HAS_NO_FANCEI_SUPPORT)
434 /*! FlexCAN Access With Non-Correctable Errors interrupt, use high word bit 2. */
435 kFLEXCAN_FlexCanAccessNCErrorInterruptEnable = FLEXCAN_MECR_INT_MASK(CAN_MECR_FANCEI_MSK_MASK),
436 #endif
437 #if !(defined(FSL_FEATURE_FLEXCAN_HAS_NO_CEI_SUPPORT) && FSL_FEATURE_FLEXCAN_HAS_NO_CEI_SUPPORT)
438 /*! Host or FlexCAN Access With Correctable Errors interrupt, use high word bit 3. */
439 kFLEXCAN_HostOrFlexCanCErrorInterruptEnable = FLEXCAN_MECR_INT_MASK(CAN_MECR_CEI_MSK_MASK),
440 #endif
441 #endif
442 };
443
444 /*!
445 * @brief FlexCAN status flags.
446 *
447 * This provides constants for the FlexCAN status flags for use in the FlexCAN functions.
448 * @note The CPU read action clears the bits corresponding to the FlEXCAN_ErrorFlag macro, therefore user need to
449 * read status flags and distinguish which error is occur using @ref _flexcan_error_flags enumerations.
450 */
451 enum _flexcan_flags
452 {
453 #if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE)
454 kFLEXCAN_ErrorOverrunFlag = CAN_ESR1_ERROVR_MASK, /*!< Error Overrun Status. */
455 kFLEXCAN_FDErrorIntFlag = CAN_ESR1_ERRINT_FAST_MASK, /*!< CAN FD Error Interrupt Flag. */
456 kFLEXCAN_BusoffDoneIntFlag = CAN_ESR1_BOFFDONEINT_MASK, /*!< Bus Off process completed Interrupt Flag. */
457 #endif
458 kFLEXCAN_SynchFlag = CAN_ESR1_SYNCH_MASK, /*!< CAN Synchronization Status. */
459 kFLEXCAN_TxWarningIntFlag = CAN_ESR1_TWRNINT_MASK, /*!< Tx Warning Interrupt Flag. */
460 kFLEXCAN_RxWarningIntFlag = CAN_ESR1_RWRNINT_MASK, /*!< Rx Warning Interrupt Flag. */
461 kFLEXCAN_IdleFlag = CAN_ESR1_IDLE_MASK, /*!< FlexCAN In IDLE Status. */
462 kFLEXCAN_FaultConfinementFlag = CAN_ESR1_FLTCONF_MASK, /*!< FlexCAN Fault Confinement State. */
463 kFLEXCAN_TransmittingFlag = CAN_ESR1_TX_MASK, /*!< FlexCAN In Transmission Status. */
464 kFLEXCAN_ReceivingFlag = CAN_ESR1_RX_MASK, /*!< FlexCAN In Reception Status. */
465 kFLEXCAN_BusOffIntFlag = CAN_ESR1_BOFFINT_MASK, /*!< Bus Off Interrupt Flag. */
466 kFLEXCAN_ErrorIntFlag = CAN_ESR1_ERRINT_MASK, /*!< CAN Error Interrupt Flag. */
467 #if !(defined(FSL_FEATURE_FLEXCAN_HAS_NO_SLFWAK_SUPPORT) && FSL_FEATURE_FLEXCAN_HAS_NO_SLFWAK_SUPPORT)
468 kFLEXCAN_WakeUpIntFlag = CAN_ESR1_WAKINT_MASK, /*!< Self Wake-Up Interrupt Flag. */
469 #endif
470 kFLEXCAN_ErrorFlag =
471 (uint32_t)(/*!< All FlexCAN Read Clear Error Status. */
472 #if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE)
473 CAN_ESR1_STFERR_FAST_MASK | CAN_ESR1_FRMERR_FAST_MASK | CAN_ESR1_CRCERR_FAST_MASK |
474 CAN_ESR1_BIT0ERR_FAST_MASK | CAN_ESR1_BIT1ERR_FAST_MASK | CAN_ESR1_ERROVR_MASK |
475 #endif
476 CAN_ESR1_TXWRN_MASK | CAN_ESR1_RXWRN_MASK | CAN_ESR1_BIT1ERR_MASK | CAN_ESR1_BIT0ERR_MASK |
477 CAN_ESR1_ACKERR_MASK | CAN_ESR1_CRCERR_MASK | CAN_ESR1_FRMERR_MASK | CAN_ESR1_STFERR_MASK),
478 #if (defined(FSL_FEATURE_FLEXCAN_HAS_PN_MODE) && FSL_FEATURE_FLEXCAN_HAS_PN_MODE)
479 kFLEXCAN_PNMatchIntFlag = FLEXCAN_PN_STATUS_MASK(CAN_WU_MTC_WUMF_MASK), /*!< PN Matching Event Interrupt Flag. */
480 kFLEXCAN_PNTimeoutIntFlag = FLEXCAN_PN_STATUS_MASK(CAN_WU_MTC_WTOF_MASK), /*!< PN Timeout Event Interrupt Flag. */
481 #endif
482 #if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO)
483 kFLEXCAN_ERxFifoUnderflowIntFlag =
484 FLEXCAN_EFIFO_STATUS_MASK(CAN_ERFSR_ERFUFW_MASK), /*!< Enhanced Rx FIFO underflow Interrupt Flag. */
485 kFLEXCAN_ERxFifoOverflowIntFlag =
486 FLEXCAN_EFIFO_STATUS_MASK(CAN_ERFSR_ERFOVF_MASK), /*!< Enhanced Rx FIFO overflow Interrupt Flag. */
487 kFLEXCAN_ERxFifoWatermarkIntFlag =
488 FLEXCAN_EFIFO_STATUS_MASK(CAN_ERFSR_ERFWMI_MASK), /*!< Enhanced Rx FIFO watermark Interrupt Flag. */
489 kFLEXCAN_ERxFifoDataAvlIntFlag =
490 FLEXCAN_EFIFO_STATUS_MASK(CAN_ERFSR_ERFDA_MASK), /*!< Enhanced Rx FIFO data available Interrupt Flag. */
491 kFLEXCAN_ERxFifoEmptyFlag = FLEXCAN_EFIFO_STATUS_MASK(CAN_ERFSR_ERFE_MASK), /*!< Enhanced Rx FIFO empty status. */
492 kFLEXCAN_ERxFifoFullFlag = FLEXCAN_EFIFO_STATUS_MASK(CAN_ERFSR_ERFF_MASK), /*!< Enhanced Rx FIFO full status. */
493 #endif
494 #if (defined(FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) && FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL)
495 /*! Host Access With Non-Correctable Error Interrupt Flag. */
496 kFLEXCAN_HostAccessNonCorrectableErrorIntFlag = FLEXCAN_MECR_INT_MASK(CAN_ERRSR_HANCEIF_MASK),
497 /*! FlexCAN Access With Non-Correctable Error Interrupt Flag. */
498 kFLEXCAN_FlexCanAccessNonCorrectableErrorIntFlag = FLEXCAN_MECR_INT_MASK(CAN_ERRSR_FANCEIF_MASK),
499 /*! Correctable Error Interrupt Flag. */
500 kFLEXCAN_CorrectableErrorIntFlag = FLEXCAN_MECR_INT_MASK(CAN_ERRSR_CEIF_MASK),
501 /*! Host Access With Non-Correctable Error Interrupt Overrun Flag. */
502 kFLEXCAN_HostAccessNonCorrectableErrorOverrunFlag = FLEXCAN_MECR_INT_MASK(CAN_ERRSR_HANCEIOF_MASK),
503 /*! FlexCAN Access With Non-Correctable Error Interrupt Overrun Flag. */
504 kFLEXCAN_FlexCanAccessNonCorrectableErrorOverrunFlag = FLEXCAN_MECR_INT_MASK(CAN_ERRSR_FANCEIOF_MASK),
505 /*! Correctable Error Interrupt Overrun Flag. */
506 kFLEXCAN_CorrectableErrorOverrunFlag = FLEXCAN_MECR_INT_MASK(CAN_ERRSR_CEIOF_MASK),
507 /*! All Memory Error Flags. */
508 kFLEXCAN_AllMemoryErrorFlag =
509 (kFLEXCAN_HostAccessNonCorrectableErrorIntFlag | kFLEXCAN_FlexCanAccessNonCorrectableErrorIntFlag |
510 kFLEXCAN_CorrectableErrorIntFlag | kFLEXCAN_HostAccessNonCorrectableErrorOverrunFlag |
511 kFLEXCAN_FlexCanAccessNonCorrectableErrorOverrunFlag | kFLEXCAN_CorrectableErrorOverrunFlag)
512 #endif
513 };
514
515 /*!
516 * @brief FlexCAN error status flags.
517 *
518 * The FlexCAN Error Status enumerations is used to report current error of the FlexCAN bus.
519 * This enumerations should be used with KFLEXCAN_ErrorFlag in @ref _flexcan_flags enumerations
520 * to ditermine which error is generated.
521 */
522 enum _flexcan_error_flags
523 {
524 #if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE)
525 kFLEXCAN_FDStuffingError = CAN_ESR1_STFERR_FAST_MASK, /*!< Stuffing Error. */
526 kFLEXCAN_FDFormError = CAN_ESR1_FRMERR_FAST_MASK, /*!< Form Error. */
527 kFLEXCAN_FDCrcError = CAN_ESR1_CRCERR_FAST_MASK, /*!< Cyclic Redundancy Check Error. */
528 kFLEXCAN_FDBit0Error = CAN_ESR1_BIT0ERR_FAST_MASK, /*!< Unable to send dominant bit. */
529 kFLEXCAN_FDBit1Error = (int)CAN_ESR1_BIT1ERR_FAST_MASK, /*!< Unable to send recessive bit. */
530 #endif
531 kFLEXCAN_TxErrorWarningFlag = CAN_ESR1_TXWRN_MASK, /*!< Tx Error Warning Status. */
532 kFLEXCAN_RxErrorWarningFlag = CAN_ESR1_RXWRN_MASK, /*!< Rx Error Warning Status. */
533 kFLEXCAN_StuffingError = CAN_ESR1_STFERR_MASK, /*!< Stuffing Error. */
534 kFLEXCAN_FormError = CAN_ESR1_FRMERR_MASK, /*!< Form Error. */
535 kFLEXCAN_CrcError = CAN_ESR1_CRCERR_MASK, /*!< Cyclic Redundancy Check Error. */
536 kFLEXCAN_AckError = CAN_ESR1_ACKERR_MASK, /*!< Received no ACK on transmission. */
537 kFLEXCAN_Bit0Error = CAN_ESR1_BIT0ERR_MASK, /*!< Unable to send dominant bit. */
538 kFLEXCAN_Bit1Error = CAN_ESR1_BIT1ERR_MASK, /*!< Unable to send recessive bit. */
539 };
540
541 /*!
542 * @brief FlexCAN Legacy Rx FIFO status flags.
543 *
544 * The FlexCAN Legacy Rx FIFO Status enumerations are used to determine the status of the
545 * Rx FIFO. Because Rx FIFO occupy the MB0 ~ MB7 (Rx Fifo filter also occupies
546 * more Message Buffer space), Rx FIFO status flags are mapped to the corresponding
547 * Message Buffer status flags.
548 */
549 enum
550 {
551 kFLEXCAN_RxFifoOverflowFlag = CAN_IFLAG1_BUF7I_MASK, /*!< Rx FIFO overflow flag. */
552 kFLEXCAN_RxFifoWarningFlag = CAN_IFLAG1_BUF6I_MASK, /*!< Rx FIFO almost full flag. */
553 kFLEXCAN_RxFifoFrameAvlFlag = CAN_IFLAG1_BUF5I_MASK, /*!< Frames available in Rx FIFO flag. */
554 };
555
556 #if (defined(FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) && FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL)
557 /*!
558 * @brief FlexCAN Memory Error Type.
559 */
560 typedef enum _flexcan_memory_error_type
561 {
562 kFLEXCAN_CorrectableError = 0U, /*!< The memory error is correctable which means on bit error. */
563 kFLEXCAN_NonCorrectableError /*!< The memory error is non-correctable which means two bit errors. */
564 } flexcan_memory_error_type_t;
565
566 /*!
567 * @brief FlexCAN Memory Access Type.
568 */
569 typedef enum _flexcan_memory_access_type
570 {
571 kFLEXCAN_MoveOutFlexCanAccess = 0U, /*!< The memory error was detected during move-out FlexCAN access. */
572 kFLEXCAN_MoveInAccess, /*!< The memory error was detected during move-in FlexCAN access. */
573 kFLEXCAN_TxArbitrationAccess, /*!< The memory error was detected during Tx Arbitration FlexCAN access. */
574 kFLEXCAN_RxMatchingAccess, /*!< The memory error was detected during Rx Matching FlexCAN access. */
575 kFLEXCAN_MoveOutHostAccess /*!< The memory error was detected during Rx Matching Host (CPU) access. */
576 } flexcan_memory_access_type_t;
577
578 /*!
579 * @brief FlexCAN Memory Error Byte Syndrome.
580 */
581 typedef enum _flexcan_byte_error_syndrome
582 {
583 kFLEXCAN_NoError = 0U, /*!< No bit error in this byte. */
584 kFLEXCAN_ParityBits0Error = 1U, /*!< Parity bit 0 error in this byte. */
585 kFLEXCAN_ParityBits1Error = 2U, /*!< Parity bit 1 error in this byte. */
586 kFLEXCAN_ParityBits2Error = 4U, /*!< Parity bit 2 error in this byte. */
587 kFLEXCAN_ParityBits3Error = 8U, /*!< Parity bit 3 error in this byte. */
588 kFLEXCAN_ParityBits4Error = 16U, /*!< Parity bit 4 error in this byte. */
589 kFLEXCAN_DataBits0Error = 28U, /*!< Data bit 0 error in this byte. */
590 kFLEXCAN_DataBits1Error = 22U, /*!< Data bit 1 error in this byte. */
591 kFLEXCAN_DataBits2Error = 19U, /*!< Data bit 2 error in this byte. */
592 kFLEXCAN_DataBits3Error = 25U, /*!< Data bit 3 error in this byte. */
593 kFLEXCAN_DataBits4Error = 26U, /*!< Data bit 4 error in this byte. */
594 kFLEXCAN_DataBits5Error = 7U, /*!< Data bit 5 error in this byte. */
595 kFLEXCAN_DataBits6Error = 21U, /*!< Data bit 6 error in this byte. */
596 kFLEXCAN_DataBits7Error = 14U, /*!< Data bit 7 error in this byte. */
597 kFLEXCAN_AllZeroError = 6U, /*!< All-zeros non-correctable error in this byte. */
598 kFLEXCAN_AllOneError = 31U, /*!< All-ones non-correctable error in this byte. */
599 kFLEXCAN_NonCorrectableErrors /*!< Non-correctable error in this byte. */
600 } flexcan_byte_error_syndrome_t;
601
602 /*!
603 * @brief FlexCAN memory error register status structure
604 *
605 * This structure contains the memory access properties that caused a memory error access.
606 * It is used as the parameter of FLEXCAN_GetMemoryErrorReportStatus() function. And user can
607 * use FLEXCAN_GetMemoryErrorReportStatus to get the status of the last memory error access.
608 */
609 typedef struct _flexcan_memory_error_report_status
610 {
611 flexcan_memory_error_type_t errorType; /*!< The type of memory error that giving rise to the report. */
612 flexcan_memory_access_type_t accessType; /*!< The type of memory access that giving rise to the memory error. */
613 uint16_t accessAddress; /*!< The address where memory error detected. */
614 uint32_t errorData; /*!< The raw data word read from memory with error. */
615 struct
616 {
617 bool byteIsRead; /*!< The byte n (0~3) was read or not. */
618 /*!< The type of error and which bit in byte (n) is affected by the error. */
619 flexcan_byte_error_syndrome_t bitAffected;
620 } byteStatus[4];
621 } flexcan_memory_error_report_status_t;
622 #endif
623
624 #if defined(__CC_ARM)
625 #pragma anon_unions
626 #endif
627 /*! @brief FlexCAN message frame structure. */
628 typedef struct _flexcan_frame
629 {
630 struct
631 {
632 uint32_t timestamp : 16; /*!< FlexCAN internal Free-Running Counter Time Stamp. */
633 uint32_t length : 4; /*!< CAN frame data length in bytes (Range: 0~8). */
634 uint32_t type : 1; /*!< CAN Frame Type(DATA or REMOTE). */
635 uint32_t format : 1; /*!< CAN Frame Identifier(STD or EXT format). */
636 uint32_t : 1; /*!< Reserved. */
637 uint32_t idhit : 9; /*!< CAN Rx FIFO filter hit id(This value is only used in Rx FIFO receive mode). */
638 };
639 struct
640 {
641 uint32_t id : 29; /*!< CAN Frame Identifier, should be set using FLEXCAN_ID_EXT() or FLEXCAN_ID_STD() macro. */
642 uint32_t : 3; /*!< Reserved. */
643 };
644 union
645 {
646 struct
647 {
648 uint32_t dataWord0; /*!< CAN Frame payload word0. */
649 uint32_t dataWord1; /*!< CAN Frame payload word1. */
650 };
651 struct
652 {
653 uint8_t dataByte3; /*!< CAN Frame payload byte3. */
654 uint8_t dataByte2; /*!< CAN Frame payload byte2. */
655 uint8_t dataByte1; /*!< CAN Frame payload byte1. */
656 uint8_t dataByte0; /*!< CAN Frame payload byte0. */
657 uint8_t dataByte7; /*!< CAN Frame payload byte7. */
658 uint8_t dataByte6; /*!< CAN Frame payload byte6. */
659 uint8_t dataByte5; /*!< CAN Frame payload byte5. */
660 uint8_t dataByte4; /*!< CAN Frame payload byte4. */
661 };
662 };
663 } flexcan_frame_t;
664
665 #if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE)
666 /*! @brief CAN FD message frame structure.
667 *
668 * The CAN FD message supporting up to sixty four bytes can be used for a data frame, depending on the length
669 * selected for the message buffers. The length should be a enumeration member, see @ref _flexcan_fd_frame_length.
670 */
671 typedef struct _flexcan_fd_frame
672 {
673 struct
674 {
675 uint32_t timestamp : 16; /*!< FlexCAN internal Free-Running Counter Time Stamp. */
676 uint32_t length : 4; /*!< CAN FD frame data length code (DLC), range see @ref _flexcan_fd_frame_length, When the
677 length <= 8, it equal to the data length, otherwise the number of valid frame data is
678 not equal to the length value. user can
679 use DLC_LENGTH_DECODE(length) macro to get the number of valid data bytes. */
680 uint32_t type : 1; /*!< CAN Frame Type(DATA or REMOTE). */
681 uint32_t format : 1; /*!< CAN Frame Identifier(STD or EXT format). */
682 uint32_t srr : 1; /*!< Substitute Remote request. */
683 uint32_t : 6;
684 uint32_t esi : 1; /*!< Error State Indicator. */
685 uint32_t brs : 1; /*!< Bit Rate Switch. */
686 uint32_t edl : 1; /*!< Extended Data Length. */
687 };
688 struct
689 {
690 uint32_t id : 29; /*!< CAN Frame Identifier, should be set using FLEXCAN_ID_EXT() or FLEXCAN_ID_STD() macro. */
691 uint32_t : 3; /*!< Reserved. */
692 };
693 union
694 {
695 struct
696 {
697 uint32_t dataWord[16]; /*!< CAN FD Frame payload, 16 double word maximum. */
698 };
699 /* Note: the maximum databyte* below is actually 64, user can add them if needed,
700 or just use dataWord[*] instead. */
701 struct
702 {
703 uint8_t dataByte3; /*!< CAN Frame payload byte3. */
704 uint8_t dataByte2; /*!< CAN Frame payload byte2. */
705 uint8_t dataByte1; /*!< CAN Frame payload byte1. */
706 uint8_t dataByte0; /*!< CAN Frame payload byte0. */
707 uint8_t dataByte7; /*!< CAN Frame payload byte7. */
708 uint8_t dataByte6; /*!< CAN Frame payload byte6. */
709 uint8_t dataByte5; /*!< CAN Frame payload byte5. */
710 uint8_t dataByte4; /*!< CAN Frame payload byte4. */
711 };
712 };
713 #if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO)
714 /*! @note ID HIT offset is changed dynamically according to data length code (DLC), when DLC is 15, they will be
715 * located below. Using FLEXCAN_FixEnhancedRxFifoFrameIdHit API is recommended to ensure this idhit value is
716 * correct.*/
717 uint32_t idhit; /*!< CAN Enhanced Rx FIFO filter hit id (This value is only used in Enhanced Rx FIFO receive
718 mode). */
719 #endif
720 } flexcan_fd_frame_t;
721 #endif
722
723 /*! @brief FlexCAN protocol timing characteristic configuration structure. */
724 typedef struct _flexcan_timing_config
725 {
726 uint16_t preDivider; /*!< Classic CAN or CAN FD nominal phase bit rate prescaler. */
727 uint8_t rJumpwidth; /*!< Classic CAN or CAN FD nominal phase Re-sync Jump Width. */
728 uint8_t phaseSeg1; /*!< Classic CAN or CAN FD nominal phase Segment 1. */
729 uint8_t phaseSeg2; /*!< Classic CAN or CAN FD nominal phase Segment 2. */
730 uint8_t propSeg; /*!< Classic CAN or CAN FD nominal phase Propagation Segment. */
731 #if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE)
732 uint16_t fpreDivider; /*!< CAN FD data phase bit rate prescaler. */
733 uint8_t frJumpwidth; /*!< CAN FD data phase Re-sync Jump Width. */
734 uint8_t fphaseSeg1; /*!< CAN FD data phase Phase Segment 1. */
735 uint8_t fphaseSeg2; /*!< CAN FD data phase Phase Segment 2. */
736 uint8_t fpropSeg; /*!< CAN FD data phase Propagation Segment. */
737 #endif
738 } flexcan_timing_config_t;
739
740 /*! @brief FlexCAN module configuration structure.
741 * @deprecated Do not use the baudRate. It has been superceded bitRate
742 * @deprecated Do not use the baudRateFD. It has been superceded bitRateFD
743 */
744 typedef struct _flexcan_config
745 {
746 union
747 {
748 struct
749 {
750 uint32_t baudRate; /*!< FlexCAN bit rate in bps, for classical CAN or CANFD nominal phase. */
751 #if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE)
752 uint32_t baudRateFD; /*!< FlexCAN FD bit rate in bps, for CANFD data phase. */
753 #endif
754 };
755 struct
756 {
757 uint32_t bitRate; /*!< FlexCAN bit rate in bps, for classical CAN or CANFD nominal phase. */
758 #if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE)
759 uint32_t bitRateFD; /*!< FlexCAN FD bit rate in bps, for CANFD data phase. */
760 #endif
761 };
762 };
763 flexcan_clock_source_t clkSrc; /*!< Clock source for FlexCAN Protocol Engine. */
764 #if !(defined(FSL_FEATURE_FLEXCAN_HAS_NO_WAKSRC_SUPPORT) && FSL_FEATURE_FLEXCAN_HAS_NO_WAKSRC_SUPPORT)
765 flexcan_wake_up_source_t wakeupSrc; /*!< Wake up source selection. */
766 #endif
767 uint8_t maxMbNum; /*!< The maximum number of Message Buffers used by user. */
768 bool enableLoopBack; /*!< Enable or Disable Loop Back Self Test Mode. */
769 bool enableTimerSync; /*!< Enable or Disable Timer Synchronization. */
770 #if !(defined(FSL_FEATURE_FLEXCAN_HAS_NO_SLFWAK_SUPPORT) && FSL_FEATURE_FLEXCAN_HAS_NO_SLFWAK_SUPPORT)
771 bool enableSelfWakeup; /*!< Enable or Disable Self Wakeup Mode. */
772 #endif
773 bool enableIndividMask; /*!< Enable or Disable Rx Individual Mask and Queue feature. */
774 bool disableSelfReception; /*!< Enable or Disable Self Reflection. */
775 bool enableListenOnlyMode; /*!< Enable or Disable Listen Only Mode. */
776 #if !(defined(FSL_FEATURE_FLEXCAN_HAS_NO_SUPV_SUPPORT) && FSL_FEATURE_FLEXCAN_HAS_NO_SUPV_SUPPORT)
777 bool enableSupervisorMode; /*!< Enable or Disable Supervisor Mode, enable this mode will make registers allow only
778 Supervisor access. */
779 #endif
780 #if (defined(FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT) && FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT)
781 bool enableDoze; /*!< Enable or Disable Doze Mode. */
782 #endif
783 #if (defined(FSL_FEATURE_FLEXCAN_HAS_PN_MODE) && FSL_FEATURE_FLEXCAN_HAS_PN_MODE)
784 bool enablePretendedeNetworking; /*!< Enable or Disable the Pretended Networking mode. */
785 #endif
786 #if (defined(FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) && FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL)
787 bool enableMemoryErrorControl; /*!< Enable or Disable the memory errors detection and correction mechanism. */
788 bool enableNonCorrectableErrorEnterFreeze; /*!< Enable or Disable Non-Correctable Errors In FlexCAN Access Put
789 Device In Freeze Mode. */
790 #endif
791 #if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_BIT_TIMING_REG) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_BIT_TIMING_REG)
792 bool enableTransceiverDelayMeasure; /*!< Enable or Disable the transceiver delay measurement, when it is enabled,
793 then the secondary sample point position is determined by the sum of the
794 transceiver delay measurement plus the enhanced TDC offset. */
795 #endif
796 flexcan_timing_config_t timingConfig; /* Protocol timing . */
797 } flexcan_config_t;
798
799 /*!
800 * @brief FlexCAN Receive Message Buffer configuration structure
801 *
802 * This structure is used as the parameter of FLEXCAN_SetRxMbConfig() function.
803 * The FLEXCAN_SetRxMbConfig() function is used to configure FlexCAN Receive
804 * Message Buffer. The function abort previous receiving process, clean the
805 * Message Buffer and activate the Rx Message Buffer using given Message Buffer
806 * setting.
807 */
808 typedef struct _flexcan_rx_mb_config
809 {
810 uint32_t id; /*!< CAN Message Buffer Frame Identifier, should be set using
811 FLEXCAN_ID_EXT() or FLEXCAN_ID_STD() macro. */
812 flexcan_frame_format_t format; /*!< CAN Frame Identifier format(Standard of Extend). */
813 flexcan_frame_type_t type; /*!< CAN Frame Type(Data or Remote). */
814 } flexcan_rx_mb_config_t;
815
816 #if (defined(FSL_FEATURE_FLEXCAN_HAS_PN_MODE) && FSL_FEATURE_FLEXCAN_HAS_PN_MODE)
817 /*! @brief FlexCAN Pretended Networking match source selection. */
818 typedef enum _flexcan_pn_match_source
819 {
820 kFLEXCAN_PNMatSrcID = 0U, /*!< Message match with ID filtering. */
821 kFLEXCAN_PNMatSrcIDAndData, /*!< Message match with ID filtering and payload filtering. */
822 } flexcan_pn_match_source_t;
823
824 /*! @brief FlexCAN Pretended Networking mode match type. */
825 typedef enum _flexcan_pn_match_mode
826 {
827 kFLEXCAN_PNMatModeEqual = 0x0U, /*!< Match upon ID/Payload contents against an exact target value. */
828 kFLEXCAN_PNMatModeGreater, /*!< Match upon an ID/Payload value greater than or equal to a specified target value.
829 */
830 kFLEXCAN_PNMatModeSmaller, /*!< Match upon an ID/Payload value smaller than or equal to a specified target value.
831 */
832 kFLEXCAN_PNMatModeRange, /*!< Match upon an ID/Payload value inside a range, greater than or equal to a specified
833 lower limit, and smaller than or equal to a specified upper limit */
834 } flexcan_pn_match_mode_t;
835
836 /*!
837 * @brief FlexCAN Pretended Networking configuration structure
838 *
839 * This structure is used as the parameter of FLEXCAN_SetPNConfig() function.
840 * The FLEXCAN_SetPNConfig() function is used to configure FlexCAN Networking work mode.
841 */
842 typedef struct _flexcan_pn_config
843 {
844 bool enableTimeout; /*!< Enable or Disable timeout event trigger wakeup.*/
845 uint16_t timeoutValue; /*!< The timeout value that generates a wakeup event, the counter timer is incremented based
846 on 64 times the CAN Bit Time unit. */
847 bool enableMatch; /*!< Enable or Disable match event trigger wakeup.*/
848 flexcan_pn_match_source_t matchSrc; /*!< Selects the match source (ID and/or data match) to trigger wakeup. */
849 uint8_t matchNum; /*!< The number of times a given message must match the predefined ID and/or data before
850 generating a wakeup event, range in 0x1 ~ 0xFF. */
851 flexcan_pn_match_mode_t idMatchMode; /*!< The ID match type. */
852 flexcan_pn_match_mode_t dataMatchMode; /*!< The data match type. */
853 uint32_t idLower; /*!< The ID target values 1 which used either for ID match "equal to", "smaller than",
854 "greater than" comparisons, or as the lower limit value in ID match "range detection". */
855 uint32_t idUpper; /*!< The ID target values 2 which used only as the upper limit value in ID match "range
856 detection" or used to store the ID mask in "equal to". */
857 uint8_t lengthLower; /*!< The lower limit for length of data bytes which used only in data match "range
858 detection". Range in 0x0 ~ 0x8.*/
859 uint8_t lengthUpper; /*!< The upper limit for length of data bytes which used only in data match "range
860 detection". Range in 0x0 ~ 0x8.*/
861 union
862 {
863 /*!< The data target values 1 which used either for data match "equal to", "smaller than",
864 "greater than" comparisons, or as the lower limit value in data match "range
865 detection". */
866 struct
867 {
868 uint32_t lowerWord0; /*!< CAN Frame payload word0. */
869 uint32_t lowerWord1; /*!< CAN Frame payload word1. */
870 };
871 struct
872 {
873 uint8_t lowerByte3; /*!< CAN Frame payload byte3. */
874 uint8_t lowerByte2; /*!< CAN Frame payload byte2. */
875 uint8_t lowerByte1; /*!< CAN Frame payload byte1. */
876 uint8_t lowerByte0; /*!< CAN Frame payload byte0. */
877 uint8_t lowerByte7; /*!< CAN Frame payload byte7. */
878 uint8_t lowerByte6; /*!< CAN Frame payload byte6. */
879 uint8_t lowerByte5; /*!< CAN Frame payload byte5. */
880 uint8_t lowerByte4; /*!< CAN Frame payload byte4. */
881 };
882 };
883 union
884 {
885 /*!< The data target values 2 which used only as the upper limit value in data match "range
886 detection" or used to store the data mask in "equal to". */
887 struct
888 {
889 uint32_t upperWord0; /*!< CAN Frame payload word0. */
890 uint32_t upperWord1; /*!< CAN Frame payload word1. */
891 };
892 struct
893 {
894 uint8_t upperByte3; /*!< CAN Frame payload byte3. */
895 uint8_t upperByte2; /*!< CAN Frame payload byte2. */
896 uint8_t upperByte1; /*!< CAN Frame payload byte1. */
897 uint8_t upperByte0; /*!< CAN Frame payload byte0. */
898 uint8_t upperByte7; /*!< CAN Frame payload byte7. */
899 uint8_t upperByte6; /*!< CAN Frame payload byte6. */
900 uint8_t upperByte5; /*!< CAN Frame payload byte5. */
901 uint8_t upperByte4; /*!< CAN Frame payload byte4. */
902 };
903 };
904 } flexcan_pn_config_t;
905 #endif
906
907 /*! @brief FlexCAN Legacy Rx FIFO configuration structure. */
908 typedef struct _flexcan_rx_fifo_config
909 {
910 uint32_t *idFilterTable; /*!< Pointer to the FlexCAN Legacy Rx FIFO identifier filter table. */
911 uint8_t idFilterNum; /*!< The FlexCAN Legacy Rx FIFO Filter elements quantity. */
912 flexcan_rx_fifo_filter_type_t idFilterType; /*!< The FlexCAN Legacy Rx FIFO Filter type. */
913 flexcan_rx_fifo_priority_t priority; /*!< The FlexCAN Legacy Rx FIFO receive priority. */
914 } flexcan_rx_fifo_config_t;
915
916 #if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO)
917 /*! @brief FlexCAN Enhanced Rx FIFO Standard ID filter element structure. */
918 typedef struct _flexcan_enhanced_rx_fifo_std_id_filter
919 {
920 uint32_t filterType : 2; /*!< FlexCAN internal Free-Running Counter Time Stamp. */
921 uint32_t : 2;
922 uint32_t rtr1 : 1; /*!< CAN FD frame data length code (DLC), range see @ref _flexcan_fd_frame_length, When the
923 length <= 8, it equal to the data length, otherwise the number of valid frame data is
924 not equal to the length value. user can
925 use DLC_LENGTH_DECODE(length) macro to get the number of valid data bytes. */
926 uint32_t std1 : 11; /*!< CAN Frame Type(DATA or REMOTE). */
927 uint32_t : 4;
928 uint32_t rtr2 : 1; /*!< CAN Frame Identifier(STD or EXT format). */
929 uint32_t std2 : 11; /*!< Substitute Remote request. */
930 } flexcan_enhanced_rx_fifo_std_id_filter_t;
931
932 /*! @brief FlexCAN Enhanced Rx FIFO Extended ID filter element structure. */
933 typedef struct _flexcan_enhanced_rx_fifo_ext_id_filter
934 {
935 uint32_t filterType : 2; /*!< FlexCAN internal Free-Running Counter Time Stamp. */
936 uint32_t rtr1 : 1; /*!< CAN FD frame data length code (DLC), range see @ref _flexcan_fd_frame_length, When the
937 length <= 8, it equal to the data length, otherwise the number of valid frame data is
938 not equal to the length value. user can
939 use DLC_LENGTH_DECODE(length) macro to get the number of valid data bytes. */
940 uint32_t std1 : 29; /*!< CAN Frame Type(DATA or REMOTE). */
941 uint32_t : 2;
942 uint32_t rtr2 : 1; /*!< CAN Frame Identifier(STD or EXT format). */
943 uint32_t std2 : 29; /*!< Substitute Remote request. */
944 } flexcan_enhanced_rx_fifo_ext_id_filter_t;
945 /*! @brief FlexCAN Enhanced Rx FIFO configuration structure. */
946 typedef struct _flexcan_enhanced_rx_fifo_config
947 {
948 uint32_t *idFilterTable; /*!< Pointer to the FlexCAN Enhanced Rx FIFO identifier filter table, each table member
949 occupies 32 bit word, table size should be equal to idFilterNum. There are two types of
950 Enhanced Rx FIFO filter elements that can be stored in table : extended-ID filter element
951 (1 word, occupie 1 table members) and standard-ID filter element (2 words, occupies 2 table
952 members), the extended-ID filter element needs to be placed in front of the table. */
953 uint8_t idFilterPairNum; /*!< idFilterPairNum is the Enhanced Rx FIFO identifier filter element pair numbers,
954 each pair of filter elements occupies 2 words and can consist of one extended ID filter
955 element or two standard ID filter elements. */
956 uint8_t extendIdFilterNum; /*!< The number of extended ID filter element items in the FlexCAN enhanced Rx FIFO
957 identifier filter table, each extended-ID filter element occupies 2 words,
958 extendIdFilterNum need less than or equal to idFilterPairNum. */
959 uint8_t fifoWatermark; /*!< (fifoWatermark + 1) is the minimum number of CAN messages stored in the Enhanced RX FIFO
960 which can trigger FIFO watermark interrupt or a DMA request. */
961 flexcan_efifo_dma_per_read_length_t dmaPerReadLength; /*!< Define the length of each read of the Enhanced RX FIFO
962 element by the DAM, see @ref _flexcan_fd_frame_length. */
963 flexcan_rx_fifo_priority_t priority; /*!< The FlexCAN Enhanced Rx FIFO receive priority. */
964 } flexcan_enhanced_rx_fifo_config_t;
965 #endif
966
967 /*! @brief FlexCAN Message Buffer transfer. */
968 typedef struct _flexcan_mb_transfer
969 {
970 #if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE)
971 flexcan_fd_frame_t *framefd;
972 #endif
973 flexcan_frame_t *frame; /*!< The buffer of CAN Message to be transfer. */
974 uint8_t mbIdx; /*!< The index of Message buffer used to transfer Message. */
975 } flexcan_mb_transfer_t;
976
977 /*! @brief FlexCAN Rx FIFO transfer. */
978 typedef struct _flexcan_fifo_transfer
979 {
980 #if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO)
981 flexcan_fd_frame_t *framefd; /*!< The buffer of CAN Message to be received from Enhanced Rx FIFO. */
982 #endif
983 flexcan_frame_t *frame; /*!< The buffer of CAN Message to be received from Legacy Rx FIFO. */
984 size_t frameNum; /*!< Number of CAN Message need to be received from Legacy or Ehanced Rx FIFO. */
985 } flexcan_fifo_transfer_t;
986
987 /*! @brief FlexCAN handle structure definition. */
988 typedef struct _flexcan_handle flexcan_handle_t;
989
990 /*! @brief FlexCAN transfer callback function.
991 *
992 * The FlexCAN transfer callback returns a value from the underlying layer.
993 * If the status equals to kStatus_FLEXCAN_ErrorStatus, the result parameter is the Content of
994 * FlexCAN status register which can be used to get the working status(or error status) of FlexCAN module.
995 * If the status equals to other FlexCAN Message Buffer transfer status, the result is the index of
996 * Message Buffer that generate transfer event.
997 * If the status equals to other FlexCAN Message Buffer transfer status, the result is meaningless and should be
998 * Ignored.
999 */
1000 #if (defined(FSL_FEATURE_FLEXCAN_HAS_PN_MODE) && FSL_FEATURE_FLEXCAN_HAS_PN_MODE) || \
1001 (defined(FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) && FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL)
1002 #define FLEXCAN_CALLBACK(x) \
1003 void(x)(CAN_Type * base, flexcan_handle_t * handle, status_t status, uint64_t result, void *userData)
1004 typedef void (*flexcan_transfer_callback_t)(
1005 CAN_Type *base, flexcan_handle_t *handle, status_t status, uint64_t result, void *userData);
1006 #else
1007 #define FLEXCAN_CALLBACK(x) \
1008 void(x)(CAN_Type * base, flexcan_handle_t * handle, status_t status, uint32_t result, void *userData)
1009 typedef void (*flexcan_transfer_callback_t)(
1010 CAN_Type *base, flexcan_handle_t *handle, status_t status, uint32_t result, void *userData);
1011 #endif
1012
1013 /*! @brief FlexCAN handle structure. */
1014 struct _flexcan_handle
1015 {
1016 flexcan_transfer_callback_t callback; /*!< Callback function. */
1017 void *userData; /*!< FlexCAN callback function parameter.*/
1018 flexcan_frame_t
1019 *volatile mbFrameBuf[CAN_WORD1_COUNT]; /*!< The buffer for received CAN data from Message Buffers. */
1020 #if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE)
1021 flexcan_fd_frame_t
1022 *volatile mbFDFrameBuf[CAN_WORD1_COUNT]; /*!< The buffer for received CAN FD data from Message Buffers. */
1023 #endif
1024 flexcan_frame_t *volatile rxFifoFrameBuf; /*!< The buffer for received CAN data from Legacy Rx FIFO. */
1025 #if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO)
1026 flexcan_fd_frame_t *volatile rxFifoFDFrameBuf; /*!< The buffer for received CAN FD data from Ehanced Rx FIFO. */
1027 #endif
1028 size_t rxFifoFrameNum; /*!< The number of CAN messages remaining to be received from Legacy or Ehanced Rx FIFO. */
1029 size_t rxFifoTransferTotalNum; /*!< Total CAN Message number need to be received from Legacy or Ehanced Rx FIFO. */
1030 volatile uint8_t mbState[CAN_WORD1_COUNT]; /*!< Message Buffer transfer state. */
1031 volatile uint8_t rxFifoState; /*!< Rx FIFO transfer state. */
1032 volatile uint32_t timestamp[CAN_WORD1_COUNT]; /*!< Mailbox transfer timestamp. */
1033 };
1034
1035 /******************************************************************************
1036 * API
1037 *****************************************************************************/
1038
1039 #if defined(__cplusplus)
1040 extern "C" {
1041 #endif
1042
1043 /*!
1044 * @name Initialization and deinitialization
1045 * @{
1046 */
1047
1048 #if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE)
1049 /*!
1050 * @brief Determine whether the FlexCAN instance support CAN FD mode at run time.
1051 *
1052 * @note Use this API only if different soc parts share the SOC part name macro define. Otherwise, a different SOC part
1053 * name can be used to determine at compile time whether the FlexCAN instance supports CAN FD mode or not.
1054 * If need use this API to determine if CAN FD mode is supported, the FLEXCAN_Init function needs to be
1055 * executed first, and then call this API and use the return to value determines whether to supports CAN FD mode,
1056 * if return true, continue calling FLEXCAN_FDInit to enable CAN FD mode.
1057 *
1058 * @param base FlexCAN peripheral base address.
1059 * @return return TRUE if instance support CAN FD mode, FALSE if instance only support classic CAN (2.0) mode.
1060 */
1061 bool FLEXCAN_IsInstanceHasFDMode(CAN_Type *base);
1062 #endif
1063
1064 /*!
1065 * @brief Enter FlexCAN Freeze Mode.
1066 *
1067 * This function makes the FlexCAN work under Freeze Mode.
1068 *
1069 * @param base FlexCAN peripheral base address.
1070 */
1071 void FLEXCAN_EnterFreezeMode(CAN_Type *base);
1072
1073 /*!
1074 * @brief Exit FlexCAN Freeze Mode.
1075 *
1076 * This function makes the FlexCAN leave Freeze Mode.
1077 *
1078 * @param base FlexCAN peripheral base address.
1079 */
1080 void FLEXCAN_ExitFreezeMode(CAN_Type *base);
1081
1082 /*!
1083 * @brief Get the FlexCAN instance from peripheral base address.
1084 *
1085 * @param base FlexCAN peripheral base address.
1086 * @return FlexCAN instance.
1087 */
1088 uint32_t FLEXCAN_GetInstance(CAN_Type *base);
1089
1090 /*!
1091 * @brief Calculates the improved timing values by specific bit Rates for classical CAN.
1092 *
1093 * This function use to calculates the Classical CAN timing values according to the given bit rate. The Calculated
1094 * timing values will be set in CTRL1/CBT/ENCBT register. The calculation is based on the recommendation of the CiA 301
1095 * v4.2.0 and previous version document.
1096 *
1097 * @param base FlexCAN peripheral base address.
1098 * @param bitRate The classical CAN speed in bps defined by user, should be less than or equal to 1Mbps.
1099 * @param sourceClock_Hz The Source clock frequency in Hz.
1100 * @param pTimingConfig Pointer to the FlexCAN timing configuration structure.
1101 *
1102 * @return TRUE if timing configuration found, FALSE if failed to find configuration.
1103 */
1104 bool FLEXCAN_CalculateImprovedTimingValues(CAN_Type *base,
1105 uint32_t bitRate,
1106 uint32_t sourceClock_Hz,
1107 flexcan_timing_config_t *pTimingConfig);
1108
1109 /*!
1110 * @brief Initializes a FlexCAN instance.
1111 *
1112 * This function initializes the FlexCAN module with user-defined settings.
1113 * This example shows how to set up the flexcan_config_t parameters and how
1114 * to call the FLEXCAN_Init function by passing in these parameters.
1115 * @code
1116 * flexcan_config_t flexcanConfig;
1117 * flexcanConfig.clkSrc = kFLEXCAN_ClkSrc0;
1118 * flexcanConfig.bitRate = 1000000U;
1119 * flexcanConfig.maxMbNum = 16;
1120 * flexcanConfig.enableLoopBack = false;
1121 * flexcanConfig.enableSelfWakeup = false;
1122 * flexcanConfig.enableIndividMask = false;
1123 * flexcanConfig.enableDoze = false;
1124 * flexcanConfig.disableSelfReception = false;
1125 * flexcanConfig.enableListenOnlyMode = false;
1126 * flexcanConfig.timingConfig = timingConfig;
1127 * FLEXCAN_Init(CAN0, &flexcanConfig, 40000000UL);
1128 * @endcode
1129 *
1130 * @param base FlexCAN peripheral base address.
1131 * @param pConfig Pointer to the user-defined configuration structure.
1132 * @param sourceClock_Hz FlexCAN Protocol Engine clock source frequency in Hz.
1133 */
1134 void FLEXCAN_Init(CAN_Type *base, const flexcan_config_t *pConfig, uint32_t sourceClock_Hz);
1135
1136 #if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE)
1137 /*!
1138 * @brief Calculates the improved timing values by specific bit rates for CANFD.
1139 *
1140 * This function use to calculates the CANFD timing values according to the given nominal phase bit rate and data phase
1141 * bit rate. The Calculated timing values will be set in CBT/ENCBT and FDCBT/EDCBT registers. The calculation is based
1142 * on the recommendation of the CiA 1301 v1.0.0 document.
1143 *
1144 * @param base FlexCAN peripheral base address.
1145 * @param bitRate The CANFD bus control speed in bps defined by user.
1146 * @param bitRateFD The CAN FD data phase speed in bps defined by user. Equal to bitRate means disable bit rate
1147 * switching.
1148 * @param sourceClock_Hz The Source clock frequency in Hz.
1149 * @param pTimingConfig Pointer to the FlexCAN timing configuration structure.
1150 *
1151 * @return TRUE if timing configuration found, FALSE if failed to find configuration
1152 */
1153 bool FLEXCAN_FDCalculateImprovedTimingValues(CAN_Type *base,
1154 uint32_t bitRate,
1155 uint32_t bitRateFD,
1156 uint32_t sourceClock_Hz,
1157 flexcan_timing_config_t *pTimingConfig);
1158 /*!
1159 * @brief Initializes a FlexCAN instance.
1160 *
1161 * This function initializes the FlexCAN module with user-defined settings.
1162 * This example shows how to set up the flexcan_config_t parameters and how
1163 * to call the FLEXCAN_FDInit function by passing in these parameters.
1164 * @code
1165 * flexcan_config_t flexcanConfig;
1166 * flexcanConfig.clkSrc = kFLEXCAN_ClkSrc0;
1167 * flexcanConfig.bitRate = 1000000U;
1168 * flexcanConfig.bitRateFD = 2000000U;
1169 * flexcanConfig.maxMbNum = 16;
1170 * flexcanConfig.enableLoopBack = false;
1171 * flexcanConfig.enableSelfWakeup = false;
1172 * flexcanConfig.enableIndividMask = false;
1173 * flexcanConfig.disableSelfReception = false;
1174 * flexcanConfig.enableListenOnlyMode = false;
1175 * flexcanConfig.enableDoze = false;
1176 * flexcanConfig.timingConfig = timingConfig;
1177 * FLEXCAN_FDInit(CAN0, &flexcanConfig, 80000000UL, kFLEXCAN_16BperMB, true);
1178 * @endcode
1179 *
1180 * @param base FlexCAN peripheral base address.
1181 * @param pConfig Pointer to the user-defined configuration structure.
1182 * @param sourceClock_Hz FlexCAN Protocol Engine clock source frequency in Hz.
1183 * @param dataSize FlexCAN Message Buffer payload size. The actual transmitted or received CAN FD frame data size needs
1184 * to be less than or equal to this value.
1185 * @param brs True if bit rate switch is enabled in FD mode.
1186 */
1187 void FLEXCAN_FDInit(
1188 CAN_Type *base, const flexcan_config_t *pConfig, uint32_t sourceClock_Hz, flexcan_mb_size_t dataSize, bool brs);
1189 #endif
1190
1191 /*!
1192 * @brief De-initializes a FlexCAN instance.
1193 *
1194 * This function disables the FlexCAN module clock and sets all register values
1195 * to the reset value.
1196 *
1197 * @param base FlexCAN peripheral base address.
1198 */
1199 void FLEXCAN_Deinit(CAN_Type *base);
1200
1201 /*!
1202 * @brief Gets the default configuration structure.
1203 *
1204 * This function initializes the FlexCAN configuration structure to default values. The default
1205 * values are as follows.
1206 * flexcanConfig->clkSrc = kFLEXCAN_ClkSrc0;
1207 * flexcanConfig->bitRate = 1000000U;
1208 * flexcanConfig->bitRateFD = 2000000U;
1209 * flexcanConfig->maxMbNum = 16;
1210 * flexcanConfig->enableLoopBack = false;
1211 * flexcanConfig->enableSelfWakeup = false;
1212 * flexcanConfig->enableIndividMask = false;
1213 * flexcanConfig->disableSelfReception = false;
1214 * flexcanConfig->enableListenOnlyMode = false;
1215 * flexcanConfig->enableDoze = false;
1216 * flexcanConfig->enableMemoryErrorControl = true;
1217 * flexcanConfig->enableNonCorrectableErrorEnterFreeze = true;
1218 * flexcanConfig.timingConfig = timingConfig;
1219 *
1220 * @param pConfig Pointer to the FlexCAN configuration structure.
1221 */
1222 void FLEXCAN_GetDefaultConfig(flexcan_config_t *pConfig);
1223
1224 /*! @} */
1225
1226 /*!
1227 * @name Configuration.
1228 * @{
1229 */
1230
1231 /*!
1232 * @brief Sets the FlexCAN classical CAN protocol timing characteristic.
1233 *
1234 * This function gives user settings to classical CAN or CAN FD nominal phase timing characteristic.
1235 * The function is for an experienced user. For less experienced users, call the FLEXCAN_SetBitRate() instead.
1236 *
1237 * @note Calling FLEXCAN_SetTimingConfig() overrides the bit rate set in FLEXCAN_Init() or FLEXCAN_SetBitRate().
1238 *
1239 * @param base FlexCAN peripheral base address.
1240 * @param pConfig Pointer to the timing configuration structure.
1241 */
1242 void FLEXCAN_SetTimingConfig(CAN_Type *base, const flexcan_timing_config_t *pConfig);
1243
1244 /*!
1245 * @brief Set bit rate of FlexCAN classical CAN frame or CAN FD frame nominal phase.
1246 *
1247 * This function set the bit rate of classical CAN frame or CAN FD frame nominal phase base on
1248 * FLEXCAN_CalculateImprovedTimingValues() API calculated timing values.
1249 *
1250 * @note Calling FLEXCAN_SetBitRate() overrides the bit rate set in FLEXCAN_Init().
1251 *
1252 * @param base FlexCAN peripheral base address.
1253 * @param sourceClock_Hz Source Clock in Hz.
1254 * @param bitRate_Bps Bit rate in Bps.
1255 * @return kStatus_Success - Set CAN baud rate (only Nominal phase) successfully.
1256 */
1257 status_t FLEXCAN_SetBitRate(CAN_Type *base, uint32_t sourceClock_Hz, uint32_t bitRate_Bps);
1258
1259 #if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE)
1260 /*!
1261 * @brief Sets the FlexCAN CANFD data phase timing characteristic.
1262 *
1263 * This function gives user settings to CANFD data phase timing characteristic.
1264 * The function is for an experienced user. For less experienced users, call the FLEXCAN_SetFDBitRate()
1265 * to set both Nominal/Data bit Rate instead.
1266 *
1267 * @note Calling FLEXCAN_SetFDTimingConfig() overrides the data phase bit rate set in
1268 * FLEXCAN_FDInit()/FLEXCAN_SetFDBitRate().
1269 *
1270 * @param base FlexCAN peripheral base address.
1271 * @param pConfig Pointer to the timing configuration structure.
1272 */
1273 void FLEXCAN_SetFDTimingConfig(CAN_Type *base, const flexcan_timing_config_t *pConfig);
1274
1275 /*!
1276 * @brief Set bit rate of FlexCAN FD frame.
1277 *
1278 * This function set the baud rate of FLEXCAN FD base on FLEXCAN_FDCalculateImprovedTimingValues() API calculated timing
1279 * values.
1280 *
1281 * @param base FlexCAN peripheral base address.
1282 * @param sourceClock_Hz Source Clock in Hz.
1283 * @param bitRateN_Bps Nominal bit Rate in Bps.
1284 * @param bitRateD_Bps Data bit Rate in Bps.
1285 * @return kStatus_Success - Set CAN FD bit rate (include Nominal and Data phase) successfully.
1286 */
1287 status_t FLEXCAN_SetFDBitRate(CAN_Type *base, uint32_t sourceClock_Hz, uint32_t bitRateN_Bps, uint32_t bitRateD_Bps);
1288 #endif
1289
1290 /*!
1291 * @brief Sets the FlexCAN receive message buffer global mask.
1292 *
1293 * This function sets the global mask for the FlexCAN message buffer in a matching process.
1294 * The configuration is only effective when the Rx individual mask is disabled in the FLEXCAN_Init().
1295 *
1296 * @param base FlexCAN peripheral base address.
1297 * @param mask Rx Message Buffer Global Mask value.
1298 */
1299 void FLEXCAN_SetRxMbGlobalMask(CAN_Type *base, uint32_t mask);
1300
1301 /*!
1302 * @brief Sets the FlexCAN receive FIFO global mask.
1303 *
1304 * This function sets the global mask for FlexCAN FIFO in a matching process.
1305 *
1306 * @param base FlexCAN peripheral base address.
1307 * @param mask Rx Fifo Global Mask value.
1308 */
1309 void FLEXCAN_SetRxFifoGlobalMask(CAN_Type *base, uint32_t mask);
1310
1311 /*!
1312 * @brief Sets the FlexCAN receive individual mask.
1313 *
1314 * This function sets the individual mask for the FlexCAN matching process.
1315 * The configuration is only effective when the Rx individual mask is enabled in the FLEXCAN_Init().
1316 * If the Rx FIFO is disabled, the individual mask is applied to the corresponding Message Buffer.
1317 * If the Rx FIFO is enabled, the individual mask for Rx FIFO occupied Message Buffer is applied to
1318 * the Rx Filter with the same index. Note that only the first 32
1319 * individual masks can be used as the Rx FIFO filter mask.
1320 *
1321 * @param base FlexCAN peripheral base address.
1322 * @param maskIdx The Index of individual Mask.
1323 * @param mask Rx Individual Mask value.
1324 */
1325 void FLEXCAN_SetRxIndividualMask(CAN_Type *base, uint8_t maskIdx, uint32_t mask);
1326
1327 /*!
1328 * @brief Configures a FlexCAN transmit message buffer.
1329 *
1330 * This function aborts the previous transmission, cleans the Message Buffer, and
1331 * configures it as a Transmit Message Buffer.
1332 *
1333 * @param base FlexCAN peripheral base address.
1334 * @param mbIdx The Message Buffer index.
1335 * @param enable Enable/disable Tx Message Buffer.
1336 * - true: Enable Tx Message Buffer.
1337 * - false: Disable Tx Message Buffer.
1338 */
1339 void FLEXCAN_SetTxMbConfig(CAN_Type *base, uint8_t mbIdx, bool enable);
1340
1341 #if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE)
1342 /*!
1343 * @brief Configures a FlexCAN transmit message buffer.
1344 *
1345 * This function aborts the previous transmission, cleans the Message Buffer, and
1346 * configures it as a Transmit Message Buffer.
1347 *
1348 * @param base FlexCAN peripheral base address.
1349 * @param mbIdx The Message Buffer index.
1350 * @param enable Enable/disable Tx Message Buffer.
1351 * - true: Enable Tx Message Buffer.
1352 * - false: Disable Tx Message Buffer.
1353 */
1354 void FLEXCAN_SetFDTxMbConfig(CAN_Type *base, uint8_t mbIdx, bool enable);
1355 #endif
1356
1357 /*!
1358 * @brief Configures a FlexCAN Receive Message Buffer.
1359 *
1360 * This function cleans a FlexCAN build-in Message Buffer and configures it
1361 * as a Receive Message Buffer.
1362 *
1363 * @param base FlexCAN peripheral base address.
1364 * @param mbIdx The Message Buffer index.
1365 * @param pRxMbConfig Pointer to the FlexCAN Message Buffer configuration structure.
1366 * @param enable Enable/disable Rx Message Buffer.
1367 * - true: Enable Rx Message Buffer.
1368 * - false: Disable Rx Message Buffer.
1369 */
1370 void FLEXCAN_SetRxMbConfig(CAN_Type *base, uint8_t mbIdx, const flexcan_rx_mb_config_t *pRxMbConfig, bool enable);
1371
1372 #if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE)
1373 /*!
1374 * @brief Configures a FlexCAN Receive Message Buffer.
1375 *
1376 * This function cleans a FlexCAN build-in Message Buffer and configures it
1377 * as a Receive Message Buffer.
1378 *
1379 * @param base FlexCAN peripheral base address.
1380 * @param mbIdx The Message Buffer index.
1381 * @param pRxMbConfig Pointer to the FlexCAN Message Buffer configuration structure.
1382 * @param enable Enable/disable Rx Message Buffer.
1383 * - true: Enable Rx Message Buffer.
1384 * - false: Disable Rx Message Buffer.
1385 */
1386 void FLEXCAN_SetFDRxMbConfig(CAN_Type *base, uint8_t mbIdx, const flexcan_rx_mb_config_t *pRxMbConfig, bool enable);
1387 #endif
1388
1389 /*!
1390 * @brief Configures the FlexCAN Legacy Rx FIFO.
1391 *
1392 * This function configures the FlexCAN Rx FIFO with given configuration.
1393 * @note Legacy Rx FIFO only can receive classic CAN message.
1394 *
1395 * @param base FlexCAN peripheral base address.
1396 * @param pRxFifoConfig Pointer to the FlexCAN Legacy Rx FIFO configuration structure. Can be NULL when enable parameter
1397 * is false.
1398 * @param enable Enable/disable Legacy Rx FIFO.
1399 * - true: Enable Legacy Rx FIFO.
1400 * - false: Disable Legacy Rx FIFO.
1401 */
1402 void FLEXCAN_SetRxFifoConfig(CAN_Type *base, const flexcan_rx_fifo_config_t *pRxFifoConfig, bool enable);
1403
1404 #if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO)
1405 /*!
1406 * @brief Configures the FlexCAN Enhanced Rx FIFO.
1407 *
1408 * This function configures the Enhanced Rx FIFO with given configuration.
1409 * @note Enhanced Rx FIFO support receive classic CAN or CAN FD messages, Legacy Rx FIFO and Enhanced Rx FIFO
1410 * cannot be enabled at the same time.
1411 *
1412 * @param base FlexCAN peripheral base address.
1413 * @param pConfig Pointer to the FlexCAN Enhanced Rx FIFO configuration structure. Can be NULL when enable parameter
1414 * is false.
1415 * @param enable Enable/disable Enhanced Rx FIFO.
1416 * - true: Enable Enhanced Rx FIFO.
1417 * - false: Disable Enhanced Rx FIFO.
1418 */
1419 void FLEXCAN_SetEnhancedRxFifoConfig(CAN_Type *base, const flexcan_enhanced_rx_fifo_config_t *pConfig, bool enable);
1420 #endif
1421
1422 #if (defined(FSL_FEATURE_FLEXCAN_HAS_PN_MODE) && FSL_FEATURE_FLEXCAN_HAS_PN_MODE)
1423 /*!
1424 * @brief Configures the FlexCAN Pretended Networking mode.
1425 *
1426 * This function configures the FlexCAN Pretended Networking mode with given configuration.
1427 *
1428 * @param base FlexCAN peripheral base address.
1429 * @param pConfig Pointer to the FlexCAN Rx FIFO configuration structure.
1430 */
1431 void FLEXCAN_SetPNConfig(CAN_Type *base, const flexcan_pn_config_t *pConfig);
1432 #endif
1433 /*! @} */
1434
1435 /*!
1436 * @name Status
1437 * @{
1438 */
1439
1440 /*!
1441 * @brief Gets the FlexCAN module interrupt flags.
1442 *
1443 * This function gets all FlexCAN status flags. The flags are returned as the logical
1444 * OR value of the enumerators @ref _flexcan_flags. To check the specific status,
1445 * compare the return value with enumerators in @ref _flexcan_flags.
1446 *
1447 * @param base FlexCAN peripheral base address.
1448 * @return FlexCAN status flags which are ORed by the enumerators in the _flexcan_flags.
1449 */
1450 #if (defined(FSL_FEATURE_FLEXCAN_HAS_PN_MODE) && FSL_FEATURE_FLEXCAN_HAS_PN_MODE) || \
1451 (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) || \
1452 (defined(FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) && FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL)
FLEXCAN_GetStatusFlags(CAN_Type * base)1453 static inline uint64_t FLEXCAN_GetStatusFlags(CAN_Type *base)
1454 {
1455 uint64_t tempflag = (uint64_t)base->ESR1;
1456 #if (defined(FSL_FEATURE_FLEXCAN_HAS_PN_MODE) && FSL_FEATURE_FLEXCAN_HAS_PN_MODE)
1457 /* Get PN Wake Up status. */
1458 tempflag |= FLEXCAN_PN_STATUS_MASK(base->WU_MTC);
1459 #endif
1460 #if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO)
1461 /* Get Enhanced Rx FIFO status. */
1462 tempflag |= FLEXCAN_EFIFO_STATUS_MASK(base->ERFSR);
1463 #endif
1464 #if (defined(FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) && FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL)
1465 /* Get Memory Error status. */
1466 tempflag |= FLEXCAN_MECR_STATUS_MASK(base->ERRSR);
1467 #endif
1468 return tempflag;
1469 }
1470 #else
FLEXCAN_GetStatusFlags(CAN_Type * base)1471 static inline uint32_t FLEXCAN_GetStatusFlags(CAN_Type *base)
1472 {
1473 return base->ESR1;
1474 }
1475 #endif
1476 /*!
1477 * @brief Clears status flags with the provided mask.
1478 *
1479 * This function clears the FlexCAN status flags with a provided mask. An automatically cleared flag
1480 * can't be cleared by this function.
1481 *
1482 * @param base FlexCAN peripheral base address.
1483 * @param mask The status flags to be cleared, it is logical OR value of @ref _flexcan_flags.
1484 */
1485 #if (defined(FSL_FEATURE_FLEXCAN_HAS_PN_MODE) && FSL_FEATURE_FLEXCAN_HAS_PN_MODE) || \
1486 (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) || \
1487 (defined(FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) && FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL)
FLEXCAN_ClearStatusFlags(CAN_Type * base,uint64_t mask)1488 static inline void FLEXCAN_ClearStatusFlags(CAN_Type *base, uint64_t mask)
1489 {
1490 #if (defined(FSL_FEATURE_FLEXCAN_HAS_PN_MODE) && FSL_FEATURE_FLEXCAN_HAS_PN_MODE)
1491 /* Clear PN Wake Up status. */
1492 base->WU_MTC = FLEXCAN_PN_STATUS_UNMASK(mask);
1493 #endif
1494 #if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO)
1495 /* Clear Enhanced Rx FIFO status. */
1496 base->ERFSR = FLEXCAN_EFIFO_STATUS_UNMASK(mask);
1497 #endif
1498 #if (defined(FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) && FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL)
1499 /* Clear Memory Error status. */
1500 base->ERRSR = FLEXCAN_MECR_STATUS_UNMASK(mask);
1501 #endif
1502 base->ESR1 = (uint32_t)(mask & 0xFFFFFFFFU);
1503 }
1504 #else
FLEXCAN_ClearStatusFlags(CAN_Type * base,uint32_t mask)1505 static inline void FLEXCAN_ClearStatusFlags(CAN_Type *base, uint32_t mask)
1506 {
1507 /* Write 1 to clear status flag. */
1508 base->ESR1 = mask;
1509 }
1510 #endif
1511 /*!
1512 * @brief Gets the FlexCAN Bus Error Counter value.
1513 *
1514 * This function gets the FlexCAN Bus Error Counter value for both Tx and
1515 * Rx direction. These values may be needed in the upper layer error handling.
1516 *
1517 * @param base FlexCAN peripheral base address.
1518 * @param txErrBuf Buffer to store Tx Error Counter value.
1519 * @param rxErrBuf Buffer to store Rx Error Counter value.
1520 */
FLEXCAN_GetBusErrCount(CAN_Type * base,uint8_t * txErrBuf,uint8_t * rxErrBuf)1521 static inline void FLEXCAN_GetBusErrCount(CAN_Type *base, uint8_t *txErrBuf, uint8_t *rxErrBuf)
1522 {
1523 if (NULL != txErrBuf)
1524 {
1525 *txErrBuf = (uint8_t)((base->ECR & CAN_ECR_TXERRCNT_MASK) >> CAN_ECR_TXERRCNT_SHIFT);
1526 }
1527
1528 if (NULL != rxErrBuf)
1529 {
1530 *rxErrBuf = (uint8_t)((base->ECR & CAN_ECR_RXERRCNT_MASK) >> CAN_ECR_RXERRCNT_SHIFT);
1531 }
1532 }
1533
1534 /*!
1535 * @brief Gets the FlexCAN Message Buffer interrupt flags.
1536 *
1537 * This function gets the interrupt flags of a given Message Buffers.
1538 *
1539 * @param base FlexCAN peripheral base address.
1540 * @param mask The ORed FlexCAN Message Buffer mask.
1541 * @return The status of given Message Buffers.
1542 */
1543 #if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0)
FLEXCAN_GetMbStatusFlags(CAN_Type * base,uint64_t mask)1544 static inline uint64_t FLEXCAN_GetMbStatusFlags(CAN_Type *base, uint64_t mask)
1545 #else
1546 static inline uint32_t FLEXCAN_GetMbStatusFlags(CAN_Type *base, uint32_t mask)
1547 #endif
1548 {
1549 #if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0)
1550 uint64_t tempflag = (uint64_t)base->IFLAG1;
1551 return (tempflag | (((uint64_t)base->IFLAG2) << 32)) & mask;
1552 #else
1553 return (base->IFLAG1 & mask);
1554 #endif
1555 }
1556
1557 #if (defined(FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB) && FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB)
1558 /*!
1559 * @brief Gets the FlexCAN High 64 Message Buffer interrupt flags.
1560 *
1561 * Valid only if the number of available MBs exceeds 64.
1562 *
1563 * @param base FlexCAN peripheral base address.
1564 * @param mask The ORed FlexCAN Message Buffer mask.
1565 * @return The status of given Message Buffers.
1566 */
FLEXCAN_GetHigh64MbStatusFlags(CAN_Type * base,uint64_t mask)1567 static inline uint64_t FLEXCAN_GetHigh64MbStatusFlags(CAN_Type *base, uint64_t mask)
1568 {
1569 uint64_t tempflag = 0U;
1570 #if defined(CAN_IFLAG3_BUF95TO64_MASK)
1571 tempflag |= (uint64_t)base->IFLAG3;
1572 #endif
1573 #if defined(CAN_IFLAG4_BUF127TO96_MASK)
1574 tempflag |= (uint64_t)base->IFLAG4;
1575 #endif
1576 return (tempflag & mask);
1577 }
1578 #endif
1579
1580 /*!
1581 * @brief Clears the FlexCAN Message Buffer interrupt flags.
1582 *
1583 * This function clears the interrupt flags of a given Message Buffers.
1584 *
1585 * @param base FlexCAN peripheral base address.
1586 * @param mask The ORed FlexCAN Message Buffer mask.
1587 */
1588 #if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0)
FLEXCAN_ClearMbStatusFlags(CAN_Type * base,uint64_t mask)1589 static inline void FLEXCAN_ClearMbStatusFlags(CAN_Type *base, uint64_t mask)
1590 #else
1591 static inline void FLEXCAN_ClearMbStatusFlags(CAN_Type *base, uint32_t mask)
1592 #endif
1593 {
1594 #if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0)
1595 base->IFLAG1 = (uint32_t)(mask & 0xFFFFFFFFU);
1596 base->IFLAG2 = (uint32_t)(mask >> 32);
1597 #else
1598 base->IFLAG1 = mask;
1599 #endif
1600 }
1601
1602 #if (defined(FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB) && FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB)
1603 /*!
1604 * @brief Clears the FlexCAN High 64 Message Buffer interrupt flags.
1605 *
1606 * Valid only if the number of available MBs exceeds 64.
1607 *
1608 * @param base FlexCAN peripheral base address.
1609 * @param mask The ORed FlexCAN Message Buffer mask.
1610 */
FLEXCAN_ClearHigh64MbStatusFlags(CAN_Type * base,uint64_t mask)1611 static inline void FLEXCAN_ClearHigh64MbStatusFlags(CAN_Type *base, uint64_t mask)
1612 {
1613 #if defined(CAN_IFLAG3_BUF95TO64_MASK)
1614 base->IFLAG3 = (uint32_t)(mask & 0xFFFFFFFFU);
1615 #endif
1616 #if defined(CAN_IFLAG4_BUF127TO96_MASK)
1617 base->IFLAG4 = (uint32_t)(mask >> 32U);
1618 #endif
1619 }
1620 #endif
1621
1622 #if (defined(FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) && FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL)
1623 /*!
1624 * @brief Gets the FlexCAN Memory Error Report registers status.
1625 *
1626 * This function gets the FlexCAN Memory Error Report registers status.
1627 *
1628 * @param base FlexCAN peripheral base address.
1629 * @param errorStatus Pointer to FlexCAN Memory Error Report registers status structure.
1630 */
1631 void FLEXCAN_GetMemoryErrorReportStatus(CAN_Type *base, flexcan_memory_error_report_status_t *errorStatus);
1632 #endif
1633
1634 #if (defined(FSL_FEATURE_FLEXCAN_HAS_PN_MODE) && FSL_FEATURE_FLEXCAN_HAS_PN_MODE)
1635 /*!
1636 * @brief Gets the FlexCAN Number of Matches when in Pretended Networking.
1637 *
1638 * This function gets the number of times a given message has matched the predefined filtering criteria for ID and/or PL
1639 * before a wakeup event.
1640 *
1641 * @param base FlexCAN peripheral base address.
1642 * @return The number of received wake up msessages.
1643 */
FLEXCAN_GetPNMatchCount(CAN_Type * base)1644 static inline uint8_t FLEXCAN_GetPNMatchCount(CAN_Type *base)
1645 {
1646 return (uint8_t)((base->WU_MTC & CAN_WU_MTC_MCOUNTER_MASK) >> CAN_WU_MTC_MCOUNTER_SHIFT);
1647 }
1648 #endif
1649
1650 #if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO)
1651 /*!
1652 * @brief Gets the number of FlexCAN Enhanced Rx FIFO available frames.
1653 *
1654 * This function gets the number of CAN messages stored in the Enhanced Rx FIFO.
1655 *
1656 * @param base FlexCAN peripheral base address.
1657 * @return The number of available CAN messages stored in the Enhanced Rx FIFO.
1658 */
FLEXCAN_GetEnhancedFifoDataCount(CAN_Type * base)1659 static inline uint32_t FLEXCAN_GetEnhancedFifoDataCount(CAN_Type *base)
1660 {
1661 return (base->ERFSR & CAN_ERFSR_ERFEL_MASK);
1662 }
1663 #endif
1664 /*! @} */
1665
1666 /*!
1667 * @name Interrupts
1668 * @{
1669 */
1670
1671 /*!
1672 * @brief Enables FlexCAN interrupts according to the provided mask.
1673 *
1674 * This function enables the FlexCAN interrupts according to the provided mask. The mask
1675 * is a logical OR of enumeration members, see @ref _flexcan_interrupt_enable.
1676 *
1677 * @param base FlexCAN peripheral base address.
1678 * @param mask The interrupts to enable. Logical OR of @ref _flexcan_interrupt_enable.
1679 */
1680 #if (defined(FSL_FEATURE_FLEXCAN_HAS_PN_MODE) && FSL_FEATURE_FLEXCAN_HAS_PN_MODE) || \
1681 (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) || \
1682 (defined(FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) && FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL)
FLEXCAN_EnableInterrupts(CAN_Type * base,uint64_t mask)1683 static inline void FLEXCAN_EnableInterrupts(CAN_Type *base, uint64_t mask)
1684 #else
1685 static inline void FLEXCAN_EnableInterrupts(CAN_Type *base, uint32_t mask)
1686 #endif
1687 {
1688 uint32_t primask = DisableGlobalIRQ();
1689 #if !(defined(FSL_FEATURE_FLEXCAN_HAS_NO_WAKMSK_SUPPORT) && FSL_FEATURE_FLEXCAN_HAS_NO_WAKMSK_SUPPORT)
1690 /* Solve Self Wake Up interrupt. */
1691 base->MCR |= (uint32_t)(mask & (uint32_t)kFLEXCAN_WakeUpInterruptEnable);
1692 #endif
1693
1694 #if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE)
1695 if (0 != FSL_FEATURE_FLEXCAN_INSTANCE_HAS_FLEXIBLE_DATA_RATEn(base))
1696 {
1697 /* Solve CAN FD frames data phase error interrupt. */
1698 base->CTRL2 |= (uint32_t)(mask & (uint32_t)kFLEXCAN_FDErrorInterruptEnable);
1699 }
1700 #endif
1701
1702 #if (defined(FSL_FEATURE_FLEXCAN_HAS_PN_MODE) && FSL_FEATURE_FLEXCAN_HAS_PN_MODE)
1703 /* Solve PN Wake Up interrupt. */
1704 base->CTRL1_PN |= FLEXCAN_PN_INT_UNMASK(mask);
1705 #endif
1706
1707 #if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO)
1708 /* Solve Enhanced Rx FIFO interrupt. */
1709 base->ERFIER |= FLEXCAN_EFIFO_INT_UNMASK(mask);
1710 #endif
1711
1712 #if (defined(FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) && FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL)
1713 /* Solve Memory Error interrupt. */
1714 base->MECR |= FLEXCAN_MECR_INT_UNMASK(mask);
1715 #endif
1716
1717 /* Solve interrupt enable bits in CTRL1 register. */
1718 base->CTRL1 |=
1719 (uint32_t)(mask & ((uint32_t)kFLEXCAN_BusOffInterruptEnable | (uint32_t)kFLEXCAN_ErrorInterruptEnable |
1720 (uint32_t)kFLEXCAN_RxWarningInterruptEnable | (uint32_t)kFLEXCAN_TxWarningInterruptEnable));
1721
1722 EnableGlobalIRQ(primask);
1723 }
1724
1725 /*!
1726 * @brief Disables FlexCAN interrupts according to the provided mask.
1727 *
1728 * This function disables the FlexCAN interrupts according to the provided mask. The mask
1729 * is a logical OR of enumeration members, see @ref _flexcan_interrupt_enable.
1730 *
1731 * @param base FlexCAN peripheral base address.
1732 * @param mask The interrupts to disable. Logical OR of @ref _flexcan_interrupt_enable.
1733 */
1734 #if (defined(FSL_FEATURE_FLEXCAN_HAS_PN_MODE) && FSL_FEATURE_FLEXCAN_HAS_PN_MODE) || \
1735 (defined(FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) && FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL)
FLEXCAN_DisableInterrupts(CAN_Type * base,uint64_t mask)1736 static inline void FLEXCAN_DisableInterrupts(CAN_Type *base, uint64_t mask)
1737 #else
1738 static inline void FLEXCAN_DisableInterrupts(CAN_Type *base, uint32_t mask)
1739 #endif
1740 {
1741 uint32_t primask = DisableGlobalIRQ();
1742
1743 #if !(defined(FSL_FEATURE_FLEXCAN_HAS_NO_WAKMSK_SUPPORT) && FSL_FEATURE_FLEXCAN_HAS_NO_WAKMSK_SUPPORT)
1744 /* Solve Wake Up Interrupt. */
1745 base->MCR &= ~(uint32_t)(mask & (uint32_t)kFLEXCAN_WakeUpInterruptEnable);
1746 #endif
1747
1748 #if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE)
1749 if (0 != FSL_FEATURE_FLEXCAN_INSTANCE_HAS_FLEXIBLE_DATA_RATEn(base))
1750 {
1751 /* Solve CAN FD frames data phase error interrupt. */
1752 base->CTRL2 &= ~(uint32_t)(mask & (uint32_t)kFLEXCAN_FDErrorInterruptEnable);
1753 }
1754 #endif
1755
1756 #if (defined(FSL_FEATURE_FLEXCAN_HAS_PN_MODE) && FSL_FEATURE_FLEXCAN_HAS_PN_MODE)
1757 /* Solve PN Wake Up Interrupt. */
1758 base->CTRL1_PN &= ~FLEXCAN_PN_STATUS_UNMASK(mask);
1759 #endif
1760
1761 #if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO)
1762 /* Solve Enhanced Rx FIFO interrupt. */
1763 base->ERFIER &= ~FLEXCAN_EFIFO_INT_UNMASK(mask);
1764 #endif
1765
1766 #if (defined(FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL) && FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL)
1767 /* Solve Memory Error Interrupt. */
1768 base->MECR &= ~FLEXCAN_MECR_STATUS_UNMASK(mask);
1769 #endif
1770
1771 /* Solve interrupt enable bits in CTRL1 register. */
1772 base->CTRL1 &=
1773 ~(uint32_t)(mask & ((uint32_t)kFLEXCAN_BusOffInterruptEnable | (uint32_t)kFLEXCAN_ErrorInterruptEnable |
1774 (uint32_t)kFLEXCAN_RxWarningInterruptEnable | (uint32_t)kFLEXCAN_TxWarningInterruptEnable));
1775
1776 EnableGlobalIRQ(primask);
1777 }
1778
1779 /*!
1780 * @brief Enables FlexCAN Message Buffer interrupts.
1781 *
1782 * This function enables the interrupts of given Message Buffers.
1783 *
1784 * @param base FlexCAN peripheral base address.
1785 * @param mask The ORed FlexCAN Message Buffer mask.
1786 */
1787 #if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0)
FLEXCAN_EnableMbInterrupts(CAN_Type * base,uint64_t mask)1788 static inline void FLEXCAN_EnableMbInterrupts(CAN_Type *base, uint64_t mask)
1789 #else
1790 static inline void FLEXCAN_EnableMbInterrupts(CAN_Type *base, uint32_t mask)
1791 #endif
1792 {
1793 uint32_t primask = DisableGlobalIRQ();
1794
1795 #if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0)
1796 base->IMASK1 |= (uint32_t)(mask & 0xFFFFFFFFU);
1797 base->IMASK2 |= (uint32_t)(mask >> 32);
1798 #else
1799 base->IMASK1 |= mask;
1800 #endif
1801 EnableGlobalIRQ(primask);
1802 }
1803
1804 #if (defined(FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB) && FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB)
1805 /*!
1806 * @brief Enables FlexCAN high 64 Message Buffer interrupts.
1807 *
1808 * Valid only if the number of available MBs exceeds 64.
1809 *
1810 * @param base FlexCAN peripheral base address.
1811 * @param mask The ORed FlexCAN Message Buffer mask.
1812 */
FLEXCAN_EnableHigh64MbInterrupts(CAN_Type * base,uint64_t mask)1813 static inline void FLEXCAN_EnableHigh64MbInterrupts(CAN_Type *base, uint64_t mask)
1814 {
1815 uint32_t primask = DisableGlobalIRQ();
1816
1817 #if defined(CAN_IMASK3_BUF95TO64M_MASK)
1818 base->IMASK3 |= (uint32_t)(mask & 0xFFFFFFFFU);
1819 #endif
1820 #if defined(CAN_IMASK4_BUF127TO96_MASK)
1821 base->IMASK4 |= (uint32_t)(mask >> 32U);
1822 #endif
1823 EnableGlobalIRQ(primask);
1824 }
1825 #endif
1826
1827 /*!
1828 * @brief Disables FlexCAN Message Buffer interrupts.
1829 *
1830 * This function disables the interrupts of given Message Buffers.
1831 *
1832 * @param base FlexCAN peripheral base address.
1833 * @param mask The ORed FlexCAN Message Buffer mask.
1834 */
1835 #if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0)
FLEXCAN_DisableMbInterrupts(CAN_Type * base,uint64_t mask)1836 static inline void FLEXCAN_DisableMbInterrupts(CAN_Type *base, uint64_t mask)
1837 #else
1838 static inline void FLEXCAN_DisableMbInterrupts(CAN_Type *base, uint32_t mask)
1839 #endif
1840 {
1841 uint32_t primask = DisableGlobalIRQ();
1842
1843 #if (defined(FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER)) && (FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER > 0)
1844 base->IMASK1 &= ~((uint32_t)(mask & 0xFFFFFFFFU));
1845 base->IMASK2 &= ~((uint32_t)(mask >> 32));
1846 #else
1847 base->IMASK1 &= ~mask;
1848 #endif
1849 EnableGlobalIRQ(primask);
1850 }
1851
1852 #if (defined(FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB) && FSL_FEATURE_FLEXCAN_HAS_MORE_THAN_64_MB)
1853 /*!
1854 * @brief Disables FlexCAN high 64 Message Buffer interrupts.
1855 *
1856 * Valid only if the number of available MBs exceeds 64.
1857 *
1858 * @param base FlexCAN peripheral base address.
1859 * @param mask The ORed FlexCAN Message Buffer mask.
1860 */
FLEXCAN_DisableHigh64MbInterrupts(CAN_Type * base,uint64_t mask)1861 static inline void FLEXCAN_DisableHigh64MbInterrupts(CAN_Type *base, uint64_t mask)
1862 {
1863 uint32_t primask = DisableGlobalIRQ();
1864
1865 #if defined(CAN_IMASK3_BUF95TO64M_MASK)
1866 base->IMASK3 &= ~((uint32_t)(mask & 0xFFFFFFFFU));
1867 #endif
1868 #if defined(CAN_IMASK4_BUF127TO96_MASK)
1869 base->IMASK4 &= ~((uint32_t)(mask >> 32U));
1870 #endif
1871 EnableGlobalIRQ(primask);
1872 }
1873 #endif
1874
1875 /*! @} */
1876
1877 #if (defined(FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA) && FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA)
1878 /*!
1879 * @name DMA Control
1880 * @{
1881 */
1882
1883 /*!
1884 * @brief Enables or disables the FlexCAN Rx FIFO DMA request.
1885 *
1886 * This function enables or disables the DMA feature of FlexCAN build-in Rx FIFO.
1887 *
1888 * @param base FlexCAN peripheral base address.
1889 * @param enable true to enable, false to disable.
1890 */
1891 void FLEXCAN_EnableRxFifoDMA(CAN_Type *base, bool enable);
1892
1893 /*!
1894 * @brief Gets the Rx FIFO Head address.
1895 *
1896 * This function returns the FlexCAN Rx FIFO Head address, which is mainly used for the DMA/eDMA use case.
1897 *
1898 * @param base FlexCAN peripheral base address.
1899 * @return FlexCAN Rx FIFO Head address.
1900 */
FLEXCAN_GetRxFifoHeadAddr(CAN_Type * base)1901 static inline uintptr_t FLEXCAN_GetRxFifoHeadAddr(CAN_Type *base)
1902 {
1903 return (uintptr_t) & (base->MB[0].CS);
1904 }
1905
1906 /*! @} */
1907 #endif /* FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA */
1908
1909 /*!
1910 * @name Bus Operations
1911 * @{
1912 */
1913
1914 /*!
1915 * @brief Enables or disables the FlexCAN module operation.
1916 *
1917 * This function enables or disables the FlexCAN module.
1918 *
1919 * @param base FlexCAN base pointer.
1920 * @param enable true to enable, false to disable.
1921 */
FLEXCAN_Enable(CAN_Type * base,bool enable)1922 static inline void FLEXCAN_Enable(CAN_Type *base, bool enable)
1923 {
1924 if (enable)
1925 {
1926 base->MCR &= ~CAN_MCR_MDIS_MASK;
1927
1928 /* Wait FlexCAN exit from low-power mode. */
1929 while (0U != (base->MCR & CAN_MCR_LPMACK_MASK))
1930 {
1931 }
1932 }
1933 else
1934 {
1935 base->MCR |= CAN_MCR_MDIS_MASK;
1936
1937 /* Wait FlexCAN enter low-power mode. */
1938 while (0U == (base->MCR & CAN_MCR_LPMACK_MASK))
1939 {
1940 }
1941 }
1942 }
1943
1944 /*!
1945 * @brief Writes a FlexCAN Message to the Transmit Message Buffer.
1946 *
1947 * This function writes a CAN Message to the specified Transmit Message Buffer
1948 * and changes the Message Buffer state to start CAN Message transmit. After
1949 * that the function returns immediately.
1950 *
1951 * @param base FlexCAN peripheral base address.
1952 * @param mbIdx The FlexCAN Message Buffer index.
1953 * @param pTxFrame Pointer to CAN message frame to be sent.
1954 * @retval kStatus_Success - Write Tx Message Buffer Successfully.
1955 * @retval kStatus_Fail - Tx Message Buffer is currently in use.
1956 */
1957 status_t FLEXCAN_WriteTxMb(CAN_Type *base, uint8_t mbIdx, const flexcan_frame_t *pTxFrame);
1958
1959 /*!
1960 * @brief Reads a FlexCAN Message from Receive Message Buffer.
1961 *
1962 * This function reads a CAN message from a specified Receive Message Buffer.
1963 * The function fills a receive CAN message frame structure with
1964 * just received data and activates the Message Buffer again.
1965 * The function returns immediately.
1966 *
1967 * @param base FlexCAN peripheral base address.
1968 * @param mbIdx The FlexCAN Message Buffer index.
1969 * @param pRxFrame Pointer to CAN message frame structure for reception.
1970 * @retval kStatus_Success - Rx Message Buffer is full and has been read successfully.
1971 * @retval kStatus_FLEXCAN_RxOverflow - Rx Message Buffer is already overflowed and has been read successfully.
1972 * @retval kStatus_Fail - Rx Message Buffer is empty.
1973 */
1974 status_t FLEXCAN_ReadRxMb(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *pRxFrame);
1975
1976 #if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE)
1977 /*!
1978 * @brief Writes a FlexCAN FD Message to the Transmit Message Buffer.
1979 *
1980 * This function writes a CAN FD Message to the specified Transmit Message Buffer
1981 * and changes the Message Buffer state to start CAN FD Message transmit. After
1982 * that the function returns immediately.
1983 *
1984 * @param base FlexCAN peripheral base address.
1985 * @param mbIdx The FlexCAN FD Message Buffer index.
1986 * @param pTxFrame Pointer to CAN FD message frame to be sent.
1987 * @retval kStatus_Success - Write Tx Message Buffer Successfully.
1988 * @retval kStatus_Fail - Tx Message Buffer is currently in use.
1989 */
1990 status_t FLEXCAN_WriteFDTxMb(CAN_Type *base, uint8_t mbIdx, const flexcan_fd_frame_t *pTxFrame);
1991
1992 /*!
1993 * @brief Reads a FlexCAN FD Message from Receive Message Buffer.
1994 *
1995 * This function reads a CAN FD message from a specified Receive Message Buffer.
1996 * The function fills a receive CAN FD message frame structure with
1997 * just received data and activates the Message Buffer again.
1998 * The function returns immediately.
1999 *
2000 * @param base FlexCAN peripheral base address.
2001 * @param mbIdx The FlexCAN FD Message Buffer index.
2002 * @param pRxFrame Pointer to CAN FD message frame structure for reception.
2003 * @retval kStatus_Success - Rx Message Buffer is full and has been read successfully.
2004 * @retval kStatus_FLEXCAN_RxOverflow - Rx Message Buffer is already overflowed and has been read successfully.
2005 * @retval kStatus_Fail - Rx Message Buffer is empty.
2006 */
2007 status_t FLEXCAN_ReadFDRxMb(CAN_Type *base, uint8_t mbIdx, flexcan_fd_frame_t *pRxFrame);
2008 #endif
2009
2010 /*!
2011 * @brief Reads a FlexCAN Message from Legacy Rx FIFO.
2012 *
2013 * This function reads a CAN message from the FlexCAN Legacy Rx FIFO.
2014 *
2015 * @param base FlexCAN peripheral base address.
2016 * @param pRxFrame Pointer to CAN message frame structure for reception.
2017 * @retval kStatus_Success - Read Message from Rx FIFO successfully.
2018 * @retval kStatus_Fail - Rx FIFO is not enabled.
2019 */
2020 status_t FLEXCAN_ReadRxFifo(CAN_Type *base, flexcan_frame_t *pRxFrame);
2021
2022 #if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO)
2023 /*!
2024 * @brief Reads a FlexCAN Message from Enhanced Rx FIFO.
2025 *
2026 * This function reads a CAN or CAN FD message from the FlexCAN Enhanced Rx FIFO.
2027 *
2028 * @param base FlexCAN peripheral base address.
2029 * @param pRxFrame Pointer to CAN FD message frame structure for reception.
2030 * @retval kStatus_Success - Read Message from Rx FIFO successfully.
2031 * @retval kStatus_Fail - Rx FIFO is not enabled.
2032 */
2033 status_t FLEXCAN_ReadEnhancedRxFifo(CAN_Type *base, flexcan_fd_frame_t *pRxFrame);
2034 #endif
2035
2036 #if (defined(FSL_FEATURE_FLEXCAN_HAS_PN_MODE) && FSL_FEATURE_FLEXCAN_HAS_PN_MODE)
2037 /*!
2038 * @brief Reads a FlexCAN Message from Wake Up MB.
2039 *
2040 * This function reads a CAN message from the FlexCAN Wake up Message Buffers. There are four Wake up Message Buffers
2041 * (WMBs) used to store incoming messages in Pretended Networking mode. The WMB index indicates the arrival order. The
2042 * last message is stored in WMB3.
2043 *
2044 * @param base FlexCAN peripheral base address.
2045 * @param pRxFrame Pointer to CAN message frame structure for reception.
2046 * @param mbIdx The FlexCAN Wake up Message Buffer index. Range in 0x0 ~ 0x3.
2047 * @retval kStatus_Success - Read Message from Wake up Message Buffer successfully.
2048 * @retval kStatus_Fail - Wake up Message Buffer has no valid content.
2049 */
2050 status_t FLEXCAN_ReadPNWakeUpMB(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *pRxFrame);
2051 #endif
2052 /*! @} */
2053
2054 /*!
2055 * @name Transactional
2056 * @{
2057 */
2058
2059 #if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE)
2060 /*!
2061 * @brief Performs a polling send transaction on the CAN bus.
2062 *
2063 * @note A transfer handle does not need to be created before calling this API.
2064 *
2065 * @param base FlexCAN peripheral base pointer.
2066 * @param mbIdx The FlexCAN FD Message Buffer index.
2067 * @param pTxFrame Pointer to CAN FD message frame to be sent.
2068 * @retval kStatus_Success - Write Tx Message Buffer Successfully.
2069 * @retval kStatus_Fail - Tx Message Buffer is currently in use.
2070 */
2071 status_t FLEXCAN_TransferFDSendBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_fd_frame_t *pTxFrame);
2072
2073 /*!
2074 * @brief Performs a polling receive transaction on the CAN bus.
2075 *
2076 * @note A transfer handle does not need to be created before calling this API.
2077 *
2078 * @param base FlexCAN peripheral base pointer.
2079 * @param mbIdx The FlexCAN FD Message Buffer index.
2080 * @param pRxFrame Pointer to CAN FD message frame structure for reception.
2081 * @retval kStatus_Success - Rx Message Buffer is full and has been read successfully.
2082 * @retval kStatus_FLEXCAN_RxOverflow - Rx Message Buffer is already overflowed and has been read successfully.
2083 * @retval kStatus_Fail - Rx Message Buffer is empty.
2084 */
2085 status_t FLEXCAN_TransferFDReceiveBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_fd_frame_t *pRxFrame);
2086
2087 /*!
2088 * @brief Sends a message using IRQ.
2089 *
2090 * This function sends a message using IRQ. This is a non-blocking function, which returns
2091 * right away. When messages have been sent out, the send callback function is called.
2092 *
2093 * @param base FlexCAN peripheral base address.
2094 * @param handle FlexCAN handle pointer.
2095 * @param pMbXfer FlexCAN FD Message Buffer transfer structure. See the #flexcan_mb_transfer_t.
2096 * @retval kStatus_Success Start Tx Message Buffer sending process successfully.
2097 * @retval kStatus_Fail Write Tx Message Buffer failed.
2098 * @retval kStatus_FLEXCAN_TxBusy Tx Message Buffer is in use.
2099 */
2100 status_t FLEXCAN_TransferFDSendNonBlocking(CAN_Type *base, flexcan_handle_t *handle, flexcan_mb_transfer_t *pMbXfer);
2101
2102 /*!
2103 * @brief Receives a message using IRQ.
2104 *
2105 * This function receives a message using IRQ. This is non-blocking function, which returns
2106 * right away. When the message has been received, the receive callback function is called.
2107 *
2108 * @param base FlexCAN peripheral base address.
2109 * @param handle FlexCAN handle pointer.
2110 * @param pMbXfer FlexCAN FD Message Buffer transfer structure. See the #flexcan_mb_transfer_t.
2111 * @retval kStatus_Success - Start Rx Message Buffer receiving process successfully.
2112 * @retval kStatus_FLEXCAN_RxBusy - Rx Message Buffer is in use.
2113 */
2114 status_t FLEXCAN_TransferFDReceiveNonBlocking(CAN_Type *base, flexcan_handle_t *handle, flexcan_mb_transfer_t *pMbXfer);
2115
2116 /*!
2117 * @brief Aborts the interrupt driven message send process.
2118 *
2119 * This function aborts the interrupt driven message send process.
2120 *
2121 * @param base FlexCAN peripheral base address.
2122 * @param handle FlexCAN handle pointer.
2123 * @param mbIdx The FlexCAN FD Message Buffer index.
2124 */
2125 void FLEXCAN_TransferFDAbortSend(CAN_Type *base, flexcan_handle_t *handle, uint8_t mbIdx);
2126
2127 /*!
2128 * @brief Aborts the interrupt driven message receive process.
2129 *
2130 * This function aborts the interrupt driven message receive process.
2131 *
2132 * @param base FlexCAN peripheral base address.
2133 * @param handle FlexCAN handle pointer.
2134 * @param mbIdx The FlexCAN FD Message Buffer index.
2135 */
2136 void FLEXCAN_TransferFDAbortReceive(CAN_Type *base, flexcan_handle_t *handle, uint8_t mbIdx);
2137 #endif
2138
2139 /*!
2140 * @brief Performs a polling send transaction on the CAN bus.
2141 *
2142 * @note A transfer handle does not need to be created before calling this API.
2143 *
2144 * @param base FlexCAN peripheral base pointer.
2145 * @param mbIdx The FlexCAN Message Buffer index.
2146 * @param pTxFrame Pointer to CAN message frame to be sent.
2147 * @retval kStatus_Success - Write Tx Message Buffer Successfully.
2148 * @retval kStatus_Fail - Tx Message Buffer is currently in use.
2149 */
2150 status_t FLEXCAN_TransferSendBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *pTxFrame);
2151
2152 /*!
2153 * @brief Performs a polling receive transaction on the CAN bus.
2154 *
2155 * @note A transfer handle does not need to be created before calling this API.
2156 *
2157 * @param base FlexCAN peripheral base pointer.
2158 * @param mbIdx The FlexCAN Message Buffer index.
2159 * @param pRxFrame Pointer to CAN message frame structure for reception.
2160 * @retval kStatus_Success - Rx Message Buffer is full and has been read successfully.
2161 * @retval kStatus_FLEXCAN_RxOverflow - Rx Message Buffer is already overflowed and has been read successfully.
2162 * @retval kStatus_Fail - Rx Message Buffer is empty.
2163 */
2164 status_t FLEXCAN_TransferReceiveBlocking(CAN_Type *base, uint8_t mbIdx, flexcan_frame_t *pRxFrame);
2165
2166 /*!
2167 * @brief Performs a polling receive transaction from Legacy Rx FIFO on the CAN bus.
2168 *
2169 * @note A transfer handle does not need to be created before calling this API.
2170 *
2171 * @param base FlexCAN peripheral base pointer.
2172 * @param pRxFrame Pointer to CAN message frame structure for reception.
2173 * @retval kStatus_Success - Read Message from Rx FIFO successfully.
2174 * @retval kStatus_Fail - Rx FIFO is not enabled.
2175 */
2176 status_t FLEXCAN_TransferReceiveFifoBlocking(CAN_Type *base, flexcan_frame_t *pRxFrame);
2177
2178 #if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO)
2179 /*!
2180 * @brief Performs a polling receive transaction from Enhanced Rx FIFO on the CAN bus.
2181 *
2182 * @note A transfer handle does not need to be created before calling this API.
2183 *
2184 * @param base FlexCAN peripheral base pointer.
2185 * @param pRxFrame Pointer to CAN FD message frame structure for reception.
2186 * @retval kStatus_Success - Read Message from Rx FIFO successfully.
2187 * @retval kStatus_Fail - Rx FIFO is not enabled.
2188 */
2189 status_t FLEXCAN_TransferReceiveEnhancedFifoBlocking(CAN_Type *base, flexcan_fd_frame_t *pRxFrame);
2190 #endif
2191
2192 /*!
2193 * @brief Initializes the FlexCAN handle.
2194 *
2195 * This function initializes the FlexCAN handle, which can be used for other FlexCAN
2196 * transactional APIs. Usually, for a specified FlexCAN instance,
2197 * call this API once to get the initialized handle.
2198 *
2199 * @param base FlexCAN peripheral base address.
2200 * @param handle FlexCAN handle pointer.
2201 * @param callback The callback function.
2202 * @param userData The parameter of the callback function.
2203 */
2204 void FLEXCAN_TransferCreateHandle(CAN_Type *base,
2205 flexcan_handle_t *handle,
2206 flexcan_transfer_callback_t callback,
2207 void *userData);
2208
2209 /*!
2210 * @brief Sends a message using IRQ.
2211 *
2212 * This function sends a message using IRQ. This is a non-blocking function, which returns
2213 * right away. When messages have been sent out, the send callback function is called.
2214 *
2215 * @param base FlexCAN peripheral base address.
2216 * @param handle FlexCAN handle pointer.
2217 * @param pMbXfer FlexCAN Message Buffer transfer structure. See the #flexcan_mb_transfer_t.
2218 * @retval kStatus_Success Start Tx Message Buffer sending process successfully.
2219 * @retval kStatus_Fail Write Tx Message Buffer failed.
2220 * @retval kStatus_FLEXCAN_TxBusy Tx Message Buffer is in use.
2221 */
2222 status_t FLEXCAN_TransferSendNonBlocking(CAN_Type *base, flexcan_handle_t *handle, flexcan_mb_transfer_t *pMbXfer);
2223
2224 /*!
2225 * @brief Receives a message using IRQ.
2226 *
2227 * This function receives a message using IRQ. This is non-blocking function, which returns
2228 * right away. When the message has been received, the receive callback function is called.
2229 *
2230 * @param base FlexCAN peripheral base address.
2231 * @param handle FlexCAN handle pointer.
2232 * @param pMbXfer FlexCAN Message Buffer transfer structure. See the #flexcan_mb_transfer_t.
2233 * @retval kStatus_Success - Start Rx Message Buffer receiving process successfully.
2234 * @retval kStatus_FLEXCAN_RxBusy - Rx Message Buffer is in use.
2235 */
2236 status_t FLEXCAN_TransferReceiveNonBlocking(CAN_Type *base, flexcan_handle_t *handle, flexcan_mb_transfer_t *pMbXfer);
2237
2238 /*!
2239 * @brief Receives a message from Rx FIFO using IRQ.
2240 *
2241 * This function receives a message using IRQ. This is a non-blocking function, which returns
2242 * right away. When all messages have been received, the receive callback function is called.
2243 *
2244 * @param base FlexCAN peripheral base address.
2245 * @param handle FlexCAN handle pointer.
2246 * @param pFifoXfer FlexCAN Rx FIFO transfer structure. See the @ref flexcan_fifo_transfer_t.
2247 * @retval kStatus_Success - Start Rx FIFO receiving process successfully.
2248 * @retval kStatus_FLEXCAN_RxFifoBusy - Rx FIFO is currently in use.
2249 */
2250 status_t FLEXCAN_TransferReceiveFifoNonBlocking(CAN_Type *base,
2251 flexcan_handle_t *handle,
2252 flexcan_fifo_transfer_t *pFifoXfer);
2253
2254 /*!
2255 * @brief Gets the Legacy Rx Fifo transfer status during a interrupt non-blocking receive.
2256 *
2257 * @param base FlexCAN peripheral base address.
2258 * @param handle FlexCAN handle pointer.
2259 * @param count Number of CAN messages receive so far by the non-blocking transaction.
2260 * @retval kStatus_InvalidArgument count is Invalid.
2261 * @retval kStatus_Success Successfully return the count.
2262 */
2263
2264 status_t FLEXCAN_TransferGetReceiveFifoCount(CAN_Type *base, flexcan_handle_t *handle, size_t *count);
2265
2266 #if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO)
2267 /*!
2268 * @brief Receives a message from Enhanced Rx FIFO using IRQ.
2269 *
2270 * This function receives a message using IRQ. This is a non-blocking function, which returns
2271 * right away. When all messages have been received, the receive callback function is called.
2272 *
2273 * @param base FlexCAN peripheral base address.
2274 * @param handle FlexCAN handle pointer.
2275 * @param pFifoXfer FlexCAN Rx FIFO transfer structure. See the ref flexcan_fifo_transfer_t.@
2276 * @retval kStatus_Success - Start Rx FIFO receiving process successfully.
2277 * @retval kStatus_FLEXCAN_RxFifoBusy - Rx FIFO is currently in use.
2278 */
2279 status_t FLEXCAN_TransferReceiveEnhancedFifoNonBlocking(CAN_Type *base,
2280 flexcan_handle_t *handle,
2281 flexcan_fifo_transfer_t *pFifoXfer);
2282
2283 /*!
2284 * @brief Gets the Enhanced Rx Fifo transfer status during a interrupt non-blocking receive.
2285 *
2286 * @param base FlexCAN peripheral base address.
2287 * @param handle FlexCAN handle pointer.
2288 * @param count Number of CAN messages receive so far by the non-blocking transaction.
2289 * @retval kStatus_InvalidArgument count is Invalid.
2290 * @retval kStatus_Success Successfully return the count.
2291 */
2292
FLEXCAN_TransferGetReceiveEnhancedFifoCount(CAN_Type * base,flexcan_handle_t * handle,size_t * count)2293 static inline status_t FLEXCAN_TransferGetReceiveEnhancedFifoCount(CAN_Type *base,
2294 flexcan_handle_t *handle,
2295 size_t *count)
2296 {
2297 return FLEXCAN_TransferGetReceiveFifoCount(base, handle, count);
2298 }
2299 #endif
2300
2301 /*!
2302 * @brief Gets the detail index of Mailbox's Timestamp by handle.
2303 *
2304 * Then function can only be used when calling non-blocking Data transfer (TX/RX) API,
2305 * After TX/RX data transfer done (User can get the status by handler's callback function),
2306 * we can get the detail index of Mailbox's timestamp by handle,
2307 * Detail non-blocking data transfer API (TX/RX) contain.
2308 * -FLEXCAN_TransferSendNonBlocking
2309 * -FLEXCAN_TransferFDSendNonBlocking
2310 * -FLEXCAN_TransferReceiveNonBlocking
2311 * -FLEXCAN_TransferFDReceiveNonBlocking
2312 * -FLEXCAN_TransferReceiveFifoNonBlocking
2313 *
2314 * @param handle FlexCAN handle pointer.
2315 * @param mbIdx The FlexCAN Message Buffer index.
2316 * @retval the index of mailbox 's timestamp stored in the handle.
2317 *
2318 */
2319 uint32_t FLEXCAN_GetTimeStamp(flexcan_handle_t *handle, uint8_t mbIdx);
2320
2321 /*!
2322 * @brief Aborts the interrupt driven message send process.
2323 *
2324 * This function aborts the interrupt driven message send process.
2325 *
2326 * @param base FlexCAN peripheral base address.
2327 * @param handle FlexCAN handle pointer.
2328 * @param mbIdx The FlexCAN Message Buffer index.
2329 */
2330 void FLEXCAN_TransferAbortSend(CAN_Type *base, flexcan_handle_t *handle, uint8_t mbIdx);
2331
2332 /*!
2333 * @brief Aborts the interrupt driven message receive process.
2334 *
2335 * This function aborts the interrupt driven message receive process.
2336 *
2337 * @param base FlexCAN peripheral base address.
2338 * @param handle FlexCAN handle pointer.
2339 * @param mbIdx The FlexCAN Message Buffer index.
2340 */
2341 void FLEXCAN_TransferAbortReceive(CAN_Type *base, flexcan_handle_t *handle, uint8_t mbIdx);
2342
2343 /*!
2344 * @brief Aborts the interrupt driven message receive from Rx FIFO process.
2345 *
2346 * This function aborts the interrupt driven message receive from Rx FIFO process.
2347 *
2348 * @param base FlexCAN peripheral base address.
2349 * @param handle FlexCAN handle pointer.
2350 */
2351 void FLEXCAN_TransferAbortReceiveFifo(CAN_Type *base, flexcan_handle_t *handle);
2352
2353 #if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO) && FSL_FEATURE_FLEXCAN_HAS_ENHANCED_RX_FIFO)
2354 /*!
2355 * @brief Aborts the interrupt driven message receive from Enhanced Rx FIFO process.
2356 *
2357 * This function aborts the interrupt driven message receive from Enhanced Rx FIFO process.
2358 *
2359 * @param base FlexCAN peripheral base address.
2360 * @param handle FlexCAN handle pointer.
2361 */
2362 void FLEXCAN_TransferAbortReceiveEnhancedFifo(CAN_Type *base, flexcan_handle_t *handle);
2363 #endif
2364
2365 /*!
2366 * @brief FlexCAN IRQ handle function.
2367 *
2368 * This function handles the FlexCAN Error, the Message Buffer, and the Rx FIFO IRQ request.
2369 *
2370 * @param base FlexCAN peripheral base address.
2371 * @param handle FlexCAN handle pointer.
2372 */
2373 void FLEXCAN_TransferHandleIRQ(CAN_Type *base, flexcan_handle_t *handle);
2374
2375 /*! @} */
2376
2377 #if defined(__cplusplus)
2378 }
2379 #endif
2380
2381 /*! @}*/
2382
2383 #endif /* FSL_FLEXCAN_H_ */
2384
