1 /* 2 ** ################################################################### 3 ** Processors: MKE06Z128VLD4 4 ** MKE06Z128VLH4 5 ** MKE06Z128VLK4 6 ** MKE06Z128VQH4 7 ** MKE06Z64VLD4 8 ** MKE06Z64VLH4 9 ** MKE06Z64VLK4 10 ** MKE06Z64VQH4 11 ** 12 ** Compilers: Freescale C/C++ for Embedded ARM 13 ** GNU C Compiler 14 ** IAR ANSI C/C++ Compiler for ARM 15 ** Keil ARM C/C++ Compiler 16 ** MCUXpresso Compiler 17 ** 18 ** Reference manual: MKE06P80M48SF0RM Rev 4 19 ** Version: rev. 1.0, 2017-05-19 20 ** Build: b201123 21 ** 22 ** Abstract: 23 ** Provides a system configuration function and a global variable that 24 ** contains the system frequency. It configures the device and initializes 25 ** the oscillator (PLL) that is part of the microcontroller device. 26 ** 27 ** Copyright 2016 Freescale Semiconductor, Inc. 28 ** Copyright 2016-2020 NXP 29 ** All rights reserved. 30 ** 31 ** SPDX-License-Identifier: BSD-3-Clause 32 ** 33 ** http: www.nxp.com 34 ** mail: support@nxp.com 35 ** 36 ** Revisions: 37 ** - rev. 1.0 (2017-05-19) 38 ** Initial version. 39 ** 40 ** ################################################################### 41 */ 42 43 /*! 44 * @file MKE06Z4 45 * @version 1.0 46 * @date 2017-05-19 47 * @brief Device specific configuration file for MKE06Z4 (implementation file) 48 * 49 * Provides a system configuration function and a global variable that contains 50 * the system frequency. It configures the device and initializes the oscillator 51 * (PLL) that is part of the microcontroller device. 52 */ 53 54 #include <stdint.h> 55 #include "fsl_device_registers.h" 56 57 58 59 /* ---------------------------------------------------------------------------- 60 -- Core clock 61 ---------------------------------------------------------------------------- */ 62 63 uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK; 64 65 /* ---------------------------------------------------------------------------- 66 -- SystemInit() 67 ---------------------------------------------------------------------------- */ 68 SystemInit(void)69void SystemInit (void) { 70 71 #if (DISABLE_WDOG) 72 WDOG->CNT = WDOG_UPDATE_KEY1; 73 WDOG->CNT = WDOG_UPDATE_KEY2; 74 WDOG->TOVAL = 0xFFFFU; 75 WDOG->CS1 = (uint8_t) ((WDOG->CS1) & ~WDOG_CS1_EN_MASK) | WDOG_CS1_UPDATE_MASK; 76 WDOG->CS2 |= 0U; 77 #endif /* (DISABLE_WDOG) */ 78 79 SystemInitHook(); 80 } 81 82 /* ---------------------------------------------------------------------------- 83 -- SystemCoreClockUpdate() 84 ---------------------------------------------------------------------------- */ 85 SystemCoreClockUpdate(void)86void SystemCoreClockUpdate (void) { 87 88 uint32_t ICSOUTClock; /* Variable to store output clock frequency of the ICS module */ 89 uint16_t Divider; 90 uint16_t Temp; 91 92 Divider = (uint16_t)(0x01U) << (((uint16_t)ICS->C2 & ICS_C2_BDIV_MASK) >> ICS_C2_BDIV_SHIFT); 93 94 switch ((ICS->C1 & ICS_C1_CLKS_MASK) >> ICS_C1_CLKS_SHIFT) { 95 case 0x0: 96 /* FLL */ 97 if((ICS->C1 & ICS_C1_IREFS_MASK) != 0x0U) 98 { 99 ICSOUTClock = CPU_INT_IRC_CLK_HZ * 1280UL; 100 } 101 else 102 { 103 /* Reference Divider */ 104 Temp = ((uint16_t)ICS->C1 & ICS_C1_RDIV_MASK) >> ICS_C1_RDIV_SHIFT; 105 Temp = (Temp + 1U) * (((OSC->CR & OSC_CR_RANGE_MASK) != 0x0U) ? 32U : 1U); 106 107 ICSOUTClock = CPU_XTAL_CLK_HZ / Temp * 1280UL; 108 } 109 break; 110 111 case 0x1: 112 /* Internal IRC */ 113 ICSOUTClock = CPU_INT_IRC_CLK_HZ; 114 break; 115 116 case 0x2: 117 /* External OSC */ 118 ICSOUTClock = CPU_XTAL_CLK_HZ; 119 break; 120 121 default: 122 ICSOUTClock = 0U; 123 break; 124 } 125 SystemCoreClock = (ICSOUTClock / Divider); 126 127 } 128 129 /* ---------------------------------------------------------------------------- 130 -- SystemInitHook() 131 ---------------------------------------------------------------------------- */ 132 SystemInitHook(void)133__attribute__ ((weak)) void SystemInitHook (void) { 134 /* Void implementation of the weak function. */ 135 } 136