1 /* This linker script generated from xt-genldscripts.tpp for LSP /home/nxf33034/dev/mcu-sdk-2.0/devices/MIMXRT798S/xtensa/hifi1/gdbio */ 2 /* Linker Script for default link */ 3 MEMORY 4 { 5 iram0_1_seg : org = 0x00580000, len = 0x2E0 6 iram0_3_seg : org = 0x00580400, len = 0x178 7 iram0_4_seg : org = 0x00580578, len = 0x4 8 iram0_5_seg : org = 0x0058057C, len = 0x1C 9 iram0_6_seg : org = 0x00580598, len = 0x4 10 iram0_7_seg : org = 0x0058059C, len = 0x1C 11 iram0_8_seg : org = 0x005805B8, len = 0x4 12 iram0_9_seg : org = 0x005805BC, len = 0x1C 13 iram0_10_seg : org = 0x005805D8, len = 0x4 14 iram0_11_seg : org = 0x005805DC, len = 0x1C 15 iram0_12_seg : org = 0x005805F8, len = 0x4 16 iram0_13_seg : org = 0x005805FC, len = 0x1C 17 iram0_14_seg : org = 0x00580618, len = 0x4 18 iram0_15_seg : org = 0x0058061C, len = 0x1C 19 iram0_16_seg : org = 0x00580638, len = 0x4 20 iram0_17_seg : org = 0x0058063C, len = 0x1C 21 iram1_0_seg : org = 0x00680000, len = 0x80000 22 dram0_0_seg : org = 0x20700000, len = 0x80000 23 } 24 25 PHDRS 26 { 27 iram0_1_phdr PT_LOAD; 28 iram0_2_phdr PT_LOAD; 29 iram0_3_phdr PT_LOAD; 30 iram0_4_phdr PT_LOAD; 31 iram0_5_phdr PT_LOAD; 32 iram0_6_phdr PT_LOAD; 33 iram0_7_phdr PT_LOAD; 34 iram0_8_phdr PT_LOAD; 35 iram0_9_phdr PT_LOAD; 36 iram0_10_phdr PT_LOAD; 37 iram0_11_phdr PT_LOAD; 38 iram0_12_phdr PT_LOAD; 39 iram0_13_phdr PT_LOAD; 40 iram0_14_phdr PT_LOAD; 41 iram0_15_phdr PT_LOAD; 42 iram0_16_phdr PT_LOAD; 43 iram0_17_phdr PT_LOAD; 44 iram0_0_phdr PT_LOAD; 45 iram1_0_phdr PT_LOAD; 46 dram0_0_phdr PT_LOAD; 47 dram0_0_bss_phdr PT_LOAD; 48 } 49 50 51 /* Default entry point: */ 52 ENTRY(_ResetVector) 53 54 55 /* Memory boundary addresses: */ 56 _memmap_mem_iram0_start = 0x580000; 57 _memmap_mem_iram0_end = 0x588000; 58 _memmap_mem_iram1_start = 0x680000; 59 _memmap_mem_iram1_end = 0x700000; 60 _memmap_mem_dram0_start = 0x20700000; 61 _memmap_mem_dram0_end = 0x20780000; 62 63 /* Memory segment boundary addresses: */ 64 _memmap_seg_iram0_1_start = 0x580000; 65 _memmap_seg_iram0_1_max = 0x5802e0; 66 _memmap_seg_iram0_3_start = 0x580400; 67 _memmap_seg_iram0_3_max = 0x580578; 68 _memmap_seg_iram0_4_start = 0x580578; 69 _memmap_seg_iram0_4_max = 0x58057c; 70 _memmap_seg_iram0_5_start = 0x58057c; 71 _memmap_seg_iram0_5_max = 0x580598; 72 _memmap_seg_iram0_6_start = 0x580598; 73 _memmap_seg_iram0_6_max = 0x58059c; 74 _memmap_seg_iram0_7_start = 0x58059c; 75 _memmap_seg_iram0_7_max = 0x5805b8; 76 _memmap_seg_iram0_8_start = 0x5805b8; 77 _memmap_seg_iram0_8_max = 0x5805bc; 78 _memmap_seg_iram0_9_start = 0x5805bc; 79 _memmap_seg_iram0_9_max = 0x5805d8; 80 _memmap_seg_iram0_10_start = 0x5805d8; 81 _memmap_seg_iram0_10_max = 0x5805dc; 82 _memmap_seg_iram0_11_start = 0x5805dc; 83 _memmap_seg_iram0_11_max = 0x5805f8; 84 _memmap_seg_iram0_12_start = 0x5805f8; 85 _memmap_seg_iram0_12_max = 0x5805fc; 86 _memmap_seg_iram0_13_start = 0x5805fc; 87 _memmap_seg_iram0_13_max = 0x580618; 88 _memmap_seg_iram0_14_start = 0x580618; 89 _memmap_seg_iram0_14_max = 0x58061c; 90 _memmap_seg_iram0_15_start = 0x58061c; 91 _memmap_seg_iram0_15_max = 0x580638; 92 _memmap_seg_iram0_16_start = 0x580638; 93 _memmap_seg_iram0_16_max = 0x58063c; 94 _memmap_seg_iram0_17_start = 0x58063c; 95 _memmap_seg_iram0_17_max = 0x580658; 96 _memmap_seg_iram1_0_start = 0x680000; 97 _memmap_seg_iram1_0_max = 0x700000; 98 _memmap_seg_dram0_0_start = 0x20700000; 99 _memmap_seg_dram0_0_max = 0x20780000; 100 101 _rom_store_table = 0; 102 PROVIDE(_memmap_reset_vector = 0x580000); 103 PROVIDE(_memmap_vecbase_reset = 0x580400); 104 /* Various memory-map dependent cache attribute settings: */ 105 _memmap_cacheattr_wb_base = 0x00021022; 106 _memmap_cacheattr_wt_base = 0x00021022; 107 _memmap_cacheattr_bp_base = 0x00022022; 108 _memmap_cacheattr_unused_mask = 0xFFF00F00; 109 _memmap_cacheattr_wb_trapnull = 0x22221222; 110 _memmap_cacheattr_wba_trapnull = 0x22221222; 111 _memmap_cacheattr_wbna_trapnull = 0x22221222; 112 _memmap_cacheattr_wt_trapnull = 0x22221222; 113 _memmap_cacheattr_bp_trapnull = 0x22222222; 114 _memmap_cacheattr_wb_strict = 0xFFF21F22; 115 _memmap_cacheattr_wt_strict = 0xFFF21F22; 116 _memmap_cacheattr_bp_strict = 0xFFF22F22; 117 _memmap_cacheattr_wb_allvalid = 0x22221222; 118 _memmap_cacheattr_wt_allvalid = 0x22221222; 119 _memmap_cacheattr_bp_allvalid = 0x22222222; 120 _memmap_region_map = 0x0000001B; 121 PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull); 122 123 SECTIONS 124 { 125 126 .ResetVector.text : ALIGN(4) 127 { 128 _ResetVector_text_start = ABSOLUTE(.); 129 KEEP (*(.ResetVector.text)) 130 . = ALIGN (4); 131 _ResetVector_text_end = ABSOLUTE(.); 132 } >iram0_1_seg :iram0_1_phdr 133 134 .ResetHandler.text : ALIGN(4) 135 { 136 _ResetHandler_text_start = ABSOLUTE(.); 137 *(.ResetHandler.literal .ResetHandler.text) 138 . = ALIGN (4); 139 _ResetHandler_text_end = ABSOLUTE(.); 140 _memmap_seg_iram0_1_end = ALIGN(0x8); 141 } >iram0_1_seg :iram0_1_phdr 142 143 144 145 .WindowVectors.text : ALIGN(4) 146 { 147 _WindowVectors_text_start = ABSOLUTE(.); 148 KEEP (*(.WindowVectors.text)) 149 . = ALIGN (4); 150 _WindowVectors_text_end = ABSOLUTE(.); 151 _memmap_seg_iram0_3_end = ALIGN(0x8); 152 } >iram0_3_seg :iram0_3_phdr 153 154 155 .Level2InterruptVector.literal : ALIGN(4) 156 { 157 _Level2InterruptVector_literal_start = ABSOLUTE(.); 158 *(.Level2InterruptVector.literal) 159 . = ALIGN (4); 160 _Level2InterruptVector_literal_end = ABSOLUTE(.); 161 _memmap_seg_iram0_4_end = ALIGN(0x8); 162 } >iram0_4_seg :iram0_4_phdr 163 164 165 .Level2InterruptVector.text : ALIGN(4) 166 { 167 _Level2InterruptVector_text_start = ABSOLUTE(.); 168 KEEP (*(.Level2InterruptVector.text)) 169 . = ALIGN (4); 170 _Level2InterruptVector_text_end = ABSOLUTE(.); 171 _memmap_seg_iram0_5_end = ALIGN(0x8); 172 } >iram0_5_seg :iram0_5_phdr 173 174 175 .Level3InterruptVector.literal : ALIGN(4) 176 { 177 _Level3InterruptVector_literal_start = ABSOLUTE(.); 178 *(.Level3InterruptVector.literal) 179 . = ALIGN (4); 180 _Level3InterruptVector_literal_end = ABSOLUTE(.); 181 _memmap_seg_iram0_6_end = ALIGN(0x8); 182 } >iram0_6_seg :iram0_6_phdr 183 184 185 .Level3InterruptVector.text : ALIGN(4) 186 { 187 _Level3InterruptVector_text_start = ABSOLUTE(.); 188 KEEP (*(.Level3InterruptVector.text)) 189 . = ALIGN (4); 190 _Level3InterruptVector_text_end = ABSOLUTE(.); 191 _memmap_seg_iram0_7_end = ALIGN(0x8); 192 } >iram0_7_seg :iram0_7_phdr 193 194 195 .DebugExceptionVector.literal : ALIGN(4) 196 { 197 _DebugExceptionVector_literal_start = ABSOLUTE(.); 198 *(.DebugExceptionVector.literal) 199 . = ALIGN (4); 200 _DebugExceptionVector_literal_end = ABSOLUTE(.); 201 _memmap_seg_iram0_8_end = ALIGN(0x8); 202 } >iram0_8_seg :iram0_8_phdr 203 204 205 .DebugExceptionVector.text : ALIGN(4) 206 { 207 _DebugExceptionVector_text_start = ABSOLUTE(.); 208 KEEP (*(.DebugExceptionVector.text)) 209 . = ALIGN (4); 210 _DebugExceptionVector_text_end = ABSOLUTE(.); 211 _memmap_seg_iram0_9_end = ALIGN(0x8); 212 } >iram0_9_seg :iram0_9_phdr 213 214 215 .NMIExceptionVector.literal : ALIGN(4) 216 { 217 _NMIExceptionVector_literal_start = ABSOLUTE(.); 218 *(.NMIExceptionVector.literal) 219 . = ALIGN (4); 220 _NMIExceptionVector_literal_end = ABSOLUTE(.); 221 _memmap_seg_iram0_10_end = ALIGN(0x8); 222 } >iram0_10_seg :iram0_10_phdr 223 224 225 .NMIExceptionVector.text : ALIGN(4) 226 { 227 _NMIExceptionVector_text_start = ABSOLUTE(.); 228 KEEP (*(.NMIExceptionVector.text)) 229 . = ALIGN (4); 230 _NMIExceptionVector_text_end = ABSOLUTE(.); 231 _memmap_seg_iram0_11_end = ALIGN(0x8); 232 } >iram0_11_seg :iram0_11_phdr 233 234 235 .KernelExceptionVector.literal : ALIGN(4) 236 { 237 _KernelExceptionVector_literal_start = ABSOLUTE(.); 238 *(.KernelExceptionVector.literal) 239 . = ALIGN (4); 240 _KernelExceptionVector_literal_end = ABSOLUTE(.); 241 _memmap_seg_iram0_12_end = ALIGN(0x8); 242 } >iram0_12_seg :iram0_12_phdr 243 244 245 .KernelExceptionVector.text : ALIGN(4) 246 { 247 _KernelExceptionVector_text_start = ABSOLUTE(.); 248 KEEP (*(.KernelExceptionVector.text)) 249 . = ALIGN (4); 250 _KernelExceptionVector_text_end = ABSOLUTE(.); 251 _memmap_seg_iram0_13_end = ALIGN(0x8); 252 } >iram0_13_seg :iram0_13_phdr 253 254 255 .UserExceptionVector.literal : ALIGN(4) 256 { 257 _UserExceptionVector_literal_start = ABSOLUTE(.); 258 *(.UserExceptionVector.literal) 259 . = ALIGN (4); 260 _UserExceptionVector_literal_end = ABSOLUTE(.); 261 _memmap_seg_iram0_14_end = ALIGN(0x8); 262 } >iram0_14_seg :iram0_14_phdr 263 264 265 .UserExceptionVector.text : ALIGN(4) 266 { 267 _UserExceptionVector_text_start = ABSOLUTE(.); 268 KEEP (*(.UserExceptionVector.text)) 269 . = ALIGN (4); 270 _UserExceptionVector_text_end = ABSOLUTE(.); 271 _memmap_seg_iram0_15_end = ALIGN(0x8); 272 } >iram0_15_seg :iram0_15_phdr 273 274 275 .DoubleExceptionVector.literal : ALIGN(4) 276 { 277 _DoubleExceptionVector_literal_start = ABSOLUTE(.); 278 *(.DoubleExceptionVector.literal) 279 . = ALIGN (4); 280 _DoubleExceptionVector_literal_end = ABSOLUTE(.); 281 _memmap_seg_iram0_16_end = ALIGN(0x8); 282 } >iram0_16_seg :iram0_16_phdr 283 284 285 .DoubleExceptionVector.text : ALIGN(4) 286 { 287 _DoubleExceptionVector_text_start = ABSOLUTE(.); 288 KEEP (*(.DoubleExceptionVector.text)) 289 . = ALIGN (4); 290 _DoubleExceptionVector_text_end = ABSOLUTE(.); 291 _memmap_seg_iram0_17_end = ALIGN(0x8); 292 } >iram0_17_seg :iram0_17_phdr 293 294 295 _memmap_mem_iram0_max = ABSOLUTE(.); 296 297 .iram1.text : ALIGN(4) 298 { 299 _iram1_text_start = ABSOLUTE(.); 300 *(.iram1.literal .iram1.text) 301 . = ALIGN (4); 302 _iram1_text_end = ABSOLUTE(.); 303 } >iram1_0_seg :iram1_0_phdr 304 305 .sram.text : ALIGN(4) 306 { 307 _sram_text_start = ABSOLUTE(.); 308 *(.sram.literal .sram.text) 309 . = ALIGN (4); 310 _sram_text_end = ABSOLUTE(.); 311 } >iram1_0_seg :iram1_0_phdr 312 313 .text : ALIGN(4) 314 { 315 _stext = .; 316 _text_start = ABSOLUTE(.); 317 *(.entry.text) 318 *(.init.literal) 319 KEEP(*(.init)) 320 *(.literal.sort.* SORT(.text.sort.*)) 321 KEEP (*(.literal.keepsort.* SORT(.text.keepsort.*) .literal.keep.* .text.keep.* .literal.*personality* .text.*personality*)) 322 *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*) 323 *(.fini.literal) 324 KEEP(*(.fini)) 325 *(.gnu.version) 326 . = ALIGN (4); 327 _text_end = ABSOLUTE(.); 328 _etext = .; 329 } >iram1_0_seg :iram1_0_phdr 330 331 .clib.text : ALIGN(4) 332 { 333 _clib_text_start = ABSOLUTE(.); 334 *(.clib.literal .clib.text) 335 . = ALIGN (4); 336 _clib_text_end = ABSOLUTE(.); 337 } >iram1_0_seg :iram1_0_phdr 338 339 .rtos.text : ALIGN(4) 340 { 341 _rtos_text_start = ABSOLUTE(.); 342 *(.rtos.literal .rtos.text) 343 . = ALIGN (4); 344 _rtos_text_end = ABSOLUTE(.); 345 } >iram1_0_seg :iram1_0_phdr 346 347 _memmap_mem_iram1_max = ABSOLUTE(.); 348 349 .sram.rodata : ALIGN(4) 350 { 351 _sram_rodata_start = ABSOLUTE(.); 352 *(.sram.rodata) 353 . = ALIGN (4); 354 _sram_rodata_end = ABSOLUTE(.); 355 } >dram0_0_seg :dram0_0_phdr 356 357 .clib.rodata : ALIGN(4) 358 { 359 _clib_rodata_start = ABSOLUTE(.); 360 *(.clib.rodata) 361 . = ALIGN (4); 362 _clib_rodata_end = ABSOLUTE(.); 363 } >dram0_0_seg :dram0_0_phdr 364 365 .rtos.rodata : ALIGN(4) 366 { 367 _rtos_rodata_start = ABSOLUTE(.); 368 *(.rtos.rodata) 369 . = ALIGN (4); 370 _rtos_rodata_end = ABSOLUTE(.); 371 } >dram0_0_seg :dram0_0_phdr 372 373 .rodata : ALIGN(4) 374 { 375 _rodata_start = ABSOLUTE(.); 376 *(.rodata) 377 *(SORT(.rodata.sort.*)) 378 KEEP (*(SORT(.rodata.keepsort.*) .rodata.keep.*)) 379 *(.rodata.*) 380 *(.gnu.linkonce.r.*) 381 *(.rodata1) 382 __XT_EXCEPTION_TABLE__ = ABSOLUTE(.); 383 KEEP (*(.xt_except_table)) 384 KEEP (*(.gcc_except_table)) 385 *(.gnu.linkonce.e.*) 386 *(.gnu.version_r) 387 PROVIDE (__eh_frame_start = .); 388 KEEP (*(.eh_frame)) 389 PROVIDE (__eh_frame_end = .); 390 /* C++ constructor and destructor tables, properly ordered: */ 391 KEEP (*crtbegin.o(.ctors)) 392 KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) 393 KEEP (*(SORT(.ctors.*))) 394 KEEP (*(.ctors)) 395 KEEP (*crtbegin.o(.dtors)) 396 KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) 397 KEEP (*(SORT(.dtors.*))) 398 KEEP (*(.dtors)) 399 /* C++ exception handlers table: */ 400 __XT_EXCEPTION_DESCS__ = ABSOLUTE(.); 401 *(.xt_except_desc) 402 *(.gnu.linkonce.h.*) 403 __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.); 404 *(.xt_except_desc_end) 405 *(.dynamic) 406 *(.gnu.version_d) 407 . = ALIGN(4); /* this table MUST be 4-byte aligned */ 408 _bss_table_start = ABSOLUTE(.); 409 LONG(_bss_start) 410 LONG(_bss_end) 411 _bss_table_end = ABSOLUTE(.); 412 . = ALIGN (4); 413 _rodata_end = ABSOLUTE(.); 414 } >dram0_0_seg :dram0_0_phdr 415 416 .dram0.rodata : ALIGN(4) 417 { 418 _dram0_rodata_start = ABSOLUTE(.); 419 *(.dram0.rodata) 420 *(.dram.rodata) 421 . = ALIGN (4); 422 _dram0_rodata_end = ABSOLUTE(.); 423 } >dram0_0_seg :dram0_0_phdr 424 425 .dram0.data : ALIGN(4) 426 { 427 _dram0_data_start = ABSOLUTE(.); 428 *(.dram0.data) 429 *(.dram.data) 430 . = ALIGN (4); 431 _dram0_data_end = ABSOLUTE(.); 432 } >dram0_0_seg :dram0_0_phdr 433 434 .clib.data : ALIGN(4) 435 { 436 _clib_data_start = ABSOLUTE(.); 437 *(.clib.data) 438 . = ALIGN (4); 439 _clib_data_end = ABSOLUTE(.); 440 } >dram0_0_seg :dram0_0_phdr 441 442 .clib.percpu.data : ALIGN(4) 443 { 444 _clib_percpu_data_start = ABSOLUTE(.); 445 *(.clib.percpu.data) 446 . = ALIGN (4); 447 _clib_percpu_data_end = ABSOLUTE(.); 448 } >dram0_0_seg :dram0_0_phdr 449 450 .rtos.percpu.data : ALIGN(4) 451 { 452 _rtos_percpu_data_start = ABSOLUTE(.); 453 *(.rtos.percpu.data) 454 . = ALIGN (4); 455 _rtos_percpu_data_end = ABSOLUTE(.); 456 } >dram0_0_seg :dram0_0_phdr 457 458 .rtos.data : ALIGN(4) 459 { 460 _rtos_data_start = ABSOLUTE(.); 461 *(.rtos.data) 462 . = ALIGN (4); 463 _rtos_data_end = ABSOLUTE(.); 464 } >dram0_0_seg :dram0_0_phdr 465 466 .sram.data : ALIGN(4) 467 { 468 _sram_data_start = ABSOLUTE(.); 469 *(.sram.data) 470 . = ALIGN (4); 471 _sram_data_end = ABSOLUTE(.); 472 } >dram0_0_seg :dram0_0_phdr 473 474 .data : ALIGN(4) 475 { 476 _data_start = ABSOLUTE(.); 477 *(.data) 478 *(SORT(.data.sort.*)) 479 KEEP (*(SORT(.data.keepsort.*) .data.keep.*)) 480 *(.data.*) 481 *(.gnu.linkonce.d.*) 482 KEEP(*(.gnu.linkonce.d.*personality*)) 483 *(.data1) 484 *(.sdata) 485 *(.sdata.*) 486 *(.gnu.linkonce.s.*) 487 *(.sdata2) 488 *(.sdata2.*) 489 *(.gnu.linkonce.s2.*) 490 KEEP(*(.jcr)) 491 *(__llvm_prf_cnts) 492 *(__llvm_prf_data) 493 *(__llvm_prf_vnds) 494 . = ALIGN (4); 495 _data_end = ABSOLUTE(.); 496 } >dram0_0_seg :dram0_0_phdr 497 498 __llvm_prf_names : ALIGN(4) 499 { 500 __llvm_prf_names_start = ABSOLUTE(.); 501 *(__llvm_prf_names) 502 . = ALIGN (4); 503 __llvm_prf_names_end = ABSOLUTE(.); 504 } >dram0_0_seg :dram0_0_phdr 505 506 __llvm_covmap : ALIGN(4) 507 { 508 __llvm_covmap_start = ABSOLUTE(.); 509 *(__llvm_covmap) 510 . = ALIGN (4); 511 __llvm_covmap_end = ABSOLUTE(.); 512 } >dram0_0_seg :dram0_0_phdr 513 514 .note.gnu.build-id : ALIGN(4) 515 { 516 _note_gnu_build-id_start = ABSOLUTE(.); 517 *(.note.gnu.build-id) 518 . = ALIGN (4); 519 _note_gnu_build-id_end = ABSOLUTE(.); 520 } >dram0_0_seg :dram0_0_phdr 521 bss(NOLOAD)522 .bss (NOLOAD) : ALIGN(8) 523 { 524 . = ALIGN (8); 525 _bss_start = ABSOLUTE(.); 526 *(.dynsbss) 527 *(.sbss) 528 *(.sbss.*) 529 *(.gnu.linkonce.sb.*) 530 *(.scommon) 531 *(.sbss2) 532 *(.sbss2.*) 533 *(.gnu.linkonce.sb2.*) 534 *(.dynbss) 535 *(.bss) 536 *(SORT(.bss.sort.*)) 537 KEEP (*(SORT(.bss.keepsort.*) .bss.keep.*)) 538 *(.bss.*) 539 *(.gnu.linkonce.b.*) 540 *(COMMON) 541 *(.clib.bss) 542 *(.clib.percpu.bss) 543 *(.rtos.percpu.bss) 544 *(.rtos.bss) 545 *(.sram.bss) 546 *(.dram0.bss) 547 . = ALIGN (8); 548 _bss_end = ABSOLUTE(.); 549 _end = ALIGN(0x8); 550 PROVIDE(end = ALIGN(0x8)); 551 _stack_sentry = ALIGN(0x8); 552 _memmap_seg_dram0_0_end = ALIGN(0x8); 553 } >dram0_0_seg :dram0_0_bss_phdr 554 555 PROVIDE(__stack = 0x20780000); 556 _heap_sentry = 0x20780000; 557 558 _memmap_mem_dram0_max = ABSOLUTE(.); 559 560 .debug 0 : { *(.debug) } 561 .line 0 : { *(.line) } 562 .debug_srcinfo 0 : { *(.debug_srcinfo) } 563 .debug_sfnames 0 : { *(.debug_sfnames) } 564 .debug_aranges 0 : { *(.debug_aranges) } 565 .debug_ranges 0 : { *(.debug_ranges) } 566 .debug_pubnames 0 : { *(.debug_pubnames) } 567 .debug_info 0 : { *(.debug_info) } 568 .debug_abbrev 0 : { *(.debug_abbrev) } 569 .debug_line 0 : { *(.debug_line) } 570 .debug_frame 0 : { *(.debug_frame) } 571 .debug_str 0 : { *(.debug_str) } 572 .debug_loc 0 : { *(.debug_loc) } 573 .debug_macinfo 0 : { *(.debug_macinfo) } 574 .debug_weaknames 0 : { *(.debug_weaknames) } 575 .debug_funcnames 0 : { *(.debug_funcnames) } 576 .debug_typenames 0 : { *(.debug_typenames) } 577 .debug_varnames 0 : { *(.debug_varnames) } 578 .debug.xt.map 0 : { *(.debug.xt.map) } 579 .xt.insn 0 : 580 { 581 KEEP (*(.xt.insn)) 582 KEEP (*(.gnu.linkonce.x.*)) 583 } 584 .xt.prop 0 : 585 { 586 *(.xt.prop) 587 *(.xt.prop.*) 588 *(.gnu.linkonce.prop.*) 589 } 590 .xt.lit 0 : 591 { 592 *(.xt.lit) 593 *(.xt.lit.*) 594 *(.gnu.linkonce.p.*) 595 } 596 .xtensa.info 0 : 597 { 598 *(.xtensa.info) 599 } 600 .debug.xt.callgraph 0 : 601 { 602 KEEP (*(.debug.xt.callgraph .debug.xt.callgraph.* .gnu.linkonce.xt.callgraph.*)) 603 } 604 .comment 0 : 605 { 606 KEEP(*(.comment)) 607 } 608 .note.GNU-stack 0 : 609 { 610 *(.note.GNU-stack) 611 } 612 } 613 614
