1 /* 2 ** ################################################################### 3 ** Processors: LPC804M101JDH20 4 ** LPC804M101JDH24 5 ** LPC804M101JHI33 6 ** LPC804M111JDH24 7 ** LPC804UK 8 ** 9 ** Compilers: GNU C Compiler 10 ** IAR ANSI C/C++ Compiler for ARM 11 ** Keil ARM C/C++ Compiler 12 ** MCUXpresso Compiler 13 ** 14 ** Reference manual: LPC804 User manual Rev.1.0 24 Jan 2018 15 ** Version: rev. 1.0, 2018-01-09 16 ** Build: b200521 17 ** 18 ** Abstract: 19 ** CMSIS Peripheral Access Layer for LPC804 20 ** 21 ** Copyright 1997-2016 Freescale Semiconductor, Inc. 22 ** Copyright 2016-2020 NXP 23 ** All rights reserved. 24 ** 25 ** SPDX-License-Identifier: BSD-3-Clause 26 ** 27 ** http: www.nxp.com 28 ** mail: support@nxp.com 29 ** 30 ** Revisions: 31 ** - rev. 1.0 (2018-01-09) 32 ** Initial version. 33 ** 34 ** ################################################################### 35 */ 36 37 /*! 38 * @file LPC804.h 39 * @version 1.0 40 * @date 2018-01-09 41 * @brief CMSIS Peripheral Access Layer for LPC804 42 * 43 * CMSIS Peripheral Access Layer for LPC804 44 */ 45 46 #ifndef _LPC804_H_ 47 #define _LPC804_H_ /**< Symbol preventing repeated inclusion */ 48 49 /** Memory map major version (memory maps with equal major version number are 50 * compatible) */ 51 #define MCU_MEM_MAP_VERSION 0x0100U 52 /** Memory map minor version */ 53 #define MCU_MEM_MAP_VERSION_MINOR 0x0000U 54 55 56 /* ---------------------------------------------------------------------------- 57 -- Interrupt vector numbers 58 ---------------------------------------------------------------------------- */ 59 60 /*! 61 * @addtogroup Interrupt_vector_numbers Interrupt vector numbers 62 * @{ 63 */ 64 65 /** Interrupt Number Definitions */ 66 #define NUMBER_OF_INT_VECTORS 48 /**< Number of interrupts in the Vector table */ 67 68 typedef enum IRQn { 69 /* Auxiliary constants */ 70 NotAvail_IRQn = -128, /**< Not available device specific interrupt */ 71 72 /* Core interrupts */ 73 NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ 74 HardFault_IRQn = -13, /**< Cortex-M0 SV Hard Fault Interrupt */ 75 SVCall_IRQn = -5, /**< Cortex-M0 SV Call Interrupt */ 76 PendSV_IRQn = -2, /**< Cortex-M0 Pend SV Interrupt */ 77 SysTick_IRQn = -1, /**< Cortex-M0 System Tick Interrupt */ 78 79 /* Device specific interrupts */ 80 SPI0_IRQn = 0, /**< SPI0 interrupt */ 81 Reserved17_IRQn = 1, /**< Reserved interrupt */ 82 DAC0_IRQn = 2, /**< DAC0 interrupt */ 83 USART0_IRQn = 3, /**< USART0 interrupt */ 84 USART1_IRQn = 4, /**< USART1 interrupt */ 85 Reserved21_IRQn = 5, /**< Reserved interrupt */ 86 Reserved22_IRQn = 6, /**< Reserved interrupt */ 87 I2C1_IRQn = 7, /**< I2C1 interrupt */ 88 I2C0_IRQn = 8, /**< I2C0 interrupt */ 89 Reserved25_IRQn = 9, /**< Reserved interrupt */ 90 MRT0_IRQn = 10, /**< Multi-rate timer interrupt */ 91 CMP_CAPT_IRQn = 11, /**< Analog comparator interrupt or Capacitive Touch interrupt */ 92 WDT_IRQn = 12, /**< Windowed watchdog timer interrupt */ 93 BOD_IRQn = 13, /**< BOD interrupts */ 94 FLASH_IRQn = 14, /**< flash interrupt */ 95 WKT_IRQn = 15, /**< Self-wake-up timer interrupt */ 96 ADC_SEQA_IRQn = 16, /**< ADC sequence A completion. */ 97 ADC_SEQB_IRQn = 17, /**< ADC sequence B completion. */ 98 ADC_THCMP_IRQn = 18, /**< ADC threshold compare and error. */ 99 ADC_OVR_IRQn = 19, /**< ADC overrun */ 100 Reserved36_IRQn = 20, /**< Reserved interrupt */ 101 Reserved37_IRQn = 21, /**< Reserved interrupt */ 102 Reserved38_IRQn = 22, /**< Reserved interrupt */ 103 CTIMER0_IRQn = 23, /**< Timer interrupt */ 104 PIN_INT0_IRQn = 24, /**< Pin interrupt 0 or pattern match engine slice 0 interrupt */ 105 PIN_INT1_IRQn = 25, /**< Pin interrupt 1 or pattern match engine slice 1 interrupt */ 106 PIN_INT2_IRQn = 26, /**< Pin interrupt 2 or pattern match engine slice 2 interrupt */ 107 PIN_INT3_IRQn = 27, /**< Pin interrupt 3 or pattern match engine slice 3 interrupt */ 108 PIN_INT4_IRQn = 28, /**< Pin interrupt 4 or pattern match engine slice 4 interrupt */ 109 PIN_INT5_IRQn = 29, /**< Pin interrupt 5 or pattern match engine slice 5 interrupt */ 110 PIN_INT6_IRQn = 30, /**< Pin interrupt 6 or pattern match engine slice 6 interrupt */ 111 PIN_INT7_IRQn = 31 /**< Pin interrupt 7 or pattern match engine slice 7 interrupt */ 112 } IRQn_Type; 113 114 /*! 115 * @} 116 */ /* end of group Interrupt_vector_numbers */ 117 118 119 /* ---------------------------------------------------------------------------- 120 -- Cortex M0 Core Configuration 121 ---------------------------------------------------------------------------- */ 122 123 /*! 124 * @addtogroup Cortex_Core_Configuration Cortex M0 Core Configuration 125 * @{ 126 */ 127 128 #define __CM0PLUS_REV 0x0000 /**< Core revision r0p0 */ 129 #define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */ 130 #define __VTOR_PRESENT 1 /**< Defines if VTOR is present or not */ 131 #define __NVIC_PRIO_BITS 2 /**< Number of priority bits implemented in the NVIC */ 132 #define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */ 133 134 #include "core_cm0plus.h" /* Core Peripheral Access Layer */ 135 #include "system_LPC804.h" /* Device specific configuration file */ 136 137 /*! 138 * @} 139 */ /* end of group Cortex_Core_Configuration */ 140 141 142 /* ---------------------------------------------------------------------------- 143 -- Device Peripheral Access Layer 144 ---------------------------------------------------------------------------- */ 145 146 /*! 147 * @addtogroup Peripheral_access_layer Device Peripheral Access Layer 148 * @{ 149 */ 150 151 152 /* 153 ** Start of section using anonymous unions 154 */ 155 156 #if defined(__ARMCC_VERSION) 157 #if (__ARMCC_VERSION >= 6010050) 158 #pragma clang diagnostic push 159 #else 160 #pragma push 161 #pragma anon_unions 162 #endif 163 #elif defined(__GNUC__) 164 /* anonymous unions are enabled by default */ 165 #elif defined(__IAR_SYSTEMS_ICC__) 166 #pragma language=extended 167 #else 168 #error Not supported compiler type 169 #endif 170 171 /* ---------------------------------------------------------------------------- 172 -- ACOMP Peripheral Access Layer 173 ---------------------------------------------------------------------------- */ 174 175 /*! 176 * @addtogroup ACOMP_Peripheral_Access_Layer ACOMP Peripheral Access Layer 177 * @{ 178 */ 179 180 /** ACOMP - Register Layout Typedef */ 181 typedef struct { 182 __IO uint32_t CTRL; /**< Comparator control register, offset: 0x0 */ 183 __IO uint32_t LAD; /**< Voltage ladder register, offset: 0x4 */ 184 } ACOMP_Type; 185 186 /* ---------------------------------------------------------------------------- 187 -- ACOMP Register Masks 188 ---------------------------------------------------------------------------- */ 189 190 /*! 191 * @addtogroup ACOMP_Register_Masks ACOMP Register Masks 192 * @{ 193 */ 194 195 /*! @name CTRL - Comparator control register */ 196 /*! @{ */ 197 #define ACOMP_CTRL_EDGESEL_MASK (0x18U) 198 #define ACOMP_CTRL_EDGESEL_SHIFT (3U) 199 /*! EDGESEL - This field controls which edges on the comparator output set the COMPEDGE bit (bit 23 below): 200 * 0b00..Falling edges 201 * 0b01..Rising edges 202 * 0b10..Both edges 203 * 0b11..Both edges 204 */ 205 #define ACOMP_CTRL_EDGESEL(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_CTRL_EDGESEL_SHIFT)) & ACOMP_CTRL_EDGESEL_MASK) 206 #define ACOMP_CTRL_COMPSA_MASK (0x40U) 207 #define ACOMP_CTRL_COMPSA_SHIFT (6U) 208 /*! COMPSA - Comparator output control 209 * 0b0..Comparator output is used directly. 210 * 0b1..Comparator output is synchronized to the bus clock for output to other modules. 211 */ 212 #define ACOMP_CTRL_COMPSA(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_CTRL_COMPSA_SHIFT)) & ACOMP_CTRL_COMPSA_MASK) 213 #define ACOMP_CTRL_COMP_VP_SEL_MASK (0x700U) 214 #define ACOMP_CTRL_COMP_VP_SEL_SHIFT (8U) 215 /*! COMP_VP_SEL - Selects positive voltage input 216 * 0b000..VOLTAGE_LADDER_OUTPUT 217 * 0b001..ACMP_I1 218 * 0b010..ACMP_I2 219 * 0b011..ACMP_I3 220 * 0b100..ACMP_I4 221 * 0b101..ACMP_I5 222 * 0b110..Band gap. Internal reference voltage. 223 * 0b111..DAC0 output 224 */ 225 #define ACOMP_CTRL_COMP_VP_SEL(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_CTRL_COMP_VP_SEL_SHIFT)) & ACOMP_CTRL_COMP_VP_SEL_MASK) 226 #define ACOMP_CTRL_COMP_VM_SEL_MASK (0x3800U) 227 #define ACOMP_CTRL_COMP_VM_SEL_SHIFT (11U) 228 /*! COMP_VM_SEL - Selects negative voltage input 229 * 0b000..VOLTAGE_LADDER_OUTPUT 230 * 0b001..ACMP_I1 231 * 0b010..ACMP_I2 232 * 0b011..ACMP_I3 233 * 0b100..ACMP_I4 234 * 0b101..ACMP_I5 235 * 0b110..Band gap. Internal reference voltage. 236 * 0b111..DAC0 output 237 */ 238 #define ACOMP_CTRL_COMP_VM_SEL(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_CTRL_COMP_VM_SEL_SHIFT)) & ACOMP_CTRL_COMP_VM_SEL_MASK) 239 #define ACOMP_CTRL_EDGECLR_MASK (0x100000U) 240 #define ACOMP_CTRL_EDGECLR_SHIFT (20U) 241 /*! EDGECLR - Interrupt clear bit. To clear the COMPEDGE bit and thus negate the interrupt request, 242 * toggle the EDGECLR bit by first writing a 1 and then a 0. 243 */ 244 #define ACOMP_CTRL_EDGECLR(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_CTRL_EDGECLR_SHIFT)) & ACOMP_CTRL_EDGECLR_MASK) 245 #define ACOMP_CTRL_COMPSTAT_MASK (0x200000U) 246 #define ACOMP_CTRL_COMPSTAT_SHIFT (21U) 247 /*! COMPSTAT - Comparator status. This bit reflects the state of the comparator output. 248 */ 249 #define ACOMP_CTRL_COMPSTAT(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_CTRL_COMPSTAT_SHIFT)) & ACOMP_CTRL_COMPSTAT_MASK) 250 #define ACOMP_CTRL_COMPEDGE_MASK (0x800000U) 251 #define ACOMP_CTRL_COMPEDGE_SHIFT (23U) 252 /*! COMPEDGE - Comparator edge-detect status. 253 */ 254 #define ACOMP_CTRL_COMPEDGE(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_CTRL_COMPEDGE_SHIFT)) & ACOMP_CTRL_COMPEDGE_MASK) 255 #define ACOMP_CTRL_INTENA_MASK (0x1000000U) 256 #define ACOMP_CTRL_INTENA_SHIFT (24U) 257 /*! INTENA - Must be set to generate interrupts. 258 */ 259 #define ACOMP_CTRL_INTENA(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_CTRL_INTENA_SHIFT)) & ACOMP_CTRL_INTENA_MASK) 260 #define ACOMP_CTRL_HYS_MASK (0x6000000U) 261 #define ACOMP_CTRL_HYS_SHIFT (25U) 262 /*! HYS - Controls the hysteresis of the comparator. When the comparator is outputting a certain 263 * state, this is the difference between the selected signals, in the opposite direction from the 264 * state being output, that will switch the output. 265 * 0b00..None (the output will switch as the voltages cross) 266 * 0b01..5 mv 267 * 0b10..10 mv 268 * 0b11..20 mv 269 */ 270 #define ACOMP_CTRL_HYS(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_CTRL_HYS_SHIFT)) & ACOMP_CTRL_HYS_MASK) 271 /*! @} */ 272 273 /*! @name LAD - Voltage ladder register */ 274 /*! @{ */ 275 #define ACOMP_LAD_LADEN_MASK (0x1U) 276 #define ACOMP_LAD_LADEN_SHIFT (0U) 277 /*! LADEN - Voltage ladder enable 278 */ 279 #define ACOMP_LAD_LADEN(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_LAD_LADEN_SHIFT)) & ACOMP_LAD_LADEN_MASK) 280 #define ACOMP_LAD_LADSEL_MASK (0x3EU) 281 #define ACOMP_LAD_LADSEL_SHIFT (1U) 282 /*! LADSEL - Voltage ladder value. The reference voltage Vref depends on the LADREF bit below. 00000 283 * = VSS 00001 = 1 x Vref/31 00010 = 2 x Vref/31 ... 11111 = Vref 284 */ 285 #define ACOMP_LAD_LADSEL(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_LAD_LADSEL_SHIFT)) & ACOMP_LAD_LADSEL_MASK) 286 #define ACOMP_LAD_LADREF_MASK (0x40U) 287 #define ACOMP_LAD_LADREF_SHIFT (6U) 288 /*! LADREF - Selects the reference voltage Vref for the voltage ladder. 289 * 0b0..Supply pin VDD 290 * 0b1..VDDCMP pin 291 */ 292 #define ACOMP_LAD_LADREF(x) (((uint32_t)(((uint32_t)(x)) << ACOMP_LAD_LADREF_SHIFT)) & ACOMP_LAD_LADREF_MASK) 293 /*! @} */ 294 295 296 /*! 297 * @} 298 */ /* end of group ACOMP_Register_Masks */ 299 300 301 /* ACOMP - Peripheral instance base addresses */ 302 /** Peripheral ACOMP base address */ 303 #define ACOMP_BASE (0x40024000u) 304 /** Peripheral ACOMP base pointer */ 305 #define ACOMP ((ACOMP_Type *)ACOMP_BASE) 306 /** Array initializer of ACOMP peripheral base addresses */ 307 #define ACOMP_BASE_ADDRS { ACOMP_BASE } 308 /** Array initializer of ACOMP peripheral base pointers */ 309 #define ACOMP_BASE_PTRS { ACOMP } 310 311 /*! 312 * @} 313 */ /* end of group ACOMP_Peripheral_Access_Layer */ 314 315 316 /* ---------------------------------------------------------------------------- 317 -- ADC Peripheral Access Layer 318 ---------------------------------------------------------------------------- */ 319 320 /*! 321 * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer 322 * @{ 323 */ 324 325 /** ADC - Register Layout Typedef */ 326 typedef struct { 327 __IO uint32_t CTRL; /**< ADC Control register. Contains the clock divide value, resolution selection, sampling time selection, and mode controls., offset: 0x0 */ 328 uint8_t RESERVED_0[4]; 329 __IO uint32_t SEQ_CTRL[2]; /**< ADC Conversion Sequence-n control register: Controls triggering and channel selection for conversion sequence-n. Also specifies interrupt mode for sequence-n., array offset: 0x8, array step: 0x4 */ 330 __I uint32_t SEQ_GDAT[2]; /**< ADC Sequence-n Global Data register. This register contains the result of the most recent ADC conversion performed under sequence-n., array offset: 0x10, array step: 0x4 */ 331 uint8_t RESERVED_1[8]; 332 __I uint32_t DAT[12]; /**< ADC Channel N Data register. This register contains the result of the most recent conversion completed on channel N., array offset: 0x20, array step: 0x4 */ 333 __IO uint32_t THR0_LOW; /**< ADC Low Compare Threshold register 0: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 0., offset: 0x50 */ 334 __IO uint32_t THR1_LOW; /**< ADC Low Compare Threshold register 1: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 1., offset: 0x54 */ 335 __IO uint32_t THR0_HIGH; /**< ADC High Compare Threshold register 0: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 0., offset: 0x58 */ 336 __IO uint32_t THR1_HIGH; /**< ADC High Compare Threshold register 1: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 1., offset: 0x5C */ 337 __IO uint32_t CHAN_THRSEL; /**< ADC Channel-Threshold Select register. Specifies which set of threshold compare registers are to be used for each channel, offset: 0x60 */ 338 __IO uint32_t INTEN; /**< ADC Interrupt Enable register. This register contains enable bits that enable the sequence-A, sequence-B, threshold compare and data overrun interrupts to be generated., offset: 0x64 */ 339 __IO uint32_t FLAGS; /**< ADC Flags register. Contains the four interrupt/DMA trigger flags and the individual component overrun and threshold-compare flags. (The overrun bits replicate information stored in the result registers)., offset: 0x68 */ 340 } ADC_Type; 341 342 /* ---------------------------------------------------------------------------- 343 -- ADC Register Masks 344 ---------------------------------------------------------------------------- */ 345 346 /*! 347 * @addtogroup ADC_Register_Masks ADC Register Masks 348 * @{ 349 */ 350 351 /*! @name CTRL - ADC Control register. Contains the clock divide value, resolution selection, sampling time selection, and mode controls. */ 352 /*! @{ */ 353 #define ADC_CTRL_CLKDIV_MASK (0xFFU) 354 #define ADC_CTRL_CLKDIV_SHIFT (0U) 355 /*! CLKDIV - In synchronous mode only, the system clock is divided by this value plus one to produce 356 * the clock for the ADC converter, which should be less than or equal to 72 MHz. Typically, 357 * software should program the smallest value in this field that yields this maximum clock rate or 358 * slightly less, but in certain cases (such as a high-impedance analog source) a slower clock may 359 * be desirable. This field is ignored in the asynchronous operating mode. 360 */ 361 #define ADC_CTRL_CLKDIV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CLKDIV_SHIFT)) & ADC_CTRL_CLKDIV_MASK) 362 #define ADC_CTRL_LPWRMODE_MASK (0x400U) 363 #define ADC_CTRL_LPWRMODE_SHIFT (10U) 364 /*! LPWRMODE - The low-power ADC mode 365 * 0b0..The low-power ADC mode is disabled. The analog circuitry remains activated even when no conversions are requested. 366 * 0b1..The low-power ADC mode is enabled. The analog circuitry is automatically powered-down when no conversions 367 * are taking place. When any (hardware or software) triggering event is detected, the analog circuitry is 368 * enabled. After the required start-up time, the requested conversion will be launched. Once the conversion 369 * completes, the analog-circuitry will again be powered-down provided no further conversions are pending. 370 * Using this mode can save an appreciable amount of current (approximately 2.5 mA) when conversions are 371 * required relatively infrequently. The penalty for using this mode is an approximately FIFTEEN ADC CLOCK delay (30 372 * clocks in 10-bit mode), based on the frequency specified in the CLKDIV field, from the time the trigger 373 * event occurs until sampling of the A/D input commences. Note: This mode will NOT power-up the A/D if the 374 * ADC_ENA bit is low. 375 */ 376 #define ADC_CTRL_LPWRMODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_LPWRMODE_SHIFT)) & ADC_CTRL_LPWRMODE_MASK) 377 /*! @} */ 378 379 /*! @name SEQ_CTRL - ADC Conversion Sequence-n control register: Controls triggering and channel selection for conversion sequence-n. Also specifies interrupt mode for sequence-n. */ 380 /*! @{ */ 381 #define ADC_SEQ_CTRL_CHANNELS_MASK (0xFFFU) 382 #define ADC_SEQ_CTRL_CHANNELS_SHIFT (0U) 383 /*! CHANNELS - Selects which one or more of the ADC channels will be sampled and converted when this 384 * sequence is launched. A 1 in any bit of this field will cause the corresponding channel to be 385 * included in the conversion sequence, where bit 0 corresponds to channel 0, bit 1 to channel 1 386 * and so forth. When this conversion sequence is triggered, either by a hardware trigger or via 387 * software command, ADC conversions will be performed on each enabled channel, in sequence, 388 * beginning with the lowest-ordered channel. This field can ONLY be changed while SEQA_ENA (bit 31) 389 * is LOW. It is allowed to change this field and set bit 31 in the same write. 390 */ 391 #define ADC_SEQ_CTRL_CHANNELS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_CHANNELS_SHIFT)) & ADC_SEQ_CTRL_CHANNELS_MASK) 392 #define ADC_SEQ_CTRL_TRIGGER_MASK (0x7000U) 393 #define ADC_SEQ_CTRL_TRIGGER_SHIFT (12U) 394 /*! TRIGGER - Selects which of the available hardware trigger sources will cause this conversion 395 * sequence to be initiated. Program the trigger input number in this field. See Table 476. In order 396 * to avoid generating a spurious trigger, it is recommended writing to this field only when 397 * SEQA_ENA (bit 31) is low. It is safe to change this field and set bit 31 in the same write. 398 */ 399 #define ADC_SEQ_CTRL_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_TRIGGER_SHIFT)) & ADC_SEQ_CTRL_TRIGGER_MASK) 400 #define ADC_SEQ_CTRL_TRIGPOL_MASK (0x40000U) 401 #define ADC_SEQ_CTRL_TRIGPOL_SHIFT (18U) 402 /*! TRIGPOL - Select the polarity of the selected input trigger for this conversion sequence. In 403 * order to avoid generating a spurious trigger, it is recommended writing to this field only when 404 * SEQA_ENA (bit 31) is low. It is safe to change this field and set bit 31 in the same write. 405 * 0b0..Negative edge. A negative edge launches the conversion sequence on the selected trigger input. 406 * 0b1..Positive edge. A positive edge launches the conversion sequence on the selected trigger input. 407 */ 408 #define ADC_SEQ_CTRL_TRIGPOL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_TRIGPOL_SHIFT)) & ADC_SEQ_CTRL_TRIGPOL_MASK) 409 #define ADC_SEQ_CTRL_SYNCBYPASS_MASK (0x80000U) 410 #define ADC_SEQ_CTRL_SYNCBYPASS_SHIFT (19U) 411 /*! SYNCBYPASS - Setting this bit allows the hardware trigger input to bypass synchronization 412 * flip-flop stages and therefore shorten the time between the trigger input signal and the start of a 413 * conversion. There are slightly different criteria for whether or not this bit can be set 414 * depending on the clock operating mode: Synchronous mode (the ASYNMODE in the CTRL register = 0): 415 * Synchronization may be bypassed (this bit may be set) if the selected trigger source is already 416 * synchronous with the main system clock (eg. coming from an on-chip, system-clock-based timer). 417 * Whether this bit is set or not, a trigger pulse must be maintained for at least one system 418 * clock period. Asynchronous mode (the ASYNMODE in the CTRL register = 1): Synchronization may be 419 * bypassed (this bit may be set) if it is certain that the duration of a trigger input pulse 420 * will be at least one cycle of the ADC clock (regardless of whether the trigger comes from and 421 * on-chip or off-chip source). If this bit is NOT set, the trigger pulse must at least be 422 * maintained for one system clock period. 423 * 0b0..Enable trigger synchronization. The hardware trigger bypass is not enabled. 424 * 0b1..Bypass trigger synchronization. The hardware trigger bypass is enabled. 425 */ 426 #define ADC_SEQ_CTRL_SYNCBYPASS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_SYNCBYPASS_SHIFT)) & ADC_SEQ_CTRL_SYNCBYPASS_MASK) 427 #define ADC_SEQ_CTRL_TSAMP_MASK (0x1F00000U) 428 #define ADC_SEQ_CTRL_TSAMP_SHIFT (20U) 429 /*! TSAMP - Sample Time The default sample period (TSAMP = "00000") at the beginning of each new 430 * conversion is 6.5 ADC clock periods. Depending on a variety of factors including ADC clock rate, 431 * output impedance of the analog source driver, ADC resolution, and the selection of channels, 432 * the sample time may need to be increased. The value programmed into the TSAMP fields dictates 433 * the number of additional ADC clock cycles (beyond 6.5) that the sample period will be extended 434 * by. Note that any additional clocks of sample time inserted will add directly to the overall 435 * number of clocks required for a conversion, effectively reducing the overall conversion 436 * throughput rate. 437 */ 438 #define ADC_SEQ_CTRL_TSAMP(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_TSAMP_SHIFT)) & ADC_SEQ_CTRL_TSAMP_MASK) 439 #define ADC_SEQ_CTRL_START_MASK (0x4000000U) 440 #define ADC_SEQ_CTRL_START_SHIFT (26U) 441 /*! START - Writing a 1 to this field will launch one pass through this conversion sequence. The 442 * behavior will be identical to a sequence triggered by a hardware trigger. Do not write 1 to this 443 * bit if the BURST bit is set. This bit is only set to a 1 momentarily when written to launch a 444 * conversion sequence. It will consequently always read back as a zero. 445 */ 446 #define ADC_SEQ_CTRL_START(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_START_SHIFT)) & ADC_SEQ_CTRL_START_MASK) 447 #define ADC_SEQ_CTRL_BURST_MASK (0x8000000U) 448 #define ADC_SEQ_CTRL_BURST_SHIFT (27U) 449 /*! BURST - Writing a 1 to this bit will cause this conversion sequence to be continuously cycled 450 * through. Other sequence A triggers will be ignored while this bit is set. Repeated conversions 451 * can be halted by clearing this bit. The sequence currently in progress will be completed before 452 * conversions are terminated. Note that a new sequence could begin just before BURST is cleared. 453 */ 454 #define ADC_SEQ_CTRL_BURST(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_BURST_SHIFT)) & ADC_SEQ_CTRL_BURST_MASK) 455 #define ADC_SEQ_CTRL_SINGLESTEP_MASK (0x10000000U) 456 #define ADC_SEQ_CTRL_SINGLESTEP_SHIFT (28U) 457 /*! SINGLESTEP - When this bit is set, a hardware trigger or a write to the START bit will launch a 458 * single conversion on the next channel in the sequence instead of the default response of 459 * launching an entire sequence of conversions. Once all of the channels comprising a sequence have 460 * been converted, a subsequent trigger will repeat the sequence beginning with the first enabled 461 * channel. Interrupt generation will still occur either after each individual conversion or at 462 * the end of the entire sequence, depending on the state of the MODE bit. 463 */ 464 #define ADC_SEQ_CTRL_SINGLESTEP(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_SINGLESTEP_SHIFT)) & ADC_SEQ_CTRL_SINGLESTEP_MASK) 465 #define ADC_SEQ_CTRL_LOWPRIO_MASK (0x20000000U) 466 #define ADC_SEQ_CTRL_LOWPRIO_SHIFT (29U) 467 /*! LOWPRIO - Set priority for sequence A. 468 * 0b0..Low priority. Any B trigger which occurs while an A conversion sequence is active will be ignored and lost. 469 * 0b1..High priority. Setting this bit to a 1 will permit any enabled B sequence trigger (including a B sequence 470 * software start) to immediately interrupt sequence A and launch a B sequence in it's place. The conversion 471 * currently in progress will be terminated. The A sequence that was interrupted will automatically resume 472 * after the B sequence completes. The channel whose conversion was terminated will be re-sampled and the 473 * conversion sequence will resume from that point. 474 */ 475 #define ADC_SEQ_CTRL_LOWPRIO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_LOWPRIO_SHIFT)) & ADC_SEQ_CTRL_LOWPRIO_MASK) 476 #define ADC_SEQ_CTRL_MODE_MASK (0x40000000U) 477 #define ADC_SEQ_CTRL_MODE_SHIFT (30U) 478 /*! MODE - Indicates whether the primary method for retrieving conversion results for this sequence 479 * will be accomplished via reading the global data register (SEQA_GDAT) at the end of each 480 * conversion, or the individual channel result registers at the end of the entire sequence. Impacts 481 * when conversion-complete interrupt/DMA trigger for sequence-A will be generated and which 482 * overrun conditions contribute to an overrun interrupt as described below. 483 * 0b0..End of conversion. The sequence A interrupt/DMA trigger will be set at the end of each individual ADC 484 * conversion performed under sequence A. This flag will mirror the DATAVALID bit in the SEQA_GDAT register. The 485 * OVERRUN bit in the SEQA_GDAT register will contribute to generation of an overrun interrupt/DMA trigger 486 * if enabled. 487 * 0b1..End of sequence. The sequence A interrupt/DMA trigger will be set when the entire set of sequence-A 488 * conversions completes. This flag will need to be explicitly cleared by software or by the DMA-clear signal in 489 * this mode. The OVERRUN bit in the SEQA_GDAT register will NOT contribute to generation of an overrun 490 * interrupt/DMA trigger since it is assumed this register may not be utilized in this mode. 491 */ 492 #define ADC_SEQ_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_MODE_SHIFT)) & ADC_SEQ_CTRL_MODE_MASK) 493 #define ADC_SEQ_CTRL_SEQ_ENA_MASK (0x80000000U) 494 #define ADC_SEQ_CTRL_SEQ_ENA_SHIFT (31U) 495 /*! SEQ_ENA - Sequence Enable. In order to avoid spuriously triggering the sequence, care should be 496 * taken to only set the SEQn_ENA bit when the selected trigger input is in its INACTIVE state 497 * (as defined by the TRIGPOL bit). If this condition is not met, the sequence will be triggered 498 * immediately upon being enabled. In order to avoid spuriously triggering the sequence, care 499 * should be taken to only set the SEQn_ENA bit when the selected trigger input is in its INACTIVE 500 * state (as defined by the TRIGPOL bit). If this condition is not met, the sequence will be 501 * triggered immediately upon being enabled. 502 * 0b0..Disabled. Sequence n is disabled. Sequence n triggers are ignored. If this bit is cleared while sequence 503 * n is in progress, the sequence will be halted at the end of the current conversion. After the sequence is 504 * re-enabled, a new trigger will be required to restart the sequence beginning with the next enabled channel. 505 * 0b1..Enabled. Sequence n is enabled. 506 */ 507 #define ADC_SEQ_CTRL_SEQ_ENA(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_SEQ_ENA_SHIFT)) & ADC_SEQ_CTRL_SEQ_ENA_MASK) 508 /*! @} */ 509 510 /* The count of ADC_SEQ_CTRL */ 511 #define ADC_SEQ_CTRL_COUNT (2U) 512 513 /*! @name SEQ_GDAT - ADC Sequence-n Global Data register. This register contains the result of the most recent ADC conversion performed under sequence-n. */ 514 /*! @{ */ 515 #define ADC_SEQ_GDAT_RESULT_MASK (0xFFF0U) 516 #define ADC_SEQ_GDAT_RESULT_SHIFT (4U) 517 /*! RESULT - This field contains the 12-bit ADC conversion result from the most recent conversion 518 * performed under conversion sequence associated with this register. The result is a binary 519 * fraction representing the voltage on the currently-selected input channel as it falls within the 520 * range of VREFP to VREFN. Zero in the field indicates that the voltage on the input pin was less 521 * than, equal to, or close to that on VREFN, while 0xFFF indicates that the voltage on the input 522 * was close to, equal to, or greater than that on VREFP. DATAVALID = 1 indicates that this 523 * result has not yet been read. 524 */ 525 #define ADC_SEQ_GDAT_RESULT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_RESULT_SHIFT)) & ADC_SEQ_GDAT_RESULT_MASK) 526 #define ADC_SEQ_GDAT_THCMPRANGE_MASK (0x30000U) 527 #define ADC_SEQ_GDAT_THCMPRANGE_SHIFT (16U) 528 /*! THCMPRANGE - Indicates whether the result of the last conversion performed was above, below or 529 * within the range established by the designated threshold comparison registers (THRn_LOW and 530 * THRn_HIGH). 531 */ 532 #define ADC_SEQ_GDAT_THCMPRANGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_THCMPRANGE_SHIFT)) & ADC_SEQ_GDAT_THCMPRANGE_MASK) 533 #define ADC_SEQ_GDAT_THCMPCROSS_MASK (0xC0000U) 534 #define ADC_SEQ_GDAT_THCMPCROSS_SHIFT (18U) 535 /*! THCMPCROSS - Indicates whether the result of the last conversion performed represented a 536 * crossing of the threshold level established by the designated LOW threshold comparison register 537 * (THRn_LOW) and, if so, in what direction the crossing occurred. 538 */ 539 #define ADC_SEQ_GDAT_THCMPCROSS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_THCMPCROSS_SHIFT)) & ADC_SEQ_GDAT_THCMPCROSS_MASK) 540 #define ADC_SEQ_GDAT_CHN_MASK (0x3C000000U) 541 #define ADC_SEQ_GDAT_CHN_SHIFT (26U) 542 /*! CHN - These bits contain the channel from which the RESULT bits were converted (e.g. 0000 543 * identifies channel 0, 0001 channel 1, etc.). 544 */ 545 #define ADC_SEQ_GDAT_CHN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_CHN_SHIFT)) & ADC_SEQ_GDAT_CHN_MASK) 546 #define ADC_SEQ_GDAT_OVERRUN_MASK (0x40000000U) 547 #define ADC_SEQ_GDAT_OVERRUN_SHIFT (30U) 548 /*! OVERRUN - This bit is set if a new conversion result is loaded into the RESULT field before a 549 * previous result has been read - i.e. while the DATAVALID bit is set. This bit is cleared, along 550 * with the DATAVALID bit, whenever this register is read. This bit will contribute to an overrun 551 * interrupt/DMA trigger if the MODE bit (in SEQAA_CTRL) for the corresponding sequence is set 552 * to '0' (and if the overrun interrupt is enabled). 553 */ 554 #define ADC_SEQ_GDAT_OVERRUN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_OVERRUN_SHIFT)) & ADC_SEQ_GDAT_OVERRUN_MASK) 555 #define ADC_SEQ_GDAT_DATAVALID_MASK (0x80000000U) 556 #define ADC_SEQ_GDAT_DATAVALID_SHIFT (31U) 557 /*! DATAVALID - This bit is set to '1' at the end of each conversion when a new result is loaded 558 * into the RESULT field. It is cleared whenever this register is read. This bit will cause a 559 * conversion-complete interrupt for the corresponding sequence if the MODE bit (in SEQA_CTRL) for that 560 * sequence is set to 0 (and if the interrupt is enabled). 561 */ 562 #define ADC_SEQ_GDAT_DATAVALID(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_DATAVALID_SHIFT)) & ADC_SEQ_GDAT_DATAVALID_MASK) 563 /*! @} */ 564 565 /* The count of ADC_SEQ_GDAT */ 566 #define ADC_SEQ_GDAT_COUNT (2U) 567 568 /*! @name DAT - ADC Channel N Data register. This register contains the result of the most recent conversion completed on channel N. */ 569 /*! @{ */ 570 #define ADC_DAT_RESULT_MASK (0xFFF0U) 571 #define ADC_DAT_RESULT_SHIFT (4U) 572 /*! RESULT - This field contains the 12-bit ADC conversion result from the last conversion performed 573 * on this channel. This will be a binary fraction representing the voltage on the AD0[n] pin, 574 * as it falls within the range of VREFP to VREFN. Zero in the field indicates that the voltage on 575 * the input pin was less than, equal to, or close to that on VREFN, while 0xFFF indicates that 576 * the voltage on the input was close to, equal to, or greater than that on VREFP. 577 */ 578 #define ADC_DAT_RESULT(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_RESULT_SHIFT)) & ADC_DAT_RESULT_MASK) 579 #define ADC_DAT_THCMPRANGE_MASK (0x30000U) 580 #define ADC_DAT_THCMPRANGE_SHIFT (16U) 581 /*! THCMPRANGE - Threshold Range Comparison result. 0x0 = In Range: The last completed conversion 582 * was greater than or equal to the value programmed into the designated LOW threshold register 583 * (THRn_LOW) but less than or equal to the value programmed into the designated HIGH threshold 584 * register (THRn_HIGH). 0x1 = Below Range: The last completed conversion on was less than the value 585 * programmed into the designated LOW threshold register (THRn_LOW). 0x2 = Above Range: The last 586 * completed conversion was greater than the value programmed into the designated HIGH threshold 587 * register (THRn_HIGH). 0x3 = Reserved. 588 */ 589 #define ADC_DAT_THCMPRANGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_THCMPRANGE_SHIFT)) & ADC_DAT_THCMPRANGE_MASK) 590 #define ADC_DAT_THCMPCROSS_MASK (0xC0000U) 591 #define ADC_DAT_THCMPCROSS_SHIFT (18U) 592 /*! THCMPCROSS - Threshold Crossing Comparison result. 0x0 = No threshold Crossing detected: The 593 * most recent completed conversion on this channel had the same relationship (above or below) to 594 * the threshold value established by the designated LOW threshold register (THRn_LOW) as did the 595 * previous conversion on this channel. 0x1 = Reserved. 0x2 = Downward Threshold Crossing 596 * Detected. Indicates that a threshold crossing in the downward direction has occurred - i.e. the 597 * previous sample on this channel was above the threshold value established by the designated LOW 598 * threshold register (THRn_LOW) and the current sample is below that threshold. 0x3 = Upward 599 * Threshold Crossing Detected. Indicates that a threshold crossing in the upward direction has occurred 600 * - i.e. the previous sample on this channel was below the threshold value established by the 601 * designated LOW threshold register (THRn_LOW) and the current sample is above that threshold. 602 */ 603 #define ADC_DAT_THCMPCROSS(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_THCMPCROSS_SHIFT)) & ADC_DAT_THCMPCROSS_MASK) 604 #define ADC_DAT_CHANNEL_MASK (0x3C000000U) 605 #define ADC_DAT_CHANNEL_SHIFT (26U) 606 /*! CHANNEL - This field is hard-coded to contain the channel number that this particular register 607 * relates to (i.e. this field will contain 0b0000 for the DAT0 register, 0b0001 for the DAT1 608 * register, etc) 609 */ 610 #define ADC_DAT_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_CHANNEL_SHIFT)) & ADC_DAT_CHANNEL_MASK) 611 #define ADC_DAT_OVERRUN_MASK (0x40000000U) 612 #define ADC_DAT_OVERRUN_SHIFT (30U) 613 /*! OVERRUN - This bit will be set to a 1 if a new conversion on this channel completes and 614 * overwrites the previous contents of the RESULT field before it has been read - i.e. while the DONE bit 615 * is set. This bit is cleared, along with the DONE bit, whenever this register is read or when 616 * the data related to this channel is read from either of the global SEQn_GDAT registers. This 617 * bit (in any of the 12 registers) will cause an overrun interrupt/DMA trigger to be asserted if 618 * the overrun interrupt is enabled. While it is allowed to include the same channels in both 619 * conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in the 620 * data registers associated with any of the channels that are shared between the two sequences. Any 621 * erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled. 622 */ 623 #define ADC_DAT_OVERRUN(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_OVERRUN_SHIFT)) & ADC_DAT_OVERRUN_MASK) 624 #define ADC_DAT_DATAVALID_MASK (0x80000000U) 625 #define ADC_DAT_DATAVALID_SHIFT (31U) 626 /*! DATAVALID - This bit is set to 1 when an ADC conversion on this channel completes. This bit is 627 * cleared whenever this register is read or when the data related to this channel is read from 628 * either of the global SEQn_GDAT registers. While it is allowed to include the same channels in 629 * both conversion sequences, doing so may cause erratic behavior of the DONE and OVERRUN bits in 630 * the data registers associated with any of the channels that are shared between the two 631 * sequences. Any erratic OVERRUN behavior will also affect overrun interrupt generation, if enabled. 632 */ 633 #define ADC_DAT_DATAVALID(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_DATAVALID_SHIFT)) & ADC_DAT_DATAVALID_MASK) 634 /*! @} */ 635 636 /* The count of ADC_DAT */ 637 #define ADC_DAT_COUNT (12U) 638 639 /*! @name THR0_LOW - ADC Low Compare Threshold register 0: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 0. */ 640 /*! @{ */ 641 #define ADC_THR0_LOW_THRLOW_MASK (0xFFF0U) 642 #define ADC_THR0_LOW_THRLOW_SHIFT (4U) 643 /*! THRLOW - Low threshold value against which ADC results will be compared 644 */ 645 #define ADC_THR0_LOW_THRLOW(x) (((uint32_t)(((uint32_t)(x)) << ADC_THR0_LOW_THRLOW_SHIFT)) & ADC_THR0_LOW_THRLOW_MASK) 646 /*! @} */ 647 648 /*! @name THR1_LOW - ADC Low Compare Threshold register 1: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 1. */ 649 /*! @{ */ 650 #define ADC_THR1_LOW_THRLOW_MASK (0xFFF0U) 651 #define ADC_THR1_LOW_THRLOW_SHIFT (4U) 652 /*! THRLOW - Low threshold value against which ADC results will be compared 653 */ 654 #define ADC_THR1_LOW_THRLOW(x) (((uint32_t)(((uint32_t)(x)) << ADC_THR1_LOW_THRLOW_SHIFT)) & ADC_THR1_LOW_THRLOW_MASK) 655 /*! @} */ 656 657 /*! @name THR0_HIGH - ADC High Compare Threshold register 0: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 0. */ 658 /*! @{ */ 659 #define ADC_THR0_HIGH_THRHIGH_MASK (0xFFF0U) 660 #define ADC_THR0_HIGH_THRHIGH_SHIFT (4U) 661 /*! THRHIGH - High threshold value against which ADC results will be compared 662 */ 663 #define ADC_THR0_HIGH_THRHIGH(x) (((uint32_t)(((uint32_t)(x)) << ADC_THR0_HIGH_THRHIGH_SHIFT)) & ADC_THR0_HIGH_THRHIGH_MASK) 664 /*! @} */ 665 666 /*! @name THR1_HIGH - ADC High Compare Threshold register 1: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 1. */ 667 /*! @{ */ 668 #define ADC_THR1_HIGH_THRHIGH_MASK (0xFFF0U) 669 #define ADC_THR1_HIGH_THRHIGH_SHIFT (4U) 670 /*! THRHIGH - High threshold value against which ADC results will be compared 671 */ 672 #define ADC_THR1_HIGH_THRHIGH(x) (((uint32_t)(((uint32_t)(x)) << ADC_THR1_HIGH_THRHIGH_SHIFT)) & ADC_THR1_HIGH_THRHIGH_MASK) 673 /*! @} */ 674 675 /*! @name CHAN_THRSEL - ADC Channel-Threshold Select register. Specifies which set of threshold compare registers are to be used for each channel */ 676 /*! @{ */ 677 #define ADC_CHAN_THRSEL_CH0_THRSEL_MASK (0x1U) 678 #define ADC_CHAN_THRSEL_CH0_THRSEL_SHIFT (0U) 679 /*! CH0_THRSEL - Threshold select for channel 0. 680 * 0b0..Threshold 0. Results for this channel will be compared against the threshold levels indicated in the THR0_LOW and THR0_HIGH registers. 681 * 0b1..Threshold 1. Results for this channel will be compared against the threshold levels indicated in the THR1_LOW and THR1_HIGH registers. 682 */ 683 #define ADC_CHAN_THRSEL_CH0_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH0_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH0_THRSEL_MASK) 684 #define ADC_CHAN_THRSEL_CH1_THRSEL_MASK (0x2U) 685 #define ADC_CHAN_THRSEL_CH1_THRSEL_SHIFT (1U) 686 /*! CH1_THRSEL - Threshold select for channel 1. See description for channel 0. 687 */ 688 #define ADC_CHAN_THRSEL_CH1_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH1_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH1_THRSEL_MASK) 689 #define ADC_CHAN_THRSEL_CH2_THRSEL_MASK (0x4U) 690 #define ADC_CHAN_THRSEL_CH2_THRSEL_SHIFT (2U) 691 /*! CH2_THRSEL - Threshold select for channel 2. See description for channel 0. 692 */ 693 #define ADC_CHAN_THRSEL_CH2_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH2_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH2_THRSEL_MASK) 694 #define ADC_CHAN_THRSEL_CH3_THRSEL_MASK (0x8U) 695 #define ADC_CHAN_THRSEL_CH3_THRSEL_SHIFT (3U) 696 /*! CH3_THRSEL - Threshold select for channel 3. See description for channel 0. 697 */ 698 #define ADC_CHAN_THRSEL_CH3_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH3_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH3_THRSEL_MASK) 699 #define ADC_CHAN_THRSEL_CH4_THRSEL_MASK (0x10U) 700 #define ADC_CHAN_THRSEL_CH4_THRSEL_SHIFT (4U) 701 /*! CH4_THRSEL - Threshold select for channel 4. See description for channel 0. 702 */ 703 #define ADC_CHAN_THRSEL_CH4_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH4_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH4_THRSEL_MASK) 704 #define ADC_CHAN_THRSEL_CH5_THRSEL_MASK (0x20U) 705 #define ADC_CHAN_THRSEL_CH5_THRSEL_SHIFT (5U) 706 /*! CH5_THRSEL - Threshold select for channel 5. See description for channel 0. 707 */ 708 #define ADC_CHAN_THRSEL_CH5_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH5_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH5_THRSEL_MASK) 709 #define ADC_CHAN_THRSEL_CH6_THRSEL_MASK (0x40U) 710 #define ADC_CHAN_THRSEL_CH6_THRSEL_SHIFT (6U) 711 /*! CH6_THRSEL - Threshold select for channel 6. See description for channel 0. 712 */ 713 #define ADC_CHAN_THRSEL_CH6_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH6_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH6_THRSEL_MASK) 714 #define ADC_CHAN_THRSEL_CH7_THRSEL_MASK (0x80U) 715 #define ADC_CHAN_THRSEL_CH7_THRSEL_SHIFT (7U) 716 /*! CH7_THRSEL - Threshold select for channel 7. See description for channel 0. 717 */ 718 #define ADC_CHAN_THRSEL_CH7_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH7_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH7_THRSEL_MASK) 719 #define ADC_CHAN_THRSEL_CH8_THRSEL_MASK (0x100U) 720 #define ADC_CHAN_THRSEL_CH8_THRSEL_SHIFT (8U) 721 /*! CH8_THRSEL - Threshold select for channel 8. See description for channel 0. 722 */ 723 #define ADC_CHAN_THRSEL_CH8_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH8_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH8_THRSEL_MASK) 724 #define ADC_CHAN_THRSEL_CH9_THRSEL_MASK (0x200U) 725 #define ADC_CHAN_THRSEL_CH9_THRSEL_SHIFT (9U) 726 /*! CH9_THRSEL - Threshold select for channel 9. See description for channel 0. 727 */ 728 #define ADC_CHAN_THRSEL_CH9_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH9_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH9_THRSEL_MASK) 729 #define ADC_CHAN_THRSEL_CH10_THRSEL_MASK (0x400U) 730 #define ADC_CHAN_THRSEL_CH10_THRSEL_SHIFT (10U) 731 /*! CH10_THRSEL - Threshold select for channel 10. See description for channel 0. 732 */ 733 #define ADC_CHAN_THRSEL_CH10_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH10_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH10_THRSEL_MASK) 734 #define ADC_CHAN_THRSEL_CH11_THRSEL_MASK (0x800U) 735 #define ADC_CHAN_THRSEL_CH11_THRSEL_SHIFT (11U) 736 /*! CH11_THRSEL - Threshold select for channel 11. See description for channel 0. 737 */ 738 #define ADC_CHAN_THRSEL_CH11_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH11_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH11_THRSEL_MASK) 739 /*! @} */ 740 741 /*! @name INTEN - ADC Interrupt Enable register. This register contains enable bits that enable the sequence-A, sequence-B, threshold compare and data overrun interrupts to be generated. */ 742 /*! @{ */ 743 #define ADC_INTEN_SEQA_INTEN_MASK (0x1U) 744 #define ADC_INTEN_SEQA_INTEN_SHIFT (0U) 745 /*! SEQA_INTEN - Sequence A interrupt enable. 746 * 0b0..Disabled. The sequence A interrupt/DMA trigger is disabled. 747 * 0b1..Enabled. The sequence A interrupt/DMA trigger is enabled and will be asserted either upon completion of 748 * each individual conversion performed as part of sequence A, or upon completion of the entire A sequence of 749 * conversions, depending on the MODE bit in the SEQA_CTRL register. 750 */ 751 #define ADC_INTEN_SEQA_INTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_SEQA_INTEN_SHIFT)) & ADC_INTEN_SEQA_INTEN_MASK) 752 #define ADC_INTEN_SEQB_INTEN_MASK (0x2U) 753 #define ADC_INTEN_SEQB_INTEN_SHIFT (1U) 754 /*! SEQB_INTEN - Sequence B interrupt enable. 755 * 0b0..Disabled. The sequence B interrupt/DMA trigger is disabled. 756 * 0b1..Enabled. The sequence B interrupt/DMA trigger is enabled and will be asserted either upon completion of 757 * each individual conversion performed as part of sequence B, or upon completion of the entire B sequence of 758 * conversions, depending on the MODE bit in the SEQB_CTRL register. 759 */ 760 #define ADC_INTEN_SEQB_INTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_SEQB_INTEN_SHIFT)) & ADC_INTEN_SEQB_INTEN_MASK) 761 #define ADC_INTEN_OVR_INTEN_MASK (0x4U) 762 #define ADC_INTEN_OVR_INTEN_SHIFT (2U) 763 /*! OVR_INTEN - Overrun interrupt enable. 764 * 0b0..Disabled. The overrun interrupt is disabled. 765 * 0b1..Enabled. The overrun interrupt is enabled. Detection of an overrun condition on any of the 12 channel 766 * data registers will cause an overrun interrupt/DMA trigger. In addition, if the MODE bit for a particular 767 * sequence is 0, then an overrun in the global data register for that sequence will also cause this 768 * interrupt/DMA trigger to be asserted. 769 */ 770 #define ADC_INTEN_OVR_INTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_OVR_INTEN_SHIFT)) & ADC_INTEN_OVR_INTEN_MASK) 771 #define ADC_INTEN_ADCMPINTEN0_MASK (0x18U) 772 #define ADC_INTEN_ADCMPINTEN0_SHIFT (3U) 773 /*! ADCMPINTEN0 - Threshold comparison interrupt enable for channel 0. 774 * 0b00..Disabled. 775 * 0b01..Outside threshold. 776 * 0b10..Crossing threshold. 777 * 0b11..Reserved 778 */ 779 #define ADC_INTEN_ADCMPINTEN0(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN0_SHIFT)) & ADC_INTEN_ADCMPINTEN0_MASK) 780 #define ADC_INTEN_ADCMPINTEN1_MASK (0x60U) 781 #define ADC_INTEN_ADCMPINTEN1_SHIFT (5U) 782 /*! ADCMPINTEN1 - Channel 1 threshold comparison interrupt enable. See description for channel 0. 783 */ 784 #define ADC_INTEN_ADCMPINTEN1(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN1_SHIFT)) & ADC_INTEN_ADCMPINTEN1_MASK) 785 #define ADC_INTEN_ADCMPINTEN2_MASK (0x180U) 786 #define ADC_INTEN_ADCMPINTEN2_SHIFT (7U) 787 /*! ADCMPINTEN2 - Channel 2 threshold comparison interrupt enable. See description for channel 0. 788 */ 789 #define ADC_INTEN_ADCMPINTEN2(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN2_SHIFT)) & ADC_INTEN_ADCMPINTEN2_MASK) 790 #define ADC_INTEN_ADCMPINTEN3_MASK (0x600U) 791 #define ADC_INTEN_ADCMPINTEN3_SHIFT (9U) 792 /*! ADCMPINTEN3 - Channel 3 threshold comparison interrupt enable. See description for channel 0. 793 */ 794 #define ADC_INTEN_ADCMPINTEN3(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN3_SHIFT)) & ADC_INTEN_ADCMPINTEN3_MASK) 795 #define ADC_INTEN_ADCMPINTEN4_MASK (0x1800U) 796 #define ADC_INTEN_ADCMPINTEN4_SHIFT (11U) 797 /*! ADCMPINTEN4 - Channel 4 threshold comparison interrupt enable. See description for channel 0. 798 */ 799 #define ADC_INTEN_ADCMPINTEN4(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN4_SHIFT)) & ADC_INTEN_ADCMPINTEN4_MASK) 800 #define ADC_INTEN_ADCMPINTEN5_MASK (0x6000U) 801 #define ADC_INTEN_ADCMPINTEN5_SHIFT (13U) 802 /*! ADCMPINTEN5 - Channel 5 threshold comparison interrupt enable. See description for channel 0. 803 */ 804 #define ADC_INTEN_ADCMPINTEN5(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN5_SHIFT)) & ADC_INTEN_ADCMPINTEN5_MASK) 805 #define ADC_INTEN_ADCMPINTEN6_MASK (0x18000U) 806 #define ADC_INTEN_ADCMPINTEN6_SHIFT (15U) 807 /*! ADCMPINTEN6 - Channel 6 threshold comparison interrupt enable. See description for channel 0. 808 */ 809 #define ADC_INTEN_ADCMPINTEN6(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN6_SHIFT)) & ADC_INTEN_ADCMPINTEN6_MASK) 810 #define ADC_INTEN_ADCMPINTEN7_MASK (0x60000U) 811 #define ADC_INTEN_ADCMPINTEN7_SHIFT (17U) 812 /*! ADCMPINTEN7 - Channel 7 threshold comparison interrupt enable. See description for channel 0. 813 */ 814 #define ADC_INTEN_ADCMPINTEN7(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN7_SHIFT)) & ADC_INTEN_ADCMPINTEN7_MASK) 815 #define ADC_INTEN_ADCMPINTEN8_MASK (0x180000U) 816 #define ADC_INTEN_ADCMPINTEN8_SHIFT (19U) 817 /*! ADCMPINTEN8 - Channel 8 threshold comparison interrupt enable. See description for channel 0. 818 */ 819 #define ADC_INTEN_ADCMPINTEN8(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN8_SHIFT)) & ADC_INTEN_ADCMPINTEN8_MASK) 820 #define ADC_INTEN_ADCMPINTEN9_MASK (0x600000U) 821 #define ADC_INTEN_ADCMPINTEN9_SHIFT (21U) 822 /*! ADCMPINTEN9 - Channel 9 threshold comparison interrupt enable. See description for channel 0. 823 */ 824 #define ADC_INTEN_ADCMPINTEN9(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN9_SHIFT)) & ADC_INTEN_ADCMPINTEN9_MASK) 825 #define ADC_INTEN_ADCMPINTEN10_MASK (0x1800000U) 826 #define ADC_INTEN_ADCMPINTEN10_SHIFT (23U) 827 /*! ADCMPINTEN10 - Channel 10 threshold comparison interrupt enable. See description for channel 0. 828 */ 829 #define ADC_INTEN_ADCMPINTEN10(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN10_SHIFT)) & ADC_INTEN_ADCMPINTEN10_MASK) 830 #define ADC_INTEN_ADCMPINTEN11_MASK (0x6000000U) 831 #define ADC_INTEN_ADCMPINTEN11_SHIFT (25U) 832 /*! ADCMPINTEN11 - Channel 21 threshold comparison interrupt enable. See description for channel 0. 833 */ 834 #define ADC_INTEN_ADCMPINTEN11(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN11_SHIFT)) & ADC_INTEN_ADCMPINTEN11_MASK) 835 /*! @} */ 836 837 /*! @name FLAGS - ADC Flags register. Contains the four interrupt/DMA trigger flags and the individual component overrun and threshold-compare flags. (The overrun bits replicate information stored in the result registers). */ 838 /*! @{ */ 839 #define ADC_FLAGS_THCMP0_MASK (0x1U) 840 #define ADC_FLAGS_THCMP0_SHIFT (0U) 841 /*! THCMP0 - Threshold comparison event on Channel 0. Set to 1 upon either an out-of-range result or 842 * a threshold-crossing result if enabled to do so in the INTEN register. This bit is cleared by 843 * writing a 1. 844 */ 845 #define ADC_FLAGS_THCMP0(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP0_SHIFT)) & ADC_FLAGS_THCMP0_MASK) 846 #define ADC_FLAGS_THCMP1_MASK (0x2U) 847 #define ADC_FLAGS_THCMP1_SHIFT (1U) 848 /*! THCMP1 - Threshold comparison event on Channel 1. See description for channel 0. 849 */ 850 #define ADC_FLAGS_THCMP1(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP1_SHIFT)) & ADC_FLAGS_THCMP1_MASK) 851 #define ADC_FLAGS_THCMP2_MASK (0x4U) 852 #define ADC_FLAGS_THCMP2_SHIFT (2U) 853 /*! THCMP2 - Threshold comparison event on Channel 2. See description for channel 0. 854 */ 855 #define ADC_FLAGS_THCMP2(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP2_SHIFT)) & ADC_FLAGS_THCMP2_MASK) 856 #define ADC_FLAGS_THCMP3_MASK (0x8U) 857 #define ADC_FLAGS_THCMP3_SHIFT (3U) 858 /*! THCMP3 - Threshold comparison event on Channel 3. See description for channel 0. 859 */ 860 #define ADC_FLAGS_THCMP3(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP3_SHIFT)) & ADC_FLAGS_THCMP3_MASK) 861 #define ADC_FLAGS_THCMP4_MASK (0x10U) 862 #define ADC_FLAGS_THCMP4_SHIFT (4U) 863 /*! THCMP4 - Threshold comparison event on Channel 4. See description for channel 0. 864 */ 865 #define ADC_FLAGS_THCMP4(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP4_SHIFT)) & ADC_FLAGS_THCMP4_MASK) 866 #define ADC_FLAGS_THCMP5_MASK (0x20U) 867 #define ADC_FLAGS_THCMP5_SHIFT (5U) 868 /*! THCMP5 - Threshold comparison event on Channel 5. See description for channel 0. 869 */ 870 #define ADC_FLAGS_THCMP5(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP5_SHIFT)) & ADC_FLAGS_THCMP5_MASK) 871 #define ADC_FLAGS_THCMP6_MASK (0x40U) 872 #define ADC_FLAGS_THCMP6_SHIFT (6U) 873 /*! THCMP6 - Threshold comparison event on Channel 6. See description for channel 0. 874 */ 875 #define ADC_FLAGS_THCMP6(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP6_SHIFT)) & ADC_FLAGS_THCMP6_MASK) 876 #define ADC_FLAGS_THCMP7_MASK (0x80U) 877 #define ADC_FLAGS_THCMP7_SHIFT (7U) 878 /*! THCMP7 - Threshold comparison event on Channel 7. See description for channel 0. 879 */ 880 #define ADC_FLAGS_THCMP7(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP7_SHIFT)) & ADC_FLAGS_THCMP7_MASK) 881 #define ADC_FLAGS_THCMP8_MASK (0x100U) 882 #define ADC_FLAGS_THCMP8_SHIFT (8U) 883 /*! THCMP8 - Threshold comparison event on Channel 8. See description for channel 0. 884 */ 885 #define ADC_FLAGS_THCMP8(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP8_SHIFT)) & ADC_FLAGS_THCMP8_MASK) 886 #define ADC_FLAGS_THCMP9_MASK (0x200U) 887 #define ADC_FLAGS_THCMP9_SHIFT (9U) 888 /*! THCMP9 - Threshold comparison event on Channel 9. See description for channel 0. 889 */ 890 #define ADC_FLAGS_THCMP9(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP9_SHIFT)) & ADC_FLAGS_THCMP9_MASK) 891 #define ADC_FLAGS_THCMP10_MASK (0x400U) 892 #define ADC_FLAGS_THCMP10_SHIFT (10U) 893 /*! THCMP10 - Threshold comparison event on Channel 10. See description for channel 0. 894 */ 895 #define ADC_FLAGS_THCMP10(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP10_SHIFT)) & ADC_FLAGS_THCMP10_MASK) 896 #define ADC_FLAGS_THCMP11_MASK (0x800U) 897 #define ADC_FLAGS_THCMP11_SHIFT (11U) 898 /*! THCMP11 - Threshold comparison event on Channel 11. See description for channel 0. 899 */ 900 #define ADC_FLAGS_THCMP11(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP11_SHIFT)) & ADC_FLAGS_THCMP11_MASK) 901 #define ADC_FLAGS_OVERRUN0_MASK (0x1000U) 902 #define ADC_FLAGS_OVERRUN0_SHIFT (12U) 903 /*! OVERRUN0 - Mirrors the OVERRRUN status flag from the result register for ADC channel 0 904 */ 905 #define ADC_FLAGS_OVERRUN0(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN0_SHIFT)) & ADC_FLAGS_OVERRUN0_MASK) 906 #define ADC_FLAGS_OVERRUN1_MASK (0x2000U) 907 #define ADC_FLAGS_OVERRUN1_SHIFT (13U) 908 /*! OVERRUN1 - Mirrors the OVERRRUN status flag from the result register for ADC channel 1 909 */ 910 #define ADC_FLAGS_OVERRUN1(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN1_SHIFT)) & ADC_FLAGS_OVERRUN1_MASK) 911 #define ADC_FLAGS_OVERRUN2_MASK (0x4000U) 912 #define ADC_FLAGS_OVERRUN2_SHIFT (14U) 913 /*! OVERRUN2 - Mirrors the OVERRRUN status flag from the result register for ADC channel 2 914 */ 915 #define ADC_FLAGS_OVERRUN2(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN2_SHIFT)) & ADC_FLAGS_OVERRUN2_MASK) 916 #define ADC_FLAGS_OVERRUN3_MASK (0x8000U) 917 #define ADC_FLAGS_OVERRUN3_SHIFT (15U) 918 /*! OVERRUN3 - Mirrors the OVERRRUN status flag from the result register for ADC channel 3 919 */ 920 #define ADC_FLAGS_OVERRUN3(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN3_SHIFT)) & ADC_FLAGS_OVERRUN3_MASK) 921 #define ADC_FLAGS_OVERRUN4_MASK (0x10000U) 922 #define ADC_FLAGS_OVERRUN4_SHIFT (16U) 923 /*! OVERRUN4 - Mirrors the OVERRRUN status flag from the result register for ADC channel 4 924 */ 925 #define ADC_FLAGS_OVERRUN4(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN4_SHIFT)) & ADC_FLAGS_OVERRUN4_MASK) 926 #define ADC_FLAGS_OVERRUN5_MASK (0x20000U) 927 #define ADC_FLAGS_OVERRUN5_SHIFT (17U) 928 /*! OVERRUN5 - Mirrors the OVERRRUN status flag from the result register for ADC channel 5 929 */ 930 #define ADC_FLAGS_OVERRUN5(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN5_SHIFT)) & ADC_FLAGS_OVERRUN5_MASK) 931 #define ADC_FLAGS_OVERRUN6_MASK (0x40000U) 932 #define ADC_FLAGS_OVERRUN6_SHIFT (18U) 933 /*! OVERRUN6 - Mirrors the OVERRRUN status flag from the result register for ADC channel 6 934 */ 935 #define ADC_FLAGS_OVERRUN6(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN6_SHIFT)) & ADC_FLAGS_OVERRUN6_MASK) 936 #define ADC_FLAGS_OVERRUN7_MASK (0x80000U) 937 #define ADC_FLAGS_OVERRUN7_SHIFT (19U) 938 /*! OVERRUN7 - Mirrors the OVERRRUN status flag from the result register for ADC channel 7 939 */ 940 #define ADC_FLAGS_OVERRUN7(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN7_SHIFT)) & ADC_FLAGS_OVERRUN7_MASK) 941 #define ADC_FLAGS_OVERRUN8_MASK (0x100000U) 942 #define ADC_FLAGS_OVERRUN8_SHIFT (20U) 943 /*! OVERRUN8 - Mirrors the OVERRRUN status flag from the result register for ADC channel 8 944 */ 945 #define ADC_FLAGS_OVERRUN8(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN8_SHIFT)) & ADC_FLAGS_OVERRUN8_MASK) 946 #define ADC_FLAGS_OVERRUN9_MASK (0x200000U) 947 #define ADC_FLAGS_OVERRUN9_SHIFT (21U) 948 /*! OVERRUN9 - Mirrors the OVERRRUN status flag from the result register for ADC channel 9 949 */ 950 #define ADC_FLAGS_OVERRUN9(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN9_SHIFT)) & ADC_FLAGS_OVERRUN9_MASK) 951 #define ADC_FLAGS_OVERRUN10_MASK (0x400000U) 952 #define ADC_FLAGS_OVERRUN10_SHIFT (22U) 953 /*! OVERRUN10 - Mirrors the OVERRRUN status flag from the result register for ADC channel 10 954 */ 955 #define ADC_FLAGS_OVERRUN10(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN10_SHIFT)) & ADC_FLAGS_OVERRUN10_MASK) 956 #define ADC_FLAGS_OVERRUN11_MASK (0x800000U) 957 #define ADC_FLAGS_OVERRUN11_SHIFT (23U) 958 /*! OVERRUN11 - Mirrors the OVERRRUN status flag from the result register for ADC channel 11 959 */ 960 #define ADC_FLAGS_OVERRUN11(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN11_SHIFT)) & ADC_FLAGS_OVERRUN11_MASK) 961 #define ADC_FLAGS_SEQA_OVR_MASK (0x1000000U) 962 #define ADC_FLAGS_SEQA_OVR_SHIFT (24U) 963 /*! SEQA_OVR - Mirrors the global OVERRUN status flag in the SEQA_GDAT register 964 */ 965 #define ADC_FLAGS_SEQA_OVR(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQA_OVR_SHIFT)) & ADC_FLAGS_SEQA_OVR_MASK) 966 #define ADC_FLAGS_SEQB_OVR_MASK (0x2000000U) 967 #define ADC_FLAGS_SEQB_OVR_SHIFT (25U) 968 /*! SEQB_OVR - Mirrors the global OVERRUN status flag in the SEQB_GDAT register 969 */ 970 #define ADC_FLAGS_SEQB_OVR(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQB_OVR_SHIFT)) & ADC_FLAGS_SEQB_OVR_MASK) 971 #define ADC_FLAGS_SEQA_INT_MASK (0x10000000U) 972 #define ADC_FLAGS_SEQA_INT_SHIFT (28U) 973 /*! SEQA_INT - Sequence A interrupt/DMA trigger. If the MODE bit in the SEQA_CTRL register is 0, 974 * this flag will mirror the DATAVALID bit in the sequence A global data register (SEQA_GDAT), which 975 * is set at the end of every ADC conversion performed as part of sequence A. It will be cleared 976 * automatically when the SEQA_GDAT register is read. If the MODE bit in the SEQA_CTRL register 977 * is 1, this flag will be set upon completion of an entire A sequence. In this case it must be 978 * cleared by writing a 1 to this SEQA_INT bit. This interrupt must be enabled in the INTEN 979 * register. 980 */ 981 #define ADC_FLAGS_SEQA_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQA_INT_SHIFT)) & ADC_FLAGS_SEQA_INT_MASK) 982 #define ADC_FLAGS_SEQB_INT_MASK (0x20000000U) 983 #define ADC_FLAGS_SEQB_INT_SHIFT (29U) 984 /*! SEQB_INT - Sequence A interrupt/DMA trigger. If the MODE bit in the SEQB_CTRL register is 0, 985 * this flag will mirror the DATAVALID bit in the sequence A global data register (SEQB_GDAT), which 986 * is set at the end of every ADC conversion performed as part of sequence B. It will be cleared 987 * automatically when the SEQB_GDAT register is read. If the MODE bit in the SEQB_CTRL register 988 * is 1, this flag will be set upon completion of an entire B sequence. In this case it must be 989 * cleared by writing a 1 to this SEQB_INT bit. This interrupt must be enabled in the INTEN 990 * register. 991 */ 992 #define ADC_FLAGS_SEQB_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQB_INT_SHIFT)) & ADC_FLAGS_SEQB_INT_MASK) 993 #define ADC_FLAGS_THCMP_INT_MASK (0x40000000U) 994 #define ADC_FLAGS_THCMP_INT_SHIFT (30U) 995 /*! THCMP_INT - Threshold Comparison Interrupt. This bit will be set if any of the THCMP flags in 996 * the lower bits of this register are set to 1 (due to an enabled out-of-range or 997 * threshold-crossing event on any channel). Each type of threshold comparison interrupt on each channel must be 998 * individually enabled in the INTEN register to cause this interrupt. This bit will be cleared 999 * when all of the individual threshold flags are cleared via writing 1s to those bits. 1000 */ 1001 #define ADC_FLAGS_THCMP_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP_INT_SHIFT)) & ADC_FLAGS_THCMP_INT_MASK) 1002 #define ADC_FLAGS_OVR_INT_MASK (0x80000000U) 1003 #define ADC_FLAGS_OVR_INT_SHIFT (31U) 1004 /*! OVR_INT - Overrun Interrupt flag. Any overrun bit in any of the individual channel data 1005 * registers will cause this interrupt. In addition, if the MODE bit in either of the SEQn_CTRL registers 1006 * is 0 then the OVERRUN bit in the corresponding SEQn_GDAT register will also cause this 1007 * interrupt. This interrupt must be enabled in the INTEN register. This bit will be cleared when all 1008 * of the individual overrun bits have been cleared via reading the corresponding data registers. 1009 */ 1010 #define ADC_FLAGS_OVR_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVR_INT_SHIFT)) & ADC_FLAGS_OVR_INT_MASK) 1011 /*! @} */ 1012 1013 1014 /*! 1015 * @} 1016 */ /* end of group ADC_Register_Masks */ 1017 1018 1019 /* ADC - Peripheral instance base addresses */ 1020 /** Peripheral ADC base address */ 1021 #define ADC_BASE (0x4001C000u) 1022 /** Peripheral ADC base pointer */ 1023 #define ADC ((ADC_Type *)ADC_BASE) 1024 /** Array initializer of ADC peripheral base addresses */ 1025 #define ADC_BASE_ADDRS { ADC_BASE } 1026 /** Array initializer of ADC peripheral base pointers */ 1027 #define ADC_BASE_PTRS { ADC } 1028 /** Interrupt vectors for the ADC peripheral type */ 1029 #define ADC_SEQ_IRQS { ADC_SEQA_IRQn, ADC_SEQB_IRQn } 1030 #define ADC_THCMP_IRQS { ADC_THCMP_IRQn } 1031 1032 /*! 1033 * @} 1034 */ /* end of group ADC_Peripheral_Access_Layer */ 1035 1036 1037 /* ---------------------------------------------------------------------------- 1038 -- CAPT Peripheral Access Layer 1039 ---------------------------------------------------------------------------- */ 1040 1041 /*! 1042 * @addtogroup CAPT_Peripheral_Access_Layer CAPT Peripheral Access Layer 1043 * @{ 1044 */ 1045 1046 /** CAPT - Register Layout Typedef */ 1047 typedef struct { 1048 __IO uint32_t CTRL; /**< Configuration and control to setup the functional clock, the rules, and the pin selections and rules., offset: 0x0 */ 1049 __IO uint32_t STATUS; /**< Status from triggers and time-outs including if in a poll now. Some are used for interrupts., offset: 0x4 */ 1050 __IO uint32_t POLL_TCNT; /**< This sets up the polling counter and measurement counter rules., offset: 0x8 */ 1051 uint8_t RESERVED_0[4]; 1052 __IO uint32_t INTENSET; /**< Interrupt enable, offset: 0x10 */ 1053 __IO uint32_t INTENCLR; /**< Interrupt enable clear, offset: 0x14 */ 1054 __I uint32_t INTSTAT; /**< Interrupt status (mask of STATUS and INTEN), offset: 0x18 */ 1055 uint8_t RESERVED_1[4]; 1056 __I uint32_t TOUCH; /**< Last touch event (touch or no-touch) in context., offset: 0x20 */ 1057 uint8_t RESERVED_2[4056]; 1058 __I uint32_t ID; /**< Block ID., offset: 0xFFC */ 1059 } CAPT_Type; 1060 1061 /* ---------------------------------------------------------------------------- 1062 -- CAPT Register Masks 1063 ---------------------------------------------------------------------------- */ 1064 1065 /*! 1066 * @addtogroup CAPT_Register_Masks CAPT Register Masks 1067 * @{ 1068 */ 1069 1070 /*! @name CTRL - Configuration and control to setup the functional clock, the rules, and the pin selections and rules. */ 1071 /*! @{ */ 1072 #define CAPT_CTRL_POLLMODE_MASK (0x3U) 1073 #define CAPT_CTRL_POLLMODE_SHIFT (0U) 1074 /*! POLLMODE - Mode of operation. May only change from 0 to another value. So, if 2 or 3, must be 1075 * changed to 0 1st. Any attempt to go from non-0 to non-0 will result in 0 anyway. 1076 * 0b00..None, inactive. Poll and time counters are turned off. Writing this will reset state and stop any 1077 * collection in progress. Note: this has no effect on STATUS - those must be cleared manually. 1078 * 0b01..Poll now - forces a manual poll to be started immediately, using XPINSEL X pin(s) to activate in the 1079 * integration loop (all pins set together). Self clears - clear is not indication it is done (see STATUS). 1080 * 0b10..Normal polling using poll delay from POLL_TCNT register. This will start with the poll delay (which can be 0). 1081 * 0b11..The CAPT block will operate in low-power mode. This means it will use GPIO as input, use combination 1082 * touch measurements, and assume it is to wake the system. This will use the POLL_TCNT poll delay, and start 1083 * with the delay. 1084 */ 1085 #define CAPT_CTRL_POLLMODE(x) (((uint32_t)(((uint32_t)(x)) << CAPT_CTRL_POLLMODE_SHIFT)) & CAPT_CTRL_POLLMODE_MASK) 1086 #define CAPT_CTRL_TYPE_MASK (0xCU) 1087 #define CAPT_CTRL_TYPE_SHIFT (2U) 1088 /*! TYPE - Selects type of Touch arrangement to use and so how to handle XPINSEL bits 1089 * 0b00..Normal - all X elements are treated as normal, such as buttons and sliders. 1090 * 0b01..3x3 grid using NXP Complementary measurements. The 1st 9 Xs are assumed to be the 3x3 grid. After that 1091 * would be normal X elements. This will also allow 3x1 and 3x2 Note: Only possible if XMAX in STATUS is >=8 1092 * 0b10..5 Sensors interleaved to act as 3x3 touch area using NXP Complementary measurements. 1st 5 Xs used for 1093 * this, all remaining are treated as normal. Note that if 16 X pins allowed, the 16th will not be usable 1094 * when TYPE=1. (use TYPE=0 and select 1 smaller than 15 ( and any others from 1 smaller than 5 on up in 1095 * XPINSEL). 1096 * 0b11..9 Sensors interleaved to act as 5x5 touch area using NXP Complementary measurements. 1st 9 Xs used for 1097 * this, all remaining are treated as normal. Note: Only possible if XMAX in STATUS is >=8 1098 */ 1099 #define CAPT_CTRL_TYPE(x) (((uint32_t)(((uint32_t)(x)) << CAPT_CTRL_TYPE_SHIFT)) & CAPT_CTRL_TYPE_MASK) 1100 #define CAPT_CTRL_TRIGGER_MASK (0x10U) 1101 #define CAPT_CTRL_TRIGGER_SHIFT (4U) 1102 /*! TRIGGER - This selects what is being used as the trigger 1103 * 0b0..Uses YH GPIO. This is not normally used except in Low-power mode. But, it can be used with POLLNOW to baseline that measurement. 1104 * 0b1..ACMP (if fitted). This assumes the ACMP state is fed in asynchronously and it will sample. 1105 */ 1106 #define CAPT_CTRL_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << CAPT_CTRL_TRIGGER_SHIFT)) & CAPT_CTRL_TRIGGER_MASK) 1107 #define CAPT_CTRL_WAIT_MASK (0x20U) 1108 #define CAPT_CTRL_WAIT_SHIFT (5U) 1109 /*! WAIT - If 0, the block will continue its X based measurements, even if the TOUCH register has 1110 * not been read (and so could OVERRUN). If 1, it will wait until read when a touch (TOUCH's 1111 * ISTOUCH bit is set) before starting the next. This should not normally be needed. 1112 */ 1113 #define CAPT_CTRL_WAIT(x) (((uint32_t)(((uint32_t)(x)) << CAPT_CTRL_WAIT_SHIFT)) & CAPT_CTRL_WAIT_MASK) 1114 #define CAPT_CTRL_FDIV_MASK (0xF00U) 1115 #define CAPT_CTRL_FDIV_SHIFT (8U) 1116 /*! FDIV - Functional clock divider, or 0 if no divide. The term "clocks" in this spec then refer to 1117 * divided clocks. For a 12MHz input (e.g. FRO 12MHz), this would normally be set to generate a 1118 * 4MHz output (so, 2). For a 1MHz input, it should be 0. Note for internal use: this does not 1119 * produce a 50/50 duty cycle when non even divide. 1120 * 0b0000..No divide 1121 * 0b0001../2 1122 * 0b0010../3 1123 * 0b0011../4 1124 * 0b0100../5 1125 * 0b0101../6 1126 * 0b0111../(FDIV+1) 1127 * 0b1000../(FDIV+1) 1128 * 0b1001../(FDIV+1) 1129 * 0b1010../(FDIV+1) 1130 * 0b1011../(FDIV+1) 1131 * 0b1100../(FDIV+1) 1132 * 0b1101../(FDIV+1) 1133 * 0b1110../(FDIV+1) 1134 * 0b1111../(FDIV+1) 1135 */ 1136 #define CAPT_CTRL_FDIV(x) (((uint32_t)(((uint32_t)(x)) << CAPT_CTRL_FDIV_SHIFT)) & CAPT_CTRL_FDIV_MASK) 1137 #define CAPT_CTRL_XPINUSE_MASK (0x3000U) 1138 #define CAPT_CTRL_XPINUSE_SHIFT (12U) 1139 /*! XPINUSE - Controls how X pins selected in XPINSEL are used when not active in the current polling round. 1140 * 0b00..Normal mode. Each inactive X pin is Hi-Z. 1141 * 0b01..Ground mode. Each inactive X pin is Low 1142 */ 1143 #define CAPT_CTRL_XPINUSE(x) (((uint32_t)(((uint32_t)(x)) << CAPT_CTRL_XPINUSE_SHIFT)) & CAPT_CTRL_XPINUSE_MASK) 1144 #define CAPT_CTRL_INCHANGE_MASK (0x8000U) 1145 #define CAPT_CTRL_INCHANGE_SHIFT (15U) 1146 /*! INCHANGE - If 1, do not attempt to write to this register again. This means the last change has 1147 * not been propagated. This can only happen after changing POLLMODE and DMA. Worse case time 1148 * would be based on divided FCLK. 1149 */ 1150 #define CAPT_CTRL_INCHANGE(x) (((uint32_t)(((uint32_t)(x)) << CAPT_CTRL_INCHANGE_SHIFT)) & CAPT_CTRL_INCHANGE_MASK) 1151 #define CAPT_CTRL_XPINSEL_MASK (0xFFFF0000U) 1152 #define CAPT_CTRL_XPINSEL_SHIFT (16U) 1153 /*! XPINSEL - Selects which of the X pins are to be used within the allowed pins - see XMAX in 1154 * STATUS. The X pins are mapped via the IOCON (as are the YH and YL pins) to physical pads. So, this 1155 * only selects which are to be used as the X half of the touch element. Note: when polling, 1156 * these are "walked" (active) one at a time. When using POLLNOW, the 1 or more selected are used at 1157 * the same time. Likewise, when in low-power mode, they are used at the same time (or small 1158 * groups). X pads not selected by XPINSEL are kept at High-Z if they are connected to a pad. This 1159 * allows using controlled sets for touch detection based on context. 1160 */ 1161 #define CAPT_CTRL_XPINSEL(x) (((uint32_t)(((uint32_t)(x)) << CAPT_CTRL_XPINSEL_SHIFT)) & CAPT_CTRL_XPINSEL_MASK) 1162 /*! @} */ 1163 1164 /*! @name STATUS - Status from triggers and time-outs including if in a poll now. Some are used for interrupts. */ 1165 /*! @{ */ 1166 #define CAPT_STATUS_YESTOUCH_MASK (0x1U) 1167 #define CAPT_STATUS_YESTOUCH_SHIFT (0U) 1168 /*! YESTOUCH - Is 1 if a touch has been detected, including a wakeup from low-power mode. 1169 */ 1170 #define CAPT_STATUS_YESTOUCH(x) (((uint32_t)(((uint32_t)(x)) << CAPT_STATUS_YESTOUCH_SHIFT)) & CAPT_STATUS_YESTOUCH_MASK) 1171 #define CAPT_STATUS_NOTOUCH_MASK (0x2U) 1172 #define CAPT_STATUS_NOTOUCH_SHIFT (1U) 1173 /*! NOTOUCH - Is 1 if a no-touch has been detected (ie. completed an integration cycle and found 1174 * no-touch). This is not set when in low-power mode. 1175 */ 1176 #define CAPT_STATUS_NOTOUCH(x) (((uint32_t)(((uint32_t)(x)) << CAPT_STATUS_NOTOUCH_SHIFT)) & CAPT_STATUS_NOTOUCH_MASK) 1177 #define CAPT_STATUS_POLLDONE_MASK (0x4U) 1178 #define CAPT_STATUS_POLLDONE_SHIFT (2U) 1179 /*! POLLDONE - Is 1 if a poll or POLLNOW is complete. 1180 */ 1181 #define CAPT_STATUS_POLLDONE(x) (((uint32_t)(((uint32_t)(x)) << CAPT_STATUS_POLLDONE_SHIFT)) & CAPT_STATUS_POLLDONE_MASK) 1182 #define CAPT_STATUS_TIMEOUT_MASK (0x8U) 1183 #define CAPT_STATUS_TIMEOUT_SHIFT (3U) 1184 /*! TIMEOUT - Is 1 if an integration cycle ended with a timeout (should not happen). 1185 */ 1186 #define CAPT_STATUS_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << CAPT_STATUS_TIMEOUT_SHIFT)) & CAPT_STATUS_TIMEOUT_MASK) 1187 #define CAPT_STATUS_OVERUN_MASK (0x10U) 1188 #define CAPT_STATUS_OVERUN_SHIFT (4U) 1189 /*! OVERUN - Is 1 if new data was collected before application read out previous ISTOUCH. No-touch 1190 * (ISTOUCH==0) data will be silently overrun. Is not possible if WAIT=1. 1191 */ 1192 #define CAPT_STATUS_OVERUN(x) (((uint32_t)(((uint32_t)(x)) << CAPT_STATUS_OVERUN_SHIFT)) & CAPT_STATUS_OVERUN_MASK) 1193 #define CAPT_STATUS_BUSY_MASK (0x100U) 1194 #define CAPT_STATUS_BUSY_SHIFT (8U) 1195 /*! BUSY - In a poll now. 1196 */ 1197 #define CAPT_STATUS_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CAPT_STATUS_BUSY_SHIFT)) & CAPT_STATUS_BUSY_MASK) 1198 #define CAPT_STATUS_XMAX_MASK (0xF0000U) 1199 #define CAPT_STATUS_XMAX_SHIFT (16U) 1200 /*! XMAX - Indicates the maximum number of X pins allowed 0-relative. So, 15 means there are pins 0 1201 * to 15, or 16 total X pins. INTERNAL note: this may be setup to be written by ROM boot. 1202 */ 1203 #define CAPT_STATUS_XMAX(x) (((uint32_t)(((uint32_t)(x)) << CAPT_STATUS_XMAX_SHIFT)) & CAPT_STATUS_XMAX_MASK) 1204 /*! @} */ 1205 1206 /*! @name POLL_TCNT - This sets up the polling counter and measurement counter rules. */ 1207 /*! @{ */ 1208 #define CAPT_POLL_TCNT_TCNT_MASK (0xFFFU) 1209 #define CAPT_POLL_TCNT_TCNT_SHIFT (0U) 1210 /*! TCNT - Sets the threshold between touch and no-touch count. If not used, then the block will 1211 * treat all events as touch or no-touch, depending whether at max or min. This is in terms of 1212 * divided FCLK. If the comparator triggers it is no-touch; if bigger than TCNT counts, it is a touch 1213 * event. 1214 */ 1215 #define CAPT_POLL_TCNT_TCNT(x) (((uint32_t)(((uint32_t)(x)) << CAPT_POLL_TCNT_TCNT_SHIFT)) & CAPT_POLL_TCNT_TCNT_MASK) 1216 #define CAPT_POLL_TCNT_TOUT_MASK (0xF000U) 1217 #define CAPT_POLL_TCNT_TOUT_SHIFT (12U) 1218 /*! TOUT - Time-out count expressed as 1 is smaller than TOUT, allowing for up to 12 bits. Must be 1219 * less than 13. So, for example, 1 is smaller than 12=4096 counts; if TOUT=12, then if 4096 1220 * counts occur without a trigger, it is a time-out. This should be set to be large enough above TCNT 1221 * to prevent timeout invalidly. 1222 */ 1223 #define CAPT_POLL_TCNT_TOUT(x) (((uint32_t)(((uint32_t)(x)) << CAPT_POLL_TCNT_TOUT_SHIFT)) & CAPT_POLL_TCNT_TOUT_MASK) 1224 #define CAPT_POLL_TCNT_POLL_MASK (0xFF0000U) 1225 #define CAPT_POLL_TCNT_POLL_SHIFT (16U) 1226 /*! POLL - Poll counter in (internal) 12-bit counter wraparounds (loosely 1msec), so related to 1227 * divided FCLK. This expresses time delay between measurement cycles (ie. after one set of X 1228 * measurements, time before starting next). This count is used to delay before the next set of 1229 * measurements. Measuring too often wastes power and does not add value since movement of fingers is 1230 * relatively slow. For low power mode, this must allow for the clock being used (e.g. a 1MHz osc) 1231 * so 12 bit count will be potentially much longer. That means, lowering the count to get the 1232 * reasonable delay period. 1233 */ 1234 #define CAPT_POLL_TCNT_POLL(x) (((uint32_t)(((uint32_t)(x)) << CAPT_POLL_TCNT_POLL_SHIFT)) & CAPT_POLL_TCNT_POLL_MASK) 1235 #define CAPT_POLL_TCNT_MDELAY_MASK (0x3000000U) 1236 #define CAPT_POLL_TCNT_MDELAY_SHIFT (24U) 1237 /*! MDELAY - If not 0, this selects the number of divided FCLKs to wait after entry of measurement 1238 * mode before deciding if has triggered. This gives the ACMP time to react to the transferred 1239 * charge. It is used as 1+(1 smaller than MDELAY), , so between 2 and 8 ticks of the divided FCLK 1240 * added during the measurement. 1241 */ 1242 #define CAPT_POLL_TCNT_MDELAY(x) (((uint32_t)(((uint32_t)(x)) << CAPT_POLL_TCNT_MDELAY_SHIFT)) & CAPT_POLL_TCNT_MDELAY_MASK) 1243 #define CAPT_POLL_TCNT_RDELAY_MASK (0xC000000U) 1244 #define CAPT_POLL_TCNT_RDELAY_SHIFT (26U) 1245 /*! RDELAY - If not 0, this is the number of divided FCLKs to hold in Step 0 'Reset' state (draining 1246 * capacitance). It is used as (1 is smaller than RDELAY), so between 2 and 8 ticks of the 1247 * divided FCLK added to the 'Reset' state. 1248 */ 1249 #define CAPT_POLL_TCNT_RDELAY(x) (((uint32_t)(((uint32_t)(x)) << CAPT_POLL_TCNT_RDELAY_SHIFT)) & CAPT_POLL_TCNT_RDELAY_MASK) 1250 #define CAPT_POLL_TCNT_TCHLOW_ER_MASK (0x80000000U) 1251 #define CAPT_POLL_TCNT_TCHLOW_ER_SHIFT (31U) 1252 /*! TCHLOW_ER - Specifies whether a touched sensor triggers at a lower or higher count than an 1253 * untouched sensor. TOUCHLOWER = 0: Trigger at count > TCNT is a touch. Trigger at count lower than 1254 * or equal to TCNT is a no-touch. TOUCHLOWER = 1: Trigger at count lower than or equal to TCNT is 1255 * a touch. Trigger at count > TCNT is a no-touch. 1256 */ 1257 #define CAPT_POLL_TCNT_TCHLOW_ER(x) (((uint32_t)(((uint32_t)(x)) << CAPT_POLL_TCNT_TCHLOW_ER_SHIFT)) & CAPT_POLL_TCNT_TCHLOW_ER_MASK) 1258 /*! @} */ 1259 1260 /*! @name INTENSET - Interrupt enable */ 1261 /*! @{ */ 1262 #define CAPT_INTENSET_YESTOUCH_MASK (0x1U) 1263 #define CAPT_INTENSET_YESTOUCH_SHIFT (0U) 1264 /*! YESTOUCH - Is 1 if a touch detected should interrupt. This includes wake from low-power mode. 1265 */ 1266 #define CAPT_INTENSET_YESTOUCH(x) (((uint32_t)(((uint32_t)(x)) << CAPT_INTENSET_YESTOUCH_SHIFT)) & CAPT_INTENSET_YESTOUCH_MASK) 1267 #define CAPT_INTENSET_NOTOUCH_MASK (0x2U) 1268 #define CAPT_INTENSET_NOTOUCH_SHIFT (1U) 1269 /*! NOTOUCH - Is 1 if a no-touch detected should interrupt 1270 */ 1271 #define CAPT_INTENSET_NOTOUCH(x) (((uint32_t)(((uint32_t)(x)) << CAPT_INTENSET_NOTOUCH_SHIFT)) & CAPT_INTENSET_NOTOUCH_MASK) 1272 #define CAPT_INTENSET_POLLDONE_MASK (0x4U) 1273 #define CAPT_INTENSET_POLLDONE_SHIFT (2U) 1274 /*! POLLDONE - Is 1 if a poll or POLLNOW completing should interrupt 1275 */ 1276 #define CAPT_INTENSET_POLLDONE(x) (((uint32_t)(((uint32_t)(x)) << CAPT_INTENSET_POLLDONE_SHIFT)) & CAPT_INTENSET_POLLDONE_MASK) 1277 #define CAPT_INTENSET_TIMEOUT_MASK (0x8U) 1278 #define CAPT_INTENSET_TIMEOUT_SHIFT (3U) 1279 /*! TIMEOUT - Is 1 if an integration cycle ending with timeout should interrupt 1280 */ 1281 #define CAPT_INTENSET_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << CAPT_INTENSET_TIMEOUT_SHIFT)) & CAPT_INTENSET_TIMEOUT_MASK) 1282 #define CAPT_INTENSET_OVERUN_MASK (0x10U) 1283 #define CAPT_INTENSET_OVERUN_SHIFT (4U) 1284 /*! OVERUN - Is 1 if an overrun should interrupt. 1285 */ 1286 #define CAPT_INTENSET_OVERUN(x) (((uint32_t)(((uint32_t)(x)) << CAPT_INTENSET_OVERUN_SHIFT)) & CAPT_INTENSET_OVERUN_MASK) 1287 /*! @} */ 1288 1289 /*! @name INTENCLR - Interrupt enable clear */ 1290 /*! @{ */ 1291 #define CAPT_INTENCLR_YESTOUCH_MASK (0x1U) 1292 #define CAPT_INTENCLR_YESTOUCH_SHIFT (0U) 1293 /*! YESTOUCH - clear the touch interrupt 1294 */ 1295 #define CAPT_INTENCLR_YESTOUCH(x) (((uint32_t)(((uint32_t)(x)) << CAPT_INTENCLR_YESTOUCH_SHIFT)) & CAPT_INTENCLR_YESTOUCH_MASK) 1296 #define CAPT_INTENCLR_NOTOUCH_MASK (0x2U) 1297 #define CAPT_INTENCLR_NOTOUCH_SHIFT (1U) 1298 /*! NOTOUCH - clear the no-touch interrupt 1299 */ 1300 #define CAPT_INTENCLR_NOTOUCH(x) (((uint32_t)(((uint32_t)(x)) << CAPT_INTENCLR_NOTOUCH_SHIFT)) & CAPT_INTENCLR_NOTOUCH_MASK) 1301 #define CAPT_INTENCLR_POLLDONE_MASK (0x4U) 1302 #define CAPT_INTENCLR_POLLDONE_SHIFT (2U) 1303 /*! POLLDONE - clear the poll or POLLNOW completing interrupt 1304 */ 1305 #define CAPT_INTENCLR_POLLDONE(x) (((uint32_t)(((uint32_t)(x)) << CAPT_INTENCLR_POLLDONE_SHIFT)) & CAPT_INTENCLR_POLLDONE_MASK) 1306 #define CAPT_INTENCLR_TIMEOUT_MASK (0x8U) 1307 #define CAPT_INTENCLR_TIMEOUT_SHIFT (3U) 1308 /*! TIMEOUT - clear the timeout interrupt 1309 */ 1310 #define CAPT_INTENCLR_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << CAPT_INTENCLR_TIMEOUT_SHIFT)) & CAPT_INTENCLR_TIMEOUT_MASK) 1311 #define CAPT_INTENCLR_OVERUN_MASK (0x10U) 1312 #define CAPT_INTENCLR_OVERUN_SHIFT (4U) 1313 /*! OVERUN - clear the overrun interrupt 1314 */ 1315 #define CAPT_INTENCLR_OVERUN(x) (((uint32_t)(((uint32_t)(x)) << CAPT_INTENCLR_OVERUN_SHIFT)) & CAPT_INTENCLR_OVERUN_MASK) 1316 /*! @} */ 1317 1318 /*! @name INTSTAT - Interrupt status (mask of STATUS and INTEN) */ 1319 /*! @{ */ 1320 #define CAPT_INTSTAT_YESTOUCH_MASK (0x1U) 1321 #define CAPT_INTSTAT_YESTOUCH_SHIFT (0U) 1322 /*! YESTOUCH - the status of touch interrrupt 1323 */ 1324 #define CAPT_INTSTAT_YESTOUCH(x) (((uint32_t)(((uint32_t)(x)) << CAPT_INTSTAT_YESTOUCH_SHIFT)) & CAPT_INTSTAT_YESTOUCH_MASK) 1325 #define CAPT_INTSTAT_NOTOUCH_MASK (0x2U) 1326 #define CAPT_INTSTAT_NOTOUCH_SHIFT (1U) 1327 /*! NOTOUCH - the status of no-touch interrrupt 1328 */ 1329 #define CAPT_INTSTAT_NOTOUCH(x) (((uint32_t)(((uint32_t)(x)) << CAPT_INTSTAT_NOTOUCH_SHIFT)) & CAPT_INTSTAT_NOTOUCH_MASK) 1330 #define CAPT_INTSTAT_POLLDONE_MASK (0x4U) 1331 #define CAPT_INTSTAT_POLLDONE_SHIFT (2U) 1332 /*! POLLDONE - the status of poll or pollnow completing interrupt 1333 */ 1334 #define CAPT_INTSTAT_POLLDONE(x) (((uint32_t)(((uint32_t)(x)) << CAPT_INTSTAT_POLLDONE_SHIFT)) & CAPT_INTSTAT_POLLDONE_MASK) 1335 #define CAPT_INTSTAT_TIMEOUT_MASK (0x8U) 1336 #define CAPT_INTSTAT_TIMEOUT_SHIFT (3U) 1337 /*! TIMEOUT - the status of timeout interrupt 1338 */ 1339 #define CAPT_INTSTAT_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << CAPT_INTSTAT_TIMEOUT_SHIFT)) & CAPT_INTSTAT_TIMEOUT_MASK) 1340 #define CAPT_INTSTAT_OVERUN_MASK (0x10U) 1341 #define CAPT_INTSTAT_OVERUN_SHIFT (4U) 1342 /*! OVERUN - the status of overrun interrupt 1343 */ 1344 #define CAPT_INTSTAT_OVERUN(x) (((uint32_t)(((uint32_t)(x)) << CAPT_INTSTAT_OVERUN_SHIFT)) & CAPT_INTSTAT_OVERUN_MASK) 1345 /*! @} */ 1346 1347 /*! @name TOUCH - Last touch event (touch or no-touch) in context. */ 1348 /*! @{ */ 1349 #define CAPT_TOUCH_COUNT_MASK (0xFFFU) 1350 #define CAPT_TOUCH_COUNT_SHIFT (0U) 1351 /*! COUNT - Count value reached at trigger. If timeout, will be (1 bigger than TOUT)-1; e.g. if TOUT=12, then 0xFFF. 1352 */ 1353 #define CAPT_TOUCH_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CAPT_TOUCH_COUNT_SHIFT)) & CAPT_TOUCH_COUNT_MASK) 1354 #define CAPT_TOUCH_XVAL_MASK (0xF000U) 1355 #define CAPT_TOUCH_XVAL_SHIFT (12U) 1356 /*! XVAL - Is the X that triggered this, or lowest X if more than one. 1357 */ 1358 #define CAPT_TOUCH_XVAL(x) (((uint32_t)(((uint32_t)(x)) << CAPT_TOUCH_XVAL_SHIFT)) & CAPT_TOUCH_XVAL_MASK) 1359 #define CAPT_TOUCH_ISTOUCH_MASK (0x10000U) 1360 #define CAPT_TOUCH_ISTOUCH_SHIFT (16U) 1361 /*! ISTOUCH - 1 if is Touch (by count) or 0 if is no-touch. 1362 */ 1363 #define CAPT_TOUCH_ISTOUCH(x) (((uint32_t)(((uint32_t)(x)) << CAPT_TOUCH_ISTOUCH_SHIFT)) & CAPT_TOUCH_ISTOUCH_MASK) 1364 #define CAPT_TOUCH_ISTO_MASK (0x20000U) 1365 #define CAPT_TOUCH_ISTO_SHIFT (17U) 1366 /*! ISTO - 1 if is Timeout. 1367 */ 1368 #define CAPT_TOUCH_ISTO(x) (((uint32_t)(((uint32_t)(x)) << CAPT_TOUCH_ISTO_SHIFT)) & CAPT_TOUCH_ISTO_MASK) 1369 #define CAPT_TOUCH_SEQ_MASK (0xF00000U) 1370 #define CAPT_TOUCH_SEQ_SHIFT (20U) 1371 /*! SEQ - Sequence number - rolling counter of polls. Changes after all selected Xs per poll (so, 0 1372 * for 1st set of Xs, then 1 for next set, etc). 1373 */ 1374 #define CAPT_TOUCH_SEQ(x) (((uint32_t)(((uint32_t)(x)) << CAPT_TOUCH_SEQ_SHIFT)) & CAPT_TOUCH_SEQ_MASK) 1375 #define CAPT_TOUCH_CHANGE_MASK (0x80000000U) 1376 #define CAPT_TOUCH_CHANGE_SHIFT (31U) 1377 /*! CHANGE - If 1, the rest of the register is 0 because the data is changing. This will only happen 1378 * for 1 cycle and would never happen if using interrupts to read, unless took so long as to 1379 * overrun. 1380 */ 1381 #define CAPT_TOUCH_CHANGE(x) (((uint32_t)(((uint32_t)(x)) << CAPT_TOUCH_CHANGE_SHIFT)) & CAPT_TOUCH_CHANGE_MASK) 1382 /*! @} */ 1383 1384 /*! @name ID - Block ID. */ 1385 /*! @{ */ 1386 #define CAPT_ID_APERTURE_MASK (0xFFU) 1387 #define CAPT_ID_APERTURE_SHIFT (0U) 1388 /*! APERTURE - Aperture: encoded as (aperture size/4K) -1, so 0x00 is a 4 K aperture. 1389 */ 1390 #define CAPT_ID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << CAPT_ID_APERTURE_SHIFT)) & CAPT_ID_APERTURE_MASK) 1391 #define CAPT_ID_MINOR_REV_MASK (0xF00U) 1392 #define CAPT_ID_MINOR_REV_SHIFT (8U) 1393 /*! MINOR_REV - Minor revision of module implementation, starting at 0. Software compatibility is expected between minor revisions. 1394 */ 1395 #define CAPT_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << CAPT_ID_MINOR_REV_SHIFT)) & CAPT_ID_MINOR_REV_MASK) 1396 #define CAPT_ID_MAJOR_REV_MASK (0xF000U) 1397 #define CAPT_ID_MAJOR_REV_SHIFT (12U) 1398 /*! MAJOR_REV - Major revision of module implementation, starting at 0. There may not be software compatibility between major revisions. 1399 */ 1400 #define CAPT_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << CAPT_ID_MAJOR_REV_SHIFT)) & CAPT_ID_MAJOR_REV_MASK) 1401 #define CAPT_ID_ID_MASK (0xFFFF0000U) 1402 #define CAPT_ID_ID_SHIFT (16U) 1403 /*! ID - Unique module identifier for this IP block. 1404 */ 1405 #define CAPT_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << CAPT_ID_ID_SHIFT)) & CAPT_ID_ID_MASK) 1406 /*! @} */ 1407 1408 1409 /*! 1410 * @} 1411 */ /* end of group CAPT_Register_Masks */ 1412 1413 1414 /* CAPT - Peripheral instance base addresses */ 1415 /** Peripheral CAPT base address */ 1416 #define CAPT_BASE (0x40060000u) 1417 /** Peripheral CAPT base pointer */ 1418 #define CAPT ((CAPT_Type *)CAPT_BASE) 1419 /** Array initializer of CAPT peripheral base addresses */ 1420 #define CAPT_BASE_ADDRS { CAPT_BASE } 1421 /** Array initializer of CAPT peripheral base pointers */ 1422 #define CAPT_BASE_PTRS { CAPT } 1423 /** Interrupt vectors for the CAPT peripheral type */ 1424 #define CAPT_IRQS { CMP_CAPT_IRQn } 1425 1426 /*! 1427 * @} 1428 */ /* end of group CAPT_Peripheral_Access_Layer */ 1429 1430 1431 /* ---------------------------------------------------------------------------- 1432 -- CRC Peripheral Access Layer 1433 ---------------------------------------------------------------------------- */ 1434 1435 /*! 1436 * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer 1437 * @{ 1438 */ 1439 1440 /** CRC - Register Layout Typedef */ 1441 typedef struct { 1442 __IO uint32_t MODE; /**< CRC mode register, offset: 0x0 */ 1443 __IO uint32_t SEED; /**< CRC seed register, offset: 0x4 */ 1444 union { /* offset: 0x8 */ 1445 __I uint32_t SUM; /**< CRC checksum register, offset: 0x8 */ 1446 __O uint32_t WR_DATA; /**< CRC data register, offset: 0x8 */ 1447 }; 1448 } CRC_Type; 1449 1450 /* ---------------------------------------------------------------------------- 1451 -- CRC Register Masks 1452 ---------------------------------------------------------------------------- */ 1453 1454 /*! 1455 * @addtogroup CRC_Register_Masks CRC Register Masks 1456 * @{ 1457 */ 1458 1459 /*! @name MODE - CRC mode register */ 1460 /*! @{ */ 1461 #define CRC_MODE_CRC_POLY_MASK (0x3U) 1462 #define CRC_MODE_CRC_POLY_SHIFT (0U) 1463 /*! CRC_POLY - CRC polynomial: 1X = CRC-32 polynomial 01 = CRC-16 polynomial 00 = CRC-CCITT polynomial 1464 */ 1465 #define CRC_MODE_CRC_POLY(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CRC_POLY_SHIFT)) & CRC_MODE_CRC_POLY_MASK) 1466 #define CRC_MODE_BIT_RVS_WR_MASK (0x4U) 1467 #define CRC_MODE_BIT_RVS_WR_SHIFT (2U) 1468 /*! BIT_RVS_WR - Data bit order: 1 = Bit order reverse for CRC_WR_DATA (per byte) 0 = No bit order reverse for CRC_WR_DATA (per byte) 1469 */ 1470 #define CRC_MODE_BIT_RVS_WR(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_BIT_RVS_WR_SHIFT)) & CRC_MODE_BIT_RVS_WR_MASK) 1471 #define CRC_MODE_CMPL_WR_MASK (0x8U) 1472 #define CRC_MODE_CMPL_WR_SHIFT (3U) 1473 /*! CMPL_WR - Data complement: 1 = 1's complement for CRC_WR_DATA 0 = No 1's complement for CRC_WR_DATA 1474 */ 1475 #define CRC_MODE_CMPL_WR(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_WR_SHIFT)) & CRC_MODE_CMPL_WR_MASK) 1476 #define CRC_MODE_BIT_RVS_SUM_MASK (0x10U) 1477 #define CRC_MODE_BIT_RVS_SUM_SHIFT (4U) 1478 /*! BIT_RVS_SUM - CRC sum bit order: 1 = Bit order reverse for CRC_SUM 0 = No bit order reverse for CRC_SUM 1479 */ 1480 #define CRC_MODE_BIT_RVS_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_BIT_RVS_SUM_SHIFT)) & CRC_MODE_BIT_RVS_SUM_MASK) 1481 #define CRC_MODE_CMPL_SUM_MASK (0x20U) 1482 #define CRC_MODE_CMPL_SUM_SHIFT (5U) 1483 /*! CMPL_SUM - CRC sum complement: 1 = 1's complement for CRC_SUM 0 = No 1's complement for CRC_SUM 1484 */ 1485 #define CRC_MODE_CMPL_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_SUM_SHIFT)) & CRC_MODE_CMPL_SUM_MASK) 1486 /*! @} */ 1487 1488 /*! @name SEED - CRC seed register */ 1489 /*! @{ */ 1490 #define CRC_SEED_CRC_SEED_MASK (0xFFFFFFFFU) 1491 #define CRC_SEED_CRC_SEED_SHIFT (0U) 1492 /*! CRC_SEED - A write access to this register will load CRC seed value to CRC_SUM register with 1493 * selected bit order and 1's complement pre-processes. A write access to this register will 1494 * overrule the CRC calculation in progresses. 1495 */ 1496 #define CRC_SEED_CRC_SEED(x) (((uint32_t)(((uint32_t)(x)) << CRC_SEED_CRC_SEED_SHIFT)) & CRC_SEED_CRC_SEED_MASK) 1497 /*! @} */ 1498 1499 /*! @name SUM - CRC checksum register */ 1500 /*! @{ */ 1501 #define CRC_SUM_CRC_SUM_MASK (0xFFFFFFFFU) 1502 #define CRC_SUM_CRC_SUM_SHIFT (0U) 1503 /*! CRC_SUM - The most recent CRC sum can be read through this register with selected bit order and 1's complement post-processes. 1504 */ 1505 #define CRC_SUM_CRC_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_SUM_CRC_SUM_SHIFT)) & CRC_SUM_CRC_SUM_MASK) 1506 /*! @} */ 1507 1508 /*! @name WR_DATA - CRC data register */ 1509 /*! @{ */ 1510 #define CRC_WR_DATA_CRC_WR_DATA_MASK (0xFFFFFFFFU) 1511 #define CRC_WR_DATA_CRC_WR_DATA_SHIFT (0U) 1512 /*! CRC_WR_DATA - Data written to this register will be taken to perform CRC calculation with 1513 * selected bit order and 1's complement pre-process. Any write size 8, 16 or 32-bit are allowed and 1514 * accept back-to-back transactions. 1515 */ 1516 #define CRC_WR_DATA_CRC_WR_DATA(x) (((uint32_t)(((uint32_t)(x)) << CRC_WR_DATA_CRC_WR_DATA_SHIFT)) & CRC_WR_DATA_CRC_WR_DATA_MASK) 1517 /*! @} */ 1518 1519 1520 /*! 1521 * @} 1522 */ /* end of group CRC_Register_Masks */ 1523 1524 1525 /* CRC - Peripheral instance base addresses */ 1526 /** Peripheral CRC base address */ 1527 #define CRC_BASE (0x50000000u) 1528 /** Peripheral CRC base pointer */ 1529 #define CRC ((CRC_Type *)CRC_BASE) 1530 /** Array initializer of CRC peripheral base addresses */ 1531 #define CRC_BASE_ADDRS { CRC_BASE } 1532 /** Array initializer of CRC peripheral base pointers */ 1533 #define CRC_BASE_PTRS { CRC } 1534 1535 /*! 1536 * @} 1537 */ /* end of group CRC_Peripheral_Access_Layer */ 1538 1539 1540 /* ---------------------------------------------------------------------------- 1541 -- CTIMER Peripheral Access Layer 1542 ---------------------------------------------------------------------------- */ 1543 1544 /*! 1545 * @addtogroup CTIMER_Peripheral_Access_Layer CTIMER Peripheral Access Layer 1546 * @{ 1547 */ 1548 1549 /** CTIMER - Register Layout Typedef */ 1550 typedef struct { 1551 __IO uint32_t IR; /**< Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending., offset: 0x0 */ 1552 __IO uint32_t TCR; /**< Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR., offset: 0x4 */ 1553 __IO uint32_t TC; /**< Timer Counter. The 32 bit TC is incremented every PR+1 cycles of the APB bus clock. The TC is controlled through the TCR., offset: 0x8 */ 1554 __IO uint32_t PR; /**< Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC., offset: 0xC */ 1555 __IO uint32_t PC; /**< Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface., offset: 0x10 */ 1556 __IO uint32_t MCR; /**< Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs., offset: 0x14 */ 1557 __IO uint32_t MR[4]; /**< Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC., array offset: 0x18, array step: 0x4 */ 1558 __IO uint32_t CCR; /**< Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place., offset: 0x28 */ 1559 __I uint32_t CR[3]; /**< Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input., array offset: 0x2C, array step: 0x4 */ 1560 uint8_t RESERVED_0[4]; 1561 __IO uint32_t EMR; /**< External Match Register. The EMR controls the match function and the external match pins., offset: 0x3C */ 1562 uint8_t RESERVED_1[48]; 1563 __IO uint32_t CTCR; /**< Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting., offset: 0x70 */ 1564 __IO uint32_t PWMC; /**< PWM Control Register. The PWMCON enables PWM mode for the external match pins., offset: 0x74 */ 1565 __IO uint32_t MSR[4]; /**< Match Shadow Register . If enabled, the Match Register will be automatically reloaded with the contents of this register whenever the TC is reset to zero., array offset: 0x78, array step: 0x4 */ 1566 } CTIMER_Type; 1567 1568 /* ---------------------------------------------------------------------------- 1569 -- CTIMER Register Masks 1570 ---------------------------------------------------------------------------- */ 1571 1572 /*! 1573 * @addtogroup CTIMER_Register_Masks CTIMER Register Masks 1574 * @{ 1575 */ 1576 1577 /*! @name IR - Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */ 1578 /*! @{ */ 1579 #define CTIMER_IR_MR0INT_MASK (0x1U) 1580 #define CTIMER_IR_MR0INT_SHIFT (0U) 1581 /*! MR0INT - Interrupt flag for match channel 0. 1582 */ 1583 #define CTIMER_IR_MR0INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR0INT_SHIFT)) & CTIMER_IR_MR0INT_MASK) 1584 #define CTIMER_IR_MR1INT_MASK (0x2U) 1585 #define CTIMER_IR_MR1INT_SHIFT (1U) 1586 /*! MR1INT - Interrupt flag for match channel 1. 1587 */ 1588 #define CTIMER_IR_MR1INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR1INT_SHIFT)) & CTIMER_IR_MR1INT_MASK) 1589 #define CTIMER_IR_MR2INT_MASK (0x4U) 1590 #define CTIMER_IR_MR2INT_SHIFT (2U) 1591 /*! MR2INT - Interrupt flag for match channel 2. 1592 */ 1593 #define CTIMER_IR_MR2INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR2INT_SHIFT)) & CTIMER_IR_MR2INT_MASK) 1594 #define CTIMER_IR_MR3INT_MASK (0x8U) 1595 #define CTIMER_IR_MR3INT_SHIFT (3U) 1596 /*! MR3INT - Interrupt flag for match channel 3. 1597 */ 1598 #define CTIMER_IR_MR3INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR3INT_SHIFT)) & CTIMER_IR_MR3INT_MASK) 1599 #define CTIMER_IR_CR0INT_MASK (0x10U) 1600 #define CTIMER_IR_CR0INT_SHIFT (4U) 1601 /*! CR0INT - Interrupt flag for capture channel 0 event. 1602 */ 1603 #define CTIMER_IR_CR0INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR0INT_SHIFT)) & CTIMER_IR_CR0INT_MASK) 1604 #define CTIMER_IR_CR1INT_MASK (0x20U) 1605 #define CTIMER_IR_CR1INT_SHIFT (5U) 1606 /*! CR1INT - Interrupt flag for capture channel 1 event. 1607 */ 1608 #define CTIMER_IR_CR1INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR1INT_SHIFT)) & CTIMER_IR_CR1INT_MASK) 1609 #define CTIMER_IR_CR2INT_MASK (0x40U) 1610 #define CTIMER_IR_CR2INT_SHIFT (6U) 1611 /*! CR2INT - Interrupt flag for capture channel 2 event. 1612 */ 1613 #define CTIMER_IR_CR2INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR2INT_SHIFT)) & CTIMER_IR_CR2INT_MASK) 1614 /*! @} */ 1615 1616 /*! @name TCR - Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */ 1617 /*! @{ */ 1618 #define CTIMER_TCR_CEN_MASK (0x1U) 1619 #define CTIMER_TCR_CEN_SHIFT (0U) 1620 /*! CEN - Counter enable. 1621 * 0b0..Disabled.The counters are disabled. 1622 * 0b1..Enabled. The Timer Counter and Prescale Counter are enabled. 1623 */ 1624 #define CTIMER_TCR_CEN(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CEN_SHIFT)) & CTIMER_TCR_CEN_MASK) 1625 #define CTIMER_TCR_CRST_MASK (0x2U) 1626 #define CTIMER_TCR_CRST_SHIFT (1U) 1627 /*! CRST - Counter reset. 1628 * 0b0..Disabled. Do nothing. 1629 * 0b1..Enabled. The Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of 1630 * the APB bus clock. The counters remain reset until TCR[1] is returned to zero. 1631 */ 1632 #define CTIMER_TCR_CRST(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CRST_SHIFT)) & CTIMER_TCR_CRST_MASK) 1633 /*! @} */ 1634 1635 /*! @name TC - Timer Counter. The 32 bit TC is incremented every PR+1 cycles of the APB bus clock. The TC is controlled through the TCR. */ 1636 /*! @{ */ 1637 #define CTIMER_TC_TCVAL_MASK (0xFFFFFFFFU) 1638 #define CTIMER_TC_TCVAL_SHIFT (0U) 1639 /*! TCVAL - Timer counter value. 1640 */ 1641 #define CTIMER_TC_TCVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TC_TCVAL_SHIFT)) & CTIMER_TC_TCVAL_MASK) 1642 /*! @} */ 1643 1644 /*! @name PR - Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC. */ 1645 /*! @{ */ 1646 #define CTIMER_PR_PRVAL_MASK (0xFFFFFFFFU) 1647 #define CTIMER_PR_PRVAL_SHIFT (0U) 1648 /*! PRVAL - Prescale counter value. 1649 */ 1650 #define CTIMER_PR_PRVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PR_PRVAL_SHIFT)) & CTIMER_PR_PRVAL_MASK) 1651 /*! @} */ 1652 1653 /*! @name PC - Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface. */ 1654 /*! @{ */ 1655 #define CTIMER_PC_PCVAL_MASK (0xFFFFFFFFU) 1656 #define CTIMER_PC_PCVAL_SHIFT (0U) 1657 /*! PCVAL - Prescale counter value. 1658 */ 1659 #define CTIMER_PC_PCVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PC_PCVAL_SHIFT)) & CTIMER_PC_PCVAL_MASK) 1660 /*! @} */ 1661 1662 /*! @name MCR - Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs. */ 1663 /*! @{ */ 1664 #define CTIMER_MCR_MR0I_MASK (0x1U) 1665 #define CTIMER_MCR_MR0I_SHIFT (0U) 1666 /*! MR0I - Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC. 0 = disabled. 1 = enabled. 1667 */ 1668 #define CTIMER_MCR_MR0I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0I_SHIFT)) & CTIMER_MCR_MR0I_MASK) 1669 #define CTIMER_MCR_MR0R_MASK (0x2U) 1670 #define CTIMER_MCR_MR0R_SHIFT (1U) 1671 /*! MR0R - Reset on MR0: the TC will be reset if MR0 matches it. 0 = disabled. 1 = enabled. 1672 */ 1673 #define CTIMER_MCR_MR0R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0R_SHIFT)) & CTIMER_MCR_MR0R_MASK) 1674 #define CTIMER_MCR_MR0S_MASK (0x4U) 1675 #define CTIMER_MCR_MR0S_SHIFT (2U) 1676 /*! MR0S - Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC. 0 = disabled. 1 = enabled. 1677 */ 1678 #define CTIMER_MCR_MR0S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0S_SHIFT)) & CTIMER_MCR_MR0S_MASK) 1679 #define CTIMER_MCR_MR1I_MASK (0x8U) 1680 #define CTIMER_MCR_MR1I_SHIFT (3U) 1681 /*! MR1I - Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC. 0 = 1682 * disabled. 1 = enabled. 0 = disabled. 1 = enabled. 1683 */ 1684 #define CTIMER_MCR_MR1I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1I_SHIFT)) & CTIMER_MCR_MR1I_MASK) 1685 #define CTIMER_MCR_MR1R_MASK (0x10U) 1686 #define CTIMER_MCR_MR1R_SHIFT (4U) 1687 /*! MR1R - Reset on MR1: the TC will be reset if MR1 matches it. 0 = disabled. 1 = enabled. 1688 */ 1689 #define CTIMER_MCR_MR1R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1R_SHIFT)) & CTIMER_MCR_MR1R_MASK) 1690 #define CTIMER_MCR_MR1S_MASK (0x20U) 1691 #define CTIMER_MCR_MR1S_SHIFT (5U) 1692 /*! MR1S - Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC. 0 = disabled. 1 = enabled. 1693 */ 1694 #define CTIMER_MCR_MR1S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1S_SHIFT)) & CTIMER_MCR_MR1S_MASK) 1695 #define CTIMER_MCR_MR2I_MASK (0x40U) 1696 #define CTIMER_MCR_MR2I_SHIFT (6U) 1697 /*! MR2I - Interrupt on MR2: an interrupt is generated when MR2 matches the value in the TC. 0 = disabled. 1 = enabled. 1698 */ 1699 #define CTIMER_MCR_MR2I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2I_SHIFT)) & CTIMER_MCR_MR2I_MASK) 1700 #define CTIMER_MCR_MR2R_MASK (0x80U) 1701 #define CTIMER_MCR_MR2R_SHIFT (7U) 1702 /*! MR2R - Reset on MR2: the TC will be reset if MR2 matches it. 0 = disabled. 1 = enabled. 1703 */ 1704 #define CTIMER_MCR_MR2R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2R_SHIFT)) & CTIMER_MCR_MR2R_MASK) 1705 #define CTIMER_MCR_MR2S_MASK (0x100U) 1706 #define CTIMER_MCR_MR2S_SHIFT (8U) 1707 /*! MR2S - Stop on MR2: the TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC. 0 = disabled. 1 = enabled. 1708 */ 1709 #define CTIMER_MCR_MR2S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2S_SHIFT)) & CTIMER_MCR_MR2S_MASK) 1710 #define CTIMER_MCR_MR3I_MASK (0x200U) 1711 #define CTIMER_MCR_MR3I_SHIFT (9U) 1712 /*! MR3I - Interrupt on MR3: an interrupt is generated when MR3 matches the value in the TC. 0 = disabled. 1 = enabled. 1713 */ 1714 #define CTIMER_MCR_MR3I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3I_SHIFT)) & CTIMER_MCR_MR3I_MASK) 1715 #define CTIMER_MCR_MR3R_MASK (0x400U) 1716 #define CTIMER_MCR_MR3R_SHIFT (10U) 1717 /*! MR3R - Reset on MR3: the TC will be reset if MR3 matches it. 0 = disabled. 1 = enabled. 1718 */ 1719 #define CTIMER_MCR_MR3R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3R_SHIFT)) & CTIMER_MCR_MR3R_MASK) 1720 #define CTIMER_MCR_MR3S_MASK (0x800U) 1721 #define CTIMER_MCR_MR3S_SHIFT (11U) 1722 /*! MR3S - Stop on MR3: the TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC. 0 = disabled. 1 = enabled. 1723 */ 1724 #define CTIMER_MCR_MR3S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3S_SHIFT)) & CTIMER_MCR_MR3S_MASK) 1725 #define CTIMER_MCR_MR0RL_MASK (0x1000000U) 1726 #define CTIMER_MCR_MR0RL_SHIFT (24U) 1727 /*! MR0RL - Reload MR0 with the contents of the Match 0 Shadow Register when the TC is reset to zero 1728 * (either via a match event or a write to bit 1 of the TCR). 0 = disabled. 1 = enabled. 1729 */ 1730 #define CTIMER_MCR_MR0RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0RL_SHIFT)) & CTIMER_MCR_MR0RL_MASK) 1731 #define CTIMER_MCR_MR1RL_MASK (0x2000000U) 1732 #define CTIMER_MCR_MR1RL_SHIFT (25U) 1733 /*! MR1RL - Reload MR1 with the contents of the Match 1 Shadow Register when the TC is reset to zero 1734 * (either via a match event or a write to bit 1 of the TCR). 0 = disabled. 1 = enabled. 1735 */ 1736 #define CTIMER_MCR_MR1RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1RL_SHIFT)) & CTIMER_MCR_MR1RL_MASK) 1737 #define CTIMER_MCR_MR2RL_MASK (0x4000000U) 1738 #define CTIMER_MCR_MR2RL_SHIFT (26U) 1739 /*! MR2RL - Reload MR2 with the contents of the Match 2 Shadow Register when the TC is reset to zero 1740 * (either via a match event or a write to bit 1 of the TCR). 0 = disabled. 1 = enabled. 1741 */ 1742 #define CTIMER_MCR_MR2RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2RL_SHIFT)) & CTIMER_MCR_MR2RL_MASK) 1743 #define CTIMER_MCR_MR3RL_MASK (0x8000000U) 1744 #define CTIMER_MCR_MR3RL_SHIFT (27U) 1745 /*! MR3RL - Reload MR3 with the contents of the Match 3 Shadow Register when the TC is reset to zero 1746 * (either via a match event or a write to bit 1 of the TCR). 0 = disabled. 1 = enabled. 1747 */ 1748 #define CTIMER_MCR_MR3RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3RL_SHIFT)) & CTIMER_MCR_MR3RL_MASK) 1749 /*! @} */ 1750 1751 /*! @name MR - Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */ 1752 /*! @{ */ 1753 #define CTIMER_MR_MATCH_MASK (0xFFFFFFFFU) 1754 #define CTIMER_MR_MATCH_SHIFT (0U) 1755 /*! MATCH - Timer counter match value. 1756 */ 1757 #define CTIMER_MR_MATCH(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MR_MATCH_SHIFT)) & CTIMER_MR_MATCH_MASK) 1758 /*! @} */ 1759 1760 /* The count of CTIMER_MR */ 1761 #define CTIMER_MR_COUNT (4U) 1762 1763 /*! @name CCR - Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */ 1764 /*! @{ */ 1765 #define CTIMER_CCR_CAP0RE_MASK (0x1U) 1766 #define CTIMER_CCR_CAP0RE_SHIFT (0U) 1767 /*! CAP0RE - Rising edge of capture channel 0: a sequence of 0 then 1 causes CR0 to be loaded with 1768 * the contents of TC. 0 = disabled. 1 = enabled. 1769 */ 1770 #define CTIMER_CCR_CAP0RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0RE_SHIFT)) & CTIMER_CCR_CAP0RE_MASK) 1771 #define CTIMER_CCR_CAP0FE_MASK (0x2U) 1772 #define CTIMER_CCR_CAP0FE_SHIFT (1U) 1773 /*! CAP0FE - Falling edge of capture channel 0: a sequence of 1 then 0 causes CR0 to be loaded with 1774 * the contents of TC. 0 = disabled. 1 = enabled. 1775 */ 1776 #define CTIMER_CCR_CAP0FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0FE_SHIFT)) & CTIMER_CCR_CAP0FE_MASK) 1777 #define CTIMER_CCR_CAP0I_MASK (0x4U) 1778 #define CTIMER_CCR_CAP0I_SHIFT (2U) 1779 /*! CAP0I - Generate interrupt on channel 0 capture event: a CR0 load generates an interrupt. 1780 */ 1781 #define CTIMER_CCR_CAP0I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0I_SHIFT)) & CTIMER_CCR_CAP0I_MASK) 1782 #define CTIMER_CCR_CAP1RE_MASK (0x8U) 1783 #define CTIMER_CCR_CAP1RE_SHIFT (3U) 1784 /*! CAP1RE - Rising edge of capture channel 1: a sequence of 0 then 1 causes CR1 to be loaded with 1785 * the contents of TC. 0 = disabled. 1 = enabled. 1786 */ 1787 #define CTIMER_CCR_CAP1RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1RE_SHIFT)) & CTIMER_CCR_CAP1RE_MASK) 1788 #define CTIMER_CCR_CAP1FE_MASK (0x10U) 1789 #define CTIMER_CCR_CAP1FE_SHIFT (4U) 1790 /*! CAP1FE - Falling edge of capture channel 1: a sequence of 1 then 0 causes CR1 to be loaded with 1791 * the contents of TC. 0 = disabled. 1 = enabled. 1792 */ 1793 #define CTIMER_CCR_CAP1FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1FE_SHIFT)) & CTIMER_CCR_CAP1FE_MASK) 1794 #define CTIMER_CCR_CAP1I_MASK (0x20U) 1795 #define CTIMER_CCR_CAP1I_SHIFT (5U) 1796 /*! CAP1I - Generate interrupt on channel 1 capture event: a CR1 load generates an interrupt. 1797 */ 1798 #define CTIMER_CCR_CAP1I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1I_SHIFT)) & CTIMER_CCR_CAP1I_MASK) 1799 #define CTIMER_CCR_CAP2RE_MASK (0x40U) 1800 #define CTIMER_CCR_CAP2RE_SHIFT (6U) 1801 /*! CAP2RE - Rising edge of capture channel 2: a sequence of 0 then 1 causes CR2 to be loaded with 1802 * the contents of TC. 0 = disabled. 1 = enabled. 1803 */ 1804 #define CTIMER_CCR_CAP2RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2RE_SHIFT)) & CTIMER_CCR_CAP2RE_MASK) 1805 #define CTIMER_CCR_CAP2FE_MASK (0x80U) 1806 #define CTIMER_CCR_CAP2FE_SHIFT (7U) 1807 /*! CAP2FE - Falling edge of capture channel 2: a sequence of 1 then 0 causes CR2 to be loaded with 1808 * the contents of TC. 0 = disabled. 1 = enabled. 1809 */ 1810 #define CTIMER_CCR_CAP2FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2FE_SHIFT)) & CTIMER_CCR_CAP2FE_MASK) 1811 #define CTIMER_CCR_CAP2I_MASK (0x100U) 1812 #define CTIMER_CCR_CAP2I_SHIFT (8U) 1813 /*! CAP2I - Generate interrupt on channel 2 capture event: a CR2 load generates an interrupt. 1814 */ 1815 #define CTIMER_CCR_CAP2I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2I_SHIFT)) & CTIMER_CCR_CAP2I_MASK) 1816 /*! @} */ 1817 1818 /*! @name CR - Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input. */ 1819 /*! @{ */ 1820 #define CTIMER_CR_CAP_MASK (0xFFFFFFFFU) 1821 #define CTIMER_CR_CAP_SHIFT (0U) 1822 /*! CAP - Timer counter capture value. 1823 */ 1824 #define CTIMER_CR_CAP(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CR_CAP_SHIFT)) & CTIMER_CR_CAP_MASK) 1825 /*! @} */ 1826 1827 /* The count of CTIMER_CR */ 1828 #define CTIMER_CR_COUNT (3U) 1829 1830 /*! @name EMR - External Match Register. The EMR controls the match function and the external match pins. */ 1831 /*! @{ */ 1832 #define CTIMER_EMR_EM0_MASK (0x1U) 1833 #define CTIMER_EMR_EM0_SHIFT (0U) 1834 /*! EM0 - External Match 0. This bit reflects the state of output MAT0, whether or not this output 1835 * is connected to a pin. When a match occurs between the TC and MR0, this bit can either toggle, 1836 * go LOW, go HIGH, or do nothing, as selected by EMR[5:4]. This bit is driven to the MAT pins if 1837 * the match function is selected via IOCON. 0 = LOW. 1 = HIGH. 1838 */ 1839 #define CTIMER_EMR_EM0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM0_SHIFT)) & CTIMER_EMR_EM0_MASK) 1840 #define CTIMER_EMR_EM1_MASK (0x2U) 1841 #define CTIMER_EMR_EM1_SHIFT (1U) 1842 /*! EM1 - External Match 1. This bit reflects the state of output MAT1, whether or not this output 1843 * is connected to a pin. When a match occurs between the TC and MR1, this bit can either toggle, 1844 * go LOW, go HIGH, or do nothing, as selected by EMR[7:6]. This bit is driven to the MAT pins if 1845 * the match function is selected via IOCON. 0 = LOW. 1 = HIGH. 1846 */ 1847 #define CTIMER_EMR_EM1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM1_SHIFT)) & CTIMER_EMR_EM1_MASK) 1848 #define CTIMER_EMR_EM2_MASK (0x4U) 1849 #define CTIMER_EMR_EM2_SHIFT (2U) 1850 /*! EM2 - External Match 2. This bit reflects the state of output MAT2, whether or not this output 1851 * is connected to a pin. When a match occurs between the TC and MR2, this bit can either toggle, 1852 * go LOW, go HIGH, or do nothing, as selected by EMR[9:8]. This bit is driven to the MAT pins if 1853 * the match function is selected via IOCON. 0 = LOW. 1 = HIGH. 1854 */ 1855 #define CTIMER_EMR_EM2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM2_SHIFT)) & CTIMER_EMR_EM2_MASK) 1856 #define CTIMER_EMR_EM3_MASK (0x8U) 1857 #define CTIMER_EMR_EM3_SHIFT (3U) 1858 /*! EM3 - External Match 3. This bit reflects the state of output MAT3, whether or not this output 1859 * is connected to a pin. When a match occurs between the TC and MR3, this bit can either toggle, 1860 * go LOW, go HIGH, or do nothing, as selected by MR[11:10]. This bit is driven to the MAT pins 1861 * if the match function is selected via IOCON. 0 = LOW. 1 = HIGH. 1862 */ 1863 #define CTIMER_EMR_EM3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM3_SHIFT)) & CTIMER_EMR_EM3_MASK) 1864 #define CTIMER_EMR_EMC0_MASK (0x30U) 1865 #define CTIMER_EMR_EMC0_SHIFT (4U) 1866 /*! EMC0 - External Match Control 0. Determines the functionality of External Match 0. 1867 * 0b00..Do Nothing. 1868 * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT0 pin is LOW if pinned out). 1869 * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT0 pin is HIGH if pinned out). 1870 * 0b11..Toggle. Toggle the corresponding External Match bit/output. 1871 */ 1872 #define CTIMER_EMR_EMC0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC0_SHIFT)) & CTIMER_EMR_EMC0_MASK) 1873 #define CTIMER_EMR_EMC1_MASK (0xC0U) 1874 #define CTIMER_EMR_EMC1_SHIFT (6U) 1875 /*! EMC1 - External Match Control 1. Determines the functionality of External Match 1. 1876 * 0b00..Do Nothing. 1877 * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT1 pin is LOW if pinned out). 1878 * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT1 pin is HIGH if pinned out). 1879 * 0b11..Toggle. Toggle the corresponding External Match bit/output. 1880 */ 1881 #define CTIMER_EMR_EMC1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC1_SHIFT)) & CTIMER_EMR_EMC1_MASK) 1882 #define CTIMER_EMR_EMC2_MASK (0x300U) 1883 #define CTIMER_EMR_EMC2_SHIFT (8U) 1884 /*! EMC2 - External Match Control 2. Determines the functionality of External Match 2. 1885 * 0b00..Do Nothing. 1886 * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT2 pin is LOW if pinned out). 1887 * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT2 pin is HIGH if pinned out). 1888 * 0b11..Toggle. Toggle the corresponding External Match bit/output. 1889 */ 1890 #define CTIMER_EMR_EMC2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC2_SHIFT)) & CTIMER_EMR_EMC2_MASK) 1891 #define CTIMER_EMR_EMC3_MASK (0xC00U) 1892 #define CTIMER_EMR_EMC3_SHIFT (10U) 1893 /*! EMC3 - External Match Control 3. Determines the functionality of External Match 3. 1894 * 0b00..Do Nothing. 1895 * 0b01..Clear. Clear the corresponding External Match bit/output to 0 (MAT3 pin is LOW if pinned out). 1896 * 0b10..Set. Set the corresponding External Match bit/output to 1 (MAT3 pin is HIGH if pinned out). 1897 * 0b11..Toggle. Toggle the corresponding External Match bit/output. 1898 */ 1899 #define CTIMER_EMR_EMC3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC3_SHIFT)) & CTIMER_EMR_EMC3_MASK) 1900 /*! @} */ 1901 1902 /*! @name CTCR - Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */ 1903 /*! @{ */ 1904 #define CTIMER_CTCR_CTMODE_MASK (0x3U) 1905 #define CTIMER_CTCR_CTMODE_SHIFT (0U) 1906 /*! CTMODE - Counter/Timer Mode This field selects which rising APB bus clock edges can increment 1907 * Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC 1908 * is incremented when the Prescale Counter matches the Prescale Register. 1909 * 0b00..Timer Mode. Incremented every rising APB bus clock edge. 1910 * 0b01..Counter Mode rising edge. TC is incremented on rising edges on the CAP input selected by bits 3:2. 1911 * 0b10..Counter Mode falling edge. TC is incremented on falling edges on the CAP input selected by bits 3:2. 1912 * 0b11..Counter Mode dual edge. TC is incremented on both edges on the CAP input selected by bits 3:2. 1913 */ 1914 #define CTIMER_CTCR_CTMODE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CTMODE_SHIFT)) & CTIMER_CTCR_CTMODE_MASK) 1915 #define CTIMER_CTCR_CINSEL_MASK (0xCU) 1916 #define CTIMER_CTCR_CINSEL_SHIFT (2U) 1917 /*! CINSEL - Count Input Select When bits 1:0 in this register are not 00, these bits select which 1918 * CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input 1919 * in the CTCR, the 3 bits for that input in the Capture Control Register (CCR) must be 1920 * programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the 1921 * same timer. 1922 * 0b00..Channel 0. CAPn.0 for CTIMERn 1923 * 0b01..Channel 1. CAPn.1 for CTIMERn 1924 * 0b10..Channel 2. CAPn.2 for CTIMERn 1925 * 0b11..Channel 3. CAPn.3 for CTIMERn 1926 */ 1927 #define CTIMER_CTCR_CINSEL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CINSEL_SHIFT)) & CTIMER_CTCR_CINSEL_MASK) 1928 #define CTIMER_CTCR_ENCC_MASK (0x10U) 1929 #define CTIMER_CTCR_ENCC_SHIFT (4U) 1930 /*! ENCC - Setting this bit to 1 enables clearing of the timer and the prescaler when the 1931 * capture-edge event specified in bits 7:5 occurs. 1932 */ 1933 #define CTIMER_CTCR_ENCC(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_ENCC_SHIFT)) & CTIMER_CTCR_ENCC_MASK) 1934 #define CTIMER_CTCR_SELCC_MASK (0xE0U) 1935 #define CTIMER_CTCR_SELCC_SHIFT (5U) 1936 /*! SELCC - Edge select. When bit 4 is 1, these bits select which capture input edge will cause the 1937 * timer and prescaler to be cleared. These bits have no effect when bit 4 is low. Values 0x2 to 1938 * 0x3 and 0x6 to 0x7 are reserved. 1939 * 0b000..Channel 0 Rising Edge. Rising edge of the signal on capture channel 0 clears the timer (if bit 4 is set). 1940 * 0b001..Channel 0 Falling Edge. Falling edge of the signal on capture channel 0 clears the timer (if bit 4 is set). 1941 * 0b010..Channel 1 Rising Edge. Rising edge of the signal on capture channel 1 clears the timer (if bit 4 is set). 1942 * 0b011..Channel 1 Falling Edge. Falling edge of the signal on capture channel 1 clears the timer (if bit 4 is set). 1943 * 0b100..Channel 2 Rising Edge. Rising edge of the signal on capture channel 2 clears the timer (if bit 4 is set). 1944 * 0b101..Channel 2 Falling Edge. Falling edge of the signal on capture channel 2 clears the timer (if bit 4 is set). 1945 */ 1946 #define CTIMER_CTCR_SELCC(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_SELCC_SHIFT)) & CTIMER_CTCR_SELCC_MASK) 1947 /*! @} */ 1948 1949 /*! @name PWMC - PWM Control Register. The PWMCON enables PWM mode for the external match pins. */ 1950 /*! @{ */ 1951 #define CTIMER_PWMC_PWMEN0_MASK (0x1U) 1952 #define CTIMER_PWMC_PWMEN0_SHIFT (0U) 1953 /*! PWMEN0 - PWM mode enable for channel0. 1954 * 0b0..Match. CTIMERn_MAT0 is controlled by EM0. 1955 * 0b1..PWM. PWM mode is enabled for CTIMERn_MAT0. 1956 */ 1957 #define CTIMER_PWMC_PWMEN0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN0_SHIFT)) & CTIMER_PWMC_PWMEN0_MASK) 1958 #define CTIMER_PWMC_PWMEN1_MASK (0x2U) 1959 #define CTIMER_PWMC_PWMEN1_SHIFT (1U) 1960 /*! PWMEN1 - PWM mode enable for channel1. 1961 * 0b0..Match. CTIMERn_MAT01 is controlled by EM1. 1962 * 0b1..PWM. PWM mode is enabled for CTIMERn_MAT1. 1963 */ 1964 #define CTIMER_PWMC_PWMEN1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN1_SHIFT)) & CTIMER_PWMC_PWMEN1_MASK) 1965 #define CTIMER_PWMC_PWMEN2_MASK (0x4U) 1966 #define CTIMER_PWMC_PWMEN2_SHIFT (2U) 1967 /*! PWMEN2 - PWM mode enable for channel2. 1968 * 0b0..Match. CTIMERn_MAT2 is controlled by EM2. 1969 * 0b1..PWM. PWM mode is enabled for CTIMERn_MAT2. 1970 */ 1971 #define CTIMER_PWMC_PWMEN2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN2_SHIFT)) & CTIMER_PWMC_PWMEN2_MASK) 1972 #define CTIMER_PWMC_PWMEN3_MASK (0x8U) 1973 #define CTIMER_PWMC_PWMEN3_SHIFT (3U) 1974 /*! PWMEN3 - PWM mode enable for channel3. Note: It is recommended to use match channel 3 to set the PWM cycle. 1975 * 0b0..Match. CTIMERn_MAT3 is controlled by EM3. 1976 * 0b1..PWM. PWM mode is enabled for CT132Bn_MAT3. 1977 */ 1978 #define CTIMER_PWMC_PWMEN3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN3_SHIFT)) & CTIMER_PWMC_PWMEN3_MASK) 1979 /*! @} */ 1980 1981 /*! @name MSR - Match Shadow Register . If enabled, the Match Register will be automatically reloaded with the contents of this register whenever the TC is reset to zero. */ 1982 /*! @{ */ 1983 #define CTIMER_MSR_MATCH_Shadow_MASK (0xFFFFFFFFU) 1984 #define CTIMER_MSR_MATCH_Shadow_SHIFT (0U) 1985 /*! MATCH_Shadow - Timer counter match value. 1986 */ 1987 #define CTIMER_MSR_MATCH_Shadow(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MSR_MATCH_Shadow_SHIFT)) & CTIMER_MSR_MATCH_Shadow_MASK) 1988 /*! @} */ 1989 1990 /* The count of CTIMER_MSR */ 1991 #define CTIMER_MSR_COUNT (4U) 1992 1993 1994 /*! 1995 * @} 1996 */ /* end of group CTIMER_Register_Masks */ 1997 1998 1999 /* CTIMER - Peripheral instance base addresses */ 2000 /** Peripheral CTIMER0 base address */ 2001 #define CTIMER0_BASE (0x40038000u) 2002 /** Peripheral CTIMER0 base pointer */ 2003 #define CTIMER0 ((CTIMER_Type *)CTIMER0_BASE) 2004 /** Array initializer of CTIMER peripheral base addresses */ 2005 #define CTIMER_BASE_ADDRS { CTIMER0_BASE } 2006 /** Array initializer of CTIMER peripheral base pointers */ 2007 #define CTIMER_BASE_PTRS { CTIMER0 } 2008 /** Interrupt vectors for the CTIMER peripheral type */ 2009 #define CTIMER_IRQS { CTIMER0_IRQn } 2010 2011 /*! 2012 * @} 2013 */ /* end of group CTIMER_Peripheral_Access_Layer */ 2014 2015 2016 /* ---------------------------------------------------------------------------- 2017 -- DAC Peripheral Access Layer 2018 ---------------------------------------------------------------------------- */ 2019 2020 /*! 2021 * @addtogroup DAC_Peripheral_Access_Layer DAC Peripheral Access Layer 2022 * @{ 2023 */ 2024 2025 /** DAC - Register Layout Typedef */ 2026 typedef struct { 2027 __IO uint32_t CR; /**< D/A Converter Register. This register contains the digital value to be converted to analog and a power control bit., offset: 0x0 */ 2028 __IO uint32_t CTRL; /**< DAC Control register. This register controls DMA and timer operation., offset: 0x4 */ 2029 __IO uint32_t CNTVAL; /**< DAC Counter Value register. This register contains the reload value for the DAC DMA/Interrupt timer., offset: 0x8 */ 2030 } DAC_Type; 2031 2032 /* ---------------------------------------------------------------------------- 2033 -- DAC Register Masks 2034 ---------------------------------------------------------------------------- */ 2035 2036 /*! 2037 * @addtogroup DAC_Register_Masks DAC Register Masks 2038 * @{ 2039 */ 2040 2041 /*! @name CR - D/A Converter Register. This register contains the digital value to be converted to analog and a power control bit. */ 2042 /*! @{ */ 2043 #define DAC_CR_VALUE_MASK (0xFFC0U) 2044 #define DAC_CR_VALUE_SHIFT (6U) 2045 /*! VALUE - After the selected settling time after this field is written with a new VALUE, the 2046 * voltage on the DAC_OUT pin (with respect to VSSA) is VALUE (VREFP - VREFN)/1024 + VREFN. 2047 */ 2048 #define DAC_CR_VALUE(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_VALUE_SHIFT)) & DAC_CR_VALUE_MASK) 2049 #define DAC_CR_BIAS_MASK (0x10000U) 2050 #define DAC_CR_BIAS_SHIFT (16U) 2051 /*! BIAS - The settling time of the DAC 2052 * 0b0..The settling time of the DAC is 1 us max, and the maximum current is 700 uA. This allows a maximum update rate of 1 MHz. 2053 * 0b1..The settling time of the DAC is 2.5 us and the maximum current is 350 uA. This allows a maximum update rate of 400 kHz. 2054 */ 2055 #define DAC_CR_BIAS(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_BIAS_SHIFT)) & DAC_CR_BIAS_MASK) 2056 /*! @} */ 2057 2058 /*! @name CTRL - DAC Control register. This register controls DMA and timer operation. */ 2059 /*! @{ */ 2060 #define DAC_CTRL_INT_CPU_REQ_MASK (0x1U) 2061 #define DAC_CTRL_INT_CPU_REQ_SHIFT (0U) 2062 /*! INT_CPU_REQ - Interrupt request to CPU. This interrupt request is handled by the CPU. 2063 * 0b0..Clear on any write to the CR register. 2064 * 0b1..Set by hardware when the timer times out. 2065 */ 2066 #define DAC_CTRL_INT_CPU_REQ(x) (((uint32_t)(((uint32_t)(x)) << DAC_CTRL_INT_CPU_REQ_SHIFT)) & DAC_CTRL_INT_CPU_REQ_MASK) 2067 #define DAC_CTRL_DBLBUF_ENA_MASK (0x2U) 2068 #define DAC_CTRL_DBLBUF_ENA_SHIFT (1U) 2069 /*! DBLBUF_ENA - dacr double buffer 2070 * 0b0..DACR double-buffering is disabled. 2071 * 0b1..When this bit and the CNT_ENA bit are both set, the double-buffering feature in the DACR register will be 2072 * enabled. Writes to the DACR register are written to a pre-buffer and then transferred to the DACR on the 2073 * next time-out of the counter. 2074 */ 2075 #define DAC_CTRL_DBLBUF_ENA(x) (((uint32_t)(((uint32_t)(x)) << DAC_CTRL_DBLBUF_ENA_SHIFT)) & DAC_CTRL_DBLBUF_ENA_MASK) 2076 #define DAC_CTRL_CNT_ENA_MASK (0x4U) 2077 #define DAC_CTRL_CNT_ENA_SHIFT (2U) 2078 /*! CNT_ENA - time-out counter operation 2079 * 0b0..Time-out counter operation is disabled. 2080 * 0b1..Time-out counter operation is enabled. 2081 */ 2082 #define DAC_CTRL_CNT_ENA(x) (((uint32_t)(((uint32_t)(x)) << DAC_CTRL_CNT_ENA_SHIFT)) & DAC_CTRL_CNT_ENA_MASK) 2083 /*! @} */ 2084 2085 /*! @name CNTVAL - DAC Counter Value register. This register contains the reload value for the DAC DMA/Interrupt timer. */ 2086 /*! @{ */ 2087 #define DAC_CNTVAL_VALUE_MASK (0xFFFFU) 2088 #define DAC_CNTVAL_VALUE_SHIFT (0U) 2089 /*! VALUE - 16-bit reload value for the DAC interrupt/DMA timer. 2090 */ 2091 #define DAC_CNTVAL_VALUE(x) (((uint32_t)(((uint32_t)(x)) << DAC_CNTVAL_VALUE_SHIFT)) & DAC_CNTVAL_VALUE_MASK) 2092 /*! @} */ 2093 2094 2095 /*! 2096 * @} 2097 */ /* end of group DAC_Register_Masks */ 2098 2099 2100 /* DAC - Peripheral instance base addresses */ 2101 /** Peripheral DAC0 base address */ 2102 #define DAC0_BASE (0x40014000u) 2103 /** Peripheral DAC0 base pointer */ 2104 #define DAC0 ((DAC_Type *)DAC0_BASE) 2105 /** Array initializer of DAC peripheral base addresses */ 2106 #define DAC_BASE_ADDRS { DAC0_BASE } 2107 /** Array initializer of DAC peripheral base pointers */ 2108 #define DAC_BASE_PTRS { DAC0 } 2109 2110 /*! 2111 * @} 2112 */ /* end of group DAC_Peripheral_Access_Layer */ 2113 2114 2115 /* ---------------------------------------------------------------------------- 2116 -- GPIO Peripheral Access Layer 2117 ---------------------------------------------------------------------------- */ 2118 2119 /*! 2120 * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer 2121 * @{ 2122 */ 2123 2124 /** GPIO - Register Layout Typedef */ 2125 typedef struct { 2126 __IO uint8_t B[1][31]; /**< Byte pin registers for all port 0 and 1 GPIO pins, array offset: 0x0, array step: index*0x1F, index2*0x1 */ 2127 uint8_t RESERVED_0[4065]; 2128 __IO uint32_t W[1][31]; /**< Word pin registers for all port 0 and 1 GPIO pins, array offset: 0x1000, array step: index*0x7C, index2*0x4 */ 2129 uint8_t RESERVED_1[3972]; 2130 __IO uint32_t DIR[1]; /**< Direction registers, array offset: 0x2000, array step: 0x4 */ 2131 uint8_t RESERVED_2[124]; 2132 __IO uint32_t MASK[1]; /**< Mask register, array offset: 0x2080, array step: 0x4 */ 2133 uint8_t RESERVED_3[124]; 2134 __IO uint32_t PIN[1]; /**< Port pin register, array offset: 0x2100, array step: 0x4 */ 2135 uint8_t RESERVED_4[124]; 2136 __IO uint32_t MPIN[1]; /**< Masked port register, array offset: 0x2180, array step: 0x4 */ 2137 uint8_t RESERVED_5[124]; 2138 __IO uint32_t SET[1]; /**< Write: Set register for port Read: output bits for port, array offset: 0x2200, array step: 0x4 */ 2139 uint8_t RESERVED_6[124]; 2140 __O uint32_t CLR[1]; /**< Clear port, array offset: 0x2280, array step: 0x4 */ 2141 uint8_t RESERVED_7[124]; 2142 __O uint32_t NOT[1]; /**< Toggle port, array offset: 0x2300, array step: 0x4 */ 2143 uint8_t RESERVED_8[124]; 2144 __O uint32_t DIRSET[1]; /**< Set pin direction bits for port, array offset: 0x2380, array step: 0x4 */ 2145 uint8_t RESERVED_9[124]; 2146 __O uint32_t DIRCLR[1]; /**< Clear pin direction bits for port, array offset: 0x2400, array step: 0x4 */ 2147 uint8_t RESERVED_10[124]; 2148 __O uint32_t DIRNOT[1]; /**< Toggle pin direction bits for port, array offset: 0x2480, array step: 0x4 */ 2149 } GPIO_Type; 2150 2151 /* ---------------------------------------------------------------------------- 2152 -- GPIO Register Masks 2153 ---------------------------------------------------------------------------- */ 2154 2155 /*! 2156 * @addtogroup GPIO_Register_Masks GPIO Register Masks 2157 * @{ 2158 */ 2159 2160 /*! @name B - Byte pin registers for all port 0 and 1 GPIO pins */ 2161 /*! @{ */ 2162 #define GPIO_B_PBYTE_MASK (0x1U) 2163 #define GPIO_B_PBYTE_SHIFT (0U) 2164 /*! PBYTE - Read: state of the pin PIOm_n, regardless of direction, masking, or alternate function, 2165 * except that pins configured as analog I/O always read as 0. One register for each port pin. 2166 * Supported pins depends on the specific device and package. Write: loads the pin's output bit. 2167 * One register for each port pin. Supported pins depends on the specific device and package. 2168 */ 2169 #define GPIO_B_PBYTE(x) (((uint8_t)(((uint8_t)(x)) << GPIO_B_PBYTE_SHIFT)) & GPIO_B_PBYTE_MASK) 2170 /*! @} */ 2171 2172 /* The count of GPIO_B */ 2173 #define GPIO_B_COUNT (1U) 2174 2175 /* The count of GPIO_B */ 2176 #define GPIO_B_COUNT2 (31U) 2177 2178 /*! @name W - Word pin registers for all port 0 and 1 GPIO pins */ 2179 /*! @{ */ 2180 #define GPIO_W_PWORD_MASK (0xFFFFFFFFU) 2181 #define GPIO_W_PWORD_SHIFT (0U) 2182 /*! PWORD - Read 0: pin PIOm_n is LOW. Write 0: clear output bit. Read 0xFFFF FFFF: pin PIOm_n is 2183 * HIGH. Write any value 0x0000 0001 to 0xFFFF FFFF: set output bit. Only 0 or 0xFFFF FFFF can be 2184 * read. Writing any value other than 0 will set the output bit. One register for each port pin. 2185 * Supported pins depends on the specific device and package. 2186 */ 2187 #define GPIO_W_PWORD(x) (((uint32_t)(((uint32_t)(x)) << GPIO_W_PWORD_SHIFT)) & GPIO_W_PWORD_MASK) 2188 /*! @} */ 2189 2190 /* The count of GPIO_W */ 2191 #define GPIO_W_COUNT (1U) 2192 2193 /* The count of GPIO_W */ 2194 #define GPIO_W_COUNT2 (31U) 2195 2196 /*! @name DIR - Direction registers */ 2197 /*! @{ */ 2198 #define GPIO_DIR_DIRP_MASK (0x7FFFFFFFU) 2199 #define GPIO_DIR_DIRP_SHIFT (0U) 2200 /*! DIRP - Selects pin direction for pin PIOm_n (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported 2201 * pins depends on the specific device and package. 0 = input. 1 = output. 2202 */ 2203 #define GPIO_DIR_DIRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP_SHIFT)) & GPIO_DIR_DIRP_MASK) 2204 /*! @} */ 2205 2206 /* The count of GPIO_DIR */ 2207 #define GPIO_DIR_COUNT (1U) 2208 2209 /*! @name MASK - Mask register */ 2210 /*! @{ */ 2211 #define GPIO_MASK_MASKP_MASK (0x7FFFFFFFU) 2212 #define GPIO_MASK_MASKP_SHIFT (0U) 2213 /*! MASKP - Controls which bits corresponding to PIOm_n are active in the MPORT register (bit 0 = 2214 * PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the specific device and package. 0 = 2215 * Read MPORT: pin state; write MPORT: load output bit. 1 = Read MPORT: 0; write MPORT: output bit 2216 * not affected. 2217 */ 2218 #define GPIO_MASK_MASKP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP_SHIFT)) & GPIO_MASK_MASKP_MASK) 2219 /*! @} */ 2220 2221 /* The count of GPIO_MASK */ 2222 #define GPIO_MASK_COUNT (1U) 2223 2224 /*! @name PIN - Port pin register */ 2225 /*! @{ */ 2226 #define GPIO_PIN_PORT_MASK (0x7FFFFFFFU) 2227 #define GPIO_PIN_PORT_SHIFT (0U) 2228 /*! PORT - Reads pin states or loads output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported 2229 * pins depends on the specific device and package. 0 = Read: pin is low; write: clear output bit. 2230 * 1 = Read: pin is high; write: set output bit. 2231 */ 2232 #define GPIO_PIN_PORT(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT_SHIFT)) & GPIO_PIN_PORT_MASK) 2233 /*! @} */ 2234 2235 /* The count of GPIO_PIN */ 2236 #define GPIO_PIN_COUNT (1U) 2237 2238 /*! @name MPIN - Masked port register */ 2239 /*! @{ */ 2240 #define GPIO_MPIN_MPORTP_MASK (0x7FFFFFFFU) 2241 #define GPIO_MPIN_MPORTP_SHIFT (0U) 2242 /*! MPORTP - Masked port register (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on 2243 * the specific device and package. 0 = Read: pin is LOW and/or the corresponding bit in the MASK 2244 * register is 1; write: clear output bit if the corresponding bit in the MASK register is 0. 1 2245 * = Read: pin is HIGH and the corresponding bit in the MASK register is 0; write: set output bit 2246 * if the corresponding bit in the MASK register is 0. 2247 */ 2248 #define GPIO_MPIN_MPORTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP_SHIFT)) & GPIO_MPIN_MPORTP_MASK) 2249 /*! @} */ 2250 2251 /* The count of GPIO_MPIN */ 2252 #define GPIO_MPIN_COUNT (1U) 2253 2254 /*! @name SET - Write: Set register for port Read: output bits for port */ 2255 /*! @{ */ 2256 #define GPIO_SET_SETP_MASK (0x7FFFFFFFU) 2257 #define GPIO_SET_SETP_SHIFT (0U) 2258 /*! SETP - Read or set output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on 2259 * the specific device and package. 0 = Read: output bit: write: no operation. 1 = Read: output 2260 * bit; write: set output bit. 2261 */ 2262 #define GPIO_SET_SETP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_SET_SETP_SHIFT)) & GPIO_SET_SETP_MASK) 2263 /*! @} */ 2264 2265 /* The count of GPIO_SET */ 2266 #define GPIO_SET_COUNT (1U) 2267 2268 /*! @name CLR - Clear port */ 2269 /*! @{ */ 2270 #define GPIO_CLR_CLRP_MASK (0x7FFFFFFFU) 2271 #define GPIO_CLR_CLRP_SHIFT (0U) 2272 /*! CLRP - Clear output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the 2273 * specific device and package. 0 = No operation. 1 = Clear output bit. 2274 */ 2275 #define GPIO_CLR_CLRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP_SHIFT)) & GPIO_CLR_CLRP_MASK) 2276 /*! @} */ 2277 2278 /* The count of GPIO_CLR */ 2279 #define GPIO_CLR_COUNT (1U) 2280 2281 /*! @name NOT - Toggle port */ 2282 /*! @{ */ 2283 #define GPIO_NOT_NOTP_MASK (0x7FFFFFFFU) 2284 #define GPIO_NOT_NOTP_SHIFT (0U) 2285 /*! NOTP - Toggle output bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on the 2286 * specific device and package. 0 = no operation. 1 = Toggle output bit. 2287 */ 2288 #define GPIO_NOT_NOTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP_SHIFT)) & GPIO_NOT_NOTP_MASK) 2289 /*! @} */ 2290 2291 /* The count of GPIO_NOT */ 2292 #define GPIO_NOT_COUNT (1U) 2293 2294 /*! @name DIRSET - Set pin direction bits for port */ 2295 /*! @{ */ 2296 #define GPIO_DIRSET_DIRSETP_MASK (0x7FFFFFFFU) 2297 #define GPIO_DIRSET_DIRSETP_SHIFT (0U) 2298 /*! DIRSETP - Set direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on 2299 * the specific device and package. 0 = No operation. 1 = Set direction bit. 2300 */ 2301 #define GPIO_DIRSET_DIRSETP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP_SHIFT)) & GPIO_DIRSET_DIRSETP_MASK) 2302 /*! @} */ 2303 2304 /* The count of GPIO_DIRSET */ 2305 #define GPIO_DIRSET_COUNT (1U) 2306 2307 /*! @name DIRCLR - Clear pin direction bits for port */ 2308 /*! @{ */ 2309 #define GPIO_DIRCLR_DIRCLRP_MASK (0x7FFFFFFFU) 2310 #define GPIO_DIRCLR_DIRCLRP_SHIFT (0U) 2311 /*! DIRCLRP - Clear direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends on 2312 * the specific device and package. 0 = No operation. 1 = Clear direction bit. 2313 */ 2314 #define GPIO_DIRCLR_DIRCLRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP_SHIFT)) & GPIO_DIRCLR_DIRCLRP_MASK) 2315 /*! @} */ 2316 2317 /* The count of GPIO_DIRCLR */ 2318 #define GPIO_DIRCLR_COUNT (1U) 2319 2320 /*! @name DIRNOT - Toggle pin direction bits for port */ 2321 /*! @{ */ 2322 #define GPIO_DIRNOT_DIRNOTP_MASK (0x7FFFFFFFU) 2323 #define GPIO_DIRNOT_DIRNOTP_SHIFT (0U) 2324 /*! DIRNOTP - Toggle direction bits (bit 0 = PIOn_0, bit 1 = PIOn_1, etc.). Supported pins depends 2325 * on the specific device and package. 0 = no operation. 1 = Toggle direction bit. 2326 */ 2327 #define GPIO_DIRNOT_DIRNOTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRNOT_DIRNOTP_SHIFT)) & GPIO_DIRNOT_DIRNOTP_MASK) 2328 /*! @} */ 2329 2330 /* The count of GPIO_DIRNOT */ 2331 #define GPIO_DIRNOT_COUNT (1U) 2332 2333 2334 /*! 2335 * @} 2336 */ /* end of group GPIO_Register_Masks */ 2337 2338 2339 /* GPIO - Peripheral instance base addresses */ 2340 /** Peripheral GPIO base address */ 2341 #define GPIO_BASE (0xA0000000u) 2342 /** Peripheral GPIO base pointer */ 2343 #define GPIO ((GPIO_Type *)GPIO_BASE) 2344 /** Array initializer of GPIO peripheral base addresses */ 2345 #define GPIO_BASE_ADDRS { GPIO_BASE } 2346 /** Array initializer of GPIO peripheral base pointers */ 2347 #define GPIO_BASE_PTRS { GPIO } 2348 2349 /*! 2350 * @} 2351 */ /* end of group GPIO_Peripheral_Access_Layer */ 2352 2353 2354 /* ---------------------------------------------------------------------------- 2355 -- I2C Peripheral Access Layer 2356 ---------------------------------------------------------------------------- */ 2357 2358 /*! 2359 * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer 2360 * @{ 2361 */ 2362 2363 /** I2C - Register Layout Typedef */ 2364 typedef struct { 2365 __IO uint32_t CFG; /**< Configuration for shared functions., offset: 0x0 */ 2366 __IO uint32_t STAT; /**< Status register for Master, Slave, and Monitor functions., offset: 0x4 */ 2367 __IO uint32_t INTENSET; /**< Interrupt Enable Set and read register., offset: 0x8 */ 2368 __O uint32_t INTENCLR; /**< Interrupt Enable Clear register., offset: 0xC */ 2369 __IO uint32_t TIMEOUT; /**< Time-out value register., offset: 0x10 */ 2370 __IO uint32_t CLKDIV; /**< Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register, and controls some timing of the Slave function., offset: 0x14 */ 2371 __I uint32_t INTSTAT; /**< Interrupt Status register for Master, Slave, and Monitor functions., offset: 0x18 */ 2372 uint8_t RESERVED_0[4]; 2373 __IO uint32_t MSTCTL; /**< Master control register., offset: 0x20 */ 2374 __IO uint32_t MSTTIME; /**< Master timing configuration., offset: 0x24 */ 2375 __IO uint32_t MSTDAT; /**< Combined Master receiver and transmitter data register., offset: 0x28 */ 2376 uint8_t RESERVED_1[20]; 2377 __IO uint32_t SLVCTL; /**< Slave control register., offset: 0x40 */ 2378 __IO uint32_t SLVDAT; /**< Combined Slave receiver and transmitter data register., offset: 0x44 */ 2379 __IO uint32_t SLVADR[4]; /**< Slave address register., array offset: 0x48, array step: 0x4 */ 2380 __IO uint32_t SLVQUAL0; /**< Slave Qualification for address 0., offset: 0x58 */ 2381 uint8_t RESERVED_2[36]; 2382 __I uint32_t MONRXDAT; /**< Monitor receiver data register., offset: 0x80 */ 2383 } I2C_Type; 2384 2385 /* ---------------------------------------------------------------------------- 2386 -- I2C Register Masks 2387 ---------------------------------------------------------------------------- */ 2388 2389 /*! 2390 * @addtogroup I2C_Register_Masks I2C Register Masks 2391 * @{ 2392 */ 2393 2394 /*! @name CFG - Configuration for shared functions. */ 2395 /*! @{ */ 2396 #define I2C_CFG_MSTEN_MASK (0x1U) 2397 #define I2C_CFG_MSTEN_SHIFT (0U) 2398 /*! MSTEN - Master Enable. When disabled, configurations settings for the Master function are not 2399 * changed, but the Master function is internally reset. 2400 * 0b0..Disabled. The I2C Master function is disabled. 2401 * 0b1..Enabled. The I2C Master function is enabled. 2402 */ 2403 #define I2C_CFG_MSTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MSTEN_SHIFT)) & I2C_CFG_MSTEN_MASK) 2404 #define I2C_CFG_SLVEN_MASK (0x2U) 2405 #define I2C_CFG_SLVEN_SHIFT (1U) 2406 /*! SLVEN - Slave Enable. When disabled, configurations settings for the Slave function are not 2407 * changed, but the Slave function is internally reset. 2408 * 0b0..Disabled. The I2C slave function is disabled. 2409 * 0b1..Enabled. The I2C slave function is enabled. 2410 */ 2411 #define I2C_CFG_SLVEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_SLVEN_SHIFT)) & I2C_CFG_SLVEN_MASK) 2412 #define I2C_CFG_MONEN_MASK (0x4U) 2413 #define I2C_CFG_MONEN_SHIFT (2U) 2414 /*! MONEN - Monitor Enable. When disabled, configurations settings for the Monitor function are not 2415 * changed, but the Monitor function is internally reset. 2416 * 0b0..Disabled. The I2C Monitor function is disabled. 2417 * 0b1..Enabled. The I2C Monitor function is enabled. 2418 */ 2419 #define I2C_CFG_MONEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MONEN_SHIFT)) & I2C_CFG_MONEN_MASK) 2420 #define I2C_CFG_TIMEOUTEN_MASK (0x8U) 2421 #define I2C_CFG_TIMEOUTEN_SHIFT (3U) 2422 /*! TIMEOUTEN - I2C bus Time-out Enable. When disabled, the time-out function is internally reset. 2423 * 0b0..Disabled. Time-out function is disabled. 2424 * 0b1..Enabled. Time-out function is enabled. Both types of time-out flags will be generated and will cause 2425 * interrupts if they are enabled. Typically, only one time-out will be used in a system. 2426 */ 2427 #define I2C_CFG_TIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_TIMEOUTEN_SHIFT)) & I2C_CFG_TIMEOUTEN_MASK) 2428 #define I2C_CFG_MONCLKSTR_MASK (0x10U) 2429 #define I2C_CFG_MONCLKSTR_SHIFT (4U) 2430 /*! MONCLKSTR - Monitor function Clock Stretching. 2431 * 0b0..Disabled. The Monitor function will not perform clock stretching. Software or DMA may not always be able 2432 * to read data provided by the Monitor function before it is overwritten. This mode may be used when 2433 * non-invasive monitoring is critical. 2434 * 0b1..Enabled. The Monitor function will perform clock stretching in order to ensure that software or DMA can 2435 * read all incoming data supplied by the Monitor function. 2436 */ 2437 #define I2C_CFG_MONCLKSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MONCLKSTR_SHIFT)) & I2C_CFG_MONCLKSTR_MASK) 2438 /*! @} */ 2439 2440 /*! @name STAT - Status register for Master, Slave, and Monitor functions. */ 2441 /*! @{ */ 2442 #define I2C_STAT_MSTPENDING_MASK (0x1U) 2443 #define I2C_STAT_MSTPENDING_SHIFT (0U) 2444 /*! MSTPENDING - Master Pending. Indicates that the Master is waiting to continue communication on 2445 * the I2C-bus (pending) or is idle. When the master is pending, the MSTSTATE bits indicate what 2446 * type of software service if any the master expects. This flag will cause an interrupt when set 2447 * if, enabled via the INTENSET register. The MSTPENDING flag is not set when the DMA is handling 2448 * an event (if the MSTDMA bit in the MSTCTL register is set). If the master is in the idle 2449 * state, and no communication is needed, mask this interrupt. 2450 * 0b0..In progress. Communication is in progress and the Master function is busy and cannot currently accept a command. 2451 * 0b1..Pending. The Master function needs software service or is in the idle state. If the master is not in the 2452 * idle state, it is waiting to receive or transmit data or the NACK bit. 2453 */ 2454 #define I2C_STAT_MSTPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTPENDING_SHIFT)) & I2C_STAT_MSTPENDING_MASK) 2455 #define I2C_STAT_MSTSTATE_MASK (0xEU) 2456 #define I2C_STAT_MSTSTATE_SHIFT (1U) 2457 /*! MSTSTATE - Master State code. The master state code reflects the master state when the 2458 * MSTPENDING bit is set, that is the master is pending or in the idle state. Each value of this field 2459 * indicates a specific required service for the Master function. All other values are reserved. See 2460 * Table 400 for details of state values and appropriate responses. 2461 * 0b000..Idle. The Master function is available to be used for a new transaction. 2462 * 0b001..Receive ready. Received data available (Master Receiver mode). Address plus Read was previously sent and Acknowledged by slave. 2463 * 0b010..Transmit ready. Data can be transmitted (Master Transmitter mode). Address plus Write was previously sent and Acknowledged by slave. 2464 * 0b011..NACK Address. Slave NACKed address. 2465 * 0b100..NACK Data. Slave NACKed transmitted data. 2466 */ 2467 #define I2C_STAT_MSTSTATE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTSTATE_SHIFT)) & I2C_STAT_MSTSTATE_MASK) 2468 #define I2C_STAT_MSTARBLOSS_MASK (0x10U) 2469 #define I2C_STAT_MSTARBLOSS_SHIFT (4U) 2470 /*! MSTARBLOSS - Master Arbitration Loss flag. This flag can be cleared by software writing a 1 to 2471 * this bit. It is also cleared automatically a 1 is written to MSTCONTINUE. 2472 * 0b0..No Arbitration Loss has occurred. 2473 * 0b1..Arbitration loss. The Master function has experienced an Arbitration Loss. At this point, the Master 2474 * function has already stopped driving the bus and gone to an idle state. Software can respond by doing nothing, 2475 * or by sending a Start in order to attempt to gain control of the bus when it next becomes idle. 2476 */ 2477 #define I2C_STAT_MSTARBLOSS(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTARBLOSS_SHIFT)) & I2C_STAT_MSTARBLOSS_MASK) 2478 #define I2C_STAT_MSTSTSTPERR_MASK (0x40U) 2479 #define I2C_STAT_MSTSTSTPERR_SHIFT (6U) 2480 /*! MSTSTSTPERR - Master Start/Stop Error flag. This flag can be cleared by software writing a 1 to 2481 * this bit. It is also cleared automatically a 1 is written to MSTCONTINUE. 2482 * 0b0..No Start/Stop Error has occurred. 2483 * 0b1..The Master function has experienced a Start/Stop Error. A Start or Stop was detected at a time when it is 2484 * not allowed by the I2C specification. The Master interface has stopped driving the bus and gone to an 2485 * idle state, no action is required. A request for a Start could be made, or software could attempt to insure 2486 * that the bus has not stalled. 2487 */ 2488 #define I2C_STAT_MSTSTSTPERR(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTSTSTPERR_SHIFT)) & I2C_STAT_MSTSTSTPERR_MASK) 2489 #define I2C_STAT_SLVPENDING_MASK (0x100U) 2490 #define I2C_STAT_SLVPENDING_SHIFT (8U) 2491 /*! SLVPENDING - Slave Pending. Indicates that the Slave function is waiting to continue 2492 * communication on the I2C-bus and needs software service. This flag will cause an interrupt when set if 2493 * enabled via INTENSET. The SLVPENDING flag is not set when the DMA is handling an event (if the 2494 * SLVDMA bit in the SLVCTL register is set). The SLVPENDING flag is read-only and is 2495 * automatically cleared when a 1 is written to the SLVCONTINUE bit in the SLVCTL register. The point in time 2496 * when SlvPending is set depends on whether the I2C interface is in HSCAPABLE mode. See Section 2497 * 25.7.2.2.2. When the I2C interface is configured to be HSCAPABLE, HS master codes are 2498 * detected automatically. Due to the requirements of the HS I2C specification, slave addresses must 2499 * also be detected automatically, since the address must be acknowledged before the clock can be 2500 * stretched. 2501 * 0b0..In progress. The Slave function does not currently need service. 2502 * 0b1..Pending. The Slave function needs service. Information on what is needed can be found in the adjacent SLVSTATE field. 2503 */ 2504 #define I2C_STAT_SLVPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVPENDING_SHIFT)) & I2C_STAT_SLVPENDING_MASK) 2505 #define I2C_STAT_SLVSTATE_MASK (0x600U) 2506 #define I2C_STAT_SLVSTATE_SHIFT (9U) 2507 /*! SLVSTATE - Slave State code. Each value of this field indicates a specific required service for 2508 * the Slave function. All other values are reserved. See Table 401 for state values and actions. 2509 * note that the occurrence of some states and how they are handled are affected by DMA mode and 2510 * Automatic Operation modes. 2511 * 0b00..Slave address. Address plus R/W received. At least one of the four slave addresses has been matched by hardware. 2512 * 0b01..Slave receive. Received data is available (Slave Receiver mode). 2513 * 0b10..Slave transmit. Data can be transmitted (Slave Transmitter mode). 2514 */ 2515 #define I2C_STAT_SLVSTATE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVSTATE_SHIFT)) & I2C_STAT_SLVSTATE_MASK) 2516 #define I2C_STAT_SLVNOTSTR_MASK (0x800U) 2517 #define I2C_STAT_SLVNOTSTR_SHIFT (11U) 2518 /*! SLVNOTSTR - Slave Not Stretching. Indicates when the slave function is stretching the I2C clock. 2519 * This is needed in order to gracefully invoke Deep Sleep or Power-down modes during slave 2520 * operation. This read-only flag reflects the slave function status in real time. 2521 * 0b0..Stretching. The slave function is currently stretching the I2C bus clock. Deep-Sleep or Power-down mode cannot be entered at this time. 2522 * 0b1..Not stretching. The slave function is not currently stretching the I 2C bus clock. Deep-sleep or 2523 * Power-down mode could be entered at this time. 2524 */ 2525 #define I2C_STAT_SLVNOTSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVNOTSTR_SHIFT)) & I2C_STAT_SLVNOTSTR_MASK) 2526 #define I2C_STAT_SLVIDX_MASK (0x3000U) 2527 #define I2C_STAT_SLVIDX_SHIFT (12U) 2528 /*! SLVIDX - Slave address match Index. This field is valid when the I2C slave function has been 2529 * selected by receiving an address that matches one of the slave addresses defined by any enabled 2530 * slave address registers, and provides an identification of the address that was matched. It is 2531 * possible that more than one address could be matched, but only one match can be reported here. 2532 * 0b00..Address 0. Slave address 0 was matched. 2533 * 0b01..Address 1. Slave address 1 was matched. 2534 * 0b10..Address 2. Slave address 2 was matched. 2535 * 0b11..Address 3. Slave address 3 was matched. 2536 */ 2537 #define I2C_STAT_SLVIDX(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVIDX_SHIFT)) & I2C_STAT_SLVIDX_MASK) 2538 #define I2C_STAT_SLVSEL_MASK (0x4000U) 2539 #define I2C_STAT_SLVSEL_SHIFT (14U) 2540 /*! SLVSEL - Slave selected flag. SLVSEL is set after an address match when software tells the Slave 2541 * function to acknowledge the address, or when the address has been automatically acknowledged. 2542 * It is cleared when another address cycle presents an address that does not match an enabled 2543 * address on the Slave function, when slave software decides to NACK a matched address, when 2544 * there is a Stop detected on the bus, when the master NACKs slave data, and in some combinations of 2545 * Automatic Operation. SLVSEL is not cleared if software NACKs data. 2546 * 0b0..Not selected. The Slave function is not currently selected. 2547 * 0b1..Selected. The Slave function is currently selected. 2548 */ 2549 #define I2C_STAT_SLVSEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVSEL_SHIFT)) & I2C_STAT_SLVSEL_MASK) 2550 #define I2C_STAT_SLVDESEL_MASK (0x8000U) 2551 #define I2C_STAT_SLVDESEL_SHIFT (15U) 2552 /*! SLVDESEL - Slave Deselected flag. This flag will cause an interrupt when set if enabled via 2553 * INTENSET. This flag can be cleared by writing a 1 to this bit. 2554 * 0b0..Not deselected. The Slave function has not become deselected. This does not mean that it is currently 2555 * selected. That information can be found in the SLVSEL flag. 2556 * 0b1..Deselected. The Slave function has become deselected. This is specifically caused by the SLVSEL flag 2557 * changing from 1 to 0. See the description of SLVSEL for details on when that event occurs. 2558 */ 2559 #define I2C_STAT_SLVDESEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVDESEL_SHIFT)) & I2C_STAT_SLVDESEL_MASK) 2560 #define I2C_STAT_MONRDY_MASK (0x10000U) 2561 #define I2C_STAT_MONRDY_SHIFT (16U) 2562 /*! MONRDY - Monitor Ready. This flag is cleared when the MONRXDAT register is read. 2563 * 0b0..No data. The Monitor function does not currently have data available. 2564 * 0b1..Data waiting. The Monitor function has data waiting to be read. 2565 */ 2566 #define I2C_STAT_MONRDY(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONRDY_SHIFT)) & I2C_STAT_MONRDY_MASK) 2567 #define I2C_STAT_MONOV_MASK (0x20000U) 2568 #define I2C_STAT_MONOV_SHIFT (17U) 2569 /*! MONOV - Monitor Overflow flag. 2570 * 0b0..No overrun. Monitor data has not overrun. 2571 * 0b1..Overrun. A Monitor data overrun has occurred. This can only happen when Monitor clock stretching not 2572 * enabled via the MONCLKSTR bit in the CFG register. Writing 1 to this bit clears the flag. 2573 */ 2574 #define I2C_STAT_MONOV(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONOV_SHIFT)) & I2C_STAT_MONOV_MASK) 2575 #define I2C_STAT_MONACTIVE_MASK (0x40000U) 2576 #define I2C_STAT_MONACTIVE_SHIFT (18U) 2577 /*! MONACTIVE - Monitor Active flag. Indicates when the Monitor function considers the I 2C bus to 2578 * be active. Active is defined here as when some Master is on the bus: a bus Start has occurred 2579 * more recently than a bus Stop. 2580 * 0b0..Inactive. The Monitor function considers the I2C bus to be inactive. 2581 * 0b1..Active. The Monitor function considers the I2C bus to be active. 2582 */ 2583 #define I2C_STAT_MONACTIVE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONACTIVE_SHIFT)) & I2C_STAT_MONACTIVE_MASK) 2584 #define I2C_STAT_MONIDLE_MASK (0x80000U) 2585 #define I2C_STAT_MONIDLE_SHIFT (19U) 2586 /*! MONIDLE - Monitor Idle flag. This flag is set when the Monitor function sees the I2C bus change 2587 * from active to inactive. This can be used by software to decide when to process data 2588 * accumulated by the Monitor function. This flag will cause an interrupt when set if enabled via the 2589 * INTENSET register. The flag can be cleared by writing a 1 to this bit. 2590 * 0b0..Not idle. The I2C bus is not idle, or this flag has been cleared by software. 2591 * 0b1..Idle. The I2C bus has gone idle at least once since the last time this flag was cleared by software. 2592 */ 2593 #define I2C_STAT_MONIDLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONIDLE_SHIFT)) & I2C_STAT_MONIDLE_MASK) 2594 #define I2C_STAT_EVENTTIMEOUT_MASK (0x1000000U) 2595 #define I2C_STAT_EVENTTIMEOUT_SHIFT (24U) 2596 /*! EVENTTIMEOUT - Event Time-out Interrupt flag. Indicates when the time between events has been 2597 * longer than the time specified by the TIMEOUT register. Events include Start, Stop, and clock 2598 * edges. The flag is cleared by writing a 1 to this bit. No time-out is created when the I2C-bus 2599 * is idle. 2600 * 0b0..No time-out. I2C bus events have not caused a time-out. 2601 * 0b1..Event time-out. The time between I2C bus events has been longer than the time specified by the TIMEOUT register. 2602 */ 2603 #define I2C_STAT_EVENTTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_EVENTTIMEOUT_SHIFT)) & I2C_STAT_EVENTTIMEOUT_MASK) 2604 #define I2C_STAT_SCLTIMEOUT_MASK (0x2000000U) 2605 #define I2C_STAT_SCLTIMEOUT_SHIFT (25U) 2606 /*! SCLTIMEOUT - SCL Time-out Interrupt flag. Indicates when SCL has remained low longer than the 2607 * time specific by the TIMEOUT register. The flag is cleared by writing a 1 to this bit. 2608 * 0b0..No time-out. SCL low time has not caused a time-out. 2609 * 0b1..Time-out. SCL low time has caused a time-out. 2610 */ 2611 #define I2C_STAT_SCLTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SCLTIMEOUT_SHIFT)) & I2C_STAT_SCLTIMEOUT_MASK) 2612 /*! @} */ 2613 2614 /*! @name INTENSET - Interrupt Enable Set and read register. */ 2615 /*! @{ */ 2616 #define I2C_INTENSET_MSTPENDINGEN_MASK (0x1U) 2617 #define I2C_INTENSET_MSTPENDINGEN_SHIFT (0U) 2618 /*! MSTPENDINGEN - Master Pending interrupt Enable. 2619 * 0b0..Disabled. The MstPending interrupt is disabled. 2620 * 0b1..Enabled. The MstPending interrupt is enabled. 2621 */ 2622 #define I2C_INTENSET_MSTPENDINGEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTPENDINGEN_SHIFT)) & I2C_INTENSET_MSTPENDINGEN_MASK) 2623 #define I2C_INTENSET_MSTARBLOSSEN_MASK (0x10U) 2624 #define I2C_INTENSET_MSTARBLOSSEN_SHIFT (4U) 2625 /*! MSTARBLOSSEN - Master Arbitration Loss interrupt Enable. 2626 * 0b0..Disabled. The MstArbLoss interrupt is disabled. 2627 * 0b1..Enabled. The MstArbLoss interrupt is enabled. 2628 */ 2629 #define I2C_INTENSET_MSTARBLOSSEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTARBLOSSEN_SHIFT)) & I2C_INTENSET_MSTARBLOSSEN_MASK) 2630 #define I2C_INTENSET_MSTSTSTPERREN_MASK (0x40U) 2631 #define I2C_INTENSET_MSTSTSTPERREN_SHIFT (6U) 2632 /*! MSTSTSTPERREN - Master Start/Stop Error interrupt Enable. 2633 * 0b0..Disabled. The MstStStpErr interrupt is disabled. 2634 * 0b1..Enabled. The MstStStpErr interrupt is enabled. 2635 */ 2636 #define I2C_INTENSET_MSTSTSTPERREN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTSTSTPERREN_SHIFT)) & I2C_INTENSET_MSTSTSTPERREN_MASK) 2637 #define I2C_INTENSET_SLVPENDINGEN_MASK (0x100U) 2638 #define I2C_INTENSET_SLVPENDINGEN_SHIFT (8U) 2639 /*! SLVPENDINGEN - Slave Pending interrupt Enable. 2640 * 0b0..Disabled. The SlvPending interrupt is disabled. 2641 * 0b1..Enabled. The SlvPending interrupt is enabled. 2642 */ 2643 #define I2C_INTENSET_SLVPENDINGEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVPENDINGEN_SHIFT)) & I2C_INTENSET_SLVPENDINGEN_MASK) 2644 #define I2C_INTENSET_SLVNOTSTREN_MASK (0x800U) 2645 #define I2C_INTENSET_SLVNOTSTREN_SHIFT (11U) 2646 /*! SLVNOTSTREN - Slave Not Stretching interrupt Enable. 2647 * 0b0..Disabled. The SlvNotStr interrupt is disabled. 2648 * 0b1..Enabled. The SlvNotStr interrupt is enabled. 2649 */ 2650 #define I2C_INTENSET_SLVNOTSTREN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVNOTSTREN_SHIFT)) & I2C_INTENSET_SLVNOTSTREN_MASK) 2651 #define I2C_INTENSET_SLVDESELEN_MASK (0x8000U) 2652 #define I2C_INTENSET_SLVDESELEN_SHIFT (15U) 2653 /*! SLVDESELEN - Slave Deselect interrupt Enable. 2654 * 0b0..Disabled. The SlvDeSel interrupt is disabled. 2655 * 0b1..Enabled. The SlvDeSel interrupt is enabled. 2656 */ 2657 #define I2C_INTENSET_SLVDESELEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVDESELEN_SHIFT)) & I2C_INTENSET_SLVDESELEN_MASK) 2658 #define I2C_INTENSET_MONRDYEN_MASK (0x10000U) 2659 #define I2C_INTENSET_MONRDYEN_SHIFT (16U) 2660 /*! MONRDYEN - Monitor data Ready interrupt Enable. 2661 * 0b0..Disabled. The MonRdy interrupt is disabled. 2662 * 0b1..Enabled. The MonRdy interrupt is enabled. 2663 */ 2664 #define I2C_INTENSET_MONRDYEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONRDYEN_SHIFT)) & I2C_INTENSET_MONRDYEN_MASK) 2665 #define I2C_INTENSET_MONOVEN_MASK (0x20000U) 2666 #define I2C_INTENSET_MONOVEN_SHIFT (17U) 2667 /*! MONOVEN - Monitor Overrun interrupt Enable. 2668 * 0b0..Disabled. The MonOv interrupt is disabled. 2669 * 0b1..Enabled. The MonOv interrupt is enabled. 2670 */ 2671 #define I2C_INTENSET_MONOVEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONOVEN_SHIFT)) & I2C_INTENSET_MONOVEN_MASK) 2672 #define I2C_INTENSET_MONIDLEEN_MASK (0x80000U) 2673 #define I2C_INTENSET_MONIDLEEN_SHIFT (19U) 2674 /*! MONIDLEEN - Monitor Idle interrupt Enable. 2675 * 0b0..Disabled. The MonIdle interrupt is disabled. 2676 * 0b1..Enabled. The MonIdle interrupt is enabled. 2677 */ 2678 #define I2C_INTENSET_MONIDLEEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONIDLEEN_SHIFT)) & I2C_INTENSET_MONIDLEEN_MASK) 2679 #define I2C_INTENSET_EVENTTIMEOUTEN_MASK (0x1000000U) 2680 #define I2C_INTENSET_EVENTTIMEOUTEN_SHIFT (24U) 2681 /*! EVENTTIMEOUTEN - Event time-out interrupt Enable. 2682 * 0b0..Disabled. The Event time-out interrupt is disabled. 2683 * 0b1..Enabled. The Event time-out interrupt is enabled. 2684 */ 2685 #define I2C_INTENSET_EVENTTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_EVENTTIMEOUTEN_SHIFT)) & I2C_INTENSET_EVENTTIMEOUTEN_MASK) 2686 #define I2C_INTENSET_SCLTIMEOUTEN_MASK (0x2000000U) 2687 #define I2C_INTENSET_SCLTIMEOUTEN_SHIFT (25U) 2688 /*! SCLTIMEOUTEN - SCL time-out interrupt Enable. 2689 * 0b0..Disabled. The SCL time-out interrupt is disabled. 2690 * 0b1..Enabled. The SCL time-out interrupt is enabled. 2691 */ 2692 #define I2C_INTENSET_SCLTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SCLTIMEOUTEN_SHIFT)) & I2C_INTENSET_SCLTIMEOUTEN_MASK) 2693 /*! @} */ 2694 2695 /*! @name INTENCLR - Interrupt Enable Clear register. */ 2696 /*! @{ */ 2697 #define I2C_INTENCLR_MSTPENDINGCLR_MASK (0x1U) 2698 #define I2C_INTENCLR_MSTPENDINGCLR_SHIFT (0U) 2699 /*! MSTPENDINGCLR - Master Pending interrupt clear. Writing 1 to this bit clears the corresponding 2700 * bit in the INTENSET register if implemented. 2701 */ 2702 #define I2C_INTENCLR_MSTPENDINGCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTPENDINGCLR_SHIFT)) & I2C_INTENCLR_MSTPENDINGCLR_MASK) 2703 #define I2C_INTENCLR_MSTARBLOSSCLR_MASK (0x10U) 2704 #define I2C_INTENCLR_MSTARBLOSSCLR_SHIFT (4U) 2705 /*! MSTARBLOSSCLR - Master Arbitration Loss interrupt clear. 2706 */ 2707 #define I2C_INTENCLR_MSTARBLOSSCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTARBLOSSCLR_SHIFT)) & I2C_INTENCLR_MSTARBLOSSCLR_MASK) 2708 #define I2C_INTENCLR_MSTSTSTPERRCLR_MASK (0x40U) 2709 #define I2C_INTENCLR_MSTSTSTPERRCLR_SHIFT (6U) 2710 /*! MSTSTSTPERRCLR - Master Start/Stop Error interrupt clear. 2711 */ 2712 #define I2C_INTENCLR_MSTSTSTPERRCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTSTSTPERRCLR_SHIFT)) & I2C_INTENCLR_MSTSTSTPERRCLR_MASK) 2713 #define I2C_INTENCLR_SLVPENDINGCLR_MASK (0x100U) 2714 #define I2C_INTENCLR_SLVPENDINGCLR_SHIFT (8U) 2715 /*! SLVPENDINGCLR - Slave Pending interrupt clear. 2716 */ 2717 #define I2C_INTENCLR_SLVPENDINGCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVPENDINGCLR_SHIFT)) & I2C_INTENCLR_SLVPENDINGCLR_MASK) 2718 #define I2C_INTENCLR_SLVNOTSTRCLR_MASK (0x800U) 2719 #define I2C_INTENCLR_SLVNOTSTRCLR_SHIFT (11U) 2720 /*! SLVNOTSTRCLR - Slave Not Stretching interrupt clear. 2721 */ 2722 #define I2C_INTENCLR_SLVNOTSTRCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVNOTSTRCLR_SHIFT)) & I2C_INTENCLR_SLVNOTSTRCLR_MASK) 2723 #define I2C_INTENCLR_SLVDESELCLR_MASK (0x8000U) 2724 #define I2C_INTENCLR_SLVDESELCLR_SHIFT (15U) 2725 /*! SLVDESELCLR - Slave Deselect interrupt clear. 2726 */ 2727 #define I2C_INTENCLR_SLVDESELCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVDESELCLR_SHIFT)) & I2C_INTENCLR_SLVDESELCLR_MASK) 2728 #define I2C_INTENCLR_MONRDYCLR_MASK (0x10000U) 2729 #define I2C_INTENCLR_MONRDYCLR_SHIFT (16U) 2730 /*! MONRDYCLR - Monitor data Ready interrupt clear. 2731 */ 2732 #define I2C_INTENCLR_MONRDYCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONRDYCLR_SHIFT)) & I2C_INTENCLR_MONRDYCLR_MASK) 2733 #define I2C_INTENCLR_MONOVCLR_MASK (0x20000U) 2734 #define I2C_INTENCLR_MONOVCLR_SHIFT (17U) 2735 /*! MONOVCLR - Monitor Overrun interrupt clear. 2736 */ 2737 #define I2C_INTENCLR_MONOVCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONOVCLR_SHIFT)) & I2C_INTENCLR_MONOVCLR_MASK) 2738 #define I2C_INTENCLR_MONIDLECLR_MASK (0x80000U) 2739 #define I2C_INTENCLR_MONIDLECLR_SHIFT (19U) 2740 /*! MONIDLECLR - Monitor Idle interrupt clear. 2741 */ 2742 #define I2C_INTENCLR_MONIDLECLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONIDLECLR_SHIFT)) & I2C_INTENCLR_MONIDLECLR_MASK) 2743 #define I2C_INTENCLR_EVENTTIMEOUTCLR_MASK (0x1000000U) 2744 #define I2C_INTENCLR_EVENTTIMEOUTCLR_SHIFT (24U) 2745 /*! EVENTTIMEOUTCLR - Event time-out interrupt clear. 2746 */ 2747 #define I2C_INTENCLR_EVENTTIMEOUTCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_EVENTTIMEOUTCLR_SHIFT)) & I2C_INTENCLR_EVENTTIMEOUTCLR_MASK) 2748 #define I2C_INTENCLR_SCLTIMEOUTCLR_MASK (0x2000000U) 2749 #define I2C_INTENCLR_SCLTIMEOUTCLR_SHIFT (25U) 2750 /*! SCLTIMEOUTCLR - SCL time-out interrupt clear. 2751 */ 2752 #define I2C_INTENCLR_SCLTIMEOUTCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SCLTIMEOUTCLR_SHIFT)) & I2C_INTENCLR_SCLTIMEOUTCLR_MASK) 2753 /*! @} */ 2754 2755 /*! @name TIMEOUT - Time-out value register. */ 2756 /*! @{ */ 2757 #define I2C_TIMEOUT_TOMIN_MASK (0xFU) 2758 #define I2C_TIMEOUT_TOMIN_SHIFT (0U) 2759 /*! TOMIN - Time-out time value, bottom four bits. These are hard-wired to 0xF. This gives a minimum 2760 * time-out of 16 I2C function clocks and also a time-out resolution of 16 I2C function clocks. 2761 */ 2762 #define I2C_TIMEOUT_TOMIN(x) (((uint32_t)(((uint32_t)(x)) << I2C_TIMEOUT_TOMIN_SHIFT)) & I2C_TIMEOUT_TOMIN_MASK) 2763 #define I2C_TIMEOUT_TO_MASK (0xFFF0U) 2764 #define I2C_TIMEOUT_TO_SHIFT (4U) 2765 /*! TO - Time-out time value. Specifies the time-out interval value in increments of 16 I 2C 2766 * function clocks, as defined by the CLKDIV register. To change this value while I2C is in operation, 2767 * disable all time-outs, write a new value to TIMEOUT, then re-enable time-outs. 0x000 = A 2768 * time-out will occur after 16 counts of the I2C function clock. 0x001 = A time-out will occur after 2769 * 32 counts of the I2C function clock. 0xFFF = A time-out will occur after 65,536 counts of the 2770 * I2C function clock. 2771 */ 2772 #define I2C_TIMEOUT_TO(x) (((uint32_t)(((uint32_t)(x)) << I2C_TIMEOUT_TO_SHIFT)) & I2C_TIMEOUT_TO_MASK) 2773 /*! @} */ 2774 2775 /*! @name CLKDIV - Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register, and controls some timing of the Slave function. */ 2776 /*! @{ */ 2777 #define I2C_CLKDIV_DIVVAL_MASK (0xFFFFU) 2778 #define I2C_CLKDIV_DIVVAL_SHIFT (0U) 2779 /*! DIVVAL - This field controls how the Flexcomm clock (FCLK) is used by the I2C functions that 2780 * need an internal clock in order to operate. 0x0000 = FCLK is used directly by the I2C. 0x0001 = 2781 * FCLK is divided by 2 before use. 0x0002 = FCLK is divided by 3 before use. 0xFFFF = FCLK is 2782 * divided by 65,536 before use. 2783 */ 2784 #define I2C_CLKDIV_DIVVAL(x) (((uint32_t)(((uint32_t)(x)) << I2C_CLKDIV_DIVVAL_SHIFT)) & I2C_CLKDIV_DIVVAL_MASK) 2785 /*! @} */ 2786 2787 /*! @name INTSTAT - Interrupt Status register for Master, Slave, and Monitor functions. */ 2788 /*! @{ */ 2789 #define I2C_INTSTAT_MSTPENDING_MASK (0x1U) 2790 #define I2C_INTSTAT_MSTPENDING_SHIFT (0U) 2791 /*! MSTPENDING - Master Pending. 2792 */ 2793 #define I2C_INTSTAT_MSTPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTPENDING_SHIFT)) & I2C_INTSTAT_MSTPENDING_MASK) 2794 #define I2C_INTSTAT_MSTARBLOSS_MASK (0x10U) 2795 #define I2C_INTSTAT_MSTARBLOSS_SHIFT (4U) 2796 /*! MSTARBLOSS - Master Arbitration Loss flag. 2797 */ 2798 #define I2C_INTSTAT_MSTARBLOSS(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTARBLOSS_SHIFT)) & I2C_INTSTAT_MSTARBLOSS_MASK) 2799 #define I2C_INTSTAT_MSTSTSTPERR_MASK (0x40U) 2800 #define I2C_INTSTAT_MSTSTSTPERR_SHIFT (6U) 2801 /*! MSTSTSTPERR - Master Start/Stop Error flag. 2802 */ 2803 #define I2C_INTSTAT_MSTSTSTPERR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTSTSTPERR_SHIFT)) & I2C_INTSTAT_MSTSTSTPERR_MASK) 2804 #define I2C_INTSTAT_SLVPENDING_MASK (0x100U) 2805 #define I2C_INTSTAT_SLVPENDING_SHIFT (8U) 2806 /*! SLVPENDING - Slave Pending. 2807 */ 2808 #define I2C_INTSTAT_SLVPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVPENDING_SHIFT)) & I2C_INTSTAT_SLVPENDING_MASK) 2809 #define I2C_INTSTAT_SLVNOTSTR_MASK (0x800U) 2810 #define I2C_INTSTAT_SLVNOTSTR_SHIFT (11U) 2811 /*! SLVNOTSTR - Slave Not Stretching status. 2812 */ 2813 #define I2C_INTSTAT_SLVNOTSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVNOTSTR_SHIFT)) & I2C_INTSTAT_SLVNOTSTR_MASK) 2814 #define I2C_INTSTAT_SLVDESEL_MASK (0x8000U) 2815 #define I2C_INTSTAT_SLVDESEL_SHIFT (15U) 2816 /*! SLVDESEL - Slave Deselected flag. 2817 */ 2818 #define I2C_INTSTAT_SLVDESEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVDESEL_SHIFT)) & I2C_INTSTAT_SLVDESEL_MASK) 2819 #define I2C_INTSTAT_MONRDY_MASK (0x10000U) 2820 #define I2C_INTSTAT_MONRDY_SHIFT (16U) 2821 /*! MONRDY - Monitor Ready. 2822 */ 2823 #define I2C_INTSTAT_MONRDY(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONRDY_SHIFT)) & I2C_INTSTAT_MONRDY_MASK) 2824 #define I2C_INTSTAT_MONOV_MASK (0x20000U) 2825 #define I2C_INTSTAT_MONOV_SHIFT (17U) 2826 /*! MONOV - Monitor Overflow flag. 2827 */ 2828 #define I2C_INTSTAT_MONOV(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONOV_SHIFT)) & I2C_INTSTAT_MONOV_MASK) 2829 #define I2C_INTSTAT_MONIDLE_MASK (0x80000U) 2830 #define I2C_INTSTAT_MONIDLE_SHIFT (19U) 2831 /*! MONIDLE - Monitor Idle flag. 2832 */ 2833 #define I2C_INTSTAT_MONIDLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONIDLE_SHIFT)) & I2C_INTSTAT_MONIDLE_MASK) 2834 #define I2C_INTSTAT_EVENTTIMEOUT_MASK (0x1000000U) 2835 #define I2C_INTSTAT_EVENTTIMEOUT_SHIFT (24U) 2836 /*! EVENTTIMEOUT - Event time-out Interrupt flag. 2837 */ 2838 #define I2C_INTSTAT_EVENTTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_EVENTTIMEOUT_SHIFT)) & I2C_INTSTAT_EVENTTIMEOUT_MASK) 2839 #define I2C_INTSTAT_SCLTIMEOUT_MASK (0x2000000U) 2840 #define I2C_INTSTAT_SCLTIMEOUT_SHIFT (25U) 2841 /*! SCLTIMEOUT - SCL time-out Interrupt flag. 2842 */ 2843 #define I2C_INTSTAT_SCLTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SCLTIMEOUT_SHIFT)) & I2C_INTSTAT_SCLTIMEOUT_MASK) 2844 /*! @} */ 2845 2846 /*! @name MSTCTL - Master control register. */ 2847 /*! @{ */ 2848 #define I2C_MSTCTL_MSTCONTINUE_MASK (0x1U) 2849 #define I2C_MSTCTL_MSTCONTINUE_SHIFT (0U) 2850 /*! MSTCONTINUE - Master Continue. 2851 * 0b0..No effect. 2852 * 0b1..Informs the Master function to continue to the next operation. 2853 */ 2854 #define I2C_MSTCTL_MSTCONTINUE(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTCONTINUE_SHIFT)) & I2C_MSTCTL_MSTCONTINUE_MASK) 2855 #define I2C_MSTCTL_MSTSTART_MASK (0x2U) 2856 #define I2C_MSTCTL_MSTSTART_SHIFT (1U) 2857 /*! MSTSTART - Master Start control. 2858 * 0b0..No effect. 2859 * 0b1..Start. A Start will be generated on the I2C bus at the next allowed time. 2860 */ 2861 #define I2C_MSTCTL_MSTSTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTSTART_SHIFT)) & I2C_MSTCTL_MSTSTART_MASK) 2862 #define I2C_MSTCTL_MSTSTOP_MASK (0x4U) 2863 #define I2C_MSTCTL_MSTSTOP_SHIFT (2U) 2864 /*! MSTSTOP - Master Stop control. 2865 * 0b0..No effect. 2866 * 0b1..Stop. A Stop will be generated on the I2C bus at the next allowed time, preceded by a NACK to the slave 2867 * if the master is receiving data from the slave (Master Receiver mode). 2868 */ 2869 #define I2C_MSTCTL_MSTSTOP(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTSTOP_SHIFT)) & I2C_MSTCTL_MSTSTOP_MASK) 2870 /*! @} */ 2871 2872 /*! @name MSTTIME - Master timing configuration. */ 2873 /*! @{ */ 2874 #define I2C_MSTTIME_MSTSCLLOW_MASK (0x7U) 2875 #define I2C_MSTTIME_MSTSCLLOW_SHIFT (0U) 2876 /*! MSTSCLLOW - Master SCL Low time. Specifies the minimum low time that will be asserted by this 2877 * master on SCL. Other devices on the bus (masters or slaves) could lengthen this time. This 2878 * corresponds to the parameter t LOW in the I2C bus specification. I2C bus specification parameters 2879 * tBUF and tSU;STA have the same values and are also controlled by MSTSCLLOW. 2880 * 0b000..2 clocks. Minimum SCL low time is 2 clocks of the I2C clock pre-divider. 2881 * 0b001..3 clocks. Minimum SCL low time is 3 clocks of the I2C clock pre-divider. 2882 * 0b010..4 clocks. Minimum SCL low time is 4 clocks of the I2C clock pre-divider. 2883 * 0b011..5 clocks. Minimum SCL low time is 5 clocks of the I2C clock pre-divider. 2884 * 0b100..6 clocks. Minimum SCL low time is 6 clocks of the I2C clock pre-divider. 2885 * 0b101..7 clocks. Minimum SCL low time is 7 clocks of the I2C clock pre-divider. 2886 * 0b110..8 clocks. Minimum SCL low time is 8 clocks of the I2C clock pre-divider. 2887 * 0b111..9 clocks. Minimum SCL low time is 9 clocks of the I2C clock pre-divider. 2888 */ 2889 #define I2C_MSTTIME_MSTSCLLOW(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTTIME_MSTSCLLOW_SHIFT)) & I2C_MSTTIME_MSTSCLLOW_MASK) 2890 #define I2C_MSTTIME_MSTSCLHIGH_MASK (0x70U) 2891 #define I2C_MSTTIME_MSTSCLHIGH_SHIFT (4U) 2892 /*! MSTSCLHIGH - Master SCL High time. Specifies the minimum high time that will be asserted by this 2893 * master on SCL. Other masters in a multi-master system could shorten this time. This 2894 * corresponds to the parameter tHIGH in the I2C bus specification. I2C bus specification parameters 2895 * tSU;STO and tHD;STA have the same values and are also controlled by MSTSCLHIGH. 2896 * 0b000..2 clocks. Minimum SCL high time is 2 clock of the I2C clock pre-divider. 2897 * 0b001..3 clocks. Minimum SCL high time is 3 clocks of the I2C clock pre-divider . 2898 * 0b010..4 clocks. Minimum SCL high time is 4 clock of the I2C clock pre-divider. 2899 * 0b011..5 clocks. Minimum SCL high time is 5 clock of the I2C clock pre-divider. 2900 * 0b100..6 clocks. Minimum SCL high time is 6 clock of the I2C clock pre-divider. 2901 * 0b101..7 clocks. Minimum SCL high time is 7 clock of the I2C clock pre-divider. 2902 * 0b110..8 clocks. Minimum SCL high time is 8 clock of the I2C clock pre-divider. 2903 * 0b111..9 clocks. Minimum SCL high time is 9 clocks of the I2C clock pre-divider. 2904 */ 2905 #define I2C_MSTTIME_MSTSCLHIGH(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTTIME_MSTSCLHIGH_SHIFT)) & I2C_MSTTIME_MSTSCLHIGH_MASK) 2906 /*! @} */ 2907 2908 /*! @name MSTDAT - Combined Master receiver and transmitter data register. */ 2909 /*! @{ */ 2910 #define I2C_MSTDAT_DATA_MASK (0xFFU) 2911 #define I2C_MSTDAT_DATA_SHIFT (0U) 2912 /*! DATA - Master function data register. Read: read the most recently received data for the Master 2913 * function. Write: transmit data using the Master function. 2914 */ 2915 #define I2C_MSTDAT_DATA(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTDAT_DATA_SHIFT)) & I2C_MSTDAT_DATA_MASK) 2916 /*! @} */ 2917 2918 /*! @name SLVCTL - Slave control register. */ 2919 /*! @{ */ 2920 #define I2C_SLVCTL_SLVCONTINUE_MASK (0x1U) 2921 #define I2C_SLVCTL_SLVCONTINUE_SHIFT (0U) 2922 /*! SLVCONTINUE - Slave Continue. 2923 * 0b0..No effect. 2924 * 0b1..Informs the Slave function to continue to the next operation. 2925 */ 2926 #define I2C_SLVCTL_SLVCONTINUE(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVCONTINUE_SHIFT)) & I2C_SLVCTL_SLVCONTINUE_MASK) 2927 #define I2C_SLVCTL_SLVNACK_MASK (0x2U) 2928 #define I2C_SLVCTL_SLVNACK_SHIFT (1U) 2929 /*! SLVNACK - Slave NACK. 2930 * 0b0..No effect. 2931 * 0b1..NACK. Causes the Slave function to NACK the master when the slave is receiving data from the master (Slave Receiver mode). 2932 */ 2933 #define I2C_SLVCTL_SLVNACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVNACK_SHIFT)) & I2C_SLVCTL_SLVNACK_MASK) 2934 /*! @} */ 2935 2936 /*! @name SLVDAT - Combined Slave receiver and transmitter data register. */ 2937 /*! @{ */ 2938 #define I2C_SLVDAT_DATA_MASK (0xFFU) 2939 #define I2C_SLVDAT_DATA_SHIFT (0U) 2940 /*! DATA - Slave function data register. Read: read the most recently received data for the Slave 2941 * function. Write: transmit data using the Slave function. 2942 */ 2943 #define I2C_SLVDAT_DATA(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVDAT_DATA_SHIFT)) & I2C_SLVDAT_DATA_MASK) 2944 /*! @} */ 2945 2946 /*! @name SLVADR - Slave address register. */ 2947 /*! @{ */ 2948 #define I2C_SLVADR_SADISABLE_MASK (0x1U) 2949 #define I2C_SLVADR_SADISABLE_SHIFT (0U) 2950 /*! SADISABLE - Slave Address n Disable. 2951 * 0b0..Enabled. Slave Address n is enabled. 2952 * 0b1..Ignored Slave Address n is ignored. 2953 */ 2954 #define I2C_SLVADR_SADISABLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_SADISABLE_SHIFT)) & I2C_SLVADR_SADISABLE_MASK) 2955 #define I2C_SLVADR_SLVADR_MASK (0xFEU) 2956 #define I2C_SLVADR_SLVADR_SHIFT (1U) 2957 /*! SLVADR - Slave Address. Seven bit slave address that is compared to received addresses if enabled. 2958 */ 2959 #define I2C_SLVADR_SLVADR(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_SLVADR_SHIFT)) & I2C_SLVADR_SLVADR_MASK) 2960 /*! @} */ 2961 2962 /* The count of I2C_SLVADR */ 2963 #define I2C_SLVADR_COUNT (4U) 2964 2965 /*! @name SLVQUAL0 - Slave Qualification for address 0. */ 2966 /*! @{ */ 2967 #define I2C_SLVQUAL0_QUALMODE0_MASK (0x1U) 2968 #define I2C_SLVQUAL0_QUALMODE0_SHIFT (0U) 2969 /*! QUALMODE0 - Qualify mode for slave address 0. 2970 * 0b0..Mask. The SLVQUAL0 field is used as a logical mask for matching address 0. 2971 * 0b1..Extend. The SLVQUAL0 field is used to extend address 0 matching in a range of addresses. 2972 */ 2973 #define I2C_SLVQUAL0_QUALMODE0(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVQUAL0_QUALMODE0_SHIFT)) & I2C_SLVQUAL0_QUALMODE0_MASK) 2974 #define I2C_SLVQUAL0_SLVQUAL0_MASK (0xFEU) 2975 #define I2C_SLVQUAL0_SLVQUAL0_SHIFT (1U) 2976 /*! SLVQUAL0 - Slave address Qualifier for address 0. A value of 0 causes the address in SLVADR0 to 2977 * be used as-is, assuming that it is enabled. If QUALMODE0 = 0, any bit in this field which is 2978 * set to 1 will cause an automatic match of the corresponding bit of the received address when it 2979 * is compared to the SLVADR0 register. If QUALMODE0 = 1, an address range is matched for 2980 * address 0. This range extends from the value defined by SLVADR0 to the address defined by SLVQUAL0 2981 * (address matches when SLVADR0[7:1] <= received address <= SLVQUAL0[7:1]). 2982 */ 2983 #define I2C_SLVQUAL0_SLVQUAL0(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVQUAL0_SLVQUAL0_SHIFT)) & I2C_SLVQUAL0_SLVQUAL0_MASK) 2984 /*! @} */ 2985 2986 /*! @name MONRXDAT - Monitor receiver data register. */ 2987 /*! @{ */ 2988 #define I2C_MONRXDAT_MONRXDAT_MASK (0xFFU) 2989 #define I2C_MONRXDAT_MONRXDAT_SHIFT (0U) 2990 /*! MONRXDAT - Monitor function Receiver Data. This reflects every data byte that passes on the I2C pins. 2991 */ 2992 #define I2C_MONRXDAT_MONRXDAT(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONRXDAT_SHIFT)) & I2C_MONRXDAT_MONRXDAT_MASK) 2993 #define I2C_MONRXDAT_MONSTART_MASK (0x100U) 2994 #define I2C_MONRXDAT_MONSTART_SHIFT (8U) 2995 /*! MONSTART - Monitor Received Start. 2996 * 0b0..No start detected. The Monitor function has not detected a Start event on the I2C bus. 2997 * 0b1..Start detected. The Monitor function has detected a Start event on the I2C bus. 2998 */ 2999 #define I2C_MONRXDAT_MONSTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONSTART_SHIFT)) & I2C_MONRXDAT_MONSTART_MASK) 3000 #define I2C_MONRXDAT_MONRESTART_MASK (0x200U) 3001 #define I2C_MONRXDAT_MONRESTART_SHIFT (9U) 3002 /*! MONRESTART - Monitor Received Repeated Start. 3003 * 0b0..No repeated start detected. The Monitor function has not detected a Repeated Start event on the I2C bus. 3004 * 0b1..Repeated start detected. The Monitor function has detected a Repeated Start event on the I2C bus. 3005 */ 3006 #define I2C_MONRXDAT_MONRESTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONRESTART_SHIFT)) & I2C_MONRXDAT_MONRESTART_MASK) 3007 #define I2C_MONRXDAT_MONNACK_MASK (0x400U) 3008 #define I2C_MONRXDAT_MONNACK_SHIFT (10U) 3009 /*! MONNACK - Monitor Received NACK. 3010 * 0b0..Acknowledged. The data currently being provided by the Monitor function was acknowledged by at least one master or slave receiver. 3011 * 0b1..Not acknowledged. The data currently being provided by the Monitor function was not acknowledged by any receiver. 3012 */ 3013 #define I2C_MONRXDAT_MONNACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONNACK_SHIFT)) & I2C_MONRXDAT_MONNACK_MASK) 3014 /*! @} */ 3015 3016 3017 /*! 3018 * @} 3019 */ /* end of group I2C_Register_Masks */ 3020 3021 3022 /* I2C - Peripheral instance base addresses */ 3023 /** Peripheral I2C0 base address */ 3024 #define I2C0_BASE (0x40050000u) 3025 /** Peripheral I2C0 base pointer */ 3026 #define I2C0 ((I2C_Type *)I2C0_BASE) 3027 /** Peripheral I2C1 base address */ 3028 #define I2C1_BASE (0x40054000u) 3029 /** Peripheral I2C1 base pointer */ 3030 #define I2C1 ((I2C_Type *)I2C1_BASE) 3031 /** Array initializer of I2C peripheral base addresses */ 3032 #define I2C_BASE_ADDRS { I2C0_BASE, I2C1_BASE } 3033 /** Array initializer of I2C peripheral base pointers */ 3034 #define I2C_BASE_PTRS { I2C0, I2C1 } 3035 /** Interrupt vectors for the I2C peripheral type */ 3036 #define I2C_IRQS { I2C0_IRQn, I2C1_IRQn } 3037 3038 /*! 3039 * @} 3040 */ /* end of group I2C_Peripheral_Access_Layer */ 3041 3042 3043 /* ---------------------------------------------------------------------------- 3044 -- IOCON Peripheral Access Layer 3045 ---------------------------------------------------------------------------- */ 3046 3047 /*! 3048 * @addtogroup IOCON_Peripheral_Access_Layer IOCON Peripheral Access Layer 3049 * @{ 3050 */ 3051 3052 /** IOCON - Register Layout Typedef */ 3053 typedef struct { 3054 __IO uint32_t PIO[30]; /**< Digital I/O control for pins PIO0_17..Digital I/O control for pins PIO0_18, array offset: 0x0, array step: 0x4 */ 3055 } IOCON_Type; 3056 3057 /* ---------------------------------------------------------------------------- 3058 -- IOCON Register Masks 3059 ---------------------------------------------------------------------------- */ 3060 3061 /*! 3062 * @addtogroup IOCON_Register_Masks IOCON Register Masks 3063 * @{ 3064 */ 3065 3066 /*! @name PIO - Digital I/O control for pins PIO0_17..Digital I/O control for pins PIO0_18 */ 3067 /*! @{ */ 3068 #define IOCON_PIO_MODE_MASK (0x18U) 3069 #define IOCON_PIO_MODE_SHIFT (3U) 3070 /*! MODE - Selects function mode (on-chip pull-up/pull-down resistor control). 3071 * 0b00..Inactive. Inactive (no pull-down/pull-up resistor enabled). 3072 * 0b01..Pull-down. Pull-down resistor enabled. 3073 * 0b10..Pull-up. Pull-up resistor enabled. 3074 * 0b11..Repeater. Repeater mode. 3075 */ 3076 #define IOCON_PIO_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_MODE_SHIFT)) & IOCON_PIO_MODE_MASK) 3077 #define IOCON_PIO_HYS_MASK (0x20U) 3078 #define IOCON_PIO_HYS_SHIFT (5U) 3079 /*! HYS - Hysteresis. 3080 * 0b0..Disable 3081 * 0b1..Enable 3082 */ 3083 #define IOCON_PIO_HYS(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_HYS_SHIFT)) & IOCON_PIO_HYS_MASK) 3084 #define IOCON_PIO_INV_MASK (0x40U) 3085 #define IOCON_PIO_INV_SHIFT (6U) 3086 /*! INV - Invert input 3087 * 0b0..Input not inverted (HIGH on pin reads as 1; LOW on pin reads as 0). 3088 * 0b1..Input inverted (HIGH on pin reads as 0, LOW on pin reads as 1). 3089 */ 3090 #define IOCON_PIO_INV(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_INV_SHIFT)) & IOCON_PIO_INV_MASK) 3091 #define IOCON_PIO_OD_MASK (0x400U) 3092 #define IOCON_PIO_OD_SHIFT (10U) 3093 /*! OD - Open-drain mode. 3094 * 0b0..Disable. 3095 * 0b1..Open-drain mode enabled. Remark: This is not a true open-drain mode. 3096 */ 3097 #define IOCON_PIO_OD(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_OD_SHIFT)) & IOCON_PIO_OD_MASK) 3098 #define IOCON_PIO_DACMODE_MASK (0x10000U) 3099 #define IOCON_PIO_DACMODE_SHIFT (16U) 3100 /*! DACMODE - DAC mode enable. 3101 * 0b0..Disable. 3102 * 0b1..Enable. 3103 */ 3104 #define IOCON_PIO_DACMODE(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_DACMODE_SHIFT)) & IOCON_PIO_DACMODE_MASK) 3105 /*! @} */ 3106 3107 /* The count of IOCON_PIO */ 3108 #define IOCON_PIO_COUNT (30U) 3109 3110 3111 /*! 3112 * @} 3113 */ /* end of group IOCON_Register_Masks */ 3114 3115 3116 /* IOCON - Peripheral instance base addresses */ 3117 /** Peripheral IOCON base address */ 3118 #define IOCON_BASE (0x40044000u) 3119 /** Peripheral IOCON base pointer */ 3120 #define IOCON ((IOCON_Type *)IOCON_BASE) 3121 /** Array initializer of IOCON peripheral base addresses */ 3122 #define IOCON_BASE_ADDRS { IOCON_BASE } 3123 /** Array initializer of IOCON peripheral base pointers */ 3124 #define IOCON_BASE_PTRS { IOCON } 3125 3126 #define IOCON_INDEX_PIO0_17 ( 0) 3127 #define IOCON_INDEX_PIO0_13 ( 1) 3128 #define IOCON_INDEX_PIO0_12 ( 2) 3129 #define IOCON_INDEX_PIO0_5 ( 3) 3130 #define IOCON_INDEX_PIO0_4 ( 4) 3131 #define IOCON_INDEX_PIO0_3 ( 5) 3132 #define IOCON_INDEX_PIO0_2 ( 6) 3133 #define IOCON_INDEX_PIO0_11 ( 7) 3134 #define IOCON_INDEX_PIO0_10 ( 8) 3135 #define IOCON_INDEX_PIO0_16 ( 9) 3136 #define IOCON_INDEX_PIO0_15 (10) 3137 #define IOCON_INDEX_PIO0_1 (11) 3138 #define IOCON_INDEX_PIO0_21 (12) 3139 #define IOCON_INDEX_PIO0_9 (13) 3140 #define IOCON_INDEX_PIO0_8 (14) 3141 #define IOCON_INDEX_PIO0_7 (15) 3142 #define IOCON_INDEX_PIO0_29 (16) 3143 #define IOCON_INDEX_PIO0_0 (17) 3144 #define IOCON_INDEX_PIO0_14 (18) 3145 #define IOCON_INDEX_PIO0_28 (19) 3146 #define IOCON_INDEX_PIO0_27 (20) 3147 #define IOCON_INDEX_PIO0_26 (21) 3148 #define IOCON_INDEX_PIO0_20 (22) 3149 #define IOCON_INDEX_PIO0_30 (23) 3150 #define IOCON_INDEX_PIO0_19 (24) 3151 #define IOCON_INDEX_PIO0_25 (25) 3152 #define IOCON_INDEX_PIO0_24 (26) 3153 #define IOCON_INDEX_PIO0_23 (27) 3154 #define IOCON_INDEX_PIO0_22 (28) 3155 #define IOCON_INDEX_PIO0_18 (29) 3156 3157 3158 /*! 3159 * @} 3160 */ /* end of group IOCON_Peripheral_Access_Layer */ 3161 3162 3163 /* ---------------------------------------------------------------------------- 3164 -- MRT Peripheral Access Layer 3165 ---------------------------------------------------------------------------- */ 3166 3167 /*! 3168 * @addtogroup MRT_Peripheral_Access_Layer MRT Peripheral Access Layer 3169 * @{ 3170 */ 3171 3172 /** MRT - Register Layout Typedef */ 3173 typedef struct { 3174 struct { /* offset: 0x0, array step: 0x10 */ 3175 __IO uint32_t INTVAL; /**< MRT Time interval value register. This value is loaded into the TIMER register., array offset: 0x0, array step: 0x10 */ 3176 __I uint32_t TIMER; /**< MRT Timer register. This register reads the value of the down-counter., array offset: 0x4, array step: 0x10 */ 3177 __IO uint32_t CTRL; /**< MRT Control register. This register controls the MRT modes., array offset: 0x8, array step: 0x10 */ 3178 __IO uint32_t STAT; /**< MRT Status register., array offset: 0xC, array step: 0x10 */ 3179 } CHANNEL[4]; 3180 uint8_t RESERVED_0[176]; 3181 __I uint32_t MODCFG; /**< Module Configuration register. This register provides information about this particular MRT instance., offset: 0xF0 */ 3182 __I uint32_t IDLE_CH; /**< Idle channel register. This register returns the number of the first idle channel., offset: 0xF4 */ 3183 __IO uint32_t IRQ_FLAG; /**< Global interrupt flag register, offset: 0xF8 */ 3184 } MRT_Type; 3185 3186 /* ---------------------------------------------------------------------------- 3187 -- MRT Register Masks 3188 ---------------------------------------------------------------------------- */ 3189 3190 /*! 3191 * @addtogroup MRT_Register_Masks MRT Register Masks 3192 * @{ 3193 */ 3194 3195 /*! @name CHANNEL_INTVAL - MRT Time interval value register. This value is loaded into the TIMER register. */ 3196 /*! @{ */ 3197 #define MRT_CHANNEL_INTVAL_IVALUE_MASK (0x7FFFFFFFU) 3198 #define MRT_CHANNEL_INTVAL_IVALUE_SHIFT (0U) 3199 /*! IVALUE - Time interval load value. This value is loaded into the TIMERn register and the MRT 3200 * channel n starts counting down from IVALUE -1. If the timer is idle, writing a non-zero value to 3201 * this bit field starts the timer immediately. If the timer is running, writing a zero to this 3202 * bit field does the following: If LOAD = 1, the timer stops immediately. If LOAD = 0, the timer 3203 * stops at the end of the time interval. 3204 */ 3205 #define MRT_CHANNEL_INTVAL_IVALUE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_INTVAL_IVALUE_SHIFT)) & MRT_CHANNEL_INTVAL_IVALUE_MASK) 3206 #define MRT_CHANNEL_INTVAL_LOAD_MASK (0x80000000U) 3207 #define MRT_CHANNEL_INTVAL_LOAD_SHIFT (31U) 3208 /*! LOAD - Determines how the timer interval value IVALUE -1 is loaded into the TIMERn register. 3209 * This bit is write-only. Reading this bit always returns 0. 3210 * 0b0..No force load. The load from the INTVALn register to the TIMERn register is processed at the end of the 3211 * time interval if the repeat mode is selected. 3212 * 0b1..Force load. The INTVALn interval value IVALUE -1 is immediately loaded into the TIMERn register while TIMERn is running. 3213 */ 3214 #define MRT_CHANNEL_INTVAL_LOAD(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_INTVAL_LOAD_SHIFT)) & MRT_CHANNEL_INTVAL_LOAD_MASK) 3215 /*! @} */ 3216 3217 /* The count of MRT_CHANNEL_INTVAL */ 3218 #define MRT_CHANNEL_INTVAL_COUNT (4U) 3219 3220 /*! @name CHANNEL_TIMER - MRT Timer register. This register reads the value of the down-counter. */ 3221 /*! @{ */ 3222 #define MRT_CHANNEL_TIMER_VALUE_MASK (0x7FFFFFFFU) 3223 #define MRT_CHANNEL_TIMER_VALUE_SHIFT (0U) 3224 /*! VALUE - Holds the current timer value of the down-counter. The initial value of the TIMERn 3225 * register is loaded as IVALUE - 1 from the INTVALn register either at the end of the time interval 3226 * or immediately in the following cases: INTVALn register is updated in the idle state. INTVALn 3227 * register is updated with LOAD = 1. When the timer is in idle state, reading this bit fields 3228 * returns -1 (0x00FF FFFF). 3229 */ 3230 #define MRT_CHANNEL_TIMER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_TIMER_VALUE_SHIFT)) & MRT_CHANNEL_TIMER_VALUE_MASK) 3231 /*! @} */ 3232 3233 /* The count of MRT_CHANNEL_TIMER */ 3234 #define MRT_CHANNEL_TIMER_COUNT (4U) 3235 3236 /*! @name CHANNEL_CTRL - MRT Control register. This register controls the MRT modes. */ 3237 /*! @{ */ 3238 #define MRT_CHANNEL_CTRL_INTEN_MASK (0x1U) 3239 #define MRT_CHANNEL_CTRL_INTEN_SHIFT (0U) 3240 /*! INTEN - Enable the TIMERn interrupt. 3241 * 0b0..Disabled. TIMERn interrupt is disabled. 3242 * 0b1..Enabled. TIMERn interrupt is enabled. 3243 */ 3244 #define MRT_CHANNEL_CTRL_INTEN(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_CTRL_INTEN_SHIFT)) & MRT_CHANNEL_CTRL_INTEN_MASK) 3245 #define MRT_CHANNEL_CTRL_MODE_MASK (0x6U) 3246 #define MRT_CHANNEL_CTRL_MODE_SHIFT (1U) 3247 /*! MODE - Selects timer mode. 3248 * 0b00..Repeat interrupt mode. 3249 * 0b01..One-shot interrupt mode. 3250 * 0b10..One-shot stall mode. 3251 * 0b11..Reserved. 3252 */ 3253 #define MRT_CHANNEL_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_CTRL_MODE_SHIFT)) & MRT_CHANNEL_CTRL_MODE_MASK) 3254 /*! @} */ 3255 3256 /* The count of MRT_CHANNEL_CTRL */ 3257 #define MRT_CHANNEL_CTRL_COUNT (4U) 3258 3259 /*! @name CHANNEL_STAT - MRT Status register. */ 3260 /*! @{ */ 3261 #define MRT_CHANNEL_STAT_INTFLAG_MASK (0x1U) 3262 #define MRT_CHANNEL_STAT_INTFLAG_SHIFT (0U) 3263 /*! INTFLAG - Monitors the interrupt flag. 3264 * 0b0..No pending interrupt. Writing a zero is equivalent to no operation. 3265 * 0b1..Pending interrupt. The interrupt is pending because TIMERn has reached the end of the time interval. If 3266 * the INTEN bit in the CONTROLn is also set to 1, the interrupt for timer channel n and the global interrupt 3267 * are raised. Writing a 1 to this bit clears the interrupt request. 3268 */ 3269 #define MRT_CHANNEL_STAT_INTFLAG(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_INTFLAG_SHIFT)) & MRT_CHANNEL_STAT_INTFLAG_MASK) 3270 #define MRT_CHANNEL_STAT_RUN_MASK (0x2U) 3271 #define MRT_CHANNEL_STAT_RUN_SHIFT (1U) 3272 /*! RUN - Indicates the state of TIMERn. This bit is read-only. 3273 * 0b0..Idle state. TIMERn is stopped. 3274 * 0b1..Running. TIMERn is running. 3275 */ 3276 #define MRT_CHANNEL_STAT_RUN(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_RUN_SHIFT)) & MRT_CHANNEL_STAT_RUN_MASK) 3277 /*! @} */ 3278 3279 /* The count of MRT_CHANNEL_STAT */ 3280 #define MRT_CHANNEL_STAT_COUNT (4U) 3281 3282 /*! @name MODCFG - Module Configuration register. This register provides information about this particular MRT instance. */ 3283 /*! @{ */ 3284 #define MRT_MODCFG_NOC_MASK (0xFU) 3285 #define MRT_MODCFG_NOC_SHIFT (0U) 3286 /*! NOC - Identifies the number of channels in this MRT.(4 channels on this device.) 3287 */ 3288 #define MRT_MODCFG_NOC(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_NOC_SHIFT)) & MRT_MODCFG_NOC_MASK) 3289 #define MRT_MODCFG_NOB_MASK (0x1F0U) 3290 #define MRT_MODCFG_NOB_SHIFT (4U) 3291 /*! NOB - Identifies the number of timer bits in this MRT. (31 bits wide on this device.) 3292 */ 3293 #define MRT_MODCFG_NOB(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_NOB_SHIFT)) & MRT_MODCFG_NOB_MASK) 3294 /*! @} */ 3295 3296 /*! @name IDLE_CH - Idle channel register. This register returns the number of the first idle channel. */ 3297 /*! @{ */ 3298 #define MRT_IDLE_CH_CHAN_MASK (0xF0U) 3299 #define MRT_IDLE_CH_CHAN_SHIFT (4U) 3300 /*! CHAN - Idle channel. Reading the CHAN bits, returns the lowest idle timer channel. The number is 3301 * positioned such that it can be used as an offset from the MRT base address in order to access 3302 * the registers for the allocated channel. If all timer channels are running, CHAN = 0xF. See 3303 * text above for more details. 3304 */ 3305 #define MRT_IDLE_CH_CHAN(x) (((uint32_t)(((uint32_t)(x)) << MRT_IDLE_CH_CHAN_SHIFT)) & MRT_IDLE_CH_CHAN_MASK) 3306 /*! @} */ 3307 3308 /*! @name IRQ_FLAG - Global interrupt flag register */ 3309 /*! @{ */ 3310 #define MRT_IRQ_FLAG_GFLAG0_MASK (0x1U) 3311 #define MRT_IRQ_FLAG_GFLAG0_SHIFT (0U) 3312 /*! GFLAG0 - Monitors the interrupt flag of TIMER0. 3313 * 0b0..No pending interrupt. Writing a zero is equivalent to no operation. 3314 * 0b1..Pending interrupt. The interrupt is pending because TIMER0 has reached the end of the time interval. If 3315 * the INTEN bit in the CONTROL0 register is also set to 1, the interrupt for timer channel 0 and the global 3316 * interrupt are raised. Writing a 1 to this bit clears the interrupt request. 3317 */ 3318 #define MRT_IRQ_FLAG_GFLAG0(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG0_SHIFT)) & MRT_IRQ_FLAG_GFLAG0_MASK) 3319 #define MRT_IRQ_FLAG_GFLAG1_MASK (0x2U) 3320 #define MRT_IRQ_FLAG_GFLAG1_SHIFT (1U) 3321 /*! GFLAG1 - Monitors the interrupt flag of TIMER1. See description of channel 0. 3322 */ 3323 #define MRT_IRQ_FLAG_GFLAG1(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG1_SHIFT)) & MRT_IRQ_FLAG_GFLAG1_MASK) 3324 /*! @} */ 3325 3326 3327 /*! 3328 * @} 3329 */ /* end of group MRT_Register_Masks */ 3330 3331 3332 /* MRT - Peripheral instance base addresses */ 3333 /** Peripheral MRT0 base address */ 3334 #define MRT0_BASE (0x40004000u) 3335 /** Peripheral MRT0 base pointer */ 3336 #define MRT0 ((MRT_Type *)MRT0_BASE) 3337 /** Array initializer of MRT peripheral base addresses */ 3338 #define MRT_BASE_ADDRS { MRT0_BASE } 3339 /** Array initializer of MRT peripheral base pointers */ 3340 #define MRT_BASE_PTRS { MRT0 } 3341 /** Interrupt vectors for the MRT peripheral type */ 3342 #define MRT_IRQS { MRT0_IRQn } 3343 3344 /*! 3345 * @} 3346 */ /* end of group MRT_Peripheral_Access_Layer */ 3347 3348 3349 /* ---------------------------------------------------------------------------- 3350 -- PINT Peripheral Access Layer 3351 ---------------------------------------------------------------------------- */ 3352 3353 /*! 3354 * @addtogroup PINT_Peripheral_Access_Layer PINT Peripheral Access Layer 3355 * @{ 3356 */ 3357 3358 /** PINT - Register Layout Typedef */ 3359 typedef struct { 3360 __IO uint32_t ISEL; /**< Pin Interrupt Mode register, offset: 0x0 */ 3361 __IO uint32_t IENR; /**< Pin interrupt level or rising edge interrupt enable register, offset: 0x4 */ 3362 __O uint32_t SIENR; /**< Pin interrupt level or rising edge interrupt set register, offset: 0x8 */ 3363 __O uint32_t CIENR; /**< Pin interrupt level (rising edge interrupt) clear register, offset: 0xC */ 3364 __IO uint32_t IENF; /**< Pin interrupt active level or falling edge interrupt enable register, offset: 0x10 */ 3365 __O uint32_t SIENF; /**< Pin interrupt active level or falling edge interrupt set register, offset: 0x14 */ 3366 __O uint32_t CIENF; /**< Pin interrupt active level or falling edge interrupt clear register, offset: 0x18 */ 3367 __IO uint32_t RISE; /**< Pin interrupt rising edge register, offset: 0x1C */ 3368 __IO uint32_t FALL; /**< Pin interrupt falling edge register, offset: 0x20 */ 3369 __IO uint32_t IST; /**< Pin interrupt status register, offset: 0x24 */ 3370 __IO uint32_t PMCTRL; /**< Pattern match interrupt control register, offset: 0x28 */ 3371 __IO uint32_t PMSRC; /**< Pattern match interrupt bit-slice source register, offset: 0x2C */ 3372 __IO uint32_t PMCFG; /**< Pattern match interrupt bit slice configuration register, offset: 0x30 */ 3373 } PINT_Type; 3374 3375 /* ---------------------------------------------------------------------------- 3376 -- PINT Register Masks 3377 ---------------------------------------------------------------------------- */ 3378 3379 /*! 3380 * @addtogroup PINT_Register_Masks PINT Register Masks 3381 * @{ 3382 */ 3383 3384 /*! @name ISEL - Pin Interrupt Mode register */ 3385 /*! @{ */ 3386 #define PINT_ISEL_PMODE_MASK (0xFFU) 3387 #define PINT_ISEL_PMODE_SHIFT (0U) 3388 /*! PMODE - Selects the interrupt mode for each pin interrupt. Bit n configures the pin interrupt 3389 * selected in PINTSELn. 0 = Edge sensitive 1 = Level sensitive 3390 */ 3391 #define PINT_ISEL_PMODE(x) (((uint32_t)(((uint32_t)(x)) << PINT_ISEL_PMODE_SHIFT)) & PINT_ISEL_PMODE_MASK) 3392 /*! @} */ 3393 3394 /*! @name IENR - Pin interrupt level or rising edge interrupt enable register */ 3395 /*! @{ */ 3396 #define PINT_IENR_ENRL_MASK (0xFFU) 3397 #define PINT_IENR_ENRL_SHIFT (0U) 3398 /*! ENRL - Enables the rising edge or level interrupt for each pin interrupt. Bit n configures the 3399 * pin interrupt selected in PINTSELn. 0 = Disable rising edge or level interrupt. 1 = Enable 3400 * rising edge or level interrupt. 3401 */ 3402 #define PINT_IENR_ENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_IENR_ENRL_SHIFT)) & PINT_IENR_ENRL_MASK) 3403 /*! @} */ 3404 3405 /*! @name SIENR - Pin interrupt level or rising edge interrupt set register */ 3406 /*! @{ */ 3407 #define PINT_SIENR_SETENRL_MASK (0xFFU) 3408 #define PINT_SIENR_SETENRL_SHIFT (0U) 3409 /*! SETENRL - Ones written to this address set bits in the IENR, thus enabling interrupts. Bit n 3410 * sets bit n in the IENR register. 0 = No operation. 1 = Enable rising edge or level interrupt. 3411 */ 3412 #define PINT_SIENR_SETENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_SIENR_SETENRL_SHIFT)) & PINT_SIENR_SETENRL_MASK) 3413 /*! @} */ 3414 3415 /*! @name CIENR - Pin interrupt level (rising edge interrupt) clear register */ 3416 /*! @{ */ 3417 #define PINT_CIENR_CENRL_MASK (0xFFU) 3418 #define PINT_CIENR_CENRL_SHIFT (0U) 3419 /*! CENRL - Ones written to this address clear bits in the IENR, thus disabling the interrupts. Bit 3420 * n clears bit n in the IENR register. 0 = No operation. 1 = Disable rising edge or level 3421 * interrupt. 3422 */ 3423 #define PINT_CIENR_CENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_CIENR_CENRL_SHIFT)) & PINT_CIENR_CENRL_MASK) 3424 /*! @} */ 3425 3426 /*! @name IENF - Pin interrupt active level or falling edge interrupt enable register */ 3427 /*! @{ */ 3428 #define PINT_IENF_ENAF_MASK (0xFFU) 3429 #define PINT_IENF_ENAF_SHIFT (0U) 3430 /*! ENAF - Enables the falling edge or configures the active level interrupt for each pin interrupt. 3431 * Bit n configures the pin interrupt selected in PINTSELn. 0 = Disable falling edge interrupt 3432 * or set active interrupt level LOW. 1 = Enable falling edge interrupt enabled or set active 3433 * interrupt level HIGH. 3434 */ 3435 #define PINT_IENF_ENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_IENF_ENAF_SHIFT)) & PINT_IENF_ENAF_MASK) 3436 /*! @} */ 3437 3438 /*! @name SIENF - Pin interrupt active level or falling edge interrupt set register */ 3439 /*! @{ */ 3440 #define PINT_SIENF_SETENAF_MASK (0xFFU) 3441 #define PINT_SIENF_SETENAF_SHIFT (0U) 3442 /*! SETENAF - Ones written to this address set bits in the IENF, thus enabling interrupts. Bit n 3443 * sets bit n in the IENF register. 0 = No operation. 1 = Select HIGH-active interrupt or enable 3444 * falling edge interrupt. 3445 */ 3446 #define PINT_SIENF_SETENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_SIENF_SETENAF_SHIFT)) & PINT_SIENF_SETENAF_MASK) 3447 /*! @} */ 3448 3449 /*! @name CIENF - Pin interrupt active level or falling edge interrupt clear register */ 3450 /*! @{ */ 3451 #define PINT_CIENF_CENAF_MASK (0xFFU) 3452 #define PINT_CIENF_CENAF_SHIFT (0U) 3453 /*! CENAF - Ones written to this address clears bits in the IENF, thus disabling interrupts. Bit n 3454 * clears bit n in the IENF register. 0 = No operation. 1 = LOW-active interrupt selected or 3455 * falling edge interrupt disabled. 3456 */ 3457 #define PINT_CIENF_CENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_CIENF_CENAF_SHIFT)) & PINT_CIENF_CENAF_MASK) 3458 /*! @} */ 3459 3460 /*! @name RISE - Pin interrupt rising edge register */ 3461 /*! @{ */ 3462 #define PINT_RISE_RDET_MASK (0xFFU) 3463 #define PINT_RISE_RDET_SHIFT (0U) 3464 /*! RDET - Rising edge detect. Bit n detects the rising edge of the pin selected in PINTSELn. Read 3465 * 0: No rising edge has been detected on this pin since Reset or the last time a one was written 3466 * to this bit. Write 0: no operation. Read 1: a rising edge has been detected since Reset or the 3467 * last time a one was written to this bit. Write 1: clear rising edge detection for this pin. 3468 */ 3469 #define PINT_RISE_RDET(x) (((uint32_t)(((uint32_t)(x)) << PINT_RISE_RDET_SHIFT)) & PINT_RISE_RDET_MASK) 3470 /*! @} */ 3471 3472 /*! @name FALL - Pin interrupt falling edge register */ 3473 /*! @{ */ 3474 #define PINT_FALL_FDET_MASK (0xFFU) 3475 #define PINT_FALL_FDET_SHIFT (0U) 3476 /*! FDET - Falling edge detect. Bit n detects the falling edge of the pin selected in PINTSELn. Read 3477 * 0: No falling edge has been detected on this pin since Reset or the last time a one was 3478 * written to this bit. Write 0: no operation. Read 1: a falling edge has been detected since Reset or 3479 * the last time a one was written to this bit. Write 1: clear falling edge detection for this 3480 * pin. 3481 */ 3482 #define PINT_FALL_FDET(x) (((uint32_t)(((uint32_t)(x)) << PINT_FALL_FDET_SHIFT)) & PINT_FALL_FDET_MASK) 3483 /*! @} */ 3484 3485 /*! @name IST - Pin interrupt status register */ 3486 /*! @{ */ 3487 #define PINT_IST_PSTAT_MASK (0xFFU) 3488 #define PINT_IST_PSTAT_SHIFT (0U) 3489 /*! PSTAT - Pin interrupt status. Bit n returns the status, clears the edge interrupt, or inverts 3490 * the active level of the pin selected in PINTSELn. Read 0: interrupt is not being requested for 3491 * this interrupt pin. Write 0: no operation. Read 1: interrupt is being requested for this 3492 * interrupt pin. Write 1 (edge-sensitive): clear rising- and falling-edge detection for this pin. 3493 * Write 1 (level-sensitive): switch the active level for this pin (in the IENF register). 3494 */ 3495 #define PINT_IST_PSTAT(x) (((uint32_t)(((uint32_t)(x)) << PINT_IST_PSTAT_SHIFT)) & PINT_IST_PSTAT_MASK) 3496 /*! @} */ 3497 3498 /*! @name PMCTRL - Pattern match interrupt control register */ 3499 /*! @{ */ 3500 #define PINT_PMCTRL_SEL_PMATCH_MASK (0x1U) 3501 #define PINT_PMCTRL_SEL_PMATCH_SHIFT (0U) 3502 /*! SEL_PMATCH - Specifies whether the 8 pin interrupts are controlled by the pin interrupt function or by the pattern match function. 3503 * 0b0..Pin interrupt. Interrupts are driven in response to the standard pin interrupt function. 3504 * 0b1..Pattern match. Interrupts are driven in response to pattern matches. 3505 */ 3506 #define PINT_PMCTRL_SEL_PMATCH(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_SEL_PMATCH_SHIFT)) & PINT_PMCTRL_SEL_PMATCH_MASK) 3507 #define PINT_PMCTRL_ENA_RXEV_MASK (0x2U) 3508 #define PINT_PMCTRL_ENA_RXEV_SHIFT (1U) 3509 /*! ENA_RXEV - Enables the RXEV output to the CPU and/or to a GPIO output when the specified boolean expression evaluates to true. 3510 * 0b0..Disabled. RXEV output to the CPU is disabled. 3511 * 0b1..Enabled. RXEV output to the CPU is enabled. 3512 */ 3513 #define PINT_PMCTRL_ENA_RXEV(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_ENA_RXEV_SHIFT)) & PINT_PMCTRL_ENA_RXEV_MASK) 3514 #define PINT_PMCTRL_PMAT_MASK (0xFF000000U) 3515 #define PINT_PMCTRL_PMAT_SHIFT (24U) 3516 /*! PMAT - This field displays the current state of pattern matches. A 1 in any bit of this field 3517 * indicates that the corresponding product term is matched by the current state of the appropriate 3518 * inputs. 3519 */ 3520 #define PINT_PMCTRL_PMAT(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_PMAT_SHIFT)) & PINT_PMCTRL_PMAT_MASK) 3521 /*! @} */ 3522 3523 /*! @name PMSRC - Pattern match interrupt bit-slice source register */ 3524 /*! @{ */ 3525 #define PINT_PMSRC_SRC0_MASK (0x700U) 3526 #define PINT_PMSRC_SRC0_SHIFT (8U) 3527 /*! SRC0 - Selects the input source for bit slice 0 3528 * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 0. 3529 * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 0. 3530 * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 0. 3531 * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 0. 3532 * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 0. 3533 * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 0. 3534 * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 0. 3535 * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 0. 3536 */ 3537 #define PINT_PMSRC_SRC0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC0_SHIFT)) & PINT_PMSRC_SRC0_MASK) 3538 #define PINT_PMSRC_SRC1_MASK (0x3800U) 3539 #define PINT_PMSRC_SRC1_SHIFT (11U) 3540 /*! SRC1 - Selects the input source for bit slice 1 3541 * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 1. 3542 * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 1. 3543 * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 1. 3544 * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 1. 3545 * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 1. 3546 * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 1. 3547 * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 1. 3548 * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 1. 3549 */ 3550 #define PINT_PMSRC_SRC1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC1_SHIFT)) & PINT_PMSRC_SRC1_MASK) 3551 #define PINT_PMSRC_SRC2_MASK (0x1C000U) 3552 #define PINT_PMSRC_SRC2_SHIFT (14U) 3553 /*! SRC2 - Selects the input source for bit slice 2 3554 * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 2. 3555 * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 2. 3556 * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 2. 3557 * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 2. 3558 * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 2. 3559 * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 2. 3560 * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 2. 3561 * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 2. 3562 */ 3563 #define PINT_PMSRC_SRC2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC2_SHIFT)) & PINT_PMSRC_SRC2_MASK) 3564 #define PINT_PMSRC_SRC3_MASK (0xE0000U) 3565 #define PINT_PMSRC_SRC3_SHIFT (17U) 3566 /*! SRC3 - Selects the input source for bit slice 3 3567 * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 3. 3568 * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 3. 3569 * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 3. 3570 * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 3. 3571 * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 3. 3572 * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 3. 3573 * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 3. 3574 * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 3. 3575 */ 3576 #define PINT_PMSRC_SRC3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC3_SHIFT)) & PINT_PMSRC_SRC3_MASK) 3577 #define PINT_PMSRC_SRC4_MASK (0x700000U) 3578 #define PINT_PMSRC_SRC4_SHIFT (20U) 3579 /*! SRC4 - Selects the input source for bit slice 4 3580 * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 4. 3581 * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 4. 3582 * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 4. 3583 * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 4. 3584 * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 4. 3585 * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 4. 3586 * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 4. 3587 * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 4. 3588 */ 3589 #define PINT_PMSRC_SRC4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC4_SHIFT)) & PINT_PMSRC_SRC4_MASK) 3590 #define PINT_PMSRC_SRC5_MASK (0x3800000U) 3591 #define PINT_PMSRC_SRC5_SHIFT (23U) 3592 /*! SRC5 - Selects the input source for bit slice 5 3593 * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 5. 3594 * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 5. 3595 * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 5. 3596 * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 5. 3597 * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 5. 3598 * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 5. 3599 * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 5. 3600 * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 5. 3601 */ 3602 #define PINT_PMSRC_SRC5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC5_SHIFT)) & PINT_PMSRC_SRC5_MASK) 3603 #define PINT_PMSRC_SRC6_MASK (0x1C000000U) 3604 #define PINT_PMSRC_SRC6_SHIFT (26U) 3605 /*! SRC6 - Selects the input source for bit slice 6 3606 * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 6. 3607 * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 6. 3608 * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 6. 3609 * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 6. 3610 * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 6. 3611 * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 6. 3612 * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 6. 3613 * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 6. 3614 */ 3615 #define PINT_PMSRC_SRC6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC6_SHIFT)) & PINT_PMSRC_SRC6_MASK) 3616 #define PINT_PMSRC_SRC7_MASK (0xE0000000U) 3617 #define PINT_PMSRC_SRC7_SHIFT (29U) 3618 /*! SRC7 - Selects the input source for bit slice 7 3619 * 0b000..Input 0. Selects the pin selected in the PINTSEL0 register as the source to bit slice 7. 3620 * 0b001..Input 1. Selects the pin selected in the PINTSEL1 register as the source to bit slice 7. 3621 * 0b010..Input 2. Selects the pin selected in the PINTSEL2 register as the source to bit slice 7. 3622 * 0b011..Input 3. Selects the pin selected in the PINTSEL3 register as the source to bit slice 7. 3623 * 0b100..Input 4. Selects the pin selected in the PINTSEL4 register as the source to bit slice 7. 3624 * 0b101..Input 5. Selects the pin selected in the PINTSEL5 register as the source to bit slice 7. 3625 * 0b110..Input 6. Selects the pin selected in the PINTSEL6 register as the source to bit slice 7. 3626 * 0b111..Input 7. Selects the pin selected in the PINTSEL7 register as the source to bit slice 7. 3627 */ 3628 #define PINT_PMSRC_SRC7(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC7_SHIFT)) & PINT_PMSRC_SRC7_MASK) 3629 /*! @} */ 3630 3631 /*! @name PMCFG - Pattern match interrupt bit slice configuration register */ 3632 /*! @{ */ 3633 #define PINT_PMCFG_PROD_ENDPTS0_MASK (0x1U) 3634 #define PINT_PMCFG_PROD_ENDPTS0_SHIFT (0U) 3635 /*! PROD_ENDPTS0 - Determines whether slice 0 is an endpoint. 3636 * 0b0..No effect. Slice 0 is not an endpoint. 3637 * 0b1..endpoint. Slice 0 is the endpoint of a product term (minterm). Pin interrupt 0 in the NVIC is raised if the minterm evaluates as true. 3638 */ 3639 #define PINT_PMCFG_PROD_ENDPTS0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS0_SHIFT)) & PINT_PMCFG_PROD_ENDPTS0_MASK) 3640 #define PINT_PMCFG_PROD_ENDPTS1_MASK (0x2U) 3641 #define PINT_PMCFG_PROD_ENDPTS1_SHIFT (1U) 3642 /*! PROD_ENDPTS1 - Determines whether slice 1 is an endpoint. 3643 * 0b0..No effect. Slice 1 is not an endpoint. 3644 * 0b1..endpoint. Slice 1 is the endpoint of a product term (minterm). Pin interrupt 1 in the NVIC is raised if the minterm evaluates as true. 3645 */ 3646 #define PINT_PMCFG_PROD_ENDPTS1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS1_SHIFT)) & PINT_PMCFG_PROD_ENDPTS1_MASK) 3647 #define PINT_PMCFG_PROD_ENDPTS2_MASK (0x4U) 3648 #define PINT_PMCFG_PROD_ENDPTS2_SHIFT (2U) 3649 /*! PROD_ENDPTS2 - Determines whether slice 2 is an endpoint. 3650 * 0b0..No effect. Slice 2 is not an endpoint. 3651 * 0b1..endpoint. Slice 2 is the endpoint of a product term (minterm). Pin interrupt 2 in the NVIC is raised if the minterm evaluates as true. 3652 */ 3653 #define PINT_PMCFG_PROD_ENDPTS2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS2_SHIFT)) & PINT_PMCFG_PROD_ENDPTS2_MASK) 3654 #define PINT_PMCFG_PROD_ENDPTS3_MASK (0x8U) 3655 #define PINT_PMCFG_PROD_ENDPTS3_SHIFT (3U) 3656 /*! PROD_ENDPTS3 - Determines whether slice 3 is an endpoint. 3657 * 0b0..No effect. Slice 3 is not an endpoint. 3658 * 0b1..endpoint. Slice 3 is the endpoint of a product term (minterm). Pin interrupt 3 in the NVIC is raised if the minterm evaluates as true. 3659 */ 3660 #define PINT_PMCFG_PROD_ENDPTS3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS3_SHIFT)) & PINT_PMCFG_PROD_ENDPTS3_MASK) 3661 #define PINT_PMCFG_PROD_ENDPTS4_MASK (0x10U) 3662 #define PINT_PMCFG_PROD_ENDPTS4_SHIFT (4U) 3663 /*! PROD_ENDPTS4 - Determines whether slice 4 is an endpoint. 3664 * 0b0..No effect. Slice 4 is not an endpoint. 3665 * 0b1..endpoint. Slice 4 is the endpoint of a product term (minterm). Pin interrupt 4 in the NVIC is raised if the minterm evaluates as true. 3666 */ 3667 #define PINT_PMCFG_PROD_ENDPTS4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS4_SHIFT)) & PINT_PMCFG_PROD_ENDPTS4_MASK) 3668 #define PINT_PMCFG_PROD_ENDPTS5_MASK (0x20U) 3669 #define PINT_PMCFG_PROD_ENDPTS5_SHIFT (5U) 3670 /*! PROD_ENDPTS5 - Determines whether slice 5 is an endpoint. 3671 * 0b0..No effect. Slice 5 is not an endpoint. 3672 * 0b1..endpoint. Slice 5 is the endpoint of a product term (minterm). Pin interrupt 5 in the NVIC is raised if the minterm evaluates as true. 3673 */ 3674 #define PINT_PMCFG_PROD_ENDPTS5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS5_SHIFT)) & PINT_PMCFG_PROD_ENDPTS5_MASK) 3675 #define PINT_PMCFG_PROD_ENDPTS6_MASK (0x40U) 3676 #define PINT_PMCFG_PROD_ENDPTS6_SHIFT (6U) 3677 /*! PROD_ENDPTS6 - Determines whether slice 6 is an endpoint. 3678 * 0b0..No effect. Slice 6 is not an endpoint. 3679 * 0b1..endpoint. Slice 6 is the endpoint of a product term (minterm). Pin interrupt 6 in the NVIC is raised if the minterm evaluates as true. 3680 */ 3681 #define PINT_PMCFG_PROD_ENDPTS6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS6_SHIFT)) & PINT_PMCFG_PROD_ENDPTS6_MASK) 3682 #define PINT_PMCFG_CFG0_MASK (0x700U) 3683 #define PINT_PMCFG_CFG0_SHIFT (8U) 3684 /*! CFG0 - Specifies the match contribution condition for bit slice 0. 3685 * 0b000..Constant HIGH. This bit slice always contributes to a product term match. 3686 * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last 3687 * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the 3688 * PMSRC registers are written to. 3689 * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last 3690 * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the 3691 * PMSRC registers are written to. 3692 * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input 3693 * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only 3694 * cleared when the PMCFG or the PMSRC registers are written to. 3695 * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. 3696 * 0b101..Low level. Match occurs when there is a low level on the specified input. 3697 * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). 3698 * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or 3699 * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit 3700 * is cleared after one clock cycle. 3701 */ 3702 #define PINT_PMCFG_CFG0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG0_SHIFT)) & PINT_PMCFG_CFG0_MASK) 3703 #define PINT_PMCFG_CFG1_MASK (0x3800U) 3704 #define PINT_PMCFG_CFG1_SHIFT (11U) 3705 /*! CFG1 - Specifies the match contribution condition for bit slice 1. 3706 * 0b000..Constant HIGH. This bit slice always contributes to a product term match. 3707 * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last 3708 * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the 3709 * PMSRC registers are written to. 3710 * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last 3711 * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the 3712 * PMSRC registers are written to. 3713 * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input 3714 * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only 3715 * cleared when the PMCFG or the PMSRC registers are written to. 3716 * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. 3717 * 0b101..Low level. Match occurs when there is a low level on the specified input. 3718 * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). 3719 * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or 3720 * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit 3721 * is cleared after one clock cycle. 3722 */ 3723 #define PINT_PMCFG_CFG1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG1_SHIFT)) & PINT_PMCFG_CFG1_MASK) 3724 #define PINT_PMCFG_CFG2_MASK (0x1C000U) 3725 #define PINT_PMCFG_CFG2_SHIFT (14U) 3726 /*! CFG2 - Specifies the match contribution condition for bit slice 2. 3727 * 0b000..Constant HIGH. This bit slice always contributes to a product term match. 3728 * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last 3729 * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the 3730 * PMSRC registers are written to. 3731 * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last 3732 * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the 3733 * PMSRC registers are written to. 3734 * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input 3735 * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only 3736 * cleared when the PMCFG or the PMSRC registers are written to. 3737 * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. 3738 * 0b101..Low level. Match occurs when there is a low level on the specified input. 3739 * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). 3740 * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or 3741 * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit 3742 * is cleared after one clock cycle. 3743 */ 3744 #define PINT_PMCFG_CFG2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG2_SHIFT)) & PINT_PMCFG_CFG2_MASK) 3745 #define PINT_PMCFG_CFG3_MASK (0xE0000U) 3746 #define PINT_PMCFG_CFG3_SHIFT (17U) 3747 /*! CFG3 - Specifies the match contribution condition for bit slice 3. 3748 * 0b000..Constant HIGH. This bit slice always contributes to a product term match. 3749 * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last 3750 * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the 3751 * PMSRC registers are written to. 3752 * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last 3753 * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the 3754 * PMSRC registers are written to. 3755 * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input 3756 * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only 3757 * cleared when the PMCFG or the PMSRC registers are written to. 3758 * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. 3759 * 0b101..Low level. Match occurs when there is a low level on the specified input. 3760 * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). 3761 * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or 3762 * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit 3763 * is cleared after one clock cycle. 3764 */ 3765 #define PINT_PMCFG_CFG3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG3_SHIFT)) & PINT_PMCFG_CFG3_MASK) 3766 #define PINT_PMCFG_CFG4_MASK (0x700000U) 3767 #define PINT_PMCFG_CFG4_SHIFT (20U) 3768 /*! CFG4 - Specifies the match contribution condition for bit slice 4. 3769 * 0b000..Constant HIGH. This bit slice always contributes to a product term match. 3770 * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last 3771 * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the 3772 * PMSRC registers are written to. 3773 * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last 3774 * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the 3775 * PMSRC registers are written to. 3776 * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input 3777 * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only 3778 * cleared when the PMCFG or the PMSRC registers are written to. 3779 * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. 3780 * 0b101..Low level. Match occurs when there is a low level on the specified input. 3781 * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). 3782 * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or 3783 * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit 3784 * is cleared after one clock cycle. 3785 */ 3786 #define PINT_PMCFG_CFG4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG4_SHIFT)) & PINT_PMCFG_CFG4_MASK) 3787 #define PINT_PMCFG_CFG5_MASK (0x3800000U) 3788 #define PINT_PMCFG_CFG5_SHIFT (23U) 3789 /*! CFG5 - Specifies the match contribution condition for bit slice 5. 3790 * 0b000..Constant HIGH. This bit slice always contributes to a product term match. 3791 * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last 3792 * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the 3793 * PMSRC registers are written to. 3794 * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last 3795 * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the 3796 * PMSRC registers are written to. 3797 * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input 3798 * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only 3799 * cleared when the PMCFG or the PMSRC registers are written to. 3800 * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. 3801 * 0b101..Low level. Match occurs when there is a low level on the specified input. 3802 * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). 3803 * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or 3804 * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit 3805 * is cleared after one clock cycle. 3806 */ 3807 #define PINT_PMCFG_CFG5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG5_SHIFT)) & PINT_PMCFG_CFG5_MASK) 3808 #define PINT_PMCFG_CFG6_MASK (0x1C000000U) 3809 #define PINT_PMCFG_CFG6_SHIFT (26U) 3810 /*! CFG6 - Specifies the match contribution condition for bit slice 6. 3811 * 0b000..Constant HIGH. This bit slice always contributes to a product term match. 3812 * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last 3813 * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the 3814 * PMSRC registers are written to. 3815 * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last 3816 * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the 3817 * PMSRC registers are written to. 3818 * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input 3819 * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only 3820 * cleared when the PMCFG or the PMSRC registers are written to. 3821 * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. 3822 * 0b101..Low level. Match occurs when there is a low level on the specified input. 3823 * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). 3824 * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or 3825 * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit 3826 * is cleared after one clock cycle. 3827 */ 3828 #define PINT_PMCFG_CFG6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG6_SHIFT)) & PINT_PMCFG_CFG6_MASK) 3829 #define PINT_PMCFG_CFG7_MASK (0xE0000000U) 3830 #define PINT_PMCFG_CFG7_SHIFT (29U) 3831 /*! CFG7 - Specifies the match contribution condition for bit slice 7. 3832 * 0b000..Constant HIGH. This bit slice always contributes to a product term match. 3833 * 0b001..Sticky rising edge. Match occurs if a rising edge on the specified input has occurred since the last 3834 * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the 3835 * PMSRC registers are written to. 3836 * 0b010..Sticky falling edge. Match occurs if a falling edge on the specified input has occurred since the last 3837 * time the edge detection for this bit slice was cleared. This bit is only cleared when the PMCFG or the 3838 * PMSRC registers are written to. 3839 * 0b011..Sticky rising or falling edge. Match occurs if either a rising or falling edge on the specified input 3840 * has occurred since the last time the edge detection for this bit slice was cleared. This bit is only 3841 * cleared when the PMCFG or the PMSRC registers are written to. 3842 * 0b100..High level. Match (for this bit slice) occurs when there is a high level on the input specified for this bit slice in the PMSRC register. 3843 * 0b101..Low level. Match occurs when there is a low level on the specified input. 3844 * 0b110..Constant 0. This bit slice never contributes to a match (should be used to disable any unused bit slices). 3845 * 0b111..Event. Non-sticky rising or falling edge. Match occurs on an event - i.e. when either a rising or 3846 * falling edge is first detected on the specified input (this is a non-sticky version of value 0x3) . This bit 3847 * is cleared after one clock cycle. 3848 */ 3849 #define PINT_PMCFG_CFG7(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG7_SHIFT)) & PINT_PMCFG_CFG7_MASK) 3850 /*! @} */ 3851 3852 3853 /*! 3854 * @} 3855 */ /* end of group PINT_Register_Masks */ 3856 3857 3858 /* PINT - Peripheral instance base addresses */ 3859 /** Peripheral PINT base address */ 3860 #define PINT_BASE (0xA0004000u) 3861 /** Peripheral PINT base pointer */ 3862 #define PINT ((PINT_Type *)PINT_BASE) 3863 /** Array initializer of PINT peripheral base addresses */ 3864 #define PINT_BASE_ADDRS { PINT_BASE } 3865 /** Array initializer of PINT peripheral base pointers */ 3866 #define PINT_BASE_PTRS { PINT } 3867 /** Interrupt vectors for the PINT peripheral type */ 3868 #define PINT_IRQS { PIN_INT0_IRQn, PIN_INT1_IRQn, PIN_INT2_IRQn, PIN_INT3_IRQn, PIN_INT4_IRQn, PIN_INT5_IRQn, PIN_INT6_IRQn, PIN_INT7_IRQn } 3869 3870 /*! 3871 * @} 3872 */ /* end of group PINT_Peripheral_Access_Layer */ 3873 3874 3875 /* ---------------------------------------------------------------------------- 3876 -- PLU Peripheral Access Layer 3877 ---------------------------------------------------------------------------- */ 3878 3879 /*! 3880 * @addtogroup PLU_Peripheral_Access_Layer PLU Peripheral Access Layer 3881 * @{ 3882 */ 3883 3884 /** PLU - Register Layout Typedef */ 3885 typedef struct { 3886 struct { /* offset: 0x0, array step: 0x20 */ 3887 __IO uint32_t INP_MUX[5]; /**< LUT0 input 0 MUX..LUT25 input 4 MUX, array offset: 0x0, array step: index*0x20, index2*0x4 */ 3888 uint8_t RESERVED_0[12]; 3889 } LUT[26]; 3890 uint8_t RESERVED_0[1216]; 3891 __IO uint32_t LUT_TRUTH[26]; /**< Specifies the Truth Table contents for LUT0..Specifies the Truth Table contents for LUT25, array offset: 0x800, array step: 0x4 */ 3892 uint8_t RESERVED_1[152]; 3893 __I uint32_t OUTPUTS; /**< Provides the current state of the 8 designated PLU Outputs., offset: 0x900 */ 3894 uint8_t RESERVED_2[764]; 3895 __IO uint32_t OUTPUT_MUX[8]; /**< Selects the source to be connected to PLU Output 0..Selects the source to be connected to PLU Output 7, array offset: 0xC00, array step: 0x4 */ 3896 } PLU_Type; 3897 3898 /* ---------------------------------------------------------------------------- 3899 -- PLU Register Masks 3900 ---------------------------------------------------------------------------- */ 3901 3902 /*! 3903 * @addtogroup PLU_Register_Masks PLU Register Masks 3904 * @{ 3905 */ 3906 3907 /*! @name LUT_INP_MUX - LUT0 input 0 MUX..LUT25 input 4 MUX */ 3908 /*! @{ */ 3909 #define PLU_LUT_INP_MUX_LUTn_INPx_MASK (0x3FU) 3910 #define PLU_LUT_INP_MUX_LUTn_INPx_SHIFT (0U) 3911 /*! LUTn_INPx - Selects the input source to be connected to LUT25 input4. For each LUT, the slot 3912 * associated with the output from LUTn itself is tied low. 3913 * 0b000000..The PLU primary inputs 0. 3914 * 0b000001..The PLU primary inputs 1. 3915 * 0b000010..The PLU primary inputs 2. 3916 * 0b000011..The PLU primary inputs 3. 3917 * 0b000100..The PLU primary inputs 4. 3918 * 0b000101..The PLU primary inputs 5. 3919 * 0b000110..The output of LUT0. 3920 * 0b000111..The output of LUT1. 3921 * 0b001000..The output of LUT2. 3922 * 0b001001..The output of LUT3. 3923 * 0b001010..The output of LUT4. 3924 * 0b001011..The output of LUT5. 3925 * 0b001100..The output of LUT6. 3926 * 0b001101..The output of LUT7. 3927 * 0b001110..The output of LUT8. 3928 * 0b001111..The output of LUT9. 3929 * 0b010000..The output of LUT10. 3930 * 0b010001..The output of LUT11. 3931 * 0b010010..The output of LUT12. 3932 * 0b010011..The output of LUT13. 3933 * 0b010100..The output of LUT14. 3934 * 0b010101..The output of LUT15. 3935 * 0b010110..The output of LUT16. 3936 * 0b010111..The output of LUT17. 3937 * 0b011000..The output of LUT18. 3938 * 0b011001..The output of LUT19. 3939 * 0b011010..The output of LUT20. 3940 * 0b011011..The output of LUT21. 3941 * 0b011100..The output of LUT22. 3942 * 0b011101..The output of LUT23. 3943 * 0b011110..The output of LUT24. 3944 * 0b011111..The output of LUT25. 3945 * 0b100000..state(0). 3946 * 0b100001..state(1). 3947 * 0b100010..state(2). 3948 * 0b100011..state(3). 3949 */ 3950 #define PLU_LUT_INP_MUX_LUTn_INPx(x) (((uint32_t)(((uint32_t)(x)) << PLU_LUT_INP_MUX_LUTn_INPx_SHIFT)) & PLU_LUT_INP_MUX_LUTn_INPx_MASK) 3951 /*! @} */ 3952 3953 /* The count of PLU_LUT_INP_MUX */ 3954 #define PLU_LUT_INP_MUX_COUNT (26U) 3955 3956 /* The count of PLU_LUT_INP_MUX */ 3957 #define PLU_LUT_INP_MUX_COUNT2 (5U) 3958 3959 /*! @name LUT_TRUTH - Specifies the Truth Table contents for LUT0..Specifies the Truth Table contents for LUT25 */ 3960 /*! @{ */ 3961 #define PLU_LUT_TRUTH_LUTn_TRUTH_MASK (0xFFFFFFFFU) 3962 #define PLU_LUT_TRUTH_LUTn_TRUTH_SHIFT (0U) 3963 /*! LUTn_TRUTH - Specifies the Truth Table contents for LUT25.. 3964 */ 3965 #define PLU_LUT_TRUTH_LUTn_TRUTH(x) (((uint32_t)(((uint32_t)(x)) << PLU_LUT_TRUTH_LUTn_TRUTH_SHIFT)) & PLU_LUT_TRUTH_LUTn_TRUTH_MASK) 3966 /*! @} */ 3967 3968 /* The count of PLU_LUT_TRUTH */ 3969 #define PLU_LUT_TRUTH_COUNT (26U) 3970 3971 /*! @name OUTPUTS - Provides the current state of the 8 designated PLU Outputs. */ 3972 /*! @{ */ 3973 #define PLU_OUTPUTS_OUTPUT_STATE_MASK (0xFFU) 3974 #define PLU_OUTPUTS_OUTPUT_STATE_SHIFT (0U) 3975 /*! OUTPUT_STATE - Provides the current state of the 8 designated PLU Outputs.. 3976 */ 3977 #define PLU_OUTPUTS_OUTPUT_STATE(x) (((uint32_t)(((uint32_t)(x)) << PLU_OUTPUTS_OUTPUT_STATE_SHIFT)) & PLU_OUTPUTS_OUTPUT_STATE_MASK) 3978 /*! @} */ 3979 3980 /*! @name OUTPUT_MUX - Selects the source to be connected to PLU Output 0..Selects the source to be connected to PLU Output 7 */ 3981 /*! @{ */ 3982 #define PLU_OUTPUT_MUX_OUTPUTn_MASK (0x1FU) 3983 #define PLU_OUTPUT_MUX_OUTPUTn_SHIFT (0U) 3984 /*! OUTPUTn - Selects the source to be connected to PLU Output 7. 3985 * 0b00000..The PLU output 0. 3986 * 0b00001..The PLU output 1. 3987 * 0b00010..The PLU output 2. 3988 * 0b00011..The PLU output 3. 3989 * 0b00100..The PLU output 4. 3990 * 0b00101..The PLU output 5. 3991 * 0b00110..The PLU output 6. 3992 * 0b00111..The PLU output 7. 3993 * 0b01000..The PLU output 8. 3994 * 0b01001..The PLU output 9. 3995 * 0b01010..The PLU output 10. 3996 * 0b01011..The PLU output 11. 3997 * 0b01100..The PLU output 12. 3998 * 0b01101..The PLU output 13. 3999 * 0b01110..The PLU output 14. 4000 * 0b01111..The PLU output 15. 4001 * 0b10000..The PLU output 16. 4002 * 0b10001..The PLU output 17. 4003 * 0b10010..The PLU output 18. 4004 * 0b10011..The PLU output 19. 4005 * 0b10100..The PLU output 20. 4006 * 0b10101..The PLU output 21. 4007 * 0b10110..The PLU output 22. 4008 * 0b10111..The PLU output 23. 4009 * 0b11000..The PLU output 24. 4010 * 0b11001..The PLU output 25. 4011 * 0b11010..state(0). 4012 * 0b11011..state(1). 4013 * 0b11100..state(2). 4014 * 0b11101..state(3). 4015 */ 4016 #define PLU_OUTPUT_MUX_OUTPUTn(x) (((uint32_t)(((uint32_t)(x)) << PLU_OUTPUT_MUX_OUTPUTn_SHIFT)) & PLU_OUTPUT_MUX_OUTPUTn_MASK) 4017 /*! @} */ 4018 4019 /* The count of PLU_OUTPUT_MUX */ 4020 #define PLU_OUTPUT_MUX_COUNT (8U) 4021 4022 4023 /*! 4024 * @} 4025 */ /* end of group PLU_Register_Masks */ 4026 4027 4028 /* PLU - Peripheral instance base addresses */ 4029 /** Peripheral PLU base address */ 4030 #define PLU_BASE (0x40028000u) 4031 /** Peripheral PLU base pointer */ 4032 #define PLU ((PLU_Type *)PLU_BASE) 4033 /** Array initializer of PLU peripheral base addresses */ 4034 #define PLU_BASE_ADDRS { PLU_BASE } 4035 /** Array initializer of PLU peripheral base pointers */ 4036 #define PLU_BASE_PTRS { PLU } 4037 4038 /*! 4039 * @} 4040 */ /* end of group PLU_Peripheral_Access_Layer */ 4041 4042 4043 /* ---------------------------------------------------------------------------- 4044 -- PMU Peripheral Access Layer 4045 ---------------------------------------------------------------------------- */ 4046 4047 /*! 4048 * @addtogroup PMU_Peripheral_Access_Layer PMU Peripheral Access Layer 4049 * @{ 4050 */ 4051 4052 /** PMU - Register Layout Typedef */ 4053 typedef struct { 4054 __IO uint32_t PCON; /**< Power control register, offset: 0x0 */ 4055 __IO uint32_t GPREG[5]; /**< General purpose register N, array offset: 0x4, array step: 0x4 */ 4056 uint8_t RESERVED_0[8]; 4057 __IO uint32_t WUSRCREG; /**< Pin wake-up source register, offset: 0x20 */ 4058 __IO uint32_t WUENAREG; /**< Pin wake-up enable register, offset: 0x24 */ 4059 } PMU_Type; 4060 4061 /* ---------------------------------------------------------------------------- 4062 -- PMU Register Masks 4063 ---------------------------------------------------------------------------- */ 4064 4065 /*! 4066 * @addtogroup PMU_Register_Masks PMU Register Masks 4067 * @{ 4068 */ 4069 4070 /*! @name PCON - Power control register */ 4071 /*! @{ */ 4072 #define PMU_PCON_PM_MASK (0x7U) 4073 #define PMU_PCON_PM_SHIFT (0U) 4074 /*! PM - Power mode 4075 * 0b000..Default. The part is in active or sleep mode. 4076 * 0b001..Deep-sleep mode. ARM WFI will enter Deep-sleep mode. 4077 * 0b010..Power-down mode. ARM WFI will enter Power-down mode. 4078 * 0b011..Deep power-down mode. ARM WFI will enter Deep-power down mode (ARM Cortex-M0+ core powered-down). 4079 */ 4080 #define PMU_PCON_PM(x) (((uint32_t)(((uint32_t)(x)) << PMU_PCON_PM_SHIFT)) & PMU_PCON_PM_MASK) 4081 #define PMU_PCON_NODPD_MASK (0x8U) 4082 #define PMU_PCON_NODPD_SHIFT (3U) 4083 /*! NODPD - A 1 in this bit prevents entry to Deep power-down mode when 0x3 is written to the PM 4084 * field above, the SLEEPDEEP bit is set, and a WFI is executed. This bit is cleared only by 4085 * power-on reset, so writing a one to this bit locks the part in a mode in which Deep power-down mode 4086 * is blocked. 4087 */ 4088 #define PMU_PCON_NODPD(x) (((uint32_t)(((uint32_t)(x)) << PMU_PCON_NODPD_SHIFT)) & PMU_PCON_NODPD_MASK) 4089 #define PMU_PCON_SLEEPFLAG_MASK (0x100U) 4090 #define PMU_PCON_SLEEPFLAG_SHIFT (8U) 4091 /*! SLEEPFLAG - Sleep mode flag 4092 * 0b0..Active mode. Read: No power-down mode entered. Part is in Active mode. Write: No effect. 4093 * 0b1..Low power mode. Read: Sleep, Deep-sleep or Power-down mode entered. Write: Writing a 1 clears the SLEEPFLAG bit to 0. 4094 */ 4095 #define PMU_PCON_SLEEPFLAG(x) (((uint32_t)(((uint32_t)(x)) << PMU_PCON_SLEEPFLAG_SHIFT)) & PMU_PCON_SLEEPFLAG_MASK) 4096 #define PMU_PCON_DPDFLAG_MASK (0x800U) 4097 #define PMU_PCON_DPDFLAG_SHIFT (11U) 4098 /*! DPDFLAG - Deep power-down flag 4099 * 0b0..Not Deep power-down. Read: Deep power-down mode not entered. Write: No effect. 4100 * 0b1..Deep power-down. Read: Deep power-down mode entered. Write: Clear the Deep power-down flag. 4101 */ 4102 #define PMU_PCON_DPDFLAG(x) (((uint32_t)(((uint32_t)(x)) << PMU_PCON_DPDFLAG_SHIFT)) & PMU_PCON_DPDFLAG_MASK) 4103 /*! @} */ 4104 4105 /*! @name GPREG - General purpose register N */ 4106 /*! @{ */ 4107 #define PMU_GPREG_GPDATA_MASK (0xFFFFFFFFU) 4108 #define PMU_GPREG_GPDATA_SHIFT (0U) 4109 /*! GPDATA - Data retained during Deep power-down mode. 4110 */ 4111 #define PMU_GPREG_GPDATA(x) (((uint32_t)(((uint32_t)(x)) << PMU_GPREG_GPDATA_SHIFT)) & PMU_GPREG_GPDATA_MASK) 4112 /*! @} */ 4113 4114 /* The count of PMU_GPREG */ 4115 #define PMU_GPREG_COUNT (5U) 4116 4117 /*! @name WUSRCREG - Pin wake-up source register */ 4118 /*! @{ */ 4119 #define PMU_WUSRCREG_WUSRCREG_MASK (0xFFU) 4120 #define PMU_WUSRCREG_WUSRCREG_SHIFT (0U) 4121 /*! WUSRCREG - Pin wake-up source 4122 */ 4123 #define PMU_WUSRCREG_WUSRCREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_WUSRCREG_WUSRCREG_SHIFT)) & PMU_WUSRCREG_WUSRCREG_MASK) 4124 /*! @} */ 4125 4126 /*! @name WUENAREG - Pin wake-up enable register */ 4127 /*! @{ */ 4128 #define PMU_WUENAREG_WUENAREG_MASK (0xFFU) 4129 #define PMU_WUENAREG_WUENAREG_SHIFT (0U) 4130 /*! WUENAREG - Pin wake-up enable 4131 */ 4132 #define PMU_WUENAREG_WUENAREG(x) (((uint32_t)(((uint32_t)(x)) << PMU_WUENAREG_WUENAREG_SHIFT)) & PMU_WUENAREG_WUENAREG_MASK) 4133 /*! @} */ 4134 4135 4136 /*! 4137 * @} 4138 */ /* end of group PMU_Register_Masks */ 4139 4140 4141 /* PMU - Peripheral instance base addresses */ 4142 /** Peripheral PMU base address */ 4143 #define PMU_BASE (0x40020000u) 4144 /** Peripheral PMU base pointer */ 4145 #define PMU ((PMU_Type *)PMU_BASE) 4146 /** Array initializer of PMU peripheral base addresses */ 4147 #define PMU_BASE_ADDRS { PMU_BASE } 4148 /** Array initializer of PMU peripheral base pointers */ 4149 #define PMU_BASE_PTRS { PMU } 4150 4151 /*! 4152 * @} 4153 */ /* end of group PMU_Peripheral_Access_Layer */ 4154 4155 4156 /* ---------------------------------------------------------------------------- 4157 -- SPI Peripheral Access Layer 4158 ---------------------------------------------------------------------------- */ 4159 4160 /*! 4161 * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer 4162 * @{ 4163 */ 4164 4165 /** SPI - Register Layout Typedef */ 4166 typedef struct { 4167 __IO uint32_t CFG; /**< SPI Configuration register, offset: 0x0 */ 4168 __IO uint32_t DLY; /**< SPI Delay register, offset: 0x4 */ 4169 __IO uint32_t STAT; /**< SPI Status. Some status flags can be cleared by writing a 1 to that bit position, offset: 0x8 */ 4170 __IO uint32_t INTENSET; /**< SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set., offset: 0xC */ 4171 __O uint32_t INTENCLR; /**< SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared., offset: 0x10 */ 4172 __I uint32_t RXDAT; /**< SPI Receive Data, offset: 0x14 */ 4173 __IO uint32_t TXDATCTL; /**< SPI Transmit Data with Control, offset: 0x18 */ 4174 __IO uint32_t TXDAT; /**< SPI Transmit Data., offset: 0x1C */ 4175 __IO uint32_t TXCTL; /**< SPI Transmit Control, offset: 0x20 */ 4176 __IO uint32_t DIV; /**< SPI clock Divider, offset: 0x24 */ 4177 __I uint32_t INTSTAT; /**< SPI Interrupt Status, offset: 0x28 */ 4178 } SPI_Type; 4179 4180 /* ---------------------------------------------------------------------------- 4181 -- SPI Register Masks 4182 ---------------------------------------------------------------------------- */ 4183 4184 /*! 4185 * @addtogroup SPI_Register_Masks SPI Register Masks 4186 * @{ 4187 */ 4188 4189 /*! @name CFG - SPI Configuration register */ 4190 /*! @{ */ 4191 #define SPI_CFG_ENABLE_MASK (0x1U) 4192 #define SPI_CFG_ENABLE_SHIFT (0U) 4193 /*! ENABLE - SPI enable. 4194 * 0b0..Disabled. The SPI is disabled and the internal state machine and counters are reset. 4195 * 0b1..Enabled. The SPI is enabled for operation. 4196 */ 4197 #define SPI_CFG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_ENABLE_SHIFT)) & SPI_CFG_ENABLE_MASK) 4198 #define SPI_CFG_MASTER_MASK (0x4U) 4199 #define SPI_CFG_MASTER_SHIFT (2U) 4200 /*! MASTER - Master mode select. 4201 * 0b0..Slave mode. The SPI will operate in slave mode. SCK, MOSI, and the SSEL signals are inputs, MISO is an output. 4202 * 0b1..Master mode. The SPI will operate in master mode. SCK, MOSI, and the SSEL signals are outputs, MISO is an input. 4203 */ 4204 #define SPI_CFG_MASTER(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_MASTER_SHIFT)) & SPI_CFG_MASTER_MASK) 4205 #define SPI_CFG_LSBF_MASK (0x8U) 4206 #define SPI_CFG_LSBF_SHIFT (3U) 4207 /*! LSBF - LSB First mode enable. 4208 * 0b0..Standard. Data is transmitted and received in standard MSB first order. 4209 * 0b1..Reverse. Data is transmitted and received in reverse order (LSB first). 4210 */ 4211 #define SPI_CFG_LSBF(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_LSBF_SHIFT)) & SPI_CFG_LSBF_MASK) 4212 #define SPI_CFG_CPHA_MASK (0x10U) 4213 #define SPI_CFG_CPHA_SHIFT (4U) 4214 /*! CPHA - Clock Phase select. 4215 * 0b0..Change. The SPI captures serial data on the first clock transition of the transfer (when the clock 4216 * changes away from the rest state). Data is changed on the following edge. 4217 * 0b1..Capture. The SPI changes serial data on the first clock transition of the transfer (when the clock 4218 * changes away from the rest state). Data is captured on the following edge. 4219 */ 4220 #define SPI_CFG_CPHA(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_CPHA_SHIFT)) & SPI_CFG_CPHA_MASK) 4221 #define SPI_CFG_CPOL_MASK (0x20U) 4222 #define SPI_CFG_CPOL_SHIFT (5U) 4223 /*! CPOL - Clock Polarity select. 4224 * 0b0..Low. The rest state of the clock (between transfers) is low. 4225 * 0b1..High. The rest state of the clock (between transfers) is high. 4226 */ 4227 #define SPI_CFG_CPOL(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_CPOL_SHIFT)) & SPI_CFG_CPOL_MASK) 4228 #define SPI_CFG_LOOP_MASK (0x80U) 4229 #define SPI_CFG_LOOP_SHIFT (7U) 4230 /*! LOOP - Loopback mode enable. Loopback mode applies only to Master mode, and connects transmit 4231 * and receive data connected together to allow simple software testing. 4232 * 0b0..Disabled. 4233 * 0b1..Enabled. 4234 */ 4235 #define SPI_CFG_LOOP(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_LOOP_SHIFT)) & SPI_CFG_LOOP_MASK) 4236 #define SPI_CFG_SPOL0_MASK (0x100U) 4237 #define SPI_CFG_SPOL0_SHIFT (8U) 4238 /*! SPOL0 - SSEL0 Polarity select. 4239 * 0b0..Low. The SSEL0 pin is active low. 4240 * 0b1..High. The SSEL0 pin is active high. 4241 */ 4242 #define SPI_CFG_SPOL0(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL0_SHIFT)) & SPI_CFG_SPOL0_MASK) 4243 #define SPI_CFG_SPOL1_MASK (0x200U) 4244 #define SPI_CFG_SPOL1_SHIFT (9U) 4245 /*! SPOL1 - SSEL1 Polarity select. 4246 * 0b0..Low. The SSEL1 pin is active low. 4247 * 0b1..High. The SSEL1 pin is active high. 4248 */ 4249 #define SPI_CFG_SPOL1(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL1_SHIFT)) & SPI_CFG_SPOL1_MASK) 4250 /*! @} */ 4251 4252 /*! @name DLY - SPI Delay register */ 4253 /*! @{ */ 4254 #define SPI_DLY_PRE_DELAY_MASK (0xFU) 4255 #define SPI_DLY_PRE_DELAY_SHIFT (0U) 4256 /*! PRE_DELAY - Controls the amount of time between SSEL assertion and the beginning of a data 4257 * transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This 4258 * is not considered part of the pre-delay. 0x0 = No additional time is inserted. 0x1 = 1 SPI 4259 * clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are 4260 * inserted. 4261 */ 4262 #define SPI_DLY_PRE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_PRE_DELAY_SHIFT)) & SPI_DLY_PRE_DELAY_MASK) 4263 #define SPI_DLY_POST_DELAY_MASK (0xF0U) 4264 #define SPI_DLY_POST_DELAY_SHIFT (4U) 4265 /*! POST_DELAY - Controls the amount of time between the end of a data transfer and SSEL 4266 * deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock 4267 * times are inserted. 0xF = 15 SPI clock times are inserted. 4268 */ 4269 #define SPI_DLY_POST_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_POST_DELAY_SHIFT)) & SPI_DLY_POST_DELAY_MASK) 4270 #define SPI_DLY_FRAME_DELAY_MASK (0xF00U) 4271 #define SPI_DLY_FRAME_DELAY_SHIFT (8U) 4272 /*! FRAME_DELAY - If the EOF flag is set, controls the minimum amount of time between the current 4273 * frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 4274 * = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock 4275 * times are inserted. 4276 */ 4277 #define SPI_DLY_FRAME_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_FRAME_DELAY_SHIFT)) & SPI_DLY_FRAME_DELAY_MASK) 4278 #define SPI_DLY_TRANSFER_DELAY_MASK (0xF000U) 4279 #define SPI_DLY_TRANSFER_DELAY_SHIFT (12U) 4280 /*! TRANSFER_DELAY - Controls the minimum amount of time that the SSEL is deasserted between 4281 * transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 4282 * = The minimum time that SSEL is deasserted is 2 SPI clock times. 0x2 = The minimum time that 4283 * SSEL is deasserted is 3 SPI clock times. 0xF = The minimum time that SSEL is deasserted is 16 4284 * SPI clock times. 4285 */ 4286 #define SPI_DLY_TRANSFER_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_TRANSFER_DELAY_SHIFT)) & SPI_DLY_TRANSFER_DELAY_MASK) 4287 /*! @} */ 4288 4289 /*! @name STAT - SPI Status. Some status flags can be cleared by writing a 1 to that bit position */ 4290 /*! @{ */ 4291 #define SPI_STAT_RXRDY_MASK (0x1U) 4292 #define SPI_STAT_RXRDY_SHIFT (0U) 4293 /*! RXRDY - Receiver Ready flag. When 1, indicates that data is available to be read from the 4294 * receiver buffer. Cleared after a read of the RXDAT register. 4295 */ 4296 #define SPI_STAT_RXRDY(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_RXRDY_SHIFT)) & SPI_STAT_RXRDY_MASK) 4297 #define SPI_STAT_TXRDY_MASK (0x2U) 4298 #define SPI_STAT_TXRDY_SHIFT (1U) 4299 /*! TXRDY - Transmitter Ready flag. When 1, this bit indicates that data may be written to the 4300 * transmit buffer. Previous data may still be in the process of being transmitted. Cleared when data 4301 * is written to TXDAT or TXDATCTL until the data is moved to the transmit shift register. 4302 */ 4303 #define SPI_STAT_TXRDY(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_TXRDY_SHIFT)) & SPI_STAT_TXRDY_MASK) 4304 #define SPI_STAT_RXOV_MASK (0x4U) 4305 #define SPI_STAT_RXOV_SHIFT (2U) 4306 /*! RXOV - Receiver Overrun interrupt flag. This flag applies only to slave mode (Master = 0). This 4307 * flag is set when the beginning of a received character is detected while the receiver buffer 4308 * is still in use. If this occurs, the receiver buffer contents are preserved, and the incoming 4309 * data is lost. Data received by the SPI should be considered undefined if RxOv is set. 4310 */ 4311 #define SPI_STAT_RXOV(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_RXOV_SHIFT)) & SPI_STAT_RXOV_MASK) 4312 #define SPI_STAT_TXUR_MASK (0x8U) 4313 #define SPI_STAT_TXUR_SHIFT (3U) 4314 /*! TXUR - Transmitter Underrun interrupt flag. This flag applies only to slave mode (Master = 0). 4315 * In this case, the transmitter must begin sending new data on the next input clock if the 4316 * transmitter is idle. If that data is not available in the transmitter holding register at that 4317 * point, there is no data to transmit and the TXUR flag is set. Data transmitted by the SPI should be 4318 * considered undefined if TXUR is set. 4319 */ 4320 #define SPI_STAT_TXUR(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_TXUR_SHIFT)) & SPI_STAT_TXUR_MASK) 4321 #define SPI_STAT_SSA_MASK (0x10U) 4322 #define SPI_STAT_SSA_SHIFT (4U) 4323 /*! SSA - Slave Select Assert. This flag is set whenever any slave select transitions from 4324 * deasserted to asserted, in both master and slave modes. This allows determining when the SPI 4325 * transmit/receive functions become busy, and allows waking up the device from reduced power modes when a 4326 * slave mode access begins. This flag is cleared by software. 4327 */ 4328 #define SPI_STAT_SSA(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_SSA_SHIFT)) & SPI_STAT_SSA_MASK) 4329 #define SPI_STAT_SSD_MASK (0x20U) 4330 #define SPI_STAT_SSD_SHIFT (5U) 4331 /*! SSD - Slave Select Deassert. This flag is set whenever any asserted slave selects transition to 4332 * deasserted, in both master and slave modes. This allows determining when the SPI 4333 * transmit/receive functions become idle. This flag is cleared by software. 4334 */ 4335 #define SPI_STAT_SSD(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_SSD_SHIFT)) & SPI_STAT_SSD_MASK) 4336 #define SPI_STAT_STALLED_MASK (0x40U) 4337 #define SPI_STAT_STALLED_SHIFT (6U) 4338 /*! STALLED - Stalled status flag. This indicates whether the SPI is currently in a stall condition. 4339 */ 4340 #define SPI_STAT_STALLED(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_STALLED_SHIFT)) & SPI_STAT_STALLED_MASK) 4341 #define SPI_STAT_ENDTRANSFER_MASK (0x80U) 4342 #define SPI_STAT_ENDTRANSFER_SHIFT (7U) 4343 /*! ENDTRANSFER - End Transfer control bit. Software can set this bit to force an end to the current 4344 * transfer when the transmitter finishes any activity already in progress, as if the EOT flag 4345 * had been set prior to the last transmission. This capability is included to support cases where 4346 * it is not known when transmit data is written that it will be the end of a transfer. The bit 4347 * is cleared when the transmitter becomes idle as the transfer comes to an end. Forcing an end 4348 * of transfer in this manner causes any specified FRAME_DELAY and TRANSFER_DELAY to be inserted. 4349 */ 4350 #define SPI_STAT_ENDTRANSFER(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_ENDTRANSFER_SHIFT)) & SPI_STAT_ENDTRANSFER_MASK) 4351 #define SPI_STAT_MSTIDLE_MASK (0x100U) 4352 #define SPI_STAT_MSTIDLE_SHIFT (8U) 4353 /*! MSTIDLE - Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. 4354 * This means that the transmit holding register is empty and the transmitter is not in the 4355 * process of sending data. 4356 */ 4357 #define SPI_STAT_MSTIDLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_MSTIDLE_SHIFT)) & SPI_STAT_MSTIDLE_MASK) 4358 /*! @} */ 4359 4360 /*! @name INTENSET - SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set. */ 4361 /*! @{ */ 4362 #define SPI_INTENSET_RXRDYEN_MASK (0x1U) 4363 #define SPI_INTENSET_RXRDYEN_SHIFT (0U) 4364 /*! RXRDYEN - Determines whether an interrupt occurs when receiver data is available. 4365 * 0b0..No interrupt will be generated when receiver data is available. 4366 * 0b1..An interrupt will be generated when receiver data is available in the RXDAT register. 4367 */ 4368 #define SPI_INTENSET_RXRDYEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_RXRDYEN_SHIFT)) & SPI_INTENSET_RXRDYEN_MASK) 4369 #define SPI_INTENSET_TXRDYEN_MASK (0x2U) 4370 #define SPI_INTENSET_TXRDYEN_SHIFT (1U) 4371 /*! TXRDYEN - Determines whether an interrupt occurs when the transmitter holding register is available. 4372 * 0b0..No interrupt will be generated when the transmitter holding register is available. 4373 * 0b1..An interrupt will be generated when data may be written to TXDAT. 4374 */ 4375 #define SPI_INTENSET_TXRDYEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_TXRDYEN_SHIFT)) & SPI_INTENSET_TXRDYEN_MASK) 4376 #define SPI_INTENSET_RXOVEN_MASK (0x4U) 4377 #define SPI_INTENSET_RXOVEN_SHIFT (2U) 4378 /*! RXOVEN - Determines whether an interrupt occurs when a receiver overrun occurs. This happens in 4379 * slave mode when there is a need for the receiver to move newly received data to the RXDAT 4380 * register when it is already in use. The interface prevents receiver overrun in Master mode by not 4381 * allowing a new transmission to begin when a receiver overrun would otherwise occur. 4382 * 0b0..No interrupt will be generated when a receiver overrun occurs. 4383 * 0b1..An interrupt will be generated if a receiver overrun occurs. 4384 */ 4385 #define SPI_INTENSET_RXOVEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_RXOVEN_SHIFT)) & SPI_INTENSET_RXOVEN_MASK) 4386 #define SPI_INTENSET_TXUREN_MASK (0x8U) 4387 #define SPI_INTENSET_TXUREN_SHIFT (3U) 4388 /*! TXUREN - Determines whether an interrupt occurs when a transmitter underrun occurs. This happens 4389 * in slave mode when there is a need to transmit data when none is available. 4390 * 0b0..No interrupt will be generated when the transmitter underruns. 4391 * 0b1..An interrupt will be generated if the transmitter underruns. 4392 */ 4393 #define SPI_INTENSET_TXUREN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_TXUREN_SHIFT)) & SPI_INTENSET_TXUREN_MASK) 4394 #define SPI_INTENSET_SSAEN_MASK (0x10U) 4395 #define SPI_INTENSET_SSAEN_SHIFT (4U) 4396 /*! SSAEN - Determines whether an interrupt occurs when the Slave Select is asserted. 4397 * 0b0..No interrupt will be generated when any Slave Select transitions from deasserted to asserted. 4398 * 0b1..An interrupt will be generated when any Slave Select transitions from deasserted to asserted. 4399 */ 4400 #define SPI_INTENSET_SSAEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_SSAEN_SHIFT)) & SPI_INTENSET_SSAEN_MASK) 4401 #define SPI_INTENSET_SSDEN_MASK (0x20U) 4402 #define SPI_INTENSET_SSDEN_SHIFT (5U) 4403 /*! SSDEN - Determines whether an interrupt occurs when the Slave Select is deasserted. 4404 * 0b0..No interrupt will be generated when all asserted Slave Selects transition to deasserted. 4405 * 0b1..An interrupt will be generated when all asserted Slave Selects transition to deasserted. 4406 */ 4407 #define SPI_INTENSET_SSDEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_SSDEN_SHIFT)) & SPI_INTENSET_SSDEN_MASK) 4408 #define SPI_INTENSET_MSTIDLEEN_MASK (0x100U) 4409 #define SPI_INTENSET_MSTIDLEEN_SHIFT (8U) 4410 /*! MSTIDLEEN - Determines whether an interrupt occurs when the MSTIDLE enable 4411 * 0b0..No interrupt will be generated when MSTIDLE enabled. 4412 * 0b1..An interrupt will be generated when MSTIDLE enabled. 4413 */ 4414 #define SPI_INTENSET_MSTIDLEEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_MSTIDLEEN_SHIFT)) & SPI_INTENSET_MSTIDLEEN_MASK) 4415 /*! @} */ 4416 4417 /*! @name INTENCLR - SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared. */ 4418 /*! @{ */ 4419 #define SPI_INTENCLR_RXRDYEN_MASK (0x1U) 4420 #define SPI_INTENCLR_RXRDYEN_SHIFT (0U) 4421 /*! RXRDYEN - Writing 1 clears the corresponding bits in the INTENSET register. 4422 */ 4423 #define SPI_INTENCLR_RXRDYEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_RXRDYEN_SHIFT)) & SPI_INTENCLR_RXRDYEN_MASK) 4424 #define SPI_INTENCLR_TXRDYEN_MASK (0x2U) 4425 #define SPI_INTENCLR_TXRDYEN_SHIFT (1U) 4426 /*! TXRDYEN - Writing 1 clears the corresponding bits in the INTENSET register. 4427 */ 4428 #define SPI_INTENCLR_TXRDYEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_TXRDYEN_SHIFT)) & SPI_INTENCLR_TXRDYEN_MASK) 4429 #define SPI_INTENCLR_RXOVEN_MASK (0x4U) 4430 #define SPI_INTENCLR_RXOVEN_SHIFT (2U) 4431 /*! RXOVEN - Writing 1 clears the corresponding bits in the INTENSET register. 4432 */ 4433 #define SPI_INTENCLR_RXOVEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_RXOVEN_SHIFT)) & SPI_INTENCLR_RXOVEN_MASK) 4434 #define SPI_INTENCLR_TXUREN_MASK (0x8U) 4435 #define SPI_INTENCLR_TXUREN_SHIFT (3U) 4436 /*! TXUREN - Writing 1 clears the corresponding bits in the INTENSET register. 4437 */ 4438 #define SPI_INTENCLR_TXUREN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_TXUREN_SHIFT)) & SPI_INTENCLR_TXUREN_MASK) 4439 #define SPI_INTENCLR_SSAEN_MASK (0x10U) 4440 #define SPI_INTENCLR_SSAEN_SHIFT (4U) 4441 /*! SSAEN - Writing 1 clears the corresponding bits in the INTENSET register. 4442 */ 4443 #define SPI_INTENCLR_SSAEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_SSAEN_SHIFT)) & SPI_INTENCLR_SSAEN_MASK) 4444 #define SPI_INTENCLR_SSDEN_MASK (0x20U) 4445 #define SPI_INTENCLR_SSDEN_SHIFT (5U) 4446 /*! SSDEN - Writing 1 clears the corresponding bits in the INTENSET register. 4447 */ 4448 #define SPI_INTENCLR_SSDEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_SSDEN_SHIFT)) & SPI_INTENCLR_SSDEN_MASK) 4449 #define SPI_INTENCLR_MSTIDLE_MASK (0x100U) 4450 #define SPI_INTENCLR_MSTIDLE_SHIFT (8U) 4451 /*! MSTIDLE - Writing 1 clears the corresponding bits in the INTENSET register. 4452 */ 4453 #define SPI_INTENCLR_MSTIDLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_MSTIDLE_SHIFT)) & SPI_INTENCLR_MSTIDLE_MASK) 4454 /*! @} */ 4455 4456 /*! @name RXDAT - SPI Receive Data */ 4457 /*! @{ */ 4458 #define SPI_RXDAT_RXDAT_MASK (0xFFFFU) 4459 #define SPI_RXDAT_RXDAT_SHIFT (0U) 4460 /*! RXDAT - Receiver Data. This contains the next piece of received data. The number of bits that 4461 * are used depends on the LEN setting in TXCTL / TXDATCTL. 4462 */ 4463 #define SPI_RXDAT_RXDAT(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXDAT_RXDAT_SHIFT)) & SPI_RXDAT_RXDAT_MASK) 4464 #define SPI_RXDAT_RXSSEL0_N_MASK (0x10000U) 4465 #define SPI_RXDAT_RXSSEL0_N_SHIFT (16U) 4466 /*! RXSSEL0_N - Slave Select for receive. This field allows the state of the SSEL0 pin to be saved 4467 * along with received data. The value will reflect the SSEL0 pin for both master and slave 4468 * operation. A zero indicates that a slave select is active. The actual polarity of each slave select 4469 * pin is configured by the related SPOL bit in CFG. 4470 */ 4471 #define SPI_RXDAT_RXSSEL0_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXDAT_RXSSEL0_N_SHIFT)) & SPI_RXDAT_RXSSEL0_N_MASK) 4472 #define SPI_RXDAT_RXSSEL1_N_MASK (0x20000U) 4473 #define SPI_RXDAT_RXSSEL1_N_SHIFT (17U) 4474 /*! RXSSEL1_N - Slave Select for receive. This field allows the state of the SSEL1 pin to be saved 4475 * along with received data. The value will reflect the SSEL1 pin for both master and slave 4476 * operation. A zero indicates that a slave select is active. The actual polarity of each slave select 4477 * pin is configured by the related SPOL bit in CFG. 4478 */ 4479 #define SPI_RXDAT_RXSSEL1_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXDAT_RXSSEL1_N_SHIFT)) & SPI_RXDAT_RXSSEL1_N_MASK) 4480 #define SPI_RXDAT_RXSSEL2_N_MASK (0x40000U) 4481 #define SPI_RXDAT_RXSSEL2_N_SHIFT (18U) 4482 /*! RXSSEL2_N - Slave Select for receive. This field allows the state of the SSEL2 pin to be saved 4483 * along with received data. The value will reflect the SSEL2 pin for both master and slave 4484 * operation. A zero indicates that a slave select is active. The actual polarity of each slave select 4485 * pin is configured by the related SPOL bit in CFG. 4486 */ 4487 #define SPI_RXDAT_RXSSEL2_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXDAT_RXSSEL2_N_SHIFT)) & SPI_RXDAT_RXSSEL2_N_MASK) 4488 #define SPI_RXDAT_RXSSEL3_N_MASK (0x80000U) 4489 #define SPI_RXDAT_RXSSEL3_N_SHIFT (19U) 4490 /*! RXSSEL3_N - Slave Select for receive. This field allows the state of the SSEL3 pin to be saved 4491 * along with received data. The value will reflect the SSEL3 pin for both master and slave 4492 * operation. A zero indicates that a slave select is active. The actual polarity of each slave select 4493 * pin is configured by the related SPOL bit in CFG. 4494 */ 4495 #define SPI_RXDAT_RXSSEL3_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXDAT_RXSSEL3_N_SHIFT)) & SPI_RXDAT_RXSSEL3_N_MASK) 4496 #define SPI_RXDAT_SOT_MASK (0x100000U) 4497 #define SPI_RXDAT_SOT_SHIFT (20U) 4498 /*! SOT - Start of Transfer flag. This flag will be 1 if this is the first data after the SSELs went 4499 * from deasserted to asserted (i.e., any previous transfer has ended). This information can be 4500 * used to identify the first piece of data in cases where the transfer length is greater than 16 4501 * bit. 4502 */ 4503 #define SPI_RXDAT_SOT(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXDAT_SOT_SHIFT)) & SPI_RXDAT_SOT_MASK) 4504 /*! @} */ 4505 4506 /*! @name TXDATCTL - SPI Transmit Data with Control */ 4507 /*! @{ */ 4508 #define SPI_TXDATCTL_TXDAT_MASK (0xFFFFU) 4509 #define SPI_TXDATCTL_TXDAT_SHIFT (0U) 4510 /*! TXDAT - Transmit Data. This field provides from 1 to 16 bits of data to be transmitted. 4511 */ 4512 #define SPI_TXDATCTL_TXDAT(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXDATCTL_TXDAT_SHIFT)) & SPI_TXDATCTL_TXDAT_MASK) 4513 #define SPI_TXDATCTL_TXSSEL0_N_MASK (0x10000U) 4514 #define SPI_TXDATCTL_TXSSEL0_N_SHIFT (16U) 4515 /*! TXSSEL0_N - Transmit Slave Select. This field asserts SSEL0 in master mode. The output on the 4516 * pin is active LOW by default. Remark: The active state of the SSEL0 pin is configured by bits in 4517 * the CFG register. 4518 * 0b0..SSEL0 asserted. 4519 * 0b1..SSEL0 not asserted. 4520 */ 4521 #define SPI_TXDATCTL_TXSSEL0_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXDATCTL_TXSSEL0_N_SHIFT)) & SPI_TXDATCTL_TXSSEL0_N_MASK) 4522 #define SPI_TXDATCTL_TXSSEL1_N_MASK (0x20000U) 4523 #define SPI_TXDATCTL_TXSSEL1_N_SHIFT (17U) 4524 /*! TXSSEL1_N - Transmit Slave Select. This field asserts SSEL1 in master mode. The output on the 4525 * pin is active LOW by default. Remark: The active state of the SSEL1 pin is configured by bits in 4526 * the CFG register. 4527 * 0b0..SSEL1 asserted. 4528 * 0b1..SSEL1 not asserted. 4529 */ 4530 #define SPI_TXDATCTL_TXSSEL1_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXDATCTL_TXSSEL1_N_SHIFT)) & SPI_TXDATCTL_TXSSEL1_N_MASK) 4531 #define SPI_TXDATCTL_EOT_MASK (0x100000U) 4532 #define SPI_TXDATCTL_EOT_SHIFT (20U) 4533 /*! EOT - End of Transfer. The asserted SSEL will be deasserted at the end of a transfer, and remain 4534 * so for at least the time specified by the Transfer_delay value in the DLY register. 4535 * 0b0..This piece of data is not treated as the end of a transfer. SSEL will not be deasserted at the end of this data. 4536 * 0b1..This piece of data is treated as the end of a transfer. SSEL will be deasserted at the end of this piece of data. 4537 */ 4538 #define SPI_TXDATCTL_EOT(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXDATCTL_EOT_SHIFT)) & SPI_TXDATCTL_EOT_MASK) 4539 #define SPI_TXDATCTL_EOF_MASK (0x200000U) 4540 #define SPI_TXDATCTL_EOF_SHIFT (21U) 4541 /*! EOF - End of Frame. Between frames, a delay may be inserted, as defined by the FRAME_DELAY value 4542 * in the DLY register. The end of a frame may not be particularly meaningful if the FRAME_DELAY 4543 * value = 0. This control can be used as part of the support for frame lengths greater than 16 4544 * bits. 4545 * 0b0..This piece of data transmitted is not treated as the end of a frame. 4546 * 0b1..This piece of data is treated as the end of a frame, causing the FRAME_DELAY time to be inserted before subsequent data is transmitted. 4547 */ 4548 #define SPI_TXDATCTL_EOF(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXDATCTL_EOF_SHIFT)) & SPI_TXDATCTL_EOF_MASK) 4549 #define SPI_TXDATCTL_RXIGNORE_MASK (0x400000U) 4550 #define SPI_TXDATCTL_RXIGNORE_SHIFT (22U) 4551 /*! RXIGNORE - Receive Ignore. This allows data to be transmitted using the SPI without the need to 4552 * read unneeded data from the receiver.Setting this bit simplifies the transmit process and can 4553 * be used with the DMA. 4554 * 0b0..Received data must be read in order to allow transmission to progress. In slave mode, an overrun error 4555 * will occur if received data is not read before new data is received. 4556 * 0b1..Received data is ignored, allowing transmission without reading unneeded received data. No receiver flags are generated. 4557 */ 4558 #define SPI_TXDATCTL_RXIGNORE(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXDATCTL_RXIGNORE_SHIFT)) & SPI_TXDATCTL_RXIGNORE_MASK) 4559 #define SPI_TXDATCTL_LEN_MASK (0xF000000U) 4560 #define SPI_TXDATCTL_LEN_SHIFT (24U) 4561 /*! LEN - Data Length. Specifies the data length from 1 to 16 bits. Note that transfer lengths 4562 * greater than 16 bits are supported by implementing multiple sequential transmits. 0x0 = Data 4563 * transfer is 1 bit in length. 0x1 = Data transfer is 2 bits in length. 0x2 = Data transfer is 3 bits 4564 * in length. ... 0xF = Data transfer is 16 bits in length. 4565 * 0b0000.. 4566 * 0b0001..Data transfer is 1 bit in length. 4567 * 0b0010..Data transfer is 2 bit in length. 4568 * 0b0011..Data transfer is 3 bit in length. 4569 * 0b0100..Data transfer is 4 bit in length. 4570 * 0b0101..Data transfer is 5 bit in length. 4571 * 0b0110..Data transfer is 6 bit in length. 4572 * 0b0111..Data transfer is 7 bit in length. 4573 * 0b1000..Data transfer is 8 bit in length. 4574 * 0b1001..Data transfer is 9 bit in length. 4575 * 0b1010..Data transfer is 10 bit in length. 4576 * 0b1011..Data transfer is 11 bit in length. 4577 * 0b1100..Data transfer is 12 bit in length. 4578 * 0b1101..Data transfer is 13 bit in length. 4579 * 0b1110..Data transfer is 14 bit in length. 4580 * 0b1111..Data transfer is 15 bit in length. 4581 */ 4582 #define SPI_TXDATCTL_LEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXDATCTL_LEN_SHIFT)) & SPI_TXDATCTL_LEN_MASK) 4583 /*! @} */ 4584 4585 /*! @name TXDAT - SPI Transmit Data. */ 4586 /*! @{ */ 4587 #define SPI_TXDAT_DATA_MASK (0xFFFFU) 4588 #define SPI_TXDAT_DATA_SHIFT (0U) 4589 /*! DATA - Transmit Data. This field provides from 4 to 16 bits of data to be transmitted. 4590 */ 4591 #define SPI_TXDAT_DATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXDAT_DATA_SHIFT)) & SPI_TXDAT_DATA_MASK) 4592 /*! @} */ 4593 4594 /*! @name TXCTL - SPI Transmit Control */ 4595 /*! @{ */ 4596 #define SPI_TXCTL_TXSSEL0_N_MASK (0x10000U) 4597 #define SPI_TXCTL_TXSSEL0_N_SHIFT (16U) 4598 /*! TXSSEL0_N - Transmit Slave Select 0. 4599 */ 4600 #define SPI_TXCTL_TXSSEL0_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXCTL_TXSSEL0_N_SHIFT)) & SPI_TXCTL_TXSSEL0_N_MASK) 4601 #define SPI_TXCTL_TXSSEL1_N_MASK (0x20000U) 4602 #define SPI_TXCTL_TXSSEL1_N_SHIFT (17U) 4603 /*! TXSSEL1_N - Transmit Slave Select 1. 4604 */ 4605 #define SPI_TXCTL_TXSSEL1_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXCTL_TXSSEL1_N_SHIFT)) & SPI_TXCTL_TXSSEL1_N_MASK) 4606 #define SPI_TXCTL_EOT_MASK (0x100000U) 4607 #define SPI_TXCTL_EOT_SHIFT (20U) 4608 /*! EOT - End of Transfer. 4609 */ 4610 #define SPI_TXCTL_EOT(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXCTL_EOT_SHIFT)) & SPI_TXCTL_EOT_MASK) 4611 #define SPI_TXCTL_EOF_MASK (0x200000U) 4612 #define SPI_TXCTL_EOF_SHIFT (21U) 4613 /*! EOF - End of Frame. 4614 */ 4615 #define SPI_TXCTL_EOF(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXCTL_EOF_SHIFT)) & SPI_TXCTL_EOF_MASK) 4616 #define SPI_TXCTL_RXIGNORE_MASK (0x400000U) 4617 #define SPI_TXCTL_RXIGNORE_SHIFT (22U) 4618 /*! RXIGNORE - Receive Ignore. 4619 */ 4620 #define SPI_TXCTL_RXIGNORE(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXCTL_RXIGNORE_SHIFT)) & SPI_TXCTL_RXIGNORE_MASK) 4621 #define SPI_TXCTL_LEN_MASK (0xF000000U) 4622 #define SPI_TXCTL_LEN_SHIFT (24U) 4623 /*! LEN - Data transfer Length. 4624 */ 4625 #define SPI_TXCTL_LEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXCTL_LEN_SHIFT)) & SPI_TXCTL_LEN_MASK) 4626 /*! @} */ 4627 4628 /*! @name DIV - SPI clock Divider */ 4629 /*! @{ */ 4630 #define SPI_DIV_DIVVAL_MASK (0xFFFFU) 4631 #define SPI_DIV_DIVVAL_SHIFT (0U) 4632 /*! DIVVAL - Rate divider value. Specifies how the Flexcomm clock (FCLK) is divided to produce the 4633 * SPI clock rate in master mode. DIVVAL is -1 encoded such that the value 0 results in FCLK/1, 4634 * the value 1 results in FCLK/2, up to the maximum possible divide value of 0xFFFF, which results 4635 * in FCLK/65536. 4636 */ 4637 #define SPI_DIV_DIVVAL(x) (((uint32_t)(((uint32_t)(x)) << SPI_DIV_DIVVAL_SHIFT)) & SPI_DIV_DIVVAL_MASK) 4638 /*! @} */ 4639 4640 /*! @name INTSTAT - SPI Interrupt Status */ 4641 /*! @{ */ 4642 #define SPI_INTSTAT_RXRDY_MASK (0x1U) 4643 #define SPI_INTSTAT_RXRDY_SHIFT (0U) 4644 /*! RXRDY - Receiver Ready flag. 4645 */ 4646 #define SPI_INTSTAT_RXRDY(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_RXRDY_SHIFT)) & SPI_INTSTAT_RXRDY_MASK) 4647 #define SPI_INTSTAT_TXRDY_MASK (0x2U) 4648 #define SPI_INTSTAT_TXRDY_SHIFT (1U) 4649 /*! TXRDY - Transmitter Ready flag. 4650 */ 4651 #define SPI_INTSTAT_TXRDY(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_TXRDY_SHIFT)) & SPI_INTSTAT_TXRDY_MASK) 4652 #define SPI_INTSTAT_RXOV_MASK (0x4U) 4653 #define SPI_INTSTAT_RXOV_SHIFT (2U) 4654 /*! RXOV - Receiver Overrun interrupt flag. 4655 */ 4656 #define SPI_INTSTAT_RXOV(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_RXOV_SHIFT)) & SPI_INTSTAT_RXOV_MASK) 4657 #define SPI_INTSTAT_TXUR_MASK (0x8U) 4658 #define SPI_INTSTAT_TXUR_SHIFT (3U) 4659 /*! TXUR - Transmitter Underrun interrupt flag. 4660 */ 4661 #define SPI_INTSTAT_TXUR(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_TXUR_SHIFT)) & SPI_INTSTAT_TXUR_MASK) 4662 #define SPI_INTSTAT_SSA_MASK (0x10U) 4663 #define SPI_INTSTAT_SSA_SHIFT (4U) 4664 /*! SSA - Slave Select Assert. 4665 */ 4666 #define SPI_INTSTAT_SSA(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_SSA_SHIFT)) & SPI_INTSTAT_SSA_MASK) 4667 #define SPI_INTSTAT_SSD_MASK (0x20U) 4668 #define SPI_INTSTAT_SSD_SHIFT (5U) 4669 /*! SSD - Slave Select Deassert. 4670 */ 4671 #define SPI_INTSTAT_SSD(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_SSD_SHIFT)) & SPI_INTSTAT_SSD_MASK) 4672 #define SPI_INTSTAT_MSTIDLE_MASK (0x100U) 4673 #define SPI_INTSTAT_MSTIDLE_SHIFT (8U) 4674 /*! MSTIDLE - Master Idle status flag. 4675 */ 4676 #define SPI_INTSTAT_MSTIDLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_MSTIDLE_SHIFT)) & SPI_INTSTAT_MSTIDLE_MASK) 4677 /*! @} */ 4678 4679 4680 /*! 4681 * @} 4682 */ /* end of group SPI_Register_Masks */ 4683 4684 4685 /* SPI - Peripheral instance base addresses */ 4686 /** Peripheral SPI0 base address */ 4687 #define SPI0_BASE (0x40058000u) 4688 /** Peripheral SPI0 base pointer */ 4689 #define SPI0 ((SPI_Type *)SPI0_BASE) 4690 /** Array initializer of SPI peripheral base addresses */ 4691 #define SPI_BASE_ADDRS { SPI0_BASE } 4692 /** Array initializer of SPI peripheral base pointers */ 4693 #define SPI_BASE_PTRS { SPI0 } 4694 /** Interrupt vectors for the SPI peripheral type */ 4695 #define SPI_IRQS { SPI0_IRQn } 4696 4697 /*! 4698 * @} 4699 */ /* end of group SPI_Peripheral_Access_Layer */ 4700 4701 4702 /* ---------------------------------------------------------------------------- 4703 -- SWM Peripheral Access Layer 4704 ---------------------------------------------------------------------------- */ 4705 4706 /*! 4707 * @addtogroup SWM_Peripheral_Access_Layer SWM Peripheral Access Layer 4708 * @{ 4709 */ 4710 4711 /** SWM - Register Layout Typedef */ 4712 typedef struct { 4713 union { /* offset: 0x0 */ 4714 struct { /* offset: 0x0 */ 4715 __IO uint32_t PINASSIGN0; /**< Pin assign register 0. Assign movable functions U0_TXD, U0_RXD, U0_RTS, U0_CTS., offset: 0x0 */ 4716 __IO uint32_t PINASSIGN1; /**< Pin assign register 1. Assign movable functions U0_SCLK, U1_TXD, U1_RXD, U1_SCLK., offset: 0x4 */ 4717 __IO uint32_t PINASSIGN2; /**< Pin assign register 2. Assign movable functions SPI0_SCK, SPI0_MOSI,SPI0_MISO,SPI0_SSEL0., offset: 0x8 */ 4718 __IO uint32_t PINASSIGN3; /**< Pin assign register 3. Assign movable function SPI0_SSEL1, T0_CAP0, T0_CAP1, T0_CAP2., offset: 0xC */ 4719 __IO uint32_t PINASSIGN4; /**< Pin assign register 4. Assign movable functions T0_MAT0, T0_MAT1,T0_MAT2,T0_MAT3., offset: 0x10 */ 4720 __IO uint32_t PINASSIGN5; /**< Pin assign register 5. Assign movable functions I2C0_SDA, I2C0_SCL, COMP0_OUT, CLKOUT, offset: 0x14 */ 4721 __IO uint32_t PINASSIGN6; /**< Pin assign register 6. Assign movable functions GPIO_INT_BMAT, LVLSHFT_IN0, LVLSHFT_IN1, LVLSHFT_OUT0., offset: 0x18 */ 4722 __IO uint32_t PINASSIGN7; /**< Pin assign register 7. Assign movable functions LVLSHFT_OUT1, I2C1_SDA, I2C1_SCL, PLU_CLKIN., offset: 0x1C */ 4723 __IO uint32_t PINASSIGN8; /**< Pin assign register 8. Assign movable functions CAPT_X0, CAPT_X1, CAPT_X2, CAPT_X3., offset: 0x20 */ 4724 __IO uint32_t PINASSIGN9; /**< Pin assign register 9. Assign movable functions CAPT_X4, CAPT_YL, CAPT_YH., offset: 0x24 */ 4725 } PINASSIGN; 4726 __IO uint32_t PINASSIGN_DATA[10]; /**< Pin assign register, array offset: 0x0, array step: 0x4 */ 4727 }; 4728 uint8_t RESERVED_0[344]; 4729 __IO uint32_t PINASSIGNFIXED0; /**< Pin assign to fixed bits register 0. Pin assign to fixed bits register 0. Assign movable functions PLU_INPUT0 to PLU_INPUT5 and PLU_OUT0 to PLU_INPUT7., offset: 0x180 */ 4730 uint8_t RESERVED_1[60]; 4731 __IO uint32_t PINENABLE0; /**< Pin enable register 0. Enables fixed-pin functions ACMP_I1, ACMP_I2, ACMP_I3,ACMP_I4, SWCLK, SWDIO, RESETN, CLKIN,WKCLK_IN, VDDCMP, ADC_0 - ADC_11,ACMP_I5,DACOUT0., offset: 0x1C0 */ 4732 } SWM_Type; 4733 4734 /* ---------------------------------------------------------------------------- 4735 -- SWM Register Masks 4736 ---------------------------------------------------------------------------- */ 4737 4738 /*! 4739 * @addtogroup SWM_Register_Masks SWM Register Masks 4740 * @{ 4741 */ 4742 4743 /*! @name PINASSIGN0 - Pin assign register 0. Assign movable functions U0_TXD, U0_RXD, U0_RTS, U0_CTS. */ 4744 /*! @{ */ 4745 #define SWM_PINASSIGN0_U0_TXD_O_MASK (0xFFU) 4746 #define SWM_PINASSIGN0_U0_TXD_O_SHIFT (0U) 4747 /*! U0_TXD_O - U0_TXD function assignment. The value is the pin number to be assigned to this 4748 * function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (= 0x7) 4749 * to PIO0_30 (= 0x1E). 4750 */ 4751 #define SWM_PINASSIGN0_U0_TXD_O(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN0_U0_TXD_O_SHIFT)) & SWM_PINASSIGN0_U0_TXD_O_MASK) 4752 #define SWM_PINASSIGN0_U0_RXD_I_MASK (0xFF00U) 4753 #define SWM_PINASSIGN0_U0_RXD_I_SHIFT (8U) 4754 /*! U0_RXD_I - U0_RXD function assignment. The value is the pin number to be assigned to this 4755 * function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (= 0x7) 4756 * to PIO0_30 (= 0x1E). 4757 */ 4758 #define SWM_PINASSIGN0_U0_RXD_I(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN0_U0_RXD_I_SHIFT)) & SWM_PINASSIGN0_U0_RXD_I_MASK) 4759 #define SWM_PINASSIGN0_U0_RTS_O_MASK (0xFF0000U) 4760 #define SWM_PINASSIGN0_U0_RTS_O_SHIFT (16U) 4761 /*! U0_RTS_O - U0_RTS function assignment. The value is the pin number to be assigned to this 4762 * function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (= 0x7) 4763 * to PIO0_30 (= 0x1E). 4764 */ 4765 #define SWM_PINASSIGN0_U0_RTS_O(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN0_U0_RTS_O_SHIFT)) & SWM_PINASSIGN0_U0_RTS_O_MASK) 4766 #define SWM_PINASSIGN0_U0_CTS_I_MASK (0xFF000000U) 4767 #define SWM_PINASSIGN0_U0_CTS_I_SHIFT (24U) 4768 /*! U0_CTS_I - U0_CTS function assignment. The value is the pin number to be assigned to this 4769 * function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (= 0x7) 4770 * to PIO0_30 (= 0x1E). 4771 */ 4772 #define SWM_PINASSIGN0_U0_CTS_I(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN0_U0_CTS_I_SHIFT)) & SWM_PINASSIGN0_U0_CTS_I_MASK) 4773 /*! @} */ 4774 4775 /*! @name PINASSIGN1 - Pin assign register 1. Assign movable functions U0_SCLK, U1_TXD, U1_RXD, U1_SCLK. */ 4776 /*! @{ */ 4777 #define SWM_PINASSIGN1_U0_SCLK_IO_MASK (0xFFU) 4778 #define SWM_PINASSIGN1_U0_SCLK_IO_SHIFT (0U) 4779 /*! U0_SCLK_IO - U0_SCLK function assignment. The value is the pin number to be assigned to this 4780 * function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (= 4781 * 0x7) to PIO0_30 (= 0x1E). 4782 */ 4783 #define SWM_PINASSIGN1_U0_SCLK_IO(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN1_U0_SCLK_IO_SHIFT)) & SWM_PINASSIGN1_U0_SCLK_IO_MASK) 4784 #define SWM_PINASSIGN1_U1_TXD_O_MASK (0xFF00U) 4785 #define SWM_PINASSIGN1_U1_TXD_O_SHIFT (8U) 4786 /*! U1_TXD_O - U1_TXD function assignment. The value is the pin number to be assigned to this 4787 * function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (= 0x7) 4788 * to PIO0_30 (= 0x1E). 4789 */ 4790 #define SWM_PINASSIGN1_U1_TXD_O(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN1_U1_TXD_O_SHIFT)) & SWM_PINASSIGN1_U1_TXD_O_MASK) 4791 #define SWM_PINASSIGN1_U1_RXD_I_MASK (0xFF0000U) 4792 #define SWM_PINASSIGN1_U1_RXD_I_SHIFT (16U) 4793 /*! U1_RXD_I - U1_RXD function assignment. The value is the pin number to be assigned to this 4794 * function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (= 0x7) 4795 * to PIO0_30 (= 0x1E). 4796 */ 4797 #define SWM_PINASSIGN1_U1_RXD_I(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN1_U1_RXD_I_SHIFT)) & SWM_PINASSIGN1_U1_RXD_I_MASK) 4798 #define SWM_PINASSIGN1_U1_SCLK_IO_MASK (0xFF000000U) 4799 #define SWM_PINASSIGN1_U1_SCLK_IO_SHIFT (24U) 4800 /*! U1_SCLK_IO - U1_SCLK function assignment. The value is the pin number to be assigned to this 4801 * function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (= 4802 * 0x7) to PIO0_30 (= 0x1E). 4803 */ 4804 #define SWM_PINASSIGN1_U1_SCLK_IO(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN1_U1_SCLK_IO_SHIFT)) & SWM_PINASSIGN1_U1_SCLK_IO_MASK) 4805 /*! @} */ 4806 4807 /*! @name PINASSIGN2 - Pin assign register 2. Assign movable functions SPI0_SCK, SPI0_MOSI,SPI0_MISO,SPI0_SSEL0. */ 4808 /*! @{ */ 4809 #define SWM_PINASSIGN2_SPI0_SCK_IO_MASK (0xFFU) 4810 #define SWM_PINASSIGN2_SPI0_SCK_IO_SHIFT (0U) 4811 /*! SPI0_SCK_IO - SPI0_SCK function assignment. The value is the pin number to be assigned to this 4812 * function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (= 4813 * 0x7) to PIO0_30 (= 0x1E). 4814 */ 4815 #define SWM_PINASSIGN2_SPI0_SCK_IO(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN2_SPI0_SCK_IO_SHIFT)) & SWM_PINASSIGN2_SPI0_SCK_IO_MASK) 4816 #define SWM_PINASSIGN2_SPI0_MOSI_IO_MASK (0xFF00U) 4817 #define SWM_PINASSIGN2_SPI0_MOSI_IO_SHIFT (8U) 4818 /*! SPI0_MOSI_IO - SPI0_MOSI function assignment. The value is the pin number to be assigned to this 4819 * function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (= 4820 * 0x7) to PIO0_30 (= 0x1E). 4821 */ 4822 #define SWM_PINASSIGN2_SPI0_MOSI_IO(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN2_SPI0_MOSI_IO_SHIFT)) & SWM_PINASSIGN2_SPI0_MOSI_IO_MASK) 4823 #define SWM_PINASSIGN2_SPI0_MISO_IO_MASK (0xFF0000U) 4824 #define SWM_PINASSIGN2_SPI0_MISO_IO_SHIFT (16U) 4825 /*! SPI0_MISO_IO - SPI0_MISO function assignment. The value is the pin number to be assigned to this 4826 * function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (= 4827 * 0x7) to PIO0_30 (= 0x1E). 4828 */ 4829 #define SWM_PINASSIGN2_SPI0_MISO_IO(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN2_SPI0_MISO_IO_SHIFT)) & SWM_PINASSIGN2_SPI0_MISO_IO_MASK) 4830 #define SWM_PINASSIGN2_SPI0_SSEL0_IO_MASK (0xFF000000U) 4831 #define SWM_PINASSIGN2_SPI0_SSEL0_IO_SHIFT (24U) 4832 /*! SPI0_SSEL0_IO - SPI0_SSEL0 function assignment. The value is the pin number to be assigned to 4833 * this function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 4834 * (= 0x7) to PIO0_30 (= 0x1E). 4835 */ 4836 #define SWM_PINASSIGN2_SPI0_SSEL0_IO(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN2_SPI0_SSEL0_IO_SHIFT)) & SWM_PINASSIGN2_SPI0_SSEL0_IO_MASK) 4837 /*! @} */ 4838 4839 /*! @name PINASSIGN3 - Pin assign register 3. Assign movable function SPI0_SSEL1, T0_CAP0, T0_CAP1, T0_CAP2. */ 4840 /*! @{ */ 4841 #define SWM_PINASSIGN3_SPI0_SSEL1_IO_MASK (0xFFU) 4842 #define SWM_PINASSIGN3_SPI0_SSEL1_IO_SHIFT (0U) 4843 /*! SPI0_SSEL1_IO - SPI0_SSEL1 function assignment. The value is the pin number to be assigned to 4844 * this function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 4845 * (= 0x7) to PIO0_30 (= 0x1E). 4846 */ 4847 #define SWM_PINASSIGN3_SPI0_SSEL1_IO(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN3_SPI0_SSEL1_IO_SHIFT)) & SWM_PINASSIGN3_SPI0_SSEL1_IO_MASK) 4848 #define SWM_PINASSIGN3_T0_CAP0_MASK (0xFF00U) 4849 #define SWM_PINASSIGN3_T0_CAP0_SHIFT (8U) 4850 /*! T0_CAP0 - T0_CAP0 function assignment. The value is the pin number to be assigned to this 4851 * function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (= 0x7) 4852 * to PIO0_30 (= 0x1E). 4853 */ 4854 #define SWM_PINASSIGN3_T0_CAP0(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN3_T0_CAP0_SHIFT)) & SWM_PINASSIGN3_T0_CAP0_MASK) 4855 #define SWM_PINASSIGN3_T0_CAP1_MASK (0xFF0000U) 4856 #define SWM_PINASSIGN3_T0_CAP1_SHIFT (16U) 4857 /*! T0_CAP1 - T0_CAP1 function assignment. The value is the pin number to be assigned to this 4858 * function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (= 0x7) 4859 * to PIO0_30 (= 0x1E). 4860 */ 4861 #define SWM_PINASSIGN3_T0_CAP1(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN3_T0_CAP1_SHIFT)) & SWM_PINASSIGN3_T0_CAP1_MASK) 4862 #define SWM_PINASSIGN3_T0_CAP2_MASK (0xFF000000U) 4863 #define SWM_PINASSIGN3_T0_CAP2_SHIFT (24U) 4864 /*! T0_CAP2 - T0_CAP2 function assignment. The value is the pin number to be assigned to this 4865 * function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (= 0x7) 4866 * to PIO0_30 (= 0x1E). 4867 */ 4868 #define SWM_PINASSIGN3_T0_CAP2(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN3_T0_CAP2_SHIFT)) & SWM_PINASSIGN3_T0_CAP2_MASK) 4869 /*! @} */ 4870 4871 /*! @name PINASSIGN4 - Pin assign register 4. Assign movable functions T0_MAT0, T0_MAT1,T0_MAT2,T0_MAT3. */ 4872 /*! @{ */ 4873 #define SWM_PINASSIGN4_T0_MAT0_MASK (0xFFU) 4874 #define SWM_PINASSIGN4_T0_MAT0_SHIFT (0U) 4875 /*! T0_MAT0 - T0_MAT0 function assignment. The value is the pin number to be assigned to this 4876 * function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (= 0x7) 4877 * to PIO0_30 (= 0x1E). 4878 */ 4879 #define SWM_PINASSIGN4_T0_MAT0(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN4_T0_MAT0_SHIFT)) & SWM_PINASSIGN4_T0_MAT0_MASK) 4880 #define SWM_PINASSIGN4_T0_MAT1_MASK (0xFF00U) 4881 #define SWM_PINASSIGN4_T0_MAT1_SHIFT (8U) 4882 /*! T0_MAT1 - T0_MAT1 function assignment. The value is the pin number to be assigned to this 4883 * function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (= 0x7) 4884 * to PIO0_30 (= 0x1E). 4885 */ 4886 #define SWM_PINASSIGN4_T0_MAT1(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN4_T0_MAT1_SHIFT)) & SWM_PINASSIGN4_T0_MAT1_MASK) 4887 #define SWM_PINASSIGN4_T0_MAT2_MASK (0xFF0000U) 4888 #define SWM_PINASSIGN4_T0_MAT2_SHIFT (16U) 4889 /*! T0_MAT2 - T0_MAT2 function assignment. The value is the pin number to be assigned to this 4890 * function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (= 0x7) 4891 * to PIO0_30 (= 0x1E). 4892 */ 4893 #define SWM_PINASSIGN4_T0_MAT2(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN4_T0_MAT2_SHIFT)) & SWM_PINASSIGN4_T0_MAT2_MASK) 4894 #define SWM_PINASSIGN4_T0_MAT3_MASK (0xFF000000U) 4895 #define SWM_PINASSIGN4_T0_MAT3_SHIFT (24U) 4896 /*! T0_MAT3 - T0_MAT3 function assignment. The value is the pin number to be assigned to this 4897 * function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (= 0x7) 4898 * to PIO0_30 (= 0x1E). 4899 */ 4900 #define SWM_PINASSIGN4_T0_MAT3(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN4_T0_MAT3_SHIFT)) & SWM_PINASSIGN4_T0_MAT3_MASK) 4901 /*! @} */ 4902 4903 /*! @name PINASSIGN5 - Pin assign register 5. Assign movable functions I2C0_SDA, I2C0_SCL, COMP0_OUT, CLKOUT */ 4904 /*! @{ */ 4905 #define SWM_PINASSIGN5_I2C0_SDA_IO_MASK (0xFFU) 4906 #define SWM_PINASSIGN5_I2C0_SDA_IO_SHIFT (0U) 4907 /*! I2C0_SDA_IO - I2C0_SDA function assignment. The value is the pin number to be assigned to this 4908 * function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (= 4909 * 0x7) to PIO0_30 (= 0x1E). 4910 */ 4911 #define SWM_PINASSIGN5_I2C0_SDA_IO(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN5_I2C0_SDA_IO_SHIFT)) & SWM_PINASSIGN5_I2C0_SDA_IO_MASK) 4912 #define SWM_PINASSIGN5_I2C0_SCL_IO_MASK (0xFF00U) 4913 #define SWM_PINASSIGN5_I2C0_SCL_IO_SHIFT (8U) 4914 /*! I2C0_SCL_IO - I2C0_SCL function assignment. The value is the pin number to be assigned to this 4915 * function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (= 4916 * 0x7) to PIO0_30 (= 0x1E). 4917 */ 4918 #define SWM_PINASSIGN5_I2C0_SCL_IO(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN5_I2C0_SCL_IO_SHIFT)) & SWM_PINASSIGN5_I2C0_SCL_IO_MASK) 4919 #define SWM_PINASSIGN5_COMP0_OUT_O_MASK (0xFF0000U) 4920 #define SWM_PINASSIGN5_COMP0_OUT_O_SHIFT (16U) 4921 /*! COMP0_OUT_O - COMP0_OUT function assignment. The value is the pin number to be assigned to this 4922 * function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (= 4923 * 0x7) to PIO0_30 (= 0x1E). 4924 */ 4925 #define SWM_PINASSIGN5_COMP0_OUT_O(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN5_COMP0_OUT_O_SHIFT)) & SWM_PINASSIGN5_COMP0_OUT_O_MASK) 4926 #define SWM_PINASSIGN5_CLKOUT_O_MASK (0xFF000000U) 4927 #define SWM_PINASSIGN5_CLKOUT_O_SHIFT (24U) 4928 /*! CLKOUT_O - CLKOUT function assignment. The value is the pin number to be assigned to this 4929 * function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (= 0x7) 4930 * to PIO0_30 (= 0x1E). 4931 */ 4932 #define SWM_PINASSIGN5_CLKOUT_O(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN5_CLKOUT_O_SHIFT)) & SWM_PINASSIGN5_CLKOUT_O_MASK) 4933 /*! @} */ 4934 4935 /*! @name PINASSIGN6 - Pin assign register 6. Assign movable functions GPIO_INT_BMAT, LVLSHFT_IN0, LVLSHFT_IN1, LVLSHFT_OUT0. */ 4936 /*! @{ */ 4937 #define SWM_PINASSIGN6_GPIO_INT_BMAT_O_MASK (0xFFU) 4938 #define SWM_PINASSIGN6_GPIO_INT_BMAT_O_SHIFT (0U) 4939 /*! GPIO_INT_BMAT_O - GPIO_INT_BMAT function assignment. The value is the pin number to be assigned 4940 * to this function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from 4941 * PIO0_7 (= 0x7) to PIO0_30 (= 0x1E). 4942 */ 4943 #define SWM_PINASSIGN6_GPIO_INT_BMAT_O(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN6_GPIO_INT_BMAT_O_SHIFT)) & SWM_PINASSIGN6_GPIO_INT_BMAT_O_MASK) 4944 #define SWM_PINASSIGN6_LVLSHFT_IN0_MASK (0xFF00U) 4945 #define SWM_PINASSIGN6_LVLSHFT_IN0_SHIFT (8U) 4946 /*! LVLSHFT_IN0 - LVLSHFT_IN0 function assignment. The value is the pin number to be assigned to 4947 * this function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 4948 * (= 0x7) to PIO0_30 (= 0x1E). 4949 */ 4950 #define SWM_PINASSIGN6_LVLSHFT_IN0(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN6_LVLSHFT_IN0_SHIFT)) & SWM_PINASSIGN6_LVLSHFT_IN0_MASK) 4951 #define SWM_PINASSIGN6_LVLSHFT_IN1_MASK (0xFF0000U) 4952 #define SWM_PINASSIGN6_LVLSHFT_IN1_SHIFT (16U) 4953 /*! LVLSHFT_IN1 - LVLSHFT_IN1 function assignment. The value is the pin number to be assigned to 4954 * this function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 4955 * (= 0x7) to PIO0_30 (= 0x1E). 4956 */ 4957 #define SWM_PINASSIGN6_LVLSHFT_IN1(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN6_LVLSHFT_IN1_SHIFT)) & SWM_PINASSIGN6_LVLSHFT_IN1_MASK) 4958 #define SWM_PINASSIGN6_LVLSHFT_OUT0_MASK (0xFF000000U) 4959 #define SWM_PINASSIGN6_LVLSHFT_OUT0_SHIFT (24U) 4960 /*! LVLSHFT_OUT0 - LVLSHFT_OUT0 function assignment. The value is the pin number to be assigned to 4961 * this function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 4962 * (= 0x7) to PIO0_30 (= 0x1E). 4963 */ 4964 #define SWM_PINASSIGN6_LVLSHFT_OUT0(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN6_LVLSHFT_OUT0_SHIFT)) & SWM_PINASSIGN6_LVLSHFT_OUT0_MASK) 4965 /*! @} */ 4966 4967 /*! @name PINASSIGN7 - Pin assign register 7. Assign movable functions LVLSHFT_OUT1, I2C1_SDA, I2C1_SCL, PLU_CLKIN. */ 4968 /*! @{ */ 4969 #define SWM_PINASSIGN7_LVLSHFT_OUT1_MASK (0xFFU) 4970 #define SWM_PINASSIGN7_LVLSHFT_OUT1_SHIFT (0U) 4971 /*! LVLSHFT_OUT1 - LVLSHFT_OUT1 function assignment. The value is the pin number to be assigned to 4972 * this function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 4973 * (= 0x7) to PIO0_30 (= 0x1E). 4974 */ 4975 #define SWM_PINASSIGN7_LVLSHFT_OUT1(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN7_LVLSHFT_OUT1_SHIFT)) & SWM_PINASSIGN7_LVLSHFT_OUT1_MASK) 4976 #define SWM_PINASSIGN7_I2C1_SDA_IO_MASK (0xFF00U) 4977 #define SWM_PINASSIGN7_I2C1_SDA_IO_SHIFT (8U) 4978 /*! I2C1_SDA_IO - I2C1_SDA function assignment. The value is the pin number to be assigned to this 4979 * function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (= 4980 * 0x7) to PIO0_30 (= 0x1E). 4981 */ 4982 #define SWM_PINASSIGN7_I2C1_SDA_IO(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN7_I2C1_SDA_IO_SHIFT)) & SWM_PINASSIGN7_I2C1_SDA_IO_MASK) 4983 #define SWM_PINASSIGN7_I2C1_SCL_IO_MASK (0xFF0000U) 4984 #define SWM_PINASSIGN7_I2C1_SCL_IO_SHIFT (16U) 4985 /*! I2C1_SCL_IO - I2C1_SCL function assignment. The value is the pin number to be assigned to this 4986 * function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (= 4987 * 0x7) to PIO0_30 (= 0x1E). 4988 */ 4989 #define SWM_PINASSIGN7_I2C1_SCL_IO(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN7_I2C1_SCL_IO_SHIFT)) & SWM_PINASSIGN7_I2C1_SCL_IO_MASK) 4990 #define SWM_PINASSIGN7_PLU_CLKIN_IN_MASK (0xFF000000U) 4991 #define SWM_PINASSIGN7_PLU_CLKIN_IN_SHIFT (24U) 4992 /*! PLU_CLKIN_IN - PLU_CLKIN function assignment. The value is the pin number to be assigned to this 4993 * function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (= 4994 * 0x7) to PIO0_30 (= 0x1E). 4995 */ 4996 #define SWM_PINASSIGN7_PLU_CLKIN_IN(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN7_PLU_CLKIN_IN_SHIFT)) & SWM_PINASSIGN7_PLU_CLKIN_IN_MASK) 4997 /*! @} */ 4998 4999 /*! @name PINASSIGN8 - Pin assign register 8. Assign movable functions CAPT_X0, CAPT_X1, CAPT_X2, CAPT_X3. */ 5000 /*! @{ */ 5001 #define SWM_PINASSIGN8_CAPT_X0_O_MASK (0xFFU) 5002 #define SWM_PINASSIGN8_CAPT_X0_O_SHIFT (0U) 5003 /*! CAPT_X0_O - CAPT_X0 function assignment. The value is the pin number to be assigned to this 5004 * function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (= 0x7) 5005 * to PIO0_30 (= 0x1E). 5006 */ 5007 #define SWM_PINASSIGN8_CAPT_X0_O(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN8_CAPT_X0_O_SHIFT)) & SWM_PINASSIGN8_CAPT_X0_O_MASK) 5008 #define SWM_PINASSIGN8_CAPT_X1_O_MASK (0xFF00U) 5009 #define SWM_PINASSIGN8_CAPT_X1_O_SHIFT (8U) 5010 /*! CAPT_X1_O - CAPT_X1 function assignment. The value is the pin number to be assigned to this 5011 * function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (= 0x7) 5012 * to PIO0_30 (= 0x1E). 5013 */ 5014 #define SWM_PINASSIGN8_CAPT_X1_O(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN8_CAPT_X1_O_SHIFT)) & SWM_PINASSIGN8_CAPT_X1_O_MASK) 5015 #define SWM_PINASSIGN8_CAPT_X2_O_MASK (0xFF0000U) 5016 #define SWM_PINASSIGN8_CAPT_X2_O_SHIFT (16U) 5017 /*! CAPT_X2_O - CAPT_X2 function assignment. The value is the pin number to be assigned to this 5018 * function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (= 0x7) 5019 * to PIO0_30 (= 0x1E). 5020 */ 5021 #define SWM_PINASSIGN8_CAPT_X2_O(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN8_CAPT_X2_O_SHIFT)) & SWM_PINASSIGN8_CAPT_X2_O_MASK) 5022 #define SWM_PINASSIGN8_CAPT_X3_O_MASK (0xFF000000U) 5023 #define SWM_PINASSIGN8_CAPT_X3_O_SHIFT (24U) 5024 /*! CAPT_X3_O - CAPT_X3 function assignment. The value is the pin number to be assigned to this 5025 * function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (= 0x7) 5026 * to PIO0_30 (= 0x1E). 5027 */ 5028 #define SWM_PINASSIGN8_CAPT_X3_O(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN8_CAPT_X3_O_SHIFT)) & SWM_PINASSIGN8_CAPT_X3_O_MASK) 5029 /*! @} */ 5030 5031 /*! @name PINASSIGN9 - Pin assign register 9. Assign movable functions CAPT_X4, CAPT_YL, CAPT_YH. */ 5032 /*! @{ */ 5033 #define SWM_PINASSIGN9_CAPT_X4_O_MASK (0xFFU) 5034 #define SWM_PINASSIGN9_CAPT_X4_O_SHIFT (0U) 5035 /*! CAPT_X4_O - CAPT_X4 function assignment. The value is the pin number to be assigned to this 5036 * function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (= 0x7) 5037 * to PIO0_30 (= 0x1E). 5038 */ 5039 #define SWM_PINASSIGN9_CAPT_X4_O(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN9_CAPT_X4_O_SHIFT)) & SWM_PINASSIGN9_CAPT_X4_O_MASK) 5040 #define SWM_PINASSIGN9_CAPT_YL_O_MASK (0xFF00U) 5041 #define SWM_PINASSIGN9_CAPT_YL_O_SHIFT (8U) 5042 /*! CAPT_YL_O - CAPT_YL function assignment. The value is the pin number to be assigned to this 5043 * function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (= 0x7) 5044 * to PIO0_30 (= 0x1E). 5045 */ 5046 #define SWM_PINASSIGN9_CAPT_YL_O(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN9_CAPT_YL_O_SHIFT)) & SWM_PINASSIGN9_CAPT_YL_O_MASK) 5047 #define SWM_PINASSIGN9_CAPT_YH_O_MASK (0xFF0000U) 5048 #define SWM_PINASSIGN9_CAPT_YH_O_SHIFT (16U) 5049 /*! CAPT_YH_O - CAPT_YH_O function assignment. The value is the pin number to be assigned to this 5050 * function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (= 5051 * 0x7) to PIO0_30 (= 0x1E). 5052 */ 5053 #define SWM_PINASSIGN9_CAPT_YH_O(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN9_CAPT_YH_O_SHIFT)) & SWM_PINASSIGN9_CAPT_YH_O_MASK) 5054 /*! @} */ 5055 5056 /*! @name PINASSIGN_DATA - Pin assign register */ 5057 /*! @{ */ 5058 #define SWM_PINASSIGN_DATA_T0_MAT3_MASK (0xFFU) 5059 #define SWM_PINASSIGN_DATA_T0_MAT3_SHIFT (0U) 5060 /*! T0_MAT3 - T0_MAT3 function assignment. The value is the pin number to be assigned to this 5061 * function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (= 0x7) 5062 * to PIO0_30 (= 0x1E). 5063 */ 5064 #define SWM_PINASSIGN_DATA_T0_MAT3(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN_DATA_T0_MAT3_SHIFT)) & SWM_PINASSIGN_DATA_T0_MAT3_MASK) 5065 #define SWM_PINASSIGN_DATA_T0_CAP0_MASK (0xFF00U) 5066 #define SWM_PINASSIGN_DATA_T0_CAP0_SHIFT (8U) 5067 /*! T0_CAP0 - T0_CAP0 function assignment. The value is the pin number to be assigned to this 5068 * function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (= 0x7) 5069 * to PIO0_30 (= 0x1E). 5070 */ 5071 #define SWM_PINASSIGN_DATA_T0_CAP0(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN_DATA_T0_CAP0_SHIFT)) & SWM_PINASSIGN_DATA_T0_CAP0_MASK) 5072 #define SWM_PINASSIGN_DATA_T0_CAP1_MASK (0xFF0000U) 5073 #define SWM_PINASSIGN_DATA_T0_CAP1_SHIFT (16U) 5074 /*! T0_CAP1 - T0_CAP1 function assignment. The value is the pin number to be assigned to this 5075 * function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (= 0x7) 5076 * to PIO0_30 (= 0x1E). 5077 */ 5078 #define SWM_PINASSIGN_DATA_T0_CAP1(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN_DATA_T0_CAP1_SHIFT)) & SWM_PINASSIGN_DATA_T0_CAP1_MASK) 5079 #define SWM_PINASSIGN_DATA_T0_CAP2_MASK (0xFF000000U) 5080 #define SWM_PINASSIGN_DATA_T0_CAP2_SHIFT (24U) 5081 /*! T0_CAP2 - T0_CAP2 function assignment. The value is the pin number to be assigned to this 5082 * function. The following pins are available: PIO0_0 (= 0) to PIO0_5 (= 0x5) and from PIO0_7 (= 0x7) 5083 * to PIO0_30 (= 0x1E). 5084 */ 5085 #define SWM_PINASSIGN_DATA_T0_CAP2(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGN_DATA_T0_CAP2_SHIFT)) & SWM_PINASSIGN_DATA_T0_CAP2_MASK) 5086 /*! @} */ 5087 5088 /* The count of SWM_PINASSIGN_DATA */ 5089 #define SWM_PINASSIGN_DATA_COUNT (10U) 5090 5091 /*! @name PINASSIGNFIXED0 - Pin assign to fixed bits register 0. Pin assign to fixed bits register 0. Assign movable functions PLU_INPUT0 to PLU_INPUT5 and PLU_OUT0 to PLU_INPUT7. */ 5092 /*! @{ */ 5093 #define SWM_PINASSIGNFIXED0_PLU_INPUT0_MASK (0x3U) 5094 #define SWM_PINASSIGNFIXED0_PLU_INPUT0_SHIFT (0U) 5095 /*! PLU_INPUT0 - PLU_INPUT0 function assignment. 5096 * 0b00..Assign to PIO0_00. 5097 * 0b01..Assign to PIO0_08. 5098 * 0b10..Assign to PIO0_17. 5099 * 0b11..None. 5100 */ 5101 #define SWM_PINASSIGNFIXED0_PLU_INPUT0(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGNFIXED0_PLU_INPUT0_SHIFT)) & SWM_PINASSIGNFIXED0_PLU_INPUT0_MASK) 5102 #define SWM_PINASSIGNFIXED0_PLU_INPUT1_MASK (0xCU) 5103 #define SWM_PINASSIGNFIXED0_PLU_INPUT1_SHIFT (2U) 5104 /*! PLU_INPUT1 - PLU_INPUT1 function assignment 5105 * 0b00..Assign to PIO0_01. 5106 * 0b01..Assign to PIO0_09. 5107 * 0b10..Assign to PIO0_18. 5108 * 0b11..None. 5109 */ 5110 #define SWM_PINASSIGNFIXED0_PLU_INPUT1(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGNFIXED0_PLU_INPUT1_SHIFT)) & SWM_PINASSIGNFIXED0_PLU_INPUT1_MASK) 5111 #define SWM_PINASSIGNFIXED0_PLU_INPUT2_MASK (0x30U) 5112 #define SWM_PINASSIGNFIXED0_PLU_INPUT2_SHIFT (4U) 5113 /*! PLU_INPUT2 - PLU_INPUT2 function assignment. 5114 * 0b00..Assign to PIO0_02. 5115 * 0b01..Assign to PIO0_10. 5116 * 0b10..Assign to PIO0_19. 5117 * 0b11..None. 5118 */ 5119 #define SWM_PINASSIGNFIXED0_PLU_INPUT2(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGNFIXED0_PLU_INPUT2_SHIFT)) & SWM_PINASSIGNFIXED0_PLU_INPUT2_MASK) 5120 #define SWM_PINASSIGNFIXED0_PLU_INPUT3_MASK (0xC0U) 5121 #define SWM_PINASSIGNFIXED0_PLU_INPUT3_SHIFT (6U) 5122 /*! PLU_INPUT3 - PLU_INPUT3 function assignment. 5123 * 0b00..Assign to PIO0_03. 5124 * 0b01..Assign to PIO0_11. 5125 * 0b10..Assign to PIO0_20. 5126 * 0b11..None. 5127 */ 5128 #define SWM_PINASSIGNFIXED0_PLU_INPUT3(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGNFIXED0_PLU_INPUT3_SHIFT)) & SWM_PINASSIGNFIXED0_PLU_INPUT3_MASK) 5129 #define SWM_PINASSIGNFIXED0_PLU_INPUT4_MASK (0x300U) 5130 #define SWM_PINASSIGNFIXED0_PLU_INPUT4_SHIFT (8U) 5131 /*! PLU_INPUT4 - PLU_INPUT4 function assignment. 5132 * 0b00..Assign to PIO0_04. 5133 * 0b01..Assign to PIO0_12. 5134 * 0b10..Assign to PIO0_21. 5135 * 0b11..None. 5136 */ 5137 #define SWM_PINASSIGNFIXED0_PLU_INPUT4(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGNFIXED0_PLU_INPUT4_SHIFT)) & SWM_PINASSIGNFIXED0_PLU_INPUT4_MASK) 5138 #define SWM_PINASSIGNFIXED0_PLU_INPUT5_MASK (0xC00U) 5139 #define SWM_PINASSIGNFIXED0_PLU_INPUT5_SHIFT (10U) 5140 /*! PLU_INPUT5 - PLU_INPUT5 function assignment. 5141 * 0b00..Assign to PIO0_05. 5142 * 0b01..Assign to PIO0_13. 5143 * 0b10..Assign to PIO0_22. 5144 * 0b11..None. 5145 */ 5146 #define SWM_PINASSIGNFIXED0_PLU_INPUT5(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGNFIXED0_PLU_INPUT5_SHIFT)) & SWM_PINASSIGNFIXED0_PLU_INPUT5_MASK) 5147 #define SWM_PINASSIGNFIXED0_PLU_OUT0_MASK (0x3000U) 5148 #define SWM_PINASSIGNFIXED0_PLU_OUT0_SHIFT (12U) 5149 /*! PLU_OUT0 - PLU_OUT0 function assignment. 5150 * 0b00..Assign to PIO0_07. 5151 * 0b01..Assign to PIO0_14. 5152 * 0b10..Assign to PIO0_23. 5153 * 0b11..None. 5154 */ 5155 #define SWM_PINASSIGNFIXED0_PLU_OUT0(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGNFIXED0_PLU_OUT0_SHIFT)) & SWM_PINASSIGNFIXED0_PLU_OUT0_MASK) 5156 #define SWM_PINASSIGNFIXED0_PLU_OUT1_MASK (0xC000U) 5157 #define SWM_PINASSIGNFIXED0_PLU_OUT1_SHIFT (14U) 5158 /*! PLU_OUT1 - PLU_OUT1 function assignment. 5159 * 0b00..Assign to PIO0_08. 5160 * 0b01..Assign to PIO0_15. 5161 * 0b10..Assign to PIO0_24. 5162 * 0b11..None. 5163 */ 5164 #define SWM_PINASSIGNFIXED0_PLU_OUT1(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGNFIXED0_PLU_OUT1_SHIFT)) & SWM_PINASSIGNFIXED0_PLU_OUT1_MASK) 5165 #define SWM_PINASSIGNFIXED0_PLU_OUT2_MASK (0x30000U) 5166 #define SWM_PINASSIGNFIXED0_PLU_OUT2_SHIFT (16U) 5167 /*! PLU_OUT2 - PLU_OUT2 function assignment. 5168 * 0b00..Assign to PIO0_09. 5169 * 0b01..Assign to PIO0_16. 5170 * 0b10..Assign to PIO0_25. 5171 * 0b11..None. 5172 */ 5173 #define SWM_PINASSIGNFIXED0_PLU_OUT2(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGNFIXED0_PLU_OUT2_SHIFT)) & SWM_PINASSIGNFIXED0_PLU_OUT2_MASK) 5174 #define SWM_PINASSIGNFIXED0_PLU_OUT3_MASK (0xC0000U) 5175 #define SWM_PINASSIGNFIXED0_PLU_OUT3_SHIFT (18U) 5176 /*! PLU_OUT3 - PLU_OUT3 function assignment. 5177 * 0b00..Assign to PIO0_10. 5178 * 0b01..Assign to PIO0_17. 5179 * 0b10..Assign to PIO0_26. 5180 * 0b11..None. 5181 */ 5182 #define SWM_PINASSIGNFIXED0_PLU_OUT3(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGNFIXED0_PLU_OUT3_SHIFT)) & SWM_PINASSIGNFIXED0_PLU_OUT3_MASK) 5183 #define SWM_PINASSIGNFIXED0_PLU_OUT4_MASK (0x300000U) 5184 #define SWM_PINASSIGNFIXED0_PLU_OUT4_SHIFT (20U) 5185 /*! PLU_OUT4 - PLU_OUT4 function assignment. 5186 * 0b00..Assign to PIO0_11. 5187 * 0b01..Assign to PIO0_18. 5188 * 0b10..Assign to PIO0_27. 5189 * 0b11..None. 5190 */ 5191 #define SWM_PINASSIGNFIXED0_PLU_OUT4(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGNFIXED0_PLU_OUT4_SHIFT)) & SWM_PINASSIGNFIXED0_PLU_OUT4_MASK) 5192 #define SWM_PINASSIGNFIXED0_PLU_OUT5_MASK (0xC00000U) 5193 #define SWM_PINASSIGNFIXED0_PLU_OUT5_SHIFT (22U) 5194 /*! PLU_OUT5 - PLU_OUT5 function assignment. 5195 * 0b00..Assign to PIO0_12. 5196 * 0b01..Assign to PIO0_19. 5197 * 0b10..Assign to PIO0_28. 5198 * 0b11..None. 5199 */ 5200 #define SWM_PINASSIGNFIXED0_PLU_OUT5(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGNFIXED0_PLU_OUT5_SHIFT)) & SWM_PINASSIGNFIXED0_PLU_OUT5_MASK) 5201 #define SWM_PINASSIGNFIXED0_PLU_OUT6_MASK (0x3000000U) 5202 #define SWM_PINASSIGNFIXED0_PLU_OUT6_SHIFT (24U) 5203 /*! PLU_OUT6 - PLU_OUT6 function assignment. 5204 * 0b00..Assign to PIO0_13. 5205 * 0b01..Assign to PIO0_20. 5206 * 0b10..Assign to PIO0_29. 5207 * 0b11..None. 5208 */ 5209 #define SWM_PINASSIGNFIXED0_PLU_OUT6(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGNFIXED0_PLU_OUT6_SHIFT)) & SWM_PINASSIGNFIXED0_PLU_OUT6_MASK) 5210 #define SWM_PINASSIGNFIXED0_PLU_OUT7_MASK (0xC000000U) 5211 #define SWM_PINASSIGNFIXED0_PLU_OUT7_SHIFT (26U) 5212 /*! PLU_OUT7 - PLU_OUT7 function assignment. 5213 * 0b00..Assign to PIO0_14. 5214 * 0b01..Assign to PIO0_21. 5215 * 0b10..Assign to PIO0_30. 5216 * 0b11..None. 5217 */ 5218 #define SWM_PINASSIGNFIXED0_PLU_OUT7(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINASSIGNFIXED0_PLU_OUT7_SHIFT)) & SWM_PINASSIGNFIXED0_PLU_OUT7_MASK) 5219 /*! @} */ 5220 5221 /*! @name PINENABLE0 - Pin enable register 0. Enables fixed-pin functions ACMP_I1, ACMP_I2, ACMP_I3,ACMP_I4, SWCLK, SWDIO, RESETN, CLKIN,WKCLK_IN, VDDCMP, ADC_0 - ADC_11,ACMP_I5,DACOUT0. */ 5222 /*! @{ */ 5223 #define SWM_PINENABLE0_ACMP_I1_MASK (0x1U) 5224 #define SWM_PINENABLE0_ACMP_I1_SHIFT (0U) 5225 /*! ACMP_I1 - ACMP_I1 function select. 5226 * 0b0..ACMP_I1 enabled on pin PIO0_00. 5227 * 0b1..ACMP_I1 disabled. 5228 */ 5229 #define SWM_PINENABLE0_ACMP_I1(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINENABLE0_ACMP_I1_SHIFT)) & SWM_PINENABLE0_ACMP_I1_MASK) 5230 #define SWM_PINENABLE0_ACMP_I2_MASK (0x2U) 5231 #define SWM_PINENABLE0_ACMP_I2_SHIFT (1U) 5232 /*! ACMP_I2 - ACMP_I2 function select. 5233 * 0b0..ACMP_I2 enabled on pin PIO0_1. 5234 * 0b1..ACMP_I2 disabled. 5235 */ 5236 #define SWM_PINENABLE0_ACMP_I2(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINENABLE0_ACMP_I2_SHIFT)) & SWM_PINENABLE0_ACMP_I2_MASK) 5237 #define SWM_PINENABLE0_ACMP_I3_MASK (0x4U) 5238 #define SWM_PINENABLE0_ACMP_I3_SHIFT (2U) 5239 /*! ACMP_I3 - ACMP_I3 function select. 5240 * 0b0..ACMP_I3 enabled on pin PIO0_14. 5241 * 0b1..ACMP_I3 disabled. 5242 */ 5243 #define SWM_PINENABLE0_ACMP_I3(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINENABLE0_ACMP_I3_SHIFT)) & SWM_PINENABLE0_ACMP_I3_MASK) 5244 #define SWM_PINENABLE0_ACMP_I4_MASK (0x8U) 5245 #define SWM_PINENABLE0_ACMP_I4_SHIFT (3U) 5246 /*! ACMP_I4 - ACMP_I4 function select. 5247 * 0b0..ACMP_I4 enabled on pin PIO0_16. 5248 * 0b1..ACMP_I4 disabled. 5249 */ 5250 #define SWM_PINENABLE0_ACMP_I4(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINENABLE0_ACMP_I4_SHIFT)) & SWM_PINENABLE0_ACMP_I4_MASK) 5251 #define SWM_PINENABLE0_SWCLK_MASK (0x10U) 5252 #define SWM_PINENABLE0_SWCLK_SHIFT (4U) 5253 /*! SWCLK - SWCLK function select. 5254 * 0b0..SWCLK enabled on pin PIO0_3. 5255 * 0b1..SWCLK disabled. 5256 */ 5257 #define SWM_PINENABLE0_SWCLK(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINENABLE0_SWCLK_SHIFT)) & SWM_PINENABLE0_SWCLK_MASK) 5258 #define SWM_PINENABLE0_SWDIO_MASK (0x20U) 5259 #define SWM_PINENABLE0_SWDIO_SHIFT (5U) 5260 /*! SWDIO - SWDIO function select. 5261 * 0b0..SWDIO enabled on pin PIO0_2. 5262 * 0b1..SWDIO disabled. 5263 */ 5264 #define SWM_PINENABLE0_SWDIO(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINENABLE0_SWDIO_SHIFT)) & SWM_PINENABLE0_SWDIO_MASK) 5265 #define SWM_PINENABLE0_RESETN_MASK (0x40U) 5266 #define SWM_PINENABLE0_RESETN_SHIFT (6U) 5267 /*! RESETN - RESETN function select. 5268 * 0b0..RESETN enabled on pin PIO0_5. 5269 * 0b1..RESETN disabled. 5270 */ 5271 #define SWM_PINENABLE0_RESETN(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINENABLE0_RESETN_SHIFT)) & SWM_PINENABLE0_RESETN_MASK) 5272 #define SWM_PINENABLE0_CLKIN_MASK (0x80U) 5273 #define SWM_PINENABLE0_CLKIN_SHIFT (7U) 5274 /*! CLKIN - CLKIN function select. 5275 * 0b0..CLKIN enabled on pin PIO0_1. 5276 * 0b1..CLKIN disabled. 5277 */ 5278 #define SWM_PINENABLE0_CLKIN(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINENABLE0_CLKIN_SHIFT)) & SWM_PINENABLE0_CLKIN_MASK) 5279 #define SWM_PINENABLE0_WKCLKIN_MASK (0x100U) 5280 #define SWM_PINENABLE0_WKCLKIN_SHIFT (8U) 5281 /*! WKCLKIN - WKCLK_IN function select. 5282 * 0b0..WKCLK_IN enabled on pin PIO0_11. 5283 * 0b1..WKCLK_IN disabled. 5284 */ 5285 #define SWM_PINENABLE0_WKCLKIN(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINENABLE0_WKCLKIN_SHIFT)) & SWM_PINENABLE0_WKCLKIN_MASK) 5286 #define SWM_PINENABLE0_VDDCMP_MASK (0x200U) 5287 #define SWM_PINENABLE0_VDDCMP_SHIFT (9U) 5288 /*! VDDCMP - VDDCMP function select. 5289 * 0b0..VDDCMP enabled on pin PIO0_6. 5290 * 0b1..VDDCMP disabled. 5291 */ 5292 #define SWM_PINENABLE0_VDDCMP(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINENABLE0_VDDCMP_SHIFT)) & SWM_PINENABLE0_VDDCMP_MASK) 5293 #define SWM_PINENABLE0_ADC_0_MASK (0x400U) 5294 #define SWM_PINENABLE0_ADC_0_SHIFT (10U) 5295 /*! ADC_0 - ADC_0 function select. 5296 * 0b0..ADC_0 enabled on pin PIO0_1. 5297 * 0b1..ADC_0 disabled. 5298 */ 5299 #define SWM_PINENABLE0_ADC_0(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINENABLE0_ADC_0_SHIFT)) & SWM_PINENABLE0_ADC_0_MASK) 5300 #define SWM_PINENABLE0_ADC_1_MASK (0x800U) 5301 #define SWM_PINENABLE0_ADC_1_SHIFT (11U) 5302 /*! ADC_1 - ADC_1 function select. 5303 * 0b0..ADC_1 enabled on pin PIO0_7. 5304 * 0b1..ADC_1 disabled. 5305 */ 5306 #define SWM_PINENABLE0_ADC_1(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINENABLE0_ADC_1_SHIFT)) & SWM_PINENABLE0_ADC_1_MASK) 5307 #define SWM_PINENABLE0_ADC_2_MASK (0x1000U) 5308 #define SWM_PINENABLE0_ADC_2_SHIFT (12U) 5309 /*! ADC_2 - ADC_2 function select. 5310 * 0b0..ADC_2 enabled on pin PIO0_14. 5311 * 0b1..ADC_2 disabled. 5312 */ 5313 #define SWM_PINENABLE0_ADC_2(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINENABLE0_ADC_2_SHIFT)) & SWM_PINENABLE0_ADC_2_MASK) 5314 #define SWM_PINENABLE0_ADC_3_MASK (0x2000U) 5315 #define SWM_PINENABLE0_ADC_3_SHIFT (13U) 5316 /*! ADC_3 - ADC_3 function select. 5317 * 0b0..ADC_3 enabled on pin PIO0_16. 5318 * 0b1..ADC_3 disabled. 5319 */ 5320 #define SWM_PINENABLE0_ADC_3(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINENABLE0_ADC_3_SHIFT)) & SWM_PINENABLE0_ADC_3_MASK) 5321 #define SWM_PINENABLE0_ADC_4_MASK (0x4000U) 5322 #define SWM_PINENABLE0_ADC_4_SHIFT (14U) 5323 /*! ADC_4 - ADC_4 function select. 5324 * 0b0..ADC_4 enabled on pin PIO0_9. 5325 * 0b1..ADC_4 disabled. 5326 */ 5327 #define SWM_PINENABLE0_ADC_4(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINENABLE0_ADC_4_SHIFT)) & SWM_PINENABLE0_ADC_4_MASK) 5328 #define SWM_PINENABLE0_ADC_5_MASK (0x8000U) 5329 #define SWM_PINENABLE0_ADC_5_SHIFT (15U) 5330 /*! ADC_5 - ADC_5 function select. 5331 * 0b0..ADC_5 enabled on pin PIO0_8. 5332 * 0b1..ADC_5 disabled. 5333 */ 5334 #define SWM_PINENABLE0_ADC_5(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINENABLE0_ADC_5_SHIFT)) & SWM_PINENABLE0_ADC_5_MASK) 5335 #define SWM_PINENABLE0_ADC_6_MASK (0x10000U) 5336 #define SWM_PINENABLE0_ADC_6_SHIFT (16U) 5337 /*! ADC_6 - ADC_6 function select. 5338 * 0b0..ADC_6 enabled on pin PIO0_11. 5339 * 0b1..ADC_6 disabled. 5340 */ 5341 #define SWM_PINENABLE0_ADC_6(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINENABLE0_ADC_6_SHIFT)) & SWM_PINENABLE0_ADC_6_MASK) 5342 #define SWM_PINENABLE0_ADC_7_MASK (0x20000U) 5343 #define SWM_PINENABLE0_ADC_7_SHIFT (17U) 5344 /*! ADC_7 - ADC_7 function select. 5345 * 0b0..ADC_7 enabled on pin PIO0_10. 5346 * 0b1..ADC_7 disabled. 5347 */ 5348 #define SWM_PINENABLE0_ADC_7(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINENABLE0_ADC_7_SHIFT)) & SWM_PINENABLE0_ADC_7_MASK) 5349 #define SWM_PINENABLE0_ADC_8_MASK (0x40000U) 5350 #define SWM_PINENABLE0_ADC_8_SHIFT (18U) 5351 /*! ADC_8 - ADC_8 function select. 5352 * 0b0..ADC_8 enabled on pin PIO0_15. 5353 * 0b1..ADC_8 disabled. 5354 */ 5355 #define SWM_PINENABLE0_ADC_8(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINENABLE0_ADC_8_SHIFT)) & SWM_PINENABLE0_ADC_8_MASK) 5356 #define SWM_PINENABLE0_ADC_9_MASK (0x80000U) 5357 #define SWM_PINENABLE0_ADC_9_SHIFT (19U) 5358 /*! ADC_9 - ADC_9 function select. 5359 * 0b0..ADC_9 enabled on pin PIO0_17. 5360 * 0b1..ADC_9 disabled. 5361 */ 5362 #define SWM_PINENABLE0_ADC_9(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINENABLE0_ADC_9_SHIFT)) & SWM_PINENABLE0_ADC_9_MASK) 5363 #define SWM_PINENABLE0_ADC_10_MASK (0x100000U) 5364 #define SWM_PINENABLE0_ADC_10_SHIFT (20U) 5365 /*! ADC_10 - ADC_10 function select. 5366 * 0b0..ADC_10 enabled on pin PIO0_13. 5367 * 0b1..ADC_10 disabled. 5368 */ 5369 #define SWM_PINENABLE0_ADC_10(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINENABLE0_ADC_10_SHIFT)) & SWM_PINENABLE0_ADC_10_MASK) 5370 #define SWM_PINENABLE0_ADC_11_MASK (0x200000U) 5371 #define SWM_PINENABLE0_ADC_11_SHIFT (21U) 5372 /*! ADC_11 - ADC_11 function select. 5373 * 0b0..ADC_11 enabled on pin PIO0_4. 5374 * 0b1..ADC_11 disabled. 5375 */ 5376 #define SWM_PINENABLE0_ADC_11(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINENABLE0_ADC_11_SHIFT)) & SWM_PINENABLE0_ADC_11_MASK) 5377 #define SWM_PINENABLE0_ACMP_I5_MASK (0x400000U) 5378 #define SWM_PINENABLE0_ACMP_I5_SHIFT (22U) 5379 /*! ACMP_I5 - ACMP_I5 function select. 5380 * 0b0..ACMP_I5 enabled on pin PIO0_21. 5381 * 0b1..ACMP_I5 disabled. 5382 */ 5383 #define SWM_PINENABLE0_ACMP_I5(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINENABLE0_ACMP_I5_SHIFT)) & SWM_PINENABLE0_ACMP_I5_MASK) 5384 #define SWM_PINENABLE0_DACOUT0_MASK (0x800000U) 5385 #define SWM_PINENABLE0_DACOUT0_SHIFT (23U) 5386 /*! DACOUT0 - DACOUT0 function select. 5387 * 0b0..DACOUT0 enabled on pin PIO0_19. 5388 * 0b1..DACOUT0 disabled. 5389 */ 5390 #define SWM_PINENABLE0_DACOUT0(x) (((uint32_t)(((uint32_t)(x)) << SWM_PINENABLE0_DACOUT0_SHIFT)) & SWM_PINENABLE0_DACOUT0_MASK) 5391 /*! @} */ 5392 5393 5394 /*! 5395 * @} 5396 */ /* end of group SWM_Register_Masks */ 5397 5398 5399 /* SWM - Peripheral instance base addresses */ 5400 /** Peripheral SWM0 base address */ 5401 #define SWM0_BASE (0x4000C000u) 5402 /** Peripheral SWM0 base pointer */ 5403 #define SWM0 ((SWM_Type *)SWM0_BASE) 5404 /** Array initializer of SWM peripheral base addresses */ 5405 #define SWM_BASE_ADDRS { SWM0_BASE } 5406 /** Array initializer of SWM peripheral base pointers */ 5407 #define SWM_BASE_PTRS { SWM0 } 5408 5409 /*! 5410 * @} 5411 */ /* end of group SWM_Peripheral_Access_Layer */ 5412 5413 5414 /* ---------------------------------------------------------------------------- 5415 -- SYSCON Peripheral Access Layer 5416 ---------------------------------------------------------------------------- */ 5417 5418 /*! 5419 * @addtogroup SYSCON_Peripheral_Access_Layer SYSCON Peripheral Access Layer 5420 * @{ 5421 */ 5422 5423 /** SYSCON - Register Layout Typedef */ 5424 typedef struct { 5425 __IO uint32_t SYSMEMREMAP; /**< System Remap register, offset: 0x0 */ 5426 uint8_t RESERVED_0[52]; 5427 __IO uint32_t SYSRSTSTAT; /**< System reset status register., offset: 0x38 */ 5428 uint8_t RESERVED_1[20]; 5429 __IO uint32_t MAINCLKSEL; /**< Main clock source select register, offset: 0x50 */ 5430 __IO uint32_t MAINCLKUEN; /**< Main clock source update enable register., offset: 0x54 */ 5431 __IO uint32_t SYSAHBCLKDIV; /**< System clock divider register, offset: 0x58 */ 5432 uint8_t RESERVED_2[4]; 5433 __IO uint32_t CAPTCLKSEL; /**< Capacitive Touch clock source select., offset: 0x60 */ 5434 __IO uint32_t ADCCLKSEL; /**< ADC clock source select register, offset: 0x64 */ 5435 __IO uint32_t ADCCLKDIV; /**< ADC clock divider register, offset: 0x68 */ 5436 uint8_t RESERVED_3[16]; 5437 __IO uint32_t LPOSCCLKEN; /**< WDT and Wake Timer clock enable control., offset: 0x7C */ 5438 __IO uint32_t SYSAHBCLKCTRL0; /**< System clock group 0 control register, offset: 0x80 */ 5439 __IO uint32_t SYSAHBCLKCTRL1; /**< System clock group 1 control register, offset: 0x84 */ 5440 __IO uint32_t PRESETCTRL0; /**< Peripheral reset group 0 control register, offset: 0x88 */ 5441 __IO uint32_t PRESETCTRL1; /**< Peripheral reset group 1 control register, offset: 0x8C */ 5442 __IO uint32_t UART0CLKSEL; /**< Function clock source select for UART0., offset: 0x90 */ 5443 __IO uint32_t UART1CLKSEL; /**< Function clock source select for UART1., offset: 0x94 */ 5444 uint8_t RESERVED_4[12]; 5445 __IO uint32_t I2C0CLKSEL; /**< Function clock source select for I2C0., offset: 0xA4 */ 5446 __IO uint32_t I2C1CLKSEL; /**< Function clock source select for I2C1., offset: 0xA8 */ 5447 uint8_t RESERVED_5[8]; 5448 __IO uint32_t SPI0CLKSEL; /**< Function clock source select for SPI0., offset: 0xB4 */ 5449 uint8_t RESERVED_6[24]; 5450 struct { /* offset: 0xD0, array step: 0xC */ 5451 __IO uint32_t FRGDIV; /**< fractional generator divider value register, array offset: 0xD0, array step: 0xC */ 5452 __IO uint32_t FRGMULT; /**< fractional generator multiplier value register, array offset: 0xD4, array step: 0xC */ 5453 __IO uint32_t FRGCLKSEL; /**< FRG clock source select register, array offset: 0xD8, array step: 0xC */ 5454 } FRG[1]; 5455 uint8_t RESERVED_7[20]; 5456 __IO uint32_t CLKOUTSEL; /**< CLKOUT clock source select register, offset: 0xF0 */ 5457 __IO uint32_t CLKOUTDIV; /**< CLKOUT clock divider registers, offset: 0xF4 */ 5458 uint8_t RESERVED_8[8]; 5459 __IO uint32_t PIOPORACP; /**< POR captured PIO0 status 0, offset: 0x100 */ 5460 uint8_t RESERVED_9[76]; 5461 __IO uint32_t BODCTRL; /**< BOD control register, offset: 0x150 */ 5462 __IO uint32_t SYSTCKCAL; /**< System tick timer calibration register, offset: 0x154 */ 5463 uint8_t RESERVED_10[24]; 5464 __IO uint32_t IRQLATENCY; /**< IRQ latency register, offset: 0x170 */ 5465 __IO uint32_t NMISRC; /**< NMI source selection register, offset: 0x174 */ 5466 __IO uint32_t PINTSEL[8]; /**< Pin interrupt select registers N, array offset: 0x178, array step: 0x4 */ 5467 uint8_t RESERVED_11[108]; 5468 __IO uint32_t STARTERP0; /**< Start logic 0 pin wake-up enable register 0, offset: 0x204 */ 5469 uint8_t RESERVED_12[12]; 5470 __IO uint32_t STARTERP1; /**< Start logic 0 pin wake-up enable register 1, offset: 0x214 */ 5471 uint8_t RESERVED_13[24]; 5472 __IO uint32_t PDSLEEPCFG; /**< Deep-sleep configuration register, offset: 0x230 */ 5473 __IO uint32_t PDAWAKECFG; /**< Wake-up configuration register, offset: 0x234 */ 5474 __IO uint32_t PDRUNCFG; /**< Power configuration register, offset: 0x238 */ 5475 uint8_t RESERVED_14[444]; 5476 __I uint32_t DEVICE_ID; /**< Device ID register, offset: 0x3F8 */ 5477 } SYSCON_Type; 5478 5479 /* ---------------------------------------------------------------------------- 5480 -- SYSCON Register Masks 5481 ---------------------------------------------------------------------------- */ 5482 5483 /*! 5484 * @addtogroup SYSCON_Register_Masks SYSCON Register Masks 5485 * @{ 5486 */ 5487 5488 /*! @name SYSMEMREMAP - System Remap register */ 5489 /*! @{ */ 5490 #define SYSCON_SYSMEMREMAP_MAP_MASK (0x3U) 5491 #define SYSCON_SYSMEMREMAP_MAP_SHIFT (0U) 5492 /*! MAP - System memory remap. Value 0x2 is reserved. 5493 * 0b00..Boot Loader Mode. Interrupt vectors are re-mapped to Boot ROM. 5494 * 0b01..User RAM Mode. Interrupt vectors are re-mapped to Static RAM. 5495 * 0b10..User Flash Mode. Interrupt vectors are not re-mapped and reside in Flash. 5496 */ 5497 #define SYSCON_SYSMEMREMAP_MAP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSMEMREMAP_MAP_SHIFT)) & SYSCON_SYSMEMREMAP_MAP_MASK) 5498 /*! @} */ 5499 5500 /*! @name SYSRSTSTAT - System reset status register. */ 5501 /*! @{ */ 5502 #define SYSCON_SYSRSTSTAT_POR_BOD_MASK (0x1U) 5503 #define SYSCON_SYSRSTSTAT_POR_BOD_SHIFT (0U) 5504 /*! POR_BOD - POR and BOD reset status 5505 */ 5506 #define SYSCON_SYSRSTSTAT_POR_BOD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSRSTSTAT_POR_BOD_SHIFT)) & SYSCON_SYSRSTSTAT_POR_BOD_MASK) 5507 #define SYSCON_SYSRSTSTAT_EXTRST_MASK (0x2U) 5508 #define SYSCON_SYSRSTSTAT_EXTRST_SHIFT (1U) 5509 /*! EXTRST - Status of the external RESET pin 5510 * 0b0.. 5511 */ 5512 #define SYSCON_SYSRSTSTAT_EXTRST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSRSTSTAT_EXTRST_SHIFT)) & SYSCON_SYSRSTSTAT_EXTRST_MASK) 5513 #define SYSCON_SYSRSTSTAT_WDT_MASK (0x4U) 5514 #define SYSCON_SYSRSTSTAT_WDT_SHIFT (2U) 5515 /*! WDT - Status of the Watchdog reset. 5516 */ 5517 #define SYSCON_SYSRSTSTAT_WDT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSRSTSTAT_WDT_SHIFT)) & SYSCON_SYSRSTSTAT_WDT_MASK) 5518 #define SYSCON_SYSRSTSTAT_SYSRST_MASK (0x10U) 5519 #define SYSCON_SYSRSTSTAT_SYSRST_SHIFT (4U) 5520 /*! SYSRST - Status of the software system reset. 5521 */ 5522 #define SYSCON_SYSRSTSTAT_SYSRST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSRSTSTAT_SYSRST_SHIFT)) & SYSCON_SYSRSTSTAT_SYSRST_MASK) 5523 /*! @} */ 5524 5525 /*! @name MAINCLKSEL - Main clock source select register */ 5526 /*! @{ */ 5527 #define SYSCON_MAINCLKSEL_SEL_MASK (0x3U) 5528 #define SYSCON_MAINCLKSEL_SEL_SHIFT (0U) 5529 /*! SEL - Clock source for main clock. 5530 * 0b00..FRO. 5531 * 0b01..External clock. 5532 * 0b10..Low power oscillator. 5533 * 0b11..FRO_DIV. 5534 */ 5535 #define SYSCON_MAINCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MAINCLKSEL_SEL_SHIFT)) & SYSCON_MAINCLKSEL_SEL_MASK) 5536 /*! @} */ 5537 5538 /*! @name MAINCLKUEN - Main clock source update enable register. */ 5539 /*! @{ */ 5540 #define SYSCON_MAINCLKUEN_ENA_MASK (0x1U) 5541 #define SYSCON_MAINCLKUEN_ENA_SHIFT (0U) 5542 /*! ENA - Enable main clock source update 5543 * 0b0..no change 5544 * 0b1..update clock source 5545 */ 5546 #define SYSCON_MAINCLKUEN_ENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MAINCLKUEN_ENA_SHIFT)) & SYSCON_MAINCLKUEN_ENA_MASK) 5547 /*! @} */ 5548 5549 /*! @name SYSAHBCLKDIV - System clock divider register */ 5550 /*! @{ */ 5551 #define SYSCON_SYSAHBCLKDIV_DIV_MASK (0xFFU) 5552 #define SYSCON_SYSAHBCLKDIV_DIV_SHIFT (0U) 5553 /*! DIV - System AHB clock divider values 0: System clock disabled. 1: Divide by 1. to 255: Divide by 255. 5554 */ 5555 #define SYSCON_SYSAHBCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSAHBCLKDIV_DIV_SHIFT)) & SYSCON_SYSAHBCLKDIV_DIV_MASK) 5556 /*! @} */ 5557 5558 /*! @name CAPTCLKSEL - Capacitive Touch clock source select. */ 5559 /*! @{ */ 5560 #define SYSCON_CAPTCLKSEL_SEL_MASK (0x7U) 5561 #define SYSCON_CAPTCLKSEL_SEL_SHIFT (0U) 5562 /*! SEL - Peripheral clock source. 5563 * 0b000..FRO 5564 * 0b001..Main clock 5565 * 0b010..Reserved 5566 * 0b011..FRO_DIV = FRO/2 5567 * 0b100..Low power oscillator 5568 * 0b101..Reserved 5569 * 0b110..Reserved 5570 * 0b111..None 5571 */ 5572 #define SYSCON_CAPTCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CAPTCLKSEL_SEL_SHIFT)) & SYSCON_CAPTCLKSEL_SEL_MASK) 5573 /*! @} */ 5574 5575 /*! @name ADCCLKSEL - ADC clock source select register */ 5576 /*! @{ */ 5577 #define SYSCON_ADCCLKSEL_SEL_MASK (0x3U) 5578 #define SYSCON_ADCCLKSEL_SEL_SHIFT (0U) 5579 /*! SEL - Clock source for ADC clock 5580 * 0b00..FRO 5581 * 0b01..External clock 5582 * 0b10..Reserved 5583 * 0b11..None 5584 */ 5585 #define SYSCON_ADCCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKSEL_SEL_SHIFT)) & SYSCON_ADCCLKSEL_SEL_MASK) 5586 /*! @} */ 5587 5588 /*! @name ADCCLKDIV - ADC clock divider register */ 5589 /*! @{ */ 5590 #define SYSCON_ADCCLKDIV_DIV_MASK (0xFFU) 5591 #define SYSCON_ADCCLKDIV_DIV_SHIFT (0U) 5592 /*! DIV - ADC clock divider values 0: ADC clock disabled. 1: Divide by 1. to 255: Divide by 255. 5593 */ 5594 #define SYSCON_ADCCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_DIV_SHIFT)) & SYSCON_ADCCLKDIV_DIV_MASK) 5595 /*! @} */ 5596 5597 /*! @name LPOSCCLKEN - WDT and Wake Timer clock enable control. */ 5598 /*! @{ */ 5599 #define SYSCON_LPOSCCLKEN_WDT_MASK (0x1U) 5600 #define SYSCON_LPOSCCLKEN_WDT_SHIFT (0U) 5601 /*! WDT - Enables clock for WDT 5602 * 0b0..Disable 5603 * 0b1..Enable 5604 */ 5605 #define SYSCON_LPOSCCLKEN_WDT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_LPOSCCLKEN_WDT_SHIFT)) & SYSCON_LPOSCCLKEN_WDT_MASK) 5606 #define SYSCON_LPOSCCLKEN_WKT_MASK (0x2U) 5607 #define SYSCON_LPOSCCLKEN_WKT_SHIFT (1U) 5608 /*! WKT - Enables clock for Wake Timer 5609 * 0b0..Disable 5610 * 0b1..Enable 5611 */ 5612 #define SYSCON_LPOSCCLKEN_WKT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_LPOSCCLKEN_WKT_SHIFT)) & SYSCON_LPOSCCLKEN_WKT_MASK) 5613 /*! @} */ 5614 5615 /*! @name SYSAHBCLKCTRL0 - System clock group 0 control register */ 5616 /*! @{ */ 5617 #define SYSCON_SYSAHBCLKCTRL0_SYS_MASK (0x1U) 5618 #define SYSCON_SYSAHBCLKCTRL0_SYS_SHIFT (0U) 5619 /*! SYS - Enables the clock for the AHB, the APB bridge, the Cortex-M0+ core clocks, SYSCON, and the 5620 * PMU. This bit is read only and always reads as 1. 5621 */ 5622 #define SYSCON_SYSAHBCLKCTRL0_SYS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSAHBCLKCTRL0_SYS_SHIFT)) & SYSCON_SYSAHBCLKCTRL0_SYS_MASK) 5623 #define SYSCON_SYSAHBCLKCTRL0_ROM_MASK (0x2U) 5624 #define SYSCON_SYSAHBCLKCTRL0_ROM_SHIFT (1U) 5625 /*! ROM - Enables clock for ROM. 5626 * 0b0..disable 5627 * 0b1..enable 5628 */ 5629 #define SYSCON_SYSAHBCLKCTRL0_ROM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSAHBCLKCTRL0_ROM_SHIFT)) & SYSCON_SYSAHBCLKCTRL0_ROM_MASK) 5630 #define SYSCON_SYSAHBCLKCTRL0_RAM0_MASK (0x4U) 5631 #define SYSCON_SYSAHBCLKCTRL0_RAM0_SHIFT (2U) 5632 /*! RAM0 - Enables clock for SRAM0 5633 * 0b0..disable 5634 * 0b1..enable 5635 */ 5636 #define SYSCON_SYSAHBCLKCTRL0_RAM0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSAHBCLKCTRL0_RAM0_SHIFT)) & SYSCON_SYSAHBCLKCTRL0_RAM0_MASK) 5637 #define SYSCON_SYSAHBCLKCTRL0_FLASH_MASK (0x10U) 5638 #define SYSCON_SYSAHBCLKCTRL0_FLASH_SHIFT (4U) 5639 /*! FLASH - Enables clock for flash. 5640 * 0b0..disable 5641 * 0b1..enable 5642 */ 5643 #define SYSCON_SYSAHBCLKCTRL0_FLASH(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSAHBCLKCTRL0_FLASH_SHIFT)) & SYSCON_SYSAHBCLKCTRL0_FLASH_MASK) 5644 #define SYSCON_SYSAHBCLKCTRL0_I2C0_MASK (0x20U) 5645 #define SYSCON_SYSAHBCLKCTRL0_I2C0_SHIFT (5U) 5646 /*! I2C0 - Enables clock for I2C0. 5647 * 0b0..disable 5648 * 0b1..enable 5649 */ 5650 #define SYSCON_SYSAHBCLKCTRL0_I2C0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSAHBCLKCTRL0_I2C0_SHIFT)) & SYSCON_SYSAHBCLKCTRL0_I2C0_MASK) 5651 #define SYSCON_SYSAHBCLKCTRL0_GPIO0_MASK (0x40U) 5652 #define SYSCON_SYSAHBCLKCTRL0_GPIO0_SHIFT (6U) 5653 /*! GPIO0 - Enables clock for GPIO0 port registers. 5654 * 0b0..disable 5655 * 0b1..enable 5656 */ 5657 #define SYSCON_SYSAHBCLKCTRL0_GPIO0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSAHBCLKCTRL0_GPIO0_SHIFT)) & SYSCON_SYSAHBCLKCTRL0_GPIO0_MASK) 5658 #define SYSCON_SYSAHBCLKCTRL0_SWM_MASK (0x80U) 5659 #define SYSCON_SYSAHBCLKCTRL0_SWM_SHIFT (7U) 5660 /*! SWM - Enables clock for switch matrix. 5661 * 0b0..disable 5662 * 0b1..enable 5663 */ 5664 #define SYSCON_SYSAHBCLKCTRL0_SWM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSAHBCLKCTRL0_SWM_SHIFT)) & SYSCON_SYSAHBCLKCTRL0_SWM_MASK) 5665 #define SYSCON_SYSAHBCLKCTRL0_WKT_MASK (0x200U) 5666 #define SYSCON_SYSAHBCLKCTRL0_WKT_SHIFT (9U) 5667 /*! WKT - Enables clock for self-wake-up timer. 5668 * 0b0..disable 5669 * 0b1..enable 5670 */ 5671 #define SYSCON_SYSAHBCLKCTRL0_WKT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSAHBCLKCTRL0_WKT_SHIFT)) & SYSCON_SYSAHBCLKCTRL0_WKT_MASK) 5672 #define SYSCON_SYSAHBCLKCTRL0_MRT_MASK (0x400U) 5673 #define SYSCON_SYSAHBCLKCTRL0_MRT_SHIFT (10U) 5674 /*! MRT - Enables clock for multi-rate timer. 5675 * 0b0..disable 5676 * 0b1..enable 5677 */ 5678 #define SYSCON_SYSAHBCLKCTRL0_MRT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSAHBCLKCTRL0_MRT_SHIFT)) & SYSCON_SYSAHBCLKCTRL0_MRT_MASK) 5679 #define SYSCON_SYSAHBCLKCTRL0_SPI0_MASK (0x800U) 5680 #define SYSCON_SYSAHBCLKCTRL0_SPI0_SHIFT (11U) 5681 /*! SPI0 - Enables clock for SPI0. 5682 * 0b0..disable 5683 * 0b1..enable 5684 */ 5685 #define SYSCON_SYSAHBCLKCTRL0_SPI0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSAHBCLKCTRL0_SPI0_SHIFT)) & SYSCON_SYSAHBCLKCTRL0_SPI0_MASK) 5686 #define SYSCON_SYSAHBCLKCTRL0_CRC_MASK (0x2000U) 5687 #define SYSCON_SYSAHBCLKCTRL0_CRC_SHIFT (13U) 5688 /*! CRC - Enables clock for CRC. 5689 * 0b0..disable 5690 * 0b1..enable 5691 */ 5692 #define SYSCON_SYSAHBCLKCTRL0_CRC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSAHBCLKCTRL0_CRC_SHIFT)) & SYSCON_SYSAHBCLKCTRL0_CRC_MASK) 5693 #define SYSCON_SYSAHBCLKCTRL0_UART0_MASK (0x4000U) 5694 #define SYSCON_SYSAHBCLKCTRL0_UART0_SHIFT (14U) 5695 /*! UART0 - Enables clock for UART0. 5696 * 0b0..disable 5697 * 0b1..enable 5698 */ 5699 #define SYSCON_SYSAHBCLKCTRL0_UART0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSAHBCLKCTRL0_UART0_SHIFT)) & SYSCON_SYSAHBCLKCTRL0_UART0_MASK) 5700 #define SYSCON_SYSAHBCLKCTRL0_UART1_MASK (0x8000U) 5701 #define SYSCON_SYSAHBCLKCTRL0_UART1_SHIFT (15U) 5702 /*! UART1 - Enables clock for UART1. 5703 * 0b0..disable 5704 * 0b1..enable 5705 */ 5706 #define SYSCON_SYSAHBCLKCTRL0_UART1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSAHBCLKCTRL0_UART1_SHIFT)) & SYSCON_SYSAHBCLKCTRL0_UART1_MASK) 5707 #define SYSCON_SYSAHBCLKCTRL0_WWDT_MASK (0x20000U) 5708 #define SYSCON_SYSAHBCLKCTRL0_WWDT_SHIFT (17U) 5709 /*! WWDT - Enables clock for WWDT. 5710 * 0b0..disable 5711 * 0b1..enable 5712 */ 5713 #define SYSCON_SYSAHBCLKCTRL0_WWDT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSAHBCLKCTRL0_WWDT_SHIFT)) & SYSCON_SYSAHBCLKCTRL0_WWDT_MASK) 5714 #define SYSCON_SYSAHBCLKCTRL0_IOCON_MASK (0x40000U) 5715 #define SYSCON_SYSAHBCLKCTRL0_IOCON_SHIFT (18U) 5716 /*! IOCON - Enables clock for IOCON. 5717 * 0b0..disable 5718 * 0b1..enable 5719 */ 5720 #define SYSCON_SYSAHBCLKCTRL0_IOCON(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSAHBCLKCTRL0_IOCON_SHIFT)) & SYSCON_SYSAHBCLKCTRL0_IOCON_MASK) 5721 #define SYSCON_SYSAHBCLKCTRL0_ACMP_MASK (0x80000U) 5722 #define SYSCON_SYSAHBCLKCTRL0_ACMP_SHIFT (19U) 5723 /*! ACMP - Enables clock for analog comparator. 5724 * 0b0..disable 5725 * 0b1..enable 5726 */ 5727 #define SYSCON_SYSAHBCLKCTRL0_ACMP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSAHBCLKCTRL0_ACMP_SHIFT)) & SYSCON_SYSAHBCLKCTRL0_ACMP_MASK) 5728 #define SYSCON_SYSAHBCLKCTRL0_I2C1_MASK (0x200000U) 5729 #define SYSCON_SYSAHBCLKCTRL0_I2C1_SHIFT (21U) 5730 /*! I2C1 - Enables clock for I2C1. 5731 * 0b0..disable 5732 * 0b1..enable 5733 */ 5734 #define SYSCON_SYSAHBCLKCTRL0_I2C1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSAHBCLKCTRL0_I2C1_SHIFT)) & SYSCON_SYSAHBCLKCTRL0_I2C1_MASK) 5735 #define SYSCON_SYSAHBCLKCTRL0_ADC_MASK (0x1000000U) 5736 #define SYSCON_SYSAHBCLKCTRL0_ADC_SHIFT (24U) 5737 /*! ADC - Enables clock for ADC. 5738 * 0b0..disable 5739 * 0b1..enable 5740 */ 5741 #define SYSCON_SYSAHBCLKCTRL0_ADC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSAHBCLKCTRL0_ADC_SHIFT)) & SYSCON_SYSAHBCLKCTRL0_ADC_MASK) 5742 #define SYSCON_SYSAHBCLKCTRL0_CTIMER_MASK (0x2000000U) 5743 #define SYSCON_SYSAHBCLKCTRL0_CTIMER_SHIFT (25U) 5744 /*! CTIMER - Enables clock for CTIMER. 5745 * 0b0..disable 5746 * 0b1..enable 5747 */ 5748 #define SYSCON_SYSAHBCLKCTRL0_CTIMER(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSAHBCLKCTRL0_CTIMER_SHIFT)) & SYSCON_SYSAHBCLKCTRL0_CTIMER_MASK) 5749 #define SYSCON_SYSAHBCLKCTRL0_DAC_MASK (0x8000000U) 5750 #define SYSCON_SYSAHBCLKCTRL0_DAC_SHIFT (27U) 5751 /*! DAC - Enables clock for DAC. 5752 * 0b0..disable 5753 * 0b1..enable 5754 */ 5755 #define SYSCON_SYSAHBCLKCTRL0_DAC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSAHBCLKCTRL0_DAC_SHIFT)) & SYSCON_SYSAHBCLKCTRL0_DAC_MASK) 5756 #define SYSCON_SYSAHBCLKCTRL0_GPIO_INT_MASK (0x10000000U) 5757 #define SYSCON_SYSAHBCLKCTRL0_GPIO_INT_SHIFT (28U) 5758 /*! GPIO_INT - Enable clock for GPIO pin interrupt registers 5759 * 0b0..disable 5760 * 0b1..enable 5761 */ 5762 #define SYSCON_SYSAHBCLKCTRL0_GPIO_INT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSAHBCLKCTRL0_GPIO_INT_SHIFT)) & SYSCON_SYSAHBCLKCTRL0_GPIO_INT_MASK) 5763 /*! @} */ 5764 5765 /*! @name SYSAHBCLKCTRL1 - System clock group 1 control register */ 5766 /*! @{ */ 5767 #define SYSCON_SYSAHBCLKCTRL1_CAPT_MASK (0x1U) 5768 #define SYSCON_SYSAHBCLKCTRL1_CAPT_SHIFT (0U) 5769 /*! CAPT - Enables the clock for Capacitive Touch. 5770 */ 5771 #define SYSCON_SYSAHBCLKCTRL1_CAPT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSAHBCLKCTRL1_CAPT_SHIFT)) & SYSCON_SYSAHBCLKCTRL1_CAPT_MASK) 5772 #define SYSCON_SYSAHBCLKCTRL1_PLU_MASK (0x20U) 5773 #define SYSCON_SYSAHBCLKCTRL1_PLU_SHIFT (5U) 5774 /*! PLU - Enables clock for PLU. 5775 * 0b0..disable 5776 * 0b1..enable 5777 */ 5778 #define SYSCON_SYSAHBCLKCTRL1_PLU(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSAHBCLKCTRL1_PLU_SHIFT)) & SYSCON_SYSAHBCLKCTRL1_PLU_MASK) 5779 /*! @} */ 5780 5781 /*! @name PRESETCTRL0 - Peripheral reset group 0 control register */ 5782 /*! @{ */ 5783 #define SYSCON_PRESETCTRL0_FLASH_RST_N_MASK (0x10U) 5784 #define SYSCON_PRESETCTRL0_FLASH_RST_N_SHIFT (4U) 5785 /*! FLASH_RST_N - flash controller reset control 5786 * 0b0..Assert the flash controller reset. 5787 * 0b1..Clear the flash controller reset. 5788 */ 5789 #define SYSCON_PRESETCTRL0_FLASH_RST_N(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_FLASH_RST_N_SHIFT)) & SYSCON_PRESETCTRL0_FLASH_RST_N_MASK) 5790 #define SYSCON_PRESETCTRL0_I2C0_RST_N_MASK (0x20U) 5791 #define SYSCON_PRESETCTRL0_I2C0_RST_N_SHIFT (5U) 5792 /*! I2C0_RST_N - I2C0 reset control 5793 * 0b0..Assert the I2C0 reset. 5794 * 0b1..Clear the I2C0 reset. 5795 */ 5796 #define SYSCON_PRESETCTRL0_I2C0_RST_N(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_I2C0_RST_N_SHIFT)) & SYSCON_PRESETCTRL0_I2C0_RST_N_MASK) 5797 #define SYSCON_PRESETCTRL0_GPIO0_RST_N_MASK (0x40U) 5798 #define SYSCON_PRESETCTRL0_GPIO0_RST_N_SHIFT (6U) 5799 /*! GPIO0_RST_N - GPIO0 reset control 5800 * 0b0..Assert the GPIO0 reset. 5801 * 0b1..Clear the GPIO0 reset. 5802 */ 5803 #define SYSCON_PRESETCTRL0_GPIO0_RST_N(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_GPIO0_RST_N_SHIFT)) & SYSCON_PRESETCTRL0_GPIO0_RST_N_MASK) 5804 #define SYSCON_PRESETCTRL0_SWM_RST_N_MASK (0x80U) 5805 #define SYSCON_PRESETCTRL0_SWM_RST_N_SHIFT (7U) 5806 /*! SWM_RST_N - SWM reset control 5807 * 0b0..Assert the SWM reset. 5808 * 0b1..Clear the SWM reset. 5809 */ 5810 #define SYSCON_PRESETCTRL0_SWM_RST_N(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_SWM_RST_N_SHIFT)) & SYSCON_PRESETCTRL0_SWM_RST_N_MASK) 5811 #define SYSCON_PRESETCTRL0_WKT_RST_N_MASK (0x200U) 5812 #define SYSCON_PRESETCTRL0_WKT_RST_N_SHIFT (9U) 5813 /*! WKT_RST_N - Self-wake-up timer (WKT) reset control 5814 * 0b0..Assert the WKT reset. 5815 * 0b1..Clear the WKT reset. 5816 */ 5817 #define SYSCON_PRESETCTRL0_WKT_RST_N(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_WKT_RST_N_SHIFT)) & SYSCON_PRESETCTRL0_WKT_RST_N_MASK) 5818 #define SYSCON_PRESETCTRL0_MRT_RST_N_MASK (0x400U) 5819 #define SYSCON_PRESETCTRL0_MRT_RST_N_SHIFT (10U) 5820 /*! MRT_RST_N - Multi-rate timer (MRT) reset control 5821 * 0b0..Assert the MRT reset. 5822 * 0b1..Clear the MRT reset. 5823 */ 5824 #define SYSCON_PRESETCTRL0_MRT_RST_N(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_MRT_RST_N_SHIFT)) & SYSCON_PRESETCTRL0_MRT_RST_N_MASK) 5825 #define SYSCON_PRESETCTRL0_SPI0_RST_N_MASK (0x800U) 5826 #define SYSCON_PRESETCTRL0_SPI0_RST_N_SHIFT (11U) 5827 /*! SPI0_RST_N - SPI0 reset control 5828 * 0b0..Assert the SPI0 reset. 5829 * 0b1..Clear the SPI0 reset. 5830 */ 5831 #define SYSCON_PRESETCTRL0_SPI0_RST_N(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_SPI0_RST_N_SHIFT)) & SYSCON_PRESETCTRL0_SPI0_RST_N_MASK) 5832 #define SYSCON_PRESETCTRL0_CRC_RST_N_MASK (0x2000U) 5833 #define SYSCON_PRESETCTRL0_CRC_RST_N_SHIFT (13U) 5834 /*! CRC_RST_N - CRC engine reset control 5835 * 0b0..Assert the CRC reset. 5836 * 0b1..Clear the CRC reset. 5837 */ 5838 #define SYSCON_PRESETCTRL0_CRC_RST_N(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_CRC_RST_N_SHIFT)) & SYSCON_PRESETCTRL0_CRC_RST_N_MASK) 5839 #define SYSCON_PRESETCTRL0_UART0_RST_N_MASK (0x4000U) 5840 #define SYSCON_PRESETCTRL0_UART0_RST_N_SHIFT (14U) 5841 /*! UART0_RST_N - UART0 reset control 5842 * 0b0..Assert the UART0 reset. 5843 * 0b1..Clear the UART0 reset. 5844 */ 5845 #define SYSCON_PRESETCTRL0_UART0_RST_N(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_UART0_RST_N_SHIFT)) & SYSCON_PRESETCTRL0_UART0_RST_N_MASK) 5846 #define SYSCON_PRESETCTRL0_UART1_RST_N_MASK (0x8000U) 5847 #define SYSCON_PRESETCTRL0_UART1_RST_N_SHIFT (15U) 5848 /*! UART1_RST_N - UART1 reset control 5849 * 0b0..Assert the UART1 reset. 5850 * 0b1..Clear the UART1 reset. 5851 */ 5852 #define SYSCON_PRESETCTRL0_UART1_RST_N(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_UART1_RST_N_SHIFT)) & SYSCON_PRESETCTRL0_UART1_RST_N_MASK) 5853 #define SYSCON_PRESETCTRL0_IOCON_RST_N_MASK (0x40000U) 5854 #define SYSCON_PRESETCTRL0_IOCON_RST_N_SHIFT (18U) 5855 /*! IOCON_RST_N - IOCON reset control 5856 * 0b0..Assert the IOCON reset. 5857 * 0b1..Clear the IOCON reset. 5858 */ 5859 #define SYSCON_PRESETCTRL0_IOCON_RST_N(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_IOCON_RST_N_SHIFT)) & SYSCON_PRESETCTRL0_IOCON_RST_N_MASK) 5860 #define SYSCON_PRESETCTRL0_ACMP_RST_N_MASK (0x80000U) 5861 #define SYSCON_PRESETCTRL0_ACMP_RST_N_SHIFT (19U) 5862 /*! ACMP_RST_N - Analog comparator reset control 5863 * 0b0..Assert the analog comparator reset. 5864 * 0b1..Clear the analog comparator reset. 5865 */ 5866 #define SYSCON_PRESETCTRL0_ACMP_RST_N(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_ACMP_RST_N_SHIFT)) & SYSCON_PRESETCTRL0_ACMP_RST_N_MASK) 5867 #define SYSCON_PRESETCTRL0_I2C1_RST_N_MASK (0x200000U) 5868 #define SYSCON_PRESETCTRL0_I2C1_RST_N_SHIFT (21U) 5869 /*! I2C1_RST_N - I2C1 reset control. 5870 * 0b0..Assert the I2C1 reset. 5871 * 0b1..Clear the I2C1 reset. 5872 */ 5873 #define SYSCON_PRESETCTRL0_I2C1_RST_N(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_I2C1_RST_N_SHIFT)) & SYSCON_PRESETCTRL0_I2C1_RST_N_MASK) 5874 #define SYSCON_PRESETCTRL0_ADC_RST_N_MASK (0x1000000U) 5875 #define SYSCON_PRESETCTRL0_ADC_RST_N_SHIFT (24U) 5876 /*! ADC_RST_N - ADC reset control 5877 * 0b0..Assert the ADC reset. 5878 * 0b1..Clear the ADC reset. 5879 */ 5880 #define SYSCON_PRESETCTRL0_ADC_RST_N(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_ADC_RST_N_SHIFT)) & SYSCON_PRESETCTRL0_ADC_RST_N_MASK) 5881 #define SYSCON_PRESETCTRL0_CTIMER0_RST_N_MASK (0x2000000U) 5882 #define SYSCON_PRESETCTRL0_CTIMER0_RST_N_SHIFT (25U) 5883 /*! CTIMER0_RST_N - CTIMER reset control 5884 * 0b0..Assert the CTIMER reset. 5885 * 0b1..Clear the CTIMER reset. 5886 */ 5887 #define SYSCON_PRESETCTRL0_CTIMER0_RST_N(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_CTIMER0_RST_N_SHIFT)) & SYSCON_PRESETCTRL0_CTIMER0_RST_N_MASK) 5888 #define SYSCON_PRESETCTRL0_DAC0_RST_N_MASK (0x8000000U) 5889 #define SYSCON_PRESETCTRL0_DAC0_RST_N_SHIFT (27U) 5890 /*! DAC0_RST_N - DAC0 reset control. 5891 * 0b0..Assert the DAC0 reset. 5892 * 0b1..Clear the DAC0 reset. 5893 */ 5894 #define SYSCON_PRESETCTRL0_DAC0_RST_N(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_DAC0_RST_N_SHIFT)) & SYSCON_PRESETCTRL0_DAC0_RST_N_MASK) 5895 #define SYSCON_PRESETCTRL0_GPIOINT_RST_N_MASK (0x10000000U) 5896 #define SYSCON_PRESETCTRL0_GPIOINT_RST_N_SHIFT (28U) 5897 /*! GPIOINT_RST_N - GPIOINT reset control 5898 * 0b0..Assert the GPIOINT reset. 5899 * 0b1..Clear the GPIOINT reset. 5900 */ 5901 #define SYSCON_PRESETCTRL0_GPIOINT_RST_N(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL0_GPIOINT_RST_N_SHIFT)) & SYSCON_PRESETCTRL0_GPIOINT_RST_N_MASK) 5902 /*! @} */ 5903 5904 /*! @name PRESETCTRL1 - Peripheral reset group 1 control register */ 5905 /*! @{ */ 5906 #define SYSCON_PRESETCTRL1_CAPT_RST_N_MASK (0x1U) 5907 #define SYSCON_PRESETCTRL1_CAPT_RST_N_SHIFT (0U) 5908 /*! CAPT_RST_N - Capacitive Touch reset control. 5909 * 0b0..Assert Capacitive Touch reset. 5910 * 0b1..Clear Capacitive Touch reset. 5911 */ 5912 #define SYSCON_PRESETCTRL1_CAPT_RST_N(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_CAPT_RST_N_SHIFT)) & SYSCON_PRESETCTRL1_CAPT_RST_N_MASK) 5913 #define SYSCON_PRESETCTRL1_FRG0_RST_N_MASK (0x8U) 5914 #define SYSCON_PRESETCTRL1_FRG0_RST_N_SHIFT (3U) 5915 /*! FRG0_RST_N - Fractional baud rate generator 0 reset control 5916 * 0b0..Assert the FRG0 reset. 5917 * 0b1..Clear the FRG0 reset. 5918 */ 5919 #define SYSCON_PRESETCTRL1_FRG0_RST_N(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_FRG0_RST_N_SHIFT)) & SYSCON_PRESETCTRL1_FRG0_RST_N_MASK) 5920 #define SYSCON_PRESETCTRL1_PLU_RST_N_MASK (0x20U) 5921 #define SYSCON_PRESETCTRL1_PLU_RST_N_SHIFT (5U) 5922 /*! PLU_RST_N - PLU reset control. 5923 * 0b0..Assert PLU reset. 5924 * 0b1..Clear PLU reset. 5925 */ 5926 #define SYSCON_PRESETCTRL1_PLU_RST_N(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL1_PLU_RST_N_SHIFT)) & SYSCON_PRESETCTRL1_PLU_RST_N_MASK) 5927 /*! @} */ 5928 5929 /*! @name UART0CLKSEL - Function clock source select for UART0. */ 5930 /*! @{ */ 5931 #define SYSCON_UART0CLKSEL_SEL_MASK (0x7U) 5932 #define SYSCON_UART0CLKSEL_SEL_SHIFT (0U) 5933 /*! SEL - Peripheral clock source 5934 * 0b000..FRO 5935 * 0b001..main clock 5936 * 0b010..Frg0clk 5937 * 0b011..none 5938 * 0b100..FRO_DIV 5939 * 0b101..none 5940 * 0b110..none 5941 * 0b111..none 5942 */ 5943 #define SYSCON_UART0CLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_UART0CLKSEL_SEL_SHIFT)) & SYSCON_UART0CLKSEL_SEL_MASK) 5944 /*! @} */ 5945 5946 /*! @name UART1CLKSEL - Function clock source select for UART1. */ 5947 /*! @{ */ 5948 #define SYSCON_UART1CLKSEL_SEL_MASK (0x7U) 5949 #define SYSCON_UART1CLKSEL_SEL_SHIFT (0U) 5950 /*! SEL - Peripheral clock source 5951 * 0b000..FRO 5952 * 0b001..main clock 5953 * 0b010..Frg0clk 5954 * 0b011..none 5955 * 0b100..FRO_DIV 5956 * 0b101..none 5957 * 0b110..none 5958 * 0b111..none 5959 */ 5960 #define SYSCON_UART1CLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_UART1CLKSEL_SEL_SHIFT)) & SYSCON_UART1CLKSEL_SEL_MASK) 5961 /*! @} */ 5962 5963 /*! @name I2C0CLKSEL - Function clock source select for I2C0. */ 5964 /*! @{ */ 5965 #define SYSCON_I2C0CLKSEL_SEL_MASK (0x7U) 5966 #define SYSCON_I2C0CLKSEL_SEL_SHIFT (0U) 5967 /*! SEL - Peripheral clock source 5968 * 0b000..FRO 5969 * 0b001..main clock 5970 * 0b010..Frg0clk 5971 * 0b011..none 5972 * 0b100..FRO_DIV 5973 * 0b101..none 5974 * 0b110..none 5975 * 0b111..none 5976 */ 5977 #define SYSCON_I2C0CLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_I2C0CLKSEL_SEL_SHIFT)) & SYSCON_I2C0CLKSEL_SEL_MASK) 5978 /*! @} */ 5979 5980 /*! @name I2C1CLKSEL - Function clock source select for I2C1. */ 5981 /*! @{ */ 5982 #define SYSCON_I2C1CLKSEL_SEL_MASK (0x7U) 5983 #define SYSCON_I2C1CLKSEL_SEL_SHIFT (0U) 5984 /*! SEL - Peripheral clock source 5985 * 0b000..FRO 5986 * 0b001..main clock 5987 * 0b010..Frg0clk 5988 * 0b011..none 5989 * 0b100..FRO_DIV 5990 * 0b101..none 5991 * 0b110..none 5992 * 0b111..none 5993 */ 5994 #define SYSCON_I2C1CLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_I2C1CLKSEL_SEL_SHIFT)) & SYSCON_I2C1CLKSEL_SEL_MASK) 5995 /*! @} */ 5996 5997 /*! @name SPI0CLKSEL - Function clock source select for SPI0. */ 5998 /*! @{ */ 5999 #define SYSCON_SPI0CLKSEL_SEL_MASK (0x7U) 6000 #define SYSCON_SPI0CLKSEL_SEL_SHIFT (0U) 6001 /*! SEL - Peripheral clock source 6002 * 0b000..FRO 6003 * 0b001..main clock 6004 * 0b010..Frg0clk 6005 * 0b011..none 6006 * 0b100..FRO_DIV 6007 * 0b101..none 6008 * 0b110..none 6009 * 0b111..none 6010 */ 6011 #define SYSCON_SPI0CLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SPI0CLKSEL_SEL_SHIFT)) & SYSCON_SPI0CLKSEL_SEL_MASK) 6012 /*! @} */ 6013 6014 /*! @name FRG_FRGDIV - fractional generator divider value register */ 6015 /*! @{ */ 6016 #define SYSCON_FRG_FRGDIV_DIV_MASK (0xFFU) 6017 #define SYSCON_FRG_FRGDIV_DIV_SHIFT (0U) 6018 /*! DIV - Denominator of the fractional divider. DIV is equal to the programmed value +1. Always set 6019 * to 0xFF to use with the fractional baud rate generator. 6020 */ 6021 #define SYSCON_FRG_FRGDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FRG_FRGDIV_DIV_SHIFT)) & SYSCON_FRG_FRGDIV_DIV_MASK) 6022 /*! @} */ 6023 6024 /* The count of SYSCON_FRG_FRGDIV */ 6025 #define SYSCON_FRG_FRGDIV_COUNT (1U) 6026 6027 /*! @name FRG_FRGMULT - fractional generator multiplier value register */ 6028 /*! @{ */ 6029 #define SYSCON_FRG_FRGMULT_MULT_MASK (0xFFU) 6030 #define SYSCON_FRG_FRGMULT_MULT_SHIFT (0U) 6031 /*! MULT - Numerator of the fractional divider. MULT is equal to the programmed value. 6032 */ 6033 #define SYSCON_FRG_FRGMULT_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FRG_FRGMULT_MULT_SHIFT)) & SYSCON_FRG_FRGMULT_MULT_MASK) 6034 /*! @} */ 6035 6036 /* The count of SYSCON_FRG_FRGMULT */ 6037 #define SYSCON_FRG_FRGMULT_COUNT (1U) 6038 6039 /*! @name FRG_FRGCLKSEL - FRG clock source select register */ 6040 /*! @{ */ 6041 #define SYSCON_FRG_FRGCLKSEL_SEL_MASK (0x3U) 6042 #define SYSCON_FRG_FRGCLKSEL_SEL_SHIFT (0U) 6043 /*! SEL - Clock source for frgN_src clock 6044 * 0b00..FRO 6045 * 0b01..main clock 6046 * 0b10..Reserved 6047 * 0b11..None 6048 */ 6049 #define SYSCON_FRG_FRGCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FRG_FRGCLKSEL_SEL_SHIFT)) & SYSCON_FRG_FRGCLKSEL_SEL_MASK) 6050 /*! @} */ 6051 6052 /* The count of SYSCON_FRG_FRGCLKSEL */ 6053 #define SYSCON_FRG_FRGCLKSEL_COUNT (1U) 6054 6055 /*! @name CLKOUTSEL - CLKOUT clock source select register */ 6056 /*! @{ */ 6057 #define SYSCON_CLKOUTSEL_SEL_MASK (0x7U) 6058 #define SYSCON_CLKOUTSEL_SEL_SHIFT (0U) 6059 /*! SEL - CLKOUT clock source 6060 * 0b000..FRO 6061 * 0b001..main clock 6062 * 0b010..Reserved 6063 * 0b011..external clock 6064 * 0b100..Low power oscillator 6065 * 0b101..Reserved 6066 * 0b110..Reserved 6067 * 0b111..None 6068 */ 6069 #define SYSCON_CLKOUTSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTSEL_SEL_SHIFT)) & SYSCON_CLKOUTSEL_SEL_MASK) 6070 /*! @} */ 6071 6072 /*! @name CLKOUTDIV - CLKOUT clock divider registers */ 6073 /*! @{ */ 6074 #define SYSCON_CLKOUTDIV_DIV_MASK (0xFFU) 6075 #define SYSCON_CLKOUTDIV_DIV_SHIFT (0U) 6076 /*! DIV - CLKOUT clock divider values 0: Disable CLKOUT clock divider. 1: Divide by 1. to 255: Divide by 255. 6077 */ 6078 #define SYSCON_CLKOUTDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_DIV_SHIFT)) & SYSCON_CLKOUTDIV_DIV_MASK) 6079 /*! @} */ 6080 6081 /*! @name PIOPORACP - POR captured PIO0 status 0 */ 6082 /*! @{ */ 6083 #define SYSCON_PIOPORACP_PIOSTAT_MASK (0xFFFFFFFFU) 6084 #define SYSCON_PIOPORACP_PIOSTAT_SHIFT (0U) 6085 /*! PIOSTAT - State of PIO0_0 to PIO0_5 and PIO0_7 to PIO0_17 at power-on reset 6086 */ 6087 #define SYSCON_PIOPORACP_PIOSTAT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PIOPORACP_PIOSTAT_SHIFT)) & SYSCON_PIOPORACP_PIOSTAT_MASK) 6088 /*! @} */ 6089 6090 /*! @name BODCTRL - BOD control register */ 6091 /*! @{ */ 6092 #define SYSCON_BODCTRL_BODRSTLEV_MASK (0x3U) 6093 #define SYSCON_BODCTRL_BODRSTLEV_SHIFT (0U) 6094 /*! BODRSTLEV - BOD reset level 6095 * 0b00..Reserved 6096 * 0b01..Level 1 6097 * 0b10..Level 2 6098 * 0b11..Level 3 6099 */ 6100 #define SYSCON_BODCTRL_BODRSTLEV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODRSTLEV_SHIFT)) & SYSCON_BODCTRL_BODRSTLEV_MASK) 6101 #define SYSCON_BODCTRL_BODINTVAL_MASK (0xCU) 6102 #define SYSCON_BODCTRL_BODINTVAL_SHIFT (2U) 6103 /*! BODINTVAL - BOD interrupt level 6104 * 0b00..Reserved 6105 * 0b01..Level 1 6106 * 0b10..Level 2 6107 * 0b11..Level 3 6108 */ 6109 #define SYSCON_BODCTRL_BODINTVAL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODINTVAL_SHIFT)) & SYSCON_BODCTRL_BODINTVAL_MASK) 6110 #define SYSCON_BODCTRL_BODRSTENA_MASK (0x10U) 6111 #define SYSCON_BODCTRL_BODRSTENA_SHIFT (4U) 6112 /*! BODRSTENA - BOD reset enable 6113 * 0b0..Disable reset function. 6114 * 0b1..Enable reset function. 6115 */ 6116 #define SYSCON_BODCTRL_BODRSTENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODRSTENA_SHIFT)) & SYSCON_BODCTRL_BODRSTENA_MASK) 6117 /*! @} */ 6118 6119 /*! @name SYSTCKCAL - System tick timer calibration register */ 6120 /*! @{ */ 6121 #define SYSCON_SYSTCKCAL_CAL_MASK (0x3FFFFFFU) 6122 #define SYSCON_SYSTCKCAL_CAL_SHIFT (0U) 6123 /*! CAL - System tick timer calibration value. 6124 */ 6125 #define SYSCON_SYSTCKCAL_CAL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTCKCAL_CAL_SHIFT)) & SYSCON_SYSTCKCAL_CAL_MASK) 6126 /*! @} */ 6127 6128 /*! @name IRQLATENCY - IRQ latency register */ 6129 /*! @{ */ 6130 #define SYSCON_IRQLATENCY_LATENCY_MASK (0xFFU) 6131 #define SYSCON_IRQLATENCY_LATENCY_SHIFT (0U) 6132 /*! LATENCY - 8-bit latency value. 6133 */ 6134 #define SYSCON_IRQLATENCY_LATENCY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_IRQLATENCY_LATENCY_SHIFT)) & SYSCON_IRQLATENCY_LATENCY_MASK) 6135 /*! @} */ 6136 6137 /*! @name NMISRC - NMI source selection register */ 6138 /*! @{ */ 6139 #define SYSCON_NMISRC_IRQN_MASK (0x1FU) 6140 #define SYSCON_NMISRC_IRQN_SHIFT (0U) 6141 /*! IRQN - The IRQ number of the interrupt that acts as the Non-Maskable Interrupt (NMI) if bit 31 is 1 6142 */ 6143 #define SYSCON_NMISRC_IRQN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_IRQN_SHIFT)) & SYSCON_NMISRC_IRQN_MASK) 6144 #define SYSCON_NMISRC_NMIEN_MASK (0x80000000U) 6145 #define SYSCON_NMISRC_NMIEN_SHIFT (31U) 6146 /*! NMIEN - Write a 1 to this bit to enable the Non-Maskable Interrupt (NMI) source selected by bits 4:0. 6147 */ 6148 #define SYSCON_NMISRC_NMIEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_NMIEN_SHIFT)) & SYSCON_NMISRC_NMIEN_MASK) 6149 /*! @} */ 6150 6151 /*! @name PINTSEL - Pin interrupt select registers N */ 6152 /*! @{ */ 6153 #define SYSCON_PINTSEL_INTPIN_MASK (0x3FU) 6154 #define SYSCON_PINTSEL_INTPIN_SHIFT (0U) 6155 /*! INTPIN - Pin number select for pin interrupt or pattern match engine input. (PIO0_0 to PIO0_5 6156 * correspond to numbers 0 to 5. PIO0_7 to PIO0_30 correspond to numbers 7 to 30.) 6157 */ 6158 #define SYSCON_PINTSEL_INTPIN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PINTSEL_INTPIN_SHIFT)) & SYSCON_PINTSEL_INTPIN_MASK) 6159 /*! @} */ 6160 6161 /* The count of SYSCON_PINTSEL */ 6162 #define SYSCON_PINTSEL_COUNT (8U) 6163 6164 /*! @name STARTERP0 - Start logic 0 pin wake-up enable register 0 */ 6165 /*! @{ */ 6166 #define SYSCON_STARTERP0_PINT0_MASK (0x1U) 6167 #define SYSCON_STARTERP0_PINT0_SHIFT (0U) 6168 /*! PINT0 - GPIO pin interrupt 0 wake-up 6169 * 0b0..Disabled 6170 * 0b1..Enabled 6171 */ 6172 #define SYSCON_STARTERP0_PINT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP0_PINT0_SHIFT)) & SYSCON_STARTERP0_PINT0_MASK) 6173 #define SYSCON_STARTERP0_PINT1_MASK (0x2U) 6174 #define SYSCON_STARTERP0_PINT1_SHIFT (1U) 6175 /*! PINT1 - GPIO pin interrupt 1 wake-up 6176 * 0b0..Disabled 6177 * 0b1..Enabled 6178 */ 6179 #define SYSCON_STARTERP0_PINT1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP0_PINT1_SHIFT)) & SYSCON_STARTERP0_PINT1_MASK) 6180 #define SYSCON_STARTERP0_PINT2_MASK (0x4U) 6181 #define SYSCON_STARTERP0_PINT2_SHIFT (2U) 6182 /*! PINT2 - GPIO pin interrupt 2 wake-up 6183 * 0b0..Disabled 6184 * 0b1..Enabled 6185 */ 6186 #define SYSCON_STARTERP0_PINT2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP0_PINT2_SHIFT)) & SYSCON_STARTERP0_PINT2_MASK) 6187 #define SYSCON_STARTERP0_PINT3_MASK (0x8U) 6188 #define SYSCON_STARTERP0_PINT3_SHIFT (3U) 6189 /*! PINT3 - GPIO pin interrupt 3 wake-up 6190 * 0b0..Disabled 6191 * 0b1..Enabled 6192 */ 6193 #define SYSCON_STARTERP0_PINT3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP0_PINT3_SHIFT)) & SYSCON_STARTERP0_PINT3_MASK) 6194 #define SYSCON_STARTERP0_PINT4_MASK (0x10U) 6195 #define SYSCON_STARTERP0_PINT4_SHIFT (4U) 6196 /*! PINT4 - GPIO pin interrupt 4 wake-up 6197 * 0b0..Disabled 6198 * 0b1..Enabled 6199 */ 6200 #define SYSCON_STARTERP0_PINT4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP0_PINT4_SHIFT)) & SYSCON_STARTERP0_PINT4_MASK) 6201 #define SYSCON_STARTERP0_PINT5_MASK (0x20U) 6202 #define SYSCON_STARTERP0_PINT5_SHIFT (5U) 6203 /*! PINT5 - GPIO pin interrupt 5 wake-up 6204 * 0b0..Disabled 6205 * 0b1..Enabled 6206 */ 6207 #define SYSCON_STARTERP0_PINT5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP0_PINT5_SHIFT)) & SYSCON_STARTERP0_PINT5_MASK) 6208 #define SYSCON_STARTERP0_PINT6_MASK (0x40U) 6209 #define SYSCON_STARTERP0_PINT6_SHIFT (6U) 6210 /*! PINT6 - GPIO pin interrupt 6 wake-up 6211 * 0b0..Disabled 6212 * 0b1..Enabled 6213 */ 6214 #define SYSCON_STARTERP0_PINT6(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP0_PINT6_SHIFT)) & SYSCON_STARTERP0_PINT6_MASK) 6215 #define SYSCON_STARTERP0_PINT7_MASK (0x80U) 6216 #define SYSCON_STARTERP0_PINT7_SHIFT (7U) 6217 /*! PINT7 - GPIO pin interrupt 7 wake-up 6218 * 0b0..Disabled 6219 * 0b1..Enabled 6220 */ 6221 #define SYSCON_STARTERP0_PINT7(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP0_PINT7_SHIFT)) & SYSCON_STARTERP0_PINT7_MASK) 6222 /*! @} */ 6223 6224 /*! @name STARTERP1 - Start logic 0 pin wake-up enable register 1 */ 6225 /*! @{ */ 6226 #define SYSCON_STARTERP1_SPI0_MASK (0x1U) 6227 #define SYSCON_STARTERP1_SPI0_SHIFT (0U) 6228 /*! SPI0 - SPI0 interrupt wake-up 6229 * 0b0..Disabled 6230 * 0b1..Enabled 6231 */ 6232 #define SYSCON_STARTERP1_SPI0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP1_SPI0_SHIFT)) & SYSCON_STARTERP1_SPI0_MASK) 6233 #define SYSCON_STARTERP1_USART0_MASK (0x8U) 6234 #define SYSCON_STARTERP1_USART0_SHIFT (3U) 6235 /*! USART0 - USART0 interrupt wake-up. Configure USART in synchronous slave mode. 6236 * 0b0..Disabled 6237 * 0b1..Enabled 6238 */ 6239 #define SYSCON_STARTERP1_USART0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP1_USART0_SHIFT)) & SYSCON_STARTERP1_USART0_MASK) 6240 #define SYSCON_STARTERP1_USART1_MASK (0x10U) 6241 #define SYSCON_STARTERP1_USART1_SHIFT (4U) 6242 /*! USART1 - USART1 interrupt wake-up. Configure USART in synchronous slave mode. 6243 * 0b0..Disabled 6244 * 0b1..Enabled 6245 */ 6246 #define SYSCON_STARTERP1_USART1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP1_USART1_SHIFT)) & SYSCON_STARTERP1_USART1_MASK) 6247 #define SYSCON_STARTERP1_PLU_MASK (0x40U) 6248 #define SYSCON_STARTERP1_PLU_SHIFT (6U) 6249 /*! PLU - PLU interrupt wake-up. 6250 * 0b0..Disabled 6251 * 0b1..Enabled 6252 */ 6253 #define SYSCON_STARTERP1_PLU(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP1_PLU_SHIFT)) & SYSCON_STARTERP1_PLU_MASK) 6254 #define SYSCON_STARTERP1_I2C1_MASK (0x80U) 6255 #define SYSCON_STARTERP1_I2C1_SHIFT (7U) 6256 /*! I2C1 - I2C1 interrupt wake-up. 6257 * 0b0..Disabled 6258 * 0b1..Enabled 6259 */ 6260 #define SYSCON_STARTERP1_I2C1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP1_I2C1_SHIFT)) & SYSCON_STARTERP1_I2C1_MASK) 6261 #define SYSCON_STARTERP1_I2C0_MASK (0x100U) 6262 #define SYSCON_STARTERP1_I2C0_SHIFT (8U) 6263 /*! I2C0 - I2C0 interrupt wake-up. 6264 * 0b0..Disabled 6265 * 0b1..Enabled 6266 */ 6267 #define SYSCON_STARTERP1_I2C0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP1_I2C0_SHIFT)) & SYSCON_STARTERP1_I2C0_MASK) 6268 #define SYSCON_STARTERP1_CAPT_MASK (0x800U) 6269 #define SYSCON_STARTERP1_CAPT_SHIFT (11U) 6270 /*! CAPT - CAPT interrupt wake-up. 6271 * 0b0..Disabled 6272 * 0b1..Enabled 6273 */ 6274 #define SYSCON_STARTERP1_CAPT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP1_CAPT_SHIFT)) & SYSCON_STARTERP1_CAPT_MASK) 6275 #define SYSCON_STARTERP1_WWDT_MASK (0x1000U) 6276 #define SYSCON_STARTERP1_WWDT_SHIFT (12U) 6277 /*! WWDT - WWDT interrupt wake-up 6278 * 0b0..Disabled 6279 * 0b1..Enabled 6280 */ 6281 #define SYSCON_STARTERP1_WWDT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP1_WWDT_SHIFT)) & SYSCON_STARTERP1_WWDT_MASK) 6282 #define SYSCON_STARTERP1_BOD_MASK (0x2000U) 6283 #define SYSCON_STARTERP1_BOD_SHIFT (13U) 6284 /*! BOD - BOD interrupt wake-up 6285 * 0b0..Disabled 6286 * 0b1..Enabled 6287 */ 6288 #define SYSCON_STARTERP1_BOD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP1_BOD_SHIFT)) & SYSCON_STARTERP1_BOD_MASK) 6289 #define SYSCON_STARTERP1_WKT_MASK (0x8000U) 6290 #define SYSCON_STARTERP1_WKT_SHIFT (15U) 6291 /*! WKT - Self-wake-up timer interrupt wake-up 6292 * 0b0..Disabled 6293 * 0b1..Enabled 6294 */ 6295 #define SYSCON_STARTERP1_WKT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERP1_WKT_SHIFT)) & SYSCON_STARTERP1_WKT_MASK) 6296 /*! @} */ 6297 6298 /*! @name PDSLEEPCFG - Deep-sleep configuration register */ 6299 /*! @{ */ 6300 #define SYSCON_PDSLEEPCFG_BOD_PD_MASK (0x8U) 6301 #define SYSCON_PDSLEEPCFG_BOD_PD_SHIFT (3U) 6302 /*! BOD_PD - BOD power-down control for Deep-sleep and Power-down mode 6303 * 0b0..powered 6304 * 0b1..powered down 6305 */ 6306 #define SYSCON_PDSLEEPCFG_BOD_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_BOD_PD_SHIFT)) & SYSCON_PDSLEEPCFG_BOD_PD_MASK) 6307 #define SYSCON_PDSLEEPCFG_LPOSC_PD_MASK (0x40U) 6308 #define SYSCON_PDSLEEPCFG_LPOSC_PD_SHIFT (6U) 6309 /*! LPOSC_PD - Low power oscillator power-down control for deep-sleep and power-down mode. Changing 6310 * this bit to powered-down has no effect when the LOCK bit in the WWDT MOD register is set. In 6311 * this case, the low power oscillator is always running. 6312 * 0b0..Disabled 6313 * 0b1..Enabled 6314 */ 6315 #define SYSCON_PDSLEEPCFG_LPOSC_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_LPOSC_PD_SHIFT)) & SYSCON_PDSLEEPCFG_LPOSC_PD_MASK) 6316 /*! @} */ 6317 6318 /*! @name PDAWAKECFG - Wake-up configuration register */ 6319 /*! @{ */ 6320 #define SYSCON_PDAWAKECFG_FROOUT_PD_MASK (0x1U) 6321 #define SYSCON_PDAWAKECFG_FROOUT_PD_SHIFT (0U) 6322 /*! FROOUT_PD - FRO oscillator output wake-up configuration 6323 * 0b0..powered 6324 * 0b1..powered down 6325 */ 6326 #define SYSCON_PDAWAKECFG_FROOUT_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDAWAKECFG_FROOUT_PD_SHIFT)) & SYSCON_PDAWAKECFG_FROOUT_PD_MASK) 6327 #define SYSCON_PDAWAKECFG_FRO_PD_MASK (0x2U) 6328 #define SYSCON_PDAWAKECFG_FRO_PD_SHIFT (1U) 6329 /*! FRO_PD - FRO oscillator power-down wake-up configuration 6330 * 0b0..powered 6331 * 0b1..powered down 6332 */ 6333 #define SYSCON_PDAWAKECFG_FRO_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDAWAKECFG_FRO_PD_SHIFT)) & SYSCON_PDAWAKECFG_FRO_PD_MASK) 6334 #define SYSCON_PDAWAKECFG_FLASH_PD_MASK (0x4U) 6335 #define SYSCON_PDAWAKECFG_FLASH_PD_SHIFT (2U) 6336 /*! FLASH_PD - Flash wake-up configuration 6337 * 0b0..powered 6338 * 0b1..powered down 6339 */ 6340 #define SYSCON_PDAWAKECFG_FLASH_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDAWAKECFG_FLASH_PD_SHIFT)) & SYSCON_PDAWAKECFG_FLASH_PD_MASK) 6341 #define SYSCON_PDAWAKECFG_BOD_PD_MASK (0x8U) 6342 #define SYSCON_PDAWAKECFG_BOD_PD_SHIFT (3U) 6343 /*! BOD_PD - BOD wake-up configuration 6344 * 0b0..powered 6345 * 0b1..powered down 6346 */ 6347 #define SYSCON_PDAWAKECFG_BOD_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDAWAKECFG_BOD_PD_SHIFT)) & SYSCON_PDAWAKECFG_BOD_PD_MASK) 6348 #define SYSCON_PDAWAKECFG_ADC_PD_MASK (0x10U) 6349 #define SYSCON_PDAWAKECFG_ADC_PD_SHIFT (4U) 6350 /*! ADC_PD - ADC wake-up configuration 6351 * 0b0..powered 6352 * 0b1..powered down 6353 */ 6354 #define SYSCON_PDAWAKECFG_ADC_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDAWAKECFG_ADC_PD_SHIFT)) & SYSCON_PDAWAKECFG_ADC_PD_MASK) 6355 #define SYSCON_PDAWAKECFG_LPOSC_PD_MASK (0x40U) 6356 #define SYSCON_PDAWAKECFG_LPOSC_PD_SHIFT (6U) 6357 /*! LPOSC_PD - Low power oscillator wake-up configuration. Changing this bit to powered-down has no 6358 * effect when the LOCK bit in the WWDT MOD register is set. In this case, the low power 6359 * oscillator is always running. 6360 * 0b0..Disabled 6361 * 0b1..Enabled 6362 */ 6363 #define SYSCON_PDAWAKECFG_LPOSC_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDAWAKECFG_LPOSC_PD_SHIFT)) & SYSCON_PDAWAKECFG_LPOSC_PD_MASK) 6364 #define SYSCON_PDAWAKECFG_DAC_MASK (0x2000U) 6365 #define SYSCON_PDAWAKECFG_DAC_SHIFT (13U) 6366 /*! DAC - DAC0 wake-up configuration. 6367 * 0b0..Disabled 6368 * 0b1..Enabled 6369 */ 6370 #define SYSCON_PDAWAKECFG_DAC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDAWAKECFG_DAC_SHIFT)) & SYSCON_PDAWAKECFG_DAC_MASK) 6371 #define SYSCON_PDAWAKECFG_ACMP_MASK (0x8000U) 6372 #define SYSCON_PDAWAKECFG_ACMP_SHIFT (15U) 6373 /*! ACMP - Analog comparator wake-up configuration 6374 * 0b0..Disabled 6375 * 0b1..Enabled 6376 */ 6377 #define SYSCON_PDAWAKECFG_ACMP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDAWAKECFG_ACMP_SHIFT)) & SYSCON_PDAWAKECFG_ACMP_MASK) 6378 /*! @} */ 6379 6380 /*! @name PDRUNCFG - Power configuration register */ 6381 /*! @{ */ 6382 #define SYSCON_PDRUNCFG_FROOUT_PD_MASK (0x1U) 6383 #define SYSCON_PDRUNCFG_FROOUT_PD_SHIFT (0U) 6384 /*! FROOUT_PD - FRO oscillator output wake-up configuration 6385 * 0b0..powered 6386 * 0b1..powered down 6387 */ 6388 #define SYSCON_PDRUNCFG_FROOUT_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_FROOUT_PD_SHIFT)) & SYSCON_PDRUNCFG_FROOUT_PD_MASK) 6389 #define SYSCON_PDRUNCFG_FRO_PD_MASK (0x2U) 6390 #define SYSCON_PDRUNCFG_FRO_PD_SHIFT (1U) 6391 /*! FRO_PD - FRO oscillator power-down wake-up configuration 6392 * 0b0..powered 6393 * 0b1..powered down 6394 */ 6395 #define SYSCON_PDRUNCFG_FRO_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_FRO_PD_SHIFT)) & SYSCON_PDRUNCFG_FRO_PD_MASK) 6396 #define SYSCON_PDRUNCFG_FLASH_PD_MASK (0x4U) 6397 #define SYSCON_PDRUNCFG_FLASH_PD_SHIFT (2U) 6398 /*! FLASH_PD - Flash wake-up configuration 6399 * 0b0..powered 6400 * 0b1..powered down 6401 */ 6402 #define SYSCON_PDRUNCFG_FLASH_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_FLASH_PD_SHIFT)) & SYSCON_PDRUNCFG_FLASH_PD_MASK) 6403 #define SYSCON_PDRUNCFG_BOD_PD_MASK (0x8U) 6404 #define SYSCON_PDRUNCFG_BOD_PD_SHIFT (3U) 6405 /*! BOD_PD - BOD wake-up configuration 6406 * 0b0..powered 6407 * 0b1..powered down 6408 */ 6409 #define SYSCON_PDRUNCFG_BOD_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_BOD_PD_SHIFT)) & SYSCON_PDRUNCFG_BOD_PD_MASK) 6410 #define SYSCON_PDRUNCFG_ADC_PD_MASK (0x10U) 6411 #define SYSCON_PDRUNCFG_ADC_PD_SHIFT (4U) 6412 /*! ADC_PD - ADC wake-up configuration 6413 * 0b0..powered 6414 * 0b1..powered down 6415 */ 6416 #define SYSCON_PDRUNCFG_ADC_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_ADC_PD_SHIFT)) & SYSCON_PDRUNCFG_ADC_PD_MASK) 6417 #define SYSCON_PDRUNCFG_LPOSC_PD_MASK (0x40U) 6418 #define SYSCON_PDRUNCFG_LPOSC_PD_SHIFT (6U) 6419 /*! LPOSC_PD - Low power oscillator power down. Changing this bit to powered-down has no effect when 6420 * the LOCK bit in the WWDT MOD register is set. In this case, the low power oscillator is 6421 * always running. 6422 * 0b0..Disabled 6423 * 0b1..Enabled 6424 */ 6425 #define SYSCON_PDRUNCFG_LPOSC_PD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_LPOSC_PD_SHIFT)) & SYSCON_PDRUNCFG_LPOSC_PD_MASK) 6426 #define SYSCON_PDRUNCFG_DAC0_MASK (0x2000U) 6427 #define SYSCON_PDRUNCFG_DAC0_SHIFT (13U) 6428 /*! DAC0 - DAC0 wake-up configuration. 6429 * 0b0..Disabled 6430 * 0b1..Enabled 6431 */ 6432 #define SYSCON_PDRUNCFG_DAC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_DAC0_SHIFT)) & SYSCON_PDRUNCFG_DAC0_MASK) 6433 #define SYSCON_PDRUNCFG_ACMP_MASK (0x8000U) 6434 #define SYSCON_PDRUNCFG_ACMP_SHIFT (15U) 6435 /*! ACMP - Analog comparator wake-up configuration 6436 * 0b0..Disabled 6437 * 0b1..Enabled 6438 */ 6439 #define SYSCON_PDRUNCFG_ACMP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_ACMP_SHIFT)) & SYSCON_PDRUNCFG_ACMP_MASK) 6440 /*! @} */ 6441 6442 /*! @name DEVICE_ID - Device ID register */ 6443 /*! @{ */ 6444 #define SYSCON_DEVICE_ID_DEVICEID_MASK (0xFFFFFFFFU) 6445 #define SYSCON_DEVICE_ID_DEVICEID_SHIFT (0U) 6446 /*! DEVICEID - Used to read the part identification number. 6447 */ 6448 #define SYSCON_DEVICE_ID_DEVICEID(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEVICE_ID_DEVICEID_SHIFT)) & SYSCON_DEVICE_ID_DEVICEID_MASK) 6449 /*! @} */ 6450 6451 6452 /*! 6453 * @} 6454 */ /* end of group SYSCON_Register_Masks */ 6455 6456 6457 /* SYSCON - Peripheral instance base addresses */ 6458 /** Peripheral SYSCON base address */ 6459 #define SYSCON_BASE (0x40048000u) 6460 /** Peripheral SYSCON base pointer */ 6461 #define SYSCON ((SYSCON_Type *)SYSCON_BASE) 6462 /** Array initializer of SYSCON peripheral base addresses */ 6463 #define SYSCON_BASE_ADDRS { SYSCON_BASE } 6464 /** Array initializer of SYSCON peripheral base pointers */ 6465 #define SYSCON_BASE_PTRS { SYSCON } 6466 6467 /*! 6468 * @} 6469 */ /* end of group SYSCON_Peripheral_Access_Layer */ 6470 6471 6472 /* ---------------------------------------------------------------------------- 6473 -- USART Peripheral Access Layer 6474 ---------------------------------------------------------------------------- */ 6475 6476 /*! 6477 * @addtogroup USART_Peripheral_Access_Layer USART Peripheral Access Layer 6478 * @{ 6479 */ 6480 6481 /** USART - Register Layout Typedef */ 6482 typedef struct { 6483 __IO uint32_t CFG; /**< USART Configuration register. Basic USART configuration settings that typically are not changed during operation., offset: 0x0 */ 6484 __IO uint32_t CTL; /**< USART Control register. USART control settings that are more likely to change during operation., offset: 0x4 */ 6485 __IO uint32_t STAT; /**< USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them., offset: 0x8 */ 6486 __IO uint32_t INTENSET; /**< Interrupt Enable read and Set register. Contains an individual interrupt enable bit for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set., offset: 0xC */ 6487 __O uint32_t INTENCLR; /**< Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared., offset: 0x10 */ 6488 __I uint32_t RXDAT; /**< Receiver Data register. Contains the last character received., offset: 0x14 */ 6489 __I uint32_t RXDATSTAT; /**< Receiver Data with Status register. Combines the last character received with the current USART receive status. Allows DMA or software to recover incoming data and status together., offset: 0x18 */ 6490 __IO uint32_t TXDAT; /**< Transmit Data register. Data to be transmitted is written here., offset: 0x1C */ 6491 __IO uint32_t BRG; /**< Baud Rate Generator register. 16-bit integer baud rate divisor value., offset: 0x20 */ 6492 __I uint32_t INTSTAT; /**< Interrupt status register. Reflects interrupts that are currently enabled., offset: 0x24 */ 6493 __IO uint32_t OSR; /**< Oversample selection register for asynchronous communication., offset: 0x28 */ 6494 __IO uint32_t ADDR; /**< Address register for automatic address matching., offset: 0x2C */ 6495 } USART_Type; 6496 6497 /* ---------------------------------------------------------------------------- 6498 -- USART Register Masks 6499 ---------------------------------------------------------------------------- */ 6500 6501 /*! 6502 * @addtogroup USART_Register_Masks USART Register Masks 6503 * @{ 6504 */ 6505 6506 /*! @name CFG - USART Configuration register. Basic USART configuration settings that typically are not changed during operation. */ 6507 /*! @{ */ 6508 #define USART_CFG_ENABLE_MASK (0x1U) 6509 #define USART_CFG_ENABLE_SHIFT (0U) 6510 /*! ENABLE - USART Enable. 6511 * 0b0..Disabled. The USART is disabled and the internal state machine and counters are reset. While Enable = 0, 6512 * all USART interrupts and DMA transfers are disabled. When Enable is set again, CFG and most other control 6513 * bits remain unchanged. When re-enabled, the USART will immediately be ready to transmit because the 6514 * transmitter has been reset and is therefore available. 6515 * 0b1..Enabled. The USART is enabled for operation. 6516 */ 6517 #define USART_CFG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_ENABLE_SHIFT)) & USART_CFG_ENABLE_MASK) 6518 #define USART_CFG_DATALEN_MASK (0xCU) 6519 #define USART_CFG_DATALEN_SHIFT (2U) 6520 /*! DATALEN - Selects the data size for the USART. 6521 * 0b00..7 bit Data length. 6522 * 0b01..8 bit Data length. 6523 * 0b10..9 bit data length. The 9th bit is commonly used for addressing in multidrop mode. See the ADDRDET bit in the CTL register. 6524 * 0b11..Reserved. 6525 */ 6526 #define USART_CFG_DATALEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_DATALEN_SHIFT)) & USART_CFG_DATALEN_MASK) 6527 #define USART_CFG_PARITYSEL_MASK (0x30U) 6528 #define USART_CFG_PARITYSEL_SHIFT (4U) 6529 /*! PARITYSEL - Selects what type of parity is used by the USART. 6530 * 0b00..No parity. 6531 * 0b01..Reserved. 6532 * 0b10..Even parity. Adds a bit to each character such that the number of 1s in a transmitted character is even, 6533 * and the number of 1s in a received character is expected to be even. 6534 * 0b11..Odd parity. Adds a bit to each character such that the number of 1s in a transmitted character is odd, 6535 * and the number of 1s in a received character is expected to be odd. 6536 */ 6537 #define USART_CFG_PARITYSEL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_PARITYSEL_SHIFT)) & USART_CFG_PARITYSEL_MASK) 6538 #define USART_CFG_STOPLEN_MASK (0x40U) 6539 #define USART_CFG_STOPLEN_SHIFT (6U) 6540 /*! STOPLEN - Number of stop bits appended to transmitted data. Only a single stop bit is required for received data. 6541 * 0b0..1 stop bit. 6542 * 0b1..2 stop bits. This setting should only be used for asynchronous communication. 6543 */ 6544 #define USART_CFG_STOPLEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_STOPLEN_SHIFT)) & USART_CFG_STOPLEN_MASK) 6545 #define USART_CFG_CTSEN_MASK (0x200U) 6546 #define USART_CFG_CTSEN_SHIFT (9U) 6547 /*! CTSEN - CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input 6548 * pin, or from the USART's own RTS if loopback mode is enabled. 6549 * 0b0..No flow control. The transmitter does not receive any automatic flow control signal. 6550 * 0b1..Flow control enabled. The transmitter uses the CTS input (or RTS output in loopback mode) for flow control purposes. 6551 */ 6552 #define USART_CFG_CTSEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_CTSEN_SHIFT)) & USART_CFG_CTSEN_MASK) 6553 #define USART_CFG_SYNCEN_MASK (0x800U) 6554 #define USART_CFG_SYNCEN_SHIFT (11U) 6555 /*! SYNCEN - Selects synchronous or asynchronous operation. 6556 * 0b0..Asynchronous mode. 6557 * 0b1..Synchronous mode. 6558 */ 6559 #define USART_CFG_SYNCEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_SYNCEN_SHIFT)) & USART_CFG_SYNCEN_MASK) 6560 #define USART_CFG_CLKPOL_MASK (0x1000U) 6561 #define USART_CFG_CLKPOL_SHIFT (12U) 6562 /*! CLKPOL - Selects the clock polarity and sampling edge of received data in synchronous mode. 6563 * 0b0..Falling edge. Un_RXD is sampled on the falling edge of SCLK. 6564 * 0b1..Rising edge. Un_RXD is sampled on the rising edge of SCLK. 6565 */ 6566 #define USART_CFG_CLKPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_CLKPOL_SHIFT)) & USART_CFG_CLKPOL_MASK) 6567 #define USART_CFG_SYNCMST_MASK (0x4000U) 6568 #define USART_CFG_SYNCMST_SHIFT (14U) 6569 /*! SYNCMST - Synchronous mode Master select. 6570 * 0b0..Slave. When synchronous mode is enabled, the USART is a slave. 6571 * 0b1..Master. When synchronous mode is enabled, the USART is a master. 6572 */ 6573 #define USART_CFG_SYNCMST(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_SYNCMST_SHIFT)) & USART_CFG_SYNCMST_MASK) 6574 #define USART_CFG_LOOP_MASK (0x8000U) 6575 #define USART_CFG_LOOP_SHIFT (15U) 6576 /*! LOOP - Selects data loopback mode. 6577 * 0b0..Normal operation. 6578 * 0b1..Loopback mode. This provides a mechanism to perform diagnostic loopback testing for USART data. Serial 6579 * data from the transmitter (Un_TXD) is connected internally to serial input of the receive (Un_RXD). Un_TXD 6580 * and Un_RTS activity will also appear on external pins if these functions are configured to appear on device 6581 * pins. The receiver RTS signal is also looped back to CTS and performs flow control if enabled by CTSEN. 6582 */ 6583 #define USART_CFG_LOOP(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_LOOP_SHIFT)) & USART_CFG_LOOP_MASK) 6584 #define USART_CFG_OETA_MASK (0x40000U) 6585 #define USART_CFG_OETA_SHIFT (18U) 6586 /*! OETA - Output Enable Turnaround time enable for RS-485 operation. 6587 * 0b0..Disabled. If selected by OESEL, the Output Enable signal deasserted at the end of the last stop bit of a transmission. 6588 * 0b1..Enabled. If selected by OESEL, the Output Enable signal remains asserted for one character time after the 6589 * end of the last stop bit of a transmission. OE will also remain asserted if another transmit begins 6590 * before it is deasserted. 6591 */ 6592 #define USART_CFG_OETA(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_OETA_SHIFT)) & USART_CFG_OETA_MASK) 6593 #define USART_CFG_AUTOADDR_MASK (0x80000U) 6594 #define USART_CFG_AUTOADDR_SHIFT (19U) 6595 /*! AUTOADDR - Automatic Address matching enable. 6596 * 0b0..Disabled. When addressing is enabled by ADDRDET, address matching is done by software. This provides the 6597 * possibility of versatile addressing (e.g. respond to more than one address). 6598 * 0b1..Enabled. When addressing is enabled by ADDRDET, address matching is done by hardware, using the value in 6599 * the ADDR register as the address to match. 6600 */ 6601 #define USART_CFG_AUTOADDR(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_AUTOADDR_SHIFT)) & USART_CFG_AUTOADDR_MASK) 6602 #define USART_CFG_OESEL_MASK (0x100000U) 6603 #define USART_CFG_OESEL_SHIFT (20U) 6604 /*! OESEL - Output Enable Select. 6605 * 0b0..Standard. The RTS signal is used as the standard flow control function. 6606 * 0b1..RS-485. The RTS signal configured to provide an output enable signal to control an RS-485 transceiver. 6607 */ 6608 #define USART_CFG_OESEL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_OESEL_SHIFT)) & USART_CFG_OESEL_MASK) 6609 #define USART_CFG_OEPOL_MASK (0x200000U) 6610 #define USART_CFG_OEPOL_SHIFT (21U) 6611 /*! OEPOL - Output Enable Polarity. 6612 * 0b0..Low. If selected by OESEL, the output enable is active low. 6613 * 0b1..High. If selected by OESEL, the output enable is active high. 6614 */ 6615 #define USART_CFG_OEPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_OEPOL_SHIFT)) & USART_CFG_OEPOL_MASK) 6616 #define USART_CFG_RXPOL_MASK (0x400000U) 6617 #define USART_CFG_RXPOL_SHIFT (22U) 6618 /*! RXPOL - Receive data polarity. 6619 * 0b0..Standard. The RX signal is used as it arrives from the pin. This means that the RX rest value is 1, start 6620 * bit is 0, data is not inverted, and the stop bit is 1. 6621 * 0b1..Inverted. The RX signal is inverted before being used by the USART. This means that the RX rest value is 6622 * 0, start bit is 1, data is inverted, and the stop bit is 0. 6623 */ 6624 #define USART_CFG_RXPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_RXPOL_SHIFT)) & USART_CFG_RXPOL_MASK) 6625 #define USART_CFG_TXPOL_MASK (0x800000U) 6626 #define USART_CFG_TXPOL_SHIFT (23U) 6627 /*! TXPOL - Transmit data polarity. 6628 * 0b0..Standard. The TX signal is sent out without change. This means that the TX rest value is 1, start bit is 6629 * 0, data is not inverted, and the stop bit is 1. 6630 * 0b1..Inverted. The TX signal is inverted by the USART before being sent out. This means that the TX rest value 6631 * is 0, start bit is 1, data is inverted, and the stop bit is 0. 6632 */ 6633 #define USART_CFG_TXPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_TXPOL_SHIFT)) & USART_CFG_TXPOL_MASK) 6634 /*! @} */ 6635 6636 /*! @name CTL - USART Control register. USART control settings that are more likely to change during operation. */ 6637 /*! @{ */ 6638 #define USART_CTL_TXBRKEN_MASK (0x2U) 6639 #define USART_CTL_TXBRKEN_SHIFT (1U) 6640 /*! TXBRKEN - Break Enable. 6641 * 0b0..Normal operation. 6642 * 0b1..Continuous break. Continuous break is sent immediately when this bit is set, and remains until this bit 6643 * is cleared. A break may be sent without danger of corrupting any currently transmitting character if the 6644 * transmitter is first disabled (TXDIS in CTL is set) and then waiting for the transmitter to be disabled 6645 * (TXDISINT in STAT = 1) before writing 1 to TXBRKEN. 6646 */ 6647 #define USART_CTL_TXBRKEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_TXBRKEN_SHIFT)) & USART_CTL_TXBRKEN_MASK) 6648 #define USART_CTL_ADDRDET_MASK (0x4U) 6649 #define USART_CTL_ADDRDET_SHIFT (2U) 6650 /*! ADDRDET - Enable address detect mode. 6651 * 0b0..Disabled. The USART presents all incoming data. 6652 * 0b1..Enabled. The USART receiver ignores incoming data that does not have the most significant bit of the data 6653 * (typically the 9th bit) = 1. When the data MSB bit = 1, the receiver treats the incoming data normally, 6654 * generating a received data interrupt. Software can then check the data to see if this is an address that 6655 * should be handled. If it is, the ADDRDET bit is cleared by software and further incoming data is handled 6656 * normally. 6657 */ 6658 #define USART_CTL_ADDRDET(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_ADDRDET_SHIFT)) & USART_CTL_ADDRDET_MASK) 6659 #define USART_CTL_TXDIS_MASK (0x40U) 6660 #define USART_CTL_TXDIS_SHIFT (6U) 6661 /*! TXDIS - Transmit Disable. 6662 * 0b0..Not disabled. USART transmitter is not disabled. 6663 * 0b1..Disabled. USART transmitter is disabled after any character currently being transmitted is complete. This 6664 * feature can be used to facilitate software flow control. 6665 */ 6666 #define USART_CTL_TXDIS(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_TXDIS_SHIFT)) & USART_CTL_TXDIS_MASK) 6667 #define USART_CTL_CC_MASK (0x100U) 6668 #define USART_CTL_CC_SHIFT (8U) 6669 /*! CC - Continuous Clock generation. By default, SCLK is only output while data is being transmitted in synchronous mode. 6670 * 0b0..Clock on character. In synchronous mode, SCLK cycles only when characters are being sent on Un_TXD or to 6671 * complete a character that is being received. 6672 * 0b1..Continuous clock. SCLK runs continuously in synchronous mode, allowing characters to be received on 6673 * Un_RxD independently from transmission on Un_TXD). 6674 */ 6675 #define USART_CTL_CC(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_CC_SHIFT)) & USART_CTL_CC_MASK) 6676 #define USART_CTL_CLRCCONRX_MASK (0x200U) 6677 #define USART_CTL_CLRCCONRX_SHIFT (9U) 6678 /*! CLRCCONRX - Clear Continuous Clock. 6679 * 0b0..No effect. No effect on the CC bit. 6680 * 0b1..Auto-clear. The CC bit is automatically cleared when a complete character has been received. This bit is cleared at the same time. 6681 */ 6682 #define USART_CTL_CLRCCONRX(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_CLRCCONRX_SHIFT)) & USART_CTL_CLRCCONRX_MASK) 6683 #define USART_CTL_AUTOBAUD_MASK (0x10000U) 6684 #define USART_CTL_AUTOBAUD_SHIFT (16U) 6685 /*! AUTOBAUD - Autobaud enable. 6686 * 0b0..Disabled. USART is in normal operating mode. 6687 * 0b1..Enabled. USART is in autobaud mode. This bit should only be set when the USART receiver is idle. The 6688 * first start bit of RX is measured and used the update the BRG register to match the received data rate. 6689 * AUTOBAUD is cleared once this process is complete, or if there is an AERR. 6690 */ 6691 #define USART_CTL_AUTOBAUD(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_AUTOBAUD_SHIFT)) & USART_CTL_AUTOBAUD_MASK) 6692 /*! @} */ 6693 6694 /*! @name STAT - USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them. */ 6695 /*! @{ */ 6696 #define USART_STAT_RXRDY_MASK (0x1U) 6697 #define USART_STAT_RXRDY_SHIFT (0U) 6698 /*! RXRDY - Receiver Ready flag. When 1, indicates that data is available to be read from the 6699 * receiver buffer. Cleared after a read of the RXDAT or RXDATSTAT registers. 6700 */ 6701 #define USART_STAT_RXRDY(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXRDY_SHIFT)) & USART_STAT_RXRDY_MASK) 6702 #define USART_STAT_RXIDLE_MASK (0x2U) 6703 #define USART_STAT_RXIDLE_SHIFT (1U) 6704 /*! RXIDLE - Receiver Idle. When 0, indicates that the receiver is currently in the process of 6705 * receiving data. When 1, indicates that the receiver is not currently in the process of receiving 6706 * data. 6707 */ 6708 #define USART_STAT_RXIDLE(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXIDLE_SHIFT)) & USART_STAT_RXIDLE_MASK) 6709 #define USART_STAT_TXRDY_MASK (0x4U) 6710 #define USART_STAT_TXRDY_SHIFT (2U) 6711 /*! TXRDY - Transmitter Ready flag. When 1, this bit indicates that data may be written to the 6712 * transmit buffer. Previous data may still be in the process of being transmitted. Cleared when data 6713 * is written to TXDAT. Set when the data is moved from the transmit buffer to the transmit shift 6714 * register. 6715 */ 6716 #define USART_STAT_TXRDY(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_TXRDY_SHIFT)) & USART_STAT_TXRDY_MASK) 6717 #define USART_STAT_TXIDLE_MASK (0x8U) 6718 #define USART_STAT_TXIDLE_SHIFT (3U) 6719 /*! TXIDLE - Transmitter Idle. When 0, indicates that the transmitter is currently in the process of 6720 * sending data.When 1, indicate that the transmitter is not currently in the process of sending 6721 * data. 6722 */ 6723 #define USART_STAT_TXIDLE(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_TXIDLE_SHIFT)) & USART_STAT_TXIDLE_MASK) 6724 #define USART_STAT_CTS_MASK (0x10U) 6725 #define USART_STAT_CTS_SHIFT (4U) 6726 /*! CTS - This bit reflects the current state of the CTS signal, regardless of the setting of the 6727 * CTSEN bit in the CFG register. This will be the value of the CTS input pin unless loopback mode 6728 * is enabled. 6729 */ 6730 #define USART_STAT_CTS(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_CTS_SHIFT)) & USART_STAT_CTS_MASK) 6731 #define USART_STAT_DELTACTS_MASK (0x20U) 6732 #define USART_STAT_DELTACTS_SHIFT (5U) 6733 /*! DELTACTS - This bit is set when a change in the state is detected for the CTS flag above. This bit is cleared by software. 6734 */ 6735 #define USART_STAT_DELTACTS(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_DELTACTS_SHIFT)) & USART_STAT_DELTACTS_MASK) 6736 #define USART_STAT_TXDISSTAT_MASK (0x40U) 6737 #define USART_STAT_TXDISSTAT_SHIFT (6U) 6738 /*! TXDISSTAT - Transmitter Disabled Interrupt flag. When 1, this bit indicates that the USART 6739 * transmitter is fully idle after being disabled via the TXDIS in the CTL register (TXDIS = 1). 6740 */ 6741 #define USART_STAT_TXDISSTAT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_TXDISSTAT_SHIFT)) & USART_STAT_TXDISSTAT_MASK) 6742 #define USART_STAT_OVERRUNINT_MASK (0x100U) 6743 #define USART_STAT_OVERRUNINT_SHIFT (8U) 6744 /*! OVERRUNINT - Overrun Error interrupt flag. This flag is set when a new character is received 6745 * while the receiver buffer is still in use. If this occurs, the newly received character in the 6746 * shift register is lost. 6747 */ 6748 #define USART_STAT_OVERRUNINT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_OVERRUNINT_SHIFT)) & USART_STAT_OVERRUNINT_MASK) 6749 #define USART_STAT_RXBRK_MASK (0x400U) 6750 #define USART_STAT_RXBRK_SHIFT (10U) 6751 /*! RXBRK - Received Break. This bit reflects the current state of the receiver break detection 6752 * logic. It is set when the Un_RXD pin remains low for 16 bit times. Note that FRAMERRINT will also 6753 * be set when this condition occurs because the stop bit(s) for the character would be missing. 6754 * RXBRK is cleared when the Un_RXD pin goes high. 6755 */ 6756 #define USART_STAT_RXBRK(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXBRK_SHIFT)) & USART_STAT_RXBRK_MASK) 6757 #define USART_STAT_DELTARXBRK_MASK (0x800U) 6758 #define USART_STAT_DELTARXBRK_SHIFT (11U) 6759 /*! DELTARXBRK - This bit is set when a change in the state of receiver break detection occurs.Cleared by software. 6760 */ 6761 #define USART_STAT_DELTARXBRK(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_DELTARXBRK_SHIFT)) & USART_STAT_DELTARXBRK_MASK) 6762 #define USART_STAT_START_MASK (0x1000U) 6763 #define USART_STAT_START_SHIFT (12U) 6764 /*! START - This bit is set when a start is detected on the receiver input. Its purpose is primarily 6765 * to allow wake-up from Deep-sleep or Power-down mode immediately when a start is detected. 6766 * Cleared by software. 6767 */ 6768 #define USART_STAT_START(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_START_SHIFT)) & USART_STAT_START_MASK) 6769 #define USART_STAT_FRAMERRINT_MASK (0x2000U) 6770 #define USART_STAT_FRAMERRINT_SHIFT (13U) 6771 /*! FRAMERRINT - Framing Error interrupt flag. This flag is set when a character is received with a 6772 * missing stop bit at the expected location. This could be an indication of a baud rate or 6773 * configuration mismatch with the transmitting source. 6774 */ 6775 #define USART_STAT_FRAMERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_FRAMERRINT_SHIFT)) & USART_STAT_FRAMERRINT_MASK) 6776 #define USART_STAT_PARITYERRINT_MASK (0x4000U) 6777 #define USART_STAT_PARITYERRINT_SHIFT (14U) 6778 /*! PARITYERRINT - Parity Error interrupt flag. This flag is set when a parity error is detected in a received character. 6779 */ 6780 #define USART_STAT_PARITYERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_PARITYERRINT_SHIFT)) & USART_STAT_PARITYERRINT_MASK) 6781 #define USART_STAT_RXNOISEINT_MASK (0x8000U) 6782 #define USART_STAT_RXNOISEINT_SHIFT (15U) 6783 /*! RXNOISEINT - Received Noise interrupt flag. Three samples of received data are taken in order to 6784 * determine the value of each received data bit, except in synchronous mode. This acts as a 6785 * noise filter if one sample disagrees. This flag is set when a received data bit contains one 6786 * disagreeing sample. This could indicate line noise, a baud rate or character format mismatch, or 6787 * loss of synchronization during data reception. 6788 */ 6789 #define USART_STAT_RXNOISEINT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXNOISEINT_SHIFT)) & USART_STAT_RXNOISEINT_MASK) 6790 #define USART_STAT_ABERR_MASK (0x10000U) 6791 #define USART_STAT_ABERR_SHIFT (16U) 6792 /*! ABERR - Autobaud Error. An autobaud error can occur if the BRG counts to its limit before the 6793 * end of the start bit that is being measured, essentially an autobaud time-out. 6794 */ 6795 #define USART_STAT_ABERR(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_ABERR_SHIFT)) & USART_STAT_ABERR_MASK) 6796 /*! @} */ 6797 6798 /*! @name INTENSET - Interrupt Enable read and Set register. Contains an individual interrupt enable bit for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set. */ 6799 /*! @{ */ 6800 #define USART_INTENSET_RXRDYEN_MASK (0x1U) 6801 #define USART_INTENSET_RXRDYEN_SHIFT (0U) 6802 /*! RXRDYEN - When 1, enables an interrupt when there is a received character available to be read from the RXDAT register. 6803 */ 6804 #define USART_INTENSET_RXRDYEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_RXRDYEN_SHIFT)) & USART_INTENSET_RXRDYEN_MASK) 6805 #define USART_INTENSET_TXRDYEN_MASK (0x4U) 6806 #define USART_INTENSET_TXRDYEN_SHIFT (2U) 6807 /*! TXRDYEN - When 1, enables an interrupt when the TXDAT register is available to take another character to transmit. 6808 */ 6809 #define USART_INTENSET_TXRDYEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_TXRDYEN_SHIFT)) & USART_INTENSET_TXRDYEN_MASK) 6810 #define USART_INTENSET_TXIDLEEN_MASK (0x8U) 6811 #define USART_INTENSET_TXIDLEEN_SHIFT (3U) 6812 /*! TXIDLEEN - When 1, enables an interrupt when the transmitter becomes idle (TXIDLE = 1). 6813 */ 6814 #define USART_INTENSET_TXIDLEEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_TXIDLEEN_SHIFT)) & USART_INTENSET_TXIDLEEN_MASK) 6815 #define USART_INTENSET_DELTACTSEN_MASK (0x20U) 6816 #define USART_INTENSET_DELTACTSEN_SHIFT (5U) 6817 /*! DELTACTSEN - When 1, enables an interrupt when there is a change in the state of the CTS input. 6818 */ 6819 #define USART_INTENSET_DELTACTSEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_DELTACTSEN_SHIFT)) & USART_INTENSET_DELTACTSEN_MASK) 6820 #define USART_INTENSET_TXDISEN_MASK (0x40U) 6821 #define USART_INTENSET_TXDISEN_SHIFT (6U) 6822 /*! TXDISEN - When 1, enables an interrupt when the transmitter is fully disabled as indicated by 6823 * the TXDISINT flag in STAT. See description of the TXDISINT bit for details. 6824 */ 6825 #define USART_INTENSET_TXDISEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_TXDISEN_SHIFT)) & USART_INTENSET_TXDISEN_MASK) 6826 #define USART_INTENSET_OVERRUNEN_MASK (0x100U) 6827 #define USART_INTENSET_OVERRUNEN_SHIFT (8U) 6828 /*! OVERRUNEN - When 1, enables an interrupt when an overrun error occurred. 6829 */ 6830 #define USART_INTENSET_OVERRUNEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_OVERRUNEN_SHIFT)) & USART_INTENSET_OVERRUNEN_MASK) 6831 #define USART_INTENSET_DELTARXBRKEN_MASK (0x800U) 6832 #define USART_INTENSET_DELTARXBRKEN_SHIFT (11U) 6833 /*! DELTARXBRKEN - When 1, enables an interrupt when a change of state has occurred in the detection 6834 * of a received break condition (break condition asserted or deasserted). 6835 */ 6836 #define USART_INTENSET_DELTARXBRKEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_DELTARXBRKEN_SHIFT)) & USART_INTENSET_DELTARXBRKEN_MASK) 6837 #define USART_INTENSET_STARTEN_MASK (0x1000U) 6838 #define USART_INTENSET_STARTEN_SHIFT (12U) 6839 /*! STARTEN - When 1, enables an interrupt when a received start bit has been detected. 6840 */ 6841 #define USART_INTENSET_STARTEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_STARTEN_SHIFT)) & USART_INTENSET_STARTEN_MASK) 6842 #define USART_INTENSET_FRAMERREN_MASK (0x2000U) 6843 #define USART_INTENSET_FRAMERREN_SHIFT (13U) 6844 /*! FRAMERREN - When 1, enables an interrupt when a framing error has been detected. 6845 */ 6846 #define USART_INTENSET_FRAMERREN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_FRAMERREN_SHIFT)) & USART_INTENSET_FRAMERREN_MASK) 6847 #define USART_INTENSET_PARITYERREN_MASK (0x4000U) 6848 #define USART_INTENSET_PARITYERREN_SHIFT (14U) 6849 /*! PARITYERREN - When 1, enables an interrupt when a parity error has been detected. 6850 */ 6851 #define USART_INTENSET_PARITYERREN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_PARITYERREN_SHIFT)) & USART_INTENSET_PARITYERREN_MASK) 6852 #define USART_INTENSET_RXNOISEEN_MASK (0x8000U) 6853 #define USART_INTENSET_RXNOISEEN_SHIFT (15U) 6854 /*! RXNOISEEN - When 1, enables an interrupt when noise is detected. 6855 */ 6856 #define USART_INTENSET_RXNOISEEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_RXNOISEEN_SHIFT)) & USART_INTENSET_RXNOISEEN_MASK) 6857 #define USART_INTENSET_ABERREN_MASK (0x10000U) 6858 #define USART_INTENSET_ABERREN_SHIFT (16U) 6859 /*! ABERREN - When 1, enables an interrupt when an autobaud error occurs. 6860 */ 6861 #define USART_INTENSET_ABERREN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_ABERREN_SHIFT)) & USART_INTENSET_ABERREN_MASK) 6862 /*! @} */ 6863 6864 /*! @name INTENCLR - Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared. */ 6865 /*! @{ */ 6866 #define USART_INTENCLR_RXRDYCLR_MASK (0x1U) 6867 #define USART_INTENCLR_RXRDYCLR_SHIFT (0U) 6868 /*! RXRDYCLR - Writing 1 clears the corresponding bit in the INTENSET register. 6869 */ 6870 #define USART_INTENCLR_RXRDYCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_RXRDYCLR_SHIFT)) & USART_INTENCLR_RXRDYCLR_MASK) 6871 #define USART_INTENCLR_TXRDYCLR_MASK (0x4U) 6872 #define USART_INTENCLR_TXRDYCLR_SHIFT (2U) 6873 /*! TXRDYCLR - Writing 1 clears the corresponding bit in the INTENSET register. 6874 */ 6875 #define USART_INTENCLR_TXRDYCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_TXRDYCLR_SHIFT)) & USART_INTENCLR_TXRDYCLR_MASK) 6876 #define USART_INTENCLR_TXIDLECLR_MASK (0x8U) 6877 #define USART_INTENCLR_TXIDLECLR_SHIFT (3U) 6878 /*! TXIDLECLR - Writing 1 clears the corresponding bit in the INTENSET register. 6879 */ 6880 #define USART_INTENCLR_TXIDLECLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_TXIDLECLR_SHIFT)) & USART_INTENCLR_TXIDLECLR_MASK) 6881 #define USART_INTENCLR_DELTACTSCLR_MASK (0x20U) 6882 #define USART_INTENCLR_DELTACTSCLR_SHIFT (5U) 6883 /*! DELTACTSCLR - Writing 1 clears the corresponding bit in the INTENSET register. 6884 */ 6885 #define USART_INTENCLR_DELTACTSCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_DELTACTSCLR_SHIFT)) & USART_INTENCLR_DELTACTSCLR_MASK) 6886 #define USART_INTENCLR_TXDISINTCLR_MASK (0x40U) 6887 #define USART_INTENCLR_TXDISINTCLR_SHIFT (6U) 6888 /*! TXDISINTCLR - Writing 1 clears the corresponding bit in the INTENSET register. 6889 */ 6890 #define USART_INTENCLR_TXDISINTCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_TXDISINTCLR_SHIFT)) & USART_INTENCLR_TXDISINTCLR_MASK) 6891 #define USART_INTENCLR_OVERRUNCLR_MASK (0x100U) 6892 #define USART_INTENCLR_OVERRUNCLR_SHIFT (8U) 6893 /*! OVERRUNCLR - Writing 1 clears the corresponding bit in the INTENSET register. 6894 */ 6895 #define USART_INTENCLR_OVERRUNCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_OVERRUNCLR_SHIFT)) & USART_INTENCLR_OVERRUNCLR_MASK) 6896 #define USART_INTENCLR_DELTARXBRKCLR_MASK (0x800U) 6897 #define USART_INTENCLR_DELTARXBRKCLR_SHIFT (11U) 6898 /*! DELTARXBRKCLR - Writing 1 clears the corresponding bit in the INTENSET register. 6899 */ 6900 #define USART_INTENCLR_DELTARXBRKCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_DELTARXBRKCLR_SHIFT)) & USART_INTENCLR_DELTARXBRKCLR_MASK) 6901 #define USART_INTENCLR_STARTCLR_MASK (0x1000U) 6902 #define USART_INTENCLR_STARTCLR_SHIFT (12U) 6903 /*! STARTCLR - Writing 1 clears the corresponding bit in the INTENSET register. 6904 */ 6905 #define USART_INTENCLR_STARTCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_STARTCLR_SHIFT)) & USART_INTENCLR_STARTCLR_MASK) 6906 #define USART_INTENCLR_FRAMERRCLR_MASK (0x2000U) 6907 #define USART_INTENCLR_FRAMERRCLR_SHIFT (13U) 6908 /*! FRAMERRCLR - Writing 1 clears the corresponding bit in the INTENSET register. 6909 */ 6910 #define USART_INTENCLR_FRAMERRCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_FRAMERRCLR_SHIFT)) & USART_INTENCLR_FRAMERRCLR_MASK) 6911 #define USART_INTENCLR_PARITYERRCLR_MASK (0x4000U) 6912 #define USART_INTENCLR_PARITYERRCLR_SHIFT (14U) 6913 /*! PARITYERRCLR - Writing 1 clears the corresponding bit in the INTENSET register. 6914 */ 6915 #define USART_INTENCLR_PARITYERRCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_PARITYERRCLR_SHIFT)) & USART_INTENCLR_PARITYERRCLR_MASK) 6916 #define USART_INTENCLR_RXNOISECLR_MASK (0x8000U) 6917 #define USART_INTENCLR_RXNOISECLR_SHIFT (15U) 6918 /*! RXNOISECLR - Writing 1 clears the corresponding bit in the INTENSET register. 6919 */ 6920 #define USART_INTENCLR_RXNOISECLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_RXNOISECLR_SHIFT)) & USART_INTENCLR_RXNOISECLR_MASK) 6921 #define USART_INTENCLR_ABERRCLR_MASK (0x10000U) 6922 #define USART_INTENCLR_ABERRCLR_SHIFT (16U) 6923 /*! ABERRCLR - Writing 1 clears the corresponding bit in the INTENSET register. 6924 */ 6925 #define USART_INTENCLR_ABERRCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_ABERRCLR_SHIFT)) & USART_INTENCLR_ABERRCLR_MASK) 6926 /*! @} */ 6927 6928 /*! @name RXDAT - Receiver Data register. Contains the last character received. */ 6929 /*! @{ */ 6930 #define USART_RXDAT_RXDAT_MASK (0x1FFU) 6931 #define USART_RXDAT_RXDAT_SHIFT (0U) 6932 /*! RXDAT - The USART Receiver Data register contains the next received character. The number of 6933 * bits that are relevant depends on the USART configuration settings. 6934 */ 6935 #define USART_RXDAT_RXDAT(x) (((uint32_t)(((uint32_t)(x)) << USART_RXDAT_RXDAT_SHIFT)) & USART_RXDAT_RXDAT_MASK) 6936 /*! @} */ 6937 6938 /*! @name RXDATSTAT - Receiver Data with Status register. Combines the last character received with the current USART receive status. Allows DMA or software to recover incoming data and status together. */ 6939 /*! @{ */ 6940 #define USART_RXDATSTAT_RXDAT_MASK (0x1FFU) 6941 #define USART_RXDATSTAT_RXDAT_SHIFT (0U) 6942 /*! RXDAT - The USART Receiver Data register contains the next received character. The number of 6943 * bits that are relevant depends on the USART configuration settings. 6944 */ 6945 #define USART_RXDATSTAT_RXDAT(x) (((uint32_t)(((uint32_t)(x)) << USART_RXDATSTAT_RXDAT_SHIFT)) & USART_RXDATSTAT_RXDAT_MASK) 6946 #define USART_RXDATSTAT_FRAMERR_MASK (0x2000U) 6947 #define USART_RXDATSTAT_FRAMERR_SHIFT (13U) 6948 /*! FRAMERR - Framing Error status flag. This bit is valid when there is a character to be read in 6949 * the RXDAT register and reflects the status of that character. This bit will set when the 6950 * character in RXDAT was received with a missing stop bit at the expected location. This could be an 6951 * indication of a baud rate or configuration mismatch with the transmitting source. 6952 */ 6953 #define USART_RXDATSTAT_FRAMERR(x) (((uint32_t)(((uint32_t)(x)) << USART_RXDATSTAT_FRAMERR_SHIFT)) & USART_RXDATSTAT_FRAMERR_MASK) 6954 #define USART_RXDATSTAT_PARITYERR_MASK (0x4000U) 6955 #define USART_RXDATSTAT_PARITYERR_SHIFT (14U) 6956 /*! PARITYERR - Parity Error status flag. This bit is valid when there is a character to be read in 6957 * the RXDAT register and reflects the status of that character. This bit will be set when a 6958 * parity error is detected in a received character. 6959 */ 6960 #define USART_RXDATSTAT_PARITYERR(x) (((uint32_t)(((uint32_t)(x)) << USART_RXDATSTAT_PARITYERR_SHIFT)) & USART_RXDATSTAT_PARITYERR_MASK) 6961 #define USART_RXDATSTAT_RXNOISE_MASK (0x8000U) 6962 #define USART_RXDATSTAT_RXNOISE_SHIFT (15U) 6963 /*! RXNOISE - Received Noise flag. 6964 */ 6965 #define USART_RXDATSTAT_RXNOISE(x) (((uint32_t)(((uint32_t)(x)) << USART_RXDATSTAT_RXNOISE_SHIFT)) & USART_RXDATSTAT_RXNOISE_MASK) 6966 /*! @} */ 6967 6968 /*! @name TXDAT - Transmit Data register. Data to be transmitted is written here. */ 6969 /*! @{ */ 6970 #define USART_TXDAT_TXDAT_MASK (0x1FFU) 6971 #define USART_TXDAT_TXDAT_SHIFT (0U) 6972 /*! TXDAT - Writing to the USART Transmit Data Register causes the data to be transmitted as soon as 6973 * the transmit shift register is available and any conditions for transmitting data are met: 6974 * CTS low (if CTSEN bit = 1), TXDIS bit = 0. 6975 */ 6976 #define USART_TXDAT_TXDAT(x) (((uint32_t)(((uint32_t)(x)) << USART_TXDAT_TXDAT_SHIFT)) & USART_TXDAT_TXDAT_MASK) 6977 /*! @} */ 6978 6979 /*! @name BRG - Baud Rate Generator register. 16-bit integer baud rate divisor value. */ 6980 /*! @{ */ 6981 #define USART_BRG_BRGVAL_MASK (0xFFFFU) 6982 #define USART_BRG_BRGVAL_SHIFT (0U) 6983 /*! BRGVAL - This value is used to divide the USART input clock to determine the baud rate, based on 6984 * the input clock from the FRG. 0 = FCLK is used directly by the USART function. 1 = FCLK is 6985 * divided by 2 before use by the USART function. 2 = FCLK is divided by 3 before use by the USART 6986 * function. 0xFFFF = FCLK is divided by 65,536 before use by the USART function. 6987 */ 6988 #define USART_BRG_BRGVAL(x) (((uint32_t)(((uint32_t)(x)) << USART_BRG_BRGVAL_SHIFT)) & USART_BRG_BRGVAL_MASK) 6989 /*! @} */ 6990 6991 /*! @name INTSTAT - Interrupt status register. Reflects interrupts that are currently enabled. */ 6992 /*! @{ */ 6993 #define USART_INTSTAT_RXRDY_MASK (0x1U) 6994 #define USART_INTSTAT_RXRDY_SHIFT (0U) 6995 /*! RXRDY - Receiver Ready flag. 6996 */ 6997 #define USART_INTSTAT_RXRDY(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_RXRDY_SHIFT)) & USART_INTSTAT_RXRDY_MASK) 6998 #define USART_INTSTAT_TXRDY_MASK (0x4U) 6999 #define USART_INTSTAT_TXRDY_SHIFT (2U) 7000 /*! TXRDY - Transmitter Ready flag. 7001 */ 7002 #define USART_INTSTAT_TXRDY(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_TXRDY_SHIFT)) & USART_INTSTAT_TXRDY_MASK) 7003 #define USART_INTSTAT_TXIDLE_MASK (0x8U) 7004 #define USART_INTSTAT_TXIDLE_SHIFT (3U) 7005 /*! TXIDLE - Transmitter idle status. 7006 */ 7007 #define USART_INTSTAT_TXIDLE(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_TXIDLE_SHIFT)) & USART_INTSTAT_TXIDLE_MASK) 7008 #define USART_INTSTAT_DELTACTS_MASK (0x20U) 7009 #define USART_INTSTAT_DELTACTS_SHIFT (5U) 7010 /*! DELTACTS - This bit is set when a change in the state of the CTS input is detected. 7011 */ 7012 #define USART_INTSTAT_DELTACTS(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_DELTACTS_SHIFT)) & USART_INTSTAT_DELTACTS_MASK) 7013 #define USART_INTSTAT_TXDISINT_MASK (0x40U) 7014 #define USART_INTSTAT_TXDISINT_SHIFT (6U) 7015 /*! TXDISINT - Transmitter Disabled Interrupt flag. 7016 */ 7017 #define USART_INTSTAT_TXDISINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_TXDISINT_SHIFT)) & USART_INTSTAT_TXDISINT_MASK) 7018 #define USART_INTSTAT_OVERRUNINT_MASK (0x100U) 7019 #define USART_INTSTAT_OVERRUNINT_SHIFT (8U) 7020 /*! OVERRUNINT - Overrun Error interrupt flag. 7021 */ 7022 #define USART_INTSTAT_OVERRUNINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_OVERRUNINT_SHIFT)) & USART_INTSTAT_OVERRUNINT_MASK) 7023 #define USART_INTSTAT_DELTARXBRK_MASK (0x800U) 7024 #define USART_INTSTAT_DELTARXBRK_SHIFT (11U) 7025 /*! DELTARXBRK - This bit is set when a change in the state of receiver break detection occurs. 7026 */ 7027 #define USART_INTSTAT_DELTARXBRK(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_DELTARXBRK_SHIFT)) & USART_INTSTAT_DELTARXBRK_MASK) 7028 #define USART_INTSTAT_START_MASK (0x1000U) 7029 #define USART_INTSTAT_START_SHIFT (12U) 7030 /*! START - This bit is set when a start is detected on the receiver input. 7031 */ 7032 #define USART_INTSTAT_START(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_START_SHIFT)) & USART_INTSTAT_START_MASK) 7033 #define USART_INTSTAT_FRAMERRINT_MASK (0x2000U) 7034 #define USART_INTSTAT_FRAMERRINT_SHIFT (13U) 7035 /*! FRAMERRINT - Framing Error interrupt flag. 7036 */ 7037 #define USART_INTSTAT_FRAMERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_FRAMERRINT_SHIFT)) & USART_INTSTAT_FRAMERRINT_MASK) 7038 #define USART_INTSTAT_PARITYERRINT_MASK (0x4000U) 7039 #define USART_INTSTAT_PARITYERRINT_SHIFT (14U) 7040 /*! PARITYERRINT - Parity Error interrupt flag. 7041 */ 7042 #define USART_INTSTAT_PARITYERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_PARITYERRINT_SHIFT)) & USART_INTSTAT_PARITYERRINT_MASK) 7043 #define USART_INTSTAT_RXNOISEINT_MASK (0x8000U) 7044 #define USART_INTSTAT_RXNOISEINT_SHIFT (15U) 7045 /*! RXNOISEINT - Received Noise interrupt flag. 7046 */ 7047 #define USART_INTSTAT_RXNOISEINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_RXNOISEINT_SHIFT)) & USART_INTSTAT_RXNOISEINT_MASK) 7048 #define USART_INTSTAT_ABERR_MASK (0x10000U) 7049 #define USART_INTSTAT_ABERR_SHIFT (16U) 7050 /*! ABERR - Autobaud Error flag. 7051 */ 7052 #define USART_INTSTAT_ABERR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_ABERR_SHIFT)) & USART_INTSTAT_ABERR_MASK) 7053 /*! @} */ 7054 7055 /*! @name OSR - Oversample selection register for asynchronous communication. */ 7056 /*! @{ */ 7057 #define USART_OSR_OSRVAL_MASK (0xFU) 7058 #define USART_OSR_OSRVAL_SHIFT (0U) 7059 /*! OSRVAL - Oversample Selection Value. 0 to 3 = not supported 0x4 = 5 function clocks are used to 7060 * transmit and receive each data bit. 0x5 = 6 function clocks are used to transmit and receive 7061 * each data bit. 0xF= 16 function clocks are used to transmit and receive each data bit. 7062 */ 7063 #define USART_OSR_OSRVAL(x) (((uint32_t)(((uint32_t)(x)) << USART_OSR_OSRVAL_SHIFT)) & USART_OSR_OSRVAL_MASK) 7064 /*! @} */ 7065 7066 /*! @name ADDR - Address register for automatic address matching. */ 7067 /*! @{ */ 7068 #define USART_ADDR_ADDRESS_MASK (0xFFU) 7069 #define USART_ADDR_ADDRESS_SHIFT (0U) 7070 /*! ADDRESS - 8-bit address used with automatic address matching. Used when address detection is 7071 * enabled (ADDRDET in CTL = 1) and automatic address matching is enabled (AUTOADDR in CFG = 1). 7072 */ 7073 #define USART_ADDR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << USART_ADDR_ADDRESS_SHIFT)) & USART_ADDR_ADDRESS_MASK) 7074 /*! @} */ 7075 7076 7077 /*! 7078 * @} 7079 */ /* end of group USART_Register_Masks */ 7080 7081 7082 /* USART - Peripheral instance base addresses */ 7083 /** Peripheral USART0 base address */ 7084 #define USART0_BASE (0x40064000u) 7085 /** Peripheral USART0 base pointer */ 7086 #define USART0 ((USART_Type *)USART0_BASE) 7087 /** Peripheral USART1 base address */ 7088 #define USART1_BASE (0x40068000u) 7089 /** Peripheral USART1 base pointer */ 7090 #define USART1 ((USART_Type *)USART1_BASE) 7091 /** Array initializer of USART peripheral base addresses */ 7092 #define USART_BASE_ADDRS { USART0_BASE, USART1_BASE } 7093 /** Array initializer of USART peripheral base pointers */ 7094 #define USART_BASE_PTRS { USART0, USART1 } 7095 /** Interrupt vectors for the USART peripheral type */ 7096 #define USART_IRQS { USART0_IRQn, USART1_IRQn } 7097 7098 /*! 7099 * @} 7100 */ /* end of group USART_Peripheral_Access_Layer */ 7101 7102 7103 /* ---------------------------------------------------------------------------- 7104 -- WKT Peripheral Access Layer 7105 ---------------------------------------------------------------------------- */ 7106 7107 /*! 7108 * @addtogroup WKT_Peripheral_Access_Layer WKT Peripheral Access Layer 7109 * @{ 7110 */ 7111 7112 /** WKT - Register Layout Typedef */ 7113 typedef struct { 7114 __IO uint32_t CTRL; /**< Self wake-up timer control register., offset: 0x0 */ 7115 uint8_t RESERVED_0[8]; 7116 __IO uint32_t COUNT; /**< Counter register., offset: 0xC */ 7117 } WKT_Type; 7118 7119 /* ---------------------------------------------------------------------------- 7120 -- WKT Register Masks 7121 ---------------------------------------------------------------------------- */ 7122 7123 /*! 7124 * @addtogroup WKT_Register_Masks WKT Register Masks 7125 * @{ 7126 */ 7127 7128 /*! @name CTRL - Self wake-up timer control register. */ 7129 /*! @{ */ 7130 #define WKT_CTRL_CLKSEL_MASK (0x1U) 7131 #define WKT_CTRL_CLKSEL_SHIFT (0U) 7132 /*! CLKSEL - Select the self wake-up timer clock source. Remark: This bit only has an effect if the SEL_EXTCLK bit is not set. 7133 * 0b0..Divided IRC clock. This clock runs at 750 kHz and provides time-out periods of up to approximately 95 7134 * minutes in 1.33 us increments. Remark: This clock is not available in not available in Deep-sleep, 7135 * power-down, deep power-down modes. Do not select this option if the timer is to be used to wake up from one of these 7136 * modes. 7137 * 0b1..This is the (nominally) 10 kHz clock and provides time-out periods of up to approximately 119 hours in 7138 * 100 us increments. The accuracy of this clock is limited to +/- 40 % over temperature and processing. 7139 * Remark: This clock is available in all power modes. Prior to use, the low-power oscillator must be enabled. The 7140 * oscillator must also be set to remain active in Deep power-down if needed. 7141 */ 7142 #define WKT_CTRL_CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << WKT_CTRL_CLKSEL_SHIFT)) & WKT_CTRL_CLKSEL_MASK) 7143 #define WKT_CTRL_ALARMFLAG_MASK (0x2U) 7144 #define WKT_CTRL_ALARMFLAG_SHIFT (1U) 7145 /*! ALARMFLAG - Wake-up or alarm timer flag. 7146 * 0b0..No time-out. The self wake-up timer has not timed out. Writing a 0 to has no effect. 7147 * 0b1..Time-out. The self wake-up timer has timed out. This flag generates an interrupt request which can wake 7148 * up the part from any reduced power mode including Deep power-down if the clock source is the low power 7149 * oscillator. Writing a 1 clears this status bit. 7150 */ 7151 #define WKT_CTRL_ALARMFLAG(x) (((uint32_t)(((uint32_t)(x)) << WKT_CTRL_ALARMFLAG_SHIFT)) & WKT_CTRL_ALARMFLAG_MASK) 7152 #define WKT_CTRL_CLEARCTR_MASK (0x4U) 7153 #define WKT_CTRL_CLEARCTR_SHIFT (2U) 7154 /*! CLEARCTR - Clears the self wake-up timer. 7155 * 0b0..No effect. Reading this bit always returns 0. 7156 * 0b1..Clear the counter. Counting is halted until a new count value is loaded. 7157 */ 7158 #define WKT_CTRL_CLEARCTR(x) (((uint32_t)(((uint32_t)(x)) << WKT_CTRL_CLEARCTR_SHIFT)) & WKT_CTRL_CLEARCTR_MASK) 7159 #define WKT_CTRL_SEL_EXTCLK_MASK (0x8U) 7160 #define WKT_CTRL_SEL_EXTCLK_SHIFT (3U) 7161 /*! SEL_EXTCLK - Select external or internal clock source for the self wake-up timer. The internal 7162 * clock source is selected by the CLKSEL bit in this register if SET_EXTCLK is set to internal. 7163 * 0b0..Internal. The clock source is the internal clock selected by the CLKSEL bit. 7164 * 0b1..External. The self wake-up timer uses the external WKTCLKIN pin. 7165 */ 7166 #define WKT_CTRL_SEL_EXTCLK(x) (((uint32_t)(((uint32_t)(x)) << WKT_CTRL_SEL_EXTCLK_SHIFT)) & WKT_CTRL_SEL_EXTCLK_MASK) 7167 /*! @} */ 7168 7169 /*! @name COUNT - Counter register. */ 7170 /*! @{ */ 7171 #define WKT_COUNT_VALUE_MASK (0xFFFFFFFFU) 7172 #define WKT_COUNT_VALUE_SHIFT (0U) 7173 /*! VALUE - A write to this register pre-loads start count value into the timer and starts the 7174 * count-down sequence. A read reflects the current value of the timer. 7175 */ 7176 #define WKT_COUNT_VALUE(x) (((uint32_t)(((uint32_t)(x)) << WKT_COUNT_VALUE_SHIFT)) & WKT_COUNT_VALUE_MASK) 7177 /*! @} */ 7178 7179 7180 /*! 7181 * @} 7182 */ /* end of group WKT_Register_Masks */ 7183 7184 7185 /* WKT - Peripheral instance base addresses */ 7186 /** Peripheral WKT base address */ 7187 #define WKT_BASE (0x40008000u) 7188 /** Peripheral WKT base pointer */ 7189 #define WKT ((WKT_Type *)WKT_BASE) 7190 /** Array initializer of WKT peripheral base addresses */ 7191 #define WKT_BASE_ADDRS { WKT_BASE } 7192 /** Array initializer of WKT peripheral base pointers */ 7193 #define WKT_BASE_PTRS { WKT } 7194 /** Interrupt vectors for the WKT peripheral type */ 7195 #define WKT_IRQS { WKT_IRQn } 7196 7197 /*! 7198 * @} 7199 */ /* end of group WKT_Peripheral_Access_Layer */ 7200 7201 7202 /* ---------------------------------------------------------------------------- 7203 -- WWDT Peripheral Access Layer 7204 ---------------------------------------------------------------------------- */ 7205 7206 /*! 7207 * @addtogroup WWDT_Peripheral_Access_Layer WWDT Peripheral Access Layer 7208 * @{ 7209 */ 7210 7211 /** WWDT - Register Layout Typedef */ 7212 typedef struct { 7213 __IO uint32_t MOD; /**< Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer., offset: 0x0 */ 7214 __IO uint32_t TC; /**< Watchdog timer constant register. This 24-bit register determines the time-out value., offset: 0x4 */ 7215 __O uint32_t FEED; /**< Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in TC., offset: 0x8 */ 7216 __I uint32_t TV; /**< Watchdog timer value register. This 24-bit register reads out the current value of the Watchdog timer., offset: 0xC */ 7217 uint8_t RESERVED_0[4]; 7218 __IO uint32_t WARNINT; /**< Watchdog Warning Interrupt compare value., offset: 0x14 */ 7219 __IO uint32_t WINDOW; /**< Watchdog Window compare value., offset: 0x18 */ 7220 } WWDT_Type; 7221 7222 /* ---------------------------------------------------------------------------- 7223 -- WWDT Register Masks 7224 ---------------------------------------------------------------------------- */ 7225 7226 /*! 7227 * @addtogroup WWDT_Register_Masks WWDT Register Masks 7228 * @{ 7229 */ 7230 7231 /*! @name MOD - Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer. */ 7232 /*! @{ */ 7233 #define WWDT_MOD_WDEN_MASK (0x1U) 7234 #define WWDT_MOD_WDEN_SHIFT (0U) 7235 /*! WDEN - Watchdog enable bit. Once this bit is set to one and a watchdog feed is performed, the 7236 * watchdog timer will run permanently. 7237 * 0b0..Stop. The watchdog timer is stopped. 7238 * 0b1..Run. The watchdog timer is running. 7239 */ 7240 #define WWDT_MOD_WDEN(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDEN_SHIFT)) & WWDT_MOD_WDEN_MASK) 7241 #define WWDT_MOD_WDRESET_MASK (0x2U) 7242 #define WWDT_MOD_WDRESET_SHIFT (1U) 7243 /*! WDRESET - Watchdog reset enable bit. Once this bit has been written with a 1 it cannot be re-written with a 0. 7244 * 0b0..Interrupt. A watchdog time-out will not cause a chip reset. 7245 * 0b1..Reset. A watchdog time-out will cause a chip reset. 7246 */ 7247 #define WWDT_MOD_WDRESET(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDRESET_SHIFT)) & WWDT_MOD_WDRESET_MASK) 7248 #define WWDT_MOD_WDTOF_MASK (0x4U) 7249 #define WWDT_MOD_WDTOF_SHIFT (2U) 7250 /*! WDTOF - Watchdog time-out flag. Set when the watchdog timer times out, by a feed error, or by 7251 * events associated with WDPROTECT. Cleared by software writing a 0 to this bit position. Causes a 7252 * chip reset if WDRESET = 1. 7253 */ 7254 #define WWDT_MOD_WDTOF(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDTOF_SHIFT)) & WWDT_MOD_WDTOF_MASK) 7255 #define WWDT_MOD_WDINT_MASK (0x8U) 7256 #define WWDT_MOD_WDINT_SHIFT (3U) 7257 /*! WDINT - Warning interrupt flag. Set when the timer is at or below the value in WDWARNINT. 7258 * Cleared by software writing a 1 to this bit position. Note that this bit cannot be cleared while the 7259 * WARNINT value is equal to the value of the TV register. This can occur if the value of 7260 * WARNINT is 0 and the WDRESET bit is 0 when TV decrements to 0. 7261 */ 7262 #define WWDT_MOD_WDINT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDINT_SHIFT)) & WWDT_MOD_WDINT_MASK) 7263 #define WWDT_MOD_WDPROTECT_MASK (0x10U) 7264 #define WWDT_MOD_WDPROTECT_SHIFT (4U) 7265 /*! WDPROTECT - Watchdog update mode. This bit can be set once by software and is only cleared by a reset. 7266 * 0b0..Flexible. The watchdog time-out value (TC) can be changed at any time. 7267 * 0b1..Threshold. The watchdog time-out value (TC) can be changed only after the counter is below the value of WDWARNINT and WDWINDOW. 7268 */ 7269 #define WWDT_MOD_WDPROTECT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDPROTECT_SHIFT)) & WWDT_MOD_WDPROTECT_MASK) 7270 #define WWDT_MOD_LOCK_MASK (0x20U) 7271 #define WWDT_MOD_LOCK_SHIFT (5U) 7272 /*! LOCK - Once this bit is set to one and a watchdog feed is performed, disabling or powering down 7273 * the watchdog oscillator is prevented by hardware. This bit can be set once by software and is 7274 * only cleared by any reset. 7275 */ 7276 #define WWDT_MOD_LOCK(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_LOCK_SHIFT)) & WWDT_MOD_LOCK_MASK) 7277 /*! @} */ 7278 7279 /*! @name TC - Watchdog timer constant register. This 24-bit register determines the time-out value. */ 7280 /*! @{ */ 7281 #define WWDT_TC_COUNT_MASK (0xFFFFFFU) 7282 #define WWDT_TC_COUNT_SHIFT (0U) 7283 /*! COUNT - Watchdog time-out value. 7284 */ 7285 #define WWDT_TC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_TC_COUNT_SHIFT)) & WWDT_TC_COUNT_MASK) 7286 /*! @} */ 7287 7288 /*! @name FEED - Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in TC. */ 7289 /*! @{ */ 7290 #define WWDT_FEED_FEED_MASK (0xFFU) 7291 #define WWDT_FEED_FEED_SHIFT (0U) 7292 /*! FEED - Feed value should be 0xAA followed by 0x55. 7293 */ 7294 #define WWDT_FEED_FEED(x) (((uint32_t)(((uint32_t)(x)) << WWDT_FEED_FEED_SHIFT)) & WWDT_FEED_FEED_MASK) 7295 /*! @} */ 7296 7297 /*! @name TV - Watchdog timer value register. This 24-bit register reads out the current value of the Watchdog timer. */ 7298 /*! @{ */ 7299 #define WWDT_TV_COUNT_MASK (0xFFFFFFU) 7300 #define WWDT_TV_COUNT_SHIFT (0U) 7301 /*! COUNT - Counter timer value. 7302 */ 7303 #define WWDT_TV_COUNT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_TV_COUNT_SHIFT)) & WWDT_TV_COUNT_MASK) 7304 /*! @} */ 7305 7306 /*! @name WARNINT - Watchdog Warning Interrupt compare value. */ 7307 /*! @{ */ 7308 #define WWDT_WARNINT_WARNINT_MASK (0x3FFU) 7309 #define WWDT_WARNINT_WARNINT_SHIFT (0U) 7310 /*! WARNINT - Watchdog warning interrupt compare value. 7311 */ 7312 #define WWDT_WARNINT_WARNINT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_WARNINT_WARNINT_SHIFT)) & WWDT_WARNINT_WARNINT_MASK) 7313 /*! @} */ 7314 7315 /*! @name WINDOW - Watchdog Window compare value. */ 7316 /*! @{ */ 7317 #define WWDT_WINDOW_WINDOW_MASK (0xFFFFFFU) 7318 #define WWDT_WINDOW_WINDOW_SHIFT (0U) 7319 /*! WINDOW - Watchdog window value. 7320 */ 7321 #define WWDT_WINDOW_WINDOW(x) (((uint32_t)(((uint32_t)(x)) << WWDT_WINDOW_WINDOW_SHIFT)) & WWDT_WINDOW_WINDOW_MASK) 7322 /*! @} */ 7323 7324 7325 /*! 7326 * @} 7327 */ /* end of group WWDT_Register_Masks */ 7328 7329 7330 /* WWDT - Peripheral instance base addresses */ 7331 /** Peripheral WWDT base address */ 7332 #define WWDT_BASE (0x40000000u) 7333 /** Peripheral WWDT base pointer */ 7334 #define WWDT ((WWDT_Type *)WWDT_BASE) 7335 /** Array initializer of WWDT peripheral base addresses */ 7336 #define WWDT_BASE_ADDRS { WWDT_BASE } 7337 /** Array initializer of WWDT peripheral base pointers */ 7338 #define WWDT_BASE_PTRS { WWDT } 7339 /** Interrupt vectors for the WWDT peripheral type */ 7340 #define WWDT_IRQS { WDT_IRQn } 7341 7342 /*! 7343 * @} 7344 */ /* end of group WWDT_Peripheral_Access_Layer */ 7345 7346 7347 /* 7348 ** End of section using anonymous unions 7349 */ 7350 7351 #if defined(__ARMCC_VERSION) 7352 #if (__ARMCC_VERSION >= 6010050) 7353 #pragma clang diagnostic pop 7354 #else 7355 #pragma pop 7356 #endif 7357 #elif defined(__GNUC__) 7358 /* leave anonymous unions enabled */ 7359 #elif defined(__IAR_SYSTEMS_ICC__) 7360 #pragma language=default 7361 #else 7362 #error Not supported compiler type 7363 #endif 7364 7365 /*! 7366 * @} 7367 */ /* end of group Peripheral_access_layer */ 7368 7369 7370 /* ---------------------------------------------------------------------------- 7371 -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). 7372 ---------------------------------------------------------------------------- */ 7373 7374 /*! 7375 * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). 7376 * @{ 7377 */ 7378 7379 #if defined(__ARMCC_VERSION) 7380 #if (__ARMCC_VERSION >= 6010050) 7381 #pragma clang system_header 7382 #endif 7383 #elif defined(__IAR_SYSTEMS_ICC__) 7384 #pragma system_include 7385 #endif 7386 7387 /** 7388 * @brief Mask and left-shift a bit field value for use in a register bit range. 7389 * @param field Name of the register bit field. 7390 * @param value Value of the bit field. 7391 * @return Masked and shifted value. 7392 */ 7393 #define NXP_VAL2FLD(field, value) (((value) << (field ## _SHIFT)) & (field ## _MASK)) 7394 /** 7395 * @brief Mask and right-shift a register value to extract a bit field value. 7396 * @param field Name of the register bit field. 7397 * @param value Value of the register. 7398 * @return Masked and shifted bit field value. 7399 */ 7400 #define NXP_FLD2VAL(field, value) (((value) & (field ## _MASK)) >> (field ## _SHIFT)) 7401 7402 /*! 7403 * @} 7404 */ /* end of group Bit_Field_Generic_Macros */ 7405 7406 7407 /* ---------------------------------------------------------------------------- 7408 -- SDK Compatibility 7409 ---------------------------------------------------------------------------- */ 7410 7411 /*! 7412 * @addtogroup SDK_Compatibility_Symbols SDK Compatibility 7413 * @{ 7414 */ 7415 7416 /* No SDK compatibility issues. */ 7417 7418 /*! 7419 * @} 7420 */ /* end of group SDK_Compatibility_Symbols */ 7421 7422 7423 #endif /* _LPC804_H_ */ 7424 7425
