1 /* 2 * Copyright 2021 ~ 2022 NXP 3 * All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 #ifndef _FSL_PF5020_H_ 8 #define _FSL_PF5020_H_ 9 10 /******************************************************************************* 11 * Includes 12 ******************************************************************************/ 13 #include "fsl_common.h" 14 15 /******************************************************************************* 16 * Definitions 17 ******************************************************************************/ 18 19 #define PF5020_DEVICE_ID 0x00U 20 #define PF5020_REV_ID 0x01U 21 #define PF5020_EMREV 0x02U 22 #define PF5020_PROG_ID 0x03U 23 #define PF5020_INT_STATUS1 0x04U 24 #define PF5020_INT_MASK1 0x05U 25 #define PF5020_INT_SENSE1 0x06U 26 #define PF5020_INT_STATUS2 0x07U 27 #define PF5020_INT_MASK2 0x08U 28 #define PF5020_INT_SENSE2 0x09U 29 #define PF5020_SW_MODE_INT 0x0AU 30 #define PF5020_SW_MODE_MASK 0x0BU 31 #define PF5020_SW_ILIM_INT 0x0CU 32 #define PF5020_SW_ILIM_MASK 0x0DU 33 #define PF5020_SW_ILIM_SENSE 0x0EU 34 #define PF5020_LDO_ILIM_INT 0x0FU 35 #define PF5020_LDO_ILIM_MASK 0x10U 36 #define PF5020_LDO_ILIM_SENSE 0x11U 37 #define PF5020_SW_UV_INT 0x12U 38 #define PF5020_SW_UV_MASK 0x13U 39 #define PF5020_SW_UV_SENSE 0x14U 40 #define PF5020_SW_OV_INT 0x15U 41 #define PF5020_SW_OV_MASK 0x16U 42 #define PF5020_SW_OV_SENSE 0x17U 43 #define PF5020_LDO_UV_INT 0x18U 44 #define PF5020_LDO_UV_MASK 0x19U 45 #define PF5020_LDO_UV_SENSE 0x1AU 46 #define PF5020_LDO_OV_INT 0x1BU 47 #define PF5020_LDO_OV_MASK 0x1CU 48 #define PF5020_LDO_OV_SENSE 0x1DU 49 #define PF5020_PWRON_INT 0x1EU 50 #define PF5020_PWRON_MASK 0x1FU 51 #define PF5020_PWRON_SENSE 0x20U 52 #define PF5020_EN_SENSE 0x21U 53 #define PF5020_SYS_INT 0x22U 54 #define PF5020_HARDFAULT_FLAGS 0x23U 55 56 #define PF5020_ABIST_PGOOD_MON 0x25U 57 #define PF5020_ABIST_OV1 0x26U 58 #define PF5020_ABIST_OV2 0x27U 59 #define PF5020_ABIST_UV1 0x28U 60 #define PF5020_ABIST_UV2 0x29U 61 #define PF5020_TEST_FLAGS 0x2AU 62 #define PF5020_ABIST_RUN 0x2BU 63 64 #define PF5020_RANDOM_GEN 0x2DU 65 #define PF5020_RANDOM_CHK 0x2EU 66 #define PF5020_VMONEN1 0x2FU 67 #define PF5020_VMONEN2 0x30U 68 #define PF5020_CTRL1 0x31U 69 #define PF5020_CTRL2 0x32U 70 #define PF5020_CTRL3 0x33U 71 #define PF5020_PWRUP_CTRL 0x34U 72 73 #define PF5020_RESETBMCU_PWRUP 0x36U 74 #define PF5020_PGOOD_PWRUP 0x37U 75 #define PF5020_PWRDN_DLY1 0x38U 76 #define PF5020_PWRDN_DLY2 0x39U 77 #define PF5020_FREQ_CTRL 0x3AU 78 79 #define PF5020_PWRON 0x3CU 80 #define PF5020_WD_CONFIG 0x3DU 81 #define PF5020_WD_CLEAR 0x3EU 82 #define PF5020_WD_EXPIRE 0x3FU 83 #define PF5020_WD_COUNTER 0x40U 84 #define PF5020_FAULT_COUNTER 0x41U 85 #define PF5020_FSAFE_COUNTER 0x42U 86 #define PF5020_FAULT_TIMERS 0x43U 87 #define PF5020_AMUX 0x44U 88 89 #define PF5020_SW_RAMP 0x46U 90 #define PF5020_SW1_CONFIG1 0x47U 91 #define PF5020_SW1_CONFIG2 0x48U 92 #define PF5020_SW1_PWRUP 0x49U 93 #define PF5020_SW1_MODE 0x4AU 94 #define PF5020_SW1_RUN_VOLT 0x4BU 95 #define PF5020_SW1_STBY_VOLT 0x4CU 96 97 #define PF5020_SW2_CONFIG1 0x4FU 98 #define PF5020_SW2_CONFIG2 0x50U 99 #define PF5020_SW2_PWRUP 0x51U 100 #define PF5020_SW2_MODE1 0x52U 101 #define PF5020_SW2_RUN_VOLT 0x53U 102 #define PF5020_SW2_STBY_VOLT 0x54U 103 104 #define PF5020_SWND1_CONFIG1 0x67U 105 #define PF5020_SWND1_CONFIG2 0x68U 106 #define PF5020_SWND1_PWRUP 0x69U 107 #define PF5020_SWND1_MODE1 0x6AU 108 #define PF5020_SWND1_RUN_VOLT 0x6BU 109 110 #define PF5020_LDO1_CONFIG1 0x6EU 111 #define PF5020_LDO1_CONFIG2 0x6FU 112 #define PF5020_LDO1_PWRUP 0x70U 113 #define PF5020_LDO1_RUN_VOLT 0x71U 114 #define PF5020_LDO1_STBY_VOLT 0x72U 115 116 #define PF5020_VSNVS_CONFIG1 0x75U 117 118 #define PF5020_PAGE_SELECT 0x77U 119 120 #define PF5020_INT_MASK_ARRAY \ 121 { \ 122 PF5020_INT_MASK1, PF5020_INT_MASK2, PF5020_SW_MODE_MASK, PF5020_SW_ILIM_MASK, PF5020_SW_UV_MASK, \ 123 PF5020_SW_OV_MASK, PF5020_PWRON_MASK \ 124 } 125 #define PF5020_INT_LATCH_ARRAY \ 126 { \ 127 PF5020_INT_STATUS1, PF5020_INT_STATUS2, PF5020_SW_MODE_INT, PF5020_SW_ILIM_INT, PF5020_SW_UV_INT, \ 128 PF5020_SW_OV_INT, PF5020_PWRON_INT \ 129 } 130 131 #define PF5020_SEQ_REG_ARRAY \ 132 { \ 133 PF5020_RESETBMCU_PWRUP, PF5020_PGOOD_PWRUP, PF5020_SW1_PWRUP, PF5020_SW2_PWRUP, PF5020_SWND1_PWRUP, \ 134 PF5020_LDO1_PWRUP \ 135 } 136 137 /*! 138 * @brief The enumeration of internal high speed clock frequency. 139 */ 140 typedef enum _pf5020_high_speed_clk_freq 141 { 142 kPF5020_HighSpeedClkFreq20MHz = 0x0U, /*!< High speed clock frequency is 20MHz, 143 switching regulator frequency is 2.5MHz. */ 144 kPF5020_HighSpeedClkFreq21MHz = 0x1U, /*!< High speed clock frequency is 21MHz, 145 switching regulator frequency is 2.625MHz. */ 146 kPF5020_HighSpeedClkFreq22MHz = 0x2U, /*!< High speed clock frequency is 22MHz, 147 switching regulator frequency is 2.750MHz. */ 148 kPF5020_HighSpeedClkFreq23MHz = 0x3U, /*!< High speed clock frequency is 23MHz, 149 switching regulator frequency is 2.875MHz. */ 150 kPF5020_HighSpeedClkFreq24MHz = 0x4U, /*!< High speed clock frequency is 24MHz, 151 switching regulator frequency is 3.0MHz. */ 152 kPF5020_HighSpeedClkFreq16MHz = 0x9U, /*!< High speed clock frequency is 16MHz, 153 switching regulator frequency is 2.0MHz. */ 154 kPF5020_HighSpeedClkFreq17MHz = 0xAU, /*!< High speed clock frequency is 17MHz, 155 switching regulator frequency is 2.125MHz. */ 156 kPF5020_HighSpeedClkFreq18MHz = 0xBU, /*!< High speed clock frequency is 18MHz, 157 switching regulator frequency is 2.25MHz. */ 158 kPF5020_HighSpeedClkFreq19MHz = 0xCU, /*!< High speed clock frequency is 19MHz, 159 switching regulator frequency is 2.375MHz. */ 160 } pf5020_high_speed_clk_freq_t; 161 162 /*! 163 * @brief The enumeration of internal high speed clock frequency range. 164 * 165 */ 166 typedef enum _pf5020_high_speed_clk_ss_range 167 { 168 kPF5020_HighSpeedClkSSRange0 = 0U, /*!< The maximum clock frequency range is +5%/-5%. */ 169 kPF5020_HighSpeedClkSSRange1 = 1U, /*!< The maximum clock frequency range is +10%/-10%. */ 170 } pf5020_high_speed_clk_ss_range_t; 171 172 /*! 173 * @brief The enumeration of VSNVS LDO output voltage, 0 means turn off VSNVS LDO. 174 */ 175 typedef enum _pf5020_vsnvs_ldo_output_voltage 176 { 177 kPF5020_VsnvsLdoOff = 0U, /*!< Turn off VSNVS LDO. */ 178 kPF5020_VsnvsLdoOutput1P8V, /*!< Vsnvs LDO output 1.8V. */ 179 kPF5020_VsnsLdoOutput3P0V, /*!< Vsnvs LDO output 3.0V. */ 180 kPF5020_VsnsLdoOutput3P3V, /*!< Vsnvs LDO output 3.3V. */ 181 } pf5020_vsnvs_ldo_output_voltage_t; 182 183 /*! 184 * @brief The enumeration of PF5020 internal regulators. 185 */ 186 typedef enum _pf5020_regulator_name 187 { 188 kPF5020_BuckRegulatorSw1 = 0x0U, /*!< Type1 Buck Regulator SW1. */ 189 kPF5020_BuckRegulatorSw2 = 0x1U, /*!< Type1 Buck Regulator SW2. */ 190 kPF5020_BuckRegulatorSwnd1 = 0x4U, /*!< Type2 Buck Regulator SWND1. */ 191 kPF5020_RegulatorLdo1 = 0x5U, /*!< Linear Regulator LDO1. */ 192 } pf5020_regulator_name_t; 193 194 /*! 195 * @brief The power down ramp and DVS rate during system on of type1 buck regulator. 196 */ 197 typedef enum _pf5020_type1_buck_regulator_dvs_ramp 198 { 199 kPF5020_DVSRamp0 = 0x0U, /*!< Type1 Buck regulator DVS ramp0. */ 200 kPF5020_DVSRamp1 = 0x1U, /*!< Type1 Buck regulator DVS ramp1. */ 201 kPF5020_DVSRamp2 = 0x2U, /*!< Type1 Buck regulator DVS ramp2. */ 202 kPF5020_DVSRamp3 = 0x3U, /*!< Type1 Buck regulator DVS ramp3. */ 203 } pf5020_type1_buck_regulator_dvs_ramp_t; 204 205 /*! 206 * @brief The enumeration of all buck regulators'(SW1, SW2, SWND1) operate modes. 207 */ 208 typedef enum _pf5020_buck_regulator_operate_mode 209 { 210 kPF5020_BuckRegulatorOff = 0x0U, /*!< Turn off buck regulator. */ 211 kPF5020_BuckRegulatorPWMMode, /*!< Set buck regulator as PWM mode. */ 212 kPF5020_BuckRegulatorPFMMode, /*!< Set buck regulator as PFM mode. */ 213 kPF5020_BuckRegulatorAutoSkipMode, /*!< Set buck regulator as Auto skip mode. */ 214 } pf5020_buck_regulator_operate_mode_t; 215 216 /*! 217 * @brief The enumeration of all buck regulators'(SW1, SW2, SWND1) phase shift values. 218 */ 219 typedef enum _pf5020_buck_regulator_phase_shift 220 { 221 kPF5020_BuckRegulatorPhaseShift45 = 0x0U, /*!< Phase shift 45 degrees. */ 222 kPF5020_BuckRegulatorPhaseShift90 = 0x1U, /*!< Phase shift 90 degrees. */ 223 kPF5020_BuckRegulatorPhaseShift135 = 0x2U, /*!< Phase shift 135 degrees. */ 224 kPF5020_BuckRegulatorPhaseShift180 = 0x3U, /*!< Phase shift 180 degrees. */ 225 kPF5020_BuckRegulatorPhaseShift225 = 0x4U, /*!< Phase shift 225 degrees. */ 226 kPF5020_BuckRegulatorPhaseShift270 = 0x5U, /*!< Phase shift 270 degrees. */ 227 kPF5020_BuckRegulatorPhaseShift315 = 0x6U, /*!< Phase shift 315 degrees. */ 228 kPF5020_BuckRegulatorPhaseShift0 = 0x7U, /*!< Phase shift 0 degrees. */ 229 } pf5020_buck_regulator_phase_shift_t; 230 231 /*! 232 * @brief The enumeration of all buck regulators'(SW1, SW2, SWND1) current limitation value. 233 */ 234 typedef enum _pf5020_buck_regulator_current_limit 235 { 236 kPF5020_BuckRegulatorCurrentLimitBypass = 0x4U, /*!< Current limit fault bypassed. */ 237 kPF5020_BuckRegulatorCurrentLimit0 = 0x0U, /*!< Current limit protection enabled and current limit is 2.1A. */ 238 kPF5020_BuckRegulatorCurrentLimit1 = 0x1U, /*!< Current limit protection enabled and current limit is 2.6A. */ 239 kPF5020_BuckRegulatorCurrentLimit2 = 0x2U, /*!< Current limit protection enabled and current limit is 3.0A. */ 240 kPF5020_BuckRegulatorCurrentLimit3 = 0x3U, /*!< Current limit protection enabled and current limit is 4.5A. */ 241 } pf5020_buck_regulator_current_limit_t; 242 243 /*! 244 * @brief The enumeration of SWND1 buck regulator output voltage. 245 */ 246 typedef enum _pf5020_swnd1_output_voltage 247 { 248 kPF5020_Swnd1Output1V = 0x0U, /*!< SWND1 output 1.0V during run state and standby state. */ 249 kPF5020_Swnd1Output1P1V, /*!< SWND1 output 1.1V during run state and standby state. */ 250 kPF5020_Swnd1Output1P2V, /*!< SWND1 output 1.2V during run state and standby state. */ 251 kPF5020_Swnd1Output1P25V, /*!< SWND1 output 1.25V during run state and standby state. */ 252 kPF5020_Swnd1Output1P3V, /*!< SWND1 output 1.3V during run state and standby state. */ 253 kPF5020_Swnd1Output1P35V, /*!< SWND1 output 1.35V during run state and standby state. */ 254 kPF5020_Swnd1Output1P5V, /*!< SWND1 output 1.5V during run state and standby state. */ 255 kPF5020_Swnd1Output1P6V, /*!< SWND1 output 1.6V during run state and standby state. */ 256 kPF5020_Swnd1Output1P8V, /*!< SWND1 output 1.8V during run state and standby state. */ 257 kPF5020_Swnd1Output1P85V, /*!< SWND1 output 1.85V during run state and standby state. */ 258 259 kPF5020_Swnd1Output2P0V, /*!< SWND1 output 2.0V during run state and standby state. */ 260 kPF5020_Swnd1Output2P1V, /*!< SWND1 output 2.1V during run state and standby state. */ 261 kPF5020_Swnd1Output2P15V, /*!< SWND1 output 2.15V during run state and standby state. */ 262 kPF5020_Swnd1Output2P25V, /*!< SWND1 output 2.25V during run state and standby state. */ 263 kPF5020_Swnd1Output2P3V, /*!< SWND1 output 2.3V during run state and standby state. */ 264 kPF5020_Swnd1Output2P4V, /*!< SWND1 output 2.4V during run state and standby state. */ 265 kPF5020_Swnd1Output2P5V, /*!< SWND1 output 2.5V during run state and standby state. */ 266 kPF5020_Swnd1Output2P8V, /*!< SWND1 output 2.8V during run state and standby state. */ 267 268 kPF5020_Swnd1Output3P15V, /*!< SWND1 output 3.15V during run state and standby state. */ 269 kPF5020_Swnd1Output3P20V, /*!< SWND1 output 3.20V during run state and standby state. */ 270 kPF5020_Swnd1Output3P25V, /*!< SWND1 output 3.25V during run state and standby state. */ 271 kPF5020_Swnd1Output3P30V, /*!< SWND1 output 3.30V during run state and standby state. */ 272 kPF5020_Swnd1Output3P35V, /*!< SWND1 output 3.3V during run state and standby state. */ 273 kPF5020_Swnd1Output3P40V, /*!< SWND1 output 3.40V during run state and standby state. */ 274 kPF5020_Swnd1Output3P50V, /*!< SWND1 output 3.50V during run state and standby state. */ 275 kPF5020_Swnd1Output3P80V, /*!< SWND1 output 3.80V during run state and standby state. */ 276 277 kPF5020_Swnd1Output4P0V, /*!< SWND1 output 4.0V during run state and standby state. */ 278 kPF5020_Swnd1Output4P1V, /*!< SWND1 output 4.1V during run state and standby state. */ 279 } pf5020_swnd1_output_voltage_t; 280 281 /*! 282 * @brief The enumeration of LDO1 output voltage. 283 */ 284 typedef enum _pf5020_ldo1_output_voltage 285 { 286 kPF5020_Ldo1Output1P5V = 0x0U, /*!< LDO1 output 1.5V. */ 287 kPF5020_Ldo1Output1P6V, /*!< LDO1 output 1.6V */ 288 kPF5020_Ldo1Output1P8V, /*!< LDO1 output 1.8V */ 289 kPF5020_Ldo1Output1P85V, /*!< LDO1 output 1.85V */ 290 kPF5020_Ldo1Output2P15V, /*!< LDO1 output 2.15V */ 291 kPF5020_Ldo1Output2P5V, /*!< LDO1 output 2.5V */ 292 kPF5020_Ldo1Output2P8V, /*!< LDO1 output 2.8V */ 293 kPF5020_Ldo1Output3P0V, /*!< LDO1 output 3.0V */ 294 kPF5020_Ldo1Output3P1V, /*!< LDO1 output 3.1V */ 295 kPF5020_Ldo1Output3P15V, /*!< LDO1 output 3.15V */ 296 kPF5020_Ldo1Output3P2V, /*!< LDO1 output 3.2V */ 297 kPF5020_Ldo1Output3P3V, /*!< LDO1 output 3.3V */ 298 kPF5020_Ldo1Output3P35V, /*!< LDO1 output 3.35V */ 299 kPF5020_Ldo1Output4P0V, /*!< LDO1 output 4.0V */ 300 kPF5020_Ldo1Output4P9V, /*!< LDO1 output 4.9V */ 301 kPF5020_Ldo1Output5P0V, /*!< LDO1 output 5.0V */ 302 } pf5020_ldo1_output_voltage_t; 303 304 /*! 305 * @brief The enumeration of UV debounce time. 306 */ 307 typedef enum _pf5020_uv_debounce_time 308 { 309 kPF5020_UVDebounceTime5us = 0x0U, /*!< UV debounce time will be set as 5us. */ 310 kPF5020_UVDebounceTime15us, /*!< UV debounce time will be set as 15us. */ 311 kPF5020_UVDebounceTime30us, /*!< UV debounce time will be set as 30us. */ 312 kPF5020_UVDebounceTime40us, /*!< UV debounce time will be set as 40us. */ 313 } pf5020_uv_debounce_time_t; 314 315 /*! 316 * @brief The enumeration of OV debounce time. 317 */ 318 typedef enum _pf5020_ov_debounce_time 319 { 320 kPF5020_OVDebounceTime30us = 0x0U, /*!< OV debounce time will be set as 30us. */ 321 kPF5020_OVDebounceTime50us, /*!< OV debounce time will be set as 50us. */ 322 kPF5020_OVDebounceTime80us, /*!< OV debounce time will be set as 80us. */ 323 kPF5020_OVDebounceTime125us, /*!< OV debounce time will be set as 125us. */ 324 } pf5020_ov_debounce_time_t; 325 326 /*! 327 * @brief The enumeration of different reset behaviors triggered by WDI pin. 328 */ 329 typedef enum _pf5020_wdi_mode 330 { 331 kPF5020_WDIPerformSoftWDReset = 0U, /*!< A WDI pin assert performs a hard WD reset. */ 332 kPF5020_WDIPerformHardWDReset = 1U, /*!< A WDI pin assert performs a soft WD reset. */ 333 } pf5020_wdi_mode_t; 334 335 /*! 336 * @brief The enumeration of temperature sensor's operate mode. 337 */ 338 typedef enum _pf5020_temp_sensor_operate_mode 339 { 340 kPF5020_TempSensorSampleMode = 0U, /*!< Temperature sensor operates in sampling mode to 341 reduce current consumption. */ 342 kPF5020_TempSensorAlwaysOnMode = 1U, /*!< Temperatue sensor operates in Always on mode. */ 343 } pf5020_temp_sensor_operate_mode_t; 344 345 /*! 346 * @brief The enumeration of AMUX selection. 347 */ 348 typedef enum _pf5020_amux_selection 349 { 350 kPF5020_AmuxSelDisable = 0x0U, /*!< AMUX selection disabled, internal signal dividing ratio N/A. */ 351 kPF5020_AmuxSelTempIc = 0x7U, /*!< AMUX selection TEMP_IC, internal signal dividing ratio 1. */ 352 } pf5020_amux_selection_t; 353 354 /*! 355 * @brief The enumeration of interupts that PF5020 support, the member of this enumeration can be used to enable/disable 356 * interrupts or get interrupt status flags. 357 */ 358 typedef enum _pf5020_interrupts 359 { 360 kPF5020_IntStatus1_VinOVLOInterrupt = 0x1ULL, /*!< Used to enable/disable Int Status1 Vin OVLO interrupt. */ 361 kPF5020_IntStatus1_PgoodInterrupt = 0x2ULL, /*!< Used to enable/disable Int Status1 PGOOD interrupt. */ 362 kPF5020_IntStatus1_PwrdnInterrupt = 0x8ULL, /*!< Used to enable/disable Int Status1 PWRDN interrupt. */ 363 kPF5020_IntStatus1_PwrupInterrupt = 0x10ULL, /*!< Used to enable/disable Int Status1 PWRUP interrupt. */ 364 kPF5020_IntStatus1_CrcInterrupt = 0x20ULL, /*!< Used to enable/disable Int Status1 CRC interrupt. */ 365 kPF5020_IntStatus1_FreqRdyInterrupt = 0x40ULL, /*!< Used to enable/disable Int Status1 frequency ready interrupt. */ 366 kPF5020_IntStatus1_SdwnInterrupt = 0x80ULL, /*!< Used to enable/disable Int Status1 SDWN interrupt. */ 367 368 kPF5020_IntStatus2_Therm80Interrupt = (0x1ULL << 8ULL), /*!< Used to enable/disable Int 369 Status2 therm 80 interrupt. */ 370 kPF5020_IntStatus2_Therm95Interrupt = (0x2ULL << 8ULL), /*!< Used to enable/disable Int 371 Status2 therm 95 interrupt. */ 372 kPF5020_IntStatus2_Therm110Interrupt = (0x4ULL << 8ULL), /*!< Used to enable/disable Int 373 Status2 therm 110 interrupt. */ 374 kPF5020_IntStatus2_Therm125Interrupt = (0x8ULL << 8ULL), /*!< Used to enable/disable Int 375 Status2 therm 125 interrupt. */ 376 kPF5020_IntStatus2_Therm140Interrupt = (0x10ULL << 8ULL), /*!< Used to enable/disable Int 377 Status2 therm 140 interrupt. */ 378 kPF5020_IntStatus2_Therm155Interrupt = (0x20ULL << 8ULL), /*!< Used to enable/disable Int 379 Status2 therm 155 interrupt. */ 380 kPF5020_IntStatus2_FsyncFltInterrupt = (0x40ULL << 8ULL), /*!< Used to enable/disable Int 381 Status2 Fsync filter interrupt. */ 382 kPF5020_IntStatus2_WdiInterrupt = (0x80ULL << 8ULL), /*!< Used to enable/disable Int Status2 WDI interrupt. */ 383 384 kPF5020_SwMode_Sw1ModeInterrupt = (0x1ULL << 16ULL), /*!< Used to enable/disable SW1 mode interrupt. */ 385 kPF5020_SwMode_Sw2ModeInterrupt = (0x2ULL << 16ULL), /*!< Used to enable/disable SW2 interrupt. */ 386 kPF5020_SwMode_Swnd1ModeInterrupt = (0x40ULL << 16ULL), /*!< Used to enable/disable SWND1 interrupt. */ 387 388 kPF5020_ILIM_Sw1IlimInterrupt = (0x1ULL << 24ULL), /*!< Used to enable/disable SW1 ILIM interrupt. */ 389 kPF5020_ILIM_Sw2IlimInterrupt = (0x2ULL << 24ULL), /*!< Used to enable/disable SW2 ILIM interrupt. */ 390 kPF5020_ILIM_Swnd1IlimInterrupt = (0x40ULL << 24ULL), /*!< Used to enable/disable SWND1 ILIM interrupt. */ 391 392 kPF5020_ILIM_Ldo1IlimInterrupt = (0x80ULL << 24ULL), /*!< Used to enable/disable LDO1 ILIM interrupt. */ 393 394 kPF5020_UV_Sw1UvInterrupt = (0x1ULL << 32ULL), /*!< Used to enable/disable SW1 UV interrupt. */ 395 kPF5020_UV_Sw2UvInterrupt = (0x2ULL << 32ULL), /*!< Used to enable/disable SW2 UV interrupt. */ 396 kPF5020_UV_Swnd1UvInterrupt = (0x40ULL << 32ULL), /*!< Used to enable/disable SWND1 UV interrupt. */ 397 398 kPF5020_UV_Ldo1UvInterrupt = (0x80ULL << 32ULL), /*!< Used to enable/disable SW1 LDO1 interrupt. */ 399 400 kPF5020_OV_Sw1OvInterrupt = (0x1ULL << 40ULL), /*!< Used to enable/disable SW1 OV interrupt. */ 401 kPF5020_OV_Sw2OvInterrupt = (0x2ULL << 40ULL), /*!< Used to enable/disable SW2 OV interrupt. */ 402 kPF5020_OV_Swnd1OvInterrupt = (0x40ULL << 40ULL), /*!< Used to enable/disable SWND1 OV interrupt. */ 403 404 kPF5020_OV_Ldo1OvInterrupt = (0x80ULL << 40ULL), /*!< Used to enable/disable LDO1 OV interrupt. */ 405 406 kPF5020_Pwron_PushInterrupt = (0x1ULL << 48ULL), /*!< Used to enable/disable PWRON Push interrupt. */ 407 kPF5020_Pwron_RelInterrupt = (0x2ULL << 48ULL), /*!< Used to enable/disable PWRON REL interrupt. */ 408 kPF5020_Pwron_1sInterrupt = (0x4ULL << 48ULL), /*!< Used to enable/disable PWRON 1s interrupt. */ 409 kPF5020_Pwron_2sInterrupt = (0x8ULL << 48ULL), /*!< Used to enable/disable PWRON 2s interrupt. */ 410 kPF5020_Pwron_3sInterrupt = (0x10ULL << 48ULL), /*!< Used to enable/disable PWRON 3s interrupt. */ 411 kPF5020_Pwron_4sInterrupt = (0x20ULL << 48ULL), /*!< Used to enable/disable PWRON 4s interrupt. */ 412 kPF5020_Pwron_8sInterrupt = (0x40ULL << 48ULL), /*!< Used to enable/disable PWRON 8s interrupt. */ 413 kPF5020_Pwron_BgmonInterrupt = (0x80ULL << 48ULL), /*!< Used to enable/disable PWRON BGMON interrupt. */ 414 415 kPF5020_AllInterrupts = 0xFFC3C3C343FFFBULL, /*!< All interrupts. */ 416 } pf5020_interrupt_t; 417 418 /*! 419 * @brief The enumeration of sequence time base. 420 */ 421 typedef enum _pf5020_sequencer_time_base 422 { 423 kPF5020_TimeBase30us = 0x0U, /*!< Sequencer time base is 30us. */ 424 kPF5020_TimeBase120us = 0x1U, /*!< Sequencer time base is 120us. */ 425 kPF5020_TimeBase250us = 0x2U, /*!< Sequencer time base is 250us. */ 426 kPF5020_TimeBase500us = 0x3U, /*!< Sequencer time base is 500us. */ 427 } pf5020_sequencer_time_base_t; 428 429 /*! 430 * @brief The enumeration of power down mode, including sequential mode and group mode. 431 */ 432 typedef enum _pf5020_power_down_mode 433 { 434 kPF5020_PowerDownSequentialMode = 0U, /*!< Use the same sequence slot value as the power up sequence to power 435 down in reverse order. */ 436 kPF5020_PowerDownGroupMode = 1U, /*!< Power down in groups, all regulators assigned to the same group are 437 disabled at the same time when the corresponding group is due to be 438 disabled. */ 439 } pf5020_power_down_mode_t; 440 441 /*! 442 * @brief The enumeration of power down group, group 4 being the lowest hierarchy and 443 * group 1 the highest hierarchy group. 444 */ 445 typedef enum _pf5020_power_down_group 446 { 447 kPF5020_PowerDownGroup4 = 0x0U, /*!< Power down group4. */ 448 kPF5020_PowerDownGroup3, /*!< Power down group3. */ 449 kPF5020_PowerDownGroup2, /*!< Power down group2. */ 450 kPF5020_PowerDownGroup1, /*!< Power down group1. */ 451 } pf5020_power_down_group_t; 452 453 /*! 454 * @brief The enumeration of power down delay. 455 */ 456 typedef enum _pf5020_power_down_delay 457 { 458 kPF5020_PowerDownDelay120us = 0x0, /*!< Power down delay 120us. */ 459 kPF5020_PowerDownDelay250us = 0x1, /*!< Power down delay 250us. */ 460 kPF5020_PowerDownDelay500us = 0x2, /*!< Power down delay 500us. */ 461 kPF5020_PowerDownDelay1000us = 0x3, /*!< Power down delay 1000us. */ 462 } pf5020_power_down_delay_t; 463 464 /*! 465 * @brief The enumeration of delay after RESETBMCU is asserted. 466 */ 467 typedef enum _pf5020_resetBMCU_delay 468 { 469 kPF5020_ResetBMcuDelayOff = 0x0U, /*!< RESETBMCU no delay. */ 470 kPF5020_ResetBMcuDelay10us, /*!< RESETBMCU delay 10 us. */ 471 kPF5020_ResetBMcuDelay100us, /*!< RESETBMCU delay 100 us. */ 472 kPF5020_ResetBMcuDelay500us, /*!< RESETBMCU delay 500 us. */ 473 } pf5020_resetBMCU_delay_t; 474 475 /*! 476 * @brief Internal high speed clock configuration. 477 */ 478 typedef struct _pf5020_high_speed_clk_config 479 { 480 pf5020_high_speed_clk_freq_t clkFreq; /*!< The frequency of internal high speed clock, 481 please refer to @ref pf5020_high_speed_clk_freq_t for details. */ 482 bool enableSS; /*!< Enable/disable spread-spectrum, 483 - \b true Enable spread-spectrum; 484 - \b false Disable spread-spectrum. */ 485 pf5020_high_speed_clk_ss_range_t ssRange; /*!< The range of internal high speed clock, 486 please refer to @ref pf5020_high_speed_clk_ss_range_t. */ 487 } pf5020_high_speed_clk_config_t; 488 489 /*! 490 * @brief Type1 buck regulator SW1 global configuration, including run/standby operate mode, run/standby voltage value. 491 */ 492 typedef struct _pf5020_sw1_regulator_config 493 { 494 pf5020_type1_buck_regulator_dvs_ramp_t sw1DvsRamp; /*!< SW1 DVS Ramp, please refer to 495 @ref pf5020_type1_buck_regulator_dvs_ramp_t 496 for details. */ 497 498 uint8_t sw1RunOutputVolt; /*!< The output voltage during RUN state, the step is 6.25mV, 499 0: 0.4V, 177: 1.8V, 178 to 255 reserved. */ 500 pf5020_buck_regulator_operate_mode_t sw1RunOperateMode; /*!< SW1 operate mode in run state, please refer to 501 @ref pf5020_buck_regulator_operate_mode_t for details. */ 502 503 uint8_t sw1StandbyOutputVolt; /*!< The output voltage during standby state, the step is 6.25mV, 504 0: 0.4V, 177: 1.8V, 178 to 255 reserved. */ 505 pf5020_buck_regulator_operate_mode_t sw1StandbyOperateMode; /*!< SW1 operate mode in standby mode. */ 506 507 pf5020_buck_regulator_phase_shift_t sw1PhaseShift; /*!< SW1 buck regulator phase shift value, please refer 508 to @ref pf5020_buck_regulator_phase_shift_t for details. */ 509 510 pf5020_buck_regulator_current_limit_t sw1CurrentLimit; /*!< SW1 buck regulator current limitation value, please 511 refer to @ref pf5020_buck_regulator_current_limit_t 512 for details. */ 513 bool sw1EnableUVBypass; /*!< Used to control whether bypass UV monitor for SW1, 514 - \b true Bypass UV monitor for SW1. 515 - \b false Don't bypass UV monitor for SW1. */ 516 bool sw1EnableOVBypass; /*!< Used to control whether bypass OV monitor for SW1, 517 - \b true Bypass OV monitor for SW1. 518 - \b false Don't bypass OV monitor for SW1. */ 519 bool sw1FaultReEnabled; /*!< Used to control whether return to sw1 regulator previous state 520 if fault condition is cleared. 521 - \b true SW1 regulator remains disabled after the fault condition is cleared 522 or no longer present. 523 - \b false SW1 regulator returns to its previous state if fault condition is cleared. */ 524 525 bool sw1EnablePGMonitor; /*!< Enable/disable SW1 regulator PG monitor. */ 526 527 bool sw1EnableWatchdogBypass; /*!< Enable/disable watchdog bypass, 528 - \b true The watchdog bypass is enabled and the output of the SW1 regulator 529 is not affected by the soft WD reset, keeping its current 530 configuration. 531 - \b false The watchdog bypass is disabled and the output of the SW1 532 regulator is returned to its default OTP value during the 533 soft WD reset. */ 534 } pf5020_sw1_regulator_config_t; 535 536 /*! 537 * @brief Type1 buck regulator SW2 global configuration, including run/standby operate mode, run/standby voltage value. 538 */ 539 typedef struct _pf5020_sw2_regulator_config 540 { 541 pf5020_type1_buck_regulator_dvs_ramp_t sw2DvsRamp; /*!< SW2 DVS Ramp, please refer to 542 @ref pf5020_type1_buck_regulator_dvs_ramp_t 543 for details. */ 544 545 uint8_t sw2RunOutputVolt; /*!< The output voltage during RUN state, the step is 6.25mV, 546 0: 0.4V, 177: 1.8V, 178 to 255 reserved. */ 547 pf5020_buck_regulator_operate_mode_t 548 sw2RunOperateMode; /*!< SW2 operate mode in run state, please refer to 549 @ref pf5020_buck_regulator_operate_mode_t for details. */ 550 551 uint8_t sw2StandbyOutputVolt; /*!< The output voltage during standby state, the step is 6.25mV, 552 0: 0.4V, 177: 1.8V, 178 to 255 reserved. */ 553 pf5020_buck_regulator_operate_mode_t sw2StandbyOperateMode; /*!< SW2 operate mode in standby mode. */ 554 555 pf5020_buck_regulator_phase_shift_t sw2PhaseShift; /*!< SW2 buck regulator phase shift value, please refer 556 to @ref pf5020_buck_regulator_phase_shift_t for details. */ 557 558 bool sw2EnableVTTOperation; /*!< Enable/disable VTT mode, VTT mode used to create VTT termination 559 for DDR memories. */ 560 561 pf5020_buck_regulator_current_limit_t sw2CurrentLimit; /*!< SW2 buck regulator current limitation value, please 562 refer to @ref pf5020_buck_regulator_current_limit_t 563 for details. */ 564 bool sw2EnableUVBypass; /*!< Used to control whether bypass UV monitor for SW2, 565 - \b true Bypass UV monitor for SW2. 566 - \b false Don't bypass UV monitor for SW2. */ 567 bool sw2EnableOVBypass; /*!< Used to control whether bypass OV monitor for SW2, 568 - \b true Bypass OV monitor for SW2. 569 - \b false Don't bypass OV monitor for SW2. */ 570 bool sw2FaultReEnabled; /*!< Used to control whether return to sw2 regulator previous state 571 if fault condition is cleared. 572 - \b true SW2 regulator remains disabled after the fault condition is cleared 573 or no longer present. 574 - \b false SW2 regulator returns to its previous state if fault condition is cleared. */ 575 576 bool sw2EnablePGMonitor; /*!< Enable/disable SW2 regulator PG monitor. */ 577 578 bool sw2EnableWatchdogBypass; /*!< Enable/disable watchdog bypass, 579 - \b true The watchdog bypass is enabled and the output of the SW2 regulator 580 is not affected by the soft WD reset, keeping its current 581 configuration. 582 - \b false The watchdog bypass is disabled and the output of the SW2 583 regulator is returned to its default OTP value during the 584 soft WD reset. */ 585 586 } pf5020_sw2_regulator_config_t; 587 588 /*! 589 * @brief Type2 buck regulator SWND1 global configuration, including run/standby operate mode, output voltage value. 590 */ 591 typedef struct _pf5020_swnd1_regulator_config 592 { 593 pf5020_swnd1_output_voltage_t swnd1OutputVolt; /*!< This member sets the output voltage during RUN 594 and Standby state. */ 595 pf5020_buck_regulator_operate_mode_t swnd1RunOperateMode; /*!< SWND1 operate mode in run state, please refer to 596 @ref pf5020_buck_regulator_operate_mode_t for details. */ 597 pf5020_buck_regulator_operate_mode_t swnd1StandbyOperateMode; /*!< SWND1 operate mode in standby mode. */ 598 599 pf5020_buck_regulator_phase_shift_t swnd1PhaseShift; /*!< SWND1 buck regulator phase shift value, please refer 600 to @ref pf5020_buck_regulator_phase_shift_t for details. */ 601 602 pf5020_buck_regulator_current_limit_t swnd1CurrentLimit; /*!< SWND1 buck regulator current limitation value, please 603 refer to @ref pf5020_buck_regulator_current_limit_t 604 for details. */ 605 bool swnd1EnableUVBypass; /*!< Used to control whether bypass UV monitor for SWND1, 606 - \b true Bypass UV monitor for SWND1. 607 - \b false Don't bypass UV monitor for SWND1. */ 608 bool swnd1EnableOVBypass; /*!< Used to control whether bypass OV monitor for SWND1, 609 - \b true Bypass OV monitor for SWND1. 610 - \b false Don't bypass OV monitor for SWND1. */ 611 bool swnd1FaultReEnabled; /*!< Used to control whether return to swnd1 regulator previous state 612 if fault condition is cleared. 613 - \b true SWND1 regulator remains disabled after the fault condition is cleared 614 or no longer present. 615 - \b false SWND1 regulator returns to its previous state if fault condition is cleared. */ 616 617 bool swnd1EnablePGMonitor; /*!< Enable/disable SWND1 regulator PG monitor. */ 618 619 bool swnd1EnableWatchdogBypass; /*!< Enable/disable watchdog bypass, 620 - \b true The watchdog bypass is enabled and the output of the SWND1 regulator 621 is not affected by the soft WD reset, keeping its current 622 configuration. 623 - \b false The watchdog bypass is disabled and the output of the SWND1 624 regulator is returned to its default OTP value during the 625 soft WD reset. */ 626 } pf5020_swnd1_regulator_config_t; 627 628 /*! 629 * @brief Linear regulator LDO1 global configuration, including run/standby operate mode, output voltage value and so 630 * on. 631 */ 632 typedef struct _pf5020_ldo1_regulator_config 633 { 634 bool ldo1RunEnable; /*!< Enable/disable LDO1 in run state, 635 - \b true Enable LDO1 in run state; 636 - \b false Disable LDO1 in run state. */ 637 pf5020_ldo1_output_voltage_t ldo1RunOutputVolt; /*!< Used to set the output voltage of LDO1 in run state, 638 please refer to @ref pf5020_ldo1_output_voltage_t. */ 639 640 bool ldo1StandbyEnable; /*!< Enable/disable LDO1 in standby state, 641 - \b true Enable LDO1 in standby state; 642 - \b false Disable LDO1 in standby state. */ 643 pf5020_ldo1_output_voltage_t ldo1StandbyOutputVolt; /*!< Used to set the output voltage of LDO1 in standby state, 644 please refer to @ref pf5020_ldo1_output_voltage_t. */ 645 646 bool ldo1EnableUVBypass; /*!< Used to control whether bypass UV monitor for LDO1, 647 - \b true Bypass UV monitor for LDO1. 648 - \b false Don't bypass UV monitor for LDO1. */ 649 bool ldo1EnableOVBypass; /*!< Used to control whether bypass OV monitor for LDO1, 650 - \b true Bypass OV monitor for LDO1. 651 - \b false Don't bypass OV monitor for LDO1. */ 652 bool ldo1EnableILIMBypass; /*!< Used to control whether bypass ILIM monitor for LDO1, 653 - \b true Bypass ILIM monitor for LDO1. 654 - \b false Don't bypass ILIM monitor for LDO1. */ 655 656 bool ldo1FaultReEnabled; /*!< Used to control whether return to ldo1 regulator previous state 657 if fault condition is cleared. 658 - \b true LDO1 regulator remains disabled after the fault condition is cleared 659 or no longer present. 660 - \b false LDO1 regulator returns to its previous state if fault condition is 661 cleared. */ 662 663 bool ldo1EnablePGMonitor; /*!< Enable/disable LDO1 regulator PG monitor. */ 664 665 bool ldo1EnableWatchdogBypass; /*!< Enable/disable watchdog bypass, 666 - \b true The watchdog bypass is enabled and the output of the LDO1 regulator 667 is not affected by the soft WD reset, keeping its current 668 configuration. 669 - \b false The watchdog bypass is disabled and the output of the LDO1 670 regulator is returned to its default OTP value during the 671 soft WD reset. */ 672 } pf5020_ldo1_regulator_config; 673 674 /*! 675 * @brief Internal watchdog timer configuration, including timer duration, cyclic counter max value and so on. 676 */ 677 typedef struct _pf5020_wdog_internal_timer_config 678 { 679 bool enable; /*!< Enable/disable the internal watchdog timer operation. */ 680 bool enableStandby; /*!< Enable/disable the internal watchdog timer operation during standby. */ 681 uint8_t timerDuration; /*!< The internal watchdog timer expire duration value, ranges from 0 to 15, 682 the actual expire time = 2 ^ timerDuration. */ 683 uint8_t cyclicCounterMaxVale; /*!< The max value of watchdog cyclic counter, and the cyclic counter is used 684 to ensure no cyclic watchdog condition occurs. */ 685 } pf5020_wdog_internal_timer_config_t; 686 687 /*! 688 * @brief PF5020 power up sequence configuration. 689 */ 690 typedef struct _pf5020_power_up_sequence 691 { 692 uint8_t resetBMCUSeq; /*!< The sequence slot of RESETBMCU pin in power up sequence, sequence code 0 indicates that 693 the RESETBMCU is not part of the power up sequence. */ 694 uint8_t pGoodSeq; /*!< The sequence slot of PGOOD pin in power up sequence, sequence code 0 indicates that 695 the PGOOD is not part of the power up sequence. */ 696 uint8_t sw1Seq; /*!< The sequence slot of SW1 regulator in power up sequence, sequence code 0 indicates that 697 the SW1 regulator is not part of the power up sequence. */ 698 uint8_t sw2Seq; /*!< The sequence slot of SW2 regulator in power up sequence, sequence code 0 indicates that 699 the SW2 regulator is not part of the power up sequence. */ 700 uint8_t swnd1Seq; /*!< The sequence slot of SWND1 regulator in power up sequence, sequence code 0 indicates that 701 the SWND1 regulator is not part of the power up sequence. */ 702 uint8_t ldo1Seq; /*!< The sequence slot of LDO in power up sequence, sequence code 0 indicates that 703 the LDO is not part of the power up sequence. */ 704 } pf5020_power_up_sequence_t; 705 706 /*! 707 * @brief PF5020 power down group configuration. 708 */ 709 typedef struct _pf5020_power_down_group_config 710 { 711 pf5020_power_down_group_t resetBMCUGroup; /*!< The power down group of RESETBMCU pin. */ 712 pf5020_power_down_group_t pGoodGroup; /*!< The power down group of PGOOD pin. */ 713 pf5020_power_down_group_t sw1Group; /*!< The power down group of SW1 regulator. */ 714 pf5020_power_down_group_t sw2Group; /*!< The power down group of SW2 regulator. */ 715 pf5020_power_down_group_t swnd1Group; /*!< The power down group of SWND1 regulator. */ 716 pf5020_power_down_group_t ldo1Group; /*!< The power down group of LDO1. */ 717 } pf5020_power_down_group_config_t; 718 719 /*! 720 * @brief PF5020 runtime handle, including send function, receive function and slave address. 721 */ 722 typedef struct _pf5020_handle 723 { 724 status_t (*I2C_SendFunc)(uint8_t deviceAddress, 725 uint32_t subAddress, 726 uint8_t subAddressSize, 727 uint8_t *txBuff, 728 uint8_t txBuffSize); /*!< Pointer to I2C send function. */ 729 status_t (*I2C_ReceiveFunc)(uint8_t deviceAddress, 730 uint32_t subAddress, 731 uint8_t subAddressSize, 732 uint8_t *rxBuff, 733 uint8_t rxBuffSize); /*!< Pointer to I2C receive function. */ 734 uint8_t slaveAddress; /*!< device slave address. */ 735 } pf5020_handle_t; 736 737 /*! 738 * @brief PF5020 initialize configuration. 739 */ 740 typedef struct _pf5020_config 741 { 742 status_t (*I2C_SendFunc)(uint8_t deviceAddress, 743 uint32_t subAddress, 744 uint8_t subAddressSize, 745 uint8_t *txBuff, 746 uint8_t txBuffSize); /*!< Pointer to I2C send function. */ 747 status_t (*I2C_ReceiveFunc)(uint8_t deviceAddress, 748 uint32_t subAddress, 749 uint8_t subAddressSize, 750 uint8_t *rxBuff, 751 uint8_t rxBuffSize); /*!< Pointer to I2C receive function. */ 752 uint8_t slaveAddress; /*!< device slave address. */ 753 } pf5020_config_t; 754 755 /******************************************************************************* 756 * API 757 ******************************************************************************/ 758 759 /*! @name Basic Interfaces 760 * @{ 761 */ 762 763 /*! 764 * @brief Write to PF5020 register via I2C. 765 * 766 * @param handle The pointer to @ref pf5020_handle_t. 767 * @param regAddr The address of register to write. 768 * @param val The value to be write. 769 * 770 * @retval #kStatus_Success The transaction was started successfully. 771 * @retval #kStatus_LPI2C_Busy Either another master is currently utilizing the bus, or a non-blocking 772 * transaction is already in progress. 773 */ 774 status_t PF5020_WriteReg(pf5020_handle_t *handle, uint8_t regAddr, uint8_t val); 775 776 /*! 777 * @brief Read value from PF5020 register via I2C. 778 * 779 * @param handle The pointer to @ref pf5020_handle_t. 780 * @param regAddr The address of register to write. 781 * @param val Pointer store return value. 782 * 783 * @retval #kStatus_Success The transaction was started successfully. 784 * @retval #kStatus_LPI2C_Busy Either another master is currently utilizing the bus, or a non-blocking 785 * transaction is already in progress. 786 */ 787 status_t PF5020_ReadReg(pf5020_handle_t *handle, uint8_t regAddr, uint8_t *val); 788 789 /*! 790 * @brief Read and modify the register value 791 * 792 * @param handle The pointer to @ref pf5020_handle_t structure. 793 * @param regAddr The address of register. 794 * @param mask The mask of register bit to be modified. 795 * @param val The value to be set. 796 * 797 * @retval #kStatus_Success The transaction was started successfully. 798 * @retval #kStatus_LPI2C_Busy Either another master is currently utilizing the bus, or a non-blocking 799 * transaction is already in progress. 800 */ 801 status_t PF5020_ModifyReg(pf5020_handle_t *handle, uint8_t regAddr, uint8_t mask, uint8_t val); 802 803 /*! 804 * @brief Dump the value of continuous registers. 805 * 806 * @param handle The pointer to @ref pf5020_handle_t structure. 807 * @param regAddr The address of start register. 808 * @param buffer The buffer to store the dumped registers' value. 809 * @param length The length of the continuous registers to be dumped. 810 * 811 * @retval #kStatus_Success The transaction was started successfully. 812 * @retval #kStatus_LPI2C_Busy Either another master is currently utilizing the bus, or a non-blocking 813 * transaction is already in progress. 814 */ 815 status_t PF5020_DumpReg(pf5020_handle_t *handle, uint8_t regAddr, uint8_t *buffer, uint8_t length); 816 817 /*! 818 * @brief Get default initialize configuration. 819 * 820 * @code 821 * config->I2C_SendFunc = NULL; 822 * config->I2C_ReceiveFunc = NULL; 823 * config->slaveAddress = 0x08U; 824 * @endcode 825 * @param config The pointer to @ref pf5020_config_t structure. 826 */ 827 void PF5020_GetDefaultConfig(pf5020_config_t *config); 828 829 /*! 830 * @brief Initialize runtime handle. 831 * 832 * @param handle The pointer to @ref pf5020_handle_t structure. 833 * @param config The pointer to @ref pf5020_config_t structure. 834 */ 835 void PF5020_CreateHandle(pf5020_handle_t *handle, const pf5020_config_t *config); 836 837 /* @} */ 838 839 /*! @name Power Up/Down Sequence Control API 840 *@{ 841 */ 842 843 /*! 844 * @brief Set power up sequencer time base. 845 * 846 * @param handle The pointer to @ref pf5020_handle_t structure. 847 * @param timeBase The time base value to set, please refer @ref pf5020_sequencer_time_base_t for details. 848 * 849 * @retval #kStatus_Success The transaction was started successfully. 850 * @retval #kStatus_LPI2C_Busy Either another master is currently utilizing the bus, or a non-blocking 851 * transaction is already in progress. 852 */ 853 status_t PF5020_SetSequencerTimeBase(pf5020_handle_t *handle, pf5020_sequencer_time_base_t timeBase); 854 855 /*! 856 * @brief Set power up sequence, when transitioning from standby state to run state, the power up sequencer is activated 857 * only if any of the regulators is re-enabled during this transition. 858 * 859 * @param handle The pointer to @ref pf5020_handle_t structure. 860 * @param powerUpSeq The pointer to @ref pf5020_power_up_sequence_t structure. 861 * @retval #kStatus_Success The transaction was started successfully. 862 * @retval #kStatus_LPI2C_Busy Either another master is currently utilizing the bus, or a non-blocking 863 * transaction is already in progress. 864 */ 865 status_t PF5020_SetPowerUpSequence(pf5020_handle_t *handle, pf5020_power_up_sequence_t *powerUpSeq); 866 867 /*! 868 * @brief Turn off PF5020 PMIC. 869 * 870 * @param handle The pointer to @ref pf5020_handle_t structure. 871 * @retval #kStatus_Success The transaction was started successfully. 872 * @retval #kStatus_LPI2C_Busy Either another master is currently utilizing the bus, or a non-blocking 873 * transaction is already in progress. 874 */ 875 status_t PF5020_TurnOffPMIC(pf5020_handle_t *handle); 876 877 /*! 878 * @brief Set power down mode, sequential mode or group mode. 879 * 880 * @param handle The pointer to @ref pf5020_handle_t structure. 881 * @param powerDownMode The power down mode to set, please refer to @ref pf5020_power_down_mode_t. 882 * @retval #kStatus_Success The transaction was started successfully. 883 * @retval #kStatus_LPI2C_Busy Either another master is currently utilizing the bus, or a non-blocking 884 * transaction is already in progress. 885 */ 886 status_t PF5020_SetPowerDownMode(pf5020_handle_t *handle, pf5020_power_down_mode_t powerDownMode); 887 888 /*! 889 * @brief Set power down groups that each internal module placed to. 890 * 891 * @param handle The pointer to @ref pf5020_handle_t structure. 892 * @param groupConfig Pointer to the @ref pf5020_power_down_group_config_t structure. 893 * @retval #kStatus_Success The transaction was started successfully. 894 * @retval #kStatus_LPI2C_Busy Either another master is currently utilizing the bus, or a non-blocking 895 * transaction is already in progress. 896 */ 897 status_t PF5020_SetPowerDownGroups(pf5020_handle_t *handle, const pf5020_power_down_group_config_t *groupConfig); 898 899 /*! 900 * @brief Set selected power down group's delay. 901 * 902 * @param handle The pointer to @ref pf5020_handle_t structure. 903 * @param group The selected power down group, please refer to @ref pf5020_power_down_group_t for details. 904 * @param delay The delay value to be set, please refer to @ref pf5020_power_down_delay_t for details. 905 * @retval #kStatus_Success The transaction was started successfully. 906 * @retval #kStatus_LPI2C_Busy Either another master is currently utilizing the bus, or a non-blocking 907 * transaction is already in progress. 908 */ 909 status_t PF5020_SetPowerDownGroupDelay(pf5020_handle_t *handle, 910 pf5020_power_down_group_t group, 911 pf5020_power_down_delay_t delay); 912 913 /*! 914 * @brief Set delay to disable the regulators after RESETBMCU is asserted. 915 * 916 * @param handle The pointer to @ref pf5020_handle_t structure. 917 * @param delay The delay value, please refer to @ref pf5020_resetBMCU_delay_t. 918 * @retval #kStatus_Success The transaction was started successfully. 919 * @retval #kStatus_LPI2C_Busy Either another master is currently utilizing the bus, or a non-blocking 920 * transaction is already in progress. 921 */ 922 status_t PF5020_SetResetBMcuPinDelay(pf5020_handle_t *handle, pf5020_resetBMCU_delay_t delay); 923 924 /* @} */ 925 926 /*! @name Clock Management 927 *@{ 928 */ 929 930 /*! 931 * @brief Configure internal high speed clock. 932 * 933 * @param handle The pointer to @ref pf5020_handle_t structure. 934 * @param config The pointer to @ref pf5020_high_speed_clk_config_t structure. 935 * @retval #kStatus_Success The transaction was started successfully. 936 * @retval #kStatus_LPI2C_Busy Either another master is currently utilizing the bus, or a non-blocking 937 * transaction is already in progress. 938 */ 939 status_t PF5020_CLK_ConfigHighSpeedClock(pf5020_handle_t *handle, const pf5020_high_speed_clk_config_t *config); 940 941 /*! 942 * @brief Enable/disable clock sync out. 943 * 944 * @param handle The pointer to @ref pf5020_handle_t structure. 945 * @param enable Used to enable/disable sync output. 946 * @retval #kStatus_Success The transaction was started successfully. 947 * @retval #kStatus_LPI2C_Busy Either another master is currently utilizing the bus, or a non-blocking 948 * transaction is already in progress. 949 */ 950 status_t PF5020_CLK_EnableSyncOut(pf5020_handle_t *handle, bool enable); 951 952 /* @} */ 953 954 /*! @name Converters Management 955 * @{ 956 */ 957 958 /*! 959 * @brief Set VSNS LDO output voltage. 960 * 961 * @param handle The pointer to @ref pf5020_handle_t structure. 962 * @param voltage The output voltage of VSNVS, please refer to @ref pf5020_vsnvs_ldo_output_voltage_t. 963 * @retval #kStatus_Success The transaction was started successfully. 964 * @retval #kStatus_LPI2C_Busy Either another master is currently utilizing the bus, or a non-blocking 965 * transaction is already in progress. 966 */ 967 status_t PF5020_SetVsnvsLdoOutputVoltage(pf5020_handle_t *handle, pf5020_vsnvs_ldo_output_voltage_t voltage); 968 969 /* SW1 Buck Regulator Control APIs. */ 970 /*! 971 * @brief Set SW1 Buck regulator global configuration. 972 * 973 * @param handle The pointer to @ref pf5020_handle_t structure. 974 * @param config The pointer to @ref pf5020_sw1_regulator_config_t structure. 975 * @retval #kStatus_Success The transaction was started successfully. 976 * @retval #kStatus_LPI2C_Busy Either another master is currently utilizing the bus, or a non-blocking 977 * transaction is already in progress. 978 */ 979 status_t PF5020_SW1_SetGlobalConfig(pf5020_handle_t *handle, const pf5020_sw1_regulator_config_t *config); 980 981 /*! 982 * @brief Set DVS Ramp for SW1 buck regulator. 983 * 984 * @param handle The pointer to @ref pf5020_handle_t structure. 985 * @param dvsRamp The DVS ramp value to set, please refer to @ref pf5020_type1_buck_regulator_dvs_ramp_t for details. 986 * @retval #kStatus_Success The transaction was started successfully. 987 * @retval #kStatus_LPI2C_Busy Either another master is currently utilizing the bus, or a non-blocking 988 * transaction is already in progress. 989 */ 990 status_t PF5020_SW1_SetDvsRamp(pf5020_handle_t *handle, pf5020_type1_buck_regulator_dvs_ramp_t dvsRamp); 991 992 /*! 993 * @brief Set SW1 regulator's output voltage and operate mode in run state. 994 * 995 * @param handle The pointer to @ref pf5020_handle_t structure. 996 * @param runOutputVolt The output voltage of SW1 in run state. 997 * @param runOperateMode The operate mode of SW1 in run state. 998 * @retval #kStatus_Success The transaction was started successfully. 999 * @retval #kStatus_LPI2C_Busy Either another master is currently utilizing the bus, or a non-blocking 1000 * transaction is already in progress. 1001 */ 1002 status_t PF5020_SW1_SetRunStateOption(pf5020_handle_t *handle, 1003 uint8_t runOutputVolt, 1004 pf5020_buck_regulator_operate_mode_t runOperateMode); 1005 1006 /*! 1007 * @brief Set SW1 regulator's output voltage and operate mode in standby state. 1008 * 1009 * @param handle The pointer to @ref pf5020_handle_t structure. 1010 * @param standbyOutputVolt The output voltage of SW1 in standby state. 1011 * @param standbyOperateMode The operate mode of SW1 in standby state. 1012 * @retval #kStatus_Success The transaction was started successfully. 1013 * @retval #kStatus_LPI2C_Busy Either another master is currently utilizing the bus, or a non-blocking 1014 * transaction is already in progress. 1015 */ 1016 status_t PF5020_SW1_SetStandbyStateOption(pf5020_handle_t *handle, 1017 uint8_t standbyOutputVolt, 1018 pf5020_buck_regulator_operate_mode_t standbyOperateMode); 1019 1020 /*! 1021 * @brief Set SW1 regulator fault detection related options. 1022 * 1023 * @param handle The pointer to @ref pf5020_handle_t structure. 1024 * @param currentLimit SW1 buck regulator current limitation value, please refer to 1025 * @ref pf5020_buck_regulator_current_limit_t for details. 1026 * @param enableUVBypass Enable/disable UV bypass. 1027 * @param enableOVBypass Enable/disable OV bypass. 1028 * @param faultReEnabled Used to control whether return to sw1 regulator previous state if fault condition is cleared. 1029 * @retval #kStatus_Success The transaction was started successfully. 1030 * @retval #kStatus_LPI2C_Busy Either another master is currently utilizing the bus, or a non-blocking 1031 * transaction is already in progress. 1032 */ 1033 status_t PF5020_SW1_SetFaultDetection(pf5020_handle_t *handle, 1034 pf5020_buck_regulator_current_limit_t currentLimit, 1035 bool enableUVBypass, 1036 bool enableOVBypass, 1037 bool faultReEnabled); 1038 1039 /*! 1040 * @brief Set SW1 regulator phase shift value. 1041 * 1042 * @param handle The pointer to @ref pf5020_handle_t structure. 1043 * @param phaseShift SW1 buck regulator phase shift value, please refer to @ref pf5020_buck_regulator_phase_shift_t 1044 * for details. 1045 * @retval #kStatus_Success The transaction was started successfully. 1046 * @retval #kStatus_LPI2C_Busy Either another master is currently utilizing the bus, or a non-blocking 1047 * transaction is already in progress. 1048 */ 1049 status_t PF5020_SW1_SetPhaseShift(pf5020_handle_t *handle, pf5020_buck_regulator_phase_shift_t phaseShift); 1050 1051 /*! 1052 * @brief Enable/disable PG monitor for SW1 regulator. 1053 * 1054 * @param handle The pointer to @ref pf5020_handle_t structure. 1055 * @param enable Enable/disable PG monitor. 1056 * @retval #kStatus_Success The transaction was started successfully. 1057 * @retval #kStatus_LPI2C_Busy Either another master is currently utilizing the bus, or a non-blocking 1058 * transaction is already in progress. 1059 */ 1060 status_t PF5020_SW1_EnablePGMonitor(pf5020_handle_t *handle, bool enable); 1061 1062 /*! 1063 * @brief Enable/disable watchdog bypass for SW1 regulator. 1064 * 1065 * @param handle The pointer to @ref pf5020_handle_t structure. 1066 * @param enable Enable/disable watchdog bypass. 1067 * @retval #kStatus_Success The transaction was started successfully. 1068 * @retval #kStatus_LPI2C_Busy Either another master is currently utilizing the bus, or a non-blocking 1069 * transaction is already in progress. 1070 */ 1071 status_t PF5020_SW1_EnableWatchDogBypass(pf5020_handle_t *handle, bool enable); 1072 1073 /* SW2 Buck Regulator Control APIs. */ 1074 /*! 1075 * @brief Set SW2 Buck regulator global configuration. 1076 * 1077 * @param handle The pointer to @ref pf5020_handle_t structure. 1078 * @param config The pointer to @ref pf5020_sw2_regulator_config_t structure. 1079 * @retval #kStatus_Success The transaction was started successfully. 1080 * @retval #kStatus_LPI2C_Busy Either another master is currently utilizing the bus, or a non-blocking 1081 * transaction is already in progress. 1082 */ 1083 status_t PF5020_SW2_SetGlobalConfig(pf5020_handle_t *handle, const pf5020_sw2_regulator_config_t *config); 1084 1085 /*! 1086 * @brief Set DVS Ramp for SW2 buck regulator. 1087 * 1088 * @param handle The pointer to @ref pf5020_handle_t structure. 1089 * @param dvsRamp The DVS ramp value to set, please refer to @ref pf5020_type1_buck_regulator_dvs_ramp_t for details. 1090 * @retval #kStatus_Success The transaction was started successfully. 1091 * @retval #kStatus_LPI2C_Busy Either another master is currently utilizing the bus, or a non-blocking 1092 * transaction is already in progress. 1093 */ 1094 status_t PF5020_SW2_SetDvsRamp(pf5020_handle_t *handle, pf5020_type1_buck_regulator_dvs_ramp_t dvsRamp); 1095 1096 /*! 1097 * @brief Set SW2 regulator's output voltage and operate mode in run state. 1098 * 1099 * @param handle The pointer to @ref pf5020_handle_t structure. 1100 * @param runOutputVolt The output voltage of SW2 in run state. 1101 * @param runOperateMode The operate mode of SW2 in run state. 1102 * @retval #kStatus_Success The transaction was started successfully. 1103 * @retval #kStatus_LPI2C_Busy Either another master is currently utilizing the bus, or a non-blocking 1104 * transaction is already in progress. 1105 */ 1106 status_t PF5020_SW2_SetRunStateOption(pf5020_handle_t *handle, 1107 uint8_t runOutputVolt, 1108 pf5020_buck_regulator_operate_mode_t runOperateMode); 1109 1110 /*! 1111 * @brief Set SW2 regulator's output voltage and operate mode in standby state. 1112 * 1113 * @param handle The pointer to @ref pf5020_handle_t structure. 1114 * @param standbyOutputVolt The output voltage of SW2 in standby state. 1115 * @param standbyOperateMode The operate mode of SW2 in standby state. 1116 * @retval #kStatus_Success The transaction was started successfully. 1117 * @retval #kStatus_LPI2C_Busy Either another master is currently utilizing the bus, or a non-blocking 1118 * transaction is already in progress. 1119 */ 1120 status_t PF5020_SW2_SetStandbyStateOption(pf5020_handle_t *handle, 1121 uint8_t standbyOutputVolt, 1122 pf5020_buck_regulator_operate_mode_t standbyOperateMode); 1123 1124 /*! 1125 * @brief Set SW2 regulator phase shift value. 1126 * 1127 * @param handle The pointer to @ref pf5020_handle_t structure. 1128 * @param phaseShift SW2 buck regulator phase shift value, please refer to @ref pf5020_buck_regulator_phase_shift_t 1129 * for details. 1130 * @retval #kStatus_Success The transaction was started successfully. 1131 * @retval #kStatus_LPI2C_Busy Either another master is currently utilizing the bus, or a non-blocking 1132 * transaction is already in progress. 1133 */ 1134 status_t PF5020_SW2_SetPhaseShift(pf5020_handle_t *handle, pf5020_buck_regulator_phase_shift_t phaseShift); 1135 1136 /*! 1137 * @brief Enable/disable SW2 VTT operateion. 1138 * 1139 * @param handle The pointer to @ref pf5020_handle_t structure. 1140 * @param enable Used to enable/disable VTT operation. 1141 * @retval #kStatus_Success The transaction was started successfully. 1142 * @retval #kStatus_LPI2C_Busy Either another master is currently utilizing the bus, or a non-blocking 1143 * transaction is already in progress. 1144 */ 1145 status_t PF5020_SW2_EnableVTTOperation(pf5020_handle_t *handle, bool enable); 1146 1147 /*! 1148 * @brief Set SW2 regulator fault detection related options. 1149 * 1150 * @param handle The pointer to @ref pf5020_handle_t structure. 1151 * @param currentLimit SW2 buck regulator current limitation value, please refer to 1152 * @ref pf5020_buck_regulator_current_limit_t for details. 1153 * @param enableUVBypass Enable/disable UV bypass. 1154 * @param enableOVBypass Enable/disable OV bypass. 1155 * @param faultReEnabled Used to control whether return to sw1 regulator previous state if fault condition is cleared. 1156 * @retval #kStatus_Success The transaction was started successfully. 1157 * @retval #kStatus_LPI2C_Busy Either another master is currently utilizing the bus, or a non-blocking 1158 * transaction is already in progress. 1159 */ 1160 status_t PF5020_SW2_SetFaultDetection(pf5020_handle_t *handle, 1161 pf5020_buck_regulator_current_limit_t currentLimit, 1162 bool enableUVBypass, 1163 bool enableOVBypass, 1164 bool faultReEnabled); 1165 1166 /*! 1167 * @brief Enable/disable PG monitor for SW2 regulator. 1168 * 1169 * @param handle The pointer to @ref pf5020_handle_t structure. 1170 * @param enable Enable/disable PG monitor. 1171 * @retval #kStatus_Success The transaction was started successfully. 1172 * @retval #kStatus_LPI2C_Busy Either another master is currently utilizing the bus, or a non-blocking 1173 * transaction is already in progress. 1174 */ 1175 status_t PF5020_SW2_EnablePGMonitor(pf5020_handle_t *handle, bool enable); 1176 1177 /*! 1178 * @brief Enable/disable watchdog bypass for SW2 regulator. 1179 * 1180 * @param handle The pointer to @ref pf5020_handle_t structure. 1181 * @param enable Enable/disable watchdog bypass. 1182 * @retval #kStatus_Success The transaction was started successfully. 1183 * @retval #kStatus_LPI2C_Busy Either another master is currently utilizing the bus, or a non-blocking 1184 * transaction is already in progress. 1185 */ 1186 status_t PF5020_SW2_EnableWatchDogBypass(pf5020_handle_t *handle, bool enable); 1187 1188 /* SWND1 Buck Regulator Control APIs. */ 1189 /*! 1190 * @brief Set SWND1 Buck regulator global configuration. 1191 * 1192 * @param handle The pointer to @ref pf5020_handle_t structure. 1193 * @param config The pointer to @ref pf5020_swnd1_regulator_config_t structure. 1194 * @retval #kStatus_Success The transaction was started successfully. 1195 * @retval #kStatus_LPI2C_Busy Either another master is currently utilizing the bus, or a non-blocking 1196 * transaction is already in progress. 1197 */ 1198 status_t PF5020_SWND1_SetGlobalConfig(pf5020_handle_t *handle, const pf5020_swnd1_regulator_config_t *config); 1199 1200 /*! 1201 * @brief Set run/standby output voltage for SWND1 regulator. 1202 * 1203 * @param handle The pointer to @ref pf5020_handle_t structure. 1204 * @param outputVolt The output voltage of SWND1 regulator in run/standby state, 1205 * please refer to @ref pf5020_swnd1_output_voltage_t for details. 1206 * @retval #kStatus_Success The transaction was started successfully. 1207 * @retval #kStatus_LPI2C_Busy Either another master is currently utilizing the bus, or a non-blocking 1208 * transaction is already in progress. 1209 */ 1210 status_t PF5020_SWND1_SetOutputVoltage(pf5020_handle_t *handle, pf5020_swnd1_output_voltage_t outputVolt); 1211 1212 /*! 1213 * @brief Set SWND1 regulator's operate mode in run and standby state. 1214 * 1215 * @param handle The pointer to @ref pf5020_handle_t structure. 1216 * @param runOperateMode The operate mode of SWND1 in run state, please refer to @ref 1217 * pf5020_buck_regulator_operate_mode_t. 1218 * @param standbyOperateMode The operate mode of SWND1 in standby state, please refer to @ref 1219 * pf5020_buck_regulator_operate_mode_t. 1220 * @retval #kStatus_Success The transaction was started successfully. 1221 * @retval #kStatus_LPI2C_Busy Either another master is currently utilizing the bus, or a non-blocking 1222 * transaction is already in progress. 1223 */ 1224 status_t PF5020_SWND1_SetOperateMode(pf5020_handle_t *handle, 1225 pf5020_buck_regulator_operate_mode_t runOperateMode, 1226 pf5020_buck_regulator_operate_mode_t standbyOperateMode); 1227 1228 /*! 1229 * @brief Set SWND1 regulator phase shift value. 1230 * 1231 * @param handle The pointer to @ref pf5020_handle_t structure. 1232 * @param phaseShift SWND1 buck regulator phase shift value, please refer to @ref pf5020_buck_regulator_phase_shift_t 1233 * for details. 1234 * @retval #kStatus_Success The transaction was started successfully. 1235 * @retval #kStatus_LPI2C_Busy Either another master is currently utilizing the bus, or a non-blocking 1236 * transaction is already in progress. 1237 */ 1238 status_t PF5020_SWND1_SetPhaseShift(pf5020_handle_t *handle, pf5020_buck_regulator_phase_shift_t phaseShift); 1239 1240 /*! 1241 * @brief Set SWND1 regulator fault detection related options. 1242 * 1243 * @param handle The pointer to @ref pf5020_handle_t structure. 1244 * @param currentLimit SWND1 buck regulator current limitation value, please refer to 1245 * @ref pf5020_buck_regulator_current_limit_t for details. 1246 * @param enableUVBypass Enable/disable UV bypass. 1247 * @param enableOVBypass Enable/disable OV bypass. 1248 * @param faultReEnabled Used to control whether return to sw1 regulator previous state if fault condition is cleared. 1249 * @retval #kStatus_Success The transaction was started successfully. 1250 * @retval #kStatus_LPI2C_Busy Either another master is currently utilizing the bus, or a non-blocking 1251 * transaction is already in progress. 1252 */ 1253 status_t PF5020_SWND1_SetFaultDetection(pf5020_handle_t *handle, 1254 pf5020_buck_regulator_current_limit_t currentLimit, 1255 bool enableUVBypass, 1256 bool enableOVBypass, 1257 bool faultReEnabled); 1258 1259 /*! 1260 * @brief Enable/disable PG monitor for SWND1 regulator. 1261 * 1262 * @param handle The pointer to @ref pf5020_handle_t structure. 1263 * @param enable Enable/disable PG monitor. 1264 * @retval #kStatus_Success The transaction was started successfully. 1265 * @retval #kStatus_LPI2C_Busy Either another master is currently utilizing the bus, or a non-blocking 1266 * transaction is already in progress. 1267 */ 1268 status_t PF5020_SWND1_EnablePGMonitor(pf5020_handle_t *handle, bool enable); 1269 1270 /*! 1271 * @brief Enable/disable watchdog bypass for SW1 regulator. 1272 * 1273 * @param handle The pointer to @ref pf5020_handle_t structure. 1274 * @param enable Enable/disable watchdog bypass. 1275 * @retval #kStatus_Success The transaction was started successfully. 1276 * @retval #kStatus_LPI2C_Busy Either another master is currently utilizing the bus, or a non-blocking 1277 * transaction is already in progress. 1278 */ 1279 status_t PF5020_SWND1_EnableWatchDogBypass(pf5020_handle_t *handle, bool enable); 1280 1281 /* LDO1 Control APIs. */ 1282 /*! 1283 * @brief Set LDO1 global configuration. 1284 * 1285 * @param handle The pointer to @ref pf5020_handle_t structure. 1286 * @param config The pointer to @ref pf5020_ldo1_regulator_config structure. 1287 * @retval #kStatus_Success The transaction was started successfully. 1288 * @retval #kStatus_LPI2C_Busy Either another master is currently utilizing the bus, or a non-blocking 1289 * transaction is already in progress. 1290 */ 1291 status_t PF5020_LDO1_SetGlobalConfig(pf5020_handle_t *handle, const pf5020_ldo1_regulator_config *config); 1292 1293 /*! 1294 * @brief Set LDO1 regulator's output voltage and operate mode in run state. 1295 * 1296 * @param handle The pointer to @ref pf5020_handle_t structure. 1297 * @param runEnable Enable/disable LDO1 in run state. 1298 * @param runOuputVolt The output voltage of LDO1 in run state, please refer to @ref pf5020_ldo1_output_voltage_t. 1299 * @retval #kStatus_Success The transaction was started successfully. 1300 * @retval #kStatus_LPI2C_Busy Either another master is currently utilizing the bus, or a non-blocking 1301 * transaction is already in progress. 1302 */ 1303 status_t PF5020_LDO1_SetRunStateOption(pf5020_handle_t *handle, 1304 bool runEnable, 1305 pf5020_ldo1_output_voltage_t runOuputVolt); 1306 1307 /*! 1308 * @brief Set LDO1 regulator's output voltage and operate mode in standby state. 1309 * 1310 * @param handle The pointer to @ref pf5020_handle_t structure. 1311 * @param standbyEnable Enable/disable LDO1 in standby state. 1312 * @param standbyOuputVolt The output voltage of LDO1 in standby state, please refer to @ref 1313 * pf5020_ldo1_output_voltage_t. 1314 * @retval #kStatus_Success The transaction was started successfully. 1315 * @retval #kStatus_LPI2C_Busy Either another master is currently utilizing the bus, or a non-blocking 1316 * transaction is already in progress. 1317 */ 1318 status_t PF5020_LDO1_SetStandbyStateOption(pf5020_handle_t *handle, 1319 bool standbyEnable, 1320 pf5020_ldo1_output_voltage_t standbyOuputVolt); 1321 1322 /*! 1323 * @brief Set SWND1 regulator fault detection related options. 1324 * 1325 * @param handle The pointer to @ref pf5020_handle_t structure. 1326 * @param enableILIMBypass Enable/disable ILIM bypass. 1327 * @param enableUVBypass Enable/disable UV bypass. 1328 * @param enableOVBypass Enable/disable OV bypass. 1329 * @param faultReEnabled Used to control whether return to ldos1 regulator previous state if fault condition is cleared. 1330 * @retval #kStatus_Success The transaction was started successfully. 1331 * @retval #kStatus_LPI2C_Busy Either another master is currently utilizing the bus, or a non-blocking 1332 * transaction is already in progress. 1333 */ 1334 status_t PF5020_LDO1_SetFaultDetection( 1335 pf5020_handle_t *handle, bool enableILIMBypass, bool enableUVBypass, bool enableOVBypass, bool faultReEnabled); 1336 1337 /*! 1338 * @brief Enable/disable PG monitor for LDO1 regulator. 1339 * 1340 * @param handle The pointer to @ref pf5020_handle_t structure. 1341 * @param enable Enable/disable PG monitor. 1342 * @retval #kStatus_Success The transaction was started successfully. 1343 * @retval #kStatus_LPI2C_Busy Either another master is currently utilizing the bus, or a non-blocking 1344 * transaction is already in progress. 1345 */ 1346 status_t PF5020_LDO1_EnablePGMonitor(pf5020_handle_t *handle, bool enable); 1347 1348 /*! 1349 * @brief Enable/disable watchdog bypass for LDO1 regulator. 1350 * 1351 * @param handle The pointer to @ref pf5020_handle_t structure. 1352 * @param enable Enable/disable watchdog bypass. 1353 * @retval #kStatus_Success The transaction was started successfully. 1354 * @retval #kStatus_LPI2C_Busy Either another master is currently utilizing the bus, or a non-blocking 1355 * transaction is already in progress. 1356 */ 1357 status_t PF5020_LDO1_EnableWatchDogBypass(pf5020_handle_t *handle, bool enable); 1358 1359 /* @} */ 1360 1361 /*! @name Fault Detection 1362 * @{ 1363 */ 1364 1365 /*! 1366 * @brief Set voltage monitor debounce time. 1367 * 1368 * @param handle The pointer to @ref pf5020_handle_t structure. 1369 * @param uvDebounceTime UV monitor debounce time, please refer to @ref pf5020_uv_debounce_time_t. 1370 * @param ovDebounceTime OV monitor debounce time, please refer to @ref pf5020_ov_debounce_time_t. 1371 * @retval #kStatus_Success The transaction was started successfully. 1372 * @retval #kStatus_LPI2C_Busy Either another master is currently utilizing the bus, or a non-blocking 1373 * transaction is already in progress. 1374 */ 1375 status_t PF5020_SetVoltageMonitorDebounceTime(pf5020_handle_t *handle, 1376 pf5020_uv_debounce_time_t uvDebounceTime, 1377 pf5020_ov_debounce_time_t ovDebounceTime); 1378 1379 /*! 1380 * @brief Enable/disable selected regulator's voltage monitor. 1381 * 1382 * @param handle The pointer to @ref pf5020_handle_t structure. 1383 * @param name The regulator to be set. 1384 * @param enable Enable/disable voltage monitor. 1385 * @retval #kStatus_Success The transaction was started successfully. 1386 * @retval #kStatus_LPI2C_Busy Either another master is currently utilizing the bus, or a non-blocking 1387 * transaction is already in progress. 1388 */ 1389 status_t PF5020_EnableVoltageMonitor(pf5020_handle_t *handle, pf5020_regulator_name_t name, bool enable); 1390 1391 /*! 1392 * @brief Set fault counter maximum value. 1393 * 1394 * @param handle Pointer to the @ref pf5020_handle_t structure. 1395 * @param maxValue Ranges from 0 to 15. 1396 * @retval #kStatus_Success The transaction was started successfully. 1397 * @retval #kStatus_LPI2C_Busy Either another master is currently utilizing the bus, or a non-blocking 1398 * transaction is already in progress. 1399 */ 1400 status_t PF5020_SetFaultCounterMaxValue(pf5020_handle_t *handle, uint8_t maxValue); 1401 1402 /*! 1403 * @brief Get fault counter current value. 1404 * 1405 * @param handle The pointer to @ref pf5020_handle_t structure. 1406 * @retval #kStatus_Success The transaction was started successfully. 1407 * @retval #kStatus_LPI2C_Busy Either another master is currently utilizing the bus, or a non-blocking 1408 * transaction is already in progress. 1409 */ 1410 uint8_t PF5020_GetFaultCounterCurrentValue(pf5020_handle_t *handle); 1411 1412 /*! 1413 * @brief Set the expire value of the fault timer, when a regulator experiences a fault event, a fault timer will start. 1414 * 1415 * @param handle Pointer to the @ref pf5020_handle_t structure. 1416 * @param expireValue The expire value of fault timer, ranges from 0 to 11, the actual expire time = 2 ^ expireValue. 1417 * 1418 * @retval #kStatus_Success The transaction was started successfully. 1419 * @retval #kStatus_LPI2C_Busy Either another master is currently utilizing the bus, or a non-blocking 1420 * transaction is already in progress. 1421 */ 1422 status_t PF5020_SetFaultTimerExpireValue(pf5020_handle_t *handle, uint8_t expireValue); 1423 1424 /* @} */ 1425 1426 /*! @name Watchdog Management 1427 * @{ 1428 */ 1429 1430 /*! 1431 * @brief Set reset behaviour asserted by WDI. 1432 * 1433 * @param handle The pointer to @ref pf5020_handle_t structure. 1434 * @param wdiMode Used to control the WDI asserted performs a hard WD reset or soft WD reset. 1435 * @retval #kStatus_Success The transaction was started successfully. 1436 * @retval #kStatus_LPI2C_Busy Either another master is currently utilizing the bus, or a non-blocking 1437 * transaction is already in progress. 1438 */ 1439 status_t PF5020_WDOG_SetWDIMode(pf5020_handle_t *handle, pf5020_wdi_mode_t wdiMode); 1440 1441 /*! 1442 * @brief Enable/disable WDI watchdog event in standby state. 1443 * 1444 * @param handle The pointer to @ref pf5020_handle_t structure. 1445 * @param enable Used to control whether generate a watchdog event in standby mode if the WDI is asserted. 1446 * @retval #kStatus_Success The transaction was started successfully. 1447 * @retval #kStatus_LPI2C_Busy Either another master is currently utilizing the bus, or a non-blocking 1448 * transaction is already in progress. 1449 */ 1450 status_t PF5020_WDOG_EnableWDIStanby(pf5020_handle_t *handle, bool enable); 1451 1452 /*! 1453 * @brief Configure internal watchdog timer. 1454 * 1455 * @param handle The pointer to @ref pf5020_handle_t structure. 1456 * @param config Pointer to @ref pf5020_wdog_internal_timer_config_t structure. 1457 * @retval #kStatus_Success The transaction was started successfully. 1458 * @retval #kStatus_LPI2C_Busy Either another master is currently utilizing the bus, or a non-blocking 1459 * transaction is already in progress. 1460 */ 1461 status_t PF5020_WDOG_ConfigInternalTimer(pf5020_handle_t *handle, const pf5020_wdog_internal_timer_config_t *config); 1462 1463 /*! 1464 * @brief Get cyclic counter current value. 1465 * 1466 * @param handle The pointer to @ref pf5020_handle_t structure. 1467 * @return Current cyclic counter value. 1468 */ 1469 uint8_t PF5020_WDOG_GetCyclicCounterValue(pf5020_handle_t *handle); 1470 1471 /*! 1472 * @brief Refresh internal watchdog timer. 1473 * 1474 * @param handle The pointer to @ref pf5020_handle_t structure. 1475 * @retval #kStatus_Success The transaction was started successfully. 1476 * @retval #kStatus_LPI2C_Busy Either another master is currently utilizing the bus, or a non-blocking 1477 * transaction is already in progress. 1478 */ 1479 status_t PF5020_WDOG_RefreshInternalTimer(pf5020_handle_t *handle); 1480 1481 /*! 1482 * @brief Set watchdog event counter maximum value. 1483 * 1484 * @param handle The pointer to @ref pf5020_handle_t structure. 1485 * @param maxValue The maximum value of watchdog event counter. 1486 * @retval #kStatus_Success The transaction was started successfully. 1487 * @retval #kStatus_LPI2C_Busy Either another master is currently utilizing the bus, or a non-blocking 1488 * transaction is already in progress. 1489 */ 1490 status_t PF5020_WDOG_SetWDEventCounterMaxValue(pf5020_handle_t *handle, uint8_t maxValue); 1491 1492 /*! 1493 * @brief Get watchdog event counter current value. 1494 * 1495 * @param handle The pointer to @ref pf5020_handle_t structure. 1496 * @return Watch dog event counter current value. 1497 */ 1498 uint8_t PF5020_WDOG_GetWDEventCounterCurrentValue(pf5020_handle_t *handle); 1499 1500 /* @} */ 1501 1502 /*! @name Temperature Sensor 1503 * @{ 1504 */ 1505 1506 /*! 1507 * @brief Configure internal thermal monitor. 1508 * 1509 * @param handle The pointer to @ref pf5020_handle_t structure. 1510 * @param enable Enable/disable temperature sensor circuit. 1511 * @param mode Used to set temperature sensor operate mode, please refer to @ref pf5020_temp_sensor_operate_mode_t. 1512 * @retval #kStatus_Success The transaction was started successfully. 1513 * @retval #kStatus_LPI2C_Busy Either another master is currently utilizing the bus, or a non-blocking 1514 * transaction is already in progress. 1515 */ 1516 status_t PF5020_TMP_SetThermalMonitorConfig(pf5020_handle_t *handle, 1517 bool enable, 1518 pf5020_temp_sensor_operate_mode_t mode); 1519 1520 /* @} */ 1521 1522 /*! @name Analog Multiplexer Control APIs 1523 * @{ 1524 */ 1525 1526 /*! 1527 * @brief Configure analog multiplexer. 1528 * 1529 * @param handle The pointer to @ref pf5020_handle_t structure. 1530 * @param enable Enable/disable analog multiplexer. 1531 * @param amuxSel Used to select amux output, please refer to @ref pf5020_amux_selection_t 1532 * @retval #kStatus_Success The transaction was started successfully. 1533 * @retval #kStatus_LPI2C_Busy Either another master is currently utilizing the bus, or a non-blocking 1534 * transaction is already in progress. 1535 */ 1536 status_t PF5020_AMUX_SetAnalogMuxConfig(pf5020_handle_t *handle, bool enable, pf5020_amux_selection_t amuxSel); 1537 1538 /* @} */ 1539 1540 /*! @name Interrupt Control 1541 * @{ 1542 */ 1543 1544 /*! 1545 * @brief Enable interrupts. 1546 * 1547 * @param handle The pointer to @ref pf5020_handle_t structure. 1548 * @param interruptMask The mask of interrupts to clear, should be the OR'ed value of @ref pf5020_interrupt_t. 1549 * @retval #kStatus_Success The transaction was started successfully. 1550 * @retval #kStatus_LPI2C_Busy Either another master is currently utilizing the bus, or a non-blocking 1551 * transaction is already in progress. 1552 */ 1553 status_t PF5020_EnableInterrupts(pf5020_handle_t *handle, uint64_t interruptMask); 1554 1555 /*! 1556 * @brief Disable Interrupts. 1557 * 1558 * @param handle The pointer to @ref pf5020_handle_t structure. 1559 * @param interruptMask The mask of interrupts to clear, should be the OR'ed value of @ref pf5020_interrupt_t. 1560 * @retval #kStatus_Success The transaction was started successfully. 1561 * @retval #kStatus_LPI2C_Busy Either another master is currently utilizing the bus, or a non-blocking 1562 * transaction is already in progress. 1563 */ 1564 status_t PF5020_DisableInterrupts(pf5020_handle_t *handle, uint64_t interruptMask); 1565 1566 /*! 1567 * @brief Get latched interrupts. 1568 * 1569 * @param handle The pointer to @ref pf5020_handle_t structure. 1570 * @param interrptLatched Pointer to store the latched interrupt value. 1571 * @retval #kStatus_Success The transaction was started successfully. 1572 * @retval #kStatus_LPI2C_Busy Either another master is currently utilizing the bus, or a non-blocking 1573 * transaction is already in progress. 1574 */ 1575 status_t PF5020_GetInterruptLatchStatus(pf5020_handle_t *handle, uint64_t *interrptLatched); 1576 1577 /*! 1578 * @brief Clear latched interrupts. 1579 * 1580 * @param handle The pointer to @ref pf5020_handle_t structure. 1581 * @param interruptMask The mask of interrupts to clear, should be the OR'ed value of @ref pf5020_interrupt_t. 1582 * @retval #kStatus_Success The transaction was started successfully. 1583 * @retval #kStatus_LPI2C_Busy Either another master is currently utilizing the bus, or a non-blocking 1584 * transaction is already in progress. 1585 */ 1586 status_t PF5020_ClearInterruptStatus(pf5020_handle_t *handle, uint64_t interruptMask); 1587 1588 /* @} */ 1589 1590 #endif /* _FSL_PF5020_H_ */ 1591
