1 /*
2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
3 * Copyright 2016-2022 NXP
4 * All rights reserved.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9 #ifndef FSL_SAI_H_
10 #define FSL_SAI_H_
11
12 #include "fsl_common.h"
13
14 /*!
15 * @addtogroup sai_driver SAI Driver
16 * @{
17 */
18
19 /*******************************************************************************
20 * Definitions
21 ******************************************************************************/
22
23 /*! @brief Used to control whether SAI_RxSetFifoConfig()/SAI_TxSetFifoConfig()
24 * allows a NULL FIFO watermark.
25 *
26 * If this macro is set to 0 then SAI_RxSetFifoConfig()/SAI_TxSetFifoConfig()
27 * will set the watermark to half of the FIFO's depth if passed a NULL
28 * watermark.
29 */
30 #ifndef MCUX_SDK_SAI_ALLOW_NULL_FIFO_WATERMARK
31 #define MCUX_SDK_SAI_ALLOW_NULL_FIFO_WATERMARK 0
32 #endif /* MCUX_SDK_SAI_ALLOW_NULL_FIFO_WATERMARK */
33
34 /*! @brief Disable implicit channel data configuration within SAI_TxSetConfig()/SAI_RxSetConfig().
35 *
36 * Use this macro to control whether SAI_RxSetConfig()/SAI_TxSetConfig() will
37 * attempt to implicitly configure the channel data. By channel data we mean
38 * the startChannel, channelMask, endChannel, and channelNums fields from the
39 * sai_transciever_t structure. By default, SAI_TxSetConfig()/SAI_RxSetConfig()
40 * will attempt to compute these fields, which may not be desired in cases where
41 * the user wants to set them before the call to said functions.
42 */
43 #ifndef MCUX_SDK_SAI_DISABLE_IMPLICIT_CHAN_CONFIG
44 #define MCUX_SDK_SAI_DISABLE_IMPLICIT_CHAN_CONFIG 0
45 #endif /* MCUX_SDK_SAI_DISABLE_IMPLICIT_CHAN_CONFIG */
46
47 /*! @name Driver version */
48 /*! @{ */
49 #define FSL_SAI_DRIVER_VERSION (MAKE_VERSION(2, 4, 2)) /*!< Version 2.4.2 */
50 /*! @} */
51
52 /*! @brief _sai_status_t, SAI return status.*/
53 enum
54 {
55 kStatus_SAI_TxBusy = MAKE_STATUS(kStatusGroup_SAI, 0), /*!< SAI Tx is busy. */
56 kStatus_SAI_RxBusy = MAKE_STATUS(kStatusGroup_SAI, 1), /*!< SAI Rx is busy. */
57 kStatus_SAI_TxError = MAKE_STATUS(kStatusGroup_SAI, 2), /*!< SAI Tx FIFO error. */
58 kStatus_SAI_RxError = MAKE_STATUS(kStatusGroup_SAI, 3), /*!< SAI Rx FIFO error. */
59 kStatus_SAI_QueueFull = MAKE_STATUS(kStatusGroup_SAI, 4), /*!< SAI transfer queue is full. */
60 kStatus_SAI_TxIdle = MAKE_STATUS(kStatusGroup_SAI, 5), /*!< SAI Tx is idle */
61 kStatus_SAI_RxIdle = MAKE_STATUS(kStatusGroup_SAI, 6) /*!< SAI Rx is idle */
62 };
63
64 /*! @brief _sai_channel_mask,.sai channel mask value, actual channel numbers is depend soc specific */
65 enum
66 {
67 kSAI_Channel0Mask = 1 << 0U, /*!< channel 0 mask value */
68 kSAI_Channel1Mask = 1 << 1U, /*!< channel 1 mask value */
69 kSAI_Channel2Mask = 1 << 2U, /*!< channel 2 mask value */
70 kSAI_Channel3Mask = 1 << 3U, /*!< channel 3 mask value */
71 kSAI_Channel4Mask = 1 << 4U, /*!< channel 4 mask value */
72 kSAI_Channel5Mask = 1 << 5U, /*!< channel 5 mask value */
73 kSAI_Channel6Mask = 1 << 6U, /*!< channel 6 mask value */
74 kSAI_Channel7Mask = 1 << 7U, /*!< channel 7 mask value */
75 };
76
77 /*! @brief Define the SAI bus type */
78 typedef enum _sai_protocol
79 {
80 kSAI_BusLeftJustified = 0x0U, /*!< Uses left justified format.*/
81 kSAI_BusRightJustified, /*!< Uses right justified format. */
82 kSAI_BusI2S, /*!< Uses I2S format. */
83 kSAI_BusPCMA, /*!< Uses I2S PCM A format.*/
84 kSAI_BusPCMB /*!< Uses I2S PCM B format. */
85 } sai_protocol_t;
86
87 /*! @brief Master or slave mode */
88 typedef enum _sai_master_slave
89 {
90 kSAI_Master = 0x0U, /*!< Master mode include bclk and frame sync */
91 kSAI_Slave = 0x1U, /*!< Slave mode include bclk and frame sync */
92 kSAI_Bclk_Master_FrameSync_Slave = 0x2U, /*!< bclk in master mode, frame sync in slave mode */
93 kSAI_Bclk_Slave_FrameSync_Master = 0x3U, /*!< bclk in slave mode, frame sync in master mode */
94 } sai_master_slave_t;
95
96 /*! @brief Mono or stereo audio format */
97 typedef enum _sai_mono_stereo
98 {
99 kSAI_Stereo = 0x0U, /*!< Stereo sound. */
100 kSAI_MonoRight, /*!< Only Right channel have sound. */
101 kSAI_MonoLeft /*!< Only left channel have sound. */
102 } sai_mono_stereo_t;
103
104 /*! @brief SAI data order, MSB or LSB */
105 typedef enum _sai_data_order
106 {
107 kSAI_DataLSB = 0x0U, /*!< LSB bit transferred first */
108 kSAI_DataMSB /*!< MSB bit transferred first */
109 } sai_data_order_t;
110
111 /*! @brief SAI clock polarity, active high or low */
112 typedef enum _sai_clock_polarity
113 {
114 kSAI_PolarityActiveHigh = 0x0U, /*!< Drive outputs on rising edge */
115 kSAI_PolarityActiveLow = 0x1U, /*!< Drive outputs on falling edge */
116 kSAI_SampleOnFallingEdge = 0x0U, /*!< Sample inputs on falling edge */
117 kSAI_SampleOnRisingEdge = 0x1U, /*!< Sample inputs on rising edge */
118 } sai_clock_polarity_t;
119
120 /*! @brief Synchronous or asynchronous mode */
121 typedef enum _sai_sync_mode
122 {
123 kSAI_ModeAsync = 0x0U, /*!< Asynchronous mode */
124 kSAI_ModeSync, /*!< Synchronous mode (with receiver or transmit) */
125 #if defined(FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI) && (FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI)
126 kSAI_ModeSyncWithOtherTx, /*!< Synchronous with another SAI transmit */
127 kSAI_ModeSyncWithOtherRx /*!< Synchronous with another SAI receiver */
128 #endif /* FSL_FEATURE_SAI_HAS_SYNC_WITH_ANOTHER_SAI */
129 } sai_sync_mode_t;
130
131 #if !(defined(FSL_FEATURE_SAI_HAS_NO_MCR_MICS) && (FSL_FEATURE_SAI_HAS_NO_MCR_MICS))
132 /*! @brief Mater clock source */
133 typedef enum _sai_mclk_source
134 {
135 kSAI_MclkSourceSysclk = 0x0U, /*!< Master clock from the system clock */
136 kSAI_MclkSourceSelect1, /*!< Master clock from source 1 */
137 kSAI_MclkSourceSelect2, /*!< Master clock from source 2 */
138 kSAI_MclkSourceSelect3 /*!< Master clock from source 3 */
139 } sai_mclk_source_t;
140 #endif
141
142 /*! @brief Bit clock source */
143 typedef enum _sai_bclk_source
144 {
145 kSAI_BclkSourceBusclk = 0x0U, /*!< Bit clock using bus clock */
146 /* General device bit source definition */
147 kSAI_BclkSourceMclkOption1 = 0x1U, /*!< Bit clock MCLK option 1 */
148 kSAI_BclkSourceMclkOption2 = 0x2U, /*!< Bit clock MCLK option2 */
149 kSAI_BclkSourceMclkOption3 = 0x3U, /*!< Bit clock MCLK option3 */
150 /* Kinetis device bit clock source definition */
151 kSAI_BclkSourceMclkDiv = 0x1U, /*!< Bit clock using master clock divider */
152 kSAI_BclkSourceOtherSai0 = 0x2U, /*!< Bit clock from other SAI device */
153 kSAI_BclkSourceOtherSai1 = 0x3U /*!< Bit clock from other SAI device */
154 } sai_bclk_source_t;
155
156 /*! @brief _sai_interrupt_enable_t, The SAI interrupt enable flag */
157 enum
158 {
159 kSAI_WordStartInterruptEnable =
160 I2S_TCSR_WSIE_MASK, /*!< Word start flag, means the first word in a frame detected */
161 kSAI_SyncErrorInterruptEnable = I2S_TCSR_SEIE_MASK, /*!< Sync error flag, means the sync error is detected */
162 kSAI_FIFOWarningInterruptEnable = I2S_TCSR_FWIE_MASK, /*!< FIFO warning flag, means the FIFO is empty */
163 kSAI_FIFOErrorInterruptEnable = I2S_TCSR_FEIE_MASK, /*!< FIFO error flag */
164 #if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO)
165 kSAI_FIFORequestInterruptEnable = I2S_TCSR_FRIE_MASK, /*!< FIFO request, means reached watermark */
166 #endif /* FSL_FEATURE_SAI_HAS_FIFO */
167 };
168
169 /*! @brief _sai_dma_enable_t, The DMA request sources */
170 enum
171 {
172 kSAI_FIFOWarningDMAEnable = I2S_TCSR_FWDE_MASK, /*!< FIFO warning caused by the DMA request */
173 #if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO)
174 kSAI_FIFORequestDMAEnable = I2S_TCSR_FRDE_MASK, /*!< FIFO request caused by the DMA request */
175 #endif /* FSL_FEATURE_SAI_HAS_FIFO */
176 };
177
178 /*! @brief _sai_flags, The SAI status flag */
179 enum
180 {
181 kSAI_WordStartFlag = I2S_TCSR_WSF_MASK, /*!< Word start flag, means the first word in a frame detected */
182 kSAI_SyncErrorFlag = I2S_TCSR_SEF_MASK, /*!< Sync error flag, means the sync error is detected */
183 kSAI_FIFOErrorFlag = I2S_TCSR_FEF_MASK, /*!< FIFO error flag */
184 #if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO)
185 kSAI_FIFORequestFlag = I2S_TCSR_FRF_MASK, /*!< FIFO request flag. */
186 #endif /* FSL_FEATURE_SAI_HAS_FIFO */
187 kSAI_FIFOWarningFlag = I2S_TCSR_FWF_MASK, /*!< FIFO warning flag */
188 };
189
190 /*! @brief The reset type */
191 typedef enum _sai_reset_type
192 {
193 kSAI_ResetTypeSoftware = I2S_TCSR_SR_MASK, /*!< Software reset, reset the logic state */
194 kSAI_ResetTypeFIFO = I2S_TCSR_FR_MASK, /*!< FIFO reset, reset the FIFO read and write pointer */
195 kSAI_ResetAll = I2S_TCSR_SR_MASK | I2S_TCSR_FR_MASK /*!< All reset. */
196 } sai_reset_type_t;
197
198 #if defined(FSL_FEATURE_SAI_HAS_FIFO_PACKING) && FSL_FEATURE_SAI_HAS_FIFO_PACKING
199 /*!
200 * @brief The SAI packing mode
201 * The mode includes 8 bit and 16 bit packing.
202 */
203 typedef enum _sai_fifo_packing
204 {
205 kSAI_FifoPackingDisabled = 0x0U, /*!< Packing disabled */
206 kSAI_FifoPacking8bit = 0x2U, /*!< 8 bit packing enabled */
207 kSAI_FifoPacking16bit = 0x3U /*!< 16bit packing enabled */
208 } sai_fifo_packing_t;
209 #endif /* FSL_FEATURE_SAI_HAS_FIFO_PACKING */
210
211 /*! @brief SAI user configuration structure */
212 typedef struct _sai_config
213 {
214 sai_protocol_t protocol; /*!< Audio bus protocol in SAI */
215 sai_sync_mode_t syncMode; /*!< SAI sync mode, control Tx/Rx clock sync */
216 #if defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR)
217 bool mclkOutputEnable; /*!< Master clock output enable, true means master clock divider enabled */
218 #if !(defined(FSL_FEATURE_SAI_HAS_NO_MCR_MICS) && (FSL_FEATURE_SAI_HAS_NO_MCR_MICS))
219 sai_mclk_source_t mclkSource; /*!< Master Clock source */
220 #endif /* FSL_FEATURE_SAI_HAS_MCR */
221 #endif
222 sai_bclk_source_t bclkSource; /*!< Bit Clock source */
223 sai_master_slave_t masterSlave; /*!< Master or slave */
224 } sai_config_t;
225
226 #ifndef SAI_XFER_QUEUE_SIZE
227 /*!@brief SAI transfer queue size, user can refine it according to use case. */
228 #define SAI_XFER_QUEUE_SIZE (4U)
229 #endif
230
231 /*! @brief Audio sample rate */
232 typedef enum _sai_sample_rate
233 {
234 kSAI_SampleRate8KHz = 8000U, /*!< Sample rate 8000 Hz */
235 kSAI_SampleRate11025Hz = 11025U, /*!< Sample rate 11025 Hz */
236 kSAI_SampleRate12KHz = 12000U, /*!< Sample rate 12000 Hz */
237 kSAI_SampleRate16KHz = 16000U, /*!< Sample rate 16000 Hz */
238 kSAI_SampleRate22050Hz = 22050U, /*!< Sample rate 22050 Hz */
239 kSAI_SampleRate24KHz = 24000U, /*!< Sample rate 24000 Hz */
240 kSAI_SampleRate32KHz = 32000U, /*!< Sample rate 32000 Hz */
241 kSAI_SampleRate44100Hz = 44100U, /*!< Sample rate 44100 Hz */
242 kSAI_SampleRate48KHz = 48000U, /*!< Sample rate 48000 Hz */
243 kSAI_SampleRate96KHz = 96000U, /*!< Sample rate 96000 Hz */
244 kSAI_SampleRate192KHz = 192000U, /*!< Sample rate 192000 Hz */
245 kSAI_SampleRate384KHz = 384000U, /*!< Sample rate 384000 Hz */
246 } sai_sample_rate_t;
247
248 /*! @brief Audio word width */
249 typedef enum _sai_word_width
250 {
251 kSAI_WordWidth8bits = 8U, /*!< Audio data width 8 bits */
252 kSAI_WordWidth16bits = 16U, /*!< Audio data width 16 bits */
253 kSAI_WordWidth24bits = 24U, /*!< Audio data width 24 bits */
254 kSAI_WordWidth32bits = 32U /*!< Audio data width 32 bits */
255 } sai_word_width_t;
256
257 #if defined(FSL_FEATURE_SAI_HAS_CHANNEL_MODE) && FSL_FEATURE_SAI_HAS_CHANNEL_MODE
258 /*! @brief sai data pin state definition */
259 typedef enum _sai_data_pin_state
260 {
261 kSAI_DataPinStateTriState =
262 0U, /*!< transmit data pins are tri-stated when slots are masked or channels are disabled */
263 kSAI_DataPinStateOutputZero = 1U, /*!< transmit data pins are never tri-stated and will output zero when slots
264 are masked or channel disabled */
265 } sai_data_pin_state_t;
266 #endif
267
268 #if defined(FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE) && FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE
269 /*! @brief sai fifo combine mode definition */
270 typedef enum _sai_fifo_combine
271 {
272 kSAI_FifoCombineDisabled = 0U, /*!< sai fifo combine mode disabled */
273 kSAI_FifoCombineModeEnabledOnRead, /*!< sai fifo combine mode enabled on FIFO reads */
274 kSAI_FifoCombineModeEnabledOnWrite, /*!< sai fifo combine mode enabled on FIFO write */
275 kSAI_FifoCombineModeEnabledOnReadWrite, /*!< sai fifo combined mode enabled on FIFO read/writes */
276 } sai_fifo_combine_t;
277 #endif
278
279 /*! @brief sai transceiver type */
280 typedef enum _sai_transceiver_type
281 {
282 kSAI_Transmitter = 0U, /*!< sai transmitter */
283 kSAI_Receiver = 1U, /*!< sai receiver */
284 } sai_transceiver_type_t;
285
286 /*! @brief sai frame sync len */
287 typedef enum _sai_frame_sync_len
288 {
289 kSAI_FrameSyncLenOneBitClk = 0U, /*!< 1 bit clock frame sync len for DSP mode */
290 kSAI_FrameSyncLenPerWordWidth = 1U, /*!< Frame sync length decided by word width */
291 } sai_frame_sync_len_t;
292
293 /*! @brief sai transfer format */
294 typedef struct _sai_transfer_format
295 {
296 uint32_t sampleRate_Hz; /*!< Sample rate of audio data */
297 uint32_t bitWidth; /*!< Data length of audio data, usually 8/16/24/32 bits */
298 sai_mono_stereo_t stereo; /*!< Mono or stereo */
299 #if defined(FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) && (FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER)
300 uint32_t masterClockHz; /*!< Master clock frequency in Hz */
301 #endif /* FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER */
302 #if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO)
303 uint8_t watermark; /*!< Watermark value */
304 #endif /* FSL_FEATURE_SAI_HAS_FIFO */
305
306 /* for the multi channel usage, user can provide channelMask Oonly, then sai driver will handle
307 * other parameter carefully, such as
308 * channelMask = kSAI_Channel0Mask | kSAI_Channel1Mask | kSAI_Channel4Mask
309 * then in SAI_RxSetFormat/SAI_TxSetFormat function, channel/endChannel/channelNums will be calculated.
310 * for the single channel usage, user can provide channel or channel mask only, such as,
311 * channel = 0 or channelMask = kSAI_Channel0Mask.
312 */
313 uint8_t channel; /*!< Transfer start channel */
314 uint8_t channelMask; /*!< enabled channel mask value, reference _sai_channel_mask */
315 uint8_t endChannel; /*!< end channel number */
316 uint8_t channelNums; /*!< Total enabled channel numbers */
317
318 sai_protocol_t protocol; /*!< Which audio protocol used */
319 bool isFrameSyncCompact; /*!< True means Frame sync length is configurable according to bitWidth, false means frame
320 sync length is 64 times of bit clock. */
321 } sai_transfer_format_t;
322
323 #if (defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR)) || \
324 (defined(FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) && (FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER))
325 /*! @brief master clock configurations */
326 typedef struct _sai_master_clock
327 {
328 #if defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR)
329 bool mclkOutputEnable; /*!< master clock output enable */
330 #if !(defined(FSL_FEATURE_SAI_HAS_NO_MCR_MICS) && (FSL_FEATURE_SAI_HAS_NO_MCR_MICS))
331 sai_mclk_source_t mclkSource; /*!< Master Clock source */
332 #endif
333 #endif
334
335 #if (defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR)) || \
336 (defined(FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) && (FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER))
337 uint32_t mclkHz; /*!< target mclk frequency */
338 uint32_t mclkSourceClkHz; /*!< mclk source frequency*/
339 #endif
340 } sai_master_clock_t;
341 #endif
342
343 /*! @brief sai fifo feature*/
344 #if (defined(FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR) && FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR) || \
345 (defined(FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE) && FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE) || \
346 (defined(FSL_FEATURE_SAI_HAS_FIFO_PACKING) && FSL_FEATURE_SAI_HAS_FIFO_PACKING) || \
347 (defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO))
348 #define FSL_SAI_HAS_FIFO_EXTEND_FEATURE 1
349 #else
350 #define FSL_SAI_HAS_FIFO_EXTEND_FEATURE 0
351 #endif
352
353 #if FSL_SAI_HAS_FIFO_EXTEND_FEATURE
354 /*! @brief sai fifo configurations */
355 typedef struct _sai_fifo
356 {
357 #if defined(FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR) && FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR
358 bool fifoContinueOneError; /*!< fifo continues when error occur */
359 #endif
360
361 #if defined(FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE) && FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE
362 sai_fifo_combine_t fifoCombine; /*!< fifo combine mode */
363 #endif
364
365 #if defined(FSL_FEATURE_SAI_HAS_FIFO_PACKING) && FSL_FEATURE_SAI_HAS_FIFO_PACKING
366 sai_fifo_packing_t fifoPacking; /*!< fifo packing mode */
367 #endif
368 #if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO)
369 uint8_t fifoWatermark; /*!< fifo watermark */
370 #endif
371 } sai_fifo_t;
372 #endif
373
374 /*! @brief sai bit clock configurations */
375 typedef struct _sai_bit_clock
376 {
377 bool bclkSrcSwap; /*!< bit clock source swap */
378 bool bclkInputDelay; /*!< bit clock actually used by the transmitter is delayed by the pad output delay,
379 this has effect of decreasing the data input setup time, but increasing the data output valid
380 time .*/
381 sai_clock_polarity_t bclkPolarity; /*!< bit clock polarity */
382 sai_bclk_source_t bclkSource; /*!< bit Clock source */
383 } sai_bit_clock_t;
384
385 /*! @brief sai frame sync configurations */
386 typedef struct _sai_frame_sync
387 {
388 uint8_t frameSyncWidth; /*!< frame sync width in number of bit clocks */
389 bool frameSyncEarly; /*!< TRUE is frame sync assert one bit before the first bit of frame
390 FALSE is frame sync assert with the first bit of the frame */
391
392 #if defined(FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE) && FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE
393 bool frameSyncGenerateOnDemand; /*!< internal frame sync is generated when FIFO waring flag is clear */
394 #endif
395
396 sai_clock_polarity_t frameSyncPolarity; /*!< frame sync polarity */
397
398 } sai_frame_sync_t;
399
400 /*! @brief sai serial data configurations */
401 typedef struct _sai_serial_data
402 {
403 #if defined(FSL_FEATURE_SAI_HAS_CHANNEL_MODE) && FSL_FEATURE_SAI_HAS_CHANNEL_MODE
404 sai_data_pin_state_t dataMode; /*!< sai data pin state when slots masked or channel disabled */
405 #endif
406
407 sai_data_order_t dataOrder; /*!< configure whether the LSB or MSB is transmitted first */
408 uint8_t dataWord0Length; /*!< configure the number of bits in the first word in each frame */
409 uint8_t dataWordNLength; /*!< configure the number of bits in the each word in each frame, except the first word */
410 uint8_t dataWordLength; /*!< used to record the data length for dma transfer */
411 uint8_t
412 dataFirstBitShifted; /*!< Configure the bit index for the first bit transmitted for each word in the frame */
413 uint8_t dataWordNum; /*!< configure the number of words in each frame */
414 uint32_t dataMaskedWord; /*!< configure whether the transmit word is masked */
415 } sai_serial_data_t;
416
417 /*! @brief sai transceiver configurations */
418 typedef struct _sai_transceiver
419 {
420 sai_serial_data_t serialData; /*!< serial data configurations */
421 sai_frame_sync_t frameSync; /*!< ws configurations */
422 sai_bit_clock_t bitClock; /*!< bit clock configurations */
423 #if FSL_SAI_HAS_FIFO_EXTEND_FEATURE
424 sai_fifo_t fifo; /*!< fifo configurations */
425 #endif
426 sai_master_slave_t masterSlave; /*!< transceiver is master or slave */
427
428 sai_sync_mode_t syncMode; /*!< transceiver sync mode */
429
430 uint8_t startChannel; /*!< Transfer start channel */
431 uint8_t channelMask; /*!< enabled channel mask value, reference _sai_channel_mask */
432 uint8_t endChannel; /*!< end channel number */
433 uint8_t channelNums; /*!< Total enabled channel numbers */
434
435 } sai_transceiver_t;
436
437 /*! @brief SAI transfer structure */
438 typedef struct _sai_transfer
439 {
440 uint8_t *data; /*!< Data start address to transfer. */
441 size_t dataSize; /*!< Transfer size. */
442 } sai_transfer_t;
443
444 typedef struct _sai_handle sai_handle_t;
445
446 /*! @brief SAI transfer callback prototype */
447 typedef void (*sai_transfer_callback_t)(I2S_Type *base, sai_handle_t *handle, status_t status, void *userData);
448
449 /*! @brief SAI handle structure */
450 struct _sai_handle
451 {
452 I2S_Type *base; /*!< base address */
453
454 uint32_t state; /*!< Transfer status */
455 sai_transfer_callback_t callback; /*!< Callback function called at transfer event*/
456 void *userData; /*!< Callback parameter passed to callback function*/
457 uint8_t bitWidth; /*!< Bit width for transfer, 8/16/24/32 bits */
458
459 /* for the multi channel usage, user can provide channelMask Oonly, then sai driver will handle
460 * other parameter carefully, such as
461 * channelMask = kSAI_Channel0Mask | kSAI_Channel1Mask | kSAI_Channel4Mask
462 * then in SAI_RxSetFormat/SAI_TxSetFormat function, channel/endChannel/channelNums will be calculated.
463 * for the single channel usage, user can provide channel or channel mask only, such as,
464 * channel = 0 or channelMask = kSAI_Channel0Mask.
465 */
466 uint8_t channel; /*!< Transfer start channel */
467 uint8_t channelMask; /*!< enabled channel mask value, refernece _sai_channel_mask */
468 uint8_t endChannel; /*!< end channel number */
469 uint8_t channelNums; /*!< Total enabled channel numbers */
470
471 sai_transfer_t saiQueue[SAI_XFER_QUEUE_SIZE]; /*!< Transfer queue storing queued transfer */
472 size_t transferSize[SAI_XFER_QUEUE_SIZE]; /*!< Data bytes need to transfer */
473 volatile uint8_t queueUser; /*!< Index for user to queue transfer */
474 volatile uint8_t queueDriver; /*!< Index for driver to get the transfer data and size */
475 #if defined(FSL_FEATURE_SAI_HAS_FIFO) && (FSL_FEATURE_SAI_HAS_FIFO)
476 uint8_t watermark; /*!< Watermark value */
477 #endif
478 };
479
480 /*******************************************************************************
481 * API
482 ******************************************************************************/
483
484 #if defined(__cplusplus)
485 extern "C" {
486 #endif /*_cplusplus*/
487
488 /*!
489 * @name Initialization and deinitialization
490 * @{
491 */
492
493 /*!
494 * @brief Initializes the SAI peripheral.
495 *
496 * This API gates the SAI clock. The SAI module can't operate unless SAI_Init is called to enable the clock.
497 *
498 * @param base SAI base pointer.
499 */
500 void SAI_Init(I2S_Type *base);
501
502 /*!
503 * @brief De-initializes the SAI peripheral.
504 *
505 * This API gates the SAI clock. The SAI module can't operate unless SAI_TxInit
506 * or SAI_RxInit is called to enable the clock.
507 *
508 * @param base SAI base pointer.
509 */
510 void SAI_Deinit(I2S_Type *base);
511
512 /*!
513 * @brief Resets the SAI Tx.
514 *
515 * This function enables the software reset and FIFO reset of SAI Tx. After reset, clear the reset bit.
516 *
517 * @param base SAI base pointer
518 */
519 void SAI_TxReset(I2S_Type *base);
520
521 /*!
522 * @brief Resets the SAI Rx.
523 *
524 * This function enables the software reset and FIFO reset of SAI Rx. After reset, clear the reset bit.
525 *
526 * @param base SAI base pointer
527 */
528 void SAI_RxReset(I2S_Type *base);
529
530 /*!
531 * @brief Enables/disables the SAI Tx.
532 *
533 * @param base SAI base pointer.
534 * @param enable True means enable SAI Tx, false means disable.
535 */
536 void SAI_TxEnable(I2S_Type *base, bool enable);
537
538 /*!
539 * @brief Enables/disables the SAI Rx.
540 *
541 * @param base SAI base pointer.
542 * @param enable True means enable SAI Rx, false means disable.
543 */
544 void SAI_RxEnable(I2S_Type *base, bool enable);
545
546 /*!
547 * @brief Set Rx bit clock direction.
548 *
549 * Select bit clock direction, master or slave.
550 *
551 * @param base SAI base pointer.
552 * @param masterSlave reference sai_master_slave_t.
553 */
SAI_TxSetBitClockDirection(I2S_Type * base,sai_master_slave_t masterSlave)554 static inline void SAI_TxSetBitClockDirection(I2S_Type *base, sai_master_slave_t masterSlave)
555 {
556 if (masterSlave == kSAI_Master)
557 {
558 base->TCR2 |= I2S_TCR2_BCD_MASK;
559 }
560 else
561 {
562 base->TCR2 &= ~I2S_TCR2_BCD_MASK;
563 }
564 }
565
566 /*!
567 * @brief Set Rx bit clock direction.
568 *
569 * Select bit clock direction, master or slave.
570 *
571 * @param base SAI base pointer.
572 * @param masterSlave reference sai_master_slave_t.
573 */
SAI_RxSetBitClockDirection(I2S_Type * base,sai_master_slave_t masterSlave)574 static inline void SAI_RxSetBitClockDirection(I2S_Type *base, sai_master_slave_t masterSlave)
575 {
576 if (masterSlave == kSAI_Master)
577 {
578 base->RCR2 |= I2S_RCR2_BCD_MASK;
579 }
580 else
581 {
582 base->RCR2 &= ~I2S_RCR2_BCD_MASK;
583 }
584 }
585
586 /*!
587 * @brief Set Rx frame sync direction.
588 *
589 * Select frame sync direction, master or slave.
590 *
591 * @param base SAI base pointer.
592 * @param masterSlave reference sai_master_slave_t.
593 */
SAI_RxSetFrameSyncDirection(I2S_Type * base,sai_master_slave_t masterSlave)594 static inline void SAI_RxSetFrameSyncDirection(I2S_Type *base, sai_master_slave_t masterSlave)
595 {
596 if (masterSlave == kSAI_Master)
597 {
598 base->RCR4 |= I2S_RCR4_FSD_MASK;
599 }
600 else
601 {
602 base->RCR4 &= ~I2S_RCR4_FSD_MASK;
603 }
604 }
605
606 /*!
607 * @brief Set Tx frame sync direction.
608 *
609 * Select frame sync direction, master or slave.
610 *
611 * @param base SAI base pointer.
612 * @param masterSlave reference sai_master_slave_t.
613 */
SAI_TxSetFrameSyncDirection(I2S_Type * base,sai_master_slave_t masterSlave)614 static inline void SAI_TxSetFrameSyncDirection(I2S_Type *base, sai_master_slave_t masterSlave)
615 {
616 if (masterSlave == kSAI_Master)
617 {
618 base->TCR4 |= I2S_TCR4_FSD_MASK;
619 }
620 else
621 {
622 base->TCR4 &= ~I2S_TCR4_FSD_MASK;
623 }
624 }
625
626 /*!
627 * @brief Transmitter bit clock rate configurations.
628 *
629 * @param base SAI base pointer.
630 * @param sourceClockHz Bit clock source frequency.
631 * @param sampleRate Audio data sample rate.
632 * @param bitWidth Audio data bitWidth.
633 * @param channelNumbers Audio channel numbers.
634 */
635 void SAI_TxSetBitClockRate(
636 I2S_Type *base, uint32_t sourceClockHz, uint32_t sampleRate, uint32_t bitWidth, uint32_t channelNumbers);
637
638 /*!
639 * @brief Receiver bit clock rate configurations.
640 *
641 * @param base SAI base pointer.
642 * @param sourceClockHz Bit clock source frequency.
643 * @param sampleRate Audio data sample rate.
644 * @param bitWidth Audio data bitWidth.
645 * @param channelNumbers Audio channel numbers.
646 */
647 void SAI_RxSetBitClockRate(
648 I2S_Type *base, uint32_t sourceClockHz, uint32_t sampleRate, uint32_t bitWidth, uint32_t channelNumbers);
649
650 /*!
651 * @brief Transmitter Bit clock configurations.
652 *
653 * @param base SAI base pointer.
654 * @param masterSlave master or slave.
655 * @param config bit clock other configurations, can be NULL in slave mode.
656 */
657 void SAI_TxSetBitclockConfig(I2S_Type *base, sai_master_slave_t masterSlave, sai_bit_clock_t *config);
658
659 /*!
660 * @brief Receiver Bit clock configurations.
661 *
662 * @param base SAI base pointer.
663 * @param masterSlave master or slave.
664 * @param config bit clock other configurations, can be NULL in slave mode.
665 */
666 void SAI_RxSetBitclockConfig(I2S_Type *base, sai_master_slave_t masterSlave, sai_bit_clock_t *config);
667
668 #if (defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR)) || \
669 (defined(FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) && (FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER))
670 /*!
671 * @brief Master clock configurations.
672 *
673 * @param base SAI base pointer.
674 * @param config master clock configurations.
675 */
676 void SAI_SetMasterClockConfig(I2S_Type *base, sai_master_clock_t *config);
677 #endif
678
679 #if FSL_SAI_HAS_FIFO_EXTEND_FEATURE
680 /*!
681 * @brief SAI transmitter fifo configurations.
682 *
683 * @param base SAI base pointer.
684 * @param config fifo configurations.
685 */
686 void SAI_TxSetFifoConfig(I2S_Type *base, sai_fifo_t *config);
687
688 /*!
689 * @brief SAI receiver fifo configurations.
690 *
691 * @param base SAI base pointer.
692 * @param config fifo configurations.
693 */
694 void SAI_RxSetFifoConfig(I2S_Type *base, sai_fifo_t *config);
695 #endif
696
697 /*!
698 * @brief SAI transmitter Frame sync configurations.
699 *
700 * @param base SAI base pointer.
701 * @param masterSlave master or slave.
702 * @param config frame sync configurations, can be NULL in slave mode.
703 */
704 void SAI_TxSetFrameSyncConfig(I2S_Type *base, sai_master_slave_t masterSlave, sai_frame_sync_t *config);
705
706 /*!
707 * @brief SAI receiver Frame sync configurations.
708 *
709 * @param base SAI base pointer.
710 * @param masterSlave master or slave.
711 * @param config frame sync configurations, can be NULL in slave mode.
712 */
713 void SAI_RxSetFrameSyncConfig(I2S_Type *base, sai_master_slave_t masterSlave, sai_frame_sync_t *config);
714
715 /*!
716 * @brief SAI transmitter Serial data configurations.
717 *
718 * @param base SAI base pointer.
719 * @param config serial data configurations.
720 */
721 void SAI_TxSetSerialDataConfig(I2S_Type *base, sai_serial_data_t *config);
722
723 /*!
724 * @brief SAI receiver Serial data configurations.
725 *
726 * @param base SAI base pointer.
727 * @param config serial data configurations.
728 */
729 void SAI_RxSetSerialDataConfig(I2S_Type *base, sai_serial_data_t *config);
730
731 /*!
732 * @brief SAI transmitter configurations.
733 *
734 * @param base SAI base pointer.
735 * @param config transmitter configurations.
736 */
737 void SAI_TxSetConfig(I2S_Type *base, sai_transceiver_t *config);
738
739 /*!
740 * @brief SAI receiver configurations.
741 *
742 * @param base SAI base pointer.
743 * @param config receiver configurations.
744 */
745 void SAI_RxSetConfig(I2S_Type *base, sai_transceiver_t *config);
746
747 /*!
748 * @brief Get classic I2S mode configurations.
749 *
750 * @param config transceiver configurations.
751 * @param bitWidth audio data bitWidth.
752 * @param mode audio data channel.
753 * @param saiChannelMask mask value of the channel to be enable.
754 */
755 void SAI_GetClassicI2SConfig(sai_transceiver_t *config,
756 sai_word_width_t bitWidth,
757 sai_mono_stereo_t mode,
758 uint32_t saiChannelMask);
759
760 /*!
761 * @brief Get left justified mode configurations.
762 *
763 * @param config transceiver configurations.
764 * @param bitWidth audio data bitWidth.
765 * @param mode audio data channel.
766 * @param saiChannelMask mask value of the channel to be enable.
767 */
768 void SAI_GetLeftJustifiedConfig(sai_transceiver_t *config,
769 sai_word_width_t bitWidth,
770 sai_mono_stereo_t mode,
771 uint32_t saiChannelMask);
772
773 /*!
774 * @brief Get right justified mode configurations.
775 *
776 * @param config transceiver configurations.
777 * @param bitWidth audio data bitWidth.
778 * @param mode audio data channel.
779 * @param saiChannelMask mask value of the channel to be enable.
780 */
781 void SAI_GetRightJustifiedConfig(sai_transceiver_t *config,
782 sai_word_width_t bitWidth,
783 sai_mono_stereo_t mode,
784 uint32_t saiChannelMask);
785
786 /*!
787 * @brief Get TDM mode configurations.
788 *
789 * @param config transceiver configurations.
790 * @param frameSyncWidth length of frame sync.
791 * @param bitWidth audio data word width.
792 * @param dataWordNum word number in one frame.
793 * @param saiChannelMask mask value of the channel to be enable.
794 */
795 void SAI_GetTDMConfig(sai_transceiver_t *config,
796 sai_frame_sync_len_t frameSyncWidth,
797 sai_word_width_t bitWidth,
798 uint32_t dataWordNum,
799 uint32_t saiChannelMask);
800
801 /*!
802 * @brief Get DSP mode configurations.
803 *
804 * @note DSP mode is also called PCM mode which support MODE A and MODE B,
805 * DSP/PCM MODE A configuration flow. RX is similiar but uses SAI_RxSetConfig instead of SAI_TxSetConfig:
806 * @code
807 * SAI_GetDSPConfig(config, kSAI_FrameSyncLenOneBitClk, bitWidth, kSAI_Stereo, channelMask)
808 * config->frameSync.frameSyncEarly = true;
809 * SAI_TxSetConfig(base, config)
810 * @endcode
811 *
812 * DSP/PCM MODE B configuration flow for TX. RX is similiar but uses SAI_RxSetConfig instead of SAI_TxSetConfig:
813 * @code
814 * SAI_GetDSPConfig(config, kSAI_FrameSyncLenOneBitClk, bitWidth, kSAI_Stereo, channelMask)
815 * SAI_TxSetConfig(base, config)
816 * @endcode
817 *
818 * @param config transceiver configurations.
819 * @param frameSyncWidth length of frame sync.
820 * @param bitWidth audio data bitWidth.
821 * @param mode audio data channel.
822 * @param saiChannelMask mask value of the channel to enable.
823 */
824 void SAI_GetDSPConfig(sai_transceiver_t *config,
825 sai_frame_sync_len_t frameSyncWidth,
826 sai_word_width_t bitWidth,
827 sai_mono_stereo_t mode,
828 uint32_t saiChannelMask);
829 /*! @} */
830
831 /*!
832 * @name Status
833 * @{
834 */
835
836 /*!
837 * @brief Gets the SAI Tx status flag state.
838 *
839 * @param base SAI base pointer
840 * @return SAI Tx status flag value. Use the Status Mask to get the status value needed.
841 */
SAI_TxGetStatusFlag(I2S_Type * base)842 static inline uint32_t SAI_TxGetStatusFlag(I2S_Type *base)
843 {
844 return base->TCSR;
845 }
846
847 /*!
848 * @brief Clears the SAI Tx status flag state.
849 *
850 * @param base SAI base pointer
851 * @param mask State mask. It can be a combination of the following source if defined:
852 * @arg kSAI_WordStartFlag
853 * @arg kSAI_SyncErrorFlag
854 * @arg kSAI_FIFOErrorFlag
855 */
SAI_TxClearStatusFlags(I2S_Type * base,uint32_t mask)856 static inline void SAI_TxClearStatusFlags(I2S_Type *base, uint32_t mask)
857 {
858 base->TCSR = ((base->TCSR & 0xFFE3FFFFU) | mask);
859 }
860
861 /*!
862 * @brief Gets the SAI Tx status flag state.
863 *
864 * @param base SAI base pointer
865 * @return SAI Rx status flag value. Use the Status Mask to get the status value needed.
866 */
SAI_RxGetStatusFlag(I2S_Type * base)867 static inline uint32_t SAI_RxGetStatusFlag(I2S_Type *base)
868 {
869 return base->RCSR;
870 }
871
872 /*!
873 * @brief Clears the SAI Rx status flag state.
874 *
875 * @param base SAI base pointer
876 * @param mask State mask. It can be a combination of the following sources if defined.
877 * @arg kSAI_WordStartFlag
878 * @arg kSAI_SyncErrorFlag
879 * @arg kSAI_FIFOErrorFlag
880 */
SAI_RxClearStatusFlags(I2S_Type * base,uint32_t mask)881 static inline void SAI_RxClearStatusFlags(I2S_Type *base, uint32_t mask)
882 {
883 base->RCSR = ((base->RCSR & 0xFFE3FFFFU) | mask);
884 }
885
886 /*!
887 * @brief Do software reset or FIFO reset .
888 *
889 * FIFO reset means clear all the data in the FIFO, and make the FIFO pointer both to 0.
890 * Software reset means clear the Tx internal logic, including the bit clock, frame count etc. But software
891 * reset will not clear any configuration registers like TCR1~TCR5.
892 * This function will also clear all the error flags such as FIFO error, sync error etc.
893 *
894 * @param base SAI base pointer
895 * @param resetType Reset type, FIFO reset or software reset
896 */
897 void SAI_TxSoftwareReset(I2S_Type *base, sai_reset_type_t resetType);
898
899 /*!
900 * @brief Do software reset or FIFO reset .
901 *
902 * FIFO reset means clear all the data in the FIFO, and make the FIFO pointer both to 0.
903 * Software reset means clear the Rx internal logic, including the bit clock, frame count etc. But software
904 * reset will not clear any configuration registers like RCR1~RCR5.
905 * This function will also clear all the error flags such as FIFO error, sync error etc.
906 *
907 * @param base SAI base pointer
908 * @param resetType Reset type, FIFO reset or software reset
909 */
910 void SAI_RxSoftwareReset(I2S_Type *base, sai_reset_type_t resetType);
911
912 /*!
913 * @brief Set the Tx channel FIFO enable mask.
914 *
915 * @param base SAI base pointer
916 * @param mask Channel enable mask, 0 means all channel FIFO disabled, 1 means channel 0 enabled,
917 * 3 means both channel 0 and channel 1 enabled.
918 */
919 void SAI_TxSetChannelFIFOMask(I2S_Type *base, uint8_t mask);
920
921 /*!
922 * @brief Set the Rx channel FIFO enable mask.
923 *
924 * @param base SAI base pointer
925 * @param mask Channel enable mask, 0 means all channel FIFO disabled, 1 means channel 0 enabled,
926 * 3 means both channel 0 and channel 1 enabled.
927 */
928 void SAI_RxSetChannelFIFOMask(I2S_Type *base, uint8_t mask);
929
930 /*!
931 * @brief Set the Tx data order.
932 *
933 * @param base SAI base pointer
934 * @param order Data order MSB or LSB
935 */
936 void SAI_TxSetDataOrder(I2S_Type *base, sai_data_order_t order);
937
938 /*!
939 * @brief Set the Rx data order.
940 *
941 * @param base SAI base pointer
942 * @param order Data order MSB or LSB
943 */
944 void SAI_RxSetDataOrder(I2S_Type *base, sai_data_order_t order);
945
946 /*!
947 * @brief Set the Tx data order.
948 *
949 * @param base SAI base pointer
950 * @param polarity
951 */
952 void SAI_TxSetBitClockPolarity(I2S_Type *base, sai_clock_polarity_t polarity);
953
954 /*!
955 * @brief Set the Rx data order.
956 *
957 * @param base SAI base pointer
958 * @param polarity
959 */
960 void SAI_RxSetBitClockPolarity(I2S_Type *base, sai_clock_polarity_t polarity);
961
962 /*!
963 * @brief Set the Tx data order.
964 *
965 * @param base SAI base pointer
966 * @param polarity
967 */
968 void SAI_TxSetFrameSyncPolarity(I2S_Type *base, sai_clock_polarity_t polarity);
969
970 /*!
971 * @brief Set the Rx data order.
972 *
973 * @param base SAI base pointer
974 * @param polarity
975 */
976 void SAI_RxSetFrameSyncPolarity(I2S_Type *base, sai_clock_polarity_t polarity);
977
978 #if defined(FSL_FEATURE_SAI_HAS_FIFO_PACKING) && FSL_FEATURE_SAI_HAS_FIFO_PACKING
979 /*!
980 * @brief Set Tx FIFO packing feature.
981 *
982 * @param base SAI base pointer.
983 * @param pack FIFO pack type. It is element of sai_fifo_packing_t.
984 */
985 void SAI_TxSetFIFOPacking(I2S_Type *base, sai_fifo_packing_t pack);
986
987 /*!
988 * @brief Set Rx FIFO packing feature.
989 *
990 * @param base SAI base pointer.
991 * @param pack FIFO pack type. It is element of sai_fifo_packing_t.
992 */
993 void SAI_RxSetFIFOPacking(I2S_Type *base, sai_fifo_packing_t pack);
994 #endif /* FSL_FEATURE_SAI_HAS_FIFO_PACKING */
995
996 #if defined(FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR) && FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR
997 /*!
998 * @brief Set Tx FIFO error continue.
999 *
1000 * FIFO error continue mode means SAI will keep running while FIFO error occurred. If this feature
1001 * not enabled, SAI will hang and users need to clear FEF flag in TCSR register.
1002 *
1003 * @param base SAI base pointer.
1004 * @param isEnabled Is FIFO error continue enabled, true means enable, false means disable.
1005 */
SAI_TxSetFIFOErrorContinue(I2S_Type * base,bool isEnabled)1006 static inline void SAI_TxSetFIFOErrorContinue(I2S_Type *base, bool isEnabled)
1007 {
1008 if (isEnabled)
1009 {
1010 base->TCR4 |= I2S_TCR4_FCONT_MASK;
1011 }
1012 else
1013 {
1014 base->TCR4 &= ~I2S_TCR4_FCONT_MASK;
1015 }
1016 }
1017
1018 /*!
1019 * @brief Set Rx FIFO error continue.
1020 *
1021 * FIFO error continue mode means SAI will keep running while FIFO error occurred. If this feature
1022 * not enabled, SAI will hang and users need to clear FEF flag in RCSR register.
1023 *
1024 * @param base SAI base pointer.
1025 * @param isEnabled Is FIFO error continue enabled, true means enable, false means disable.
1026 */
SAI_RxSetFIFOErrorContinue(I2S_Type * base,bool isEnabled)1027 static inline void SAI_RxSetFIFOErrorContinue(I2S_Type *base, bool isEnabled)
1028 {
1029 if (isEnabled)
1030 {
1031 base->RCR4 |= I2S_RCR4_FCONT_MASK;
1032 }
1033 else
1034 {
1035 base->RCR4 &= ~I2S_RCR4_FCONT_MASK;
1036 }
1037 }
1038 #endif
1039
1040 /*! @} */
1041
1042 /*!
1043 * @name Interrupts
1044 * @{
1045 */
1046
1047 /*!
1048 * @brief Enables the SAI Tx interrupt requests.
1049 *
1050 * @param base SAI base pointer
1051 * @param mask interrupt source
1052 * The parameter can be a combination of the following sources if defined.
1053 * @arg kSAI_WordStartInterruptEnable
1054 * @arg kSAI_SyncErrorInterruptEnable
1055 * @arg kSAI_FIFOWarningInterruptEnable
1056 * @arg kSAI_FIFORequestInterruptEnable
1057 * @arg kSAI_FIFOErrorInterruptEnable
1058 */
SAI_TxEnableInterrupts(I2S_Type * base,uint32_t mask)1059 static inline void SAI_TxEnableInterrupts(I2S_Type *base, uint32_t mask)
1060 {
1061 base->TCSR = ((base->TCSR & 0xFFE3FFFFU) | mask);
1062 }
1063
1064 /*!
1065 * @brief Enables the SAI Rx interrupt requests.
1066 *
1067 * @param base SAI base pointer
1068 * @param mask interrupt source
1069 * The parameter can be a combination of the following sources if defined.
1070 * @arg kSAI_WordStartInterruptEnable
1071 * @arg kSAI_SyncErrorInterruptEnable
1072 * @arg kSAI_FIFOWarningInterruptEnable
1073 * @arg kSAI_FIFORequestInterruptEnable
1074 * @arg kSAI_FIFOErrorInterruptEnable
1075 */
SAI_RxEnableInterrupts(I2S_Type * base,uint32_t mask)1076 static inline void SAI_RxEnableInterrupts(I2S_Type *base, uint32_t mask)
1077 {
1078 base->RCSR = ((base->RCSR & 0xFFE3FFFFU) | mask);
1079 }
1080
1081 /*!
1082 * @brief Disables the SAI Tx interrupt requests.
1083 *
1084 * @param base SAI base pointer
1085 * @param mask interrupt source
1086 * The parameter can be a combination of the following sources if defined.
1087 * @arg kSAI_WordStartInterruptEnable
1088 * @arg kSAI_SyncErrorInterruptEnable
1089 * @arg kSAI_FIFOWarningInterruptEnable
1090 * @arg kSAI_FIFORequestInterruptEnable
1091 * @arg kSAI_FIFOErrorInterruptEnable
1092 */
SAI_TxDisableInterrupts(I2S_Type * base,uint32_t mask)1093 static inline void SAI_TxDisableInterrupts(I2S_Type *base, uint32_t mask)
1094 {
1095 base->TCSR = ((base->TCSR & 0xFFE3FFFFU) & (~mask));
1096 }
1097
1098 /*!
1099 * @brief Disables the SAI Rx interrupt requests.
1100 *
1101 * @param base SAI base pointer
1102 * @param mask interrupt source
1103 * The parameter can be a combination of the following sources if defined.
1104 * @arg kSAI_WordStartInterruptEnable
1105 * @arg kSAI_SyncErrorInterruptEnable
1106 * @arg kSAI_FIFOWarningInterruptEnable
1107 * @arg kSAI_FIFORequestInterruptEnable
1108 * @arg kSAI_FIFOErrorInterruptEnable
1109 */
SAI_RxDisableInterrupts(I2S_Type * base,uint32_t mask)1110 static inline void SAI_RxDisableInterrupts(I2S_Type *base, uint32_t mask)
1111 {
1112 base->RCSR = ((base->RCSR & 0xFFE3FFFFU) & (~mask));
1113 }
1114
1115 /*! @} */
1116
1117 /*!
1118 * @name DMA Control
1119 * @{
1120 */
1121
1122 /*!
1123 * @brief Enables/disables the SAI Tx DMA requests.
1124 * @param base SAI base pointer
1125 * @param mask DMA source
1126 * The parameter can be combination of the following sources if defined.
1127 * @arg kSAI_FIFOWarningDMAEnable
1128 * @arg kSAI_FIFORequestDMAEnable
1129 * @param enable True means enable DMA, false means disable DMA.
1130 */
SAI_TxEnableDMA(I2S_Type * base,uint32_t mask,bool enable)1131 static inline void SAI_TxEnableDMA(I2S_Type *base, uint32_t mask, bool enable)
1132 {
1133 if (enable)
1134 {
1135 base->TCSR = ((base->TCSR & 0xFFE3FFFFU) | mask);
1136 }
1137 else
1138 {
1139 base->TCSR = ((base->TCSR & 0xFFE3FFFFU) & (~mask));
1140 }
1141 }
1142
1143 /*!
1144 * @brief Enables/disables the SAI Rx DMA requests.
1145 * @param base SAI base pointer
1146 * @param mask DMA source
1147 * The parameter can be a combination of the following sources if defined.
1148 * @arg kSAI_FIFOWarningDMAEnable
1149 * @arg kSAI_FIFORequestDMAEnable
1150 * @param enable True means enable DMA, false means disable DMA.
1151 */
SAI_RxEnableDMA(I2S_Type * base,uint32_t mask,bool enable)1152 static inline void SAI_RxEnableDMA(I2S_Type *base, uint32_t mask, bool enable)
1153 {
1154 if (enable)
1155 {
1156 base->RCSR = ((base->RCSR & 0xFFE3FFFFU) | mask);
1157 }
1158 else
1159 {
1160 base->RCSR = ((base->RCSR & 0xFFE3FFFFU) & (~mask));
1161 }
1162 }
1163
1164 /*!
1165 * @brief Gets the SAI Tx data register address.
1166 *
1167 * This API is used to provide a transfer address for the SAI DMA transfer configuration.
1168 *
1169 * @param base SAI base pointer.
1170 * @param channel Which data channel used.
1171 * @return data register address.
1172 */
SAI_TxGetDataRegisterAddress(I2S_Type * base,uint32_t channel)1173 static inline uintptr_t SAI_TxGetDataRegisterAddress(I2S_Type *base, uint32_t channel)
1174 {
1175 return (uintptr_t)(&(base->TDR)[channel]);
1176 }
1177
1178 /*!
1179 * @brief Gets the SAI Rx data register address.
1180 *
1181 * This API is used to provide a transfer address for the SAI DMA transfer configuration.
1182 *
1183 * @param base SAI base pointer.
1184 * @param channel Which data channel used.
1185 * @return data register address.
1186 */
SAI_RxGetDataRegisterAddress(I2S_Type * base,uint32_t channel)1187 static inline uintptr_t SAI_RxGetDataRegisterAddress(I2S_Type *base, uint32_t channel)
1188 {
1189 return (uintptr_t)(&(base->RDR)[channel]);
1190 }
1191
1192 /*! @} */
1193
1194 /*!
1195 * @name Bus Operations
1196 * @{
1197 */
1198
1199 /*!
1200 * @brief Sends data using a blocking method.
1201 *
1202 * @note This function blocks by polling until data is ready to be sent.
1203 *
1204 * @param base SAI base pointer.
1205 * @param channel Data channel used.
1206 * @param bitWidth How many bits in an audio word; usually 8/16/24/32 bits.
1207 * @param buffer Pointer to the data to be written.
1208 * @param size Bytes to be written.
1209 */
1210 void SAI_WriteBlocking(I2S_Type *base, uint32_t channel, uint32_t bitWidth, uint8_t *buffer, uint32_t size);
1211
1212 /*!
1213 * @brief Sends data to multi channel using a blocking method.
1214 *
1215 * @note This function blocks by polling until data is ready to be sent.
1216 *
1217 * @param base SAI base pointer.
1218 * @param channel Data channel used.
1219 * @param channelMask channel mask.
1220 * @param bitWidth How many bits in an audio word; usually 8/16/24/32 bits.
1221 * @param buffer Pointer to the data to be written.
1222 * @param size Bytes to be written.
1223 */
1224 void SAI_WriteMultiChannelBlocking(
1225 I2S_Type *base, uint32_t channel, uint32_t channelMask, uint32_t bitWidth, uint8_t *buffer, uint32_t size);
1226
1227 /*!
1228 * @brief Writes data into SAI FIFO.
1229 *
1230 * @param base SAI base pointer.
1231 * @param channel Data channel used.
1232 * @param data Data needs to be written.
1233 */
SAI_WriteData(I2S_Type * base,uint32_t channel,uint32_t data)1234 static inline void SAI_WriteData(I2S_Type *base, uint32_t channel, uint32_t data)
1235 {
1236 base->TDR[channel] = data;
1237 }
1238
1239 /*!
1240 * @brief Receives data using a blocking method.
1241 *
1242 * @note This function blocks by polling until data is ready to be sent.
1243 *
1244 * @param base SAI base pointer.
1245 * @param channel Data channel used.
1246 * @param bitWidth How many bits in an audio word; usually 8/16/24/32 bits.
1247 * @param buffer Pointer to the data to be read.
1248 * @param size Bytes to be read.
1249 */
1250 void SAI_ReadBlocking(I2S_Type *base, uint32_t channel, uint32_t bitWidth, uint8_t *buffer, uint32_t size);
1251
1252 /*!
1253 * @brief Receives multi channel data using a blocking method.
1254 *
1255 * @note This function blocks by polling until data is ready to be sent.
1256 *
1257 * @param base SAI base pointer.
1258 * @param channel Data channel used.
1259 * @param channelMask channel mask.
1260 * @param bitWidth How many bits in an audio word; usually 8/16/24/32 bits.
1261 * @param buffer Pointer to the data to be read.
1262 * @param size Bytes to be read.
1263 */
1264 void SAI_ReadMultiChannelBlocking(
1265 I2S_Type *base, uint32_t channel, uint32_t channelMask, uint32_t bitWidth, uint8_t *buffer, uint32_t size);
1266
1267 /*!
1268 * @brief Reads data from the SAI FIFO.
1269 *
1270 * @param base SAI base pointer.
1271 * @param channel Data channel used.
1272 * @return Data in SAI FIFO.
1273 */
SAI_ReadData(I2S_Type * base,uint32_t channel)1274 static inline uint32_t SAI_ReadData(I2S_Type *base, uint32_t channel)
1275 {
1276 return base->RDR[channel];
1277 }
1278
1279 /*! @} */
1280
1281 /*!
1282 * @name Transactional
1283 * @{
1284 */
1285
1286 /*!
1287 * @brief Initializes the SAI Tx handle.
1288 *
1289 * This function initializes the Tx handle for the SAI Tx transactional APIs. Call
1290 * this function once to get the handle initialized.
1291 *
1292 * @param base SAI base pointer
1293 * @param handle SAI handle pointer.
1294 * @param callback Pointer to the user callback function.
1295 * @param userData User parameter passed to the callback function
1296 */
1297 void SAI_TransferTxCreateHandle(I2S_Type *base, sai_handle_t *handle, sai_transfer_callback_t callback, void *userData);
1298
1299 /*!
1300 * @brief Initializes the SAI Rx handle.
1301 *
1302 * This function initializes the Rx handle for the SAI Rx transactional APIs. Call
1303 * this function once to get the handle initialized.
1304 *
1305 * @param base SAI base pointer.
1306 * @param handle SAI handle pointer.
1307 * @param callback Pointer to the user callback function.
1308 * @param userData User parameter passed to the callback function.
1309 */
1310 void SAI_TransferRxCreateHandle(I2S_Type *base, sai_handle_t *handle, sai_transfer_callback_t callback, void *userData);
1311
1312 /*!
1313 * @brief SAI transmitter transfer configurations.
1314 *
1315 * This function initializes the Tx, include bit clock, frame sync, master clock, serial data and fifo
1316 * configurations.
1317 *
1318 * @param base SAI base pointer.
1319 * @param handle SAI handle pointer.
1320 * @param config tranmitter configurations.
1321 */
1322 void SAI_TransferTxSetConfig(I2S_Type *base, sai_handle_t *handle, sai_transceiver_t *config);
1323
1324 /*!
1325 * @brief SAI receiver transfer configurations.
1326 *
1327 * This function initializes the Rx, include bit clock, frame sync, master clock, serial data and fifo
1328 * configurations.
1329 *
1330 * @param base SAI base pointer.
1331 * @param handle SAI handle pointer.
1332 * @param config receiver configurations.
1333 */
1334 void SAI_TransferRxSetConfig(I2S_Type *base, sai_handle_t *handle, sai_transceiver_t *config);
1335
1336
1337 /*!
1338 * @brief Performs an interrupt non-blocking send transfer on SAI.
1339 *
1340 * @note This API returns immediately after the transfer initiates.
1341 * Call the SAI_TxGetTransferStatusIRQ to poll the transfer status and check whether
1342 * the transfer is finished. If the return status is not kStatus_SAI_Busy, the transfer
1343 * is finished.
1344 *
1345 * @param base SAI base pointer.
1346 * @param handle Pointer to the sai_handle_t structure which stores the transfer state.
1347 * @param xfer Pointer to the sai_transfer_t structure.
1348 * @retval kStatus_Success Successfully started the data receive.
1349 * @retval kStatus_SAI_TxBusy Previous receive still not finished.
1350 * @retval kStatus_InvalidArgument The input parameter is invalid.
1351 */
1352 status_t SAI_TransferSendNonBlocking(I2S_Type *base, sai_handle_t *handle, sai_transfer_t *xfer);
1353
1354 /*!
1355 * @brief Performs an interrupt non-blocking receive transfer on SAI.
1356 *
1357 * @note This API returns immediately after the transfer initiates.
1358 * Call the SAI_RxGetTransferStatusIRQ to poll the transfer status and check whether
1359 * the transfer is finished. If the return status is not kStatus_SAI_Busy, the transfer
1360 * is finished.
1361 *
1362 * @param base SAI base pointer
1363 * @param handle Pointer to the sai_handle_t structure which stores the transfer state.
1364 * @param xfer Pointer to the sai_transfer_t structure.
1365 * @retval kStatus_Success Successfully started the data receive.
1366 * @retval kStatus_SAI_RxBusy Previous receive still not finished.
1367 * @retval kStatus_InvalidArgument The input parameter is invalid.
1368 */
1369 status_t SAI_TransferReceiveNonBlocking(I2S_Type *base, sai_handle_t *handle, sai_transfer_t *xfer);
1370
1371 /*!
1372 * @brief Gets a set byte count.
1373 *
1374 * @param base SAI base pointer.
1375 * @param handle Pointer to the sai_handle_t structure which stores the transfer state.
1376 * @param count Bytes count sent.
1377 * @retval kStatus_Success Succeed get the transfer count.
1378 * @retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress.
1379 */
1380 status_t SAI_TransferGetSendCount(I2S_Type *base, sai_handle_t *handle, size_t *count);
1381
1382 /*!
1383 * @brief Gets a received byte count.
1384 *
1385 * @param base SAI base pointer.
1386 * @param handle Pointer to the sai_handle_t structure which stores the transfer state.
1387 * @param count Bytes count received.
1388 * @retval kStatus_Success Succeed get the transfer count.
1389 * @retval kStatus_NoTransferInProgress There is not a non-blocking transaction currently in progress.
1390 */
1391 status_t SAI_TransferGetReceiveCount(I2S_Type *base, sai_handle_t *handle, size_t *count);
1392
1393 /*!
1394 * @brief Aborts the current send.
1395 *
1396 * @note This API can be called any time when an interrupt non-blocking transfer initiates
1397 * to abort the transfer early.
1398 *
1399 * @param base SAI base pointer.
1400 * @param handle Pointer to the sai_handle_t structure which stores the transfer state.
1401 */
1402 void SAI_TransferAbortSend(I2S_Type *base, sai_handle_t *handle);
1403
1404 /*!
1405 * @brief Aborts the current IRQ receive.
1406 *
1407 * @note This API can be called when an interrupt non-blocking transfer initiates
1408 * to abort the transfer early.
1409 *
1410 * @param base SAI base pointer
1411 * @param handle Pointer to the sai_handle_t structure which stores the transfer state.
1412 */
1413 void SAI_TransferAbortReceive(I2S_Type *base, sai_handle_t *handle);
1414
1415 /*!
1416 * @brief Terminate all SAI send.
1417 *
1418 * This function will clear all transfer slots buffered in the sai queue. If users only want to abort the
1419 * current transfer slot, please call SAI_TransferAbortSend.
1420 *
1421 * @param base SAI base pointer.
1422 * @param handle SAI eDMA handle pointer.
1423 */
1424 void SAI_TransferTerminateSend(I2S_Type *base, sai_handle_t *handle);
1425
1426 /*!
1427 * @brief Terminate all SAI receive.
1428 *
1429 * This function will clear all transfer slots buffered in the sai queue. If users only want to abort the
1430 * current transfer slot, please call SAI_TransferAbortReceive.
1431 *
1432 * @param base SAI base pointer.
1433 * @param handle SAI eDMA handle pointer.
1434 */
1435 void SAI_TransferTerminateReceive(I2S_Type *base, sai_handle_t *handle);
1436
1437 /*!
1438 * @brief Tx interrupt handler.
1439 *
1440 * @param base SAI base pointer.
1441 * @param handle Pointer to the sai_handle_t structure.
1442 */
1443 void SAI_TransferTxHandleIRQ(I2S_Type *base, sai_handle_t *handle);
1444
1445 /*!
1446 * @brief Tx interrupt handler.
1447 *
1448 * @param base SAI base pointer.
1449 * @param handle Pointer to the sai_handle_t structure.
1450 */
1451 void SAI_TransferRxHandleIRQ(I2S_Type *base, sai_handle_t *handle);
1452
1453 /*! @} */
1454
1455 #if defined(__cplusplus)
1456 }
1457 #endif /*_cplusplus*/
1458
1459 /*! @} */
1460
1461 #endif /* FSL_SAI_H_ */
1462
