1 /*
2 * Copyright 2021-2023 NXP
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 /**
8 * @file SchM_Icu.c
9 * @version 1.0.0
10 *
11 * @brief AUTOSAR Rte - module implementation
12 * @details This module implements stubs for the AUTOSAR Rte
13 * This file contains sample code only. It is not part of the production code deliverables.
14 *
15 * @addtogroup RTE_MODULE
16 * @{
17 */
18
19 #ifdef __cplusplus
20 extern "C"{
21 #endif
22
23 /*==================================================================================================
24 * INCLUDE FILES
25 * 1) system and project includes
26 * 2) needed interfaces from external units
27 * 3) internal and external interfaces from this unit
28 ==================================================================================================*/
29 #include "Std_Types.h"
30 #include "Mcal.h"
31 #include "OsIf.h"
32 #include "SchM_Icu.h"
33 #ifdef MCAL_TESTING_ENVIRONMENT
34 #include "EUnit.h" /* EUnit Test Suite */
35 #endif
36
37 /*==================================================================================================
38 * SOURCE FILE VERSION INFORMATION
39 ==================================================================================================*/
40 #define SCHM_ICU_AR_RELEASE_MAJOR_VERSION_C 4
41 #define SCHM_ICU_AR_RELEASE_MINOR_VERSION_C 7
42 #define SCHM_ICU_AR_RELEASE_REVISION_VERSION_C 0
43 #define SCHM_ICU_SW_MAJOR_VERSION_C 1
44 #define SCHM_ICU_SW_MINOR_VERSION_C 0
45 #define SCHM_ICU_SW_PATCH_VERSION_C 0
46
47 /*==================================================================================================
48 * LOCAL CONSTANTS
49 ==================================================================================================*/
50 #ifdef MCAL_PLATFORM_ARM
51 #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
52 #define ISR_STATE_MASK ((uint32)0x000000C0UL) /**< @brief DAIF bit I and F */
53 #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
54 #define ISR_STATE_MASK ((uint32)0x00000080UL) /**< @brief CPSR bit I */
55 #else
56 #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
57 #define ISR_STATE_MASK ((uint32)0x000000FFUL) /**< @brief BASEPRI[7:0] mask */
58 #else
59 #define ISR_STATE_MASK ((uint32)0x00000001UL) /**< @brief PRIMASK bit 0 */
60 #endif
61 #endif
62 #else
63 #ifdef MCAL_PLATFORM_S12
64 #define ISR_STATE_MASK ((uint32)0x00000010UL) /**< @brief I bit of CCR */
65 #else
66 #define ISR_STATE_MASK ((uint32)0x00008000UL) /**< @brief EE bit of MSR */
67 #endif
68 #endif
69 /*==================================================================================================
70 * LOCAL MACROS
71 ==================================================================================================*/
72 #ifdef MCAL_PLATFORM_ARM
73 #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
74 #define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) != (uint32)(ISR_STATE_MASK))
75 #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
76 #define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) != (uint32)(ISR_STATE_MASK))
77 #else
78 #define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) == (uint32)0)
79 #endif
80 #else
81 #ifdef MCAL_PLATFORM_S12
82 #define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) == (uint32)0)
83 #else
84 #define ISR_ON(msr) (uint32)((uint32)(msr) & (uint32)(ISR_STATE_MASK))
85 #endif
86 #endif
87
88 /*==================================================================================================
89 * FILE VERSION CHECKS
90 ==================================================================================================*/
91
92 /*==================================================================================================
93 * LOCAL TYPEDEFS (STRUCTURES, UNIONS, ENUMS)
94 ==================================================================================================*/
95
96
97 /*==================================================================================================
98 * LOCAL VARIABLES
99 ==================================================================================================*/
100 #define RTE_START_SEC_VAR_CLEARED_32_NO_CACHEABLE
101 #include "Rte_MemMap.h"
102 VAR_SEC_NOCACHE(msr_ICU_EXCLUSIVE_AREA_00) static volatile uint32 msr_ICU_EXCLUSIVE_AREA_00[NUMBER_OF_CORES];
103 VAR_SEC_NOCACHE(reentry_guard_ICU_EXCLUSIVE_AREA_00) static volatile uint32 reentry_guard_ICU_EXCLUSIVE_AREA_00[NUMBER_OF_CORES];
104 VAR_SEC_NOCACHE(msr_ICU_EXCLUSIVE_AREA_01) static volatile uint32 msr_ICU_EXCLUSIVE_AREA_01[NUMBER_OF_CORES];
105 VAR_SEC_NOCACHE(reentry_guard_ICU_EXCLUSIVE_AREA_01) static volatile uint32 reentry_guard_ICU_EXCLUSIVE_AREA_01[NUMBER_OF_CORES];
106 VAR_SEC_NOCACHE(msr_ICU_EXCLUSIVE_AREA_02) static volatile uint32 msr_ICU_EXCLUSIVE_AREA_02[NUMBER_OF_CORES];
107 VAR_SEC_NOCACHE(reentry_guard_ICU_EXCLUSIVE_AREA_02) static volatile uint32 reentry_guard_ICU_EXCLUSIVE_AREA_02[NUMBER_OF_CORES];
108 VAR_SEC_NOCACHE(msr_ICU_EXCLUSIVE_AREA_03) static volatile uint32 msr_ICU_EXCLUSIVE_AREA_03[NUMBER_OF_CORES];
109 VAR_SEC_NOCACHE(reentry_guard_ICU_EXCLUSIVE_AREA_03) static volatile uint32 reentry_guard_ICU_EXCLUSIVE_AREA_03[NUMBER_OF_CORES];
110 VAR_SEC_NOCACHE(msr_ICU_EXCLUSIVE_AREA_04) static volatile uint32 msr_ICU_EXCLUSIVE_AREA_04[NUMBER_OF_CORES];
111 VAR_SEC_NOCACHE(reentry_guard_ICU_EXCLUSIVE_AREA_04) static volatile uint32 reentry_guard_ICU_EXCLUSIVE_AREA_04[NUMBER_OF_CORES];
112 VAR_SEC_NOCACHE(msr_ICU_EXCLUSIVE_AREA_05) static volatile uint32 msr_ICU_EXCLUSIVE_AREA_05[NUMBER_OF_CORES];
113 VAR_SEC_NOCACHE(reentry_guard_ICU_EXCLUSIVE_AREA_05) static volatile uint32 reentry_guard_ICU_EXCLUSIVE_AREA_05[NUMBER_OF_CORES];
114 VAR_SEC_NOCACHE(msr_ICU_EXCLUSIVE_AREA_06) static volatile uint32 msr_ICU_EXCLUSIVE_AREA_06[NUMBER_OF_CORES];
115 VAR_SEC_NOCACHE(reentry_guard_ICU_EXCLUSIVE_AREA_06) static volatile uint32 reentry_guard_ICU_EXCLUSIVE_AREA_06[NUMBER_OF_CORES];
116 VAR_SEC_NOCACHE(msr_ICU_EXCLUSIVE_AREA_07) static volatile uint32 msr_ICU_EXCLUSIVE_AREA_07[NUMBER_OF_CORES];
117 VAR_SEC_NOCACHE(reentry_guard_ICU_EXCLUSIVE_AREA_07) static volatile uint32 reentry_guard_ICU_EXCLUSIVE_AREA_07[NUMBER_OF_CORES];
118 VAR_SEC_NOCACHE(msr_ICU_EXCLUSIVE_AREA_08) static volatile uint32 msr_ICU_EXCLUSIVE_AREA_08[NUMBER_OF_CORES];
119 VAR_SEC_NOCACHE(reentry_guard_ICU_EXCLUSIVE_AREA_08) static volatile uint32 reentry_guard_ICU_EXCLUSIVE_AREA_08[NUMBER_OF_CORES];
120 VAR_SEC_NOCACHE(msr_ICU_EXCLUSIVE_AREA_09) static volatile uint32 msr_ICU_EXCLUSIVE_AREA_09[NUMBER_OF_CORES];
121 VAR_SEC_NOCACHE(reentry_guard_ICU_EXCLUSIVE_AREA_09) static volatile uint32 reentry_guard_ICU_EXCLUSIVE_AREA_09[NUMBER_OF_CORES];
122 VAR_SEC_NOCACHE(msr_ICU_EXCLUSIVE_AREA_11) static volatile uint32 msr_ICU_EXCLUSIVE_AREA_11[NUMBER_OF_CORES];
123 VAR_SEC_NOCACHE(reentry_guard_ICU_EXCLUSIVE_AREA_11) static volatile uint32 reentry_guard_ICU_EXCLUSIVE_AREA_11[NUMBER_OF_CORES];
124 VAR_SEC_NOCACHE(msr_ICU_EXCLUSIVE_AREA_15) static volatile uint32 msr_ICU_EXCLUSIVE_AREA_15[NUMBER_OF_CORES];
125 VAR_SEC_NOCACHE(reentry_guard_ICU_EXCLUSIVE_AREA_15) static volatile uint32 reentry_guard_ICU_EXCLUSIVE_AREA_15[NUMBER_OF_CORES];
126 VAR_SEC_NOCACHE(msr_ICU_EXCLUSIVE_AREA_16) static volatile uint32 msr_ICU_EXCLUSIVE_AREA_16[NUMBER_OF_CORES];
127 VAR_SEC_NOCACHE(reentry_guard_ICU_EXCLUSIVE_AREA_16) static volatile uint32 reentry_guard_ICU_EXCLUSIVE_AREA_16[NUMBER_OF_CORES];
128 VAR_SEC_NOCACHE(msr_ICU_EXCLUSIVE_AREA_17) static volatile uint32 msr_ICU_EXCLUSIVE_AREA_17[NUMBER_OF_CORES];
129 VAR_SEC_NOCACHE(reentry_guard_ICU_EXCLUSIVE_AREA_17) static volatile uint32 reentry_guard_ICU_EXCLUSIVE_AREA_17[NUMBER_OF_CORES];
130 VAR_SEC_NOCACHE(msr_ICU_EXCLUSIVE_AREA_18) static volatile uint32 msr_ICU_EXCLUSIVE_AREA_18[NUMBER_OF_CORES];
131 VAR_SEC_NOCACHE(reentry_guard_ICU_EXCLUSIVE_AREA_18) static volatile uint32 reentry_guard_ICU_EXCLUSIVE_AREA_18[NUMBER_OF_CORES];
132 VAR_SEC_NOCACHE(msr_ICU_EXCLUSIVE_AREA_19) static volatile uint32 msr_ICU_EXCLUSIVE_AREA_19[NUMBER_OF_CORES];
133 VAR_SEC_NOCACHE(reentry_guard_ICU_EXCLUSIVE_AREA_19) static volatile uint32 reentry_guard_ICU_EXCLUSIVE_AREA_19[NUMBER_OF_CORES];
134 VAR_SEC_NOCACHE(msr_ICU_EXCLUSIVE_AREA_20) static volatile uint32 msr_ICU_EXCLUSIVE_AREA_20[NUMBER_OF_CORES];
135 VAR_SEC_NOCACHE(reentry_guard_ICU_EXCLUSIVE_AREA_20) static volatile uint32 reentry_guard_ICU_EXCLUSIVE_AREA_20[NUMBER_OF_CORES];
136 VAR_SEC_NOCACHE(msr_ICU_EXCLUSIVE_AREA_21) static volatile uint32 msr_ICU_EXCLUSIVE_AREA_21[NUMBER_OF_CORES];
137 VAR_SEC_NOCACHE(reentry_guard_ICU_EXCLUSIVE_AREA_21) static volatile uint32 reentry_guard_ICU_EXCLUSIVE_AREA_21[NUMBER_OF_CORES];
138 VAR_SEC_NOCACHE(msr_ICU_EXCLUSIVE_AREA_22) static volatile uint32 msr_ICU_EXCLUSIVE_AREA_22[NUMBER_OF_CORES];
139 VAR_SEC_NOCACHE(reentry_guard_ICU_EXCLUSIVE_AREA_22) static volatile uint32 reentry_guard_ICU_EXCLUSIVE_AREA_22[NUMBER_OF_CORES];
140 VAR_SEC_NOCACHE(msr_ICU_EXCLUSIVE_AREA_23) static volatile uint32 msr_ICU_EXCLUSIVE_AREA_23[NUMBER_OF_CORES];
141 VAR_SEC_NOCACHE(reentry_guard_ICU_EXCLUSIVE_AREA_23) static volatile uint32 reentry_guard_ICU_EXCLUSIVE_AREA_23[NUMBER_OF_CORES];
142 VAR_SEC_NOCACHE(msr_ICU_EXCLUSIVE_AREA_24) static volatile uint32 msr_ICU_EXCLUSIVE_AREA_24[NUMBER_OF_CORES];
143 VAR_SEC_NOCACHE(reentry_guard_ICU_EXCLUSIVE_AREA_24) static volatile uint32 reentry_guard_ICU_EXCLUSIVE_AREA_24[NUMBER_OF_CORES];
144 VAR_SEC_NOCACHE(msr_ICU_EXCLUSIVE_AREA_25) static volatile uint32 msr_ICU_EXCLUSIVE_AREA_25[NUMBER_OF_CORES];
145 VAR_SEC_NOCACHE(reentry_guard_ICU_EXCLUSIVE_AREA_25) static volatile uint32 reentry_guard_ICU_EXCLUSIVE_AREA_25[NUMBER_OF_CORES];
146 VAR_SEC_NOCACHE(msr_ICU_EXCLUSIVE_AREA_26) static volatile uint32 msr_ICU_EXCLUSIVE_AREA_26[NUMBER_OF_CORES];
147 VAR_SEC_NOCACHE(reentry_guard_ICU_EXCLUSIVE_AREA_26) static volatile uint32 reentry_guard_ICU_EXCLUSIVE_AREA_26[NUMBER_OF_CORES];
148 VAR_SEC_NOCACHE(msr_ICU_EXCLUSIVE_AREA_27) static volatile uint32 msr_ICU_EXCLUSIVE_AREA_27[NUMBER_OF_CORES];
149 VAR_SEC_NOCACHE(reentry_guard_ICU_EXCLUSIVE_AREA_27) static volatile uint32 reentry_guard_ICU_EXCLUSIVE_AREA_27[NUMBER_OF_CORES];
150 VAR_SEC_NOCACHE(msr_ICU_EXCLUSIVE_AREA_28) static volatile uint32 msr_ICU_EXCLUSIVE_AREA_28[NUMBER_OF_CORES];
151 VAR_SEC_NOCACHE(reentry_guard_ICU_EXCLUSIVE_AREA_28) static volatile uint32 reentry_guard_ICU_EXCLUSIVE_AREA_28[NUMBER_OF_CORES];
152 VAR_SEC_NOCACHE(msr_ICU_EXCLUSIVE_AREA_29) static volatile uint32 msr_ICU_EXCLUSIVE_AREA_29[NUMBER_OF_CORES];
153 VAR_SEC_NOCACHE(reentry_guard_ICU_EXCLUSIVE_AREA_29) static volatile uint32 reentry_guard_ICU_EXCLUSIVE_AREA_29[NUMBER_OF_CORES];
154 VAR_SEC_NOCACHE(msr_ICU_EXCLUSIVE_AREA_30) static volatile uint32 msr_ICU_EXCLUSIVE_AREA_30[NUMBER_OF_CORES];
155 VAR_SEC_NOCACHE(reentry_guard_ICU_EXCLUSIVE_AREA_30) static volatile uint32 reentry_guard_ICU_EXCLUSIVE_AREA_30[NUMBER_OF_CORES];
156 VAR_SEC_NOCACHE(msr_ICU_EXCLUSIVE_AREA_31) static volatile uint32 msr_ICU_EXCLUSIVE_AREA_31[NUMBER_OF_CORES];
157 VAR_SEC_NOCACHE(reentry_guard_ICU_EXCLUSIVE_AREA_31) static volatile uint32 reentry_guard_ICU_EXCLUSIVE_AREA_31[NUMBER_OF_CORES];
158 VAR_SEC_NOCACHE(msr_ICU_EXCLUSIVE_AREA_32) static volatile uint32 msr_ICU_EXCLUSIVE_AREA_32[NUMBER_OF_CORES];
159 VAR_SEC_NOCACHE(reentry_guard_ICU_EXCLUSIVE_AREA_32) static volatile uint32 reentry_guard_ICU_EXCLUSIVE_AREA_32[NUMBER_OF_CORES];
160 VAR_SEC_NOCACHE(msr_ICU_EXCLUSIVE_AREA_33) static volatile uint32 msr_ICU_EXCLUSIVE_AREA_33[NUMBER_OF_CORES];
161 VAR_SEC_NOCACHE(reentry_guard_ICU_EXCLUSIVE_AREA_33) static volatile uint32 reentry_guard_ICU_EXCLUSIVE_AREA_33[NUMBER_OF_CORES];
162 VAR_SEC_NOCACHE(msr_ICU_EXCLUSIVE_AREA_44) static volatile uint32 msr_ICU_EXCLUSIVE_AREA_44[NUMBER_OF_CORES];
163 VAR_SEC_NOCACHE(reentry_guard_ICU_EXCLUSIVE_AREA_44) static volatile uint32 reentry_guard_ICU_EXCLUSIVE_AREA_44[NUMBER_OF_CORES];
164 VAR_SEC_NOCACHE(msr_ICU_EXCLUSIVE_AREA_45) static volatile uint32 msr_ICU_EXCLUSIVE_AREA_45[NUMBER_OF_CORES];
165 VAR_SEC_NOCACHE(reentry_guard_ICU_EXCLUSIVE_AREA_45) static volatile uint32 reentry_guard_ICU_EXCLUSIVE_AREA_45[NUMBER_OF_CORES];
166 VAR_SEC_NOCACHE(msr_ICU_EXCLUSIVE_AREA_46) static volatile uint32 msr_ICU_EXCLUSIVE_AREA_46[NUMBER_OF_CORES];
167 VAR_SEC_NOCACHE(reentry_guard_ICU_EXCLUSIVE_AREA_46) static volatile uint32 reentry_guard_ICU_EXCLUSIVE_AREA_46[NUMBER_OF_CORES];
168 VAR_SEC_NOCACHE(msr_ICU_EXCLUSIVE_AREA_47) static volatile uint32 msr_ICU_EXCLUSIVE_AREA_47[NUMBER_OF_CORES];
169 VAR_SEC_NOCACHE(reentry_guard_ICU_EXCLUSIVE_AREA_47) static volatile uint32 reentry_guard_ICU_EXCLUSIVE_AREA_47[NUMBER_OF_CORES];
170 VAR_SEC_NOCACHE(msr_ICU_EXCLUSIVE_AREA_48) static volatile uint32 msr_ICU_EXCLUSIVE_AREA_48[NUMBER_OF_CORES];
171 VAR_SEC_NOCACHE(reentry_guard_ICU_EXCLUSIVE_AREA_48) static volatile uint32 reentry_guard_ICU_EXCLUSIVE_AREA_48[NUMBER_OF_CORES];
172 VAR_SEC_NOCACHE(msr_ICU_EXCLUSIVE_AREA_49) static volatile uint32 msr_ICU_EXCLUSIVE_AREA_49[NUMBER_OF_CORES];
173 VAR_SEC_NOCACHE(reentry_guard_ICU_EXCLUSIVE_AREA_49) static volatile uint32 reentry_guard_ICU_EXCLUSIVE_AREA_49[NUMBER_OF_CORES];
174 VAR_SEC_NOCACHE(msr_ICU_EXCLUSIVE_AREA_50) static volatile uint32 msr_ICU_EXCLUSIVE_AREA_50[NUMBER_OF_CORES];
175 VAR_SEC_NOCACHE(reentry_guard_ICU_EXCLUSIVE_AREA_50) static volatile uint32 reentry_guard_ICU_EXCLUSIVE_AREA_50[NUMBER_OF_CORES];
176 VAR_SEC_NOCACHE(msr_ICU_EXCLUSIVE_AREA_51) static volatile uint32 msr_ICU_EXCLUSIVE_AREA_51[NUMBER_OF_CORES];
177 VAR_SEC_NOCACHE(reentry_guard_ICU_EXCLUSIVE_AREA_51) static volatile uint32 reentry_guard_ICU_EXCLUSIVE_AREA_51[NUMBER_OF_CORES];
178 VAR_SEC_NOCACHE(msr_ICU_EXCLUSIVE_AREA_52) static volatile uint32 msr_ICU_EXCLUSIVE_AREA_52[NUMBER_OF_CORES];
179 VAR_SEC_NOCACHE(reentry_guard_ICU_EXCLUSIVE_AREA_52) static volatile uint32 reentry_guard_ICU_EXCLUSIVE_AREA_52[NUMBER_OF_CORES];
180 VAR_SEC_NOCACHE(msr_ICU_EXCLUSIVE_AREA_53) static volatile uint32 msr_ICU_EXCLUSIVE_AREA_53[NUMBER_OF_CORES];
181 VAR_SEC_NOCACHE(reentry_guard_ICU_EXCLUSIVE_AREA_53) static volatile uint32 reentry_guard_ICU_EXCLUSIVE_AREA_53[NUMBER_OF_CORES];
182 VAR_SEC_NOCACHE(msr_ICU_EXCLUSIVE_AREA_57) static volatile uint32 msr_ICU_EXCLUSIVE_AREA_57[NUMBER_OF_CORES];
183 VAR_SEC_NOCACHE(reentry_guard_ICU_EXCLUSIVE_AREA_57) static volatile uint32 reentry_guard_ICU_EXCLUSIVE_AREA_57[NUMBER_OF_CORES];
184 VAR_SEC_NOCACHE(msr_ICU_EXCLUSIVE_AREA_58) static volatile uint32 msr_ICU_EXCLUSIVE_AREA_58[NUMBER_OF_CORES];
185 VAR_SEC_NOCACHE(reentry_guard_ICU_EXCLUSIVE_AREA_58) static volatile uint32 reentry_guard_ICU_EXCLUSIVE_AREA_58[NUMBER_OF_CORES];
186 VAR_SEC_NOCACHE(msr_ICU_EXCLUSIVE_AREA_59) static volatile uint32 msr_ICU_EXCLUSIVE_AREA_59[NUMBER_OF_CORES];
187 VAR_SEC_NOCACHE(reentry_guard_ICU_EXCLUSIVE_AREA_59) static volatile uint32 reentry_guard_ICU_EXCLUSIVE_AREA_59[NUMBER_OF_CORES];
188
189 #define RTE_STOP_SEC_VAR_CLEARED_32_NO_CACHEABLE
190 #include "Rte_MemMap.h"
191 /*==================================================================================================
192 * GLOBAL CONSTANTS
193 ==================================================================================================*/
194
195
196 /*==================================================================================================
197 * GLOBAL VARIABLES
198 ==================================================================================================*/
199
200 /*==================================================================================================
201 * LOCAL FUNCTION PROTOTYPES
202 ==================================================================================================*/
203
204 #ifndef _COSMIC_C_S32ZE_
205 /*================================================================================================*/
206 /**
207 * @brief This function returns the MSR register value (32 bits).
208 * @details This function returns the MSR register value (32 bits).
209 *
210 * @param[in] void No input parameters
211 * @return uint32 msr This function returns the MSR register value (32 bits).
212 *
213 * @pre None
214 * @post None
215 *
216 */
217 uint32 Icu_schm_read_msr(void);
218 #endif /*ifndef _COSMIC_C_S32ZE_*/
219 /*==================================================================================================
220 * LOCAL FUNCTIONS
221 ==================================================================================================*/
222 #define RTE_START_SEC_CODE
223 #include "Rte_MemMap.h"
224
225 #if (defined(_GREENHILLS_C_S32ZE_) || defined(_CODEWARRIOR_C_S32ZE_))
226 /*================================================================================================*/
227 /**
228 * @brief This macro returns the MSR register value (32 bits).
229 * @details This macro function implementation returns the MSR register value in r3 (32 bits).
230 *
231 * @pre None
232 * @post None
233 *
234 */
235 #ifdef MCAL_PLATFORM_ARM
236 #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
Icu_schm_read_msr(void)237 ASM_KEYWORD uint32 Icu_schm_read_msr(void)
238 {
239 mrs x0, S3_3_c4_c2_1
240 }
241 #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
Icu_schm_read_msr(void)242 ASM_KEYWORD uint32 Icu_schm_read_msr(void)
243 {
244 mrs r0, CPSR
245 }
246 #else
Icu_schm_read_msr(void)247 ASM_KEYWORD uint32 Icu_schm_read_msr(void)
248 {
249 #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
250 mrs r0, BASEPRI
251 #else
252 mrs r0, PRIMASK
253 #endif
254 }
255 #endif
256 #else
257 #ifdef MCAL_PLATFORM_S12
Icu_schm_read_msr(void)258 ASM_KEYWORD uint32 Icu_schm_read_msr(void)
259 {
260 tfr ccr, d6
261 }
262 #else
Icu_schm_read_msr(void)263 ASM_KEYWORD uint32 Icu_schm_read_msr(void)
264 {
265 mfmsr r3
266 }
267 #endif
268 #endif
269 #endif /*#ifdef GHS||CW*/
270
271 #ifdef _DIABDATA_C_S32ZE_
272 /**
273 * @brief This function returns the MSR register value (32 bits).
274 * @details This function returns the MSR register value (32 bits).
275 *
276 * @param[in] void No input parameters
277 * @return uint32 msr This function returns the MSR register value (32 bits).
278 *
279 * @pre None
280 * @post None
281 *
282 */
283 #ifdef MCAL_PLATFORM_ARM
Icu_schm_read_msr(void)284 uint32 Icu_schm_read_msr(void)
285 {
286 register uint32 reg_tmp;
287 #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
288 __asm volatile( " mrs %x0, DAIF " : "=r" (reg_tmp) );
289 #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
290 __asm volatile( " mrs %0, CPSR " : "=r" (reg_tmp) );
291 #else
292 #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
293 __asm volatile( " mrs %0, basepri " : "=r" (reg_tmp) );
294 #else
295 __asm volatile( " mrs %0, primask " : "=r" (reg_tmp) );
296 #endif
297 #endif
298 return (uint32)reg_tmp;
299 }
300 #else
Icu_schm_read_msr(void)301 ASM_KEYWORD uint32 Icu_schm_read_msr(void)
302 {
303 mfmsr r3
304 }
305 #endif /* MCAL_PLATFORM_ARM */
306
307 #endif /* _DIABDATA_C_S32ZE_*/
308
309 #ifdef _COSMIC_C_S32ZE_
310 /*================================================================================================*/
311 /**
312 * @brief This function returns the MSR register value (32 bits).
313 * @details This function returns the MSR register value (32 bits).
314 *
315 * @param[in] void No input parameters
316 * @return uint32 msr This function returns the MSR register value (32 bits).
317 *
318 * @pre None
319 * @post None
320 *
321 */
322
323 #ifdef MCAL_PLATFORM_S12
324 #define Icu_schm_read_msr() ASM_KEYWORD("tfr ccr, d6")
325 #else
326 #define Icu_schm_read_msr() ASM_KEYWORD("mfmsr r3")
327 #endif
328
329 #endif /*Cosmic compiler only*/
330
331
332 #ifdef _HITECH_C_S32ZE_
333 /*================================================================================================*/
334 /**
335 * @brief This function returns the MSR register value (32 bits).
336 * @details This function returns the MSR register value (32 bits).
337 *
338 * @param[in] void No input parameters
339 * @return uint32 msr This function returns the MSR register value (32 bits).
340 *
341 * @pre None
342 * @post None
343 *
344 */
Icu_schm_read_msr(void)345 uint32 Icu_schm_read_msr(void)
346 {
347 uint32 result;
348 __asm volatile("mfmsr %0" : "=r" (result) :);
349 return result;
350 }
351
352 #endif /*HighTec compiler only*/
353 /*================================================================================================*/
354 #ifdef _LINARO_C_S32ZE_
355 /**
356 * @brief This function returns the MSR register value (32 bits).
357 * @details This function returns the MSR register value (32 bits).
358 *
359 * @param[in] void No input parameters
360 * @return uint32 msr This function returns the MSR register value (32 bits).
361 *
362 * @pre None
363 * @post None
364 *
365 */
Icu_schm_read_msr(void)366 uint32 Icu_schm_read_msr(void)
367 {
368 register uint32 reg_tmp;
369 #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
370 __asm volatile( " mrs %x0, DAIF " : "=r" (reg_tmp) );
371 #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
372 __asm volatile( " mrs %0, CPSR " : "=r" (reg_tmp) );
373 #else
374 #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
375 __asm volatile( " mrs %0, basepri " : "=r" (reg_tmp) );
376 #else
377 __asm volatile( " mrs %0, primask " : "=r" (reg_tmp) );
378 #endif
379 #endif
380 return (uint32)reg_tmp;
381 }
382 #endif /* _LINARO_C_S32ZE_*/
383 /*================================================================================================*/
384
385 #ifdef _ARM_DS5_C_S32ZE_
386 /**
387 * @brief This function returns the MSR register value (32 bits).
388 * @details This function returns the MSR register value (32 bits).
389 *
390 * @param[in] void No input parameters
391 * @return uint32 msr This function returns the MSR register value (32 bits).
392 *
393 * @pre None
394 * @post None
395 *
396 */
Icu_schm_read_msr(void)397 uint32 Icu_schm_read_msr(void)
398 {
399 register uint32 reg_tmp;
400 #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
401 __asm volatile( " mrs %x0, DAIF " : "=r" (reg_tmp) );
402 #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
403 __asm volatile( " mrs %0, CPSR " : "=r" (reg_tmp) );
404 #else
405 #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
406 __asm volatile( " mrs %0, basepri " : "=r" (reg_tmp) );
407 #else
408 __asm volatile( " mrs %0, primask " : "=r" (reg_tmp) );
409 #endif
410 #endif
411 return (uint32)reg_tmp;
412 }
413 #endif /* _ARM_DS5_C_S32ZE_ */
414
415 #ifdef _IAR_C_S32ZE_
416 /**
417 * @brief This function returns the MSR register value (32 bits).
418 * @details This function returns the MSR register value (32 bits).
419 *
420 * @param[in] void No input parameters
421 * @return uint32 msr This function returns the MSR register value (32 bits).
422 *
423 * @pre None
424 * @post None
425 *
426 */
Icu_schm_read_msr(void)427 uint32 Icu_schm_read_msr(void)
428 {
429 register uint32 reg_tmp;
430
431 #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
432 __asm volatile( " mrs %0, basepri " : "=r" (reg_tmp) );
433 #else
434 __asm volatile( " mrs %0, primask " : "=r" (reg_tmp) );
435 #endif
436
437 return (uint32)reg_tmp;
438 }
439 #endif /* _IAR_C_S32ZE_ */
440
441 #define RTE_STOP_SEC_CODE
442 #include "Rte_MemMap.h"
443
444 /*==================================================================================================
445 * GLOBAL FUNCTIONS
446 ==================================================================================================*/
447 #define RTE_START_SEC_CODE
448 #include "Rte_MemMap.h"
449
SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_00(void)450 void SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_00(void)
451 {
452 uint32 msr;
453 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
454
455 if(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_00[u32CoreId])
456 {
457 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
458 msr = OsIf_Trusted_Call_Return(Icu_schm_read_msr);
459 #else
460 msr = Icu_schm_read_msr(); /*read MSR (to store interrupts state)*/
461 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
462 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
463 {
464 OsIf_SuspendAllInterrupts();
465 #ifdef _ARM_DS5_C_S32ZE_
466 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
467 #endif
468 }
469 msr_ICU_EXCLUSIVE_AREA_00[u32CoreId] = msr;
470 }
471 reentry_guard_ICU_EXCLUSIVE_AREA_00[u32CoreId]++;
472 }
473
SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_00(void)474 void SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_00(void)
475 {
476 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
477
478 reentry_guard_ICU_EXCLUSIVE_AREA_00[u32CoreId]--;
479 if ((ISR_ON(msr_ICU_EXCLUSIVE_AREA_00[u32CoreId]))&&(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_00[u32CoreId])) /*if interrupts were enabled*/
480 {
481 OsIf_ResumeAllInterrupts();
482 #ifdef _ARM_DS5_C_S32ZE_
483 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
484 #endif
485 }
486 }
487
SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_01(void)488 void SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_01(void)
489 {
490 uint32 msr;
491 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
492
493 if(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_01[u32CoreId])
494 {
495 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
496 msr = OsIf_Trusted_Call_Return(Icu_schm_read_msr);
497 #else
498 msr = Icu_schm_read_msr(); /*read MSR (to store interrupts state)*/
499 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
500 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
501 {
502 OsIf_SuspendAllInterrupts();
503 #ifdef _ARM_DS5_C_S32ZE_
504 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
505 #endif
506 }
507 msr_ICU_EXCLUSIVE_AREA_01[u32CoreId] = msr;
508 }
509 reentry_guard_ICU_EXCLUSIVE_AREA_01[u32CoreId]++;
510 }
511
SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_01(void)512 void SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_01(void)
513 {
514 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
515
516 reentry_guard_ICU_EXCLUSIVE_AREA_01[u32CoreId]--;
517 if ((ISR_ON(msr_ICU_EXCLUSIVE_AREA_01[u32CoreId]))&&(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_01[u32CoreId])) /*if interrupts were enabled*/
518 {
519 OsIf_ResumeAllInterrupts();
520 #ifdef _ARM_DS5_C_S32ZE_
521 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
522 #endif
523 }
524 }
525
SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_02(void)526 void SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_02(void)
527 {
528 uint32 msr;
529 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
530
531 if(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_02[u32CoreId])
532 {
533 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
534 msr = OsIf_Trusted_Call_Return(Icu_schm_read_msr);
535 #else
536 msr = Icu_schm_read_msr(); /*read MSR (to store interrupts state)*/
537 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
538 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
539 {
540 OsIf_SuspendAllInterrupts();
541 #ifdef _ARM_DS5_C_S32ZE_
542 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
543 #endif
544 }
545 msr_ICU_EXCLUSIVE_AREA_02[u32CoreId] = msr;
546 }
547 reentry_guard_ICU_EXCLUSIVE_AREA_02[u32CoreId]++;
548 }
549
SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_02(void)550 void SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_02(void)
551 {
552 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
553
554 reentry_guard_ICU_EXCLUSIVE_AREA_02[u32CoreId]--;
555 if ((ISR_ON(msr_ICU_EXCLUSIVE_AREA_02[u32CoreId]))&&(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_02[u32CoreId])) /*if interrupts were enabled*/
556 {
557 OsIf_ResumeAllInterrupts();
558 #ifdef _ARM_DS5_C_S32ZE_
559 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
560 #endif
561 }
562 }
563
SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_03(void)564 void SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_03(void)
565 {
566 uint32 msr;
567 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
568
569 if(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_03[u32CoreId])
570 {
571 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
572 msr = OsIf_Trusted_Call_Return(Icu_schm_read_msr);
573 #else
574 msr = Icu_schm_read_msr(); /*read MSR (to store interrupts state)*/
575 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
576 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
577 {
578 OsIf_SuspendAllInterrupts();
579 #ifdef _ARM_DS5_C_S32ZE_
580 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
581 #endif
582 }
583 msr_ICU_EXCLUSIVE_AREA_03[u32CoreId] = msr;
584 }
585 reentry_guard_ICU_EXCLUSIVE_AREA_03[u32CoreId]++;
586 }
587
SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_03(void)588 void SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_03(void)
589 {
590 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
591
592 reentry_guard_ICU_EXCLUSIVE_AREA_03[u32CoreId]--;
593 if ((ISR_ON(msr_ICU_EXCLUSIVE_AREA_03[u32CoreId]))&&(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_03[u32CoreId])) /*if interrupts were enabled*/
594 {
595 OsIf_ResumeAllInterrupts();
596 #ifdef _ARM_DS5_C_S32ZE_
597 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
598 #endif
599 }
600 }
601
SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_04(void)602 void SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_04(void)
603 {
604 uint32 msr;
605 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
606
607 if(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_04[u32CoreId])
608 {
609 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
610 msr = OsIf_Trusted_Call_Return(Icu_schm_read_msr);
611 #else
612 msr = Icu_schm_read_msr(); /*read MSR (to store interrupts state)*/
613 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
614 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
615 {
616 OsIf_SuspendAllInterrupts();
617 #ifdef _ARM_DS5_C_S32ZE_
618 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
619 #endif
620 }
621 msr_ICU_EXCLUSIVE_AREA_04[u32CoreId] = msr;
622 }
623 reentry_guard_ICU_EXCLUSIVE_AREA_04[u32CoreId]++;
624 }
625
SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_04(void)626 void SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_04(void)
627 {
628 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
629
630 reentry_guard_ICU_EXCLUSIVE_AREA_04[u32CoreId]--;
631 if ((ISR_ON(msr_ICU_EXCLUSIVE_AREA_04[u32CoreId]))&&(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_04[u32CoreId])) /*if interrupts were enabled*/
632 {
633 OsIf_ResumeAllInterrupts();
634 #ifdef _ARM_DS5_C_S32ZE_
635 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
636 #endif
637 }
638 }
639
SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_05(void)640 void SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_05(void)
641 {
642 uint32 msr;
643 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
644
645 if(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_05[u32CoreId])
646 {
647 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
648 msr = OsIf_Trusted_Call_Return(Icu_schm_read_msr);
649 #else
650 msr = Icu_schm_read_msr(); /*read MSR (to store interrupts state)*/
651 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
652 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
653 {
654 OsIf_SuspendAllInterrupts();
655 #ifdef _ARM_DS5_C_S32ZE_
656 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
657 #endif
658 }
659 msr_ICU_EXCLUSIVE_AREA_05[u32CoreId] = msr;
660 }
661 reentry_guard_ICU_EXCLUSIVE_AREA_05[u32CoreId]++;
662 }
663
SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_05(void)664 void SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_05(void)
665 {
666 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
667
668 reentry_guard_ICU_EXCLUSIVE_AREA_05[u32CoreId]--;
669 if ((ISR_ON(msr_ICU_EXCLUSIVE_AREA_05[u32CoreId]))&&(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_05[u32CoreId])) /*if interrupts were enabled*/
670 {
671 OsIf_ResumeAllInterrupts();
672 #ifdef _ARM_DS5_C_S32ZE_
673 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
674 #endif
675 }
676 }
677
SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_06(void)678 void SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_06(void)
679 {
680 uint32 msr;
681 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
682
683 if(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_06[u32CoreId])
684 {
685 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
686 msr = OsIf_Trusted_Call_Return(Icu_schm_read_msr);
687 #else
688 msr = Icu_schm_read_msr(); /*read MSR (to store interrupts state)*/
689 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
690 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
691 {
692 OsIf_SuspendAllInterrupts();
693 #ifdef _ARM_DS5_C_S32ZE_
694 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
695 #endif
696 }
697 msr_ICU_EXCLUSIVE_AREA_06[u32CoreId] = msr;
698 }
699 reentry_guard_ICU_EXCLUSIVE_AREA_06[u32CoreId]++;
700 }
701
SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_06(void)702 void SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_06(void)
703 {
704 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
705
706 reentry_guard_ICU_EXCLUSIVE_AREA_06[u32CoreId]--;
707 if ((ISR_ON(msr_ICU_EXCLUSIVE_AREA_06[u32CoreId]))&&(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_06[u32CoreId])) /*if interrupts were enabled*/
708 {
709 OsIf_ResumeAllInterrupts();
710 #ifdef _ARM_DS5_C_S32ZE_
711 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
712 #endif
713 }
714 }
715
SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_07(void)716 void SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_07(void)
717 {
718 uint32 msr;
719 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
720
721 if(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_07[u32CoreId])
722 {
723 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
724 msr = OsIf_Trusted_Call_Return(Icu_schm_read_msr);
725 #else
726 msr = Icu_schm_read_msr(); /*read MSR (to store interrupts state)*/
727 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
728 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
729 {
730 OsIf_SuspendAllInterrupts();
731 #ifdef _ARM_DS5_C_S32ZE_
732 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
733 #endif
734 }
735 msr_ICU_EXCLUSIVE_AREA_07[u32CoreId] = msr;
736 }
737 reentry_guard_ICU_EXCLUSIVE_AREA_07[u32CoreId]++;
738 }
739
SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_07(void)740 void SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_07(void)
741 {
742 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
743
744 reentry_guard_ICU_EXCLUSIVE_AREA_07[u32CoreId]--;
745 if ((ISR_ON(msr_ICU_EXCLUSIVE_AREA_07[u32CoreId]))&&(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_07[u32CoreId])) /*if interrupts were enabled*/
746 {
747 OsIf_ResumeAllInterrupts();
748 #ifdef _ARM_DS5_C_S32ZE_
749 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
750 #endif
751 }
752 }
753
SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_08(void)754 void SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_08(void)
755 {
756 uint32 msr;
757 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
758
759 if(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_08[u32CoreId])
760 {
761 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
762 msr = OsIf_Trusted_Call_Return(Icu_schm_read_msr);
763 #else
764 msr = Icu_schm_read_msr(); /*read MSR (to store interrupts state)*/
765 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
766 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
767 {
768 OsIf_SuspendAllInterrupts();
769 #ifdef _ARM_DS5_C_S32ZE_
770 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
771 #endif
772 }
773 msr_ICU_EXCLUSIVE_AREA_08[u32CoreId] = msr;
774 }
775 reentry_guard_ICU_EXCLUSIVE_AREA_08[u32CoreId]++;
776 }
777
SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_08(void)778 void SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_08(void)
779 {
780 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
781
782 reentry_guard_ICU_EXCLUSIVE_AREA_08[u32CoreId]--;
783 if ((ISR_ON(msr_ICU_EXCLUSIVE_AREA_08[u32CoreId]))&&(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_08[u32CoreId])) /*if interrupts were enabled*/
784 {
785 OsIf_ResumeAllInterrupts();
786 #ifdef _ARM_DS5_C_S32ZE_
787 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
788 #endif
789 }
790 }
791
SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_09(void)792 void SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_09(void)
793 {
794 uint32 msr;
795 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
796
797 if(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_09[u32CoreId])
798 {
799 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
800 msr = OsIf_Trusted_Call_Return(Icu_schm_read_msr);
801 #else
802 msr = Icu_schm_read_msr(); /*read MSR (to store interrupts state)*/
803 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
804 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
805 {
806 OsIf_SuspendAllInterrupts();
807 #ifdef _ARM_DS5_C_S32ZE_
808 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
809 #endif
810 }
811 msr_ICU_EXCLUSIVE_AREA_09[u32CoreId] = msr;
812 }
813 reentry_guard_ICU_EXCLUSIVE_AREA_09[u32CoreId]++;
814 }
815
SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_09(void)816 void SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_09(void)
817 {
818 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
819
820 reentry_guard_ICU_EXCLUSIVE_AREA_09[u32CoreId]--;
821 if ((ISR_ON(msr_ICU_EXCLUSIVE_AREA_09[u32CoreId]))&&(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_09[u32CoreId])) /*if interrupts were enabled*/
822 {
823 OsIf_ResumeAllInterrupts();
824 #ifdef _ARM_DS5_C_S32ZE_
825 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
826 #endif
827 }
828 }
829
SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_11(void)830 void SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_11(void)
831 {
832 uint32 msr;
833 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
834
835 if(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_11[u32CoreId])
836 {
837 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
838 msr = OsIf_Trusted_Call_Return(Icu_schm_read_msr);
839 #else
840 msr = Icu_schm_read_msr(); /*read MSR (to store interrupts state)*/
841 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
842 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
843 {
844 OsIf_SuspendAllInterrupts();
845 #ifdef _ARM_DS5_C_S32ZE_
846 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
847 #endif
848 }
849 msr_ICU_EXCLUSIVE_AREA_11[u32CoreId] = msr;
850 }
851 reentry_guard_ICU_EXCLUSIVE_AREA_11[u32CoreId]++;
852 }
853
SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_11(void)854 void SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_11(void)
855 {
856 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
857
858 reentry_guard_ICU_EXCLUSIVE_AREA_11[u32CoreId]--;
859 if ((ISR_ON(msr_ICU_EXCLUSIVE_AREA_11[u32CoreId]))&&(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_11[u32CoreId])) /*if interrupts were enabled*/
860 {
861 OsIf_ResumeAllInterrupts();
862 #ifdef _ARM_DS5_C_S32ZE_
863 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
864 #endif
865 }
866 }
867
SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_15(void)868 void SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_15(void)
869 {
870 uint32 msr;
871 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
872
873 if(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_15[u32CoreId])
874 {
875 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
876 msr = OsIf_Trusted_Call_Return(Icu_schm_read_msr);
877 #else
878 msr = Icu_schm_read_msr(); /*read MSR (to store interrupts state)*/
879 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
880 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
881 {
882 OsIf_SuspendAllInterrupts();
883 #ifdef _ARM_DS5_C_S32ZE_
884 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
885 #endif
886 }
887 msr_ICU_EXCLUSIVE_AREA_15[u32CoreId] = msr;
888 }
889 reentry_guard_ICU_EXCLUSIVE_AREA_15[u32CoreId]++;
890 }
891
SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_15(void)892 void SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_15(void)
893 {
894 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
895
896 reentry_guard_ICU_EXCLUSIVE_AREA_15[u32CoreId]--;
897 if ((ISR_ON(msr_ICU_EXCLUSIVE_AREA_15[u32CoreId]))&&(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_15[u32CoreId])) /*if interrupts were enabled*/
898 {
899 OsIf_ResumeAllInterrupts();
900 #ifdef _ARM_DS5_C_S32ZE_
901 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
902 #endif
903 }
904 }
905
SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_16(void)906 void SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_16(void)
907 {
908 uint32 msr;
909 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
910
911 if(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_16[u32CoreId])
912 {
913 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
914 msr = OsIf_Trusted_Call_Return(Icu_schm_read_msr);
915 #else
916 msr = Icu_schm_read_msr(); /*read MSR (to store interrupts state)*/
917 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
918 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
919 {
920 OsIf_SuspendAllInterrupts();
921 #ifdef _ARM_DS5_C_S32ZE_
922 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
923 #endif
924 }
925 msr_ICU_EXCLUSIVE_AREA_16[u32CoreId] = msr;
926 }
927 reentry_guard_ICU_EXCLUSIVE_AREA_16[u32CoreId]++;
928 }
929
SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_16(void)930 void SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_16(void)
931 {
932 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
933
934 reentry_guard_ICU_EXCLUSIVE_AREA_16[u32CoreId]--;
935 if ((ISR_ON(msr_ICU_EXCLUSIVE_AREA_16[u32CoreId]))&&(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_16[u32CoreId])) /*if interrupts were enabled*/
936 {
937 OsIf_ResumeAllInterrupts();
938 #ifdef _ARM_DS5_C_S32ZE_
939 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
940 #endif
941 }
942 }
943
SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_17(void)944 void SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_17(void)
945 {
946 uint32 msr;
947 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
948
949 if(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_17[u32CoreId])
950 {
951 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
952 msr = OsIf_Trusted_Call_Return(Icu_schm_read_msr);
953 #else
954 msr = Icu_schm_read_msr(); /*read MSR (to store interrupts state)*/
955 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
956 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
957 {
958 OsIf_SuspendAllInterrupts();
959 #ifdef _ARM_DS5_C_S32ZE_
960 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
961 #endif
962 }
963 msr_ICU_EXCLUSIVE_AREA_17[u32CoreId] = msr;
964 }
965 reentry_guard_ICU_EXCLUSIVE_AREA_17[u32CoreId]++;
966 }
967
SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_17(void)968 void SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_17(void)
969 {
970 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
971
972 reentry_guard_ICU_EXCLUSIVE_AREA_17[u32CoreId]--;
973 if ((ISR_ON(msr_ICU_EXCLUSIVE_AREA_17[u32CoreId]))&&(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_17[u32CoreId])) /*if interrupts were enabled*/
974 {
975 OsIf_ResumeAllInterrupts();
976 #ifdef _ARM_DS5_C_S32ZE_
977 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
978 #endif
979 }
980 }
981
SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_18(void)982 void SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_18(void)
983 {
984 uint32 msr;
985 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
986
987 if(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_18[u32CoreId])
988 {
989 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
990 msr = OsIf_Trusted_Call_Return(Icu_schm_read_msr);
991 #else
992 msr = Icu_schm_read_msr(); /*read MSR (to store interrupts state)*/
993 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
994 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
995 {
996 OsIf_SuspendAllInterrupts();
997 #ifdef _ARM_DS5_C_S32ZE_
998 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
999 #endif
1000 }
1001 msr_ICU_EXCLUSIVE_AREA_18[u32CoreId] = msr;
1002 }
1003 reentry_guard_ICU_EXCLUSIVE_AREA_18[u32CoreId]++;
1004 }
1005
SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_18(void)1006 void SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_18(void)
1007 {
1008 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1009
1010 reentry_guard_ICU_EXCLUSIVE_AREA_18[u32CoreId]--;
1011 if ((ISR_ON(msr_ICU_EXCLUSIVE_AREA_18[u32CoreId]))&&(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_18[u32CoreId])) /*if interrupts were enabled*/
1012 {
1013 OsIf_ResumeAllInterrupts();
1014 #ifdef _ARM_DS5_C_S32ZE_
1015 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1016 #endif
1017 }
1018 }
1019
SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_19(void)1020 void SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_19(void)
1021 {
1022 uint32 msr;
1023 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1024
1025 if(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_19[u32CoreId])
1026 {
1027 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1028 msr = OsIf_Trusted_Call_Return(Icu_schm_read_msr);
1029 #else
1030 msr = Icu_schm_read_msr(); /*read MSR (to store interrupts state)*/
1031 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1032 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1033 {
1034 OsIf_SuspendAllInterrupts();
1035 #ifdef _ARM_DS5_C_S32ZE_
1036 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1037 #endif
1038 }
1039 msr_ICU_EXCLUSIVE_AREA_19[u32CoreId] = msr;
1040 }
1041 reentry_guard_ICU_EXCLUSIVE_AREA_19[u32CoreId]++;
1042 }
1043
SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_19(void)1044 void SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_19(void)
1045 {
1046 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1047
1048 reentry_guard_ICU_EXCLUSIVE_AREA_19[u32CoreId]--;
1049 if ((ISR_ON(msr_ICU_EXCLUSIVE_AREA_19[u32CoreId]))&&(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_19[u32CoreId])) /*if interrupts were enabled*/
1050 {
1051 OsIf_ResumeAllInterrupts();
1052 #ifdef _ARM_DS5_C_S32ZE_
1053 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1054 #endif
1055 }
1056 }
1057
SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_20(void)1058 void SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_20(void)
1059 {
1060 uint32 msr;
1061 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1062
1063 if(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_20[u32CoreId])
1064 {
1065 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1066 msr = OsIf_Trusted_Call_Return(Icu_schm_read_msr);
1067 #else
1068 msr = Icu_schm_read_msr(); /*read MSR (to store interrupts state)*/
1069 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1070 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1071 {
1072 OsIf_SuspendAllInterrupts();
1073 #ifdef _ARM_DS5_C_S32ZE_
1074 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1075 #endif
1076 }
1077 msr_ICU_EXCLUSIVE_AREA_20[u32CoreId] = msr;
1078 }
1079 reentry_guard_ICU_EXCLUSIVE_AREA_20[u32CoreId]++;
1080 }
1081
SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_20(void)1082 void SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_20(void)
1083 {
1084 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1085
1086 reentry_guard_ICU_EXCLUSIVE_AREA_20[u32CoreId]--;
1087 if ((ISR_ON(msr_ICU_EXCLUSIVE_AREA_20[u32CoreId]))&&(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_20[u32CoreId])) /*if interrupts were enabled*/
1088 {
1089 OsIf_ResumeAllInterrupts();
1090 #ifdef _ARM_DS5_C_S32ZE_
1091 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1092 #endif
1093 }
1094 }
1095
SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_21(void)1096 void SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_21(void)
1097 {
1098 uint32 msr;
1099 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1100
1101 if(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_21[u32CoreId])
1102 {
1103 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1104 msr = OsIf_Trusted_Call_Return(Icu_schm_read_msr);
1105 #else
1106 msr = Icu_schm_read_msr(); /*read MSR (to store interrupts state)*/
1107 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1108 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1109 {
1110 OsIf_SuspendAllInterrupts();
1111 #ifdef _ARM_DS5_C_S32ZE_
1112 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1113 #endif
1114 }
1115 msr_ICU_EXCLUSIVE_AREA_21[u32CoreId] = msr;
1116 }
1117 reentry_guard_ICU_EXCLUSIVE_AREA_21[u32CoreId]++;
1118 }
1119
SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_21(void)1120 void SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_21(void)
1121 {
1122 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1123
1124 reentry_guard_ICU_EXCLUSIVE_AREA_21[u32CoreId]--;
1125 if ((ISR_ON(msr_ICU_EXCLUSIVE_AREA_21[u32CoreId]))&&(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_21[u32CoreId])) /*if interrupts were enabled*/
1126 {
1127 OsIf_ResumeAllInterrupts();
1128 #ifdef _ARM_DS5_C_S32ZE_
1129 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1130 #endif
1131 }
1132 }
1133
SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_22(void)1134 void SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_22(void)
1135 {
1136 uint32 msr;
1137 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1138
1139 if(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_22[u32CoreId])
1140 {
1141 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1142 msr = OsIf_Trusted_Call_Return(Icu_schm_read_msr);
1143 #else
1144 msr = Icu_schm_read_msr(); /*read MSR (to store interrupts state)*/
1145 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1146 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1147 {
1148 OsIf_SuspendAllInterrupts();
1149 #ifdef _ARM_DS5_C_S32ZE_
1150 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1151 #endif
1152 }
1153 msr_ICU_EXCLUSIVE_AREA_22[u32CoreId] = msr;
1154 }
1155 reentry_guard_ICU_EXCLUSIVE_AREA_22[u32CoreId]++;
1156 }
1157
SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_22(void)1158 void SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_22(void)
1159 {
1160 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1161
1162 reentry_guard_ICU_EXCLUSIVE_AREA_22[u32CoreId]--;
1163 if ((ISR_ON(msr_ICU_EXCLUSIVE_AREA_22[u32CoreId]))&&(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_22[u32CoreId])) /*if interrupts were enabled*/
1164 {
1165 OsIf_ResumeAllInterrupts();
1166 #ifdef _ARM_DS5_C_S32ZE_
1167 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1168 #endif
1169 }
1170 }
1171
SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_23(void)1172 void SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_23(void)
1173 {
1174 uint32 msr;
1175 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1176
1177 if(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_23[u32CoreId])
1178 {
1179 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1180 msr = OsIf_Trusted_Call_Return(Icu_schm_read_msr);
1181 #else
1182 msr = Icu_schm_read_msr(); /*read MSR (to store interrupts state)*/
1183 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1184 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1185 {
1186 OsIf_SuspendAllInterrupts();
1187 #ifdef _ARM_DS5_C_S32ZE_
1188 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1189 #endif
1190 }
1191 msr_ICU_EXCLUSIVE_AREA_23[u32CoreId] = msr;
1192 }
1193 reentry_guard_ICU_EXCLUSIVE_AREA_23[u32CoreId]++;
1194 }
1195
SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_23(void)1196 void SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_23(void)
1197 {
1198 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1199
1200 reentry_guard_ICU_EXCLUSIVE_AREA_23[u32CoreId]--;
1201 if ((ISR_ON(msr_ICU_EXCLUSIVE_AREA_23[u32CoreId]))&&(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_23[u32CoreId])) /*if interrupts were enabled*/
1202 {
1203 OsIf_ResumeAllInterrupts();
1204 #ifdef _ARM_DS5_C_S32ZE_
1205 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1206 #endif
1207 }
1208 }
1209
SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_24(void)1210 void SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_24(void)
1211 {
1212 uint32 msr;
1213 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1214
1215 if(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_24[u32CoreId])
1216 {
1217 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1218 msr = OsIf_Trusted_Call_Return(Icu_schm_read_msr);
1219 #else
1220 msr = Icu_schm_read_msr(); /*read MSR (to store interrupts state)*/
1221 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1222 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1223 {
1224 OsIf_SuspendAllInterrupts();
1225 #ifdef _ARM_DS5_C_S32ZE_
1226 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1227 #endif
1228 }
1229 msr_ICU_EXCLUSIVE_AREA_24[u32CoreId] = msr;
1230 }
1231 reentry_guard_ICU_EXCLUSIVE_AREA_24[u32CoreId]++;
1232 }
1233
SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_24(void)1234 void SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_24(void)
1235 {
1236 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1237
1238 reentry_guard_ICU_EXCLUSIVE_AREA_24[u32CoreId]--;
1239 if ((ISR_ON(msr_ICU_EXCLUSIVE_AREA_24[u32CoreId]))&&(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_24[u32CoreId])) /*if interrupts were enabled*/
1240 {
1241 OsIf_ResumeAllInterrupts();
1242 #ifdef _ARM_DS5_C_S32ZE_
1243 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1244 #endif
1245 }
1246 }
1247
SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_25(void)1248 void SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_25(void)
1249 {
1250 uint32 msr;
1251 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1252
1253 if(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_25[u32CoreId])
1254 {
1255 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1256 msr = OsIf_Trusted_Call_Return(Icu_schm_read_msr);
1257 #else
1258 msr = Icu_schm_read_msr(); /*read MSR (to store interrupts state)*/
1259 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1260 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1261 {
1262 OsIf_SuspendAllInterrupts();
1263 #ifdef _ARM_DS5_C_S32ZE_
1264 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1265 #endif
1266 }
1267 msr_ICU_EXCLUSIVE_AREA_25[u32CoreId] = msr;
1268 }
1269 reentry_guard_ICU_EXCLUSIVE_AREA_25[u32CoreId]++;
1270 }
1271
SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_25(void)1272 void SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_25(void)
1273 {
1274 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1275
1276 reentry_guard_ICU_EXCLUSIVE_AREA_25[u32CoreId]--;
1277 if ((ISR_ON(msr_ICU_EXCLUSIVE_AREA_25[u32CoreId]))&&(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_25[u32CoreId])) /*if interrupts were enabled*/
1278 {
1279 OsIf_ResumeAllInterrupts();
1280 #ifdef _ARM_DS5_C_S32ZE_
1281 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1282 #endif
1283 }
1284 }
1285
SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_26(void)1286 void SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_26(void)
1287 {
1288 uint32 msr;
1289 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1290
1291 if(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_26[u32CoreId])
1292 {
1293 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1294 msr = OsIf_Trusted_Call_Return(Icu_schm_read_msr);
1295 #else
1296 msr = Icu_schm_read_msr(); /*read MSR (to store interrupts state)*/
1297 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1298 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1299 {
1300 OsIf_SuspendAllInterrupts();
1301 #ifdef _ARM_DS5_C_S32ZE_
1302 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1303 #endif
1304 }
1305 msr_ICU_EXCLUSIVE_AREA_26[u32CoreId] = msr;
1306 }
1307 reentry_guard_ICU_EXCLUSIVE_AREA_26[u32CoreId]++;
1308 }
1309
SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_26(void)1310 void SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_26(void)
1311 {
1312 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1313
1314 reentry_guard_ICU_EXCLUSIVE_AREA_26[u32CoreId]--;
1315 if ((ISR_ON(msr_ICU_EXCLUSIVE_AREA_26[u32CoreId]))&&(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_26[u32CoreId])) /*if interrupts were enabled*/
1316 {
1317 OsIf_ResumeAllInterrupts();
1318 #ifdef _ARM_DS5_C_S32ZE_
1319 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1320 #endif
1321 }
1322 }
1323
SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_27(void)1324 void SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_27(void)
1325 {
1326 uint32 msr;
1327 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1328
1329 if(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_27[u32CoreId])
1330 {
1331 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1332 msr = OsIf_Trusted_Call_Return(Icu_schm_read_msr);
1333 #else
1334 msr = Icu_schm_read_msr(); /*read MSR (to store interrupts state)*/
1335 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1336 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1337 {
1338 OsIf_SuspendAllInterrupts();
1339 #ifdef _ARM_DS5_C_S32ZE_
1340 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1341 #endif
1342 }
1343 msr_ICU_EXCLUSIVE_AREA_27[u32CoreId] = msr;
1344 }
1345 reentry_guard_ICU_EXCLUSIVE_AREA_27[u32CoreId]++;
1346 }
1347
SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_27(void)1348 void SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_27(void)
1349 {
1350 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1351
1352 reentry_guard_ICU_EXCLUSIVE_AREA_27[u32CoreId]--;
1353 if ((ISR_ON(msr_ICU_EXCLUSIVE_AREA_27[u32CoreId]))&&(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_27[u32CoreId])) /*if interrupts were enabled*/
1354 {
1355 OsIf_ResumeAllInterrupts();
1356 #ifdef _ARM_DS5_C_S32ZE_
1357 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1358 #endif
1359 }
1360 }
1361
SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_28(void)1362 void SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_28(void)
1363 {
1364 uint32 msr;
1365 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1366
1367 if(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_28[u32CoreId])
1368 {
1369 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1370 msr = OsIf_Trusted_Call_Return(Icu_schm_read_msr);
1371 #else
1372 msr = Icu_schm_read_msr(); /*read MSR (to store interrupts state)*/
1373 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1374 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1375 {
1376 OsIf_SuspendAllInterrupts();
1377 #ifdef _ARM_DS5_C_S32ZE_
1378 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1379 #endif
1380 }
1381 msr_ICU_EXCLUSIVE_AREA_28[u32CoreId] = msr;
1382 }
1383 reentry_guard_ICU_EXCLUSIVE_AREA_28[u32CoreId]++;
1384 }
1385
SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_28(void)1386 void SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_28(void)
1387 {
1388 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1389
1390 reentry_guard_ICU_EXCLUSIVE_AREA_28[u32CoreId]--;
1391 if ((ISR_ON(msr_ICU_EXCLUSIVE_AREA_28[u32CoreId]))&&(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_28[u32CoreId])) /*if interrupts were enabled*/
1392 {
1393 OsIf_ResumeAllInterrupts();
1394 #ifdef _ARM_DS5_C_S32ZE_
1395 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1396 #endif
1397 }
1398 }
1399
SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_29(void)1400 void SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_29(void)
1401 {
1402 uint32 msr;
1403 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1404
1405 if(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_29[u32CoreId])
1406 {
1407 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1408 msr = OsIf_Trusted_Call_Return(Icu_schm_read_msr);
1409 #else
1410 msr = Icu_schm_read_msr(); /*read MSR (to store interrupts state)*/
1411 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1412 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1413 {
1414 OsIf_SuspendAllInterrupts();
1415 #ifdef _ARM_DS5_C_S32ZE_
1416 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1417 #endif
1418 }
1419 msr_ICU_EXCLUSIVE_AREA_29[u32CoreId] = msr;
1420 }
1421 reentry_guard_ICU_EXCLUSIVE_AREA_29[u32CoreId]++;
1422 }
1423
SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_29(void)1424 void SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_29(void)
1425 {
1426 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1427
1428 reentry_guard_ICU_EXCLUSIVE_AREA_29[u32CoreId]--;
1429 if ((ISR_ON(msr_ICU_EXCLUSIVE_AREA_29[u32CoreId]))&&(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_29[u32CoreId])) /*if interrupts were enabled*/
1430 {
1431 OsIf_ResumeAllInterrupts();
1432 #ifdef _ARM_DS5_C_S32ZE_
1433 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1434 #endif
1435 }
1436 }
1437
SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_30(void)1438 void SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_30(void)
1439 {
1440 uint32 msr;
1441 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1442
1443 if(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_30[u32CoreId])
1444 {
1445 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1446 msr = OsIf_Trusted_Call_Return(Icu_schm_read_msr);
1447 #else
1448 msr = Icu_schm_read_msr(); /*read MSR (to store interrupts state)*/
1449 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1450 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1451 {
1452 OsIf_SuspendAllInterrupts();
1453 #ifdef _ARM_DS5_C_S32ZE_
1454 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1455 #endif
1456 }
1457 msr_ICU_EXCLUSIVE_AREA_30[u32CoreId] = msr;
1458 }
1459 reentry_guard_ICU_EXCLUSIVE_AREA_30[u32CoreId]++;
1460 }
1461
SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_30(void)1462 void SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_30(void)
1463 {
1464 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1465
1466 reentry_guard_ICU_EXCLUSIVE_AREA_30[u32CoreId]--;
1467 if ((ISR_ON(msr_ICU_EXCLUSIVE_AREA_30[u32CoreId]))&&(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_30[u32CoreId])) /*if interrupts were enabled*/
1468 {
1469 OsIf_ResumeAllInterrupts();
1470 #ifdef _ARM_DS5_C_S32ZE_
1471 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1472 #endif
1473 }
1474 }
1475
SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_31(void)1476 void SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_31(void)
1477 {
1478 uint32 msr;
1479 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1480
1481 if(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_31[u32CoreId])
1482 {
1483 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1484 msr = OsIf_Trusted_Call_Return(Icu_schm_read_msr);
1485 #else
1486 msr = Icu_schm_read_msr(); /*read MSR (to store interrupts state)*/
1487 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1488 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1489 {
1490 OsIf_SuspendAllInterrupts();
1491 #ifdef _ARM_DS5_C_S32ZE_
1492 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1493 #endif
1494 }
1495 msr_ICU_EXCLUSIVE_AREA_31[u32CoreId] = msr;
1496 }
1497 reentry_guard_ICU_EXCLUSIVE_AREA_31[u32CoreId]++;
1498 }
1499
SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_31(void)1500 void SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_31(void)
1501 {
1502 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1503
1504 reentry_guard_ICU_EXCLUSIVE_AREA_31[u32CoreId]--;
1505 if ((ISR_ON(msr_ICU_EXCLUSIVE_AREA_31[u32CoreId]))&&(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_31[u32CoreId])) /*if interrupts were enabled*/
1506 {
1507 OsIf_ResumeAllInterrupts();
1508 #ifdef _ARM_DS5_C_S32ZE_
1509 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1510 #endif
1511 }
1512 }
1513
SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_32(void)1514 void SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_32(void)
1515 {
1516 uint32 msr;
1517 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1518
1519 if(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_32[u32CoreId])
1520 {
1521 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1522 msr = OsIf_Trusted_Call_Return(Icu_schm_read_msr);
1523 #else
1524 msr = Icu_schm_read_msr(); /*read MSR (to store interrupts state)*/
1525 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1526 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1527 {
1528 OsIf_SuspendAllInterrupts();
1529 #ifdef _ARM_DS5_C_S32ZE_
1530 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1531 #endif
1532 }
1533 msr_ICU_EXCLUSIVE_AREA_32[u32CoreId] = msr;
1534 }
1535 reentry_guard_ICU_EXCLUSIVE_AREA_32[u32CoreId]++;
1536 }
1537
SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_32(void)1538 void SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_32(void)
1539 {
1540 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1541
1542 reentry_guard_ICU_EXCLUSIVE_AREA_32[u32CoreId]--;
1543 if ((ISR_ON(msr_ICU_EXCLUSIVE_AREA_32[u32CoreId]))&&(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_32[u32CoreId])) /*if interrupts were enabled*/
1544 {
1545 OsIf_ResumeAllInterrupts();
1546 #ifdef _ARM_DS5_C_S32ZE_
1547 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1548 #endif
1549 }
1550 }
1551
SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_33(void)1552 void SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_33(void)
1553 {
1554 uint32 msr;
1555 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1556
1557 if(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_33[u32CoreId])
1558 {
1559 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1560 msr = OsIf_Trusted_Call_Return(Icu_schm_read_msr);
1561 #else
1562 msr = Icu_schm_read_msr(); /*read MSR (to store interrupts state)*/
1563 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1564 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1565 {
1566 OsIf_SuspendAllInterrupts();
1567 #ifdef _ARM_DS5_C_S32ZE_
1568 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1569 #endif
1570 }
1571 msr_ICU_EXCLUSIVE_AREA_33[u32CoreId] = msr;
1572 }
1573 reentry_guard_ICU_EXCLUSIVE_AREA_33[u32CoreId]++;
1574 }
1575
SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_33(void)1576 void SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_33(void)
1577 {
1578 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1579
1580 reentry_guard_ICU_EXCLUSIVE_AREA_33[u32CoreId]--;
1581 if ((ISR_ON(msr_ICU_EXCLUSIVE_AREA_33[u32CoreId]))&&(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_33[u32CoreId])) /*if interrupts were enabled*/
1582 {
1583 OsIf_ResumeAllInterrupts();
1584 #ifdef _ARM_DS5_C_S32ZE_
1585 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1586 #endif
1587 }
1588 }
1589
SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_44(void)1590 void SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_44(void)
1591 {
1592 uint32 msr;
1593 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1594
1595 if(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_44[u32CoreId])
1596 {
1597 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1598 msr = OsIf_Trusted_Call_Return(Icu_schm_read_msr);
1599 #else
1600 msr = Icu_schm_read_msr(); /*read MSR (to store interrupts state)*/
1601 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1602 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1603 {
1604 OsIf_SuspendAllInterrupts();
1605 #ifdef _ARM_DS5_C_S32ZE_
1606 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1607 #endif
1608 }
1609 msr_ICU_EXCLUSIVE_AREA_44[u32CoreId] = msr;
1610 }
1611 reentry_guard_ICU_EXCLUSIVE_AREA_44[u32CoreId]++;
1612 }
1613
SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_44(void)1614 void SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_44(void)
1615 {
1616 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1617
1618 reentry_guard_ICU_EXCLUSIVE_AREA_44[u32CoreId]--;
1619 if ((ISR_ON(msr_ICU_EXCLUSIVE_AREA_44[u32CoreId]))&&(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_44[u32CoreId])) /*if interrupts were enabled*/
1620 {
1621 OsIf_ResumeAllInterrupts();
1622 #ifdef _ARM_DS5_C_S32ZE_
1623 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1624 #endif
1625 }
1626 }
1627
SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_45(void)1628 void SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_45(void)
1629 {
1630 uint32 msr;
1631 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1632
1633 if(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_45[u32CoreId])
1634 {
1635 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1636 msr = OsIf_Trusted_Call_Return(Icu_schm_read_msr);
1637 #else
1638 msr = Icu_schm_read_msr(); /*read MSR (to store interrupts state)*/
1639 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1640 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1641 {
1642 OsIf_SuspendAllInterrupts();
1643 #ifdef _ARM_DS5_C_S32ZE_
1644 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1645 #endif
1646 }
1647 msr_ICU_EXCLUSIVE_AREA_45[u32CoreId] = msr;
1648 }
1649 reentry_guard_ICU_EXCLUSIVE_AREA_45[u32CoreId]++;
1650 }
1651
SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_45(void)1652 void SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_45(void)
1653 {
1654 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1655
1656 reentry_guard_ICU_EXCLUSIVE_AREA_45[u32CoreId]--;
1657 if ((ISR_ON(msr_ICU_EXCLUSIVE_AREA_45[u32CoreId]))&&(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_45[u32CoreId])) /*if interrupts were enabled*/
1658 {
1659 OsIf_ResumeAllInterrupts();
1660 #ifdef _ARM_DS5_C_S32ZE_
1661 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1662 #endif
1663 }
1664 }
1665
SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_46(void)1666 void SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_46(void)
1667 {
1668 uint32 msr;
1669 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1670
1671 if(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_46[u32CoreId])
1672 {
1673 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1674 msr = OsIf_Trusted_Call_Return(Icu_schm_read_msr);
1675 #else
1676 msr = Icu_schm_read_msr(); /*read MSR (to store interrupts state)*/
1677 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1678 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1679 {
1680 OsIf_SuspendAllInterrupts();
1681 #ifdef _ARM_DS5_C_S32ZE_
1682 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1683 #endif
1684 }
1685 msr_ICU_EXCLUSIVE_AREA_46[u32CoreId] = msr;
1686 }
1687 reentry_guard_ICU_EXCLUSIVE_AREA_46[u32CoreId]++;
1688 }
1689
SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_46(void)1690 void SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_46(void)
1691 {
1692 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1693
1694 reentry_guard_ICU_EXCLUSIVE_AREA_46[u32CoreId]--;
1695 if ((ISR_ON(msr_ICU_EXCLUSIVE_AREA_46[u32CoreId]))&&(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_46[u32CoreId])) /*if interrupts were enabled*/
1696 {
1697 OsIf_ResumeAllInterrupts();
1698 #ifdef _ARM_DS5_C_S32ZE_
1699 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1700 #endif
1701 }
1702 }
1703
SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_47(void)1704 void SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_47(void)
1705 {
1706 uint32 msr;
1707 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1708
1709 if(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_47[u32CoreId])
1710 {
1711 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1712 msr = OsIf_Trusted_Call_Return(Icu_schm_read_msr);
1713 #else
1714 msr = Icu_schm_read_msr(); /*read MSR (to store interrupts state)*/
1715 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1716 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1717 {
1718 OsIf_SuspendAllInterrupts();
1719 #ifdef _ARM_DS5_C_S32ZE_
1720 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1721 #endif
1722 }
1723 msr_ICU_EXCLUSIVE_AREA_47[u32CoreId] = msr;
1724 }
1725 reentry_guard_ICU_EXCLUSIVE_AREA_47[u32CoreId]++;
1726 }
1727
SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_47(void)1728 void SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_47(void)
1729 {
1730 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1731
1732 reentry_guard_ICU_EXCLUSIVE_AREA_47[u32CoreId]--;
1733 if ((ISR_ON(msr_ICU_EXCLUSIVE_AREA_47[u32CoreId]))&&(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_47[u32CoreId])) /*if interrupts were enabled*/
1734 {
1735 OsIf_ResumeAllInterrupts();
1736 #ifdef _ARM_DS5_C_S32ZE_
1737 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1738 #endif
1739 }
1740 }
1741
SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_48(void)1742 void SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_48(void)
1743 {
1744 uint32 msr;
1745 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1746
1747 if(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_48[u32CoreId])
1748 {
1749 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1750 msr = OsIf_Trusted_Call_Return(Icu_schm_read_msr);
1751 #else
1752 msr = Icu_schm_read_msr(); /*read MSR (to store interrupts state)*/
1753 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1754 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1755 {
1756 OsIf_SuspendAllInterrupts();
1757 #ifdef _ARM_DS5_C_S32ZE_
1758 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1759 #endif
1760 }
1761 msr_ICU_EXCLUSIVE_AREA_48[u32CoreId] = msr;
1762 }
1763 reentry_guard_ICU_EXCLUSIVE_AREA_48[u32CoreId]++;
1764 }
1765
SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_48(void)1766 void SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_48(void)
1767 {
1768 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1769
1770 reentry_guard_ICU_EXCLUSIVE_AREA_48[u32CoreId]--;
1771 if ((ISR_ON(msr_ICU_EXCLUSIVE_AREA_48[u32CoreId]))&&(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_48[u32CoreId])) /*if interrupts were enabled*/
1772 {
1773 OsIf_ResumeAllInterrupts();
1774 #ifdef _ARM_DS5_C_S32ZE_
1775 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1776 #endif
1777 }
1778 }
1779
SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_49(void)1780 void SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_49(void)
1781 {
1782 uint32 msr;
1783 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1784
1785 if(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_49[u32CoreId])
1786 {
1787 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1788 msr = OsIf_Trusted_Call_Return(Icu_schm_read_msr);
1789 #else
1790 msr = Icu_schm_read_msr(); /*read MSR (to store interrupts state)*/
1791 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1792 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1793 {
1794 OsIf_SuspendAllInterrupts();
1795 #ifdef _ARM_DS5_C_S32ZE_
1796 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1797 #endif
1798 }
1799 msr_ICU_EXCLUSIVE_AREA_49[u32CoreId] = msr;
1800 }
1801 reentry_guard_ICU_EXCLUSIVE_AREA_49[u32CoreId]++;
1802 }
1803
SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_49(void)1804 void SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_49(void)
1805 {
1806 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1807
1808 reentry_guard_ICU_EXCLUSIVE_AREA_49[u32CoreId]--;
1809 if ((ISR_ON(msr_ICU_EXCLUSIVE_AREA_49[u32CoreId]))&&(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_49[u32CoreId])) /*if interrupts were enabled*/
1810 {
1811 OsIf_ResumeAllInterrupts();
1812 #ifdef _ARM_DS5_C_S32ZE_
1813 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1814 #endif
1815 }
1816 }
1817
SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_50(void)1818 void SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_50(void)
1819 {
1820 uint32 msr;
1821 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1822
1823 if(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_50[u32CoreId])
1824 {
1825 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1826 msr = OsIf_Trusted_Call_Return(Icu_schm_read_msr);
1827 #else
1828 msr = Icu_schm_read_msr(); /*read MSR (to store interrupts state)*/
1829 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1830 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1831 {
1832 OsIf_SuspendAllInterrupts();
1833 #ifdef _ARM_DS5_C_S32ZE_
1834 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1835 #endif
1836 }
1837 msr_ICU_EXCLUSIVE_AREA_50[u32CoreId] = msr;
1838 }
1839 reentry_guard_ICU_EXCLUSIVE_AREA_50[u32CoreId]++;
1840 }
1841
SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_50(void)1842 void SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_50(void)
1843 {
1844 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1845
1846 reentry_guard_ICU_EXCLUSIVE_AREA_50[u32CoreId]--;
1847 if ((ISR_ON(msr_ICU_EXCLUSIVE_AREA_50[u32CoreId]))&&(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_50[u32CoreId])) /*if interrupts were enabled*/
1848 {
1849 OsIf_ResumeAllInterrupts();
1850 #ifdef _ARM_DS5_C_S32ZE_
1851 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1852 #endif
1853 }
1854 }
1855
SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_51(void)1856 void SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_51(void)
1857 {
1858 uint32 msr;
1859 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1860
1861 if(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_51[u32CoreId])
1862 {
1863 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1864 msr = OsIf_Trusted_Call_Return(Icu_schm_read_msr);
1865 #else
1866 msr = Icu_schm_read_msr(); /*read MSR (to store interrupts state)*/
1867 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1868 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1869 {
1870 OsIf_SuspendAllInterrupts();
1871 #ifdef _ARM_DS5_C_S32ZE_
1872 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1873 #endif
1874 }
1875 msr_ICU_EXCLUSIVE_AREA_51[u32CoreId] = msr;
1876 }
1877 reentry_guard_ICU_EXCLUSIVE_AREA_51[u32CoreId]++;
1878 }
1879
SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_51(void)1880 void SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_51(void)
1881 {
1882 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1883
1884 reentry_guard_ICU_EXCLUSIVE_AREA_51[u32CoreId]--;
1885 if ((ISR_ON(msr_ICU_EXCLUSIVE_AREA_51[u32CoreId]))&&(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_51[u32CoreId])) /*if interrupts were enabled*/
1886 {
1887 OsIf_ResumeAllInterrupts();
1888 #ifdef _ARM_DS5_C_S32ZE_
1889 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1890 #endif
1891 }
1892 }
1893
SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_52(void)1894 void SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_52(void)
1895 {
1896 uint32 msr;
1897 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1898
1899 if(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_52[u32CoreId])
1900 {
1901 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1902 msr = OsIf_Trusted_Call_Return(Icu_schm_read_msr);
1903 #else
1904 msr = Icu_schm_read_msr(); /*read MSR (to store interrupts state)*/
1905 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1906 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1907 {
1908 OsIf_SuspendAllInterrupts();
1909 #ifdef _ARM_DS5_C_S32ZE_
1910 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1911 #endif
1912 }
1913 msr_ICU_EXCLUSIVE_AREA_52[u32CoreId] = msr;
1914 }
1915 reentry_guard_ICU_EXCLUSIVE_AREA_52[u32CoreId]++;
1916 }
1917
SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_52(void)1918 void SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_52(void)
1919 {
1920 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1921
1922 reentry_guard_ICU_EXCLUSIVE_AREA_52[u32CoreId]--;
1923 if ((ISR_ON(msr_ICU_EXCLUSIVE_AREA_52[u32CoreId]))&&(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_52[u32CoreId])) /*if interrupts were enabled*/
1924 {
1925 OsIf_ResumeAllInterrupts();
1926 #ifdef _ARM_DS5_C_S32ZE_
1927 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1928 #endif
1929 }
1930 }
1931
SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_53(void)1932 void SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_53(void)
1933 {
1934 uint32 msr;
1935 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1936
1937 if(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_53[u32CoreId])
1938 {
1939 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1940 msr = OsIf_Trusted_Call_Return(Icu_schm_read_msr);
1941 #else
1942 msr = Icu_schm_read_msr(); /*read MSR (to store interrupts state)*/
1943 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1944 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1945 {
1946 OsIf_SuspendAllInterrupts();
1947 #ifdef _ARM_DS5_C_S32ZE_
1948 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1949 #endif
1950 }
1951 msr_ICU_EXCLUSIVE_AREA_53[u32CoreId] = msr;
1952 }
1953 reentry_guard_ICU_EXCLUSIVE_AREA_53[u32CoreId]++;
1954 }
1955
SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_53(void)1956 void SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_53(void)
1957 {
1958 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1959
1960 reentry_guard_ICU_EXCLUSIVE_AREA_53[u32CoreId]--;
1961 if ((ISR_ON(msr_ICU_EXCLUSIVE_AREA_53[u32CoreId]))&&(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_53[u32CoreId])) /*if interrupts were enabled*/
1962 {
1963 OsIf_ResumeAllInterrupts();
1964 #ifdef _ARM_DS5_C_S32ZE_
1965 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1966 #endif
1967 }
1968 }
1969
SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_57(void)1970 void SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_57(void)
1971 {
1972 uint32 msr;
1973 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1974
1975 if(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_57[u32CoreId])
1976 {
1977 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
1978 msr = OsIf_Trusted_Call_Return(Icu_schm_read_msr);
1979 #else
1980 msr = Icu_schm_read_msr(); /*read MSR (to store interrupts state)*/
1981 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
1982 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
1983 {
1984 OsIf_SuspendAllInterrupts();
1985 #ifdef _ARM_DS5_C_S32ZE_
1986 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
1987 #endif
1988 }
1989 msr_ICU_EXCLUSIVE_AREA_57[u32CoreId] = msr;
1990 }
1991 reentry_guard_ICU_EXCLUSIVE_AREA_57[u32CoreId]++;
1992 }
1993
SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_57(void)1994 void SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_57(void)
1995 {
1996 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
1997
1998 reentry_guard_ICU_EXCLUSIVE_AREA_57[u32CoreId]--;
1999 if ((ISR_ON(msr_ICU_EXCLUSIVE_AREA_57[u32CoreId]))&&(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_57[u32CoreId])) /*if interrupts were enabled*/
2000 {
2001 OsIf_ResumeAllInterrupts();
2002 #ifdef _ARM_DS5_C_S32ZE_
2003 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2004 #endif
2005 }
2006 }
2007
SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_58(void)2008 void SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_58(void)
2009 {
2010 uint32 msr;
2011 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2012
2013 if(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_58[u32CoreId])
2014 {
2015 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
2016 msr = OsIf_Trusted_Call_Return(Icu_schm_read_msr);
2017 #else
2018 msr = Icu_schm_read_msr(); /*read MSR (to store interrupts state)*/
2019 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
2020 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
2021 {
2022 OsIf_SuspendAllInterrupts();
2023 #ifdef _ARM_DS5_C_S32ZE_
2024 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2025 #endif
2026 }
2027 msr_ICU_EXCLUSIVE_AREA_58[u32CoreId] = msr;
2028 }
2029 reentry_guard_ICU_EXCLUSIVE_AREA_58[u32CoreId]++;
2030 }
2031
SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_58(void)2032 void SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_58(void)
2033 {
2034 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2035
2036 reentry_guard_ICU_EXCLUSIVE_AREA_58[u32CoreId]--;
2037 if ((ISR_ON(msr_ICU_EXCLUSIVE_AREA_58[u32CoreId]))&&(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_58[u32CoreId])) /*if interrupts were enabled*/
2038 {
2039 OsIf_ResumeAllInterrupts();
2040 #ifdef _ARM_DS5_C_S32ZE_
2041 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2042 #endif
2043 }
2044 }
2045
SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_59(void)2046 void SchM_Enter_Icu_ICU_EXCLUSIVE_AREA_59(void)
2047 {
2048 uint32 msr;
2049 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2050
2051 if(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_59[u32CoreId])
2052 {
2053 #if (defined MCAL_ENABLE_USER_MODE_SUPPORT)
2054 msr = OsIf_Trusted_Call_Return(Icu_schm_read_msr);
2055 #else
2056 msr = Icu_schm_read_msr(); /*read MSR (to store interrupts state)*/
2057 #endif /* MCAL_ENABLE_USER_MODE_SUPPORT */
2058 if (ISR_ON(msr)) /*if MSR[EE] = 0, skip calling Suspend/Resume AllInterrupts*/
2059 {
2060 OsIf_SuspendAllInterrupts();
2061 #ifdef _ARM_DS5_C_S32ZE_
2062 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2063 #endif
2064 }
2065 msr_ICU_EXCLUSIVE_AREA_59[u32CoreId] = msr;
2066 }
2067 reentry_guard_ICU_EXCLUSIVE_AREA_59[u32CoreId]++;
2068 }
2069
SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_59(void)2070 void SchM_Exit_Icu_ICU_EXCLUSIVE_AREA_59(void)
2071 {
2072 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2073
2074 reentry_guard_ICU_EXCLUSIVE_AREA_59[u32CoreId]--;
2075 if ((ISR_ON(msr_ICU_EXCLUSIVE_AREA_59[u32CoreId]))&&(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_59[u32CoreId])) /*if interrupts were enabled*/
2076 {
2077 OsIf_ResumeAllInterrupts();
2078 #ifdef _ARM_DS5_C_S32ZE_
2079 ASM_KEYWORD(" nop ");/* Compiler fix - forces the CSPID instruction to be generated with -02, -Ospace are selected*/
2080 #endif
2081 }
2082 }
2083
2084
2085 #ifdef MCAL_TESTING_ENVIRONMENT
2086 /**
2087 @brief This function checks that all entered exclusive areas were also exited.
2088 @details This function checks that all entered exclusive areas were also exited. The check
2089 is done by verifying that all reentry_guard_* static variables are back to the
2090 zero value.
2091
2092 @param[in] void No input parameters
2093 @return void This function does not return a value. Test asserts are used instead.
2094
2095 @pre None
2096 @post None
2097
2098 @remarks Covers
2099 @remarks Implements
2100 */
SchM_Check_icu(void)2101 void SchM_Check_icu(void)
2102 {
2103 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
2104
2105 EU_ASSERT(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_00[u32CoreId]);
2106 reentry_guard_ICU_EXCLUSIVE_AREA_00[u32CoreId] = 0UL; /*reset reentry_guard_ICU_EXCLUSIVE_AREA_00 for the next test in the suite*/
2107
2108 EU_ASSERT(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_01[u32CoreId]);
2109 reentry_guard_ICU_EXCLUSIVE_AREA_01[u32CoreId] = 0UL; /*reset reentry_guard_ICU_EXCLUSIVE_AREA_01 for the next test in the suite*/
2110
2111 EU_ASSERT(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_02[u32CoreId]);
2112 reentry_guard_ICU_EXCLUSIVE_AREA_02[u32CoreId] = 0UL; /*reset reentry_guard_ICU_EXCLUSIVE_AREA_02 for the next test in the suite*/
2113
2114 EU_ASSERT(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_03[u32CoreId]);
2115 reentry_guard_ICU_EXCLUSIVE_AREA_03[u32CoreId] = 0UL; /*reset reentry_guard_ICU_EXCLUSIVE_AREA_03 for the next test in the suite*/
2116
2117 EU_ASSERT(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_04[u32CoreId]);
2118 reentry_guard_ICU_EXCLUSIVE_AREA_04[u32CoreId] = 0UL; /*reset reentry_guard_ICU_EXCLUSIVE_AREA_04 for the next test in the suite*/
2119
2120 EU_ASSERT(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_05[u32CoreId]);
2121 reentry_guard_ICU_EXCLUSIVE_AREA_05[u32CoreId] = 0UL; /*reset reentry_guard_ICU_EXCLUSIVE_AREA_05 for the next test in the suite*/
2122
2123 EU_ASSERT(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_06[u32CoreId]);
2124 reentry_guard_ICU_EXCLUSIVE_AREA_06[u32CoreId] = 0UL; /*reset reentry_guard_ICU_EXCLUSIVE_AREA_06 for the next test in the suite*/
2125
2126 EU_ASSERT(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_07[u32CoreId]);
2127 reentry_guard_ICU_EXCLUSIVE_AREA_07[u32CoreId] = 0UL; /*reset reentry_guard_ICU_EXCLUSIVE_AREA_07 for the next test in the suite*/
2128
2129 EU_ASSERT(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_08[u32CoreId]);
2130 reentry_guard_ICU_EXCLUSIVE_AREA_08[u32CoreId] = 0UL; /*reset reentry_guard_ICU_EXCLUSIVE_AREA_08 for the next test in the suite*/
2131
2132 EU_ASSERT(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_09[u32CoreId]);
2133 reentry_guard_ICU_EXCLUSIVE_AREA_09[u32CoreId] = 0UL; /*reset reentry_guard_ICU_EXCLUSIVE_AREA_09 for the next test in the suite*/
2134
2135 EU_ASSERT(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_11[u32CoreId]);
2136 reentry_guard_ICU_EXCLUSIVE_AREA_11[u32CoreId] = 0UL; /*reset reentry_guard_ICU_EXCLUSIVE_AREA_11 for the next test in the suite*/
2137
2138 EU_ASSERT(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_15[u32CoreId]);
2139 reentry_guard_ICU_EXCLUSIVE_AREA_15[u32CoreId] = 0UL; /*reset reentry_guard_ICU_EXCLUSIVE_AREA_15 for the next test in the suite*/
2140
2141 EU_ASSERT(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_16[u32CoreId]);
2142 reentry_guard_ICU_EXCLUSIVE_AREA_16[u32CoreId] = 0UL; /*reset reentry_guard_ICU_EXCLUSIVE_AREA_16 for the next test in the suite*/
2143
2144 EU_ASSERT(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_17[u32CoreId]);
2145 reentry_guard_ICU_EXCLUSIVE_AREA_17[u32CoreId] = 0UL; /*reset reentry_guard_ICU_EXCLUSIVE_AREA_17 for the next test in the suite*/
2146
2147 EU_ASSERT(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_18[u32CoreId]);
2148 reentry_guard_ICU_EXCLUSIVE_AREA_18[u32CoreId] = 0UL; /*reset reentry_guard_ICU_EXCLUSIVE_AREA_18 for the next test in the suite*/
2149
2150 EU_ASSERT(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_19[u32CoreId]);
2151 reentry_guard_ICU_EXCLUSIVE_AREA_19[u32CoreId] = 0UL; /*reset reentry_guard_ICU_EXCLUSIVE_AREA_19 for the next test in the suite*/
2152
2153 EU_ASSERT(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_20[u32CoreId]);
2154 reentry_guard_ICU_EXCLUSIVE_AREA_20[u32CoreId] = 0UL; /*reset reentry_guard_ICU_EXCLUSIVE_AREA_20 for the next test in the suite*/
2155
2156 EU_ASSERT(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_21[u32CoreId]);
2157 reentry_guard_ICU_EXCLUSIVE_AREA_21[u32CoreId] = 0UL; /*reset reentry_guard_ICU_EXCLUSIVE_AREA_21 for the next test in the suite*/
2158
2159 EU_ASSERT(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_22[u32CoreId]);
2160 reentry_guard_ICU_EXCLUSIVE_AREA_22[u32CoreId] = 0UL; /*reset reentry_guard_ICU_EXCLUSIVE_AREA_22 for the next test in the suite*/
2161
2162 EU_ASSERT(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_23[u32CoreId]);
2163 reentry_guard_ICU_EXCLUSIVE_AREA_23[u32CoreId] = 0UL; /*reset reentry_guard_ICU_EXCLUSIVE_AREA_23 for the next test in the suite*/
2164
2165 EU_ASSERT(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_24[u32CoreId]);
2166 reentry_guard_ICU_EXCLUSIVE_AREA_24[u32CoreId] = 0UL; /*reset reentry_guard_ICU_EXCLUSIVE_AREA_24 for the next test in the suite*/
2167
2168 EU_ASSERT(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_25[u32CoreId]);
2169 reentry_guard_ICU_EXCLUSIVE_AREA_25[u32CoreId] = 0UL; /*reset reentry_guard_ICU_EXCLUSIVE_AREA_25 for the next test in the suite*/
2170
2171 EU_ASSERT(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_26[u32CoreId]);
2172 reentry_guard_ICU_EXCLUSIVE_AREA_26[u32CoreId] = 0UL; /*reset reentry_guard_ICU_EXCLUSIVE_AREA_26 for the next test in the suite*/
2173
2174 EU_ASSERT(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_27[u32CoreId]);
2175 reentry_guard_ICU_EXCLUSIVE_AREA_27[u32CoreId] = 0UL; /*reset reentry_guard_ICU_EXCLUSIVE_AREA_27 for the next test in the suite*/
2176
2177 EU_ASSERT(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_28[u32CoreId]);
2178 reentry_guard_ICU_EXCLUSIVE_AREA_28[u32CoreId] = 0UL; /*reset reentry_guard_ICU_EXCLUSIVE_AREA_28 for the next test in the suite*/
2179
2180 EU_ASSERT(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_29[u32CoreId]);
2181 reentry_guard_ICU_EXCLUSIVE_AREA_29[u32CoreId] = 0UL; /*reset reentry_guard_ICU_EXCLUSIVE_AREA_29 for the next test in the suite*/
2182
2183 EU_ASSERT(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_30[u32CoreId]);
2184 reentry_guard_ICU_EXCLUSIVE_AREA_30[u32CoreId] = 0UL; /*reset reentry_guard_ICU_EXCLUSIVE_AREA_30 for the next test in the suite*/
2185
2186 EU_ASSERT(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_31[u32CoreId]);
2187 reentry_guard_ICU_EXCLUSIVE_AREA_31[u32CoreId] = 0UL; /*reset reentry_guard_ICU_EXCLUSIVE_AREA_31 for the next test in the suite*/
2188
2189 EU_ASSERT(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_32[u32CoreId]);
2190 reentry_guard_ICU_EXCLUSIVE_AREA_32[u32CoreId] = 0UL; /*reset reentry_guard_ICU_EXCLUSIVE_AREA_32 for the next test in the suite*/
2191
2192 EU_ASSERT(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_33[u32CoreId]);
2193 reentry_guard_ICU_EXCLUSIVE_AREA_33[u32CoreId] = 0UL; /*reset reentry_guard_ICU_EXCLUSIVE_AREA_33 for the next test in the suite*/
2194
2195 EU_ASSERT(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_44[u32CoreId]);
2196 reentry_guard_ICU_EXCLUSIVE_AREA_44[u32CoreId] = 0UL; /*reset reentry_guard_ICU_EXCLUSIVE_AREA_44 for the next test in the suite*/
2197
2198 EU_ASSERT(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_45[u32CoreId]);
2199 reentry_guard_ICU_EXCLUSIVE_AREA_45[u32CoreId] = 0UL; /*reset reentry_guard_ICU_EXCLUSIVE_AREA_45 for the next test in the suite*/
2200
2201 EU_ASSERT(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_46[u32CoreId]);
2202 reentry_guard_ICU_EXCLUSIVE_AREA_46[u32CoreId] = 0UL; /*reset reentry_guard_ICU_EXCLUSIVE_AREA_46 for the next test in the suite*/
2203
2204 EU_ASSERT(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_47[u32CoreId]);
2205 reentry_guard_ICU_EXCLUSIVE_AREA_47[u32CoreId] = 0UL; /*reset reentry_guard_ICU_EXCLUSIVE_AREA_47 for the next test in the suite*/
2206
2207 EU_ASSERT(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_48[u32CoreId]);
2208 reentry_guard_ICU_EXCLUSIVE_AREA_48[u32CoreId] = 0UL; /*reset reentry_guard_ICU_EXCLUSIVE_AREA_48 for the next test in the suite*/
2209
2210 EU_ASSERT(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_49[u32CoreId]);
2211 reentry_guard_ICU_EXCLUSIVE_AREA_49[u32CoreId] = 0UL; /*reset reentry_guard_ICU_EXCLUSIVE_AREA_49 for the next test in the suite*/
2212
2213 EU_ASSERT(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_50[u32CoreId]);
2214 reentry_guard_ICU_EXCLUSIVE_AREA_50[u32CoreId] = 0UL; /*reset reentry_guard_ICU_EXCLUSIVE_AREA_50 for the next test in the suite*/
2215
2216 EU_ASSERT(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_51[u32CoreId]);
2217 reentry_guard_ICU_EXCLUSIVE_AREA_51[u32CoreId] = 0UL; /*reset reentry_guard_ICU_EXCLUSIVE_AREA_51 for the next test in the suite*/
2218
2219 EU_ASSERT(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_52[u32CoreId]);
2220 reentry_guard_ICU_EXCLUSIVE_AREA_52[u32CoreId] = 0UL; /*reset reentry_guard_ICU_EXCLUSIVE_AREA_52 for the next test in the suite*/
2221
2222 EU_ASSERT(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_53[u32CoreId]);
2223 reentry_guard_ICU_EXCLUSIVE_AREA_53[u32CoreId] = 0UL; /*reset reentry_guard_ICU_EXCLUSIVE_AREA_53 for the next test in the suite*/
2224
2225 EU_ASSERT(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_57[u32CoreId]);
2226 reentry_guard_ICU_EXCLUSIVE_AREA_57[u32CoreId] = 0UL; /*reset reentry_guard_ICU_EXCLUSIVE_AREA_57 for the next test in the suite*/
2227
2228 EU_ASSERT(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_58[u32CoreId]);
2229 reentry_guard_ICU_EXCLUSIVE_AREA_58[u32CoreId] = 0UL; /*reset reentry_guard_ICU_EXCLUSIVE_AREA_58 for the next test in the suite*/
2230
2231 EU_ASSERT(0UL == reentry_guard_ICU_EXCLUSIVE_AREA_59[u32CoreId]);
2232 reentry_guard_ICU_EXCLUSIVE_AREA_59[u32CoreId] = 0UL; /*reset reentry_guard_ICU_EXCLUSIVE_AREA_59 for the next test in the suite*/
2233
2234
2235 }
2236 #endif /*MCAL_TESTING_ENVIRONMENT*/
2237
2238 #define RTE_STOP_SEC_CODE
2239 #include "Rte_MemMap.h"
2240
2241 #ifdef __cplusplus
2242 }
2243 #endif
2244
2245 /** @} */
2246
