1 /*
2  * Copyright 2021-2023 NXP
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 /**
7 *   @file       Clock_Ip_Specific.c
8 *   @version    1.0.0
9 *
10 *   @brief   CLOCK driver implementations.
11 *   @details CLOCK driver implementations.
12 *
13 *   @addtogroup CLOCK_DRIVER Clock Ip Driver
14 *   @{
15 */
16 
17 #ifdef __cplusplus
18 extern "C"{
19 #endif
20 
21 
22 /*==================================================================================================
23 *                                          INCLUDE FILES
24 * 1) system and project includes
25 * 2) needed interfaces from external units
26 * 3) internal and external interfaces from this unit
27 ==================================================================================================*/
28 
29 
30 
31 #include "Clock_Ip_Private.h"
32 
33 #if (defined(CLOCK_IP_ENABLE_USER_MODE_SUPPORT))
34   #if (STD_ON == CLOCK_IP_ENABLE_USER_MODE_SUPPORT)
35     #define USER_MODE_REG_PROT_ENABLED      (STD_ON)
36     #include "RegLockMacros.h"
37   #endif
38 #endif /* CLOCK_IP_ENABLE_USER_MODE_SUPPORT */
39 
40 /*==================================================================================================
41                                SOURCE FILE VERSION INFORMATION
42 ==================================================================================================*/
43 #define CLOCK_IP_SPECIFIC_VENDOR_ID_C                      43
44 #define CLOCK_IP_SPECIFIC_AR_RELEASE_MAJOR_VERSION_C       4
45 #define CLOCK_IP_SPECIFIC_AR_RELEASE_MINOR_VERSION_C       7
46 #define CLOCK_IP_SPECIFIC_AR_RELEASE_REVISION_VERSION_C    0
47 #define CLOCK_IP_SPECIFIC_SW_MAJOR_VERSION_C               1
48 #define CLOCK_IP_SPECIFIC_SW_MINOR_VERSION_C               0
49 #define CLOCK_IP_SPECIFIC_SW_PATCH_VERSION_C               0
50 
51 /*==================================================================================================
52 *                                     FILE VERSION CHECKS
53 ==================================================================================================*/
54 /* Check if Clock_Ip_Specific.c file and Clock_Ip_Private.h file are of the same vendor */
55 #if (CLOCK_IP_SPECIFIC_VENDOR_ID_C != CLOCK_IP_PRIVATE_VENDOR_ID)
56     #error "Clock_Ip_Specific.c and Clock_Ip_Private.h have different vendor ids"
57 #endif
58 
59 /* Check if Clock_Ip_Specific.c file and Clock_Ip_Private.h file are of the same Autosar version */
60 #if ((CLOCK_IP_SPECIFIC_AR_RELEASE_MAJOR_VERSION_C != CLOCK_IP_PRIVATE_AR_RELEASE_MAJOR_VERSION) || \
61      (CLOCK_IP_SPECIFIC_AR_RELEASE_MINOR_VERSION_C != CLOCK_IP_PRIVATE_AR_RELEASE_MINOR_VERSION) || \
62      (CLOCK_IP_SPECIFIC_AR_RELEASE_REVISION_VERSION_C != CLOCK_IP_PRIVATE_AR_RELEASE_REVISION_VERSION) \
63     )
64     #error "AutoSar Version Numbers of Clock_Ip_Specific.c and Clock_Ip_Private.h are different"
65 #endif
66 
67 /* Check if Clock_Ip_Specific.c file and Clock_Ip_Private.h file are of the same Software version */
68 #if ((CLOCK_IP_SPECIFIC_SW_MAJOR_VERSION_C != CLOCK_IP_PRIVATE_SW_MAJOR_VERSION) || \
69      (CLOCK_IP_SPECIFIC_SW_MINOR_VERSION_C != CLOCK_IP_PRIVATE_SW_MINOR_VERSION) || \
70      (CLOCK_IP_SPECIFIC_SW_PATCH_VERSION_C != CLOCK_IP_PRIVATE_SW_PATCH_VERSION) \
71     )
72     #error "Software Version Numbers of Clock_Ip_Specific.c and Clock_Ip_Private.h are different"
73 #endif
74 
75 #if (defined(CLOCK_IP_ENABLE_USER_MODE_SUPPORT))
76   #if (STD_ON == CLOCK_IP_ENABLE_USER_MODE_SUPPORT)
77     #ifndef DISABLE_MCAL_INTERMODULE_ASR_CHECK
78     /* Check if Clock_Ip_Specific.c file and RegLockMacros.h file are of the same Autosar version */
79     #if ((CLOCK_IP_SPECIFIC_AR_RELEASE_MAJOR_VERSION    != REGLOCKMACROS_AR_RELEASE_MAJOR_VERSION) || \
80         (CLOCK_IP_SPECIFIC_AR_RELEASE_MINOR_VERSION    != REGLOCKMACROS_AR_RELEASE_MINOR_VERSION))
81         #error "AutoSar Version Numbers of Clock_Ip_Specific.c and RegLockMacros.h are different"
82     #endif
83     #endif
84   #endif
85 #endif /* CLOCK_IP_ENABLE_USER_MODE_SUPPORT */
86 
87 
88 /*==================================================================================================
89                           LOCAL TYPEDEFS (STRUCTURES, UNIONS, ENUMS)
90 ==================================================================================================*/
91 
92 /*==================================================================================================
93 *                                       LOCAL MACROS
94 ==================================================================================================*/
95 
96 #define DFS_DVPORT      (DFS_DVPORT_MFN(0u) | DFS_DVPORT_MFI(1U))
97 #define DFS_PORT_RESET  (DFS_PORTRESET_RESET0_MASK | DFS_PORTRESET_RESET1_MASK | DFS_PORTRESET_RESET2_MASK | DFS_PORTRESET_RESET3_MASK | DFS_PORTRESET_RESET4_MASK | DFS_PORTRESET_RESET5_MASK)
98 
99 #define RTU0_CORE_CLK_MAX_FREQUENCY 900000000U
100 #define RTU0_CORE_CLK_THRESHOLD0_FREQUENCY (RTU0_CORE_CLK_MAX_FREQUENCY>>2U)
101 #define RTU0_CORE_CLK_THRESHOLD1_FREQUENCY (RTU0_CORE_CLK_THRESHOLD0_FREQUENCY*(2U))
102 #define RTU0_CORE_CLK_THRESHOLD2_FREQUENCY (RTU0_CORE_CLK_THRESHOLD0_FREQUENCY*(3U))
103 
104 #define RTU1_CORE_CLK_MAX_FREQUENCY 900000000U
105 #define RTU1_CORE_CLK_THRESHOLD0_FREQUENCY (RTU1_CORE_CLK_MAX_FREQUENCY>>2U)
106 #define RTU1_CORE_CLK_THRESHOLD1_FREQUENCY (RTU1_CORE_CLK_THRESHOLD0_FREQUENCY*(2U))
107 #define RTU1_CORE_CLK_THRESHOLD2_FREQUENCY (RTU1_CORE_CLK_THRESHOLD0_FREQUENCY*(3U))
108 
109 #define SMU_M33_CORE_CLK_MAX_FREQUENCY 400000000U
110 #define SMU_M33_CORE_CLK_THRESHOLD0_FREQUENCY (SMU_M33_CORE_CLK_MAX_FREQUENCY>>2U)
111 #define SMU_M33_CORE_CLK_THRESHOLD1_FREQUENCY (SMU_M33_CORE_CLK_THRESHOLD0_FREQUENCY*(2U))
112 #define SMU_M33_CORE_CLK_THRESHOLD2_FREQUENCY (SMU_M33_CORE_CLK_THRESHOLD0_FREQUENCY*(3U))
113 
114 #define CE_M33_CORE_CLK_MAX_FREQUENCY 405000000U
115 #define CE_M33_CORE_CLK_THRESHOLD0_FREQUENCY (CE_M33_CORE_CLK_MAX_FREQUENCY>>2U)
116 #define CE_M33_CORE_CLK_THRESHOLD1_FREQUENCY (CE_M33_CORE_CLK_THRESHOLD0_FREQUENCY*(2U))
117 #define CE_M33_CORE_CLK_THRESHOLD2_FREQUENCY (CE_M33_CORE_CLK_THRESHOLD0_FREQUENCY*(3U))
118 
119 
120 /*==================================================================================================
121                                        LOCAL CONSTANTS
122 ==================================================================================================*/
123 
124 /*==================================================================================================
125                                        LOCAL VARIABLES
126 ==================================================================================================*/
127 
128 
129 /*==================================================================================================
130                                        GLOBAL CONSTANTS
131 ==================================================================================================*/
132 
133 
134 /*==================================================================================================
135                                        GLOBAL VARIABLES
136 ==================================================================================================*/
137 
138 /*==================================================================================================
139                                    LOCAL FUNCTION PROTOTYPES
140 ==================================================================================================*/
141 /* Clock start section code */
142 #define MCU_START_SEC_CODE
143 #include "Mcu_MemMap.h"
144 
145 #if (defined(CLOCK_IP_ENABLE_USER_MODE_SUPPORT))
146   #if (STD_ON == CLOCK_IP_ENABLE_USER_MODE_SUPPORT)
147     #if (defined(CLOCK_IP_HAS_SYSTEM_DIV2_CLK) || defined(CLOCK_IP_HAS_SYSTEM_DIV4_MON1_CLK) || defined(CLOCK_IP_HAS_SYSTEM_DIV4_MON2_CLK))
148 void Clock_Ip_SpecificSetUserAccessAllowed(void);
149     #endif /* (defined(CLOCK_IP_HAS_SYSTEM_DIV2_CLK) || defined(CLOCK_IP_HAS_SYSTEM_DIV4_MON1_CLK) || defined(CLOCK_IP_HAS_SYSTEM_DIV4_MON2_CLK)) */
150   #endif
151 #endif /* CLOCK_IP_ENABLE_USER_MODE_SUPPORT */
152 
153 #ifdef CLOCK_IP_HAS_RAM_WAIT_STATES
154 
155 void SRAMController_SetRamIWS(uint32 SmuM33CoreClk_IwsSetting, uint32 Rtu0CoreClk_IwsSetting, uint32 Rtu1CoreClk_IwsSetting, uint32 CeM33CoreClk_IwsSetting);
156 
157 /*==================================================================================================
158                                        LOCAL FUNCTIONS
159 ==================================================================================================*/
160 
161 
162 /* Calculate ram wait states value */
Clock_Ip_GetIwsSetting(uint32 ConfiguredCoreClockFrequnecy,uint32 Threshold0,uint32 Threshold1,uint32 Threshold2)163 static uint32 Clock_Ip_GetIwsSetting(uint32 ConfiguredCoreClockFrequnecy, uint32 Threshold0, uint32 Threshold1, uint32 Threshold2)
164 {
165     uint32 IwsSetting = 0U;
166 
167     if (ConfiguredCoreClockFrequnecy >= Threshold2)
168     {
169         IwsSetting = 3U;
170     }
171     else if (ConfiguredCoreClockFrequnecy >= Threshold1)
172     {
173         IwsSetting = 2U;
174     }
175     else if (ConfiguredCoreClockFrequnecy >= Threshold0)
176     {
177         IwsSetting = 1U;
178     }
179     else
180     {
181         /* Nothing else to be done. */
182     }
183 
184     return IwsSetting;
185 }
186 
187 
188 /* Function set ram wait states */
Clock_Ip_SetRamWaitStates(void)189 void Clock_Ip_SetRamWaitStates(void)
190 {
191    /* Process configured frequency values */
192     uint32 Rtu0CoreClk_IwsSetting = 0U;
193     uint32 Rtu0CoreClk_ConfiguredFrequency = 0U;
194 
195     uint32 Rtu1CoreClk_IwsSetting = 0U;
196     uint32 Rtu1CoreClk_ConfiguredFrequency = 0U;
197 
198     uint32 SmuM33CoreClk_IwsSetting = 0U;
199     uint32 SmuM33CoreClk_ConfiguredFrequency = 0U;
200 
201     uint32 CeM33CoreClk_IwsSetting = 0U;
202     uint32 CeM33CoreClk_ConfiguredFrequency = 0U;
203 
204 #if defined(CLOCK_IP_HAS_RTU0_CORE_CLK)
205     Rtu0CoreClk_ConfiguredFrequency = (*Clock_Ip_pxConfig->ConfiguredFrequencies)[Clock_Ip_FreqIds[RTU0_CORE_CLK]].ConfiguredFrequencyValue;
206 #endif
207 #if defined(CLOCK_IP_HAS_RTU1_CORE_CLK)
208     Rtu1CoreClk_ConfiguredFrequency = (*Clock_Ip_pxConfig->ConfiguredFrequencies)[Clock_Ip_FreqIds[RTU1_CORE_CLK]].ConfiguredFrequencyValue;
209 #endif
210 #if defined(CLOCK_IP_HAS_SMU_M33_CORE_CLK)
211     SmuM33CoreClk_ConfiguredFrequency = (*Clock_Ip_pxConfig->ConfiguredFrequencies)[Clock_Ip_FreqIds[SMU_M33_CORE_CLK]].ConfiguredFrequencyValue;
212 #endif
213 #if defined(CLOCK_IP_HAS_CE_M33_CORE_CLK)
214     CeM33CoreClk_ConfiguredFrequency = (*Clock_Ip_pxConfig->ConfiguredFrequencies)[Clock_Ip_FreqIds[CE_M33_CORE_CLK]].ConfiguredFrequencyValue;
215 #endif
216 
217 #if (defined(CLOCK_IP_DEV_ERROR_DETECT) && (CLOCK_IP_DEV_ERROR_DETECT == STD_ON))
218 #if defined(CLOCK_IP_HAS_RTU0_CORE_CLK)
219     CLOCK_IP_DEV_ASSERT(Rtu0CoreClk_ConfiguredFrequency != 0U);
220 #endif
221 #if defined(CLOCK_IP_HAS_RTU1_CORE_CLK)
222     CLOCK_IP_DEV_ASSERT(Rtu1CoreClk_ConfiguredFrequency != 0U);
223 #endif
224 #if defined(CLOCK_IP_HAS_SMU_M33_CORE_CLK)
225     CLOCK_IP_DEV_ASSERT(SmuM33CoreClk_ConfiguredFrequency != 0U);
226 #endif
227 #if defined(CLOCK_IP_HAS_CE_M33_CORE_CLK)
228     CLOCK_IP_DEV_ASSERT(CeM33CoreClk_ConfiguredFrequency != 0U);
229 #endif
230 #endif
231 
232     SmuM33CoreClk_IwsSetting = Clock_Ip_GetIwsSetting(SmuM33CoreClk_ConfiguredFrequency, SMU_M33_CORE_CLK_THRESHOLD0_FREQUENCY, SMU_M33_CORE_CLK_THRESHOLD1_FREQUENCY, SMU_M33_CORE_CLK_THRESHOLD2_FREQUENCY);
233     Rtu0CoreClk_IwsSetting = Clock_Ip_GetIwsSetting(Rtu0CoreClk_ConfiguredFrequency, RTU0_CORE_CLK_THRESHOLD0_FREQUENCY, RTU0_CORE_CLK_THRESHOLD1_FREQUENCY, RTU0_CORE_CLK_THRESHOLD2_FREQUENCY);
234     Rtu1CoreClk_IwsSetting = Clock_Ip_GetIwsSetting(Rtu1CoreClk_ConfiguredFrequency, RTU1_CORE_CLK_THRESHOLD0_FREQUENCY, RTU1_CORE_CLK_THRESHOLD1_FREQUENCY, RTU1_CORE_CLK_THRESHOLD2_FREQUENCY);
235     CeM33CoreClk_IwsSetting = Clock_Ip_GetIwsSetting(CeM33CoreClk_ConfiguredFrequency, CE_M33_CORE_CLK_THRESHOLD0_FREQUENCY, CE_M33_CORE_CLK_THRESHOLD1_FREQUENCY, CE_M33_CORE_CLK_THRESHOLD2_FREQUENCY);
236 
237     #ifdef CLOCK_IP_ENABLE_USER_MODE_SUPPORT
238         #if (STD_ON == CLOCK_IP_ENABLE_USER_MODE_SUPPORT)
239             OsIf_Trusted_Call4params(SRAMController_SetRamIWS, (SmuM33CoreClk_IwsSetting), (Rtu0CoreClk_IwsSetting), (Rtu1CoreClk_IwsSetting), (CeM33CoreClk_IwsSetting));
240         #else
241             SRAMController_SetRamIWS(SmuM33CoreClk_IwsSetting, Rtu0CoreClk_IwsSetting, Rtu1CoreClk_IwsSetting, CeM33CoreClk_IwsSetting);
242         #endif
243     #else
244         SRAMController_SetRamIWS(SmuM33CoreClk_IwsSetting, Rtu0CoreClk_IwsSetting, Rtu1CoreClk_IwsSetting, CeM33CoreClk_IwsSetting);
245     #endif
246 }
247 #endif
248 
Clock_Ip_SpecificPlatformInitClock(Clock_Ip_ClockConfigType const * Config)249 static void Clock_Ip_SpecificPlatformInitClock(Clock_Ip_ClockConfigType const * Config)
250 {
251     uint32 RegValue;
252     uint32 CoreDfsIsInReset = IP_CORE_DFS->CTL & DFS_CTL_DFS_RESET_MASK;            /* if master core dfs is in reset */
253     uint32 PeriphDfsIsInReset = IP_PERIPH_DFS->CTL & DFS_CTL_DFS_RESET_MASK;        /* if master periph dfs is in reset */
254 
255     (void)Config;
256 
257     if ((CoreDfsIsInReset != 0U) && (PeriphDfsIsInReset != 0U))
258     {
259         if ((IP_CORE_PLL->PLLCR & PLLDIG_PLLCR_PLLPD_MASK) != 0U)   /* if CORE_PLL is not enabled */
260         {
261             IP_CORE_PLL->PLLCLKMUX = 0U;                                                   /* FIRC input reference 48 MHz */
262             RegValue = IP_CORE_PLL->PLLDV;
263             RegValue &= ~(PLLDIG_PLLDV_RDIV_MASK | PLLDIG_PLLDV_MFI_MASK);
264             IP_CORE_PLL->PLLDV = (RegValue | (PLLDIG_PLLDV_RDIV(1U) | PLLDIG_PLLDV_MFI(30U)) );          /* /1 * 30 */
265 
266             IP_CORE_PLL->PLLFD &= ~(PLLDIG_PLLFD_MFN_MASK | PLLDIG_PLLFD_SDMEN_MASK);      /* Disable modulation */
267             IP_CORE_PLL->PLLCR &= ~PLLDIG_PLLCR_PLLPD_MASK;                                /* Start CORE_PLL */
268         }
269 
270         if ((IP_PERIPH_PLL->PLLCR & PLLDIG_PLLCR_PLLPD_MASK) != 0U)   /* if PERIPH_PLL is not enabled */
271         {
272             IP_PERIPH_PLL->PLLCLKMUX = 0U;                                                   /* FIRC input reference 48 MHz */
273             RegValue = IP_PERIPH_PLL->PLLDV;
274             RegValue &= ~(PLLDIG_PLLDV_RDIV_MASK | PLLDIG_PLLDV_MFI_MASK);
275             IP_PERIPH_PLL->PLLDV = (RegValue | (PLLDIG_PLLDV_RDIV(1U) | PLLDIG_PLLDV_MFI(30U)) );          /* /1 * 30 */
276 
277             IP_PERIPH_PLL->PLLFD &= ~(PLLDIG_PLLFD_MFN_MASK | PLLDIG_PLLFD_SDMEN_MASK);      /* Disable modulation */
278             IP_PERIPH_PLL->PLLCR &= ~PLLDIG_PLLCR_PLLPD_MASK;                                /* Start PERIPH_PLL */
279         }
280 
281         IP_CORE_DFS->PORTRESET |= DFS_PORT_RESET;
282         IP_CORE_DFS->DVPORT[0U] = DFS_DVPORT;
283         IP_CORE_DFS->DVPORT[1U] = DFS_DVPORT;
284         IP_CORE_DFS->DVPORT[2U] = DFS_DVPORT;
285         IP_CORE_DFS->DVPORT[3U] = DFS_DVPORT;
286         IP_CORE_DFS->DVPORT[4U] = DFS_DVPORT;
287         IP_CORE_DFS->DVPORT[5U] = DFS_DVPORT;
288         IP_CORE_DFS->CTL &= ~DFS_CTL_DFS_RESET_MASK;
289         IP_CORE_DFS->PORTRESET &= ~DFS_PORT_RESET;
290 
291         IP_PERIPH_DFS->PORTRESET |= DFS_PORT_RESET;
292         IP_PERIPH_DFS->DVPORT[0U] = DFS_DVPORT;
293         IP_PERIPH_DFS->DVPORT[1U] = DFS_DVPORT;
294         IP_PERIPH_DFS->DVPORT[2U] = DFS_DVPORT;
295         IP_PERIPH_DFS->DVPORT[3U] = DFS_DVPORT;
296         IP_PERIPH_DFS->DVPORT[4U] = DFS_DVPORT;
297         IP_PERIPH_DFS->DVPORT[5U] = DFS_DVPORT;
298         IP_PERIPH_DFS->CTL &= ~DFS_CTL_DFS_RESET_MASK;
299         IP_PERIPH_DFS->PORTRESET &= ~DFS_PORT_RESET;
300     }
301     else if (CoreDfsIsInReset != 0U)
302     {
303         if ((IP_CORE_PLL->PLLCR & PLLDIG_PLLCR_PLLPD_MASK) != 0U)   /* if CORE_PLL is not enabled */
304         {
305             IP_CORE_PLL->PLLCLKMUX = 0U;                                                   /* FIRC input reference 48 MHz */
306             RegValue = IP_CORE_PLL->PLLDV;
307             RegValue &= ~(PLLDIG_PLLDV_RDIV_MASK | PLLDIG_PLLDV_MFI_MASK);
308             IP_CORE_PLL->PLLDV = (RegValue | (PLLDIG_PLLDV_RDIV(1U) | PLLDIG_PLLDV_MFI(30U)) );          /* /1 * 30 */
309 
310             IP_CORE_PLL->PLLFD &= ~(PLLDIG_PLLFD_MFN_MASK | PLLDIG_PLLFD_SDMEN_MASK);      /* Disable modulation */
311             IP_CORE_PLL->PLLCR &= ~PLLDIG_PLLCR_PLLPD_MASK;                                /* Start CORE_PLL */
312         }
313 
314         IP_CORE_DFS->PORTRESET |= DFS_PORT_RESET;
315         IP_CORE_DFS->DVPORT[0U] = DFS_DVPORT;
316         IP_CORE_DFS->DVPORT[1U] = DFS_DVPORT;
317         IP_CORE_DFS->DVPORT[2U] = DFS_DVPORT;
318         IP_CORE_DFS->DVPORT[3U] = DFS_DVPORT;
319         IP_CORE_DFS->DVPORT[4U] = DFS_DVPORT;
320         IP_CORE_DFS->DVPORT[5U] = DFS_DVPORT;
321         IP_CORE_DFS->CTL &= ~DFS_CTL_DFS_RESET_MASK;
322         IP_CORE_DFS->PORTRESET &= ~DFS_PORT_RESET;
323     }
324     else if (PeriphDfsIsInReset != 0U)
325     {
326         if ((IP_PERIPH_PLL->PLLCR & PLLDIG_PLLCR_PLLPD_MASK) != 0U)   /* if PERIPH_PLL is not enabled */
327         {
328             IP_PERIPH_PLL->PLLCLKMUX = 0U;                                                   /* FIRC input reference 48 MHz */
329             RegValue = IP_PERIPH_PLL->PLLDV;
330             RegValue &= ~(PLLDIG_PLLDV_RDIV_MASK | PLLDIG_PLLDV_MFI_MASK);
331             IP_PERIPH_PLL->PLLDV = (RegValue | (PLLDIG_PLLDV_RDIV(1U) | PLLDIG_PLLDV_MFI(30U)) );          /* /1 * 30 */
332 
333             IP_PERIPH_PLL->PLLFD &= ~(PLLDIG_PLLFD_MFN_MASK | PLLDIG_PLLFD_SDMEN_MASK);      /* Disable modulation */
334             IP_PERIPH_PLL->PLLCR &= ~PLLDIG_PLLCR_PLLPD_MASK;                                /* Start PERIPH_PLL */
335         }
336 
337         IP_PERIPH_DFS->PORTRESET |= DFS_PORT_RESET;
338         IP_PERIPH_DFS->DVPORT[0U] = DFS_DVPORT;
339         IP_PERIPH_DFS->DVPORT[1U] = DFS_DVPORT;
340         IP_PERIPH_DFS->DVPORT[2U] = DFS_DVPORT;
341         IP_PERIPH_DFS->DVPORT[3U] = DFS_DVPORT;
342         IP_PERIPH_DFS->DVPORT[4U] = DFS_DVPORT;
343         IP_PERIPH_DFS->DVPORT[5U] = DFS_DVPORT;
344         IP_PERIPH_DFS->CTL &= ~DFS_CTL_DFS_RESET_MASK;
345         IP_PERIPH_DFS->PORTRESET &= ~DFS_PORT_RESET;
346     }
347     else
348     {
349         /* periph Dfs and core Dfs are not in reset */
350     }
351     /* enable clock gate for DDR PLL PHI0 to input CLKOUT0 clock source */
352     IP_GPR0->CLKOUT0SEL |= GPR0_CLKOUT0SEL_CGEN(1U);
353 }
354 
355 
Clock_Ip_McMeEnterKey(void)356 void Clock_Ip_McMeEnterKey(void)
357 {
358     IP_MC_ME->CTL_KEY = 0x5AF0;                                         /* Enter key */
359 
360     IP_MC_ME->CTL_KEY = 0xA50F;                                         /* Enter inverted key */
361 }
362 
363 
364 #if (defined(CLOCK_IP_ENABLE_USER_MODE_SUPPORT))
365   #if (STD_ON == CLOCK_IP_ENABLE_USER_MODE_SUPPORT)
366     #if (defined(CLOCK_IP_HAS_SYSTEM_DIV2_CLK) || defined(CLOCK_IP_HAS_SYSTEM_DIV4_MON1_CLK) || defined(CLOCK_IP_HAS_SYSTEM_DIV4_MON2_CLK))
Clock_Ip_SpecificSetUserAccessAllowed(void)367 void Clock_Ip_SpecificSetUserAccessAllowed(void)
368 {
369 
370 #if (defined(MCAL_CMU_AE_REG_PROT_AVAILABLE))
371   #if(STD_ON == MCAL_CMU_AE_REG_PROT_AVAILABLE)
372 
373     /* CMU_AE SetUserAccessAllowed */
374     #if (defined(IP_CMU_FC_AE_1_BASE) || defined(IP_CMU_FC_AE_2_BASE))
375     SET_USER_ACCESS_ALLOWED(IP_CMU_FM_AE_0_BASE, CMU_AE_PROT_MEM_U32);
376     #endif
377 
378 #endif
379 #endif /* MCAL_CMU_AE_REG_PROT_AVAILABLE */
380 
381 }
382 #endif /* (defined(CLOCK_IP_HAS_SYSTEM_DIV2_CLK) || defined(CLOCK_IP_HAS_SYSTEM_DIV4_MON1_CLK) || defined(CLOCK_IP_HAS_SYSTEM_DIV4_MON2_CLK)) */
383 #endif
384 #endif /* CLOCK_IP_ENABLE_USER_MODE_SUPPORT */
385 
Clock_Ip_Command(Clock_Ip_ClockConfigType const * Config,Clock_Ip_CommandType Command)386 void Clock_Ip_Command(Clock_Ip_ClockConfigType const * Config, Clock_Ip_CommandType Command)
387 {
388     switch(Command)
389     {
390         case CLOCK_IP_INITIALIZE_PLATFORM_COMMAND:
391             Clock_Ip_SpecificPlatformInitClock(Config);
392             break;
393 #ifdef CLOCK_IP_ENABLE_USER_MODE_SUPPORT
394     #if (STD_ON == CLOCK_IP_ENABLE_USER_MODE_SUPPORT)
395         #if (defined(CLOCK_IP_HAS_SYSTEM_DIV2_CLK) || defined(CLOCK_IP_HAS_SYSTEM_DIV4_MON1_CLK) || defined(CLOCK_IP_HAS_SYSTEM_DIV4_MON2_CLK))
396         case CLOCK_IP_SET_USER_ACCESS_ALLOWED_COMMAND:
397             OsIf_Trusted_Call(Clock_Ip_SpecificSetUserAccessAllowed);
398             break;
399         #endif
400     #endif
401 #endif
402         default:
403             /* Command is not implemented on this platform */
404             break;
405     }
406 }
407 
408 /* Clock stop section code */
409 #define MCU_STOP_SEC_CODE
410 #include "Mcu_MemMap.h"
411 
412 
413 #ifdef CLOCK_IP_HAS_RAM_WAIT_STATES
414 
415 
416 /* Clock start rom section code */
417 #define MCU_START_SEC_CODE_AC
418 #include "Mcu_MemMap.h"
419 
420 /* Set Ram IWS */
SRAMController_SetRamIWS(uint32 SmuM33CoreClk_IwsSetting,uint32 Rtu0CoreClk_IwsSetting,uint32 Rtu1CoreClk_IwsSetting,uint32 CeM33CoreClk_IwsSetting)421 void SRAMController_SetRamIWS(uint32 SmuM33CoreClk_IwsSetting, uint32 Rtu0CoreClk_IwsSetting, uint32 Rtu1CoreClk_IwsSetting, uint32 CeM33CoreClk_IwsSetting)
422 {
423 #if (1 == 1)
424     (void)SmuM33CoreClk_IwsSetting;
425     (void)Rtu0CoreClk_IwsSetting;
426     (void)Rtu1CoreClk_IwsSetting;
427     (void)CeM33CoreClk_IwsSetting;
428 #else
429     IP_SMU__SRAMCTL_0->RAMCR |= ((IP_SMU__SRAMCTL_0->RAMCR & ~SRAMCTL_RAMCR_IWS_MASK) | SRAMCTL_RAMCR_IWS(SmuM33CoreClk_IwsSetting));
430     IP_SMU__SRAMCTL_1->RAMCR |= ((IP_SMU__SRAMCTL_1->RAMCR & ~SRAMCTL_RAMCR_IWS_MASK) | SRAMCTL_RAMCR_IWS(SmuM33CoreClk_IwsSetting));
431     IP_SMU__SRAMCTL_2->RAMCR |= ((IP_SMU__SRAMCTL_2->RAMCR & ~SRAMCTL_RAMCR_IWS_MASK) | SRAMCTL_RAMCR_IWS(SmuM33CoreClk_IwsSetting));
432     IP_SMU__SRAMCTL_3->RAMCR |= ((IP_SMU__SRAMCTL_3->RAMCR & ~SRAMCTL_RAMCR_IWS_MASK) | SRAMCTL_RAMCR_IWS(SmuM33CoreClk_IwsSetting));
433 
434     IP_RTU0__SRAMCTL_C0->RAMCR |= ((IP_RTU0__SRAMCTL_C0->RAMCR & ~SRAMCTL_RAMCR_IWS_MASK) | SRAMCTL_RAMCR_IWS(Rtu0CoreClk_IwsSetting));
435     IP_RTU0__SRAMCTL_C1->RAMCR |= ((IP_RTU0__SRAMCTL_C1->RAMCR & ~SRAMCTL_RAMCR_IWS_MASK) | SRAMCTL_RAMCR_IWS(Rtu0CoreClk_IwsSetting));
436     IP_RTU0__SRAMCTL_C2->RAMCR |= ((IP_RTU0__SRAMCTL_C2->RAMCR & ~SRAMCTL_RAMCR_IWS_MASK) | SRAMCTL_RAMCR_IWS(Rtu0CoreClk_IwsSetting));
437     IP_RTU0__SRAMCTL_C3->RAMCR |= ((IP_RTU0__SRAMCTL_C3->RAMCR & ~SRAMCTL_RAMCR_IWS_MASK) | SRAMCTL_RAMCR_IWS(Rtu0CoreClk_IwsSetting));
438     IP_RTU0__SRAMCTL_C4->RAMCR |= ((IP_RTU0__SRAMCTL_C4->RAMCR & ~SRAMCTL_RAMCR_IWS_MASK) | SRAMCTL_RAMCR_IWS(Rtu0CoreClk_IwsSetting));
439     IP_RTU0__SRAMCTL_C5->RAMCR |= ((IP_RTU0__SRAMCTL_C5->RAMCR & ~SRAMCTL_RAMCR_IWS_MASK) | SRAMCTL_RAMCR_IWS(Rtu0CoreClk_IwsSetting));
440     IP_RTU0__SRAMCTL_C6->RAMCR |= ((IP_RTU0__SRAMCTL_C6->RAMCR & ~SRAMCTL_RAMCR_IWS_MASK) | SRAMCTL_RAMCR_IWS(Rtu0CoreClk_IwsSetting));
441     IP_RTU0__SRAMCTL_D0->RAMCR |= ((IP_RTU0__SRAMCTL_D0->RAMCR & ~SRAMCTL_RAMCR_IWS_MASK) | SRAMCTL_RAMCR_IWS(Rtu0CoreClk_IwsSetting));
442     IP_RTU0__SRAMCTL_D1->RAMCR |= ((IP_RTU0__SRAMCTL_D1->RAMCR & ~SRAMCTL_RAMCR_IWS_MASK) | SRAMCTL_RAMCR_IWS(Rtu0CoreClk_IwsSetting));
443     IP_RTU0__SRAMCTL_D2->RAMCR |= ((IP_RTU0__SRAMCTL_D2->RAMCR & ~SRAMCTL_RAMCR_IWS_MASK) | SRAMCTL_RAMCR_IWS(Rtu0CoreClk_IwsSetting));
444 
445     IP_RTU1__SRAMCTL_C0->RAMCR |= ((IP_RTU1__SRAMCTL_C0->RAMCR & ~SRAMCTL_RAMCR_IWS_MASK) | SRAMCTL_RAMCR_IWS(Rtu1CoreClk_IwsSetting));
446     IP_RTU1__SRAMCTL_C1->RAMCR |= ((IP_RTU1__SRAMCTL_C1->RAMCR & ~SRAMCTL_RAMCR_IWS_MASK) | SRAMCTL_RAMCR_IWS(Rtu1CoreClk_IwsSetting));
447     IP_RTU1__SRAMCTL_C2->RAMCR |= ((IP_RTU1__SRAMCTL_C2->RAMCR & ~SRAMCTL_RAMCR_IWS_MASK) | SRAMCTL_RAMCR_IWS(Rtu1CoreClk_IwsSetting));
448     IP_RTU1__SRAMCTL_C3->RAMCR |= ((IP_RTU1__SRAMCTL_C3->RAMCR & ~SRAMCTL_RAMCR_IWS_MASK) | SRAMCTL_RAMCR_IWS(Rtu1CoreClk_IwsSetting));
449     IP_RTU1__SRAMCTL_C4->RAMCR |= ((IP_RTU1__SRAMCTL_C4->RAMCR & ~SRAMCTL_RAMCR_IWS_MASK) | SRAMCTL_RAMCR_IWS(Rtu1CoreClk_IwsSetting));
450     IP_RTU1__SRAMCTL_C5->RAMCR |= ((IP_RTU1__SRAMCTL_C5->RAMCR & ~SRAMCTL_RAMCR_IWS_MASK) | SRAMCTL_RAMCR_IWS(Rtu1CoreClk_IwsSetting));
451     IP_RTU1__SRAMCTL_C6->RAMCR |= ((IP_RTU1__SRAMCTL_C6->RAMCR & ~SRAMCTL_RAMCR_IWS_MASK) | SRAMCTL_RAMCR_IWS(Rtu1CoreClk_IwsSetting));
452     IP_RTU1__SRAMCTL_D0->RAMCR |= ((IP_RTU1__SRAMCTL_D0->RAMCR & ~SRAMCTL_RAMCR_IWS_MASK) | SRAMCTL_RAMCR_IWS(Rtu1CoreClk_IwsSetting));
453     IP_RTU1__SRAMCTL_D1->RAMCR |= ((IP_RTU1__SRAMCTL_D1->RAMCR & ~SRAMCTL_RAMCR_IWS_MASK) | SRAMCTL_RAMCR_IWS(Rtu1CoreClk_IwsSetting));
454     IP_RTU1__SRAMCTL_D2->RAMCR |= ((IP_RTU1__SRAMCTL_D2->RAMCR & ~SRAMCTL_RAMCR_IWS_MASK) | SRAMCTL_RAMCR_IWS(Rtu1CoreClk_IwsSetting));
455 
456     IP_CE_SRAMCTL_0->RAMCR |= ((IP_CE_SRAMCTL_0->RAMCR & ~SRAMCTL_RAMCR_IWS_MASK) | SRAMCTL_RAMCR_IWS(CeM33CoreClk_IwsSetting));
457     IP_CE_SRAMCTL_1->RAMCR |= ((IP_CE_SRAMCTL_1->RAMCR & ~SRAMCTL_RAMCR_IWS_MASK) | SRAMCTL_RAMCR_IWS(CeM33CoreClk_IwsSetting));
458     IP_CE_SRAMCTL_2->RAMCR |= ((IP_CE_SRAMCTL_2->RAMCR & ~SRAMCTL_RAMCR_IWS_MASK) | SRAMCTL_RAMCR_IWS(CeM33CoreClk_IwsSetting));
459 #endif
460 }
461 
462 /* Clock stop rom section code */
463 #define MCU_STOP_SEC_CODE_AC
464 #include "Mcu_MemMap.h"
465 #endif
466 
467 
468 
469 #ifdef __cplusplus
470 }
471 #endif
472 
473 /** @} */
474 
475