1 /*
2 * Copyright 2021-2023 NXP
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 /**
8 * @file
9 *
10 * @addtogroup siul2_icu_ip SIUL2 IPL
11 * @{
12 */
13
14 #ifdef __cplusplus
15 extern "C"{
16 #endif
17
18 /*==================================================================================================
19 * INCLUDE FILES
20 * 1) system and project includes
21 * 2) needed interfaces from external units
22 * 3) internal and external interfaces from this unit
23 ==================================================================================================*/
24 #include "SchM_Icu.h"
25 #include "Std_Types.h"
26 #include "Siul2_Icu_Ip.h"
27 #include "Siul2_Icu_Ip_Irq.h"
28
29 /*==================================================================================================
30 * SOURCE FILE VERSION INFORMATION
31 ==================================================================================================*/
32 #define SIUL2_ICU_IRQ_VENDOR_ID_C 43
33 #define SIUL2_ICU_IRQ_AR_RELEASE_MAJOR_VERSION_C 4
34 #define SIUL2_ICU_IRQ_AR_RELEASE_MINOR_VERSION_C 7
35 #define SIUL2_ICU_IRQ_AR_RELEASE_REVISION_VERSION_C 0
36 #define SIUL2_ICU_IRQ_SW_MAJOR_VERSION_C 1
37 #define SIUL2_ICU_IRQ_SW_MINOR_VERSION_C 0
38 #define SIUL2_ICU_IRQ_SW_PATCH_VERSION_C 0
39
40 /*==================================================================================================
41 * FILE VERSION CHECKS
42 ==================================================================================================*/
43 #ifndef DISABLE_MCAL_INTERMODULE_ASR_CHECK
44 /* Check if header file and Std_Types.h file are of the same Autosar version */
45 #if ((SIUL2_ICU_IRQ_AR_RELEASE_MAJOR_VERSION_C != STD_AR_RELEASE_MAJOR_VERSION) || \
46 (SIUL2_ICU_IRQ_AR_RELEASE_MINOR_VERSION_C != STD_AR_RELEASE_MINOR_VERSION))
47 #error "AutoSar Version Numbers of Siul2_Icu_Ip_Irq.c and Std_Types.h are different"
48 #endif
49
50 /* Check if header file and SchM_Icu.h file are of the same Autosar version */
51 #if ((SIUL2_ICU_IRQ_AR_RELEASE_MAJOR_VERSION_C != SCHM_ICU_AR_RELEASE_MAJOR_VERSION) || \
52 (SIUL2_ICU_IRQ_AR_RELEASE_MINOR_VERSION_C != SCHM_ICU_AR_RELEASE_MINOR_VERSION))
53 #error "AutoSar Version Numbers of Siul2_Icu_Ip_Irq.c and SchM_Icu.h are different"
54 #endif
55 #endif
56
57 /* Check if source file and ICU header file are of the same vendor */
58 #if (SIUL2_ICU_IRQ_VENDOR_ID_C != SIUL2_ICU_IP_VENDOR_ID)
59 #error "Siul2_Icu_Ip_Irq.c and Siul2_Icu_Ip.h have different vendor IDs"
60 #endif
61 /* Check if source file and ICU header file are of the same AutoSar version */
62 #if ((SIUL2_ICU_IRQ_AR_RELEASE_MAJOR_VERSION_C != SIUL2_ICU_IP_AR_RELEASE_MAJOR_VERSION) || \
63 (SIUL2_ICU_IRQ_AR_RELEASE_MINOR_VERSION_C != SIUL2_ICU_IP_AR_RELEASE_MINOR_VERSION) || \
64 (SIUL2_ICU_IRQ_AR_RELEASE_REVISION_VERSION_C != SIUL2_ICU_IP_AR_RELEASE_REVISION_VERSION))
65 #error "AutoSar Version Numbers of Siul2_Icu_Ip_Irq.c and Siul2_Icu_Ip.h are different"
66 #endif
67 /* Check if source file and ICU header file are of the same Software version */
68 #if ((SIUL2_ICU_IRQ_SW_MAJOR_VERSION_C != SIUL2_ICU_IP_SW_MAJOR_VERSION) || \
69 (SIUL2_ICU_IRQ_SW_MINOR_VERSION_C != SIUL2_ICU_IP_SW_MINOR_VERSION) || \
70 (SIUL2_ICU_IRQ_SW_PATCH_VERSION_C != SIUL2_ICU_IP_SW_PATCH_VERSION))
71 #error "Software Version Numbers of Siul2_Icu_Ip_Irq.c and Siul2_Icu_Ip.h are different"
72 #endif
73
74 /* Check if source file and ICU header file are of the same vendor */
75 #if (SIUL2_ICU_IRQ_VENDOR_ID_C != SIUL2_ICU_IP_IRQ_VENDOR_ID)
76 #error "Siul2_Icu_Ip_Irq.c and Siul2_Icu_Ip_Irq.h have different vendor IDs"
77 #endif
78 /* Check if source file and ICU header file are of the same AutoSar version */
79 #if ((SIUL2_ICU_IRQ_AR_RELEASE_MAJOR_VERSION_C != SIUL2_ICU_IP_IRQ_AR_RELEASE_MAJOR_VERSION) || \
80 (SIUL2_ICU_IRQ_AR_RELEASE_MINOR_VERSION_C != SIUL2_ICU_IP_IRQ_AR_RELEASE_MINOR_VERSION) || \
81 (SIUL2_ICU_IRQ_AR_RELEASE_REVISION_VERSION_C != SIUL2_ICU_IP_IRQ_AR_RELEASE_REVISION_VERSION))
82 #error "AutoSar Version Numbers of Siul2_Icu_Ip_Irq.c and Siul2_Icu_Ip_Irq.h are different"
83 #endif
84 /* Check if source file and ICU header file are of the same Software version */
85 #if ((SIUL2_ICU_IRQ_SW_MAJOR_VERSION_C != SIUL2_ICU_IP_IRQ_SW_MAJOR_VERSION) || \
86 (SIUL2_ICU_IRQ_SW_MINOR_VERSION_C != SIUL2_ICU_IP_IRQ_SW_MINOR_VERSION) || \
87 (SIUL2_ICU_IRQ_SW_PATCH_VERSION_C != SIUL2_ICU_IP_IRQ_SW_PATCH_VERSION))
88 #error "Software Version Numbers of Siul2_Icu_Ip_Irq.c and Siul2_Icu_Ip_Irq.h are different"
89 #endif
90
91 /*==================================================================================================
92 * GLOBAL VARIABLE DECLARATIONS
93 ==================================================================================================*/
94 #if (STD_ON == SIUL2_ICU_IP_USED)
95
96 #define ICU_START_SEC_VAR_CLEARED_UNSPECIFIED
97 #include "Icu_MemMap.h"
98
99 extern Siul2_Icu_Ip_State Siul2_Icu_Ip_aChannelState[SIUL2_ICU_IP_NUM_OF_CHANNELS_USED];
100
101 #define ICU_STOP_SEC_VAR_CLEARED_UNSPECIFIED
102 #include "Icu_MemMap.h"
103
104 #define ICU_START_SEC_VAR_INIT_8
105 #include "Icu_MemMap.h"
106 /* This array stores the positions in the Siul2_Icu_Ip_aChannelState array of the configured Siul2 channels. */
107 extern uint8 Siul2_Icu_Ip_IndexInChState[SIUL2_ICU_IP_NUM_OF_INSTANCES][SIUL2_ICU_IP_NUM_OF_CHANNELS];
108 #define ICU_STOP_SEC_VAR_INIT_8
109 #include "Icu_MemMap.h"
110 /*==================================================================================================
111 * LOCAL FUNCTION PROTOTYPES
112 ==================================================================================================*/
113 #define ICU_START_SEC_CODE
114 #include "Icu_MemMap.h"
115
116 #if ( (defined SIUL2_0_ICU_EIRQ_SINGLE_INT) || (defined SIUL2_1_ICU_EIRQ_SINGLE_INT) || \
117 (defined SIUL2_4_ICU_EIRQ_SINGLE_INT) || (defined SIUL2_5_ICU_EIRQ_SINGLE_INT) || \
118 (defined SIUL2_AE_ICU_EIRQ_SINGLE_INT))
119 /**
120 * @brief
121 *
122 * @param instance
123 * @implements Siul2_Icu_Ip_ProcessSingleInterrupt_Activity
124 */
125 static inline void Siul2_Icu_Ip_ProcessSingleInterrupt(uint8 instance);
126 #endif
127
128 #if ((defined SIUL2_ICU_IRQ_CH_0_ISR_USED) || (defined SIUL2_ICU_IRQ_CH_1_ISR_USED) \
129 || (defined SIUL2_ICU_IRQ_CH_2_ISR_USED) || (defined SIUL2_ICU_IRQ_CH_3_ISR_USED) \
130 || (defined SIUL2_ICU_IRQ_CH_4_ISR_USED) || (defined SIUL2_ICU_IRQ_CH_5_ISR_USED) \
131 || (defined SIUL2_ICU_IRQ_CH_6_ISR_USED) || (defined SIUL2_ICU_IRQ_CH_7_ISR_USED) \
132 || (defined SIUL2_ICU_IRQ_CH_8_ISR_USED) || (defined SIUL2_ICU_IRQ_CH_9_ISR_USED) \
133 || (defined SIUL2_ICU_IRQ_CH_10_ISR_USED) || (defined SIUL2_ICU_IRQ_CH_11_ISR_USED) \
134 || (defined SIUL2_ICU_IRQ_CH_12_ISR_USED) || (defined SIUL2_ICU_IRQ_CH_13_ISR_USED) \
135 || (defined SIUL2_ICU_IRQ_CH_14_ISR_USED) || (defined SIUL2_ICU_IRQ_CH_15_ISR_USED) \
136 || (defined SIUL2_ICU_IRQ_CH_16_ISR_USED) || (defined SIUL2_ICU_IRQ_CH_17_ISR_USED) \
137 || (defined SIUL2_ICU_IRQ_CH_18_ISR_USED) || (defined SIUL2_ICU_IRQ_CH_19_ISR_USED) \
138 || (defined SIUL2_ICU_IRQ_CH_20_ISR_USED) || (defined SIUL2_ICU_IRQ_CH_21_ISR_USED) \
139 || (defined SIUL2_ICU_IRQ_CH_22_ISR_USED) || (defined SIUL2_ICU_IRQ_CH_23_ISR_USED) \
140 || (defined SIUL2_ICU_IRQ_CH_24_ISR_USED) || (defined SIUL2_ICU_IRQ_CH_25_ISR_USED) \
141 || (defined SIUL2_ICU_IRQ_CH_26_ISR_USED) || (defined SIUL2_ICU_IRQ_CH_27_ISR_USED) \
142 || (defined SIUL2_ICU_IRQ_CH_28_ISR_USED) || (defined SIUL2_ICU_IRQ_CH_29_ISR_USED) \
143 || (defined SIUL2_ICU_IRQ_CH_30_ISR_USED) || (defined SIUL2_ICU_IRQ_CH_31_ISR_USED))
144 static inline void Siul2_Icu_Ip_ProcessInterrupt(uint8 instance, uint8 firstHwChannel);
145 #endif
146
147 #if ((defined SIUL2_ICU_IRQ_CH_0_ISR_USED) || (defined SIUL2_ICU_IRQ_CH_1_ISR_USED) \
148 || (defined SIUL2_ICU_IRQ_CH_2_ISR_USED) || (defined SIUL2_ICU_IRQ_CH_3_ISR_USED) \
149 || (defined SIUL2_ICU_IRQ_CH_4_ISR_USED) || (defined SIUL2_ICU_IRQ_CH_5_ISR_USED) \
150 || (defined SIUL2_ICU_IRQ_CH_6_ISR_USED) || (defined SIUL2_ICU_IRQ_CH_7_ISR_USED) \
151 || (defined SIUL2_ICU_IRQ_CH_8_ISR_USED) || (defined SIUL2_ICU_IRQ_CH_9_ISR_USED) \
152 || (defined SIUL2_ICU_IRQ_CH_10_ISR_USED) || (defined SIUL2_ICU_IRQ_CH_11_ISR_USED) \
153 || (defined SIUL2_ICU_IRQ_CH_12_ISR_USED) || (defined SIUL2_ICU_IRQ_CH_13_ISR_USED) \
154 || (defined SIUL2_ICU_IRQ_CH_14_ISR_USED) || (defined SIUL2_ICU_IRQ_CH_15_ISR_USED) \
155 || (defined SIUL2_ICU_IRQ_CH_16_ISR_USED) || (defined SIUL2_ICU_IRQ_CH_17_ISR_USED) \
156 || (defined SIUL2_ICU_IRQ_CH_18_ISR_USED) || (defined SIUL2_ICU_IRQ_CH_19_ISR_USED) \
157 || (defined SIUL2_ICU_IRQ_CH_20_ISR_USED) || (defined SIUL2_ICU_IRQ_CH_21_ISR_USED) \
158 || (defined SIUL2_ICU_IRQ_CH_22_ISR_USED) || (defined SIUL2_ICU_IRQ_CH_23_ISR_USED) \
159 || (defined SIUL2_ICU_IRQ_CH_24_ISR_USED) || (defined SIUL2_ICU_IRQ_CH_25_ISR_USED) \
160 || (defined SIUL2_ICU_IRQ_CH_26_ISR_USED) || (defined SIUL2_ICU_IRQ_CH_27_ISR_USED) \
161 || (defined SIUL2_ICU_IRQ_CH_28_ISR_USED) || (defined SIUL2_ICU_IRQ_CH_29_ISR_USED) \
162 || (defined SIUL2_ICU_IRQ_CH_30_ISR_USED) || (defined SIUL2_ICU_IRQ_CH_31_ISR_USED) \
163 || (defined SIUL2_0_ICU_EIRQ_SINGLE_INT) || (defined SIUL2_1_ICU_EIRQ_SINGLE_INT) \
164 || (defined SIUL2_4_ICU_EIRQ_SINGLE_INT) || (defined SIUL2_5_ICU_EIRQ_SINGLE_INT) \
165 || (defined SIUL2_AE_ICU_EIRQ_SINGLE_INT))
166 /**
167 * @brief
168 *
169 * @param instance
170 * @param hwChannel
171 */
172 static inline void Siul2_Icu_Ip_ReportEvents(uint8 instance, uint8 hwChannel);
173 #endif
174 /*==================================================================================================
175 * LOCAL FUNCTIONS
176 ==================================================================================================*/
177 #if ( (defined SIUL2_0_ICU_EIRQ_SINGLE_INT) || (defined SIUL2_1_ICU_EIRQ_SINGLE_INT) || \
178 (defined SIUL2_4_ICU_EIRQ_SINGLE_INT) || (defined SIUL2_5_ICU_EIRQ_SINGLE_INT) || \
179 (defined SIUL2_AE_ICU_EIRQ_SINGLE_INT))
Siul2_Icu_Ip_ProcessSingleInterrupt(uint8 instance)180 static inline void Siul2_Icu_Ip_ProcessSingleInterrupt(uint8 instance)
181 {
182 uint8 u8IrqChannel = 0U;
183 uint32 u32RegIrqMask = 0U;
184 uint32 u32ChannelMask = 1U;
185 uint32 u32RegFlags = 0U;
186 uint32 u32RegIrqEn = 0U;
187 #ifdef SIUL2_ICU_AE_AVAILABLE
188 if (instance >= SIUL2_ICU_AE_MIN_INSTANCE)
189 {
190 u32RegFlags = Siul2_Ae_Icu_Ip_pBase[instance - SIUL2_ICU_AE_MIN_INSTANCE]->DISR0;
191 u32RegIrqEn = Siul2_Ae_Icu_Ip_pBase[instance - SIUL2_ICU_AE_MIN_INSTANCE]->DIRER0;
192 }
193 else
194 {
195 #endif
196 u32RegFlags = Siul2_Icu_Ip_pBase[instance]->DISR0;
197 u32RegIrqEn = Siul2_Icu_Ip_pBase[instance]->DIRER0;
198 #ifdef SIUL2_ICU_AE_AVAILABLE
199 }
200 #endif
201 /* Select which channels will be serviced - only the enabled irq ones*/
202 u32RegIrqMask = u32RegFlags & u32RegIrqEn;
203
204 for (u8IrqChannel = 0; u8IrqChannel < SIUL2_ICU_IP_NUM_OF_CHANNELS; u8IrqChannel++)
205 {
206 if (TRUE != Siul2_Icu_Ip_aChannelState[Siul2_Icu_Ip_IndexInChState[instance][u8IrqChannel]].chInit)
207 {
208 if (0x0U != (u32RegFlags & u32ChannelMask))
209 {
210 #ifdef SIUL2_ICU_AE_AVAILABLE
211 if (instance >= SIUL2_ICU_AE_MIN_INSTANCE)
212 {
213 /* Clear pending interrupt serviced */
214 Siul2_Ae_Icu_Ip_pBase[instance - SIUL2_ICU_AE_MIN_INSTANCE]->DISR0 = u32RegFlags & u32ChannelMask;
215 }
216 else
217 {
218 #endif
219 /* Clear pending interrupt serviced */
220 Siul2_Icu_Ip_pBase[instance]->DISR0 = u32RegFlags & u32ChannelMask;
221 #ifdef SIUL2_ICU_AE_AVAILABLE
222 }
223 #endif
224 }
225 }
226 else
227 {
228 if (0x0U != (u32RegIrqMask & u32ChannelMask))
229 {
230
231
232 #ifdef SIUL2_ICU_AE_AVAILABLE
233 if (instance >= SIUL2_ICU_AE_MIN_INSTANCE)
234 {
235 /* Clear pending interrupt serviced */
236 Siul2_Ae_Icu_Ip_pBase[instance - SIUL2_ICU_AE_MIN_INSTANCE]->DISR0 = u32RegFlags & u32ChannelMask;
237 }
238 else
239 {
240 #endif
241 /* Clear pending interrupt serviced */
242 Siul2_Icu_Ip_pBase[instance]->DISR0 = u32RegFlags & u32ChannelMask;
243 #ifdef SIUL2_ICU_AE_AVAILABLE
244 }
245 #endif
246
247 Siul2_Icu_Ip_ReportEvents(instance, u8IrqChannel);
248 }
249 }
250 u32ChannelMask <<= (uint32)1U;
251 }
252 }
253 #endif /* All single interrupt cases. */
254
255 #if ((defined SIUL2_ICU_IRQ_CH_0_ISR_USED) || (defined SIUL2_ICU_IRQ_CH_1_ISR_USED) \
256 || (defined SIUL2_ICU_IRQ_CH_2_ISR_USED) || (defined SIUL2_ICU_IRQ_CH_3_ISR_USED) \
257 || (defined SIUL2_ICU_IRQ_CH_4_ISR_USED) || (defined SIUL2_ICU_IRQ_CH_5_ISR_USED) \
258 || (defined SIUL2_ICU_IRQ_CH_6_ISR_USED) || (defined SIUL2_ICU_IRQ_CH_7_ISR_USED) \
259 || (defined SIUL2_ICU_IRQ_CH_8_ISR_USED) || (defined SIUL2_ICU_IRQ_CH_9_ISR_USED) \
260 || (defined SIUL2_ICU_IRQ_CH_10_ISR_USED) || (defined SIUL2_ICU_IRQ_CH_11_ISR_USED) \
261 || (defined SIUL2_ICU_IRQ_CH_12_ISR_USED) || (defined SIUL2_ICU_IRQ_CH_13_ISR_USED) \
262 || (defined SIUL2_ICU_IRQ_CH_14_ISR_USED) || (defined SIUL2_ICU_IRQ_CH_15_ISR_USED) \
263 || (defined SIUL2_ICU_IRQ_CH_16_ISR_USED) || (defined SIUL2_ICU_IRQ_CH_17_ISR_USED) \
264 || (defined SIUL2_ICU_IRQ_CH_18_ISR_USED) || (defined SIUL2_ICU_IRQ_CH_19_ISR_USED) \
265 || (defined SIUL2_ICU_IRQ_CH_20_ISR_USED) || (defined SIUL2_ICU_IRQ_CH_21_ISR_USED) \
266 || (defined SIUL2_ICU_IRQ_CH_22_ISR_USED) || (defined SIUL2_ICU_IRQ_CH_23_ISR_USED) \
267 || (defined SIUL2_ICU_IRQ_CH_24_ISR_USED) || (defined SIUL2_ICU_IRQ_CH_25_ISR_USED) \
268 || (defined SIUL2_ICU_IRQ_CH_26_ISR_USED) || (defined SIUL2_ICU_IRQ_CH_27_ISR_USED) \
269 || (defined SIUL2_ICU_IRQ_CH_28_ISR_USED) || (defined SIUL2_ICU_IRQ_CH_29_ISR_USED) \
270 || (defined SIUL2_ICU_IRQ_CH_30_ISR_USED) || (defined SIUL2_ICU_IRQ_CH_31_ISR_USED))
271 /** @implements Siul2_Icu_Ip_ProcessInterrupt_Activity */
Siul2_Icu_Ip_ProcessInterrupt(uint8 instance,uint8 firstHwChannel)272 static inline void Siul2_Icu_Ip_ProcessInterrupt(uint8 instance, uint8 firstHwChannel)
273 {
274 uint8 u8IrqChannel;
275 uint32 u32RegIrqMask = (uint32)0xFFU << (uint32)firstHwChannel;
276 uint32 u32ChannelMask = (uint32)1U << (uint32)firstHwChannel;
277
278 uint32 u32RegFlags = (Siul2_Icu_Ip_pBase[instance])->DISR0;
279 uint32 u32RegIrqEn = (Siul2_Icu_Ip_pBase[instance])->DIRER0;
280
281 /* Select which channels will be serviced - only the enabled irq ones*/
282 u32RegIrqMask = u32RegFlags & u32RegIrqEn & u32RegIrqMask;
283
284 for (u8IrqChannel = (uint8)firstHwChannel; u8IrqChannel < (uint8)(firstHwChannel + 8U); u8IrqChannel++)
285 {
286 if (0x0U != (u32RegIrqMask & u32ChannelMask))
287 {
288 /* Clear pending interrupt serviced */
289 (Siul2_Icu_Ip_pBase[instance])->DISR0 = u32RegFlags & u32ChannelMask;
290
291 Siul2_Icu_Ip_ReportEvents(instance, u8IrqChannel);
292 }
293 u32ChannelMask <<= (uint32)1U;
294 }
295 }
296 #endif
297
298 #if ((defined SIUL2_ICU_IRQ_CH_0_ISR_USED) || (defined SIUL2_ICU_IRQ_CH_1_ISR_USED) \
299 || (defined SIUL2_ICU_IRQ_CH_2_ISR_USED) || (defined SIUL2_ICU_IRQ_CH_3_ISR_USED) \
300 || (defined SIUL2_ICU_IRQ_CH_4_ISR_USED) || (defined SIUL2_ICU_IRQ_CH_5_ISR_USED) \
301 || (defined SIUL2_ICU_IRQ_CH_6_ISR_USED) || (defined SIUL2_ICU_IRQ_CH_7_ISR_USED) \
302 || (defined SIUL2_ICU_IRQ_CH_8_ISR_USED) || (defined SIUL2_ICU_IRQ_CH_9_ISR_USED) \
303 || (defined SIUL2_ICU_IRQ_CH_10_ISR_USED) || (defined SIUL2_ICU_IRQ_CH_11_ISR_USED) \
304 || (defined SIUL2_ICU_IRQ_CH_12_ISR_USED) || (defined SIUL2_ICU_IRQ_CH_13_ISR_USED) \
305 || (defined SIUL2_ICU_IRQ_CH_14_ISR_USED) || (defined SIUL2_ICU_IRQ_CH_15_ISR_USED) \
306 || (defined SIUL2_ICU_IRQ_CH_16_ISR_USED) || (defined SIUL2_ICU_IRQ_CH_17_ISR_USED) \
307 || (defined SIUL2_ICU_IRQ_CH_18_ISR_USED) || (defined SIUL2_ICU_IRQ_CH_19_ISR_USED) \
308 || (defined SIUL2_ICU_IRQ_CH_20_ISR_USED) || (defined SIUL2_ICU_IRQ_CH_21_ISR_USED) \
309 || (defined SIUL2_ICU_IRQ_CH_22_ISR_USED) || (defined SIUL2_ICU_IRQ_CH_23_ISR_USED) \
310 || (defined SIUL2_ICU_IRQ_CH_24_ISR_USED) || (defined SIUL2_ICU_IRQ_CH_25_ISR_USED) \
311 || (defined SIUL2_ICU_IRQ_CH_26_ISR_USED) || (defined SIUL2_ICU_IRQ_CH_27_ISR_USED) \
312 || (defined SIUL2_ICU_IRQ_CH_28_ISR_USED) || (defined SIUL2_ICU_IRQ_CH_29_ISR_USED) \
313 || (defined SIUL2_ICU_IRQ_CH_30_ISR_USED) || (defined SIUL2_ICU_IRQ_CH_31_ISR_USED) \
314 || (defined SIUL2_0_ICU_EIRQ_SINGLE_INT) || (defined SIUL2_1_ICU_EIRQ_SINGLE_INT) \
315 || (defined SIUL2_4_ICU_EIRQ_SINGLE_INT) || (defined SIUL2_5_ICU_EIRQ_SINGLE_INT) \
316 || (defined SIUL2_AE_ICU_EIRQ_SINGLE_INT))
Siul2_Icu_Ip_ReportEvents(uint8 instance,uint8 hwChannel)317 static inline void Siul2_Icu_Ip_ReportEvents(uint8 instance, uint8 hwChannel)
318 {
319 uint8 u8ChIndex = Siul2_Icu_Ip_IndexInChState[instance][hwChannel];
320
321 /* Calling HLD Report Events for the logical channel. */
322 if (Siul2_Icu_Ip_aChannelState[u8ChIndex].callback != NULL_PTR)
323 {
324 Siul2_Icu_Ip_aChannelState[u8ChIndex].callback(Siul2_Icu_Ip_aChannelState[u8ChIndex].callbackParam, FALSE);
325 }
326 else
327 {
328 /* Calling Notification for the IPL channel. */
329 if ((NULL_PTR != Siul2_Icu_Ip_aChannelState[u8ChIndex].Siul2ChannelNotification) && \
330 ((boolean)TRUE == Siul2_Icu_Ip_aChannelState[u8ChIndex].notificationEnable))
331 {
332 Siul2_Icu_Ip_aChannelState[u8ChIndex].Siul2ChannelNotification();
333 }
334 }
335 }
336 #endif
337
338 /*==================================================================================================
339 * GLOBAL FUNCTIONS
340 ==================================================================================================*/
341 #if (defined(SIUL2_0_ICU_EIRQ_SINGLE_INT))
ISR(SIUL2_0_ICU_EIRQ_SINGLE_INT_HANDLER)342 ISR(SIUL2_0_ICU_EIRQ_SINGLE_INT_HANDLER)
343 {
344 /*calling process interrupt function of corresponding instance*/
345 Siul2_Icu_Ip_ProcessSingleInterrupt(0U);
346 }
347 #endif /* SIUL2_0_ICU_EIRQ_SINGLE_INT */
348
349 #if (defined(SIUL2_1_ICU_EIRQ_SINGLE_INT))
ISR(SIUL2_1_ICU_EIRQ_SINGLE_INT_HANDLER)350 ISR(SIUL2_1_ICU_EIRQ_SINGLE_INT_HANDLER)
351 {
352 /*calling process interrupt function of corresponding instance*/
353 Siul2_Icu_Ip_ProcessSingleInterrupt(1U);
354 }
355 #endif /* SIUL2_1_ICU_EIRQ_SINGLE_INT */
356
357 #if (defined(SIUL2_4_ICU_EIRQ_SINGLE_INT))
ISR(SIUL2_4_ICU_EIRQ_SINGLE_INT_HANDLER)358 ISR(SIUL2_4_ICU_EIRQ_SINGLE_INT_HANDLER)
359 {
360 /*calling process interrupt function of corresponding instance*/
361 Siul2_Icu_Ip_ProcessSingleInterrupt(4U);
362 }
363 #endif /* SIUL2_4_ICU_EIRQ_SINGLE_INT */
364
365 #if (defined(SIUL2_5_ICU_EIRQ_SINGLE_INT))
ISR(SIUL2_5_ICU_EIRQ_SINGLE_INT_HANDLER)366 ISR(SIUL2_5_ICU_EIRQ_SINGLE_INT_HANDLER)
367 {
368 /*calling process interrupt function of corresponding instance*/
369 Siul2_Icu_Ip_ProcessSingleInterrupt(5U);
370 }
371 #endif /* SIUL2_5_ICU_EIRQ_SINGLE_INT */
372
373 #if (defined(SIUL2_AE_ICU_EIRQ_SINGLE_INT))
ISR(SIUL2_AE_ICU_EIRQ_SINGLE_INT_HANDLER)374 ISR(SIUL2_AE_ICU_EIRQ_SINGLE_INT_HANDLER)
375 {
376 /*calling process interrupt function of corresponding instance*/
377 Siul2_Icu_Ip_ProcessSingleInterrupt(6U);
378 }
379 #endif /* SIUL2_AE_ICU_EIRQ_SINGLE_INT */
380
381 #if ((defined SIUL2_ICU_IRQ_CH_0_ISR_USED) || (defined SIUL2_ICU_IRQ_CH_1_ISR_USED) ||\
382 (defined SIUL2_ICU_IRQ_CH_2_ISR_USED) || (defined SIUL2_ICU_IRQ_CH_3_ISR_USED) ||\
383 (defined SIUL2_ICU_IRQ_CH_4_ISR_USED) || (defined SIUL2_ICU_IRQ_CH_5_ISR_USED) ||\
384 (defined SIUL2_ICU_IRQ_CH_6_ISR_USED) || (defined SIUL2_ICU_IRQ_CH_7_ISR_USED))
ISR(SIUL2_EXT_IRQ_0_7_ISR)385 ISR(SIUL2_EXT_IRQ_0_7_ISR)
386 {
387 /*implement IRQ for the instance 0*/
388 Siul2_Icu_Ip_ProcessInterrupt(0U, SIUL2_ICU_IRQ_0);
389 }
390 #endif /* IRQ 0 - 7 */
391
392 #if ((defined SIUL2_ICU_IRQ_CH_8_ISR_USED) || (defined SIUL2_ICU_IRQ_CH_9_ISR_USED) ||\
393 (defined SIUL2_ICU_IRQ_CH_10_ISR_USED) || (defined SIUL2_ICU_IRQ_CH_11_ISR_USED) ||\
394 (defined SIUL2_ICU_IRQ_CH_12_ISR_USED) || (defined SIUL2_ICU_IRQ_CH_13_ISR_USED) ||\
395 (defined SIUL2_ICU_IRQ_CH_14_ISR_USED) || (defined SIUL2_ICU_IRQ_CH_15_ISR_USED))
ISR(SIUL2_EXT_IRQ_8_15_ISR)396 ISR(SIUL2_EXT_IRQ_8_15_ISR)
397 {
398 /*implement IRQ for the instance 0*/
399 Siul2_Icu_Ip_ProcessInterrupt(0U, SIUL2_ICU_IRQ_8);
400 }
401 #endif /* IRQ 8 - 15 */
402
403 #if ((defined SIUL2_ICU_IRQ_CH_16_ISR_USED) || (defined SIUL2_ICU_IRQ_CH_17_ISR_USED) || \
404 (defined SIUL2_ICU_IRQ_CH_18_ISR_USED) || (defined SIUL2_ICU_IRQ_CH_19_ISR_USED) || \
405 (defined SIUL2_ICU_IRQ_CH_20_ISR_USED) || (defined SIUL2_ICU_IRQ_CH_21_ISR_USED) || \
406 (defined SIUL2_ICU_IRQ_CH_22_ISR_USED) || (defined SIUL2_ICU_IRQ_CH_23_ISR_USED))
ISR(SIUL2_EXT_IRQ_16_23_ISR)407 ISR(SIUL2_EXT_IRQ_16_23_ISR)
408 {
409 /*implement IRQ for the instance 0*/
410 Siul2_Icu_Ip_ProcessInterrupt(0U, SIUL2_ICU_IRQ_16);
411 }
412 #endif
413
414 #if ((defined SIUL2_ICU_IRQ_CH_24_ISR_USED) || (defined SIUL2_ICU_IRQ_CH_25_ISR_USED) || \
415 (defined SIUL2_ICU_IRQ_CH_26_ISR_USED) || (defined SIUL2_ICU_IRQ_CH_27_ISR_USED) || \
416 (defined SIUL2_ICU_IRQ_CH_28_ISR_USED) || (defined SIUL2_ICU_IRQ_CH_29_ISR_USED) || \
417 (defined SIUL2_ICU_IRQ_CH_30_ISR_USED) || (defined SIUL2_ICU_IRQ_CH_31_ISR_USED))
ISR(SIUL2_EXT_IRQ_24_31_ISR)418 ISR(SIUL2_EXT_IRQ_24_31_ISR)
419 {
420 /*implement IRQ for the instance 0*/
421 Siul2_Icu_Ip_ProcessInterrupt(0U, SIUL2_ICU_IRQ_24);
422 }
423 #endif
424
425 #define ICU_STOP_SEC_CODE
426 #include "Icu_MemMap.h"
427
428 #endif /* SIUL2_ICU_IP_USED */
429
430 #ifdef __cplusplus
431 }
432 #endif
433
434 /** @} */
435
