1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2023 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32Z2_SW_PORT2.h 10 * @version 2.1 11 * @date 2023-07-20 12 * @brief Peripheral Access Layer for S32Z2_SW_PORT2 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32Z2_SW_PORT2_H_) /* Check if memory map has not been already included */ 58 #define S32Z2_SW_PORT2_H_ 59 60 #include "S32Z2_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- SW_PORT2 Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup SW_PORT2_Peripheral_Access_Layer SW_PORT2 Peripheral Access Layer 68 * @{ 69 */ 70 71 /** SW_PORT2 - Size of Registers Arrays */ 72 #define SW_PORT2_TCT_NUM_COUNT 8u 73 74 /** SW_PORT2 - Register Layout Typedef */ 75 typedef struct { 76 __I uint32_t PCAPR; /**< Port capability register, offset: 0x0 */ 77 __I uint32_t PMCAPR; /**< Port MAC capability register, offset: 0x4 */ 78 __I uint32_t PIOCAPR; /**< Port I/O capability register, offset: 0x8 */ 79 uint8_t RESERVED_0[4]; 80 __IO uint32_t PCR; /**< Port configuration register, offset: 0x10 */ 81 uint8_t RESERVED_1[12]; 82 __IO uint32_t PMAR0; /**< Port MAC address register 0, offset: 0x20 */ 83 __IO uint32_t PMAR1; /**< Port MAC address register 1, offset: 0x24 */ 84 uint8_t RESERVED_2[40]; 85 __IO uint32_t PTAR; /**< Port TPID acceptance register, offset: 0x50 */ 86 __IO uint32_t PQOSMR; /**< Port QoS mode register, offset: 0x54 */ 87 uint8_t RESERVED_3[8]; 88 __I uint32_t PQOR; /**< Port Queue Operational register, offset: 0x60 */ 89 uint8_t RESERVED_4[28]; 90 __IO uint32_t PPCR; /**< Port parser configuration register, offset: 0x80 */ 91 __IO uint32_t PIPFCR; /**< Port ingress port filter configuration register, offset: 0x84 */ 92 uint8_t RESERVED_5[24]; 93 __IO uint32_t PSGCR; /**< Port stream gate configuration register, offset: 0xA0 */ 94 uint8_t RESERVED_6[92]; 95 __IO uint32_t POR; /**< Port operational register, offset: 0x100 */ 96 __I uint32_t PSR; /**< Port status register, offset: 0x104 */ 97 __IO uint32_t PRXSDUOR; /**< Port receive SDU overhead register, offset: 0x108 */ 98 __IO uint32_t PTXSDUOR; /**< Port transmit SDU overhead register, offset: 0x10C */ 99 __IO uint32_t PTGSCR; /**< Port time gate scheduling control register, offset: 0x110 */ 100 __I uint32_t PTGAGLSR; /**< Port time gate scheduling admin gate list status register, offset: 0x114 */ 101 __I uint32_t PTGAGLLR; /**< Port time gate scheduling admin gate list length register, offset: 0x118 */ 102 __I uint32_t PTGOGLLR; /**< Port time gating operational gate list length register, offset: 0x11C */ 103 uint8_t RESERVED_7[160]; 104 __I uint32_t PRXDCR; /**< Port Rx discard count register, offset: 0x1C0 */ 105 uint8_t RESERVED_8[4]; 106 __IO uint32_t PRXDCRR0; /**< Port Rx discard count reason register 0, offset: 0x1C8 */ 107 __IO uint32_t PRXDCRR1; /**< Port Rx discard count reason register 1, offset: 0x1CC */ 108 uint8_t RESERVED_9[16]; 109 __I uint32_t PTXDCR; /**< Port Tx discard count register, offset: 0x1E0 */ 110 uint8_t RESERVED_10[4]; 111 __IO uint32_t PTXDCRR0; /**< Port Tx discard count reason register 0, offset: 0x1E8 */ 112 __IO uint32_t PTXDCRR1; /**< Port Tx discard count reason register 1, offset: 0x1EC */ 113 uint8_t RESERVED_11[16]; 114 struct { /* offset: 0x200, array step: 0x20 */ 115 __I uint32_t PTGSTCSR; /**< Port time gate scheduling traffic class 0 status register..Port time gate scheduling traffic class 7 status register, array offset: 0x200, array step: 0x20 */ 116 uint8_t RESERVED_0[4]; 117 __IO uint32_t PTCTMSDUR; /**< Port traffic class 0 transmit maximum SDU register..Port traffic class 7 transmit maximum SDU register, array offset: 0x208, array step: 0x20 */ 118 uint8_t RESERVED_1[4]; 119 __IO uint32_t PTCCBSR0; /**< Port transmit traffic class 0 credit based shaper register 0..Port transmit traffic class 7 credit based shaper register 0, array offset: 0x210, array step: 0x20 */ 120 __IO uint32_t PTCCBSR1; /**< Port traffic class 0 credit based shaper register 1..Port traffic class 7 credit based shaper register 1, array offset: 0x214, array step: 0x20 */ 121 uint8_t RESERVED_2[8]; 122 } TCT_NUM[SW_PORT2_TCT_NUM_COUNT]; 123 uint8_t RESERVED_12[256]; 124 __IO uint32_t PBPMCR0; /**< Port buffer pool mapping configuration register 0, offset: 0x400 */ 125 __IO uint32_t PBPMCR1; /**< Port buffer pool mapping configuration register 1, offset: 0x404 */ 126 uint8_t RESERVED_13[48]; 127 __IO uint32_t PPCPDEIMR; /**< Port PCP DEI mapping register, offset: 0x438 */ 128 uint8_t RESERVED_14[4]; 129 __IO uint32_t PMCR; /**< Port mirror configuration register, offset: 0x440 */ 130 uint8_t RESERVED_15[20]; 131 __IO uint32_t PLANIDCR; /**< Port LANID configuration register, offset: 0x458 */ 132 uint8_t RESERVED_16[4]; 133 __IO uint32_t PISIDCR; /**< Port ingress stream identification configuration register, offset: 0x460 */ 134 __IO uint32_t PFMCR; /**< Port frame modification configuration register, offset: 0x464 */ 135 uint8_t RESERVED_17[8]; 136 __IO uint32_t PIPV2QMR0; /**< Port IPV to queue mapping register 0, offset: 0x470 */ 137 uint8_t RESERVED_18[60]; 138 __I uint32_t PTCMINLR; /**< Port time capture minimum latency register, offset: 0x4B0 */ 139 __I uint32_t PTCMAXLR; /**< Port time capture maximum latency register, offset: 0x4B4 */ 140 uint8_t RESERVED_19[72]; 141 __IO uint32_t BPCR; /**< Bridge port configuration register, offset: 0x500 */ 142 uint8_t RESERVED_20[12]; 143 __IO uint32_t BPDVR; /**< Bridge port default VLAN register, offset: 0x510 */ 144 uint8_t RESERVED_21[12]; 145 __IO uint32_t BPSTGSR; /**< Bridge port spanning tree group state register, offset: 0x520 */ 146 uint8_t RESERVED_22[4]; 147 __IO uint32_t BPSCR0; /**< Bridge port storm control register 0, offset: 0x528 */ 148 __IO uint32_t BPSCR1; /**< Bridge port storm control register 1, offset: 0x52C */ 149 __I uint32_t BPOR; /**< Bridge port operational register, offset: 0x530 */ 150 uint8_t RESERVED_23[76]; 151 __I uint32_t BPDCR; /**< Bridge port discard count register, offset: 0x580 */ 152 uint8_t RESERVED_24[4]; 153 __IO uint32_t BPDCRR0; /**< Bridge port discard count reason register 0, offset: 0x588 */ 154 __IO uint32_t BPDCRR1; /**< Bridge port discard count reason register 1, offset: 0x58C */ 155 __IO uint32_t BPMLFSR; /**< Bridge port MAC learning failure status register, offset: 0x590 */ 156 } SW_PORT2_Type, *SW_PORT2_MemMapPtr; 157 158 /** Number of instances of the SW_PORT2 module. */ 159 #define SW_PORT2_INSTANCE_COUNT (1u) 160 161 /* SW_PORT2 - Peripheral instance base addresses */ 162 /** Peripheral NETC__SW0_PORT2 base address */ 163 #define IP_NETC__SW0_PORT2_BASE (0x74A0C000u) 164 /** Peripheral NETC__SW0_PORT2 base pointer */ 165 #define IP_NETC__SW0_PORT2 ((SW_PORT2_Type *)IP_NETC__SW0_PORT2_BASE) 166 /** Array initializer of SW_PORT2 peripheral base addresses */ 167 #define IP_SW_PORT2_BASE_ADDRS { IP_NETC__SW0_PORT2_BASE } 168 /** Array initializer of SW_PORT2 peripheral base pointers */ 169 #define IP_SW_PORT2_BASE_PTRS { IP_NETC__SW0_PORT2 } 170 171 /* ---------------------------------------------------------------------------- 172 -- SW_PORT2 Register Masks 173 ---------------------------------------------------------------------------- */ 174 175 /*! 176 * @addtogroup SW_PORT2_Register_Masks SW_PORT2 Register Masks 177 * @{ 178 */ 179 180 /*! @name PCAPR - Port capability register */ 181 /*! @{ */ 182 183 #define SW_PORT2_PCAPR_LINK_TYPE_MASK (0x10U) 184 #define SW_PORT2_PCAPR_LINK_TYPE_SHIFT (4U) 185 #define SW_PORT2_PCAPR_LINK_TYPE_WIDTH (1U) 186 #define SW_PORT2_PCAPR_LINK_TYPE(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_PCAPR_LINK_TYPE_SHIFT)) & SW_PORT2_PCAPR_LINK_TYPE_MASK) 187 188 #define SW_PORT2_PCAPR_NUM_TC_MASK (0xF000U) 189 #define SW_PORT2_PCAPR_NUM_TC_SHIFT (12U) 190 #define SW_PORT2_PCAPR_NUM_TC_WIDTH (4U) 191 #define SW_PORT2_PCAPR_NUM_TC(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_PCAPR_NUM_TC_SHIFT)) & SW_PORT2_PCAPR_NUM_TC_MASK) 192 193 #define SW_PORT2_PCAPR_NUM_Q_MASK (0xF0000U) 194 #define SW_PORT2_PCAPR_NUM_Q_SHIFT (16U) 195 #define SW_PORT2_PCAPR_NUM_Q_WIDTH (4U) 196 #define SW_PORT2_PCAPR_NUM_Q(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_PCAPR_NUM_Q_SHIFT)) & SW_PORT2_PCAPR_NUM_Q_MASK) 197 198 #define SW_PORT2_PCAPR_NUM_CG_MASK (0xF000000U) 199 #define SW_PORT2_PCAPR_NUM_CG_SHIFT (24U) 200 #define SW_PORT2_PCAPR_NUM_CG_WIDTH (4U) 201 #define SW_PORT2_PCAPR_NUM_CG(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_PCAPR_NUM_CG_SHIFT)) & SW_PORT2_PCAPR_NUM_CG_MASK) 202 203 #define SW_PORT2_PCAPR_TGS_MASK (0x10000000U) 204 #define SW_PORT2_PCAPR_TGS_SHIFT (28U) 205 #define SW_PORT2_PCAPR_TGS_WIDTH (1U) 206 #define SW_PORT2_PCAPR_TGS(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_PCAPR_TGS_SHIFT)) & SW_PORT2_PCAPR_TGS_MASK) 207 208 #define SW_PORT2_PCAPR_CBS_MASK (0x20000000U) 209 #define SW_PORT2_PCAPR_CBS_SHIFT (29U) 210 #define SW_PORT2_PCAPR_CBS_WIDTH (1U) 211 #define SW_PORT2_PCAPR_CBS(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_PCAPR_CBS_SHIFT)) & SW_PORT2_PCAPR_CBS_MASK) 212 /*! @} */ 213 214 /*! @name PMCAPR - Port MAC capability register */ 215 /*! @{ */ 216 217 #define SW_PORT2_PMCAPR_MAC_VAR_MASK (0x7U) 218 #define SW_PORT2_PMCAPR_MAC_VAR_SHIFT (0U) 219 #define SW_PORT2_PMCAPR_MAC_VAR_WIDTH (3U) 220 #define SW_PORT2_PMCAPR_MAC_VAR(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_PMCAPR_MAC_VAR_SHIFT)) & SW_PORT2_PMCAPR_MAC_VAR_MASK) 221 222 #define SW_PORT2_PMCAPR_EFPAD_MASK (0x30U) 223 #define SW_PORT2_PMCAPR_EFPAD_SHIFT (4U) 224 #define SW_PORT2_PMCAPR_EFPAD_WIDTH (2U) 225 #define SW_PORT2_PMCAPR_EFPAD(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_PMCAPR_EFPAD_SHIFT)) & SW_PORT2_PMCAPR_EFPAD_MASK) 226 227 #define SW_PORT2_PMCAPR_HD_MASK (0x100U) 228 #define SW_PORT2_PMCAPR_HD_SHIFT (8U) 229 #define SW_PORT2_PMCAPR_HD_WIDTH (1U) 230 #define SW_PORT2_PMCAPR_HD(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_PMCAPR_HD_SHIFT)) & SW_PORT2_PMCAPR_HD_MASK) 231 232 #define SW_PORT2_PMCAPR_FP_MASK (0x600U) 233 #define SW_PORT2_PMCAPR_FP_SHIFT (9U) 234 #define SW_PORT2_PMCAPR_FP_WIDTH (2U) 235 #define SW_PORT2_PMCAPR_FP(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_PMCAPR_FP_SHIFT)) & SW_PORT2_PMCAPR_FP_MASK) 236 237 #define SW_PORT2_PMCAPR_MII_PROT_MASK (0xF000000U) 238 #define SW_PORT2_PMCAPR_MII_PROT_SHIFT (24U) 239 #define SW_PORT2_PMCAPR_MII_PROT_WIDTH (4U) 240 #define SW_PORT2_PMCAPR_MII_PROT(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_PMCAPR_MII_PROT_SHIFT)) & SW_PORT2_PMCAPR_MII_PROT_MASK) 241 /*! @} */ 242 243 /*! @name PIOCAPR - Port I/O capability register */ 244 /*! @{ */ 245 246 #define SW_PORT2_PIOCAPR_PCS_PROT_MASK (0xFFFFU) 247 #define SW_PORT2_PIOCAPR_PCS_PROT_SHIFT (0U) 248 #define SW_PORT2_PIOCAPR_PCS_PROT_WIDTH (16U) 249 #define SW_PORT2_PIOCAPR_PCS_PROT(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_PIOCAPR_PCS_PROT_SHIFT)) & SW_PORT2_PIOCAPR_PCS_PROT_MASK) 250 251 #define SW_PORT2_PIOCAPR_IO_VAR_MASK (0xF000000U) 252 #define SW_PORT2_PIOCAPR_IO_VAR_SHIFT (24U) 253 #define SW_PORT2_PIOCAPR_IO_VAR_WIDTH (4U) 254 #define SW_PORT2_PIOCAPR_IO_VAR(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_PIOCAPR_IO_VAR_SHIFT)) & SW_PORT2_PIOCAPR_IO_VAR_MASK) 255 256 #define SW_PORT2_PIOCAPR_EMDIO_MASK (0x10000000U) 257 #define SW_PORT2_PIOCAPR_EMDIO_SHIFT (28U) 258 #define SW_PORT2_PIOCAPR_EMDIO_WIDTH (1U) 259 #define SW_PORT2_PIOCAPR_EMDIO(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_PIOCAPR_EMDIO_SHIFT)) & SW_PORT2_PIOCAPR_EMDIO_MASK) 260 261 #define SW_PORT2_PIOCAPR_REVMII_RATE_MASK (0x40000000U) 262 #define SW_PORT2_PIOCAPR_REVMII_RATE_SHIFT (30U) 263 #define SW_PORT2_PIOCAPR_REVMII_RATE_WIDTH (1U) 264 #define SW_PORT2_PIOCAPR_REVMII_RATE(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_PIOCAPR_REVMII_RATE_SHIFT)) & SW_PORT2_PIOCAPR_REVMII_RATE_MASK) 265 266 #define SW_PORT2_PIOCAPR_REVMII_MASK (0x80000000U) 267 #define SW_PORT2_PIOCAPR_REVMII_SHIFT (31U) 268 #define SW_PORT2_PIOCAPR_REVMII_WIDTH (1U) 269 #define SW_PORT2_PIOCAPR_REVMII(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_PIOCAPR_REVMII_SHIFT)) & SW_PORT2_PIOCAPR_REVMII_MASK) 270 /*! @} */ 271 272 /*! @name PCR - Port configuration register */ 273 /*! @{ */ 274 275 #define SW_PORT2_PCR_HDR_FMT_MASK (0x1U) 276 #define SW_PORT2_PCR_HDR_FMT_SHIFT (0U) 277 #define SW_PORT2_PCR_HDR_FMT_WIDTH (1U) 278 #define SW_PORT2_PCR_HDR_FMT(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_PCR_HDR_FMT_SHIFT)) & SW_PORT2_PCR_HDR_FMT_MASK) 279 280 #define SW_PORT2_PCR_L2DOSE_MASK (0x10U) 281 #define SW_PORT2_PCR_L2DOSE_SHIFT (4U) 282 #define SW_PORT2_PCR_L2DOSE_WIDTH (1U) 283 #define SW_PORT2_PCR_L2DOSE(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_PCR_L2DOSE_SHIFT)) & SW_PORT2_PCR_L2DOSE_MASK) 284 285 #define SW_PORT2_PCR_TIMER_CS_MASK (0x100U) 286 #define SW_PORT2_PCR_TIMER_CS_SHIFT (8U) 287 #define SW_PORT2_PCR_TIMER_CS_WIDTH (1U) 288 #define SW_PORT2_PCR_TIMER_CS(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_PCR_TIMER_CS_SHIFT)) & SW_PORT2_PCR_TIMER_CS_MASK) 289 290 #define SW_PORT2_PCR_FCSEA_MASK (0x1000U) 291 #define SW_PORT2_PCR_FCSEA_SHIFT (12U) 292 #define SW_PORT2_PCR_FCSEA_WIDTH (1U) 293 #define SW_PORT2_PCR_FCSEA(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_PCR_FCSEA_SHIFT)) & SW_PORT2_PCR_FCSEA_MASK) 294 295 #define SW_PORT2_PCR_PSPEED_MASK (0x3FFF0000U) 296 #define SW_PORT2_PCR_PSPEED_SHIFT (16U) 297 #define SW_PORT2_PCR_PSPEED_WIDTH (14U) 298 #define SW_PORT2_PCR_PSPEED(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_PCR_PSPEED_SHIFT)) & SW_PORT2_PCR_PSPEED_MASK) 299 /*! @} */ 300 301 /*! @name PMAR0 - Port MAC address register 0 */ 302 /*! @{ */ 303 304 #define SW_PORT2_PMAR0_PRIM_MAC_ADDR_MASK (0xFFFFFFFFU) 305 #define SW_PORT2_PMAR0_PRIM_MAC_ADDR_SHIFT (0U) 306 #define SW_PORT2_PMAR0_PRIM_MAC_ADDR_WIDTH (32U) 307 #define SW_PORT2_PMAR0_PRIM_MAC_ADDR(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_PMAR0_PRIM_MAC_ADDR_SHIFT)) & SW_PORT2_PMAR0_PRIM_MAC_ADDR_MASK) 308 /*! @} */ 309 310 /*! @name PMAR1 - Port MAC address register 1 */ 311 /*! @{ */ 312 313 #define SW_PORT2_PMAR1_PRIM_MAC_ADDR_MASK (0xFFFFU) 314 #define SW_PORT2_PMAR1_PRIM_MAC_ADDR_SHIFT (0U) 315 #define SW_PORT2_PMAR1_PRIM_MAC_ADDR_WIDTH (16U) 316 #define SW_PORT2_PMAR1_PRIM_MAC_ADDR(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_PMAR1_PRIM_MAC_ADDR_SHIFT)) & SW_PORT2_PMAR1_PRIM_MAC_ADDR_MASK) 317 /*! @} */ 318 319 /*! @name PTAR - Port TPID acceptance register */ 320 /*! @{ */ 321 322 #define SW_PORT2_PTAR_OVTPIDL_MASK (0xFU) 323 #define SW_PORT2_PTAR_OVTPIDL_SHIFT (0U) 324 #define SW_PORT2_PTAR_OVTPIDL_WIDTH (4U) 325 #define SW_PORT2_PTAR_OVTPIDL(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_PTAR_OVTPIDL_SHIFT)) & SW_PORT2_PTAR_OVTPIDL_MASK) 326 327 #define SW_PORT2_PTAR_IVTPIDL_MASK (0xF0U) 328 #define SW_PORT2_PTAR_IVTPIDL_SHIFT (4U) 329 #define SW_PORT2_PTAR_IVTPIDL_WIDTH (4U) 330 #define SW_PORT2_PTAR_IVTPIDL(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_PTAR_IVTPIDL_SHIFT)) & SW_PORT2_PTAR_IVTPIDL_MASK) 331 /*! @} */ 332 333 /*! @name PQOSMR - Port QoS mode register */ 334 /*! @{ */ 335 336 #define SW_PORT2_PQOSMR_VS_MASK (0x1U) 337 #define SW_PORT2_PQOSMR_VS_SHIFT (0U) 338 #define SW_PORT2_PQOSMR_VS_WIDTH (1U) 339 #define SW_PORT2_PQOSMR_VS(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_PQOSMR_VS_SHIFT)) & SW_PORT2_PQOSMR_VS_MASK) 340 341 #define SW_PORT2_PQOSMR_VE_MASK (0x2U) 342 #define SW_PORT2_PQOSMR_VE_SHIFT (1U) 343 #define SW_PORT2_PQOSMR_VE_WIDTH (1U) 344 #define SW_PORT2_PQOSMR_VE(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_PQOSMR_VE_SHIFT)) & SW_PORT2_PQOSMR_VE_MASK) 345 346 #define SW_PORT2_PQOSMR_DDR_MASK (0xCU) 347 #define SW_PORT2_PQOSMR_DDR_SHIFT (2U) 348 #define SW_PORT2_PQOSMR_DDR_WIDTH (2U) 349 #define SW_PORT2_PQOSMR_DDR(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_PQOSMR_DDR_SHIFT)) & SW_PORT2_PQOSMR_DDR_MASK) 350 351 #define SW_PORT2_PQOSMR_DIPV_MASK (0x70U) 352 #define SW_PORT2_PQOSMR_DIPV_SHIFT (4U) 353 #define SW_PORT2_PQOSMR_DIPV_WIDTH (3U) 354 #define SW_PORT2_PQOSMR_DIPV(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_PQOSMR_DIPV_SHIFT)) & SW_PORT2_PQOSMR_DIPV_MASK) 355 356 #define SW_PORT2_PQOSMR_VQMP_MASK (0xF0000U) 357 #define SW_PORT2_PQOSMR_VQMP_SHIFT (16U) 358 #define SW_PORT2_PQOSMR_VQMP_WIDTH (4U) 359 #define SW_PORT2_PQOSMR_VQMP(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_PQOSMR_VQMP_SHIFT)) & SW_PORT2_PQOSMR_VQMP_MASK) 360 361 #define SW_PORT2_PQOSMR_QVMP_MASK (0xF00000U) 362 #define SW_PORT2_PQOSMR_QVMP_SHIFT (20U) 363 #define SW_PORT2_PQOSMR_QVMP_WIDTH (4U) 364 #define SW_PORT2_PQOSMR_QVMP(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_PQOSMR_QVMP_SHIFT)) & SW_PORT2_PQOSMR_QVMP_MASK) 365 /*! @} */ 366 367 /*! @name PQOR - Port Queue Operational register */ 368 /*! @{ */ 369 370 #define SW_PORT2_PQOR_Q0S_MASK (0x1U) 371 #define SW_PORT2_PQOR_Q0S_SHIFT (0U) 372 #define SW_PORT2_PQOR_Q0S_WIDTH (1U) 373 #define SW_PORT2_PQOR_Q0S(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_PQOR_Q0S_SHIFT)) & SW_PORT2_PQOR_Q0S_MASK) 374 375 #define SW_PORT2_PQOR_Q1S_MASK (0x2U) 376 #define SW_PORT2_PQOR_Q1S_SHIFT (1U) 377 #define SW_PORT2_PQOR_Q1S_WIDTH (1U) 378 #define SW_PORT2_PQOR_Q1S(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_PQOR_Q1S_SHIFT)) & SW_PORT2_PQOR_Q1S_MASK) 379 380 #define SW_PORT2_PQOR_Q2S_MASK (0x4U) 381 #define SW_PORT2_PQOR_Q2S_SHIFT (2U) 382 #define SW_PORT2_PQOR_Q2S_WIDTH (1U) 383 #define SW_PORT2_PQOR_Q2S(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_PQOR_Q2S_SHIFT)) & SW_PORT2_PQOR_Q2S_MASK) 384 385 #define SW_PORT2_PQOR_Q3S_MASK (0x8U) 386 #define SW_PORT2_PQOR_Q3S_SHIFT (3U) 387 #define SW_PORT2_PQOR_Q3S_WIDTH (1U) 388 #define SW_PORT2_PQOR_Q3S(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_PQOR_Q3S_SHIFT)) & SW_PORT2_PQOR_Q3S_MASK) 389 390 #define SW_PORT2_PQOR_Q4S_MASK (0x10U) 391 #define SW_PORT2_PQOR_Q4S_SHIFT (4U) 392 #define SW_PORT2_PQOR_Q4S_WIDTH (1U) 393 #define SW_PORT2_PQOR_Q4S(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_PQOR_Q4S_SHIFT)) & SW_PORT2_PQOR_Q4S_MASK) 394 395 #define SW_PORT2_PQOR_Q5S_MASK (0x20U) 396 #define SW_PORT2_PQOR_Q5S_SHIFT (5U) 397 #define SW_PORT2_PQOR_Q5S_WIDTH (1U) 398 #define SW_PORT2_PQOR_Q5S(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_PQOR_Q5S_SHIFT)) & SW_PORT2_PQOR_Q5S_MASK) 399 400 #define SW_PORT2_PQOR_Q6S_MASK (0x40U) 401 #define SW_PORT2_PQOR_Q6S_SHIFT (6U) 402 #define SW_PORT2_PQOR_Q6S_WIDTH (1U) 403 #define SW_PORT2_PQOR_Q6S(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_PQOR_Q6S_SHIFT)) & SW_PORT2_PQOR_Q6S_MASK) 404 405 #define SW_PORT2_PQOR_Q7S_MASK (0x80U) 406 #define SW_PORT2_PQOR_Q7S_SHIFT (7U) 407 #define SW_PORT2_PQOR_Q7S_WIDTH (1U) 408 #define SW_PORT2_PQOR_Q7S(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_PQOR_Q7S_SHIFT)) & SW_PORT2_PQOR_Q7S_MASK) 409 /*! @} */ 410 411 /*! @name PPCR - Port parser configuration register */ 412 /*! @{ */ 413 414 #define SW_PORT2_PPCR_L1PFS_MASK (0x3EU) 415 #define SW_PORT2_PPCR_L1PFS_SHIFT (1U) 416 #define SW_PORT2_PPCR_L1PFS_WIDTH (5U) 417 #define SW_PORT2_PPCR_L1PFS(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_PPCR_L1PFS_SHIFT)) & SW_PORT2_PPCR_L1PFS_MASK) 418 419 #define SW_PORT2_PPCR_L2PFS_MASK (0x3E00U) 420 #define SW_PORT2_PPCR_L2PFS_SHIFT (9U) 421 #define SW_PORT2_PPCR_L2PFS_WIDTH (5U) 422 #define SW_PORT2_PPCR_L2PFS(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_PPCR_L2PFS_SHIFT)) & SW_PORT2_PPCR_L2PFS_MASK) 423 424 #define SW_PORT2_PPCR_L3HFP_MASK (0x10000U) 425 #define SW_PORT2_PPCR_L3HFP_SHIFT (16U) 426 #define SW_PORT2_PPCR_L3HFP_WIDTH (1U) 427 #define SW_PORT2_PPCR_L3HFP(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_PPCR_L3HFP_SHIFT)) & SW_PORT2_PPCR_L3HFP_MASK) 428 429 #define SW_PORT2_PPCR_L3PFS_MASK (0x3E0000U) 430 #define SW_PORT2_PPCR_L3PFS_SHIFT (17U) 431 #define SW_PORT2_PPCR_L3PFS_WIDTH (5U) 432 #define SW_PORT2_PPCR_L3PFS(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_PPCR_L3PFS_SHIFT)) & SW_PORT2_PPCR_L3PFS_MASK) 433 434 #define SW_PORT2_PPCR_L4HFP_MASK (0x1000000U) 435 #define SW_PORT2_PPCR_L4HFP_SHIFT (24U) 436 #define SW_PORT2_PPCR_L4HFP_WIDTH (1U) 437 #define SW_PORT2_PPCR_L4HFP(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_PPCR_L4HFP_SHIFT)) & SW_PORT2_PPCR_L4HFP_MASK) 438 439 #define SW_PORT2_PPCR_L4PFS_MASK (0x3E000000U) 440 #define SW_PORT2_PPCR_L4PFS_SHIFT (25U) 441 #define SW_PORT2_PPCR_L4PFS_WIDTH (5U) 442 #define SW_PORT2_PPCR_L4PFS(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_PPCR_L4PFS_SHIFT)) & SW_PORT2_PPCR_L4PFS_MASK) 443 /*! @} */ 444 445 /*! @name PIPFCR - Port ingress port filter configuration register */ 446 /*! @{ */ 447 448 #define SW_PORT2_PIPFCR_EN_MASK (0x1U) 449 #define SW_PORT2_PIPFCR_EN_SHIFT (0U) 450 #define SW_PORT2_PIPFCR_EN_WIDTH (1U) 451 #define SW_PORT2_PIPFCR_EN(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_PIPFCR_EN_SHIFT)) & SW_PORT2_PIPFCR_EN_MASK) 452 /*! @} */ 453 454 /*! @name PSGCR - Port stream gate configuration register */ 455 /*! @{ */ 456 457 #define SW_PORT2_PSGCR_PDELAY_MASK (0xFFFFFFU) 458 #define SW_PORT2_PSGCR_PDELAY_SHIFT (0U) 459 #define SW_PORT2_PSGCR_PDELAY_WIDTH (24U) 460 #define SW_PORT2_PSGCR_PDELAY(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_PSGCR_PDELAY_SHIFT)) & SW_PORT2_PSGCR_PDELAY_MASK) 461 462 #define SW_PORT2_PSGCR_OGC_MASK (0x80000000U) 463 #define SW_PORT2_PSGCR_OGC_SHIFT (31U) 464 #define SW_PORT2_PSGCR_OGC_WIDTH (1U) 465 #define SW_PORT2_PSGCR_OGC(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_PSGCR_OGC_SHIFT)) & SW_PORT2_PSGCR_OGC_MASK) 466 /*! @} */ 467 468 /*! @name POR - Port operational register */ 469 /*! @{ */ 470 471 #define SW_PORT2_POR_TXDIS_MASK (0x1U) 472 #define SW_PORT2_POR_TXDIS_SHIFT (0U) 473 #define SW_PORT2_POR_TXDIS_WIDTH (1U) 474 #define SW_PORT2_POR_TXDIS(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_POR_TXDIS_SHIFT)) & SW_PORT2_POR_TXDIS_MASK) 475 476 #define SW_PORT2_POR_RXDIS_MASK (0x2U) 477 #define SW_PORT2_POR_RXDIS_SHIFT (1U) 478 #define SW_PORT2_POR_RXDIS_WIDTH (1U) 479 #define SW_PORT2_POR_RXDIS(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_POR_RXDIS_SHIFT)) & SW_PORT2_POR_RXDIS_MASK) 480 /*! @} */ 481 482 /*! @name PSR - Port status register */ 483 /*! @{ */ 484 485 #define SW_PORT2_PSR_TX_BUSY_MASK (0x1U) 486 #define SW_PORT2_PSR_TX_BUSY_SHIFT (0U) 487 #define SW_PORT2_PSR_TX_BUSY_WIDTH (1U) 488 #define SW_PORT2_PSR_TX_BUSY(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_PSR_TX_BUSY_SHIFT)) & SW_PORT2_PSR_TX_BUSY_MASK) 489 490 #define SW_PORT2_PSR_RX_BUSY_MASK (0x2U) 491 #define SW_PORT2_PSR_RX_BUSY_SHIFT (1U) 492 #define SW_PORT2_PSR_RX_BUSY_WIDTH (1U) 493 #define SW_PORT2_PSR_RX_BUSY(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_PSR_RX_BUSY_SHIFT)) & SW_PORT2_PSR_RX_BUSY_MASK) 494 /*! @} */ 495 496 /*! @name PRXSDUOR - Port receive SDU overhead register */ 497 /*! @{ */ 498 499 #define SW_PORT2_PRXSDUOR_PPDU_BCO_MASK (0x1FU) 500 #define SW_PORT2_PRXSDUOR_PPDU_BCO_SHIFT (0U) 501 #define SW_PORT2_PRXSDUOR_PPDU_BCO_WIDTH (5U) 502 #define SW_PORT2_PRXSDUOR_PPDU_BCO(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_PRXSDUOR_PPDU_BCO_SHIFT)) & SW_PORT2_PRXSDUOR_PPDU_BCO_MASK) 503 504 #define SW_PORT2_PRXSDUOR_MACSEC_BCO_MASK (0x1F00U) 505 #define SW_PORT2_PRXSDUOR_MACSEC_BCO_SHIFT (8U) 506 #define SW_PORT2_PRXSDUOR_MACSEC_BCO_WIDTH (5U) 507 #define SW_PORT2_PRXSDUOR_MACSEC_BCO(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_PRXSDUOR_MACSEC_BCO_SHIFT)) & SW_PORT2_PRXSDUOR_MACSEC_BCO_MASK) 508 /*! @} */ 509 510 /*! @name PTXSDUOR - Port transmit SDU overhead register */ 511 /*! @{ */ 512 513 #define SW_PORT2_PTXSDUOR_PPDU_BCO_MASK (0x1FU) 514 #define SW_PORT2_PTXSDUOR_PPDU_BCO_SHIFT (0U) 515 #define SW_PORT2_PTXSDUOR_PPDU_BCO_WIDTH (5U) 516 #define SW_PORT2_PTXSDUOR_PPDU_BCO(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_PTXSDUOR_PPDU_BCO_SHIFT)) & SW_PORT2_PTXSDUOR_PPDU_BCO_MASK) 517 518 #define SW_PORT2_PTXSDUOR_MACSEC_BCO_MASK (0x1F00U) 519 #define SW_PORT2_PTXSDUOR_MACSEC_BCO_SHIFT (8U) 520 #define SW_PORT2_PTXSDUOR_MACSEC_BCO_WIDTH (5U) 521 #define SW_PORT2_PTXSDUOR_MACSEC_BCO(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_PTXSDUOR_MACSEC_BCO_SHIFT)) & SW_PORT2_PTXSDUOR_MACSEC_BCO_MASK) 522 /*! @} */ 523 524 /*! @name PTGSCR - Port time gate scheduling control register */ 525 /*! @{ */ 526 527 #define SW_PORT2_PTGSCR_TGE_MASK (0x80000000U) 528 #define SW_PORT2_PTGSCR_TGE_SHIFT (31U) 529 #define SW_PORT2_PTGSCR_TGE_WIDTH (1U) 530 #define SW_PORT2_PTGSCR_TGE(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_PTGSCR_TGE_SHIFT)) & SW_PORT2_PTGSCR_TGE_MASK) 531 /*! @} */ 532 533 /*! @name PTGAGLSR - Port time gate scheduling admin gate list status register */ 534 /*! @{ */ 535 536 #define SW_PORT2_PTGAGLSR_TG_MASK (0x1U) 537 #define SW_PORT2_PTGAGLSR_TG_SHIFT (0U) 538 #define SW_PORT2_PTGAGLSR_TG_WIDTH (1U) 539 #define SW_PORT2_PTGAGLSR_TG(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_PTGAGLSR_TG_SHIFT)) & SW_PORT2_PTGAGLSR_TG_MASK) 540 541 #define SW_PORT2_PTGAGLSR_CFG_PEND_MASK (0x2U) 542 #define SW_PORT2_PTGAGLSR_CFG_PEND_SHIFT (1U) 543 #define SW_PORT2_PTGAGLSR_CFG_PEND_WIDTH (1U) 544 #define SW_PORT2_PTGAGLSR_CFG_PEND(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_PTGAGLSR_CFG_PEND_SHIFT)) & SW_PORT2_PTGAGLSR_CFG_PEND_MASK) 545 /*! @} */ 546 547 /*! @name PTGAGLLR - Port time gate scheduling admin gate list length register */ 548 /*! @{ */ 549 550 #define SW_PORT2_PTGAGLLR_ADMIN_GATE_LIST_LENGTH_MASK (0xFFFFU) 551 #define SW_PORT2_PTGAGLLR_ADMIN_GATE_LIST_LENGTH_SHIFT (0U) 552 #define SW_PORT2_PTGAGLLR_ADMIN_GATE_LIST_LENGTH_WIDTH (16U) 553 #define SW_PORT2_PTGAGLLR_ADMIN_GATE_LIST_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_PTGAGLLR_ADMIN_GATE_LIST_LENGTH_SHIFT)) & SW_PORT2_PTGAGLLR_ADMIN_GATE_LIST_LENGTH_MASK) 554 /*! @} */ 555 556 /*! @name PTGOGLLR - Port time gating operational gate list length register */ 557 /*! @{ */ 558 559 #define SW_PORT2_PTGOGLLR_OPER_GATE_LIST_LENGTH_MASK (0xFFFFU) 560 #define SW_PORT2_PTGOGLLR_OPER_GATE_LIST_LENGTH_SHIFT (0U) 561 #define SW_PORT2_PTGOGLLR_OPER_GATE_LIST_LENGTH_WIDTH (16U) 562 #define SW_PORT2_PTGOGLLR_OPER_GATE_LIST_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_PTGOGLLR_OPER_GATE_LIST_LENGTH_SHIFT)) & SW_PORT2_PTGOGLLR_OPER_GATE_LIST_LENGTH_MASK) 563 /*! @} */ 564 565 /*! @name PRXDCR - Port Rx discard count register */ 566 /*! @{ */ 567 568 #define SW_PORT2_PRXDCR_COUNT_MASK (0xFFFFFFFFU) 569 #define SW_PORT2_PRXDCR_COUNT_SHIFT (0U) 570 #define SW_PORT2_PRXDCR_COUNT_WIDTH (32U) 571 #define SW_PORT2_PRXDCR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_PRXDCR_COUNT_SHIFT)) & SW_PORT2_PRXDCR_COUNT_MASK) 572 /*! @} */ 573 574 /*! @name PRXDCRR0 - Port Rx discard count reason register 0 */ 575 /*! @{ */ 576 577 #define SW_PORT2_PRXDCRR0_PCDR_MASK (0x1U) 578 #define SW_PORT2_PRXDCRR0_PCDR_SHIFT (0U) 579 #define SW_PORT2_PRXDCRR0_PCDR_WIDTH (1U) 580 #define SW_PORT2_PRXDCRR0_PCDR(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_PRXDCRR0_PCDR_SHIFT)) & SW_PORT2_PRXDCRR0_PCDR_MASK) 581 582 #define SW_PORT2_PRXDCRR0_SMREDR_MASK (0x2U) 583 #define SW_PORT2_PRXDCRR0_SMREDR_SHIFT (1U) 584 #define SW_PORT2_PRXDCRR0_SMREDR_WIDTH (1U) 585 #define SW_PORT2_PRXDCRR0_SMREDR(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_PRXDCRR0_SMREDR_SHIFT)) & SW_PORT2_PRXDCRR0_SMREDR_MASK) 586 587 #define SW_PORT2_PRXDCRR0_RXDISDR_MASK (0x4U) 588 #define SW_PORT2_PRXDCRR0_RXDISDR_SHIFT (2U) 589 #define SW_PORT2_PRXDCRR0_RXDISDR_WIDTH (1U) 590 #define SW_PORT2_PRXDCRR0_RXDISDR(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_PRXDCRR0_RXDISDR_SHIFT)) & SW_PORT2_PRXDCRR0_RXDISDR_MASK) 591 592 #define SW_PORT2_PRXDCRR0_IPFDR_MASK (0x8U) 593 #define SW_PORT2_PRXDCRR0_IPFDR_SHIFT (3U) 594 #define SW_PORT2_PRXDCRR0_IPFDR_WIDTH (1U) 595 #define SW_PORT2_PRXDCRR0_IPFDR(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_PRXDCRR0_IPFDR_SHIFT)) & SW_PORT2_PRXDCRR0_IPFDR_MASK) 596 597 #define SW_PORT2_PRXDCRR0_RPDR_MASK (0x10U) 598 #define SW_PORT2_PRXDCRR0_RPDR_SHIFT (4U) 599 #define SW_PORT2_PRXDCRR0_RPDR_WIDTH (1U) 600 #define SW_PORT2_PRXDCRR0_RPDR(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_PRXDCRR0_RPDR_SHIFT)) & SW_PORT2_PRXDCRR0_RPDR_MASK) 601 602 #define SW_PORT2_PRXDCRR0_ISFDR_MASK (0x20U) 603 #define SW_PORT2_PRXDCRR0_ISFDR_SHIFT (5U) 604 #define SW_PORT2_PRXDCRR0_ISFDR_WIDTH (1U) 605 #define SW_PORT2_PRXDCRR0_ISFDR(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_PRXDCRR0_ISFDR_SHIFT)) & SW_PORT2_PRXDCRR0_ISFDR_MASK) 606 607 #define SW_PORT2_PRXDCRR0_SGCDR_MASK (0x40U) 608 #define SW_PORT2_PRXDCRR0_SGCDR_SHIFT (6U) 609 #define SW_PORT2_PRXDCRR0_SGCDR_WIDTH (1U) 610 #define SW_PORT2_PRXDCRR0_SGCDR(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_PRXDCRR0_SGCDR_SHIFT)) & SW_PORT2_PRXDCRR0_SGCDR_MASK) 611 612 #define SW_PORT2_PRXDCRR0_SGOEDR_MASK (0x80U) 613 #define SW_PORT2_PRXDCRR0_SGOEDR_SHIFT (7U) 614 #define SW_PORT2_PRXDCRR0_SGOEDR_WIDTH (1U) 615 #define SW_PORT2_PRXDCRR0_SGOEDR(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_PRXDCRR0_SGOEDR_SHIFT)) & SW_PORT2_PRXDCRR0_SGOEDR_MASK) 616 617 #define SW_PORT2_PRXDCRR0_MSDUEDR_MASK (0x100U) 618 #define SW_PORT2_PRXDCRR0_MSDUEDR_SHIFT (8U) 619 #define SW_PORT2_PRXDCRR0_MSDUEDR_WIDTH (1U) 620 #define SW_PORT2_PRXDCRR0_MSDUEDR(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_PRXDCRR0_MSDUEDR_SHIFT)) & SW_PORT2_PRXDCRR0_MSDUEDR_MASK) 621 622 #define SW_PORT2_PRXDCRR0_FMMEDR_MASK (0x200U) 623 #define SW_PORT2_PRXDCRR0_FMMEDR_SHIFT (9U) 624 #define SW_PORT2_PRXDCRR0_FMMEDR_WIDTH (1U) 625 #define SW_PORT2_PRXDCRR0_FMMEDR(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_PRXDCRR0_FMMEDR_SHIFT)) & SW_PORT2_PRXDCRR0_FMMEDR_MASK) 626 627 #define SW_PORT2_PRXDCRR0_CMDR_MASK (0x400U) 628 #define SW_PORT2_PRXDCRR0_CMDR_SHIFT (10U) 629 #define SW_PORT2_PRXDCRR0_CMDR_WIDTH (1U) 630 #define SW_PORT2_PRXDCRR0_CMDR(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_PRXDCRR0_CMDR_SHIFT)) & SW_PORT2_PRXDCRR0_CMDR_MASK) 631 632 #define SW_PORT2_PRXDCRR0_ITEDR_MASK (0x800U) 633 #define SW_PORT2_PRXDCRR0_ITEDR_SHIFT (11U) 634 #define SW_PORT2_PRXDCRR0_ITEDR_WIDTH (1U) 635 #define SW_PORT2_PRXDCRR0_ITEDR(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_PRXDCRR0_ITEDR_SHIFT)) & SW_PORT2_PRXDCRR0_ITEDR_MASK) 636 637 #define SW_PORT2_PRXDCRR0_ECCEDR_MASK (0x1000U) 638 #define SW_PORT2_PRXDCRR0_ECCEDR_SHIFT (12U) 639 #define SW_PORT2_PRXDCRR0_ECCEDR_WIDTH (1U) 640 #define SW_PORT2_PRXDCRR0_ECCEDR(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_PRXDCRR0_ECCEDR_SHIFT)) & SW_PORT2_PRXDCRR0_ECCEDR_MASK) 641 642 #define SW_PORT2_PRXDCRR0_L2DOSDR_MASK (0x4000U) 643 #define SW_PORT2_PRXDCRR0_L2DOSDR_SHIFT (14U) 644 #define SW_PORT2_PRXDCRR0_L2DOSDR_WIDTH (1U) 645 #define SW_PORT2_PRXDCRR0_L2DOSDR(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_PRXDCRR0_L2DOSDR_SHIFT)) & SW_PORT2_PRXDCRR0_L2DOSDR_MASK) 646 647 #define SW_PORT2_PRXDCRR0_PEDR_MASK (0x10000U) 648 #define SW_PORT2_PRXDCRR0_PEDR_SHIFT (16U) 649 #define SW_PORT2_PRXDCRR0_PEDR_WIDTH (1U) 650 #define SW_PORT2_PRXDCRR0_PEDR(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_PRXDCRR0_PEDR_SHIFT)) & SW_PORT2_PRXDCRR0_PEDR_MASK) 651 652 #define SW_PORT2_PRXDCRR0_NODESTDR_MASK (0x20000U) 653 #define SW_PORT2_PRXDCRR0_NODESTDR_SHIFT (17U) 654 #define SW_PORT2_PRXDCRR0_NODESTDR_WIDTH (1U) 655 #define SW_PORT2_PRXDCRR0_NODESTDR(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_PRXDCRR0_NODESTDR_SHIFT)) & SW_PORT2_PRXDCRR0_NODESTDR_MASK) 656 /*! @} */ 657 658 /*! @name PRXDCRR1 - Port Rx discard count reason register 1 */ 659 /*! @{ */ 660 661 #define SW_PORT2_PRXDCRR1_ENTRYID_MASK (0xFFFFU) 662 #define SW_PORT2_PRXDCRR1_ENTRYID_SHIFT (0U) 663 #define SW_PORT2_PRXDCRR1_ENTRYID_WIDTH (16U) 664 #define SW_PORT2_PRXDCRR1_ENTRYID(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_PRXDCRR1_ENTRYID_SHIFT)) & SW_PORT2_PRXDCRR1_ENTRYID_MASK) 665 666 #define SW_PORT2_PRXDCRR1_TT_MASK (0xF0000000U) 667 #define SW_PORT2_PRXDCRR1_TT_SHIFT (28U) 668 #define SW_PORT2_PRXDCRR1_TT_WIDTH (4U) 669 #define SW_PORT2_PRXDCRR1_TT(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_PRXDCRR1_TT_SHIFT)) & SW_PORT2_PRXDCRR1_TT_MASK) 670 /*! @} */ 671 672 /*! @name PTXDCR - Port Tx discard count register */ 673 /*! @{ */ 674 675 #define SW_PORT2_PTXDCR_COUNT_MASK (0xFFFFFFFFU) 676 #define SW_PORT2_PTXDCR_COUNT_SHIFT (0U) 677 #define SW_PORT2_PTXDCR_COUNT_WIDTH (32U) 678 #define SW_PORT2_PTXDCR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_PTXDCR_COUNT_SHIFT)) & SW_PORT2_PTXDCR_COUNT_MASK) 679 /*! @} */ 680 681 /*! @name PTXDCRR0 - Port Tx discard count reason register 0 */ 682 /*! @{ */ 683 684 #define SW_PORT2_PTXDCRR0_TXDISDR_MASK (0x1U) 685 #define SW_PORT2_PTXDCRR0_TXDISDR_SHIFT (0U) 686 #define SW_PORT2_PTXDCRR0_TXDISDR_WIDTH (1U) 687 #define SW_PORT2_PTXDCRR0_TXDISDR(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_PTXDCRR0_TXDISDR_SHIFT)) & SW_PORT2_PTXDCRR0_TXDISDR_MASK) 688 689 #define SW_PORT2_PTXDCRR0_ECCEDR_MASK (0x2U) 690 #define SW_PORT2_PTXDCRR0_ECCEDR_SHIFT (1U) 691 #define SW_PORT2_PTXDCRR0_ECCEDR_WIDTH (1U) 692 #define SW_PORT2_PTXDCRR0_ECCEDR(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_PTXDCRR0_ECCEDR_SHIFT)) & SW_PORT2_PTXDCRR0_ECCEDR_MASK) 693 694 #define SW_PORT2_PTXDCRR0_PEDR_MASK (0x4U) 695 #define SW_PORT2_PTXDCRR0_PEDR_SHIFT (2U) 696 #define SW_PORT2_PTXDCRR0_PEDR_WIDTH (1U) 697 #define SW_PORT2_PTXDCRR0_PEDR(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_PTXDCRR0_PEDR_SHIFT)) & SW_PORT2_PTXDCRR0_PEDR_MASK) 698 699 #define SW_PORT2_PTXDCRR0_TGSFTLDR_MASK (0x10U) 700 #define SW_PORT2_PTXDCRR0_TGSFTLDR_SHIFT (4U) 701 #define SW_PORT2_PTXDCRR0_TGSFTLDR_WIDTH (1U) 702 #define SW_PORT2_PTXDCRR0_TGSFTLDR(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_PTXDCRR0_TGSFTLDR_SHIFT)) & SW_PORT2_PTXDCRR0_TGSFTLDR_MASK) 703 704 #define SW_PORT2_PTXDCRR0_FMMDR_MASK (0x20U) 705 #define SW_PORT2_PTXDCRR0_FMMDR_SHIFT (5U) 706 #define SW_PORT2_PTXDCRR0_FMMDR_WIDTH (1U) 707 #define SW_PORT2_PTXDCRR0_FMMDR(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_PTXDCRR0_FMMDR_SHIFT)) & SW_PORT2_PTXDCRR0_FMMDR_MASK) 708 709 #define SW_PORT2_PTXDCRR0_TXDISEDR_MASK (0x40U) 710 #define SW_PORT2_PTXDCRR0_TXDISEDR_SHIFT (6U) 711 #define SW_PORT2_PTXDCRR0_TXDISEDR_WIDTH (1U) 712 #define SW_PORT2_PTXDCRR0_TXDISEDR(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_PTXDCRR0_TXDISEDR_SHIFT)) & SW_PORT2_PTXDCRR0_TXDISEDR_MASK) 713 714 #define SW_PORT2_PTXDCRR0_MSDUEDR_MASK (0x80U) 715 #define SW_PORT2_PTXDCRR0_MSDUEDR_SHIFT (7U) 716 #define SW_PORT2_PTXDCRR0_MSDUEDR_WIDTH (1U) 717 #define SW_PORT2_PTXDCRR0_MSDUEDR(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_PTXDCRR0_MSDUEDR_SHIFT)) & SW_PORT2_PTXDCRR0_MSDUEDR_MASK) 718 719 #define SW_PORT2_PTXDCRR0_QCONGDR_MASK (0x100U) 720 #define SW_PORT2_PTXDCRR0_QCONGDR_SHIFT (8U) 721 #define SW_PORT2_PTXDCRR0_QCONGDR_WIDTH (1U) 722 #define SW_PORT2_PTXDCRR0_QCONGDR(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_PTXDCRR0_QCONGDR_SHIFT)) & SW_PORT2_PTXDCRR0_QCONGDR_MASK) 723 724 #define SW_PORT2_PTXDCRR0_ITEDR_MASK (0x200U) 725 #define SW_PORT2_PTXDCRR0_ITEDR_SHIFT (9U) 726 #define SW_PORT2_PTXDCRR0_ITEDR_WIDTH (1U) 727 #define SW_PORT2_PTXDCRR0_ITEDR(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_PTXDCRR0_ITEDR_SHIFT)) & SW_PORT2_PTXDCRR0_ITEDR_MASK) 728 729 #define SW_PORT2_PTXDCRR0_INVEQDR_MASK (0x400U) 730 #define SW_PORT2_PTXDCRR0_INVEQDR_SHIFT (10U) 731 #define SW_PORT2_PTXDCRR0_INVEQDR_WIDTH (1U) 732 #define SW_PORT2_PTXDCRR0_INVEQDR(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_PTXDCRR0_INVEQDR_SHIFT)) & SW_PORT2_PTXDCRR0_INVEQDR_MASK) 733 734 #define SW_PORT2_PTXDCRR0_SQRTNSQDR_MASK (0x800U) 735 #define SW_PORT2_PTXDCRR0_SQRTNSQDR_SHIFT (11U) 736 #define SW_PORT2_PTXDCRR0_SQRTNSQDR_WIDTH (1U) 737 #define SW_PORT2_PTXDCRR0_SQRTNSQDR(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_PTXDCRR0_SQRTNSQDR_SHIFT)) & SW_PORT2_PTXDCRR0_SQRTNSQDR_MASK) 738 739 #define SW_PORT2_PTXDCRR0_SQRRDR_MASK (0x2000U) 740 #define SW_PORT2_PTXDCRR0_SQRRDR_SHIFT (13U) 741 #define SW_PORT2_PTXDCRR0_SQRRDR_WIDTH (1U) 742 #define SW_PORT2_PTXDCRR0_SQRRDR(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_PTXDCRR0_SQRRDR_SHIFT)) & SW_PORT2_PTXDCRR0_SQRRDR_MASK) 743 744 #define SW_PORT2_PTXDCRR0_SQRDDR_MASK (0x4000U) 745 #define SW_PORT2_PTXDCRR0_SQRDDR_SHIFT (14U) 746 #define SW_PORT2_PTXDCRR0_SQRDDR_WIDTH (1U) 747 #define SW_PORT2_PTXDCRR0_SQRDDR(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_PTXDCRR0_SQRDDR_SHIFT)) & SW_PORT2_PTXDCRR0_SQRDDR_MASK) 748 749 #define SW_PORT2_PTXDCRR0_SMREDR_MASK (0x8000U) 750 #define SW_PORT2_PTXDCRR0_SMREDR_SHIFT (15U) 751 #define SW_PORT2_PTXDCRR0_SMREDR_WIDTH (1U) 752 #define SW_PORT2_PTXDCRR0_SMREDR(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_PTXDCRR0_SMREDR_SHIFT)) & SW_PORT2_PTXDCRR0_SMREDR_MASK) 753 /*! @} */ 754 755 /*! @name PTXDCRR1 - Port Tx discard count reason register 1 */ 756 /*! @{ */ 757 758 #define SW_PORT2_PTXDCRR1_ENTRYID_MASK (0xFFFFU) 759 #define SW_PORT2_PTXDCRR1_ENTRYID_SHIFT (0U) 760 #define SW_PORT2_PTXDCRR1_ENTRYID_WIDTH (16U) 761 #define SW_PORT2_PTXDCRR1_ENTRYID(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_PTXDCRR1_ENTRYID_SHIFT)) & SW_PORT2_PTXDCRR1_ENTRYID_MASK) 762 763 #define SW_PORT2_PTXDCRR1_TT_MASK (0xF0000000U) 764 #define SW_PORT2_PTXDCRR1_TT_SHIFT (28U) 765 #define SW_PORT2_PTXDCRR1_TT_WIDTH (4U) 766 #define SW_PORT2_PTXDCRR1_TT(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_PTXDCRR1_TT_SHIFT)) & SW_PORT2_PTXDCRR1_TT_MASK) 767 /*! @} */ 768 769 /*! @name PTGSTCSR - Port time gate scheduling traffic class 0 status register..Port time gate scheduling traffic class 7 status register */ 770 /*! @{ */ 771 772 #define SW_PORT2_PTGSTCSR_LH_STATE_MASK (0x10000U) 773 #define SW_PORT2_PTGSTCSR_LH_STATE_SHIFT (16U) 774 #define SW_PORT2_PTGSTCSR_LH_STATE_WIDTH (1U) 775 #define SW_PORT2_PTGSTCSR_LH_STATE(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_PTGSTCSR_LH_STATE_SHIFT)) & SW_PORT2_PTGSTCSR_LH_STATE_MASK) 776 /*! @} */ 777 778 /*! @name PTCTMSDUR - Port traffic class 0 transmit maximum SDU register..Port traffic class 7 transmit maximum SDU register */ 779 /*! @{ */ 780 781 #define SW_PORT2_PTCTMSDUR_MAXSDU_MASK (0xFFFFU) 782 #define SW_PORT2_PTCTMSDUR_MAXSDU_SHIFT (0U) 783 #define SW_PORT2_PTCTMSDUR_MAXSDU_WIDTH (16U) 784 #define SW_PORT2_PTCTMSDUR_MAXSDU(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_PTCTMSDUR_MAXSDU_SHIFT)) & SW_PORT2_PTCTMSDUR_MAXSDU_MASK) 785 786 #define SW_PORT2_PTCTMSDUR_SDU_TYPE_MASK (0x30000U) 787 #define SW_PORT2_PTCTMSDUR_SDU_TYPE_SHIFT (16U) 788 #define SW_PORT2_PTCTMSDUR_SDU_TYPE_WIDTH (2U) 789 #define SW_PORT2_PTCTMSDUR_SDU_TYPE(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_PTCTMSDUR_SDU_TYPE_SHIFT)) & SW_PORT2_PTCTMSDUR_SDU_TYPE_MASK) 790 791 #define SW_PORT2_PTCTMSDUR_SF_MAXSDU_DIS_MASK (0x1000000U) 792 #define SW_PORT2_PTCTMSDUR_SF_MAXSDU_DIS_SHIFT (24U) 793 #define SW_PORT2_PTCTMSDUR_SF_MAXSDU_DIS_WIDTH (1U) 794 #define SW_PORT2_PTCTMSDUR_SF_MAXSDU_DIS(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_PTCTMSDUR_SF_MAXSDU_DIS_SHIFT)) & SW_PORT2_PTCTMSDUR_SF_MAXSDU_DIS_MASK) 795 /*! @} */ 796 797 /*! @name PTCCBSR0 - Port transmit traffic class 0 credit based shaper register 0..Port transmit traffic class 7 credit based shaper register 0 */ 798 /*! @{ */ 799 800 #define SW_PORT2_PTCCBSR0_BW_MASK (0x7FU) 801 #define SW_PORT2_PTCCBSR0_BW_SHIFT (0U) 802 #define SW_PORT2_PTCCBSR0_BW_WIDTH (7U) 803 #define SW_PORT2_PTCCBSR0_BW(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_PTCCBSR0_BW_SHIFT)) & SW_PORT2_PTCCBSR0_BW_MASK) 804 805 #define SW_PORT2_PTCCBSR0_CBSE_MASK (0x80000000U) 806 #define SW_PORT2_PTCCBSR0_CBSE_SHIFT (31U) 807 #define SW_PORT2_PTCCBSR0_CBSE_WIDTH (1U) 808 #define SW_PORT2_PTCCBSR0_CBSE(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_PTCCBSR0_CBSE_SHIFT)) & SW_PORT2_PTCCBSR0_CBSE_MASK) 809 /*! @} */ 810 811 /*! @name PTCCBSR1 - Port traffic class 0 credit based shaper register 1..Port traffic class 7 credit based shaper register 1 */ 812 /*! @{ */ 813 814 #define SW_PORT2_PTCCBSR1_HI_CREDIT_MASK (0xFFFFFFFFU) 815 #define SW_PORT2_PTCCBSR1_HI_CREDIT_SHIFT (0U) 816 #define SW_PORT2_PTCCBSR1_HI_CREDIT_WIDTH (32U) 817 #define SW_PORT2_PTCCBSR1_HI_CREDIT(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_PTCCBSR1_HI_CREDIT_SHIFT)) & SW_PORT2_PTCCBSR1_HI_CREDIT_MASK) 818 /*! @} */ 819 820 /*! @name PBPMCR0 - Port buffer pool mapping configuration register 0 */ 821 /*! @{ */ 822 823 #define SW_PORT2_PBPMCR0_IPV0_INDEX_MASK (0xFFU) 824 #define SW_PORT2_PBPMCR0_IPV0_INDEX_SHIFT (0U) 825 #define SW_PORT2_PBPMCR0_IPV0_INDEX_WIDTH (8U) 826 #define SW_PORT2_PBPMCR0_IPV0_INDEX(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_PBPMCR0_IPV0_INDEX_SHIFT)) & SW_PORT2_PBPMCR0_IPV0_INDEX_MASK) 827 828 #define SW_PORT2_PBPMCR0_IPV1_INDEX_MASK (0xFF00U) 829 #define SW_PORT2_PBPMCR0_IPV1_INDEX_SHIFT (8U) 830 #define SW_PORT2_PBPMCR0_IPV1_INDEX_WIDTH (8U) 831 #define SW_PORT2_PBPMCR0_IPV1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_PBPMCR0_IPV1_INDEX_SHIFT)) & SW_PORT2_PBPMCR0_IPV1_INDEX_MASK) 832 833 #define SW_PORT2_PBPMCR0_IPV2_INDEX_MASK (0xFF0000U) 834 #define SW_PORT2_PBPMCR0_IPV2_INDEX_SHIFT (16U) 835 #define SW_PORT2_PBPMCR0_IPV2_INDEX_WIDTH (8U) 836 #define SW_PORT2_PBPMCR0_IPV2_INDEX(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_PBPMCR0_IPV2_INDEX_SHIFT)) & SW_PORT2_PBPMCR0_IPV2_INDEX_MASK) 837 838 #define SW_PORT2_PBPMCR0_IPV3_INDEX_MASK (0xFF000000U) 839 #define SW_PORT2_PBPMCR0_IPV3_INDEX_SHIFT (24U) 840 #define SW_PORT2_PBPMCR0_IPV3_INDEX_WIDTH (8U) 841 #define SW_PORT2_PBPMCR0_IPV3_INDEX(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_PBPMCR0_IPV3_INDEX_SHIFT)) & SW_PORT2_PBPMCR0_IPV3_INDEX_MASK) 842 /*! @} */ 843 844 /*! @name PBPMCR1 - Port buffer pool mapping configuration register 1 */ 845 /*! @{ */ 846 847 #define SW_PORT2_PBPMCR1_IPV4_INDEX_MASK (0xFFU) 848 #define SW_PORT2_PBPMCR1_IPV4_INDEX_SHIFT (0U) 849 #define SW_PORT2_PBPMCR1_IPV4_INDEX_WIDTH (8U) 850 #define SW_PORT2_PBPMCR1_IPV4_INDEX(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_PBPMCR1_IPV4_INDEX_SHIFT)) & SW_PORT2_PBPMCR1_IPV4_INDEX_MASK) 851 852 #define SW_PORT2_PBPMCR1_IPV5_INDEX_MASK (0xFF00U) 853 #define SW_PORT2_PBPMCR1_IPV5_INDEX_SHIFT (8U) 854 #define SW_PORT2_PBPMCR1_IPV5_INDEX_WIDTH (8U) 855 #define SW_PORT2_PBPMCR1_IPV5_INDEX(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_PBPMCR1_IPV5_INDEX_SHIFT)) & SW_PORT2_PBPMCR1_IPV5_INDEX_MASK) 856 857 #define SW_PORT2_PBPMCR1_IPV6_INDEX_MASK (0xFF0000U) 858 #define SW_PORT2_PBPMCR1_IPV6_INDEX_SHIFT (16U) 859 #define SW_PORT2_PBPMCR1_IPV6_INDEX_WIDTH (8U) 860 #define SW_PORT2_PBPMCR1_IPV6_INDEX(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_PBPMCR1_IPV6_INDEX_SHIFT)) & SW_PORT2_PBPMCR1_IPV6_INDEX_MASK) 861 862 #define SW_PORT2_PBPMCR1_IPV7_INDEX_MASK (0xFF000000U) 863 #define SW_PORT2_PBPMCR1_IPV7_INDEX_SHIFT (24U) 864 #define SW_PORT2_PBPMCR1_IPV7_INDEX_WIDTH (8U) 865 #define SW_PORT2_PBPMCR1_IPV7_INDEX(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_PBPMCR1_IPV7_INDEX_SHIFT)) & SW_PORT2_PBPMCR1_IPV7_INDEX_MASK) 866 /*! @} */ 867 868 /*! @name PPCPDEIMR - Port PCP DEI mapping register */ 869 /*! @{ */ 870 871 #define SW_PORT2_PPCPDEIMR_IPCPMP_MASK (0xFU) 872 #define SW_PORT2_PPCPDEIMR_IPCPMP_SHIFT (0U) 873 #define SW_PORT2_PPCPDEIMR_IPCPMP_WIDTH (4U) 874 #define SW_PORT2_PPCPDEIMR_IPCPMP(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_PPCPDEIMR_IPCPMP_SHIFT)) & SW_PORT2_PPCPDEIMR_IPCPMP_MASK) 875 876 #define SW_PORT2_PPCPDEIMR_IPCPMPV_MASK (0x80U) 877 #define SW_PORT2_PPCPDEIMR_IPCPMPV_SHIFT (7U) 878 #define SW_PORT2_PPCPDEIMR_IPCPMPV_WIDTH (1U) 879 #define SW_PORT2_PPCPDEIMR_IPCPMPV(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_PPCPDEIMR_IPCPMPV_SHIFT)) & SW_PORT2_PPCPDEIMR_IPCPMPV_MASK) 880 881 #define SW_PORT2_PPCPDEIMR_EPCPMP_MASK (0xF00U) 882 #define SW_PORT2_PPCPDEIMR_EPCPMP_SHIFT (8U) 883 #define SW_PORT2_PPCPDEIMR_EPCPMP_WIDTH (4U) 884 #define SW_PORT2_PPCPDEIMR_EPCPMP(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_PPCPDEIMR_EPCPMP_SHIFT)) & SW_PORT2_PPCPDEIMR_EPCPMP_MASK) 885 886 #define SW_PORT2_PPCPDEIMR_EPCPMPV_MASK (0x8000U) 887 #define SW_PORT2_PPCPDEIMR_EPCPMPV_SHIFT (15U) 888 #define SW_PORT2_PPCPDEIMR_EPCPMPV_WIDTH (1U) 889 #define SW_PORT2_PPCPDEIMR_EPCPMPV(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_PPCPDEIMR_EPCPMPV_SHIFT)) & SW_PORT2_PPCPDEIMR_EPCPMPV_MASK) 890 891 #define SW_PORT2_PPCPDEIMR_DR0DEI_MASK (0x10000U) 892 #define SW_PORT2_PPCPDEIMR_DR0DEI_SHIFT (16U) 893 #define SW_PORT2_PPCPDEIMR_DR0DEI_WIDTH (1U) 894 #define SW_PORT2_PPCPDEIMR_DR0DEI(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_PPCPDEIMR_DR0DEI_SHIFT)) & SW_PORT2_PPCPDEIMR_DR0DEI_MASK) 895 896 #define SW_PORT2_PPCPDEIMR_DR1DEI_MASK (0x20000U) 897 #define SW_PORT2_PPCPDEIMR_DR1DEI_SHIFT (17U) 898 #define SW_PORT2_PPCPDEIMR_DR1DEI_WIDTH (1U) 899 #define SW_PORT2_PPCPDEIMR_DR1DEI(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_PPCPDEIMR_DR1DEI_SHIFT)) & SW_PORT2_PPCPDEIMR_DR1DEI_MASK) 900 901 #define SW_PORT2_PPCPDEIMR_DR2DEI_MASK (0x40000U) 902 #define SW_PORT2_PPCPDEIMR_DR2DEI_SHIFT (18U) 903 #define SW_PORT2_PPCPDEIMR_DR2DEI_WIDTH (1U) 904 #define SW_PORT2_PPCPDEIMR_DR2DEI(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_PPCPDEIMR_DR2DEI_SHIFT)) & SW_PORT2_PPCPDEIMR_DR2DEI_MASK) 905 906 #define SW_PORT2_PPCPDEIMR_DR3DEI_MASK (0x80000U) 907 #define SW_PORT2_PPCPDEIMR_DR3DEI_SHIFT (19U) 908 #define SW_PORT2_PPCPDEIMR_DR3DEI_WIDTH (1U) 909 #define SW_PORT2_PPCPDEIMR_DR3DEI(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_PPCPDEIMR_DR3DEI_SHIFT)) & SW_PORT2_PPCPDEIMR_DR3DEI_MASK) 910 911 #define SW_PORT2_PPCPDEIMR_DRME_MASK (0x100000U) 912 #define SW_PORT2_PPCPDEIMR_DRME_SHIFT (20U) 913 #define SW_PORT2_PPCPDEIMR_DRME_WIDTH (1U) 914 #define SW_PORT2_PPCPDEIMR_DRME(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_PPCPDEIMR_DRME_SHIFT)) & SW_PORT2_PPCPDEIMR_DRME_MASK) 915 /*! @} */ 916 917 /*! @name PMCR - Port mirror configuration register */ 918 /*! @{ */ 919 920 #define SW_PORT2_PMCR_IMIRE_MASK (0x1U) 921 #define SW_PORT2_PMCR_IMIRE_SHIFT (0U) 922 #define SW_PORT2_PMCR_IMIRE_WIDTH (1U) 923 #define SW_PORT2_PMCR_IMIRE(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_PMCR_IMIRE_SHIFT)) & SW_PORT2_PMCR_IMIRE_MASK) 924 /*! @} */ 925 926 /*! @name PLANIDCR - Port LANID configuration register */ 927 /*! @{ */ 928 929 #define SW_PORT2_PLANIDCR_LANID_MASK (0xFU) 930 #define SW_PORT2_PLANIDCR_LANID_SHIFT (0U) 931 #define SW_PORT2_PLANIDCR_LANID_WIDTH (4U) 932 #define SW_PORT2_PLANIDCR_LANID(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_PLANIDCR_LANID_SHIFT)) & SW_PORT2_PLANIDCR_LANID_MASK) 933 /*! @} */ 934 935 /*! @name PISIDCR - Port ingress stream identification configuration register */ 936 /*! @{ */ 937 938 #define SW_PORT2_PISIDCR_KCPAIR_MASK (0x1U) 939 #define SW_PORT2_PISIDCR_KCPAIR_SHIFT (0U) 940 #define SW_PORT2_PISIDCR_KCPAIR_WIDTH (1U) 941 #define SW_PORT2_PISIDCR_KCPAIR(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_PISIDCR_KCPAIR_SHIFT)) & SW_PORT2_PISIDCR_KCPAIR_MASK) 942 943 #define SW_PORT2_PISIDCR_KC0EN_MASK (0x2U) 944 #define SW_PORT2_PISIDCR_KC0EN_SHIFT (1U) 945 #define SW_PORT2_PISIDCR_KC0EN_WIDTH (1U) 946 #define SW_PORT2_PISIDCR_KC0EN(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_PISIDCR_KC0EN_SHIFT)) & SW_PORT2_PISIDCR_KC0EN_MASK) 947 948 #define SW_PORT2_PISIDCR_KC1EN_MASK (0x4U) 949 #define SW_PORT2_PISIDCR_KC1EN_SHIFT (2U) 950 #define SW_PORT2_PISIDCR_KC1EN_WIDTH (1U) 951 #define SW_PORT2_PISIDCR_KC1EN(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_PISIDCR_KC1EN_SHIFT)) & SW_PORT2_PISIDCR_KC1EN_MASK) 952 953 #define SW_PORT2_PISIDCR_ISEID_MASK (0xFFFF0000U) 954 #define SW_PORT2_PISIDCR_ISEID_SHIFT (16U) 955 #define SW_PORT2_PISIDCR_ISEID_WIDTH (16U) 956 #define SW_PORT2_PISIDCR_ISEID(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_PISIDCR_ISEID_SHIFT)) & SW_PORT2_PISIDCR_ISEID_MASK) 957 /*! @} */ 958 959 /*! @name PFMCR - Port frame modification configuration register */ 960 /*! @{ */ 961 962 #define SW_PORT2_PFMCR_FMMA_MASK (0x1U) 963 #define SW_PORT2_PFMCR_FMMA_SHIFT (0U) 964 #define SW_PORT2_PFMCR_FMMA_WIDTH (1U) 965 #define SW_PORT2_PFMCR_FMMA(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_PFMCR_FMMA_SHIFT)) & SW_PORT2_PFMCR_FMMA_MASK) 966 /*! @} */ 967 968 /*! @name PIPV2QMR0 - Port IPV to queue mapping register 0 */ 969 /*! @{ */ 970 971 #define SW_PORT2_PIPV2QMR0_IPV0_Q_MASK (0xFU) 972 #define SW_PORT2_PIPV2QMR0_IPV0_Q_SHIFT (0U) 973 #define SW_PORT2_PIPV2QMR0_IPV0_Q_WIDTH (4U) 974 #define SW_PORT2_PIPV2QMR0_IPV0_Q(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_PIPV2QMR0_IPV0_Q_SHIFT)) & SW_PORT2_PIPV2QMR0_IPV0_Q_MASK) 975 976 #define SW_PORT2_PIPV2QMR0_IPV1_Q_MASK (0xF0U) 977 #define SW_PORT2_PIPV2QMR0_IPV1_Q_SHIFT (4U) 978 #define SW_PORT2_PIPV2QMR0_IPV1_Q_WIDTH (4U) 979 #define SW_PORT2_PIPV2QMR0_IPV1_Q(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_PIPV2QMR0_IPV1_Q_SHIFT)) & SW_PORT2_PIPV2QMR0_IPV1_Q_MASK) 980 981 #define SW_PORT2_PIPV2QMR0_IPV2_Q_MASK (0xF00U) 982 #define SW_PORT2_PIPV2QMR0_IPV2_Q_SHIFT (8U) 983 #define SW_PORT2_PIPV2QMR0_IPV2_Q_WIDTH (4U) 984 #define SW_PORT2_PIPV2QMR0_IPV2_Q(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_PIPV2QMR0_IPV2_Q_SHIFT)) & SW_PORT2_PIPV2QMR0_IPV2_Q_MASK) 985 986 #define SW_PORT2_PIPV2QMR0_IPV3_Q_MASK (0xF000U) 987 #define SW_PORT2_PIPV2QMR0_IPV3_Q_SHIFT (12U) 988 #define SW_PORT2_PIPV2QMR0_IPV3_Q_WIDTH (4U) 989 #define SW_PORT2_PIPV2QMR0_IPV3_Q(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_PIPV2QMR0_IPV3_Q_SHIFT)) & SW_PORT2_PIPV2QMR0_IPV3_Q_MASK) 990 991 #define SW_PORT2_PIPV2QMR0_IPV4_Q_MASK (0xF0000U) 992 #define SW_PORT2_PIPV2QMR0_IPV4_Q_SHIFT (16U) 993 #define SW_PORT2_PIPV2QMR0_IPV4_Q_WIDTH (4U) 994 #define SW_PORT2_PIPV2QMR0_IPV4_Q(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_PIPV2QMR0_IPV4_Q_SHIFT)) & SW_PORT2_PIPV2QMR0_IPV4_Q_MASK) 995 996 #define SW_PORT2_PIPV2QMR0_IPV5_Q_MASK (0xF00000U) 997 #define SW_PORT2_PIPV2QMR0_IPV5_Q_SHIFT (20U) 998 #define SW_PORT2_PIPV2QMR0_IPV5_Q_WIDTH (4U) 999 #define SW_PORT2_PIPV2QMR0_IPV5_Q(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_PIPV2QMR0_IPV5_Q_SHIFT)) & SW_PORT2_PIPV2QMR0_IPV5_Q_MASK) 1000 1001 #define SW_PORT2_PIPV2QMR0_IPV6_Q_MASK (0xF000000U) 1002 #define SW_PORT2_PIPV2QMR0_IPV6_Q_SHIFT (24U) 1003 #define SW_PORT2_PIPV2QMR0_IPV6_Q_WIDTH (4U) 1004 #define SW_PORT2_PIPV2QMR0_IPV6_Q(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_PIPV2QMR0_IPV6_Q_SHIFT)) & SW_PORT2_PIPV2QMR0_IPV6_Q_MASK) 1005 1006 #define SW_PORT2_PIPV2QMR0_IPV7_Q_MASK (0xF0000000U) 1007 #define SW_PORT2_PIPV2QMR0_IPV7_Q_SHIFT (28U) 1008 #define SW_PORT2_PIPV2QMR0_IPV7_Q_WIDTH (4U) 1009 #define SW_PORT2_PIPV2QMR0_IPV7_Q(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_PIPV2QMR0_IPV7_Q_SHIFT)) & SW_PORT2_PIPV2QMR0_IPV7_Q_MASK) 1010 /*! @} */ 1011 1012 /*! @name PTCMINLR - Port time capture minimum latency register */ 1013 /*! @{ */ 1014 1015 #define SW_PORT2_PTCMINLR_LATENCY_MASK (0x3FFFFFFFU) 1016 #define SW_PORT2_PTCMINLR_LATENCY_SHIFT (0U) 1017 #define SW_PORT2_PTCMINLR_LATENCY_WIDTH (30U) 1018 #define SW_PORT2_PTCMINLR_LATENCY(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_PTCMINLR_LATENCY_SHIFT)) & SW_PORT2_PTCMINLR_LATENCY_MASK) 1019 1020 #define SW_PORT2_PTCMINLR_COUNT_MASK (0xC0000000U) 1021 #define SW_PORT2_PTCMINLR_COUNT_SHIFT (30U) 1022 #define SW_PORT2_PTCMINLR_COUNT_WIDTH (2U) 1023 #define SW_PORT2_PTCMINLR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_PTCMINLR_COUNT_SHIFT)) & SW_PORT2_PTCMINLR_COUNT_MASK) 1024 /*! @} */ 1025 1026 /*! @name PTCMAXLR - Port time capture maximum latency register */ 1027 /*! @{ */ 1028 1029 #define SW_PORT2_PTCMAXLR_LATENCY_MASK (0x3FFFFFFFU) 1030 #define SW_PORT2_PTCMAXLR_LATENCY_SHIFT (0U) 1031 #define SW_PORT2_PTCMAXLR_LATENCY_WIDTH (30U) 1032 #define SW_PORT2_PTCMAXLR_LATENCY(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_PTCMAXLR_LATENCY_SHIFT)) & SW_PORT2_PTCMAXLR_LATENCY_MASK) 1033 /*! @} */ 1034 1035 /*! @name BPCR - Bridge port configuration register */ 1036 /*! @{ */ 1037 1038 #define SW_PORT2_BPCR_DYN_LIMIT_MASK (0xFFFFU) 1039 #define SW_PORT2_BPCR_DYN_LIMIT_SHIFT (0U) 1040 #define SW_PORT2_BPCR_DYN_LIMIT_WIDTH (16U) 1041 #define SW_PORT2_BPCR_DYN_LIMIT(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_BPCR_DYN_LIMIT_SHIFT)) & SW_PORT2_BPCR_DYN_LIMIT_MASK) 1042 1043 #define SW_PORT2_BPCR_UUCASTE_MASK (0x1000000U) 1044 #define SW_PORT2_BPCR_UUCASTE_SHIFT (24U) 1045 #define SW_PORT2_BPCR_UUCASTE_WIDTH (1U) 1046 #define SW_PORT2_BPCR_UUCASTE(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_BPCR_UUCASTE_SHIFT)) & SW_PORT2_BPCR_UUCASTE_MASK) 1047 1048 #define SW_PORT2_BPCR_UMCASTE_MASK (0x2000000U) 1049 #define SW_PORT2_BPCR_UMCASTE_SHIFT (25U) 1050 #define SW_PORT2_BPCR_UMCASTE_WIDTH (1U) 1051 #define SW_PORT2_BPCR_UMCASTE(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_BPCR_UMCASTE_SHIFT)) & SW_PORT2_BPCR_UMCASTE_MASK) 1052 1053 #define SW_PORT2_BPCR_MCASTE_MASK (0x4000000U) 1054 #define SW_PORT2_BPCR_MCASTE_SHIFT (26U) 1055 #define SW_PORT2_BPCR_MCASTE_WIDTH (1U) 1056 #define SW_PORT2_BPCR_MCASTE(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_BPCR_MCASTE_SHIFT)) & SW_PORT2_BPCR_MCASTE_MASK) 1057 1058 #define SW_PORT2_BPCR_BCASTE_MASK (0x8000000U) 1059 #define SW_PORT2_BPCR_BCASTE_SHIFT (27U) 1060 #define SW_PORT2_BPCR_BCASTE_WIDTH (1U) 1061 #define SW_PORT2_BPCR_BCASTE(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_BPCR_BCASTE_SHIFT)) & SW_PORT2_BPCR_BCASTE_MASK) 1062 1063 #define SW_PORT2_BPCR_STAMVD_MASK (0x10000000U) 1064 #define SW_PORT2_BPCR_STAMVD_SHIFT (28U) 1065 #define SW_PORT2_BPCR_STAMVD_WIDTH (1U) 1066 #define SW_PORT2_BPCR_STAMVD(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_BPCR_STAMVD_SHIFT)) & SW_PORT2_BPCR_STAMVD_MASK) 1067 1068 #define SW_PORT2_BPCR_SRCPRND_MASK (0x20000000U) 1069 #define SW_PORT2_BPCR_SRCPRND_SHIFT (29U) 1070 #define SW_PORT2_BPCR_SRCPRND_WIDTH (1U) 1071 #define SW_PORT2_BPCR_SRCPRND(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_BPCR_SRCPRND_SHIFT)) & SW_PORT2_BPCR_SRCPRND_MASK) 1072 /*! @} */ 1073 1074 /*! @name BPDVR - Bridge port default VLAN register */ 1075 /*! @{ */ 1076 1077 #define SW_PORT2_BPDVR_VID_MASK (0xFFFU) 1078 #define SW_PORT2_BPDVR_VID_SHIFT (0U) 1079 #define SW_PORT2_BPDVR_VID_WIDTH (12U) 1080 #define SW_PORT2_BPDVR_VID(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_BPDVR_VID_SHIFT)) & SW_PORT2_BPDVR_VID_MASK) 1081 1082 #define SW_PORT2_BPDVR_DEI_MASK (0x1000U) 1083 #define SW_PORT2_BPDVR_DEI_SHIFT (12U) 1084 #define SW_PORT2_BPDVR_DEI_WIDTH (1U) 1085 #define SW_PORT2_BPDVR_DEI(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_BPDVR_DEI_SHIFT)) & SW_PORT2_BPDVR_DEI_MASK) 1086 1087 #define SW_PORT2_BPDVR_PCP_MASK (0xE000U) 1088 #define SW_PORT2_BPDVR_PCP_SHIFT (13U) 1089 #define SW_PORT2_BPDVR_PCP_WIDTH (3U) 1090 #define SW_PORT2_BPDVR_PCP(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_BPDVR_PCP_SHIFT)) & SW_PORT2_BPDVR_PCP_MASK) 1091 1092 #define SW_PORT2_BPDVR_TPID_MASK (0x10000U) 1093 #define SW_PORT2_BPDVR_TPID_SHIFT (16U) 1094 #define SW_PORT2_BPDVR_TPID_WIDTH (1U) 1095 #define SW_PORT2_BPDVR_TPID(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_BPDVR_TPID_SHIFT)) & SW_PORT2_BPDVR_TPID_MASK) 1096 1097 #define SW_PORT2_BPDVR_RXTAGA_MASK (0xF00000U) 1098 #define SW_PORT2_BPDVR_RXTAGA_SHIFT (20U) 1099 #define SW_PORT2_BPDVR_RXTAGA_WIDTH (4U) 1100 #define SW_PORT2_BPDVR_RXTAGA(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_BPDVR_RXTAGA_SHIFT)) & SW_PORT2_BPDVR_RXTAGA_MASK) 1101 1102 #define SW_PORT2_BPDVR_RXVAM_MASK (0x1000000U) 1103 #define SW_PORT2_BPDVR_RXVAM_SHIFT (24U) 1104 #define SW_PORT2_BPDVR_RXVAM_WIDTH (1U) 1105 #define SW_PORT2_BPDVR_RXVAM(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_BPDVR_RXVAM_SHIFT)) & SW_PORT2_BPDVR_RXVAM_MASK) 1106 1107 #define SW_PORT2_BPDVR_TXTAGA_MASK (0x6000000U) 1108 #define SW_PORT2_BPDVR_TXTAGA_SHIFT (25U) 1109 #define SW_PORT2_BPDVR_TXTAGA_WIDTH (2U) 1110 #define SW_PORT2_BPDVR_TXTAGA(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_BPDVR_TXTAGA_SHIFT)) & SW_PORT2_BPDVR_TXTAGA_MASK) 1111 /*! @} */ 1112 1113 /*! @name BPSTGSR - Bridge port spanning tree group state register */ 1114 /*! @{ */ 1115 1116 #define SW_PORT2_BPSTGSR_STG_STATE0_MASK (0x3U) 1117 #define SW_PORT2_BPSTGSR_STG_STATE0_SHIFT (0U) 1118 #define SW_PORT2_BPSTGSR_STG_STATE0_WIDTH (2U) 1119 #define SW_PORT2_BPSTGSR_STG_STATE0(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_BPSTGSR_STG_STATE0_SHIFT)) & SW_PORT2_BPSTGSR_STG_STATE0_MASK) 1120 1121 #define SW_PORT2_BPSTGSR_STG_STATE1_MASK (0xCU) 1122 #define SW_PORT2_BPSTGSR_STG_STATE1_SHIFT (2U) 1123 #define SW_PORT2_BPSTGSR_STG_STATE1_WIDTH (2U) 1124 #define SW_PORT2_BPSTGSR_STG_STATE1(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_BPSTGSR_STG_STATE1_SHIFT)) & SW_PORT2_BPSTGSR_STG_STATE1_MASK) 1125 1126 #define SW_PORT2_BPSTGSR_STG_STATE2_MASK (0x30U) 1127 #define SW_PORT2_BPSTGSR_STG_STATE2_SHIFT (4U) 1128 #define SW_PORT2_BPSTGSR_STG_STATE2_WIDTH (2U) 1129 #define SW_PORT2_BPSTGSR_STG_STATE2(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_BPSTGSR_STG_STATE2_SHIFT)) & SW_PORT2_BPSTGSR_STG_STATE2_MASK) 1130 1131 #define SW_PORT2_BPSTGSR_STG_STATE3_MASK (0xC0U) 1132 #define SW_PORT2_BPSTGSR_STG_STATE3_SHIFT (6U) 1133 #define SW_PORT2_BPSTGSR_STG_STATE3_WIDTH (2U) 1134 #define SW_PORT2_BPSTGSR_STG_STATE3(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_BPSTGSR_STG_STATE3_SHIFT)) & SW_PORT2_BPSTGSR_STG_STATE3_MASK) 1135 1136 #define SW_PORT2_BPSTGSR_STG_STATE4_MASK (0x300U) 1137 #define SW_PORT2_BPSTGSR_STG_STATE4_SHIFT (8U) 1138 #define SW_PORT2_BPSTGSR_STG_STATE4_WIDTH (2U) 1139 #define SW_PORT2_BPSTGSR_STG_STATE4(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_BPSTGSR_STG_STATE4_SHIFT)) & SW_PORT2_BPSTGSR_STG_STATE4_MASK) 1140 1141 #define SW_PORT2_BPSTGSR_STG_STATE5_MASK (0xC00U) 1142 #define SW_PORT2_BPSTGSR_STG_STATE5_SHIFT (10U) 1143 #define SW_PORT2_BPSTGSR_STG_STATE5_WIDTH (2U) 1144 #define SW_PORT2_BPSTGSR_STG_STATE5(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_BPSTGSR_STG_STATE5_SHIFT)) & SW_PORT2_BPSTGSR_STG_STATE5_MASK) 1145 1146 #define SW_PORT2_BPSTGSR_STG_STATE6_MASK (0x3000U) 1147 #define SW_PORT2_BPSTGSR_STG_STATE6_SHIFT (12U) 1148 #define SW_PORT2_BPSTGSR_STG_STATE6_WIDTH (2U) 1149 #define SW_PORT2_BPSTGSR_STG_STATE6(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_BPSTGSR_STG_STATE6_SHIFT)) & SW_PORT2_BPSTGSR_STG_STATE6_MASK) 1150 1151 #define SW_PORT2_BPSTGSR_STG_STATE7_MASK (0xC000U) 1152 #define SW_PORT2_BPSTGSR_STG_STATE7_SHIFT (14U) 1153 #define SW_PORT2_BPSTGSR_STG_STATE7_WIDTH (2U) 1154 #define SW_PORT2_BPSTGSR_STG_STATE7(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_BPSTGSR_STG_STATE7_SHIFT)) & SW_PORT2_BPSTGSR_STG_STATE7_MASK) 1155 1156 #define SW_PORT2_BPSTGSR_STG_STATE8_MASK (0x30000U) 1157 #define SW_PORT2_BPSTGSR_STG_STATE8_SHIFT (16U) 1158 #define SW_PORT2_BPSTGSR_STG_STATE8_WIDTH (2U) 1159 #define SW_PORT2_BPSTGSR_STG_STATE8(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_BPSTGSR_STG_STATE8_SHIFT)) & SW_PORT2_BPSTGSR_STG_STATE8_MASK) 1160 1161 #define SW_PORT2_BPSTGSR_STG_STATE9_MASK (0xC0000U) 1162 #define SW_PORT2_BPSTGSR_STG_STATE9_SHIFT (18U) 1163 #define SW_PORT2_BPSTGSR_STG_STATE9_WIDTH (2U) 1164 #define SW_PORT2_BPSTGSR_STG_STATE9(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_BPSTGSR_STG_STATE9_SHIFT)) & SW_PORT2_BPSTGSR_STG_STATE9_MASK) 1165 1166 #define SW_PORT2_BPSTGSR_STG_STATE10_MASK (0x300000U) 1167 #define SW_PORT2_BPSTGSR_STG_STATE10_SHIFT (20U) 1168 #define SW_PORT2_BPSTGSR_STG_STATE10_WIDTH (2U) 1169 #define SW_PORT2_BPSTGSR_STG_STATE10(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_BPSTGSR_STG_STATE10_SHIFT)) & SW_PORT2_BPSTGSR_STG_STATE10_MASK) 1170 1171 #define SW_PORT2_BPSTGSR_STG_STATE11_MASK (0xC00000U) 1172 #define SW_PORT2_BPSTGSR_STG_STATE11_SHIFT (22U) 1173 #define SW_PORT2_BPSTGSR_STG_STATE11_WIDTH (2U) 1174 #define SW_PORT2_BPSTGSR_STG_STATE11(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_BPSTGSR_STG_STATE11_SHIFT)) & SW_PORT2_BPSTGSR_STG_STATE11_MASK) 1175 1176 #define SW_PORT2_BPSTGSR_STG_STATE12_MASK (0x3000000U) 1177 #define SW_PORT2_BPSTGSR_STG_STATE12_SHIFT (24U) 1178 #define SW_PORT2_BPSTGSR_STG_STATE12_WIDTH (2U) 1179 #define SW_PORT2_BPSTGSR_STG_STATE12(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_BPSTGSR_STG_STATE12_SHIFT)) & SW_PORT2_BPSTGSR_STG_STATE12_MASK) 1180 1181 #define SW_PORT2_BPSTGSR_STG_STATE13_MASK (0xC000000U) 1182 #define SW_PORT2_BPSTGSR_STG_STATE13_SHIFT (26U) 1183 #define SW_PORT2_BPSTGSR_STG_STATE13_WIDTH (2U) 1184 #define SW_PORT2_BPSTGSR_STG_STATE13(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_BPSTGSR_STG_STATE13_SHIFT)) & SW_PORT2_BPSTGSR_STG_STATE13_MASK) 1185 1186 #define SW_PORT2_BPSTGSR_STG_STATE14_MASK (0x30000000U) 1187 #define SW_PORT2_BPSTGSR_STG_STATE14_SHIFT (28U) 1188 #define SW_PORT2_BPSTGSR_STG_STATE14_WIDTH (2U) 1189 #define SW_PORT2_BPSTGSR_STG_STATE14(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_BPSTGSR_STG_STATE14_SHIFT)) & SW_PORT2_BPSTGSR_STG_STATE14_MASK) 1190 1191 #define SW_PORT2_BPSTGSR_STG_STATE15_MASK (0xC0000000U) 1192 #define SW_PORT2_BPSTGSR_STG_STATE15_SHIFT (30U) 1193 #define SW_PORT2_BPSTGSR_STG_STATE15_WIDTH (2U) 1194 #define SW_PORT2_BPSTGSR_STG_STATE15(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_BPSTGSR_STG_STATE15_SHIFT)) & SW_PORT2_BPSTGSR_STG_STATE15_MASK) 1195 /*! @} */ 1196 1197 /*! @name BPSCR0 - Bridge port storm control register 0 */ 1198 /*! @{ */ 1199 1200 #define SW_PORT2_BPSCR0_UUCASTRPEID_MASK (0xFFFU) 1201 #define SW_PORT2_BPSCR0_UUCASTRPEID_SHIFT (0U) 1202 #define SW_PORT2_BPSCR0_UUCASTRPEID_WIDTH (12U) 1203 #define SW_PORT2_BPSCR0_UUCASTRPEID(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_BPSCR0_UUCASTRPEID_SHIFT)) & SW_PORT2_BPSCR0_UUCASTRPEID_MASK) 1204 1205 #define SW_PORT2_BPSCR0_BCASTRPEID_MASK (0xFFF0000U) 1206 #define SW_PORT2_BPSCR0_BCASTRPEID_SHIFT (16U) 1207 #define SW_PORT2_BPSCR0_BCASTRPEID_WIDTH (12U) 1208 #define SW_PORT2_BPSCR0_BCASTRPEID(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_BPSCR0_BCASTRPEID_SHIFT)) & SW_PORT2_BPSCR0_BCASTRPEID_MASK) 1209 /*! @} */ 1210 1211 /*! @name BPSCR1 - Bridge port storm control register 1 */ 1212 /*! @{ */ 1213 1214 #define SW_PORT2_BPSCR1_MCASTRPEID_MASK (0xFFFU) 1215 #define SW_PORT2_BPSCR1_MCASTRPEID_SHIFT (0U) 1216 #define SW_PORT2_BPSCR1_MCASTRPEID_WIDTH (12U) 1217 #define SW_PORT2_BPSCR1_MCASTRPEID(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_BPSCR1_MCASTRPEID_SHIFT)) & SW_PORT2_BPSCR1_MCASTRPEID_MASK) 1218 1219 #define SW_PORT2_BPSCR1_UMCASTRPEID_MASK (0xFFF0000U) 1220 #define SW_PORT2_BPSCR1_UMCASTRPEID_SHIFT (16U) 1221 #define SW_PORT2_BPSCR1_UMCASTRPEID_WIDTH (12U) 1222 #define SW_PORT2_BPSCR1_UMCASTRPEID(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_BPSCR1_UMCASTRPEID_SHIFT)) & SW_PORT2_BPSCR1_UMCASTRPEID_MASK) 1223 /*! @} */ 1224 1225 /*! @name BPOR - Bridge port operational register */ 1226 /*! @{ */ 1227 1228 #define SW_PORT2_BPOR_NUM_DYN_MASK (0xFFFFU) 1229 #define SW_PORT2_BPOR_NUM_DYN_SHIFT (0U) 1230 #define SW_PORT2_BPOR_NUM_DYN_WIDTH (16U) 1231 #define SW_PORT2_BPOR_NUM_DYN(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_BPOR_NUM_DYN_SHIFT)) & SW_PORT2_BPOR_NUM_DYN_MASK) 1232 /*! @} */ 1233 1234 /*! @name BPDCR - Bridge port discard count register */ 1235 /*! @{ */ 1236 1237 #define SW_PORT2_BPDCR_COUNT_MASK (0xFFFFFFFFU) 1238 #define SW_PORT2_BPDCR_COUNT_SHIFT (0U) 1239 #define SW_PORT2_BPDCR_COUNT_WIDTH (32U) 1240 #define SW_PORT2_BPDCR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_BPDCR_COUNT_SHIFT)) & SW_PORT2_BPDCR_COUNT_MASK) 1241 /*! @} */ 1242 1243 /*! @name BPDCRR0 - Bridge port discard count reason register 0 */ 1244 /*! @{ */ 1245 1246 #define SW_PORT2_BPDCRR0_BPACDR_MASK (0x1U) 1247 #define SW_PORT2_BPDCRR0_BPACDR_SHIFT (0U) 1248 #define SW_PORT2_BPDCRR0_BPACDR_WIDTH (1U) 1249 #define SW_PORT2_BPDCRR0_BPACDR(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_BPDCRR0_BPACDR_SHIFT)) & SW_PORT2_BPDCRR0_BPACDR_MASK) 1250 1251 #define SW_PORT2_BPDCRR0_ISTGSDR_MASK (0x2U) 1252 #define SW_PORT2_BPDCRR0_ISTGSDR_SHIFT (1U) 1253 #define SW_PORT2_BPDCRR0_ISTGSDR_WIDTH (1U) 1254 #define SW_PORT2_BPDCRR0_ISTGSDR(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_BPDCRR0_ISTGSDR_SHIFT)) & SW_PORT2_BPDCRR0_ISTGSDR_MASK) 1255 1256 #define SW_PORT2_BPDCRR0_BPVFLTDR_MASK (0x4U) 1257 #define SW_PORT2_BPDCRR0_BPVFLTDR_SHIFT (2U) 1258 #define SW_PORT2_BPDCRR0_BPVFLTDR_WIDTH (1U) 1259 #define SW_PORT2_BPDCRR0_BPVFLTDR(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_BPDCRR0_BPVFLTDR_SHIFT)) & SW_PORT2_BPDCRR0_BPVFLTDR_MASK) 1260 1261 #define SW_PORT2_BPDCRR0_MACLNFDR_MASK (0x8U) 1262 #define SW_PORT2_BPDCRR0_MACLNFDR_SHIFT (3U) 1263 #define SW_PORT2_BPDCRR0_MACLNFDR_WIDTH (1U) 1264 #define SW_PORT2_BPDCRR0_MACLNFDR(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_BPDCRR0_MACLNFDR_SHIFT)) & SW_PORT2_BPDCRR0_MACLNFDR_MASK) 1265 1266 #define SW_PORT2_BPDCRR0_STAMVDDR_MASK (0x80U) 1267 #define SW_PORT2_BPDCRR0_STAMVDDR_SHIFT (7U) 1268 #define SW_PORT2_BPDCRR0_STAMVDDR_WIDTH (1U) 1269 #define SW_PORT2_BPDCRR0_STAMVDDR(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_BPDCRR0_STAMVDDR_SHIFT)) & SW_PORT2_BPDCRR0_STAMVDDR_MASK) 1270 1271 #define SW_PORT2_BPDCRR0_MACFDDDR_MASK (0x100U) 1272 #define SW_PORT2_BPDCRR0_MACFDDDR_SHIFT (8U) 1273 #define SW_PORT2_BPDCRR0_MACFDDDR_WIDTH (1U) 1274 #define SW_PORT2_BPDCRR0_MACFDDDR(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_BPDCRR0_MACFDDDR_SHIFT)) & SW_PORT2_BPDCRR0_MACFDDDR_MASK) 1275 1276 #define SW_PORT2_BPDCRR0_NODESTDR_MASK (0x200U) 1277 #define SW_PORT2_BPDCRR0_NODESTDR_SHIFT (9U) 1278 #define SW_PORT2_BPDCRR0_NODESTDR_WIDTH (1U) 1279 #define SW_PORT2_BPDCRR0_NODESTDR(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_BPDCRR0_NODESTDR_SHIFT)) & SW_PORT2_BPDCRR0_NODESTDR_MASK) 1280 1281 #define SW_PORT2_BPDCRR0_IPMFDR_MASK (0x400U) 1282 #define SW_PORT2_BPDCRR0_IPMFDR_SHIFT (10U) 1283 #define SW_PORT2_BPDCRR0_IPMFDR_WIDTH (1U) 1284 #define SW_PORT2_BPDCRR0_IPMFDR(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_BPDCRR0_IPMFDR_SHIFT)) & SW_PORT2_BPDCRR0_IPMFDR_MASK) 1285 1286 #define SW_PORT2_BPDCRR0_UFMMDR_MASK (0x800U) 1287 #define SW_PORT2_BPDCRR0_UFMMDR_SHIFT (11U) 1288 #define SW_PORT2_BPDCRR0_UFMMDR_WIDTH (1U) 1289 #define SW_PORT2_BPDCRR0_UFMMDR(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_BPDCRR0_UFMMDR_SHIFT)) & SW_PORT2_BPDCRR0_UFMMDR_MASK) 1290 1291 #define SW_PORT2_BPDCRR0_MISCDR_MASK (0x1000U) 1292 #define SW_PORT2_BPDCRR0_MISCDR_SHIFT (12U) 1293 #define SW_PORT2_BPDCRR0_MISCDR_WIDTH (1U) 1294 #define SW_PORT2_BPDCRR0_MISCDR(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_BPDCRR0_MISCDR_SHIFT)) & SW_PORT2_BPDCRR0_MISCDR_MASK) 1295 1296 #define SW_PORT2_BPDCRR0_STRMCTRLDR_MASK (0x2000U) 1297 #define SW_PORT2_BPDCRR0_STRMCTRLDR_SHIFT (13U) 1298 #define SW_PORT2_BPDCRR0_STRMCTRLDR_WIDTH (1U) 1299 #define SW_PORT2_BPDCRR0_STRMCTRLDR(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_BPDCRR0_STRMCTRLDR_SHIFT)) & SW_PORT2_BPDCRR0_STRMCTRLDR_MASK) 1300 /*! @} */ 1301 1302 /*! @name BPDCRR1 - Bridge port discard count reason register 1 */ 1303 /*! @{ */ 1304 1305 #define SW_PORT2_BPDCRR1_ENTRYID_MASK (0x7FFFFFFU) 1306 #define SW_PORT2_BPDCRR1_ENTRYID_SHIFT (0U) 1307 #define SW_PORT2_BPDCRR1_ENTRYID_WIDTH (27U) 1308 #define SW_PORT2_BPDCRR1_ENTRYID(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_BPDCRR1_ENTRYID_SHIFT)) & SW_PORT2_BPDCRR1_ENTRYID_MASK) 1309 1310 #define SW_PORT2_BPDCRR1_TT_MASK (0xF0000000U) 1311 #define SW_PORT2_BPDCRR1_TT_SHIFT (28U) 1312 #define SW_PORT2_BPDCRR1_TT_WIDTH (4U) 1313 #define SW_PORT2_BPDCRR1_TT(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_BPDCRR1_TT_SHIFT)) & SW_PORT2_BPDCRR1_TT_MASK) 1314 /*! @} */ 1315 1316 /*! @name BPMLFSR - Bridge port MAC learning failure status register */ 1317 /*! @{ */ 1318 1319 #define SW_PORT2_BPMLFSR_BPMLLRFR_MASK (0x1U) 1320 #define SW_PORT2_BPMLFSR_BPMLLRFR_SHIFT (0U) 1321 #define SW_PORT2_BPMLFSR_BPMLLRFR_WIDTH (1U) 1322 #define SW_PORT2_BPMLFSR_BPMLLRFR(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_BPMLFSR_BPMLLRFR_SHIFT)) & SW_PORT2_BPMLFSR_BPMLLRFR_MASK) 1323 1324 #define SW_PORT2_BPMLFSR_FFDBTRFR_MASK (0x2U) 1325 #define SW_PORT2_BPMLFSR_FFDBTRFR_SHIFT (1U) 1326 #define SW_PORT2_BPMLFSR_FFDBTRFR_WIDTH (1U) 1327 #define SW_PORT2_BPMLFSR_FFDBTRFR(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_BPMLFSR_FFDBTRFR_SHIFT)) & SW_PORT2_BPMLFSR_FFDBTRFR_MASK) 1328 1329 #define SW_PORT2_BPMLFSR_HCCLRFR_MASK (0x4U) 1330 #define SW_PORT2_BPMLFSR_HCCLRFR_SHIFT (2U) 1331 #define SW_PORT2_BPMLFSR_HCCLRFR_WIDTH (1U) 1332 #define SW_PORT2_BPMLFSR_HCCLRFR(x) (((uint32_t)(((uint32_t)(x)) << SW_PORT2_BPMLFSR_HCCLRFR_SHIFT)) & SW_PORT2_BPMLFSR_HCCLRFR_MASK) 1333 /*! @} */ 1334 1335 /*! 1336 * @} 1337 */ /* end of group SW_PORT2_Register_Masks */ 1338 1339 /*! 1340 * @} 1341 */ /* end of group SW_PORT2_Peripheral_Access_Layer */ 1342 1343 #endif /* #if !defined(S32Z2_SW_PORT2_H_) */ 1344
