1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2023 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32Z2_ERM.h 10 * @version 2.1 11 * @date 2023-07-20 12 * @brief Peripheral Access Layer for S32Z2_ERM 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32Z2_ERM_H_) /* Check if memory map has not been already included */ 58 #define S32Z2_ERM_H_ 59 60 #include "S32Z2_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- ERM Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup ERM_Peripheral_Access_Layer ERM Peripheral Access Layer 68 * @{ 69 */ 70 71 /** ERM - Register Layout Typedef */ 72 typedef struct { 73 __IO uint32_t CR0; /**< ERM Configuration Register 0, offset: 0x0 */ 74 __IO uint32_t CR1; /**< ERM Configuration Register 1, offset: 0x4, available only on: CE_ERM_0, CE_ERM_1, CE_ERM_2, ERM_3, SMU.ERM/SMU__ERM (missing on ERM_0, ERM_1, ERM_2, ERM_4, ERM_5) */ 75 __IO uint32_t CR2; /**< ERM Configuration Register 2, offset: 0x8, available only on: CE_ERM_0, CE_ERM_1, CE_ERM_2, ERM_3, SMU.ERM/SMU__ERM (missing on ERM_0, ERM_1, ERM_2, ERM_4, ERM_5) */ 76 uint8_t RESERVED_0[4]; 77 __IO uint32_t SR0; /**< ERM Status Register 0, offset: 0x10 */ 78 __IO uint32_t SR1; /**< ERM Status Register 1, offset: 0x14, available only on: CE_ERM_0, CE_ERM_1, CE_ERM_2, ERM_3, SMU.ERM/SMU__ERM (missing on ERM_0, ERM_1, ERM_2, ERM_4, ERM_5) */ 79 __IO uint32_t SR2; /**< ERM Status Register 2, offset: 0x18, available only on: CE_ERM_0, CE_ERM_1, CE_ERM_2, ERM_3, SMU.ERM/SMU__ERM (missing on ERM_0, ERM_1, ERM_2, ERM_4, ERM_5) */ 80 uint8_t RESERVED_1[228]; 81 __I uint32_t EAR0; /**< ERM Memory 0 Error Address Register, offset: 0x100, available only on: CE_ERM_0, CE_ERM_2, ERM_0, ERM_1, ERM_3, ERM_4, ERM_5, SMU.ERM/SMU__ERM (missing on CE_ERM_1, ERM_2) */ 82 __I uint32_t SYN0; /**< ERM Memory 0 Syndrome Register, offset: 0x104, available only on: CE_ERM_0, ERM_0, ERM_1, ERM_3, ERM_4, ERM_5, SMU.ERM/SMU__ERM (missing on CE_ERM_1, CE_ERM_2, ERM_2) */ 83 __IO uint32_t CORR_ERR_CNT0; /**< ERM Memory 0 Correctable Error Count Register, offset: 0x108, available only on: CE_ERM_0, CE_ERM_2, ERM_0, ERM_1, ERM_2, ERM_3, ERM_4, ERM_5, SMU.ERM/SMU__ERM (missing on CE_ERM_1) */ 84 uint8_t RESERVED_2[4]; 85 __I uint32_t EAR1; /**< ERM Memory 1 Error Address Register, offset: 0x110, available only on: CE_ERM_0, CE_ERM_2, ERM_3, ERM_5, SMU.ERM/SMU__ERM (missing on CE_ERM_1, ERM_0, ERM_1, ERM_2, ERM_4) */ 86 __I uint32_t SYN1; /**< ERM Memory 1 Syndrome Register, offset: 0x114, available only on: CE_ERM_0, ERM_3, SMU.ERM/SMU__ERM (missing on CE_ERM_1, CE_ERM_2, ERM_0, ERM_1, ERM_2, ERM_4, ERM_5) */ 87 __IO uint32_t CORR_ERR_CNT1; /**< ERM Memory 1 Correctable Error Count Register, offset: 0x118, available only on: CE_ERM_0, CE_ERM_2, ERM_2, ERM_3, ERM_4, ERM_5, SMU.ERM/SMU__ERM (missing on CE_ERM_1, ERM_0, ERM_1) */ 88 uint8_t RESERVED_3[4]; 89 __I uint32_t EAR2; /**< ERM Memory 2 Error Address Register, offset: 0x120, available only on: CE_ERM_0, CE_ERM_2, ERM_3, ERM_5, SMU.ERM/SMU__ERM (missing on CE_ERM_1, ERM_0, ERM_1, ERM_2, ERM_4) */ 90 __I uint32_t SYN2; /**< ERM Memory 2 Syndrome Register, offset: 0x124, available only on: CE_ERM_0, ERM_3, SMU.ERM/SMU__ERM (missing on CE_ERM_1, CE_ERM_2, ERM_0, ERM_1, ERM_2, ERM_4, ERM_5) */ 91 __IO uint32_t CORR_ERR_CNT2; /**< ERM Memory 2 Correctable Error Count Register, offset: 0x128, available only on: CE_ERM_0, CE_ERM_2, ERM_2, ERM_3, ERM_4, ERM_5, SMU.ERM/SMU__ERM (missing on CE_ERM_1, ERM_0, ERM_1) */ 92 uint8_t RESERVED_4[4]; 93 __I uint32_t EAR3; /**< ERM Memory 3 Error Address Register, offset: 0x130, available only on: CE_ERM_0, CE_ERM_2, ERM_3, ERM_5, SMU.ERM/SMU__ERM (missing on CE_ERM_1, ERM_0, ERM_1, ERM_2, ERM_4) */ 94 __I uint32_t SYN3; /**< ERM Memory 3 Syndrome Register, offset: 0x134, available only on: ERM_3, SMU.ERM/SMU__ERM (missing on CE_ERM_0, CE_ERM_1, CE_ERM_2, ERM_0, ERM_1, ERM_2, ERM_4, ERM_5) */ 95 __IO uint32_t CORR_ERR_CNT3; /**< ERM Memory 3 Correctable Error Count Register, offset: 0x138, available only on: CE_ERM_0, CE_ERM_2, ERM_2, ERM_3, ERM_4, ERM_5, SMU.ERM/SMU__ERM (missing on CE_ERM_1, ERM_0, ERM_1) */ 96 uint8_t RESERVED_5[4]; 97 __I uint32_t EAR4; /**< ERM Memory 4 Error Address Register, offset: 0x140, available only on: CE_ERM_2, ERM_5 (missing on CE_ERM_0, CE_ERM_1, ERM_0, ERM_1, ERM_2, ERM_3, ERM_4, SMU.ERM/SMU__ERM) */ 98 uint8_t RESERVED_6[4]; 99 __IO uint32_t CORR_ERR_CNT4; /**< ERM Memory 4 Correctable Error Count Register, offset: 0x148, available only on: CE_ERM_2, ERM_2, ERM_3, ERM_4, ERM_5 (missing on CE_ERM_0, CE_ERM_1, ERM_0, ERM_1, SMU.ERM/SMU__ERM) */ 100 uint8_t RESERVED_7[4]; 101 __I uint32_t EAR5; /**< ERM Memory 5 Error Address Register, offset: 0x150, available only on: CE_ERM_0, CE_ERM_1, CE_ERM_2, ERM_3, SMU.ERM/SMU__ERM (missing on ERM_0, ERM_1, ERM_2, ERM_4, ERM_5) */ 102 __I uint32_t SYN5; /**< ERM Memory 5 Syndrome Register, offset: 0x154, available only on: CE_ERM_0, ERM_3, SMU.ERM/SMU__ERM (missing on CE_ERM_1, CE_ERM_2, ERM_0, ERM_1, ERM_2, ERM_4, ERM_5) */ 103 __IO uint32_t CORR_ERR_CNT5; /**< ERM Memory 5 Correctable Error Count Register, offset: 0x158, available only on: CE_ERM_0, CE_ERM_1, CE_ERM_2, ERM_2, ERM_3, SMU.ERM/SMU__ERM (missing on ERM_0, ERM_1, ERM_4, ERM_5) */ 104 uint8_t RESERVED_8[4]; 105 __I uint32_t EAR6; /**< ERM Memory 6 Error Address Register, offset: 0x160, available only on: CE_ERM_0, CE_ERM_1, CE_ERM_2, SMU.ERM/SMU__ERM (missing on ERM_0, ERM_1, ERM_2, ERM_3, ERM_4, ERM_5) */ 106 __I uint32_t SYN6; /**< ERM Memory 6 Syndrome Register, offset: 0x164, available only on: CE_ERM_0, CE_ERM_1, SMU.ERM/SMU__ERM (missing on CE_ERM_2, ERM_0, ERM_1, ERM_2, ERM_3, ERM_4, ERM_5) */ 107 __IO uint32_t CORR_ERR_CNT6; /**< ERM Memory 6 Correctable Error Count Register, offset: 0x168, available only on: CE_ERM_0, CE_ERM_1, CE_ERM_2, ERM_2, ERM_3, SMU.ERM/SMU__ERM (missing on ERM_0, ERM_1, ERM_4, ERM_5) */ 108 uint8_t RESERVED_9[4]; 109 __I uint32_t EAR7; /**< ERM Memory 7 Error Address Register, offset: 0x170, available only on: CE_ERM_0, CE_ERM_1, CE_ERM_2, ERM_3, SMU.ERM/SMU__ERM (missing on ERM_0, ERM_1, ERM_2, ERM_4, ERM_5) */ 110 __I uint32_t SYN7; /**< ERM Memory 7 Syndrome Register, offset: 0x174, available only on: CE_ERM_0, CE_ERM_1, SMU.ERM/SMU__ERM (missing on CE_ERM_2, ERM_0, ERM_1, ERM_2, ERM_3, ERM_4, ERM_5) */ 111 __IO uint32_t CORR_ERR_CNT7; /**< ERM Memory 7 Correctable Error Count Register, offset: 0x178, available only on: CE_ERM_0, CE_ERM_1, CE_ERM_2, ERM_2, ERM_3, SMU.ERM/SMU__ERM (missing on ERM_0, ERM_1, ERM_4, ERM_5) */ 112 uint8_t RESERVED_10[4]; 113 __I uint32_t EAR8; /**< ERM Memory 8 Error Address Register, offset: 0x180, available only on: CE_ERM_0, CE_ERM_1, CE_ERM_2, ERM_3, SMU.ERM/SMU__ERM (missing on ERM_0, ERM_1, ERM_2, ERM_4, ERM_5) */ 114 __I uint32_t SYN8; /**< ERM Memory 8 Syndrome Register, offset: 0x184, available only on: CE_ERM_0, CE_ERM_1, SMU.ERM/SMU__ERM (missing on CE_ERM_2, ERM_0, ERM_1, ERM_2, ERM_3, ERM_4, ERM_5) */ 115 __IO uint32_t CORR_ERR_CNT8; /**< ERM Memory 8 Correctable Error Count Register, offset: 0x188, available only on: CE_ERM_0, CE_ERM_1, CE_ERM_2, ERM_3, SMU.ERM/SMU__ERM (missing on ERM_0, ERM_1, ERM_2, ERM_4, ERM_5) */ 116 uint8_t RESERVED_11[4]; 117 __I uint32_t EAR9; /**< ERM Memory 9 Error Address Register, offset: 0x190, available only on: CE_ERM_0, CE_ERM_1, CE_ERM_2, ERM_3, SMU.ERM/SMU__ERM (missing on ERM_0, ERM_1, ERM_2, ERM_4, ERM_5) */ 118 __I uint32_t SYN9; /**< ERM Memory 9 Syndrome Register, offset: 0x194, available only on: CE_ERM_0, CE_ERM_1, ERM_3, SMU.ERM/SMU__ERM (missing on CE_ERM_2, ERM_0, ERM_1, ERM_2, ERM_4, ERM_5) */ 119 __IO uint32_t CORR_ERR_CNT9; /**< ERM Memory 9 Correctable Error Count Register, offset: 0x198, available only on: CE_ERM_0, CE_ERM_1, CE_ERM_2, ERM_3, SMU.ERM/SMU__ERM (missing on ERM_0, ERM_1, ERM_2, ERM_4, ERM_5) */ 120 uint8_t RESERVED_12[4]; 121 __I uint32_t EAR10; /**< ERM Memory 10 Error Address Register, offset: 0x1A0, available only on: CE_ERM_0, CE_ERM_1, CE_ERM_2, SMU.ERM/SMU__ERM (missing on ERM_0, ERM_1, ERM_2, ERM_3, ERM_4, ERM_5) */ 122 __I uint32_t SYN10; /**< ERM Memory 10 Syndrome Register, offset: 0x1A4, available only on: CE_ERM_0, SMU.ERM/SMU__ERM (missing on CE_ERM_1, CE_ERM_2, ERM_0, ERM_1, ERM_2, ERM_3, ERM_4, ERM_5) */ 123 __IO uint32_t CORR_ERR_CNT10; /**< ERM Memory 10 Correctable Error Count Register, offset: 0x1A8, available only on: CE_ERM_0, CE_ERM_1, CE_ERM_2, ERM_3, SMU.ERM/SMU__ERM (missing on ERM_0, ERM_1, ERM_2, ERM_4, ERM_5) */ 124 uint8_t RESERVED_13[4]; 125 __I uint32_t EAR11; /**< ERM Memory 11 Error Address Register, offset: 0x1B0, available only on: CE_ERM_0, CE_ERM_1, CE_ERM_2, SMU.ERM/SMU__ERM (missing on ERM_0, ERM_1, ERM_2, ERM_3, ERM_4, ERM_5) */ 126 __I uint32_t SYN11; /**< ERM Memory 11 Syndrome Register, offset: 0x1B4, available only on: CE_ERM_0, SMU.ERM/SMU__ERM (missing on CE_ERM_1, CE_ERM_2, ERM_0, ERM_1, ERM_2, ERM_3, ERM_4, ERM_5) */ 127 __IO uint32_t CORR_ERR_CNT11; /**< ERM Memory 11 Correctable Error Count Register, offset: 0x1B8, available only on: CE_ERM_0, CE_ERM_1, CE_ERM_2, ERM_3, SMU.ERM/SMU__ERM (missing on ERM_0, ERM_1, ERM_2, ERM_4, ERM_5) */ 128 uint8_t RESERVED_14[4]; 129 __I uint32_t EAR12; /**< ERM Memory 12 Error Address Register, offset: 0x1C0, available only on: CE_ERM_0, CE_ERM_1, CE_ERM_2, SMU.ERM/SMU__ERM (missing on ERM_0, ERM_1, ERM_2, ERM_3, ERM_4, ERM_5) */ 130 __I uint32_t SYN12; /**< ERM Memory 12 Syndrome Register, offset: 0x1C4, available only on: CE_ERM_0, SMU.ERM/SMU__ERM (missing on CE_ERM_1, CE_ERM_2, ERM_0, ERM_1, ERM_2, ERM_3, ERM_4, ERM_5) */ 131 __IO uint32_t CORR_ERR_CNT12; /**< ERM Memory 12 Correctable Error Count Register, offset: 0x1C8, available only on: CE_ERM_0, CE_ERM_1, CE_ERM_2, ERM_3, SMU.ERM/SMU__ERM (missing on ERM_0, ERM_1, ERM_2, ERM_4, ERM_5) */ 132 uint8_t RESERVED_15[4]; 133 __I uint32_t EAR13; /**< ERM Memory 13 Error Address Register, offset: 0x1D0, available only on: CE_ERM_0, CE_ERM_2, SMU.ERM/SMU__ERM (missing on CE_ERM_1, ERM_0, ERM_1, ERM_2, ERM_3, ERM_4, ERM_5) */ 134 __I uint32_t SYN13; /**< ERM Memory 13 Syndrome Register, offset: 0x1D4, available only on: CE_ERM_0, SMU.ERM/SMU__ERM (missing on CE_ERM_1, CE_ERM_2, ERM_0, ERM_1, ERM_2, ERM_3, ERM_4, ERM_5) */ 135 __IO uint32_t CORR_ERR_CNT13; /**< ERM Memory 13 Correctable Error Count Register, offset: 0x1D8, available only on: CE_ERM_0, CE_ERM_2, ERM_3, SMU.ERM/SMU__ERM (missing on CE_ERM_1, ERM_0, ERM_1, ERM_2, ERM_4, ERM_5) */ 136 uint8_t RESERVED_16[4]; 137 __I uint32_t EAR14; /**< ERM Memory 14 Error Address Register, offset: 0x1E0, available only on: CE_ERM_0, CE_ERM_2, SMU.ERM/SMU__ERM (missing on CE_ERM_1, ERM_0, ERM_1, ERM_2, ERM_3, ERM_4, ERM_5) */ 138 __I uint32_t SYN14; /**< ERM Memory 14 Syndrome Register, offset: 0x1E4, available only on: CE_ERM_0, SMU.ERM/SMU__ERM (missing on CE_ERM_1, CE_ERM_2, ERM_0, ERM_1, ERM_2, ERM_3, ERM_4, ERM_5) */ 139 __IO uint32_t CORR_ERR_CNT14; /**< ERM Memory 14 Correctable Error Count Register, offset: 0x1E8, available only on: CE_ERM_0, CE_ERM_2, ERM_3, SMU.ERM/SMU__ERM (missing on CE_ERM_1, ERM_0, ERM_1, ERM_2, ERM_4, ERM_5) */ 140 uint8_t RESERVED_17[4]; 141 __I uint32_t EAR15; /**< ERM Memory 15 Error Address Register, offset: 0x1F0, available only on: CE_ERM_0, CE_ERM_2, SMU.ERM/SMU__ERM (missing on CE_ERM_1, ERM_0, ERM_1, ERM_2, ERM_3, ERM_4, ERM_5) */ 142 uint8_t RESERVED_18[4]; 143 __IO uint32_t CORR_ERR_CNT15; /**< ERM Memory 15 Correctable Error Count Register, offset: 0x1F8, available only on: CE_ERM_0, CE_ERM_2, ERM_3, SMU.ERM/SMU__ERM (missing on CE_ERM_1, ERM_0, ERM_1, ERM_2, ERM_4, ERM_5) */ 144 uint8_t RESERVED_19[4]; 145 __I uint32_t EAR16; /**< ERM Memory 16 Error Address Register, offset: 0x200, available only on: CE_ERM_0, CE_ERM_1, CE_ERM_2, SMU.ERM/SMU__ERM (missing on ERM_0, ERM_1, ERM_2, ERM_3, ERM_4, ERM_5) */ 146 uint8_t RESERVED_20[4]; 147 __IO uint32_t CORR_ERR_CNT16; /**< ERM Memory 16 Correctable Error Count Register, offset: 0x208, available only on: CE_ERM_0, CE_ERM_1, CE_ERM_2, ERM_3, SMU.ERM/SMU__ERM (missing on ERM_0, ERM_1, ERM_2, ERM_4, ERM_5) */ 148 uint8_t RESERVED_21[4]; 149 __I uint32_t EAR17; /**< ERM Memory 17 Error Address Register, offset: 0x210, available only on: CE_ERM_0, CE_ERM_2, SMU.ERM/SMU__ERM (missing on CE_ERM_1, ERM_0, ERM_1, ERM_2, ERM_3, ERM_4, ERM_5) */ 150 uint8_t RESERVED_22[4]; 151 __IO uint32_t CORR_ERR_CNT17; /**< ERM Memory 17 Correctable Error Count Register, offset: 0x218, available only on: CE_ERM_0, CE_ERM_2, ERM_3, SMU.ERM/SMU__ERM (missing on CE_ERM_1, ERM_0, ERM_1, ERM_2, ERM_4, ERM_5) */ 152 uint8_t RESERVED_23[4]; 153 __I uint32_t EAR18; /**< ERM Memory 18 Error Address Register, offset: 0x220, available only on: CE_ERM_0, CE_ERM_2 (missing on CE_ERM_1, ERM_0, ERM_1, ERM_2, ERM_3, ERM_4, ERM_5, SMU.ERM/SMU__ERM) */ 154 __I uint32_t SYN18; /**< ERM Memory 18 Syndrome Register, offset: 0x224, available only on: CE_ERM_0 (missing on CE_ERM_1, CE_ERM_2, ERM_0, ERM_1, ERM_2, ERM_3, ERM_4, ERM_5, SMU.ERM/SMU__ERM) */ 155 __IO uint32_t CORR_ERR_CNT18; /**< ERM Memory 18 Correctable Error Count Register, offset: 0x228, available only on: CE_ERM_0, CE_ERM_2, SMU.ERM/SMU__ERM (missing on CE_ERM_1, ERM_0, ERM_1, ERM_2, ERM_3, ERM_4, ERM_5) */ 156 uint8_t RESERVED_24[4]; 157 __I uint32_t EAR19; /**< ERM Memory 19 Error Address Register, offset: 0x230, available only on: CE_ERM_2 (missing on CE_ERM_0, CE_ERM_1, ERM_0, ERM_1, ERM_2, ERM_3, ERM_4, ERM_5, SMU.ERM/SMU__ERM) */ 158 uint8_t RESERVED_25[4]; 159 __IO uint32_t CORR_ERR_CNT19; /**< ERM Memory 19 Correctable Error Count Register, offset: 0x238, available only on: CE_ERM_2 (missing on CE_ERM_0, CE_ERM_1, ERM_0, ERM_1, ERM_2, ERM_3, ERM_4, ERM_5, SMU.ERM/SMU__ERM) */ 160 uint8_t RESERVED_26[4]; 161 __I uint32_t EAR20; /**< ERM Memory 20 Error Address Register, offset: 0x240, available only on: CE_ERM_1, CE_ERM_2 (missing on CE_ERM_0, ERM_0, ERM_1, ERM_2, ERM_3, ERM_4, ERM_5, SMU.ERM/SMU__ERM) */ 162 __I uint32_t SYN20; /**< ERM Memory 20 Syndrome Register, offset: 0x244, available only on: CE_ERM_1 (missing on CE_ERM_0, CE_ERM_2, ERM_0, ERM_1, ERM_2, ERM_3, ERM_4, ERM_5, SMU.ERM/SMU__ERM) */ 163 __IO uint32_t CORR_ERR_CNT20; /**< ERM Memory 20 Correctable Error Count Register, offset: 0x248, available only on: CE_ERM_1, CE_ERM_2 (missing on CE_ERM_0, ERM_0, ERM_1, ERM_2, ERM_3, ERM_4, ERM_5, SMU.ERM/SMU__ERM) */ 164 uint8_t RESERVED_27[4]; 165 __I uint32_t EAR21; /**< ERM Memory 21 Error Address Register, offset: 0x250, available only on: CE_ERM_2 (missing on CE_ERM_0, CE_ERM_1, ERM_0, ERM_1, ERM_2, ERM_3, ERM_4, ERM_5, SMU.ERM/SMU__ERM) */ 166 uint8_t RESERVED_28[4]; 167 __IO uint32_t CORR_ERR_CNT21; /**< ERM Memory 21 Correctable Error Count Register, offset: 0x258, available only on: CE_ERM_2 (missing on CE_ERM_0, CE_ERM_1, ERM_0, ERM_1, ERM_2, ERM_3, ERM_4, ERM_5, SMU.ERM/SMU__ERM) */ 168 uint8_t RESERVED_29[4]; 169 __I uint32_t EAR22; /**< ERM Memory 22 Error Address Register, offset: 0x260, available only on: CE_ERM_2 (missing on CE_ERM_0, CE_ERM_1, ERM_0, ERM_1, ERM_2, ERM_3, ERM_4, ERM_5, SMU.ERM/SMU__ERM) */ 170 uint8_t RESERVED_30[4]; 171 __IO uint32_t CORR_ERR_CNT22; /**< ERM Memory 22 Correctable Error Count Register, offset: 0x268, available only on: CE_ERM_2 (missing on CE_ERM_0, CE_ERM_1, ERM_0, ERM_1, ERM_2, ERM_3, ERM_4, ERM_5, SMU.ERM/SMU__ERM) */ 172 uint8_t RESERVED_31[4]; 173 __I uint32_t EAR23; /**< ERM Memory 23 Error Address Register, offset: 0x270, available only on: CE_ERM_2 (missing on CE_ERM_0, CE_ERM_1, ERM_0, ERM_1, ERM_2, ERM_3, ERM_4, ERM_5, SMU.ERM/SMU__ERM) */ 174 uint8_t RESERVED_32[4]; 175 __IO uint32_t CORR_ERR_CNT23; /**< ERM Memory 23 Correctable Error Count Register, offset: 0x278, available only on: CE_ERM_2 (missing on CE_ERM_0, CE_ERM_1, ERM_0, ERM_1, ERM_2, ERM_3, ERM_4, ERM_5, SMU.ERM/SMU__ERM) */ 176 } ERM_Type, *ERM_MemMapPtr; 177 178 /** Number of instances of the ERM module. */ 179 #define ERM_INSTANCE_COUNT (10u) 180 181 /* ERM - Peripheral instance base addresses */ 182 /** Peripheral CE_ERM_0 base address */ 183 #define IP_CE_ERM_0_BASE (0x44810000u) 184 /** Peripheral CE_ERM_0 base pointer */ 185 #define IP_CE_ERM_0 ((ERM_Type *)IP_CE_ERM_0_BASE) 186 /** Peripheral CE_ERM_1 base address */ 187 #define IP_CE_ERM_1_BASE (0x44818000u) 188 /** Peripheral CE_ERM_1 base pointer */ 189 #define IP_CE_ERM_1 ((ERM_Type *)IP_CE_ERM_1_BASE) 190 /** Peripheral CE_ERM_2 base address */ 191 #define IP_CE_ERM_2_BASE (0x44830000u) 192 /** Peripheral CE_ERM_2 base pointer */ 193 #define IP_CE_ERM_2 ((ERM_Type *)IP_CE_ERM_2_BASE) 194 /** Peripheral ERM_0 base address */ 195 #define IP_ERM_0_BASE (0x40070000u) 196 /** Peripheral ERM_0 base pointer */ 197 #define IP_ERM_0 ((ERM_Type *)IP_ERM_0_BASE) 198 /** Peripheral ERM_1 base address */ 199 #define IP_ERM_1_BASE (0x40870000u) 200 /** Peripheral ERM_1 base pointer */ 201 #define IP_ERM_1 ((ERM_Type *)IP_ERM_1_BASE) 202 /** Peripheral ERM_2 base address */ 203 #define IP_ERM_2_BASE (0x41070000u) 204 /** Peripheral ERM_2 base pointer */ 205 #define IP_ERM_2 ((ERM_Type *)IP_ERM_2_BASE) 206 /** Peripheral ERM_3 base address */ 207 #define IP_ERM_3_BASE (0x41870000u) 208 /** Peripheral ERM_3 base pointer */ 209 #define IP_ERM_3 ((ERM_Type *)IP_ERM_3_BASE) 210 /** Peripheral ERM_4 base address */ 211 #define IP_ERM_4_BASE (0x42070000u) 212 /** Peripheral ERM_4 base pointer */ 213 #define IP_ERM_4 ((ERM_Type *)IP_ERM_4_BASE) 214 /** Peripheral ERM_5 base address */ 215 #define IP_ERM_5_BASE (0x42870000u) 216 /** Peripheral ERM_5 base pointer */ 217 #define IP_ERM_5 ((ERM_Type *)IP_ERM_5_BASE) 218 /** Peripheral SMU__ERM base address */ 219 #define IP_SMU__ERM_BASE (0x45010000u) 220 /** Peripheral SMU__ERM base pointer */ 221 #define IP_SMU__ERM ((ERM_Type *)IP_SMU__ERM_BASE) 222 /** Array initializer of ERM peripheral base addresses */ 223 #define IP_ERM_BASE_ADDRS { IP_CE_ERM_0_BASE, IP_CE_ERM_1_BASE, IP_CE_ERM_2_BASE, IP_ERM_0_BASE, IP_ERM_1_BASE, IP_ERM_2_BASE, IP_ERM_3_BASE, IP_ERM_4_BASE, IP_ERM_5_BASE, IP_SMU__ERM_BASE } 224 /** Array initializer of ERM peripheral base pointers */ 225 #define IP_ERM_BASE_PTRS { IP_CE_ERM_0, IP_CE_ERM_1, IP_CE_ERM_2, IP_ERM_0, IP_ERM_1, IP_ERM_2, IP_ERM_3, IP_ERM_4, IP_ERM_5, IP_SMU__ERM } 226 227 /* ---------------------------------------------------------------------------- 228 -- ERM Register Masks 229 ---------------------------------------------------------------------------- */ 230 231 /*! 232 * @addtogroup ERM_Register_Masks ERM Register Masks 233 * @{ 234 */ 235 236 /*! @name CR0 - ERM Configuration Register 0 */ 237 /*! @{ */ 238 239 #define ERM_CR0_ENCIE7_MASK (0x4U) 240 #define ERM_CR0_ENCIE7_SHIFT (2U) 241 #define ERM_CR0_ENCIE7_WIDTH (1U) 242 #define ERM_CR0_ENCIE7(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR0_ENCIE7_SHIFT)) & ERM_CR0_ENCIE7_MASK) 243 244 #define ERM_CR0_ESCIE7_MASK (0x8U) 245 #define ERM_CR0_ESCIE7_SHIFT (3U) 246 #define ERM_CR0_ESCIE7_WIDTH (1U) 247 #define ERM_CR0_ESCIE7(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR0_ESCIE7_SHIFT)) & ERM_CR0_ESCIE7_MASK) 248 249 #define ERM_CR0_ENCIE6_MASK (0x40U) 250 #define ERM_CR0_ENCIE6_SHIFT (6U) 251 #define ERM_CR0_ENCIE6_WIDTH (1U) 252 #define ERM_CR0_ENCIE6(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR0_ENCIE6_SHIFT)) & ERM_CR0_ENCIE6_MASK) 253 254 #define ERM_CR0_ESCIE6_MASK (0x80U) 255 #define ERM_CR0_ESCIE6_SHIFT (7U) 256 #define ERM_CR0_ESCIE6_WIDTH (1U) 257 #define ERM_CR0_ESCIE6(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR0_ESCIE6_SHIFT)) & ERM_CR0_ESCIE6_MASK) 258 259 #define ERM_CR0_ENCIE5_MASK (0x400U) 260 #define ERM_CR0_ENCIE5_SHIFT (10U) 261 #define ERM_CR0_ENCIE5_WIDTH (1U) 262 #define ERM_CR0_ENCIE5(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR0_ENCIE5_SHIFT)) & ERM_CR0_ENCIE5_MASK) 263 264 #define ERM_CR0_ESCIE5_MASK (0x800U) 265 #define ERM_CR0_ESCIE5_SHIFT (11U) 266 #define ERM_CR0_ESCIE5_WIDTH (1U) 267 #define ERM_CR0_ESCIE5(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR0_ESCIE5_SHIFT)) & ERM_CR0_ESCIE5_MASK) 268 269 #define ERM_CR0_ENCIE4_MASK (0x4000U) 270 #define ERM_CR0_ENCIE4_SHIFT (14U) 271 #define ERM_CR0_ENCIE4_WIDTH (1U) 272 #define ERM_CR0_ENCIE4(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR0_ENCIE4_SHIFT)) & ERM_CR0_ENCIE4_MASK) 273 274 #define ERM_CR0_ESCIE4_MASK (0x8000U) 275 #define ERM_CR0_ESCIE4_SHIFT (15U) 276 #define ERM_CR0_ESCIE4_WIDTH (1U) 277 #define ERM_CR0_ESCIE4(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR0_ESCIE4_SHIFT)) & ERM_CR0_ESCIE4_MASK) 278 279 #define ERM_CR0_ENCIE3_MASK (0x40000U) 280 #define ERM_CR0_ENCIE3_SHIFT (18U) 281 #define ERM_CR0_ENCIE3_WIDTH (1U) 282 #define ERM_CR0_ENCIE3(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR0_ENCIE3_SHIFT)) & ERM_CR0_ENCIE3_MASK) 283 284 #define ERM_CR0_ESCIE3_MASK (0x80000U) 285 #define ERM_CR0_ESCIE3_SHIFT (19U) 286 #define ERM_CR0_ESCIE3_WIDTH (1U) 287 #define ERM_CR0_ESCIE3(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR0_ESCIE3_SHIFT)) & ERM_CR0_ESCIE3_MASK) 288 289 #define ERM_CR0_ENCIE2_MASK (0x400000U) 290 #define ERM_CR0_ENCIE2_SHIFT (22U) 291 #define ERM_CR0_ENCIE2_WIDTH (1U) 292 #define ERM_CR0_ENCIE2(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR0_ENCIE2_SHIFT)) & ERM_CR0_ENCIE2_MASK) 293 294 #define ERM_CR0_ESCIE2_MASK (0x800000U) 295 #define ERM_CR0_ESCIE2_SHIFT (23U) 296 #define ERM_CR0_ESCIE2_WIDTH (1U) 297 #define ERM_CR0_ESCIE2(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR0_ESCIE2_SHIFT)) & ERM_CR0_ESCIE2_MASK) 298 299 #define ERM_CR0_ENCIE1_MASK (0x4000000U) 300 #define ERM_CR0_ENCIE1_SHIFT (26U) 301 #define ERM_CR0_ENCIE1_WIDTH (1U) 302 #define ERM_CR0_ENCIE1(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR0_ENCIE1_SHIFT)) & ERM_CR0_ENCIE1_MASK) 303 304 #define ERM_CR0_ESCIE1_MASK (0x8000000U) 305 #define ERM_CR0_ESCIE1_SHIFT (27U) 306 #define ERM_CR0_ESCIE1_WIDTH (1U) 307 #define ERM_CR0_ESCIE1(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR0_ESCIE1_SHIFT)) & ERM_CR0_ESCIE1_MASK) 308 309 #define ERM_CR0_ENCIE0_MASK (0x40000000U) 310 #define ERM_CR0_ENCIE0_SHIFT (30U) 311 #define ERM_CR0_ENCIE0_WIDTH (1U) 312 #define ERM_CR0_ENCIE0(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR0_ENCIE0_SHIFT)) & ERM_CR0_ENCIE0_MASK) 313 314 #define ERM_CR0_ESCIE0_MASK (0x80000000U) 315 #define ERM_CR0_ESCIE0_SHIFT (31U) 316 #define ERM_CR0_ESCIE0_WIDTH (1U) 317 #define ERM_CR0_ESCIE0(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR0_ESCIE0_SHIFT)) & ERM_CR0_ESCIE0_MASK) 318 /*! @} */ 319 320 /*! @name CR1 - ERM Configuration Register 1 */ 321 /*! @{ */ 322 323 #define ERM_CR1_ENCIE15_MASK (0x4U) 324 #define ERM_CR1_ENCIE15_SHIFT (2U) 325 #define ERM_CR1_ENCIE15_WIDTH (1U) 326 #define ERM_CR1_ENCIE15(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR1_ENCIE15_SHIFT)) & ERM_CR1_ENCIE15_MASK) 327 328 #define ERM_CR1_ESCIE15_MASK (0x8U) 329 #define ERM_CR1_ESCIE15_SHIFT (3U) 330 #define ERM_CR1_ESCIE15_WIDTH (1U) 331 #define ERM_CR1_ESCIE15(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR1_ESCIE15_SHIFT)) & ERM_CR1_ESCIE15_MASK) 332 333 #define ERM_CR1_ENCIE14_MASK (0x40U) 334 #define ERM_CR1_ENCIE14_SHIFT (6U) 335 #define ERM_CR1_ENCIE14_WIDTH (1U) 336 #define ERM_CR1_ENCIE14(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR1_ENCIE14_SHIFT)) & ERM_CR1_ENCIE14_MASK) 337 338 #define ERM_CR1_ESCIE14_MASK (0x80U) 339 #define ERM_CR1_ESCIE14_SHIFT (7U) 340 #define ERM_CR1_ESCIE14_WIDTH (1U) 341 #define ERM_CR1_ESCIE14(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR1_ESCIE14_SHIFT)) & ERM_CR1_ESCIE14_MASK) 342 343 #define ERM_CR1_ENCIE13_MASK (0x400U) 344 #define ERM_CR1_ENCIE13_SHIFT (10U) 345 #define ERM_CR1_ENCIE13_WIDTH (1U) 346 #define ERM_CR1_ENCIE13(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR1_ENCIE13_SHIFT)) & ERM_CR1_ENCIE13_MASK) 347 348 #define ERM_CR1_ESCIE13_MASK (0x800U) 349 #define ERM_CR1_ESCIE13_SHIFT (11U) 350 #define ERM_CR1_ESCIE13_WIDTH (1U) 351 #define ERM_CR1_ESCIE13(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR1_ESCIE13_SHIFT)) & ERM_CR1_ESCIE13_MASK) 352 353 #define ERM_CR1_ENCIE12_MASK (0x4000U) 354 #define ERM_CR1_ENCIE12_SHIFT (14U) 355 #define ERM_CR1_ENCIE12_WIDTH (1U) 356 #define ERM_CR1_ENCIE12(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR1_ENCIE12_SHIFT)) & ERM_CR1_ENCIE12_MASK) 357 358 #define ERM_CR1_ESCIE12_MASK (0x8000U) 359 #define ERM_CR1_ESCIE12_SHIFT (15U) 360 #define ERM_CR1_ESCIE12_WIDTH (1U) 361 #define ERM_CR1_ESCIE12(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR1_ESCIE12_SHIFT)) & ERM_CR1_ESCIE12_MASK) 362 363 #define ERM_CR1_ENCIE11_MASK (0x40000U) 364 #define ERM_CR1_ENCIE11_SHIFT (18U) 365 #define ERM_CR1_ENCIE11_WIDTH (1U) 366 #define ERM_CR1_ENCIE11(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR1_ENCIE11_SHIFT)) & ERM_CR1_ENCIE11_MASK) 367 368 #define ERM_CR1_ESCIE11_MASK (0x80000U) 369 #define ERM_CR1_ESCIE11_SHIFT (19U) 370 #define ERM_CR1_ESCIE11_WIDTH (1U) 371 #define ERM_CR1_ESCIE11(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR1_ESCIE11_SHIFT)) & ERM_CR1_ESCIE11_MASK) 372 373 #define ERM_CR1_ENCIE10_MASK (0x400000U) 374 #define ERM_CR1_ENCIE10_SHIFT (22U) 375 #define ERM_CR1_ENCIE10_WIDTH (1U) 376 #define ERM_CR1_ENCIE10(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR1_ENCIE10_SHIFT)) & ERM_CR1_ENCIE10_MASK) 377 378 #define ERM_CR1_ESCIE10_MASK (0x800000U) 379 #define ERM_CR1_ESCIE10_SHIFT (23U) 380 #define ERM_CR1_ESCIE10_WIDTH (1U) 381 #define ERM_CR1_ESCIE10(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR1_ESCIE10_SHIFT)) & ERM_CR1_ESCIE10_MASK) 382 383 #define ERM_CR1_ENCIE9_MASK (0x4000000U) 384 #define ERM_CR1_ENCIE9_SHIFT (26U) 385 #define ERM_CR1_ENCIE9_WIDTH (1U) 386 #define ERM_CR1_ENCIE9(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR1_ENCIE9_SHIFT)) & ERM_CR1_ENCIE9_MASK) 387 388 #define ERM_CR1_ESCIE9_MASK (0x8000000U) 389 #define ERM_CR1_ESCIE9_SHIFT (27U) 390 #define ERM_CR1_ESCIE9_WIDTH (1U) 391 #define ERM_CR1_ESCIE9(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR1_ESCIE9_SHIFT)) & ERM_CR1_ESCIE9_MASK) 392 393 #define ERM_CR1_ENCIE8_MASK (0x40000000U) 394 #define ERM_CR1_ENCIE8_SHIFT (30U) 395 #define ERM_CR1_ENCIE8_WIDTH (1U) 396 #define ERM_CR1_ENCIE8(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR1_ENCIE8_SHIFT)) & ERM_CR1_ENCIE8_MASK) 397 398 #define ERM_CR1_ESCIE8_MASK (0x80000000U) 399 #define ERM_CR1_ESCIE8_SHIFT (31U) 400 #define ERM_CR1_ESCIE8_WIDTH (1U) 401 #define ERM_CR1_ESCIE8(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR1_ESCIE8_SHIFT)) & ERM_CR1_ESCIE8_MASK) 402 /*! @} */ 403 404 /*! @name CR2 - ERM Configuration Register 2 */ 405 /*! @{ */ 406 407 #define ERM_CR2_ENCIE23_MASK (0x4U) 408 #define ERM_CR2_ENCIE23_SHIFT (2U) 409 #define ERM_CR2_ENCIE23_WIDTH (1U) 410 #define ERM_CR2_ENCIE23(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR2_ENCIE23_SHIFT)) & ERM_CR2_ENCIE23_MASK) 411 412 #define ERM_CR2_ESCIE23_MASK (0x8U) 413 #define ERM_CR2_ESCIE23_SHIFT (3U) 414 #define ERM_CR2_ESCIE23_WIDTH (1U) 415 #define ERM_CR2_ESCIE23(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR2_ESCIE23_SHIFT)) & ERM_CR2_ESCIE23_MASK) 416 417 #define ERM_CR2_ENCIE22_MASK (0x40U) 418 #define ERM_CR2_ENCIE22_SHIFT (6U) 419 #define ERM_CR2_ENCIE22_WIDTH (1U) 420 #define ERM_CR2_ENCIE22(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR2_ENCIE22_SHIFT)) & ERM_CR2_ENCIE22_MASK) 421 422 #define ERM_CR2_ESCIE22_MASK (0x80U) 423 #define ERM_CR2_ESCIE22_SHIFT (7U) 424 #define ERM_CR2_ESCIE22_WIDTH (1U) 425 #define ERM_CR2_ESCIE22(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR2_ESCIE22_SHIFT)) & ERM_CR2_ESCIE22_MASK) 426 427 #define ERM_CR2_ENCIE21_MASK (0x400U) 428 #define ERM_CR2_ENCIE21_SHIFT (10U) 429 #define ERM_CR2_ENCIE21_WIDTH (1U) 430 #define ERM_CR2_ENCIE21(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR2_ENCIE21_SHIFT)) & ERM_CR2_ENCIE21_MASK) 431 432 #define ERM_CR2_ESCIE21_MASK (0x800U) 433 #define ERM_CR2_ESCIE21_SHIFT (11U) 434 #define ERM_CR2_ESCIE21_WIDTH (1U) 435 #define ERM_CR2_ESCIE21(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR2_ESCIE21_SHIFT)) & ERM_CR2_ESCIE21_MASK) 436 437 #define ERM_CR2_ENCIE20_MASK (0x4000U) 438 #define ERM_CR2_ENCIE20_SHIFT (14U) 439 #define ERM_CR2_ENCIE20_WIDTH (1U) 440 #define ERM_CR2_ENCIE20(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR2_ENCIE20_SHIFT)) & ERM_CR2_ENCIE20_MASK) 441 442 #define ERM_CR2_ESCIE20_MASK (0x8000U) 443 #define ERM_CR2_ESCIE20_SHIFT (15U) 444 #define ERM_CR2_ESCIE20_WIDTH (1U) 445 #define ERM_CR2_ESCIE20(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR2_ESCIE20_SHIFT)) & ERM_CR2_ESCIE20_MASK) 446 447 #define ERM_CR2_ENCIE19_MASK (0x40000U) 448 #define ERM_CR2_ENCIE19_SHIFT (18U) 449 #define ERM_CR2_ENCIE19_WIDTH (1U) 450 #define ERM_CR2_ENCIE19(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR2_ENCIE19_SHIFT)) & ERM_CR2_ENCIE19_MASK) 451 452 #define ERM_CR2_ESCIE19_MASK (0x80000U) 453 #define ERM_CR2_ESCIE19_SHIFT (19U) 454 #define ERM_CR2_ESCIE19_WIDTH (1U) 455 #define ERM_CR2_ESCIE19(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR2_ESCIE19_SHIFT)) & ERM_CR2_ESCIE19_MASK) 456 457 #define ERM_CR2_ENCIE18_MASK (0x400000U) 458 #define ERM_CR2_ENCIE18_SHIFT (22U) 459 #define ERM_CR2_ENCIE18_WIDTH (1U) 460 #define ERM_CR2_ENCIE18(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR2_ENCIE18_SHIFT)) & ERM_CR2_ENCIE18_MASK) 461 462 #define ERM_CR2_ESCIE18_MASK (0x800000U) 463 #define ERM_CR2_ESCIE18_SHIFT (23U) 464 #define ERM_CR2_ESCIE18_WIDTH (1U) 465 #define ERM_CR2_ESCIE18(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR2_ESCIE18_SHIFT)) & ERM_CR2_ESCIE18_MASK) 466 467 #define ERM_CR2_ENCIE17_MASK (0x4000000U) 468 #define ERM_CR2_ENCIE17_SHIFT (26U) 469 #define ERM_CR2_ENCIE17_WIDTH (1U) 470 #define ERM_CR2_ENCIE17(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR2_ENCIE17_SHIFT)) & ERM_CR2_ENCIE17_MASK) 471 472 #define ERM_CR2_ESCIE17_MASK (0x8000000U) 473 #define ERM_CR2_ESCIE17_SHIFT (27U) 474 #define ERM_CR2_ESCIE17_WIDTH (1U) 475 #define ERM_CR2_ESCIE17(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR2_ESCIE17_SHIFT)) & ERM_CR2_ESCIE17_MASK) 476 477 #define ERM_CR2_ENCIE16_MASK (0x40000000U) 478 #define ERM_CR2_ENCIE16_SHIFT (30U) 479 #define ERM_CR2_ENCIE16_WIDTH (1U) 480 #define ERM_CR2_ENCIE16(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR2_ENCIE16_SHIFT)) & ERM_CR2_ENCIE16_MASK) 481 482 #define ERM_CR2_ESCIE16_MASK (0x80000000U) 483 #define ERM_CR2_ESCIE16_SHIFT (31U) 484 #define ERM_CR2_ESCIE16_WIDTH (1U) 485 #define ERM_CR2_ESCIE16(x) (((uint32_t)(((uint32_t)(x)) << ERM_CR2_ESCIE16_SHIFT)) & ERM_CR2_ESCIE16_MASK) 486 /*! @} */ 487 488 /*! @name SR0 - ERM Status Register 0 */ 489 /*! @{ */ 490 491 #define ERM_SR0_NCE7_MASK (0x4U) 492 #define ERM_SR0_NCE7_SHIFT (2U) 493 #define ERM_SR0_NCE7_WIDTH (1U) 494 #define ERM_SR0_NCE7(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR0_NCE7_SHIFT)) & ERM_SR0_NCE7_MASK) 495 496 #define ERM_SR0_SBC7_MASK (0x8U) 497 #define ERM_SR0_SBC7_SHIFT (3U) 498 #define ERM_SR0_SBC7_WIDTH (1U) 499 #define ERM_SR0_SBC7(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR0_SBC7_SHIFT)) & ERM_SR0_SBC7_MASK) 500 501 #define ERM_SR0_NCE6_MASK (0x40U) 502 #define ERM_SR0_NCE6_SHIFT (6U) 503 #define ERM_SR0_NCE6_WIDTH (1U) 504 #define ERM_SR0_NCE6(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR0_NCE6_SHIFT)) & ERM_SR0_NCE6_MASK) 505 506 #define ERM_SR0_SBC6_MASK (0x80U) 507 #define ERM_SR0_SBC6_SHIFT (7U) 508 #define ERM_SR0_SBC6_WIDTH (1U) 509 #define ERM_SR0_SBC6(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR0_SBC6_SHIFT)) & ERM_SR0_SBC6_MASK) 510 511 #define ERM_SR0_NCE5_MASK (0x400U) 512 #define ERM_SR0_NCE5_SHIFT (10U) 513 #define ERM_SR0_NCE5_WIDTH (1U) 514 #define ERM_SR0_NCE5(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR0_NCE5_SHIFT)) & ERM_SR0_NCE5_MASK) 515 516 #define ERM_SR0_SBC5_MASK (0x800U) 517 #define ERM_SR0_SBC5_SHIFT (11U) 518 #define ERM_SR0_SBC5_WIDTH (1U) 519 #define ERM_SR0_SBC5(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR0_SBC5_SHIFT)) & ERM_SR0_SBC5_MASK) 520 521 #define ERM_SR0_NCE4_MASK (0x4000U) 522 #define ERM_SR0_NCE4_SHIFT (14U) 523 #define ERM_SR0_NCE4_WIDTH (1U) 524 #define ERM_SR0_NCE4(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR0_NCE4_SHIFT)) & ERM_SR0_NCE4_MASK) 525 526 #define ERM_SR0_SBC4_MASK (0x8000U) 527 #define ERM_SR0_SBC4_SHIFT (15U) 528 #define ERM_SR0_SBC4_WIDTH (1U) 529 #define ERM_SR0_SBC4(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR0_SBC4_SHIFT)) & ERM_SR0_SBC4_MASK) 530 531 #define ERM_SR0_NCE3_MASK (0x40000U) 532 #define ERM_SR0_NCE3_SHIFT (18U) 533 #define ERM_SR0_NCE3_WIDTH (1U) 534 #define ERM_SR0_NCE3(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR0_NCE3_SHIFT)) & ERM_SR0_NCE3_MASK) 535 536 #define ERM_SR0_SBC3_MASK (0x80000U) 537 #define ERM_SR0_SBC3_SHIFT (19U) 538 #define ERM_SR0_SBC3_WIDTH (1U) 539 #define ERM_SR0_SBC3(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR0_SBC3_SHIFT)) & ERM_SR0_SBC3_MASK) 540 541 #define ERM_SR0_NCE2_MASK (0x400000U) 542 #define ERM_SR0_NCE2_SHIFT (22U) 543 #define ERM_SR0_NCE2_WIDTH (1U) 544 #define ERM_SR0_NCE2(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR0_NCE2_SHIFT)) & ERM_SR0_NCE2_MASK) 545 546 #define ERM_SR0_SBC2_MASK (0x800000U) 547 #define ERM_SR0_SBC2_SHIFT (23U) 548 #define ERM_SR0_SBC2_WIDTH (1U) 549 #define ERM_SR0_SBC2(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR0_SBC2_SHIFT)) & ERM_SR0_SBC2_MASK) 550 551 #define ERM_SR0_NCE1_MASK (0x4000000U) 552 #define ERM_SR0_NCE1_SHIFT (26U) 553 #define ERM_SR0_NCE1_WIDTH (1U) 554 #define ERM_SR0_NCE1(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR0_NCE1_SHIFT)) & ERM_SR0_NCE1_MASK) 555 556 #define ERM_SR0_SBC1_MASK (0x8000000U) 557 #define ERM_SR0_SBC1_SHIFT (27U) 558 #define ERM_SR0_SBC1_WIDTH (1U) 559 #define ERM_SR0_SBC1(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR0_SBC1_SHIFT)) & ERM_SR0_SBC1_MASK) 560 561 #define ERM_SR0_NCE0_MASK (0x40000000U) 562 #define ERM_SR0_NCE0_SHIFT (30U) 563 #define ERM_SR0_NCE0_WIDTH (1U) 564 #define ERM_SR0_NCE0(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR0_NCE0_SHIFT)) & ERM_SR0_NCE0_MASK) 565 566 #define ERM_SR0_SBC0_MASK (0x80000000U) 567 #define ERM_SR0_SBC0_SHIFT (31U) 568 #define ERM_SR0_SBC0_WIDTH (1U) 569 #define ERM_SR0_SBC0(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR0_SBC0_SHIFT)) & ERM_SR0_SBC0_MASK) 570 /*! @} */ 571 572 /*! @name SR1 - ERM Status Register 1 */ 573 /*! @{ */ 574 575 #define ERM_SR1_NCE15_MASK (0x4U) 576 #define ERM_SR1_NCE15_SHIFT (2U) 577 #define ERM_SR1_NCE15_WIDTH (1U) 578 #define ERM_SR1_NCE15(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR1_NCE15_SHIFT)) & ERM_SR1_NCE15_MASK) 579 580 #define ERM_SR1_SBC15_MASK (0x8U) 581 #define ERM_SR1_SBC15_SHIFT (3U) 582 #define ERM_SR1_SBC15_WIDTH (1U) 583 #define ERM_SR1_SBC15(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR1_SBC15_SHIFT)) & ERM_SR1_SBC15_MASK) 584 585 #define ERM_SR1_NCE14_MASK (0x40U) 586 #define ERM_SR1_NCE14_SHIFT (6U) 587 #define ERM_SR1_NCE14_WIDTH (1U) 588 #define ERM_SR1_NCE14(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR1_NCE14_SHIFT)) & ERM_SR1_NCE14_MASK) 589 590 #define ERM_SR1_SBC14_MASK (0x80U) 591 #define ERM_SR1_SBC14_SHIFT (7U) 592 #define ERM_SR1_SBC14_WIDTH (1U) 593 #define ERM_SR1_SBC14(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR1_SBC14_SHIFT)) & ERM_SR1_SBC14_MASK) 594 595 #define ERM_SR1_NCE13_MASK (0x400U) 596 #define ERM_SR1_NCE13_SHIFT (10U) 597 #define ERM_SR1_NCE13_WIDTH (1U) 598 #define ERM_SR1_NCE13(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR1_NCE13_SHIFT)) & ERM_SR1_NCE13_MASK) 599 600 #define ERM_SR1_SBC13_MASK (0x800U) 601 #define ERM_SR1_SBC13_SHIFT (11U) 602 #define ERM_SR1_SBC13_WIDTH (1U) 603 #define ERM_SR1_SBC13(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR1_SBC13_SHIFT)) & ERM_SR1_SBC13_MASK) 604 605 #define ERM_SR1_NCE12_MASK (0x4000U) 606 #define ERM_SR1_NCE12_SHIFT (14U) 607 #define ERM_SR1_NCE12_WIDTH (1U) 608 #define ERM_SR1_NCE12(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR1_NCE12_SHIFT)) & ERM_SR1_NCE12_MASK) 609 610 #define ERM_SR1_SBC12_MASK (0x8000U) 611 #define ERM_SR1_SBC12_SHIFT (15U) 612 #define ERM_SR1_SBC12_WIDTH (1U) 613 #define ERM_SR1_SBC12(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR1_SBC12_SHIFT)) & ERM_SR1_SBC12_MASK) 614 615 #define ERM_SR1_NCE11_MASK (0x40000U) 616 #define ERM_SR1_NCE11_SHIFT (18U) 617 #define ERM_SR1_NCE11_WIDTH (1U) 618 #define ERM_SR1_NCE11(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR1_NCE11_SHIFT)) & ERM_SR1_NCE11_MASK) 619 620 #define ERM_SR1_SBC11_MASK (0x80000U) 621 #define ERM_SR1_SBC11_SHIFT (19U) 622 #define ERM_SR1_SBC11_WIDTH (1U) 623 #define ERM_SR1_SBC11(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR1_SBC11_SHIFT)) & ERM_SR1_SBC11_MASK) 624 625 #define ERM_SR1_NCE10_MASK (0x400000U) 626 #define ERM_SR1_NCE10_SHIFT (22U) 627 #define ERM_SR1_NCE10_WIDTH (1U) 628 #define ERM_SR1_NCE10(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR1_NCE10_SHIFT)) & ERM_SR1_NCE10_MASK) 629 630 #define ERM_SR1_SBC10_MASK (0x800000U) 631 #define ERM_SR1_SBC10_SHIFT (23U) 632 #define ERM_SR1_SBC10_WIDTH (1U) 633 #define ERM_SR1_SBC10(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR1_SBC10_SHIFT)) & ERM_SR1_SBC10_MASK) 634 635 #define ERM_SR1_NCE9_MASK (0x4000000U) 636 #define ERM_SR1_NCE9_SHIFT (26U) 637 #define ERM_SR1_NCE9_WIDTH (1U) 638 #define ERM_SR1_NCE9(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR1_NCE9_SHIFT)) & ERM_SR1_NCE9_MASK) 639 640 #define ERM_SR1_SBC9_MASK (0x8000000U) 641 #define ERM_SR1_SBC9_SHIFT (27U) 642 #define ERM_SR1_SBC9_WIDTH (1U) 643 #define ERM_SR1_SBC9(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR1_SBC9_SHIFT)) & ERM_SR1_SBC9_MASK) 644 645 #define ERM_SR1_NCE8_MASK (0x40000000U) 646 #define ERM_SR1_NCE8_SHIFT (30U) 647 #define ERM_SR1_NCE8_WIDTH (1U) 648 #define ERM_SR1_NCE8(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR1_NCE8_SHIFT)) & ERM_SR1_NCE8_MASK) 649 650 #define ERM_SR1_SBC8_MASK (0x80000000U) 651 #define ERM_SR1_SBC8_SHIFT (31U) 652 #define ERM_SR1_SBC8_WIDTH (1U) 653 #define ERM_SR1_SBC8(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR1_SBC8_SHIFT)) & ERM_SR1_SBC8_MASK) 654 /*! @} */ 655 656 /*! @name SR2 - ERM Status Register 2 */ 657 /*! @{ */ 658 659 #define ERM_SR2_NCE23_MASK (0x4U) 660 #define ERM_SR2_NCE23_SHIFT (2U) 661 #define ERM_SR2_NCE23_WIDTH (1U) 662 #define ERM_SR2_NCE23(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR2_NCE23_SHIFT)) & ERM_SR2_NCE23_MASK) 663 664 #define ERM_SR2_SBC23_MASK (0x8U) 665 #define ERM_SR2_SBC23_SHIFT (3U) 666 #define ERM_SR2_SBC23_WIDTH (1U) 667 #define ERM_SR2_SBC23(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR2_SBC23_SHIFT)) & ERM_SR2_SBC23_MASK) 668 669 #define ERM_SR2_NCE22_MASK (0x40U) 670 #define ERM_SR2_NCE22_SHIFT (6U) 671 #define ERM_SR2_NCE22_WIDTH (1U) 672 #define ERM_SR2_NCE22(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR2_NCE22_SHIFT)) & ERM_SR2_NCE22_MASK) 673 674 #define ERM_SR2_SBC22_MASK (0x80U) 675 #define ERM_SR2_SBC22_SHIFT (7U) 676 #define ERM_SR2_SBC22_WIDTH (1U) 677 #define ERM_SR2_SBC22(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR2_SBC22_SHIFT)) & ERM_SR2_SBC22_MASK) 678 679 #define ERM_SR2_NCE21_MASK (0x400U) 680 #define ERM_SR2_NCE21_SHIFT (10U) 681 #define ERM_SR2_NCE21_WIDTH (1U) 682 #define ERM_SR2_NCE21(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR2_NCE21_SHIFT)) & ERM_SR2_NCE21_MASK) 683 684 #define ERM_SR2_SBC21_MASK (0x800U) 685 #define ERM_SR2_SBC21_SHIFT (11U) 686 #define ERM_SR2_SBC21_WIDTH (1U) 687 #define ERM_SR2_SBC21(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR2_SBC21_SHIFT)) & ERM_SR2_SBC21_MASK) 688 689 #define ERM_SR2_NCE20_MASK (0x4000U) 690 #define ERM_SR2_NCE20_SHIFT (14U) 691 #define ERM_SR2_NCE20_WIDTH (1U) 692 #define ERM_SR2_NCE20(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR2_NCE20_SHIFT)) & ERM_SR2_NCE20_MASK) 693 694 #define ERM_SR2_SBC20_MASK (0x8000U) 695 #define ERM_SR2_SBC20_SHIFT (15U) 696 #define ERM_SR2_SBC20_WIDTH (1U) 697 #define ERM_SR2_SBC20(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR2_SBC20_SHIFT)) & ERM_SR2_SBC20_MASK) 698 699 #define ERM_SR2_NCE19_MASK (0x40000U) 700 #define ERM_SR2_NCE19_SHIFT (18U) 701 #define ERM_SR2_NCE19_WIDTH (1U) 702 #define ERM_SR2_NCE19(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR2_NCE19_SHIFT)) & ERM_SR2_NCE19_MASK) 703 704 #define ERM_SR2_SBC19_MASK (0x80000U) 705 #define ERM_SR2_SBC19_SHIFT (19U) 706 #define ERM_SR2_SBC19_WIDTH (1U) 707 #define ERM_SR2_SBC19(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR2_SBC19_SHIFT)) & ERM_SR2_SBC19_MASK) 708 709 #define ERM_SR2_NCE18_MASK (0x400000U) 710 #define ERM_SR2_NCE18_SHIFT (22U) 711 #define ERM_SR2_NCE18_WIDTH (1U) 712 #define ERM_SR2_NCE18(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR2_NCE18_SHIFT)) & ERM_SR2_NCE18_MASK) 713 714 #define ERM_SR2_SBC18_MASK (0x800000U) 715 #define ERM_SR2_SBC18_SHIFT (23U) 716 #define ERM_SR2_SBC18_WIDTH (1U) 717 #define ERM_SR2_SBC18(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR2_SBC18_SHIFT)) & ERM_SR2_SBC18_MASK) 718 719 #define ERM_SR2_NCE17_MASK (0x4000000U) 720 #define ERM_SR2_NCE17_SHIFT (26U) 721 #define ERM_SR2_NCE17_WIDTH (1U) 722 #define ERM_SR2_NCE17(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR2_NCE17_SHIFT)) & ERM_SR2_NCE17_MASK) 723 724 #define ERM_SR2_SBC17_MASK (0x8000000U) 725 #define ERM_SR2_SBC17_SHIFT (27U) 726 #define ERM_SR2_SBC17_WIDTH (1U) 727 #define ERM_SR2_SBC17(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR2_SBC17_SHIFT)) & ERM_SR2_SBC17_MASK) 728 729 #define ERM_SR2_NCE16_MASK (0x40000000U) 730 #define ERM_SR2_NCE16_SHIFT (30U) 731 #define ERM_SR2_NCE16_WIDTH (1U) 732 #define ERM_SR2_NCE16(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR2_NCE16_SHIFT)) & ERM_SR2_NCE16_MASK) 733 734 #define ERM_SR2_SBC16_MASK (0x80000000U) 735 #define ERM_SR2_SBC16_SHIFT (31U) 736 #define ERM_SR2_SBC16_WIDTH (1U) 737 #define ERM_SR2_SBC16(x) (((uint32_t)(((uint32_t)(x)) << ERM_SR2_SBC16_SHIFT)) & ERM_SR2_SBC16_MASK) 738 /*! @} */ 739 740 /*! @name EAR0 - ERM Memory 0 Error Address Register */ 741 /*! @{ */ 742 743 #define ERM_EAR0_EAR_MASK (0xFFFFFFFFU) 744 #define ERM_EAR0_EAR_SHIFT (0U) 745 #define ERM_EAR0_EAR_WIDTH (32U) 746 #define ERM_EAR0_EAR(x) (((uint32_t)(((uint32_t)(x)) << ERM_EAR0_EAR_SHIFT)) & ERM_EAR0_EAR_MASK) 747 /*! @} */ 748 749 /*! @name SYN0 - ERM Memory 0 Syndrome Register */ 750 /*! @{ */ 751 752 #define ERM_SYN0_SYNDROME_MASK (0xFF000000U) 753 #define ERM_SYN0_SYNDROME_SHIFT (24U) 754 #define ERM_SYN0_SYNDROME_WIDTH (8U) 755 #define ERM_SYN0_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << ERM_SYN0_SYNDROME_SHIFT)) & ERM_SYN0_SYNDROME_MASK) 756 /*! @} */ 757 758 /*! @name CORR_ERR_CNT0 - ERM Memory 0 Correctable Error Count Register */ 759 /*! @{ */ 760 761 #define ERM_CORR_ERR_CNT0_COUNT_MASK (0xFFU) 762 #define ERM_CORR_ERR_CNT0_COUNT_SHIFT (0U) 763 #define ERM_CORR_ERR_CNT0_COUNT_WIDTH (8U) 764 #define ERM_CORR_ERR_CNT0_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ERM_CORR_ERR_CNT0_COUNT_SHIFT)) & ERM_CORR_ERR_CNT0_COUNT_MASK) 765 /*! @} */ 766 767 /*! @name EAR1 - ERM Memory 1 Error Address Register */ 768 /*! @{ */ 769 770 #define ERM_EAR1_EAR_MASK (0xFFFFFFFFU) 771 #define ERM_EAR1_EAR_SHIFT (0U) 772 #define ERM_EAR1_EAR_WIDTH (32U) 773 #define ERM_EAR1_EAR(x) (((uint32_t)(((uint32_t)(x)) << ERM_EAR1_EAR_SHIFT)) & ERM_EAR1_EAR_MASK) 774 /*! @} */ 775 776 /*! @name SYN1 - ERM Memory 1 Syndrome Register */ 777 /*! @{ */ 778 779 #define ERM_SYN1_SYNDROME_MASK (0xFF000000U) 780 #define ERM_SYN1_SYNDROME_SHIFT (24U) 781 #define ERM_SYN1_SYNDROME_WIDTH (8U) 782 #define ERM_SYN1_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << ERM_SYN1_SYNDROME_SHIFT)) & ERM_SYN1_SYNDROME_MASK) 783 /*! @} */ 784 785 /*! @name CORR_ERR_CNT1 - ERM Memory 1 Correctable Error Count Register */ 786 /*! @{ */ 787 788 #define ERM_CORR_ERR_CNT1_COUNT_MASK (0xFFU) 789 #define ERM_CORR_ERR_CNT1_COUNT_SHIFT (0U) 790 #define ERM_CORR_ERR_CNT1_COUNT_WIDTH (8U) 791 #define ERM_CORR_ERR_CNT1_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ERM_CORR_ERR_CNT1_COUNT_SHIFT)) & ERM_CORR_ERR_CNT1_COUNT_MASK) 792 /*! @} */ 793 794 /*! @name EAR2 - ERM Memory 2 Error Address Register */ 795 /*! @{ */ 796 797 #define ERM_EAR2_EAR_MASK (0xFFFFFFFFU) 798 #define ERM_EAR2_EAR_SHIFT (0U) 799 #define ERM_EAR2_EAR_WIDTH (32U) 800 #define ERM_EAR2_EAR(x) (((uint32_t)(((uint32_t)(x)) << ERM_EAR2_EAR_SHIFT)) & ERM_EAR2_EAR_MASK) 801 /*! @} */ 802 803 /*! @name SYN2 - ERM Memory 2 Syndrome Register */ 804 /*! @{ */ 805 806 #define ERM_SYN2_SYNDROME_MASK (0xFF000000U) 807 #define ERM_SYN2_SYNDROME_SHIFT (24U) 808 #define ERM_SYN2_SYNDROME_WIDTH (8U) 809 #define ERM_SYN2_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << ERM_SYN2_SYNDROME_SHIFT)) & ERM_SYN2_SYNDROME_MASK) 810 /*! @} */ 811 812 /*! @name CORR_ERR_CNT2 - ERM Memory 2 Correctable Error Count Register */ 813 /*! @{ */ 814 815 #define ERM_CORR_ERR_CNT2_COUNT_MASK (0xFFU) 816 #define ERM_CORR_ERR_CNT2_COUNT_SHIFT (0U) 817 #define ERM_CORR_ERR_CNT2_COUNT_WIDTH (8U) 818 #define ERM_CORR_ERR_CNT2_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ERM_CORR_ERR_CNT2_COUNT_SHIFT)) & ERM_CORR_ERR_CNT2_COUNT_MASK) 819 /*! @} */ 820 821 /*! @name EAR3 - ERM Memory 3 Error Address Register */ 822 /*! @{ */ 823 824 #define ERM_EAR3_EAR_MASK (0xFFFFFFFFU) 825 #define ERM_EAR3_EAR_SHIFT (0U) 826 #define ERM_EAR3_EAR_WIDTH (32U) 827 #define ERM_EAR3_EAR(x) (((uint32_t)(((uint32_t)(x)) << ERM_EAR3_EAR_SHIFT)) & ERM_EAR3_EAR_MASK) 828 /*! @} */ 829 830 /*! @name SYN3 - ERM Memory 3 Syndrome Register */ 831 /*! @{ */ 832 833 #define ERM_SYN3_SYNDROME_MASK (0xFF000000U) 834 #define ERM_SYN3_SYNDROME_SHIFT (24U) 835 #define ERM_SYN3_SYNDROME_WIDTH (8U) 836 #define ERM_SYN3_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << ERM_SYN3_SYNDROME_SHIFT)) & ERM_SYN3_SYNDROME_MASK) 837 /*! @} */ 838 839 /*! @name CORR_ERR_CNT3 - ERM Memory 3 Correctable Error Count Register */ 840 /*! @{ */ 841 842 #define ERM_CORR_ERR_CNT3_COUNT_MASK (0xFFU) 843 #define ERM_CORR_ERR_CNT3_COUNT_SHIFT (0U) 844 #define ERM_CORR_ERR_CNT3_COUNT_WIDTH (8U) 845 #define ERM_CORR_ERR_CNT3_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ERM_CORR_ERR_CNT3_COUNT_SHIFT)) & ERM_CORR_ERR_CNT3_COUNT_MASK) 846 /*! @} */ 847 848 /*! @name EAR4 - ERM Memory 4 Error Address Register */ 849 /*! @{ */ 850 851 #define ERM_EAR4_EAR_MASK (0xFFFFFFFFU) 852 #define ERM_EAR4_EAR_SHIFT (0U) 853 #define ERM_EAR4_EAR_WIDTH (32U) 854 #define ERM_EAR4_EAR(x) (((uint32_t)(((uint32_t)(x)) << ERM_EAR4_EAR_SHIFT)) & ERM_EAR4_EAR_MASK) 855 /*! @} */ 856 857 /*! @name CORR_ERR_CNT4 - ERM Memory 4 Correctable Error Count Register */ 858 /*! @{ */ 859 860 #define ERM_CORR_ERR_CNT4_COUNT_MASK (0xFFU) 861 #define ERM_CORR_ERR_CNT4_COUNT_SHIFT (0U) 862 #define ERM_CORR_ERR_CNT4_COUNT_WIDTH (8U) 863 #define ERM_CORR_ERR_CNT4_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ERM_CORR_ERR_CNT4_COUNT_SHIFT)) & ERM_CORR_ERR_CNT4_COUNT_MASK) 864 /*! @} */ 865 866 /*! @name EAR5 - ERM Memory 5 Error Address Register */ 867 /*! @{ */ 868 869 #define ERM_EAR5_EAR_MASK (0xFFFFFFFFU) 870 #define ERM_EAR5_EAR_SHIFT (0U) 871 #define ERM_EAR5_EAR_WIDTH (32U) 872 #define ERM_EAR5_EAR(x) (((uint32_t)(((uint32_t)(x)) << ERM_EAR5_EAR_SHIFT)) & ERM_EAR5_EAR_MASK) 873 /*! @} */ 874 875 /*! @name SYN5 - ERM Memory 5 Syndrome Register */ 876 /*! @{ */ 877 878 #define ERM_SYN5_SYNDROME_MASK (0xFF000000U) 879 #define ERM_SYN5_SYNDROME_SHIFT (24U) 880 #define ERM_SYN5_SYNDROME_WIDTH (8U) 881 #define ERM_SYN5_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << ERM_SYN5_SYNDROME_SHIFT)) & ERM_SYN5_SYNDROME_MASK) 882 /*! @} */ 883 884 /*! @name CORR_ERR_CNT5 - ERM Memory 5 Correctable Error Count Register */ 885 /*! @{ */ 886 887 #define ERM_CORR_ERR_CNT5_COUNT_MASK (0xFFU) 888 #define ERM_CORR_ERR_CNT5_COUNT_SHIFT (0U) 889 #define ERM_CORR_ERR_CNT5_COUNT_WIDTH (8U) 890 #define ERM_CORR_ERR_CNT5_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ERM_CORR_ERR_CNT5_COUNT_SHIFT)) & ERM_CORR_ERR_CNT5_COUNT_MASK) 891 /*! @} */ 892 893 /*! @name EAR6 - ERM Memory 6 Error Address Register */ 894 /*! @{ */ 895 896 #define ERM_EAR6_EAR_MASK (0xFFFFFFFFU) 897 #define ERM_EAR6_EAR_SHIFT (0U) 898 #define ERM_EAR6_EAR_WIDTH (32U) 899 #define ERM_EAR6_EAR(x) (((uint32_t)(((uint32_t)(x)) << ERM_EAR6_EAR_SHIFT)) & ERM_EAR6_EAR_MASK) 900 /*! @} */ 901 902 /*! @name SYN6 - ERM Memory 6 Syndrome Register */ 903 /*! @{ */ 904 905 #define ERM_SYN6_SYNDROME_EXT_MASK (0x3U) 906 #define ERM_SYN6_SYNDROME_EXT_SHIFT (0U) 907 #define ERM_SYN6_SYNDROME_EXT_WIDTH (2U) 908 #define ERM_SYN6_SYNDROME_EXT(x) (((uint32_t)(((uint32_t)(x)) << ERM_SYN6_SYNDROME_EXT_SHIFT)) & ERM_SYN6_SYNDROME_EXT_MASK) 909 910 #define ERM_SYN6_SYNDROME_MASK (0xFF000000U) 911 #define ERM_SYN6_SYNDROME_SHIFT (24U) 912 #define ERM_SYN6_SYNDROME_WIDTH (8U) 913 #define ERM_SYN6_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << ERM_SYN6_SYNDROME_SHIFT)) & ERM_SYN6_SYNDROME_MASK) 914 /*! @} */ 915 916 /*! @name CORR_ERR_CNT6 - ERM Memory 6 Correctable Error Count Register */ 917 /*! @{ */ 918 919 #define ERM_CORR_ERR_CNT6_COUNT_MASK (0xFFU) 920 #define ERM_CORR_ERR_CNT6_COUNT_SHIFT (0U) 921 #define ERM_CORR_ERR_CNT6_COUNT_WIDTH (8U) 922 #define ERM_CORR_ERR_CNT6_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ERM_CORR_ERR_CNT6_COUNT_SHIFT)) & ERM_CORR_ERR_CNT6_COUNT_MASK) 923 /*! @} */ 924 925 /*! @name EAR7 - ERM Memory 7 Error Address Register */ 926 /*! @{ */ 927 928 #define ERM_EAR7_EAR_MASK (0xFFFFFFFFU) 929 #define ERM_EAR7_EAR_SHIFT (0U) 930 #define ERM_EAR7_EAR_WIDTH (32U) 931 #define ERM_EAR7_EAR(x) (((uint32_t)(((uint32_t)(x)) << ERM_EAR7_EAR_SHIFT)) & ERM_EAR7_EAR_MASK) 932 /*! @} */ 933 934 /*! @name SYN7 - ERM Memory 7 Syndrome Register */ 935 /*! @{ */ 936 937 #define ERM_SYN7_SYNDROME_EXT_MASK (0x3U) 938 #define ERM_SYN7_SYNDROME_EXT_SHIFT (0U) 939 #define ERM_SYN7_SYNDROME_EXT_WIDTH (2U) 940 #define ERM_SYN7_SYNDROME_EXT(x) (((uint32_t)(((uint32_t)(x)) << ERM_SYN7_SYNDROME_EXT_SHIFT)) & ERM_SYN7_SYNDROME_EXT_MASK) 941 942 #define ERM_SYN7_SYNDROME_MASK (0xFF000000U) 943 #define ERM_SYN7_SYNDROME_SHIFT (24U) 944 #define ERM_SYN7_SYNDROME_WIDTH (8U) 945 #define ERM_SYN7_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << ERM_SYN7_SYNDROME_SHIFT)) & ERM_SYN7_SYNDROME_MASK) 946 /*! @} */ 947 948 /*! @name CORR_ERR_CNT7 - ERM Memory 7 Correctable Error Count Register */ 949 /*! @{ */ 950 951 #define ERM_CORR_ERR_CNT7_COUNT_MASK (0xFFU) 952 #define ERM_CORR_ERR_CNT7_COUNT_SHIFT (0U) 953 #define ERM_CORR_ERR_CNT7_COUNT_WIDTH (8U) 954 #define ERM_CORR_ERR_CNT7_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ERM_CORR_ERR_CNT7_COUNT_SHIFT)) & ERM_CORR_ERR_CNT7_COUNT_MASK) 955 /*! @} */ 956 957 /*! @name EAR8 - ERM Memory 8 Error Address Register */ 958 /*! @{ */ 959 960 #define ERM_EAR8_EAR_MASK (0xFFFFFFFFU) 961 #define ERM_EAR8_EAR_SHIFT (0U) 962 #define ERM_EAR8_EAR_WIDTH (32U) 963 #define ERM_EAR8_EAR(x) (((uint32_t)(((uint32_t)(x)) << ERM_EAR8_EAR_SHIFT)) & ERM_EAR8_EAR_MASK) 964 /*! @} */ 965 966 /*! @name SYN8 - ERM Memory 8 Syndrome Register */ 967 /*! @{ */ 968 969 #define ERM_SYN8_SYNDROME_EXT_MASK (0x3U) 970 #define ERM_SYN8_SYNDROME_EXT_SHIFT (0U) 971 #define ERM_SYN8_SYNDROME_EXT_WIDTH (2U) 972 #define ERM_SYN8_SYNDROME_EXT(x) (((uint32_t)(((uint32_t)(x)) << ERM_SYN8_SYNDROME_EXT_SHIFT)) & ERM_SYN8_SYNDROME_EXT_MASK) 973 974 #define ERM_SYN8_SYNDROME_MASK (0xFF000000U) 975 #define ERM_SYN8_SYNDROME_SHIFT (24U) 976 #define ERM_SYN8_SYNDROME_WIDTH (8U) 977 #define ERM_SYN8_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << ERM_SYN8_SYNDROME_SHIFT)) & ERM_SYN8_SYNDROME_MASK) 978 /*! @} */ 979 980 /*! @name CORR_ERR_CNT8 - ERM Memory 8 Correctable Error Count Register */ 981 /*! @{ */ 982 983 #define ERM_CORR_ERR_CNT8_COUNT_MASK (0xFFU) 984 #define ERM_CORR_ERR_CNT8_COUNT_SHIFT (0U) 985 #define ERM_CORR_ERR_CNT8_COUNT_WIDTH (8U) 986 #define ERM_CORR_ERR_CNT8_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ERM_CORR_ERR_CNT8_COUNT_SHIFT)) & ERM_CORR_ERR_CNT8_COUNT_MASK) 987 /*! @} */ 988 989 /*! @name EAR9 - ERM Memory 9 Error Address Register */ 990 /*! @{ */ 991 992 #define ERM_EAR9_EAR_MASK (0xFFFFFFFFU) 993 #define ERM_EAR9_EAR_SHIFT (0U) 994 #define ERM_EAR9_EAR_WIDTH (32U) 995 #define ERM_EAR9_EAR(x) (((uint32_t)(((uint32_t)(x)) << ERM_EAR9_EAR_SHIFT)) & ERM_EAR9_EAR_MASK) 996 /*! @} */ 997 998 /*! @name SYN9 - ERM Memory 9 Syndrome Register */ 999 /*! @{ */ 1000 1001 #define ERM_SYN9_SYNDROME_EXT_MASK (0x3U) 1002 #define ERM_SYN9_SYNDROME_EXT_SHIFT (0U) 1003 #define ERM_SYN9_SYNDROME_EXT_WIDTH (2U) 1004 #define ERM_SYN9_SYNDROME_EXT(x) (((uint32_t)(((uint32_t)(x)) << ERM_SYN9_SYNDROME_EXT_SHIFT)) & ERM_SYN9_SYNDROME_EXT_MASK) 1005 1006 #define ERM_SYN9_SYNDROME_MASK (0xFF000000U) 1007 #define ERM_SYN9_SYNDROME_SHIFT (24U) 1008 #define ERM_SYN9_SYNDROME_WIDTH (8U) 1009 #define ERM_SYN9_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << ERM_SYN9_SYNDROME_SHIFT)) & ERM_SYN9_SYNDROME_MASK) 1010 /*! @} */ 1011 1012 /*! @name CORR_ERR_CNT9 - ERM Memory 9 Correctable Error Count Register */ 1013 /*! @{ */ 1014 1015 #define ERM_CORR_ERR_CNT9_COUNT_MASK (0xFFU) 1016 #define ERM_CORR_ERR_CNT9_COUNT_SHIFT (0U) 1017 #define ERM_CORR_ERR_CNT9_COUNT_WIDTH (8U) 1018 #define ERM_CORR_ERR_CNT9_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ERM_CORR_ERR_CNT9_COUNT_SHIFT)) & ERM_CORR_ERR_CNT9_COUNT_MASK) 1019 /*! @} */ 1020 1021 /*! @name EAR10 - ERM Memory 10 Error Address Register */ 1022 /*! @{ */ 1023 1024 #define ERM_EAR10_EAR_MASK (0xFFFFFFFFU) 1025 #define ERM_EAR10_EAR_SHIFT (0U) 1026 #define ERM_EAR10_EAR_WIDTH (32U) 1027 #define ERM_EAR10_EAR(x) (((uint32_t)(((uint32_t)(x)) << ERM_EAR10_EAR_SHIFT)) & ERM_EAR10_EAR_MASK) 1028 /*! @} */ 1029 1030 /*! @name SYN10 - ERM Memory 10 Syndrome Register */ 1031 /*! @{ */ 1032 1033 #define ERM_SYN10_SYNDROME_MASK (0xFF000000U) 1034 #define ERM_SYN10_SYNDROME_SHIFT (24U) 1035 #define ERM_SYN10_SYNDROME_WIDTH (8U) 1036 #define ERM_SYN10_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << ERM_SYN10_SYNDROME_SHIFT)) & ERM_SYN10_SYNDROME_MASK) 1037 /*! @} */ 1038 1039 /*! @name CORR_ERR_CNT10 - ERM Memory 10 Correctable Error Count Register */ 1040 /*! @{ */ 1041 1042 #define ERM_CORR_ERR_CNT10_COUNT_MASK (0xFFU) 1043 #define ERM_CORR_ERR_CNT10_COUNT_SHIFT (0U) 1044 #define ERM_CORR_ERR_CNT10_COUNT_WIDTH (8U) 1045 #define ERM_CORR_ERR_CNT10_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ERM_CORR_ERR_CNT10_COUNT_SHIFT)) & ERM_CORR_ERR_CNT10_COUNT_MASK) 1046 /*! @} */ 1047 1048 /*! @name EAR11 - ERM Memory 11 Error Address Register */ 1049 /*! @{ */ 1050 1051 #define ERM_EAR11_EAR_MASK (0xFFFFFFFFU) 1052 #define ERM_EAR11_EAR_SHIFT (0U) 1053 #define ERM_EAR11_EAR_WIDTH (32U) 1054 #define ERM_EAR11_EAR(x) (((uint32_t)(((uint32_t)(x)) << ERM_EAR11_EAR_SHIFT)) & ERM_EAR11_EAR_MASK) 1055 /*! @} */ 1056 1057 /*! @name SYN11 - ERM Memory 11 Syndrome Register */ 1058 /*! @{ */ 1059 1060 #define ERM_SYN11_SYNDROME_MASK (0xFF000000U) 1061 #define ERM_SYN11_SYNDROME_SHIFT (24U) 1062 #define ERM_SYN11_SYNDROME_WIDTH (8U) 1063 #define ERM_SYN11_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << ERM_SYN11_SYNDROME_SHIFT)) & ERM_SYN11_SYNDROME_MASK) 1064 /*! @} */ 1065 1066 /*! @name CORR_ERR_CNT11 - ERM Memory 11 Correctable Error Count Register */ 1067 /*! @{ */ 1068 1069 #define ERM_CORR_ERR_CNT11_COUNT_MASK (0xFFU) 1070 #define ERM_CORR_ERR_CNT11_COUNT_SHIFT (0U) 1071 #define ERM_CORR_ERR_CNT11_COUNT_WIDTH (8U) 1072 #define ERM_CORR_ERR_CNT11_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ERM_CORR_ERR_CNT11_COUNT_SHIFT)) & ERM_CORR_ERR_CNT11_COUNT_MASK) 1073 /*! @} */ 1074 1075 /*! @name EAR12 - ERM Memory 12 Error Address Register */ 1076 /*! @{ */ 1077 1078 #define ERM_EAR12_EAR_MASK (0xFFFFFFFFU) 1079 #define ERM_EAR12_EAR_SHIFT (0U) 1080 #define ERM_EAR12_EAR_WIDTH (32U) 1081 #define ERM_EAR12_EAR(x) (((uint32_t)(((uint32_t)(x)) << ERM_EAR12_EAR_SHIFT)) & ERM_EAR12_EAR_MASK) 1082 /*! @} */ 1083 1084 /*! @name SYN12 - ERM Memory 12 Syndrome Register */ 1085 /*! @{ */ 1086 1087 #define ERM_SYN12_SYNDROME_MASK (0xFF000000U) 1088 #define ERM_SYN12_SYNDROME_SHIFT (24U) 1089 #define ERM_SYN12_SYNDROME_WIDTH (8U) 1090 #define ERM_SYN12_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << ERM_SYN12_SYNDROME_SHIFT)) & ERM_SYN12_SYNDROME_MASK) 1091 /*! @} */ 1092 1093 /*! @name CORR_ERR_CNT12 - ERM Memory 12 Correctable Error Count Register */ 1094 /*! @{ */ 1095 1096 #define ERM_CORR_ERR_CNT12_COUNT_MASK (0xFFU) 1097 #define ERM_CORR_ERR_CNT12_COUNT_SHIFT (0U) 1098 #define ERM_CORR_ERR_CNT12_COUNT_WIDTH (8U) 1099 #define ERM_CORR_ERR_CNT12_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ERM_CORR_ERR_CNT12_COUNT_SHIFT)) & ERM_CORR_ERR_CNT12_COUNT_MASK) 1100 /*! @} */ 1101 1102 /*! @name EAR13 - ERM Memory 13 Error Address Register */ 1103 /*! @{ */ 1104 1105 #define ERM_EAR13_EAR_MASK (0xFFFFFFFFU) 1106 #define ERM_EAR13_EAR_SHIFT (0U) 1107 #define ERM_EAR13_EAR_WIDTH (32U) 1108 #define ERM_EAR13_EAR(x) (((uint32_t)(((uint32_t)(x)) << ERM_EAR13_EAR_SHIFT)) & ERM_EAR13_EAR_MASK) 1109 /*! @} */ 1110 1111 /*! @name SYN13 - ERM Memory 13 Syndrome Register */ 1112 /*! @{ */ 1113 1114 #define ERM_SYN13_SYNDROME_MASK (0xFF000000U) 1115 #define ERM_SYN13_SYNDROME_SHIFT (24U) 1116 #define ERM_SYN13_SYNDROME_WIDTH (8U) 1117 #define ERM_SYN13_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << ERM_SYN13_SYNDROME_SHIFT)) & ERM_SYN13_SYNDROME_MASK) 1118 /*! @} */ 1119 1120 /*! @name CORR_ERR_CNT13 - ERM Memory 13 Correctable Error Count Register */ 1121 /*! @{ */ 1122 1123 #define ERM_CORR_ERR_CNT13_COUNT_MASK (0xFFU) 1124 #define ERM_CORR_ERR_CNT13_COUNT_SHIFT (0U) 1125 #define ERM_CORR_ERR_CNT13_COUNT_WIDTH (8U) 1126 #define ERM_CORR_ERR_CNT13_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ERM_CORR_ERR_CNT13_COUNT_SHIFT)) & ERM_CORR_ERR_CNT13_COUNT_MASK) 1127 /*! @} */ 1128 1129 /*! @name EAR14 - ERM Memory 14 Error Address Register */ 1130 /*! @{ */ 1131 1132 #define ERM_EAR14_EAR_MASK (0xFFFFFFFFU) 1133 #define ERM_EAR14_EAR_SHIFT (0U) 1134 #define ERM_EAR14_EAR_WIDTH (32U) 1135 #define ERM_EAR14_EAR(x) (((uint32_t)(((uint32_t)(x)) << ERM_EAR14_EAR_SHIFT)) & ERM_EAR14_EAR_MASK) 1136 /*! @} */ 1137 1138 /*! @name SYN14 - ERM Memory 14 Syndrome Register */ 1139 /*! @{ */ 1140 1141 #define ERM_SYN14_SYNDROME_MASK (0xFF000000U) 1142 #define ERM_SYN14_SYNDROME_SHIFT (24U) 1143 #define ERM_SYN14_SYNDROME_WIDTH (8U) 1144 #define ERM_SYN14_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << ERM_SYN14_SYNDROME_SHIFT)) & ERM_SYN14_SYNDROME_MASK) 1145 /*! @} */ 1146 1147 /*! @name CORR_ERR_CNT14 - ERM Memory 14 Correctable Error Count Register */ 1148 /*! @{ */ 1149 1150 #define ERM_CORR_ERR_CNT14_COUNT_MASK (0xFFU) 1151 #define ERM_CORR_ERR_CNT14_COUNT_SHIFT (0U) 1152 #define ERM_CORR_ERR_CNT14_COUNT_WIDTH (8U) 1153 #define ERM_CORR_ERR_CNT14_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ERM_CORR_ERR_CNT14_COUNT_SHIFT)) & ERM_CORR_ERR_CNT14_COUNT_MASK) 1154 /*! @} */ 1155 1156 /*! @name EAR15 - ERM Memory 15 Error Address Register */ 1157 /*! @{ */ 1158 1159 #define ERM_EAR15_EAR_MASK (0xFFFFFFFFU) 1160 #define ERM_EAR15_EAR_SHIFT (0U) 1161 #define ERM_EAR15_EAR_WIDTH (32U) 1162 #define ERM_EAR15_EAR(x) (((uint32_t)(((uint32_t)(x)) << ERM_EAR15_EAR_SHIFT)) & ERM_EAR15_EAR_MASK) 1163 /*! @} */ 1164 1165 /*! @name CORR_ERR_CNT15 - ERM Memory 15 Correctable Error Count Register */ 1166 /*! @{ */ 1167 1168 #define ERM_CORR_ERR_CNT15_COUNT_MASK (0xFFU) 1169 #define ERM_CORR_ERR_CNT15_COUNT_SHIFT (0U) 1170 #define ERM_CORR_ERR_CNT15_COUNT_WIDTH (8U) 1171 #define ERM_CORR_ERR_CNT15_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ERM_CORR_ERR_CNT15_COUNT_SHIFT)) & ERM_CORR_ERR_CNT15_COUNT_MASK) 1172 /*! @} */ 1173 1174 /*! @name EAR16 - ERM Memory 16 Error Address Register */ 1175 /*! @{ */ 1176 1177 #define ERM_EAR16_EAR_MASK (0xFFFFFFFFU) 1178 #define ERM_EAR16_EAR_SHIFT (0U) 1179 #define ERM_EAR16_EAR_WIDTH (32U) 1180 #define ERM_EAR16_EAR(x) (((uint32_t)(((uint32_t)(x)) << ERM_EAR16_EAR_SHIFT)) & ERM_EAR16_EAR_MASK) 1181 /*! @} */ 1182 1183 /*! @name CORR_ERR_CNT16 - ERM Memory 16 Correctable Error Count Register */ 1184 /*! @{ */ 1185 1186 #define ERM_CORR_ERR_CNT16_COUNT_MASK (0xFFU) 1187 #define ERM_CORR_ERR_CNT16_COUNT_SHIFT (0U) 1188 #define ERM_CORR_ERR_CNT16_COUNT_WIDTH (8U) 1189 #define ERM_CORR_ERR_CNT16_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ERM_CORR_ERR_CNT16_COUNT_SHIFT)) & ERM_CORR_ERR_CNT16_COUNT_MASK) 1190 /*! @} */ 1191 1192 /*! @name EAR17 - ERM Memory 17 Error Address Register */ 1193 /*! @{ */ 1194 1195 #define ERM_EAR17_EAR_MASK (0xFFFFFFFFU) 1196 #define ERM_EAR17_EAR_SHIFT (0U) 1197 #define ERM_EAR17_EAR_WIDTH (32U) 1198 #define ERM_EAR17_EAR(x) (((uint32_t)(((uint32_t)(x)) << ERM_EAR17_EAR_SHIFT)) & ERM_EAR17_EAR_MASK) 1199 /*! @} */ 1200 1201 /*! @name CORR_ERR_CNT17 - ERM Memory 17 Correctable Error Count Register */ 1202 /*! @{ */ 1203 1204 #define ERM_CORR_ERR_CNT17_COUNT_MASK (0xFFU) 1205 #define ERM_CORR_ERR_CNT17_COUNT_SHIFT (0U) 1206 #define ERM_CORR_ERR_CNT17_COUNT_WIDTH (8U) 1207 #define ERM_CORR_ERR_CNT17_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ERM_CORR_ERR_CNT17_COUNT_SHIFT)) & ERM_CORR_ERR_CNT17_COUNT_MASK) 1208 /*! @} */ 1209 1210 /*! @name EAR18 - ERM Memory 18 Error Address Register */ 1211 /*! @{ */ 1212 1213 #define ERM_EAR18_EAR_MASK (0xFFFFFFFFU) 1214 #define ERM_EAR18_EAR_SHIFT (0U) 1215 #define ERM_EAR18_EAR_WIDTH (32U) 1216 #define ERM_EAR18_EAR(x) (((uint32_t)(((uint32_t)(x)) << ERM_EAR18_EAR_SHIFT)) & ERM_EAR18_EAR_MASK) 1217 /*! @} */ 1218 1219 /*! @name SYN18 - ERM Memory 18 Syndrome Register */ 1220 /*! @{ */ 1221 1222 #define ERM_SYN18_SYNDROME_MASK (0xFF000000U) 1223 #define ERM_SYN18_SYNDROME_SHIFT (24U) 1224 #define ERM_SYN18_SYNDROME_WIDTH (8U) 1225 #define ERM_SYN18_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << ERM_SYN18_SYNDROME_SHIFT)) & ERM_SYN18_SYNDROME_MASK) 1226 /*! @} */ 1227 1228 /*! @name CORR_ERR_CNT18 - ERM Memory 18 Correctable Error Count Register */ 1229 /*! @{ */ 1230 1231 #define ERM_CORR_ERR_CNT18_COUNT_MASK (0xFFU) 1232 #define ERM_CORR_ERR_CNT18_COUNT_SHIFT (0U) 1233 #define ERM_CORR_ERR_CNT18_COUNT_WIDTH (8U) 1234 #define ERM_CORR_ERR_CNT18_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ERM_CORR_ERR_CNT18_COUNT_SHIFT)) & ERM_CORR_ERR_CNT18_COUNT_MASK) 1235 /*! @} */ 1236 1237 /*! @name EAR19 - ERM Memory 19 Error Address Register */ 1238 /*! @{ */ 1239 1240 #define ERM_EAR19_EAR_MASK (0xFFFFFFFFU) 1241 #define ERM_EAR19_EAR_SHIFT (0U) 1242 #define ERM_EAR19_EAR_WIDTH (32U) 1243 #define ERM_EAR19_EAR(x) (((uint32_t)(((uint32_t)(x)) << ERM_EAR19_EAR_SHIFT)) & ERM_EAR19_EAR_MASK) 1244 /*! @} */ 1245 1246 /*! @name CORR_ERR_CNT19 - ERM Memory 19 Correctable Error Count Register */ 1247 /*! @{ */ 1248 1249 #define ERM_CORR_ERR_CNT19_COUNT_MASK (0xFFU) 1250 #define ERM_CORR_ERR_CNT19_COUNT_SHIFT (0U) 1251 #define ERM_CORR_ERR_CNT19_COUNT_WIDTH (8U) 1252 #define ERM_CORR_ERR_CNT19_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ERM_CORR_ERR_CNT19_COUNT_SHIFT)) & ERM_CORR_ERR_CNT19_COUNT_MASK) 1253 /*! @} */ 1254 1255 /*! @name EAR20 - ERM Memory 20 Error Address Register */ 1256 /*! @{ */ 1257 1258 #define ERM_EAR20_EAR_MASK (0xFFFFFFFFU) 1259 #define ERM_EAR20_EAR_SHIFT (0U) 1260 #define ERM_EAR20_EAR_WIDTH (32U) 1261 #define ERM_EAR20_EAR(x) (((uint32_t)(((uint32_t)(x)) << ERM_EAR20_EAR_SHIFT)) & ERM_EAR20_EAR_MASK) 1262 /*! @} */ 1263 1264 /*! @name SYN20 - ERM Memory 20 Syndrome Register */ 1265 /*! @{ */ 1266 1267 #define ERM_SYN20_SYNDROME_EXT_MASK (0x3U) 1268 #define ERM_SYN20_SYNDROME_EXT_SHIFT (0U) 1269 #define ERM_SYN20_SYNDROME_EXT_WIDTH (2U) 1270 #define ERM_SYN20_SYNDROME_EXT(x) (((uint32_t)(((uint32_t)(x)) << ERM_SYN20_SYNDROME_EXT_SHIFT)) & ERM_SYN20_SYNDROME_EXT_MASK) 1271 1272 #define ERM_SYN20_SYNDROME_MASK (0xFF000000U) 1273 #define ERM_SYN20_SYNDROME_SHIFT (24U) 1274 #define ERM_SYN20_SYNDROME_WIDTH (8U) 1275 #define ERM_SYN20_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << ERM_SYN20_SYNDROME_SHIFT)) & ERM_SYN20_SYNDROME_MASK) 1276 /*! @} */ 1277 1278 /*! @name CORR_ERR_CNT20 - ERM Memory 20 Correctable Error Count Register */ 1279 /*! @{ */ 1280 1281 #define ERM_CORR_ERR_CNT20_COUNT_MASK (0xFFU) 1282 #define ERM_CORR_ERR_CNT20_COUNT_SHIFT (0U) 1283 #define ERM_CORR_ERR_CNT20_COUNT_WIDTH (8U) 1284 #define ERM_CORR_ERR_CNT20_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ERM_CORR_ERR_CNT20_COUNT_SHIFT)) & ERM_CORR_ERR_CNT20_COUNT_MASK) 1285 /*! @} */ 1286 1287 /*! @name EAR21 - ERM Memory 21 Error Address Register */ 1288 /*! @{ */ 1289 1290 #define ERM_EAR21_EAR_MASK (0xFFFFFFFFU) 1291 #define ERM_EAR21_EAR_SHIFT (0U) 1292 #define ERM_EAR21_EAR_WIDTH (32U) 1293 #define ERM_EAR21_EAR(x) (((uint32_t)(((uint32_t)(x)) << ERM_EAR21_EAR_SHIFT)) & ERM_EAR21_EAR_MASK) 1294 /*! @} */ 1295 1296 /*! @name CORR_ERR_CNT21 - ERM Memory 21 Correctable Error Count Register */ 1297 /*! @{ */ 1298 1299 #define ERM_CORR_ERR_CNT21_COUNT_MASK (0xFFU) 1300 #define ERM_CORR_ERR_CNT21_COUNT_SHIFT (0U) 1301 #define ERM_CORR_ERR_CNT21_COUNT_WIDTH (8U) 1302 #define ERM_CORR_ERR_CNT21_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ERM_CORR_ERR_CNT21_COUNT_SHIFT)) & ERM_CORR_ERR_CNT21_COUNT_MASK) 1303 /*! @} */ 1304 1305 /*! @name EAR22 - ERM Memory 22 Error Address Register */ 1306 /*! @{ */ 1307 1308 #define ERM_EAR22_EAR_MASK (0xFFFFFFFFU) 1309 #define ERM_EAR22_EAR_SHIFT (0U) 1310 #define ERM_EAR22_EAR_WIDTH (32U) 1311 #define ERM_EAR22_EAR(x) (((uint32_t)(((uint32_t)(x)) << ERM_EAR22_EAR_SHIFT)) & ERM_EAR22_EAR_MASK) 1312 /*! @} */ 1313 1314 /*! @name CORR_ERR_CNT22 - ERM Memory 22 Correctable Error Count Register */ 1315 /*! @{ */ 1316 1317 #define ERM_CORR_ERR_CNT22_COUNT_MASK (0xFFU) 1318 #define ERM_CORR_ERR_CNT22_COUNT_SHIFT (0U) 1319 #define ERM_CORR_ERR_CNT22_COUNT_WIDTH (8U) 1320 #define ERM_CORR_ERR_CNT22_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ERM_CORR_ERR_CNT22_COUNT_SHIFT)) & ERM_CORR_ERR_CNT22_COUNT_MASK) 1321 /*! @} */ 1322 1323 /*! @name EAR23 - ERM Memory 23 Error Address Register */ 1324 /*! @{ */ 1325 1326 #define ERM_EAR23_EAR_MASK (0xFFFFFFFFU) 1327 #define ERM_EAR23_EAR_SHIFT (0U) 1328 #define ERM_EAR23_EAR_WIDTH (32U) 1329 #define ERM_EAR23_EAR(x) (((uint32_t)(((uint32_t)(x)) << ERM_EAR23_EAR_SHIFT)) & ERM_EAR23_EAR_MASK) 1330 /*! @} */ 1331 1332 /*! @name CORR_ERR_CNT23 - ERM Memory 23 Correctable Error Count Register */ 1333 /*! @{ */ 1334 1335 #define ERM_CORR_ERR_CNT23_COUNT_MASK (0xFFU) 1336 #define ERM_CORR_ERR_CNT23_COUNT_SHIFT (0U) 1337 #define ERM_CORR_ERR_CNT23_COUNT_WIDTH (8U) 1338 #define ERM_CORR_ERR_CNT23_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ERM_CORR_ERR_CNT23_COUNT_SHIFT)) & ERM_CORR_ERR_CNT23_COUNT_MASK) 1339 /*! @} */ 1340 1341 /*! 1342 * @} 1343 */ /* end of group ERM_Register_Masks */ 1344 1345 /*! 1346 * @} 1347 */ /* end of group ERM_Peripheral_Access_Layer */ 1348 1349 #endif /* #if !defined(S32Z2_ERM_H_) */ 1350
