1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2023 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32Z2_EDMA3_MP.h 10 * @version 2.1 11 * @date 2023-07-20 12 * @brief Peripheral Access Layer for S32Z2_EDMA3_MP 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32Z2_EDMA3_MP_H_) /* Check if memory map has not been already included */ 58 #define S32Z2_EDMA3_MP_H_ 59 60 #include "S32Z2_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- EDMA3_MP Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup EDMA3_MP_Peripheral_Access_Layer EDMA3_MP Peripheral Access Layer 68 * @{ 69 */ 70 71 /** EDMA3_MP - Size of Registers Arrays */ 72 #define EDMA3_MP_MP_GRPRI_COUNT 32u 73 74 /** EDMA3_MP - Register Layout Typedef */ 75 typedef struct { 76 __IO uint32_t CSR; /**< Management Page Control, offset: 0x0 */ 77 __I uint32_t ES; /**< Management Page Error Status, offset: 0x4 */ 78 __I uint32_t INT; /**< Management Page Interrupt Request Status, offset: 0x8 */ 79 __I uint32_t HRS; /**< Management Page Hardware Request Status, offset: 0xC */ 80 uint8_t RESERVED_0[240]; 81 __IO uint32_t CH_GRPRI[EDMA3_MP_MP_GRPRI_COUNT]; /**< Channel Arbitration Group, array offset: 0x100, array step: 0x4, irregular array, not all indices are valid */ 82 } EDMA3_MP_Type, *EDMA3_MP_MemMapPtr; 83 84 /** Number of instances of the EDMA3_MP module. */ 85 #define EDMA3_MP_INSTANCE_COUNT (5u) 86 87 /* EDMA3_MP - Peripheral instance base addresses */ 88 /** Peripheral EDMA_0_MP base address */ 89 #define IP_EDMA_0_MP_BASE (0x405D0000u) 90 /** Peripheral EDMA_0_MP base pointer */ 91 #define IP_EDMA_0_MP ((EDMA3_MP_Type *)IP_EDMA_0_MP_BASE) 92 /** Peripheral EDMA_1_MP base address */ 93 #define IP_EDMA_1_MP_BASE (0x40DD0000u) 94 /** Peripheral EDMA_1_MP base pointer */ 95 #define IP_EDMA_1_MP ((EDMA3_MP_Type *)IP_EDMA_1_MP_BASE) 96 /** Peripheral EDMA_4_MP base address */ 97 #define IP_EDMA_4_MP_BASE (0x425D0000u) 98 /** Peripheral EDMA_4_MP base pointer */ 99 #define IP_EDMA_4_MP ((EDMA3_MP_Type *)IP_EDMA_4_MP_BASE) 100 /** Peripheral EDMA_5_MP base address */ 101 #define IP_EDMA_5_MP_BASE (0x42DD0000u) 102 /** Peripheral EDMA_5_MP base pointer */ 103 #define IP_EDMA_5_MP ((EDMA3_MP_Type *)IP_EDMA_5_MP_BASE) 104 /** Peripheral CE_EDMA_MP base address */ 105 #define IP_CE_EDMA_MP_BASE (0x44E00000u) 106 /** Peripheral CE_EDMA_MP base pointer */ 107 #define IP_CE_EDMA_MP ((EDMA3_MP_Type *)IP_CE_EDMA_MP_BASE) 108 /** Array initializer of EDMA3_MP peripheral base addresses */ 109 #define IP_EDMA3_MP_BASE_ADDRS { IP_EDMA_0_MP_BASE, IP_EDMA_1_MP_BASE, IP_EDMA_4_MP_BASE, IP_EDMA_5_MP_BASE, IP_CE_EDMA_MP_BASE } 110 /** Array initializer of EDMA3_MP peripheral base pointers */ 111 #define IP_EDMA3_MP_BASE_PTRS { IP_EDMA_0_MP, IP_EDMA_1_MP, IP_EDMA_4_MP, IP_EDMA_5_MP, IP_CE_EDMA_MP } 112 113 /* ---------------------------------------------------------------------------- 114 -- EDMA3_MP Register Masks 115 ---------------------------------------------------------------------------- */ 116 117 /*! 118 * @addtogroup EDMA3_MP_Register_Masks EDMA3_MP Register Masks 119 * @{ 120 */ 121 122 /*! @name CSR - Management Page Control */ 123 /*! @{ */ 124 125 #define EDMA3_MP_CSR_EDBG_MASK (0x2U) 126 #define EDMA3_MP_CSR_EDBG_SHIFT (1U) 127 #define EDMA3_MP_CSR_EDBG_WIDTH (1U) 128 #define EDMA3_MP_CSR_EDBG(x) (((uint32_t)(((uint32_t)(x)) << EDMA3_MP_CSR_EDBG_SHIFT)) & EDMA3_MP_CSR_EDBG_MASK) 129 130 #define EDMA3_MP_CSR_ERCA_MASK (0x4U) 131 #define EDMA3_MP_CSR_ERCA_SHIFT (2U) 132 #define EDMA3_MP_CSR_ERCA_WIDTH (1U) 133 #define EDMA3_MP_CSR_ERCA(x) (((uint32_t)(((uint32_t)(x)) << EDMA3_MP_CSR_ERCA_SHIFT)) & EDMA3_MP_CSR_ERCA_MASK) 134 135 #define EDMA3_MP_CSR_HAE_MASK (0x10U) 136 #define EDMA3_MP_CSR_HAE_SHIFT (4U) 137 #define EDMA3_MP_CSR_HAE_WIDTH (1U) 138 #define EDMA3_MP_CSR_HAE(x) (((uint32_t)(((uint32_t)(x)) << EDMA3_MP_CSR_HAE_SHIFT)) & EDMA3_MP_CSR_HAE_MASK) 139 140 #define EDMA3_MP_CSR_HALT_MASK (0x20U) 141 #define EDMA3_MP_CSR_HALT_SHIFT (5U) 142 #define EDMA3_MP_CSR_HALT_WIDTH (1U) 143 #define EDMA3_MP_CSR_HALT(x) (((uint32_t)(((uint32_t)(x)) << EDMA3_MP_CSR_HALT_SHIFT)) & EDMA3_MP_CSR_HALT_MASK) 144 145 #define EDMA3_MP_CSR_GCLC_MASK (0x40U) 146 #define EDMA3_MP_CSR_GCLC_SHIFT (6U) 147 #define EDMA3_MP_CSR_GCLC_WIDTH (1U) 148 #define EDMA3_MP_CSR_GCLC(x) (((uint32_t)(((uint32_t)(x)) << EDMA3_MP_CSR_GCLC_SHIFT)) & EDMA3_MP_CSR_GCLC_MASK) 149 150 #define EDMA3_MP_CSR_GMRC_MASK (0x80U) 151 #define EDMA3_MP_CSR_GMRC_SHIFT (7U) 152 #define EDMA3_MP_CSR_GMRC_WIDTH (1U) 153 #define EDMA3_MP_CSR_GMRC(x) (((uint32_t)(((uint32_t)(x)) << EDMA3_MP_CSR_GMRC_SHIFT)) & EDMA3_MP_CSR_GMRC_MASK) 154 155 #define EDMA3_MP_CSR_ECX_MASK (0x100U) 156 #define EDMA3_MP_CSR_ECX_SHIFT (8U) 157 #define EDMA3_MP_CSR_ECX_WIDTH (1U) 158 #define EDMA3_MP_CSR_ECX(x) (((uint32_t)(((uint32_t)(x)) << EDMA3_MP_CSR_ECX_SHIFT)) & EDMA3_MP_CSR_ECX_MASK) 159 160 #define EDMA3_MP_CSR_CX_MASK (0x200U) 161 #define EDMA3_MP_CSR_CX_SHIFT (9U) 162 #define EDMA3_MP_CSR_CX_WIDTH (1U) 163 #define EDMA3_MP_CSR_CX(x) (((uint32_t)(((uint32_t)(x)) << EDMA3_MP_CSR_CX_SHIFT)) & EDMA3_MP_CSR_CX_MASK) 164 165 #define EDMA3_MP_CSR_ACTIVE_ID_MASK (0x1F000000U) /* Merged from fields with different position or width, of widths (4, 5), largest definition used */ 166 #define EDMA3_MP_CSR_ACTIVE_ID_SHIFT (24U) 167 #define EDMA3_MP_CSR_ACTIVE_ID_WIDTH (5U) 168 #define EDMA3_MP_CSR_ACTIVE_ID(x) (((uint32_t)(((uint32_t)(x)) << EDMA3_MP_CSR_ACTIVE_ID_SHIFT)) & EDMA3_MP_CSR_ACTIVE_ID_MASK) /* Merged from fields with different position or width, of widths (4, 5), largest definition used */ 169 170 #define EDMA3_MP_CSR_ACTIVE_MASK (0x80000000U) 171 #define EDMA3_MP_CSR_ACTIVE_SHIFT (31U) 172 #define EDMA3_MP_CSR_ACTIVE_WIDTH (1U) 173 #define EDMA3_MP_CSR_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << EDMA3_MP_CSR_ACTIVE_SHIFT)) & EDMA3_MP_CSR_ACTIVE_MASK) 174 /*! @} */ 175 176 /*! @name ES - Management Page Error Status */ 177 /*! @{ */ 178 179 #define EDMA3_MP_ES_DBE_MASK (0x1U) 180 #define EDMA3_MP_ES_DBE_SHIFT (0U) 181 #define EDMA3_MP_ES_DBE_WIDTH (1U) 182 #define EDMA3_MP_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << EDMA3_MP_ES_DBE_SHIFT)) & EDMA3_MP_ES_DBE_MASK) 183 184 #define EDMA3_MP_ES_SBE_MASK (0x2U) 185 #define EDMA3_MP_ES_SBE_SHIFT (1U) 186 #define EDMA3_MP_ES_SBE_WIDTH (1U) 187 #define EDMA3_MP_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << EDMA3_MP_ES_SBE_SHIFT)) & EDMA3_MP_ES_SBE_MASK) 188 189 #define EDMA3_MP_ES_SGE_MASK (0x4U) 190 #define EDMA3_MP_ES_SGE_SHIFT (2U) 191 #define EDMA3_MP_ES_SGE_WIDTH (1U) 192 #define EDMA3_MP_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << EDMA3_MP_ES_SGE_SHIFT)) & EDMA3_MP_ES_SGE_MASK) 193 194 #define EDMA3_MP_ES_NCE_MASK (0x8U) 195 #define EDMA3_MP_ES_NCE_SHIFT (3U) 196 #define EDMA3_MP_ES_NCE_WIDTH (1U) 197 #define EDMA3_MP_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << EDMA3_MP_ES_NCE_SHIFT)) & EDMA3_MP_ES_NCE_MASK) 198 199 #define EDMA3_MP_ES_DOE_MASK (0x10U) 200 #define EDMA3_MP_ES_DOE_SHIFT (4U) 201 #define EDMA3_MP_ES_DOE_WIDTH (1U) 202 #define EDMA3_MP_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << EDMA3_MP_ES_DOE_SHIFT)) & EDMA3_MP_ES_DOE_MASK) 203 204 #define EDMA3_MP_ES_DAE_MASK (0x20U) 205 #define EDMA3_MP_ES_DAE_SHIFT (5U) 206 #define EDMA3_MP_ES_DAE_WIDTH (1U) 207 #define EDMA3_MP_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << EDMA3_MP_ES_DAE_SHIFT)) & EDMA3_MP_ES_DAE_MASK) 208 209 #define EDMA3_MP_ES_SOE_MASK (0x40U) 210 #define EDMA3_MP_ES_SOE_SHIFT (6U) 211 #define EDMA3_MP_ES_SOE_WIDTH (1U) 212 #define EDMA3_MP_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << EDMA3_MP_ES_SOE_SHIFT)) & EDMA3_MP_ES_SOE_MASK) 213 214 #define EDMA3_MP_ES_SAE_MASK (0x80U) 215 #define EDMA3_MP_ES_SAE_SHIFT (7U) 216 #define EDMA3_MP_ES_SAE_WIDTH (1U) 217 #define EDMA3_MP_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << EDMA3_MP_ES_SAE_SHIFT)) & EDMA3_MP_ES_SAE_MASK) 218 219 #define EDMA3_MP_ES_ECX_MASK (0x100U) 220 #define EDMA3_MP_ES_ECX_SHIFT (8U) 221 #define EDMA3_MP_ES_ECX_WIDTH (1U) 222 #define EDMA3_MP_ES_ECX(x) (((uint32_t)(((uint32_t)(x)) << EDMA3_MP_ES_ECX_SHIFT)) & EDMA3_MP_ES_ECX_MASK) 223 224 #define EDMA3_MP_ES_UCE_MASK (0x200U) 225 #define EDMA3_MP_ES_UCE_SHIFT (9U) 226 #define EDMA3_MP_ES_UCE_WIDTH (1U) 227 #define EDMA3_MP_ES_UCE(x) (((uint32_t)(((uint32_t)(x)) << EDMA3_MP_ES_UCE_SHIFT)) & EDMA3_MP_ES_UCE_MASK) 228 229 #define EDMA3_MP_ES_ERRCHN_MASK (0x1F000000U) /* Merged from fields with different position or width, of widths (4, 5), largest definition used */ 230 #define EDMA3_MP_ES_ERRCHN_SHIFT (24U) 231 #define EDMA3_MP_ES_ERRCHN_WIDTH (5U) 232 #define EDMA3_MP_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x)) << EDMA3_MP_ES_ERRCHN_SHIFT)) & EDMA3_MP_ES_ERRCHN_MASK) /* Merged from fields with different position or width, of widths (4, 5), largest definition used */ 233 234 #define EDMA3_MP_ES_VLD_MASK (0x80000000U) 235 #define EDMA3_MP_ES_VLD_SHIFT (31U) 236 #define EDMA3_MP_ES_VLD_WIDTH (1U) 237 #define EDMA3_MP_ES_VLD(x) (((uint32_t)(((uint32_t)(x)) << EDMA3_MP_ES_VLD_SHIFT)) & EDMA3_MP_ES_VLD_MASK) 238 /*! @} */ 239 240 /*! @name INT - Management Page Interrupt Request Status */ 241 /*! @{ */ 242 243 #define EDMA3_MP_INT_INT_MASK (0xFFFFFFFFU) /* Merged from fields with different position or width, of widths (16, 32), largest definition used */ 244 #define EDMA3_MP_INT_INT_SHIFT (0U) 245 #define EDMA3_MP_INT_INT_WIDTH (32U) 246 #define EDMA3_MP_INT_INT(x) (((uint32_t)(((uint32_t)(x)) << EDMA3_MP_INT_INT_SHIFT)) & EDMA3_MP_INT_INT_MASK) /* Merged from fields with different position or width, of widths (16, 32), largest definition used */ 247 /*! @} */ 248 249 /*! @name HRS - Management Page Hardware Request Status */ 250 /*! @{ */ 251 252 #define EDMA3_MP_HRS_HRS_MASK (0xFFFFFFFFU) 253 #define EDMA3_MP_HRS_HRS_SHIFT (0U) 254 #define EDMA3_MP_HRS_HRS_WIDTH (32U) 255 #define EDMA3_MP_HRS_HRS(x) (((uint32_t)(((uint32_t)(x)) << EDMA3_MP_HRS_HRS_SHIFT)) & EDMA3_MP_HRS_HRS_MASK) 256 /*! @} */ 257 258 /*! @name CH_GRPRI - Channel Arbitration Group */ 259 /*! @{ */ 260 261 #define EDMA3_MP_CH_GRPRI_GRPRI_MASK (0x1FU) 262 #define EDMA3_MP_CH_GRPRI_GRPRI_SHIFT (0U) 263 #define EDMA3_MP_CH_GRPRI_GRPRI_WIDTH (5U) 264 #define EDMA3_MP_CH_GRPRI_GRPRI(x) (((uint32_t)(((uint32_t)(x)) << EDMA3_MP_CH_GRPRI_GRPRI_SHIFT)) & EDMA3_MP_CH_GRPRI_GRPRI_MASK) 265 /*! @} */ 266 267 /*! 268 * @} 269 */ /* end of group EDMA3_MP_Register_Masks */ 270 271 /*! 272 * @} 273 */ /* end of group EDMA3_MP_Peripheral_Access_Layer */ 274 275 #endif /* #if !defined(S32Z2_EDMA3_MP_H_) */ 276
